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authorStefan Roese <sr@denx.de>2007-11-20 05:19:16 -0500
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-12-23 14:31:16 -0500
commitf4151b9ba87901eb3a7bc49f418cc352d4e1927e (patch)
tree7481891935cea47d7794e583a6fdfe530575c17d /arch/ppc/mm
parent4922566f0394ac41c72fb960f22b4f84333026bc (diff)
[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG
Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/ppc/mm')
-rw-r--r--arch/ppc/mm/44x_mmu.c51
1 files changed, 16 insertions, 35 deletions
diff --git a/arch/ppc/mm/44x_mmu.c b/arch/ppc/mm/44x_mmu.c
index 6536a25cfcb8..fbb577a0d165 100644
--- a/arch/ppc/mm/44x_mmu.c
+++ b/arch/ppc/mm/44x_mmu.c
@@ -60,38 +60,28 @@ extern char etext[], _stext[];
60 * Just needed it declared someplace. 60 * Just needed it declared someplace.
61 */ 61 */
62unsigned int tlb_44x_index = 0; 62unsigned int tlb_44x_index = 0;
63unsigned int tlb_44x_hwater = 62; 63unsigned int tlb_44x_hwater = PPC4XX_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
64int icache_44x_need_flush; 64int icache_44x_need_flush;
65 65
66/* 66/*
67 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem 67 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
68 */ 68 */
69static void __init 69static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
70ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
71{ 70{
72 unsigned long attrib = 0; 71 __asm__ __volatile__(
73 72 "tlbwe %2,%3,%4\n"
74 __asm__ __volatile__("\ 73 "tlbwe %1,%3,%5\n"
75 clrrwi %2,%2,10\n\ 74 "tlbwe %0,%3,%6\n"
76 ori %2,%2,%4\n\
77 clrrwi %1,%1,10\n\
78 li %0,0\n\
79 ori %0,%0,%5\n\
80 tlbwe %2,%3,%6\n\
81 tlbwe %1,%3,%7\n\
82 tlbwe %0,%3,%8"
83 : 75 :
84 : "r" (attrib), "r" (phys), "r" (virt), "r" (slot), 76 : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
85 "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M), 77 "r" (phys),
86 "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), 78 "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
79 "r" (tlb_44x_hwater--), /* slot for this TLB entry */
87 "i" (PPC44x_TLB_PAGEID), 80 "i" (PPC44x_TLB_PAGEID),
88 "i" (PPC44x_TLB_XLAT), 81 "i" (PPC44x_TLB_XLAT),
89 "i" (PPC44x_TLB_ATTRIB)); 82 "i" (PPC44x_TLB_ATTRIB));
90} 83}
91 84
92/*
93 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
94 */
95void __init MMU_init_hw(void) 85void __init MMU_init_hw(void)
96{ 86{
97 flush_instruction_cache(); 87 flush_instruction_cache();
@@ -99,22 +89,13 @@ void __init MMU_init_hw(void)
99 89
100unsigned long __init mmu_mapin_ram(void) 90unsigned long __init mmu_mapin_ram(void)
101{ 91{
102 unsigned int pinned_tlbs = 1; 92 unsigned long addr;
103 int i;
104
105 /* Determine number of entries necessary to cover lowmem */
106 pinned_tlbs = (unsigned int)
107 (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
108
109 /* Write upper watermark to save location */
110 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
111 93
112 /* If necessary, set additional pinned TLBs */ 94 /* Pin in enough TLBs to cover any lowmem not covered by the
113 if (pinned_tlbs > 1) 95 * initial 256M mapping established in head_44x.S */
114 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { 96 for (addr = PPC_PIN_SIZE; addr < total_lowmem;
115 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE; 97 addr += PPC_PIN_SIZE)
116 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); 98 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
117 }
118 99
119 return total_lowmem; 100 return total_lowmem;
120} 101}