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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc/mm/4xx_mmu.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ppc/mm/4xx_mmu.c')
-rw-r--r--arch/ppc/mm/4xx_mmu.c142
1 files changed, 142 insertions, 0 deletions
diff --git a/arch/ppc/mm/4xx_mmu.c b/arch/ppc/mm/4xx_mmu.c
new file mode 100644
index 000000000000..a7f616140381
--- /dev/null
+++ b/arch/ppc/mm/4xx_mmu.c
@@ -0,0 +1,142 @@
1/*
2 * This file contains the routines for initializing the MMU
3 * on the 4xx series of chips.
4 * -- paulus
5 *
6 * Derived from arch/ppc/mm/init.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 *
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24#include <linux/config.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/kernel.h>
28#include <linux/errno.h>
29#include <linux/string.h>
30#include <linux/types.h>
31#include <linux/ptrace.h>
32#include <linux/mman.h>
33#include <linux/mm.h>
34#include <linux/swap.h>
35#include <linux/stddef.h>
36#include <linux/vmalloc.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/bootmem.h>
40#include <linux/highmem.h>
41
42#include <asm/pgalloc.h>
43#include <asm/prom.h>
44#include <asm/io.h>
45#include <asm/mmu_context.h>
46#include <asm/pgtable.h>
47#include <asm/mmu.h>
48#include <asm/uaccess.h>
49#include <asm/smp.h>
50#include <asm/bootx.h>
51#include <asm/machdep.h>
52#include <asm/setup.h>
53#include "mmu_decl.h"
54
55extern int __map_without_ltlbs;
56/*
57 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
58 */
59void __init MMU_init_hw(void)
60{
61 /*
62 * The Zone Protection Register (ZPR) defines how protection will
63 * be applied to every page which is a member of a given zone. At
64 * present, we utilize only two of the 4xx's zones.
65 * The zone index bits (of ZSEL) in the PTE are used for software
66 * indicators, except the LSB. For user access, zone 1 is used,
67 * for kernel access, zone 0 is used. We set all but zone 1
68 * to zero, allowing only kernel access as indicated in the PTE.
69 * For zone 1, we set a 01 binary (a value of 10 will not work)
70 * to allow user access as indicated in the PTE. This also allows
71 * kernel access as indicated in the PTE.
72 */
73
74 mtspr(SPRN_ZPR, 0x10000000);
75
76 flush_instruction_cache();
77
78 /*
79 * Set up the real-mode cache parameters for the exception vector
80 * handlers (which are run in real-mode).
81 */
82
83 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
84
85 /*
86 * Cache instruction and data space where the exception
87 * vectors and the kernel live in real-mode.
88 */
89
90 mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */
91 mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */
92}
93
94#define LARGE_PAGE_SIZE_16M (1<<24)
95#define LARGE_PAGE_SIZE_4M (1<<22)
96
97unsigned long __init mmu_mapin_ram(void)
98{
99 unsigned long v, s;
100 phys_addr_t p;
101
102 v = KERNELBASE;
103 p = PPC_MEMSTART;
104 s = 0;
105
106 if (__map_without_ltlbs) {
107 return s;
108 }
109
110 while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) {
111 pmd_t *pmdp;
112 unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
113
114 spin_lock(&init_mm.page_table_lock);
115 pmdp = pmd_offset(pgd_offset_k(v), v);
116 pmd_val(*pmdp++) = val;
117 pmd_val(*pmdp++) = val;
118 pmd_val(*pmdp++) = val;
119 pmd_val(*pmdp++) = val;
120 spin_unlock(&init_mm.page_table_lock);
121
122 v += LARGE_PAGE_SIZE_16M;
123 p += LARGE_PAGE_SIZE_16M;
124 s += LARGE_PAGE_SIZE_16M;
125 }
126
127 while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) {
128 pmd_t *pmdp;
129 unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
130
131 spin_lock(&init_mm.page_table_lock);
132 pmdp = pmd_offset(pgd_offset_k(v), v);
133 pmd_val(*pmdp) = val;
134 spin_unlock(&init_mm.page_table_lock);
135
136 v += LARGE_PAGE_SIZE_4M;
137 p += LARGE_PAGE_SIZE_4M;
138 s += LARGE_PAGE_SIZE_4M;
139 }
140
141 return s;
142}