[PATCH] ppc32: add 440ep support

Add PPC440EP core support.  PPC440EP is a PPC440-based SoC with a classic PPC
FPU and another set of peripherals.

Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

4 files changed, 34 insertions, 0 deletions

diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 50936cda0af9..8a3d74f2531e 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -852,6 +852,26 @@ struct cpu_spec	cpu_specs[] = {
 
 #endif /* CONFIG_40x */
 #ifdef CONFIG_44x
+        {
+                .pvr_mask               = 0xf0000fff,
+                .pvr_value              = 0x40000850,
+                .cpu_name               = "440EP Rev. A",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB,
+                .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+        },
+        {
+                .pvr_mask               = 0xf0000fff,
+                .pvr_value              = 0x400008d3,
+                .cpu_name               = "440EP Rev. B",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB,
+                .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+        },
         {       /* 440GP Rev. B */
                 .pvr_mask               = 0xf0000fff,
                 .pvr_value              = 0x40000440,
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index d4df68629cc6..cb83045e2edf 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -215,6 +215,7 @@ syscall_dotrace_cont:
         lwzx    r10,r10,r0      /* Fetch system call handler [ptr] */
         mtlr    r10
         addi    r9,r1,STACK_FRAME_OVERHEAD
+        PPC440EP_ERR42
         blrl                    /* Call handler */
         .globl  ret_from_syscall
 ret_from_syscall:
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 72ee8f33bde4..69ff3a9961e8 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -190,7 +190,9 @@ skpinv:	addi	r4,r4,1				/* Increment */
 
         /* xlat fields */
         lis     r4,UART0_PHYS_IO_BASE@h         /* RPN depends on SoC */
+#ifndef CONFIG_440EP
         ori     r4,r4,0x0001            /* ERPN is 1 for second 4GB page */
+#endif
 
         /* attrib fields */
         li      r5,0
@@ -228,6 +230,16 @@ skpinv:	addi	r4,r4,1				/* Increment */
         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
         mtspr   SPRN_IVPR,r4
 
+#ifdef CONFIG_440EP
+        /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
+        mfspr   r2,SPRN_CCR0
+        lis     r3,0xffef
+        ori     r3,r3,0xffff
+        and     r2,r2,r3
+        mtspr   SPRN_CCR0,r2
+        isync
+#endif
+
         /*
          * This is where the main kernel code starts.
          */
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index c2fb85b49a11..ce71b4a01585 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1145,6 +1145,7 @@ _GLOBAL(kernel_thread)
         stwu    r0,-16(r1)
         mtlr    r30             /* fn addr in lr */
         mr      r3,r31          /* load arg and call fn */
+        PPC440EP_ERR42
         blrl
         li      r0,__NR_exit    /* exit if function returns */
         li      r3,0