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authorJeff Garzik <jgarzik@pobox.com>2005-08-11 00:07:03 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-11 00:07:03 -0400
commitcd04b947bc674f8fc9cac38ec30497bae5d664ad (patch)
tree988b0b7ea08063e5499672346eb2f619f0629717 /arch/ppc/kernel
parentb3df9f813bc7b9db62ae0c90b8990b1cebf97345 (diff)
parentbc68552faad0e134eb22281343d5ae5a4873fa80 (diff)
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'arch/ppc/kernel')
-rw-r--r--arch/ppc/kernel/cputable.c20
-rw-r--r--arch/ppc/kernel/entry.S1
-rw-r--r--arch/ppc/kernel/head_44x.S24
-rw-r--r--arch/ppc/kernel/misc.S4
-rw-r--r--arch/ppc/kernel/pci.c15
-rw-r--r--arch/ppc/kernel/ppc_ksyms.c2
6 files changed, 59 insertions, 7 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 50936cda0af9..8a3d74f2531e 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -852,6 +852,26 @@ struct cpu_spec cpu_specs[] = {
852 852
853#endif /* CONFIG_40x */ 853#endif /* CONFIG_40x */
854#ifdef CONFIG_44x 854#ifdef CONFIG_44x
855 {
856 .pvr_mask = 0xf0000fff,
857 .pvr_value = 0x40000850,
858 .cpu_name = "440EP Rev. A",
859 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
860 CPU_FTR_USE_TB,
861 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
862 .icache_bsize = 32,
863 .dcache_bsize = 32,
864 },
865 {
866 .pvr_mask = 0xf0000fff,
867 .pvr_value = 0x400008d3,
868 .cpu_name = "440EP Rev. B",
869 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
870 CPU_FTR_USE_TB,
871 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
872 .icache_bsize = 32,
873 .dcache_bsize = 32,
874 },
855 { /* 440GP Rev. B */ 875 { /* 440GP Rev. B */
856 .pvr_mask = 0xf0000fff, 876 .pvr_mask = 0xf0000fff,
857 .pvr_value = 0x40000440, 877 .pvr_value = 0x40000440,
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index d4df68629cc6..cb83045e2edf 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -215,6 +215,7 @@ syscall_dotrace_cont:
215 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */ 215 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
216 mtlr r10 216 mtlr r10
217 addi r9,r1,STACK_FRAME_OVERHEAD 217 addi r9,r1,STACK_FRAME_OVERHEAD
218 PPC440EP_ERR42
218 blrl /* Call handler */ 219 blrl /* Call handler */
219 .globl ret_from_syscall 220 .globl ret_from_syscall
220ret_from_syscall: 221ret_from_syscall:
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 6c7ae6052464..69ff3a9961e8 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -179,24 +179,26 @@ skpinv: addi r4,r4,1 /* Increment */
1794: 1794:
180#ifdef CONFIG_SERIAL_TEXT_DEBUG 180#ifdef CONFIG_SERIAL_TEXT_DEBUG
181 /* 181 /*
182 * Add temporary UART mapping for early debug. This 182 * Add temporary UART mapping for early debug.
183 * mapping must be identical to that used by the early 183 * We can map UART registers wherever we want as long as they don't
184 * bootloader code since the same asm/serial.h parameters 184 * interfere with other system mappings (e.g. with pinned entries).
185 * are used for polled operation. 185 * For an example of how we handle this - see ocotea.h. --ebs
186 */ 186 */
187 /* pageid fields */ 187 /* pageid fields */
188 lis r3,UART0_IO_BASE@h 188 lis r3,UART0_IO_BASE@h
189 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M 189 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K
190 190
191 /* xlat fields */ 191 /* xlat fields */
192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ 192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193#ifndef CONFIG_440EP
193 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ 194 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
195#endif
194 196
195 /* attrib fields */ 197 /* attrib fields */
196 li r5,0 198 li r5,0
197 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) 199 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
198 200
199 li r0,1 /* TLB slot 1 */ 201 li r0,0 /* TLB slot 0 */
200 202
201 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ 203 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
202 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ 204 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
@@ -228,6 +230,16 @@ skpinv: addi r4,r4,1 /* Increment */
228 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 230 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
229 mtspr SPRN_IVPR,r4 231 mtspr SPRN_IVPR,r4
230 232
233#ifdef CONFIG_440EP
234 /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
235 mfspr r2,SPRN_CCR0
236 lis r3,0xffef
237 ori r3,r3,0xffff
238 and r2,r2,r3
239 mtspr SPRN_CCR0,r2
240 isync
241#endif
242
231 /* 243 /*
232 * This is where the main kernel code starts. 244 * This is where the main kernel code starts.
233 */ 245 */
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 191a8def3bdb..ce71b4a01585 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1145,6 +1145,7 @@ _GLOBAL(kernel_thread)
1145 stwu r0,-16(r1) 1145 stwu r0,-16(r1)
1146 mtlr r30 /* fn addr in lr */ 1146 mtlr r30 /* fn addr in lr */
1147 mr r3,r31 /* load arg and call fn */ 1147 mr r3,r31 /* load arg and call fn */
1148 PPC440EP_ERR42
1148 blrl 1149 blrl
1149 li r0,__NR_exit /* exit if function returns */ 1150 li r0,__NR_exit /* exit if function returns */
1150 li r3,0 1151 li r3,0
@@ -1451,3 +1452,6 @@ _GLOBAL(sys_call_table)
1451 .long sys_waitid 1452 .long sys_waitid
1452 .long sys_ioprio_set 1453 .long sys_ioprio_set
1453 .long sys_ioprio_get 1454 .long sys_ioprio_get
1455 .long sys_inotify_init /* 275 */
1456 .long sys_inotify_add_watch
1457 .long sys_inotify_rm_watch
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
index 70cfb6ffd877..7b3586a3bf30 100644
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -160,6 +160,21 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
160} 160}
161EXPORT_SYMBOL(pcibios_resource_to_bus); 161EXPORT_SYMBOL(pcibios_resource_to_bus);
162 162
163void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
164 struct pci_bus_region *region)
165{
166 unsigned long offset = 0;
167 struct pci_controller *hose = dev->sysdata;
168
169 if (hose && res->flags & IORESOURCE_IO)
170 offset = (unsigned long)hose->io_base_virt - isa_io_base;
171 else if (hose && res->flags & IORESOURCE_MEM)
172 offset = hose->pci_mem_offset;
173 res->start = region->start + offset;
174 res->end = region->end + offset;
175}
176EXPORT_SYMBOL(pcibios_bus_to_resource);
177
163/* 178/*
164 * We need to avoid collisions with `mirrored' VGA ports 179 * We need to avoid collisions with `mirrored' VGA ports
165 * and other strange ISA hardware, so we always want the 180 * and other strange ISA hardware, so we always want the
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index d59ad07de8e7..e7d40cc6c1b6 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -324,7 +324,7 @@ EXPORT_SYMBOL(__res);
324 324
325EXPORT_SYMBOL(next_mmu_context); 325EXPORT_SYMBOL(next_mmu_context);
326EXPORT_SYMBOL(set_context); 326EXPORT_SYMBOL(set_context);
327EXPORT_SYMBOL(handle_mm_fault); /* For MOL */ 327EXPORT_SYMBOL_GPL(__handle_mm_fault); /* For MOL */
328EXPORT_SYMBOL(disarm_decr); 328EXPORT_SYMBOL(disarm_decr);
329#ifdef CONFIG_PPC_STD_MMU 329#ifdef CONFIG_PPC_STD_MMU
330extern long mol_trampoline; 330extern long mol_trampoline;