[PATCH] ppc32: Add support for Freescale e200 (Book-E) core

The e200 core is a Book-E core (similar to e500) that has a unified L1 cache
and is not cache coherent on the bus.  The e200 core also adds a separate
exception level for debug exceptions.  Part of this patch helps to cleanup a
few cases that are true for all Freescale Book-E parts, not just e500.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 21 insertions, 3 deletions

diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
index 2ca8ecfeefd9..9e6ae5696650 100644
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -173,13 +173,13 @@ static inline int check_io_access(struct pt_regs *regs)
 /* On 4xx, the reason for the machine check or program exception
    is in the ESR. */
 #define get_reason(regs)        ((regs)->dsisr)
-#ifndef CONFIG_E500
+#ifndef CONFIG_FSL_BOOKE
 #define get_mc_reason(regs)     ((regs)->dsisr)
 #else
 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 #endif
 #define REASON_FP               ESR_FP
-#define REASON_ILLEGAL          ESR_PIL
+#define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 #define REASON_PRIVILEGED       ESR_PPR
 #define REASON_TRAP             ESR_PTR
 
@@ -302,7 +302,25 @@ void MachineCheckException(struct pt_regs *regs)
                 printk("Bus - Instruction Parity Error\n");
         if (reason & MCSR_BUS_RPERR)
                 printk("Bus - Read Parity Error\n");
-#else /* !CONFIG_4xx && !CONFIG_E500 */
+#elif defined (CONFIG_E200)
+        printk("Machine check in kernel mode.\n");
+        printk("Caused by (from MCSR=%lx): ", reason);
+
+        if (reason & MCSR_MCP)
+                printk("Machine Check Signal\n");
+        if (reason & MCSR_CP_PERR)
+                printk("Cache Push Parity Error\n");
+        if (reason & MCSR_CPERR)
+                printk("Cache Parity Error\n");
+        if (reason & MCSR_EXCP_ERR)
+                printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
+        if (reason & MCSR_BUS_IRERR)
+                printk("Bus - Read Bus Error on instruction fetch\n");
+        if (reason & MCSR_BUS_DRERR)
+                printk("Bus - Read Bus Error on data load\n");
+        if (reason & MCSR_BUS_WRERR)
+                printk("Bus - Write Bus Error on buffered store or cache line push\n");
+#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
         printk("Machine check in kernel mode.\n");
         printk("Caused by (from SRR1=%lx): ", reason);
         switch (reason & 0x601F0000) {