[PPC] Remove 85xx from arch/ppc

85xx exists in arch/powerpc as well as cuImage support to boot from
a u-boot that doesn't support device trees.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 2 insertions, 44 deletions

diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index e0c850d85c53..d5e0dfc9ffec 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -165,24 +165,7 @@ _GLOBAL(_tlbia)
         ble     1b
 
         isync
-#elif defined(CONFIG_FSL_BOOKE)
-        /* Invalidate all entries in TLB0 */
-        li      r3, 0x04
-        tlbivax 0,3
-        /* Invalidate all entries in TLB1 */
-        li      r3, 0x0c
-        tlbivax 0,3
-        /* Invalidate all entries in TLB2 */
-        li      r3, 0x14
-        tlbivax 0,3
-        /* Invalidate all entries in TLB3 */
-        li      r3, 0x1c
-        tlbivax 0,3
-        msync
-#ifdef CONFIG_SMP
-        tlbsync
-#endif /* CONFIG_SMP */
-#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
+#else /* !(CONFIG_40x || CONFIG_44x) */
 #if defined(CONFIG_SMP)
         rlwinm  r8,r1,0,0,18
         lwz     r8,TI_CPU(r8)
@@ -268,20 +251,7 @@ _GLOBAL(_tlbie)
         tlbwe   r3, r3, PPC44x_TLB_PAGEID
         isync
 10:
-#elif defined(CONFIG_FSL_BOOKE)
-        rlwinm  r4, r3, 0, 0, 19
-        ori     r5, r4, 0x08    /* TLBSEL = 1 */
-        ori     r6, r4, 0x10    /* TLBSEL = 2 */
-        ori     r7, r4, 0x18    /* TLBSEL = 3 */
-        tlbivax 0, r4
-        tlbivax 0, r5
-        tlbivax 0, r6
-        tlbivax 0, r7
-        msync
-#if defined(CONFIG_SMP)
-        tlbsync
-#endif /* CONFIG_SMP */
-#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
+#else /* !(CONFIG_40x || CONFIG_44x) */
 #if defined(CONFIG_SMP)
         rlwinm  r8,r1,0,0,18
         lwz     r8,TI_CPU(r8)
@@ -338,18 +308,6 @@ _GLOBAL(flush_instruction_cache)
         lis     r3, KERNELBASE@h
         iccci   0,r3
 #endif
-#elif CONFIG_FSL_BOOKE
-BEGIN_FTR_SECTION
-        mfspr   r3,SPRN_L1CSR0
-        ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
-        /* msync; isync recommended here */
-        mtspr   SPRN_L1CSR0,r3
-        isync
-        blr
-END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
-        mfspr   r3,SPRN_L1CSR1
-        ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
-        mtspr   SPRN_L1CSR1,r3
 #else
         mfspr   r3,SPRN_PVR
         rlwinm  r3,r3,16,16,31