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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc/kernel/head_fsl_booke.S
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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1/*
2 * arch/ppc/kernel/head_fsl_booke.S
3 *
4 * Kernel execution entry point code.
5 *
6 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
7 * Initial PowerPC version.
8 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Rewritten for PReP
10 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
11 * Low-level exception handers, MMU support, and rewrite.
12 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
13 * PowerPC 8xx modifications.
14 * Copyright (c) 1998-1999 TiVo, Inc.
15 * PowerPC 403GCX modifications.
16 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
17 * PowerPC 403GCX/405GP modifications.
18 * Copyright 2000 MontaVista Software Inc.
19 * PPC405 modifications
20 * PowerPC 403GCX/405GP modifications.
21 * Author: MontaVista Software, Inc.
22 * frank_rowand@mvista.com or source@mvista.com
23 * debbie_chu@mvista.com
24 * Copyright 2002-2004 MontaVista Software, Inc.
25 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
26 * Copyright 2004 Freescale Semiconductor, Inc
27 * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
28 *
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the
31 * Free Software Foundation; either version 2 of the License, or (at your
32 * option) any later version.
33 */
34
35#include <linux/config.h>
36#include <linux/threads.h>
37#include <asm/processor.h>
38#include <asm/page.h>
39#include <asm/mmu.h>
40#include <asm/pgtable.h>
41#include <asm/cputable.h>
42#include <asm/thread_info.h>
43#include <asm/ppc_asm.h>
44#include <asm/offsets.h>
45#include "head_booke.h"
46
47/* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 .text
59_GLOBAL(_stext)
60_GLOBAL(_start)
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
66/*
67 * Save parameters we are passed
68 */
69 mr r31,r3
70 mr r30,r4
71 mr r29,r5
72 mr r28,r6
73 mr r27,r7
74 li r24,0 /* CPU number */
75
76/* We try to not make any assumptions about how the boot loader
77 * setup or used the TLBs. We invalidate all mappings from the
78 * boot loader and load a single entry in TLB1[0] to map the
79 * first 16M of kernel memory. Any boot info passed from the
80 * bootloader needs to live in this first 16M.
81 *
82 * Requirement on bootloader:
83 * - The page we're executing in needs to reside in TLB1 and
84 * have IPROT=1. If not an invalidate broadcast could
85 * evict the entry we're currently executing in.
86 *
87 * r3 = Index of TLB1 were executing in
88 * r4 = Current MSR[IS]
89 * r5 = Index of TLB1 temp mapping
90 *
91 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
92 * if needed
93 */
94
95/* 1. Find the index of the entry we're executing in */
96 bl invstr /* Find our address */
97invstr: mflr r6 /* Make it accessible */
98 mfmsr r7
99 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
100 mfspr r7, SPRN_PID0
101 slwi r7,r7,16
102 or r7,r7,r4
103 mtspr SPRN_MAS6,r7
104 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
105 mfspr r7,SPRN_MAS1
106 andis. r7,r7,MAS1_VALID@h
107 bne match_TLB
108 mfspr r7,SPRN_PID1
109 slwi r7,r7,16
110 or r7,r7,r4
111 mtspr SPRN_MAS6,r7
112 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
113 mfspr r7,SPRN_MAS1
114 andis. r7,r7,MAS1_VALID@h
115 bne match_TLB
116 mfspr r7, SPRN_PID2
117 slwi r7,r7,16
118 or r7,r7,r4
119 mtspr SPRN_MAS6,r7
120 tlbsx 0,r6 /* Fall through, we had to match */
121match_TLB:
122 mfspr r7,SPRN_MAS0
123 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
124
125 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
126 oris r7,r7,MAS1_IPROT@h
127 mtspr SPRN_MAS1,r7
128 tlbwe
129
130/* 2. Invalidate all entries except the entry we're executing in */
131 mfspr r9,SPRN_TLB1CFG
132 andi. r9,r9,0xfff
133 li r6,0 /* Set Entry counter to 0 */
1341: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
135 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
136 mtspr SPRN_MAS0,r7
137 tlbre
138 mfspr r7,SPRN_MAS1
139 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
140 cmpw r3,r6
141 beq skpinv /* Dont update the current execution TLB */
142 mtspr SPRN_MAS1,r7
143 tlbwe
144 isync
145skpinv: addi r6,r6,1 /* Increment */
146 cmpw r6,r9 /* Are we done? */
147 bne 1b /* If not, repeat */
148
149 /* Invalidate TLB0 */
150 li r6,0x04
151 tlbivax 0,r6
152#ifdef CONFIG_SMP
153 tlbsync
154#endif
155 /* Invalidate TLB1 */
156 li r6,0x0c
157 tlbivax 0,r6
158#ifdef CONFIG_SMP
159 tlbsync
160#endif
161 msync
162
163/* 3. Setup a temp mapping and jump to it */
164 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
165 addi r5, r5, 0x1
166 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
167 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
168 mtspr SPRN_MAS0,r7
169 tlbre
170
171 /* Just modify the entry ID and EPN for the temp mapping */
172 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
173 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
174 mtspr SPRN_MAS0,r7
175 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
176 slwi r6,r6,12
177 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
178 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
179 mtspr SPRN_MAS1,r6
180 mfspr r6,SPRN_MAS2
181 li r7,0 /* temp EPN = 0 */
182 rlwimi r7,r6,0,20,31
183 mtspr SPRN_MAS2,r7
184 tlbwe
185
186 xori r6,r4,1
187 slwi r6,r6,5 /* setup new context with other address space */
188 bl 1f /* Find our address */
1891: mflr r9
190 rlwimi r7,r9,0,20,31
191 addi r7,r7,24
192 mtspr SPRN_SRR0,r7
193 mtspr SPRN_SRR1,r6
194 rfi
195
196/* 4. Clear out PIDs & Search info */
197 li r6,0
198 mtspr SPRN_PID0,r6
199 mtspr SPRN_PID1,r6
200 mtspr SPRN_PID2,r6
201 mtspr SPRN_MAS6,r6
202
203/* 5. Invalidate mapping we started in */
204 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
205 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
206 mtspr SPRN_MAS0,r7
207 tlbre
208 li r6,0
209 mtspr SPRN_MAS1,r6
210 tlbwe
211 /* Invalidate TLB1 */
212 li r9,0x0c
213 tlbivax 0,r9
214#ifdef CONFIG_SMP
215 tlbsync
216#endif
217 msync
218
219/* 6. Setup KERNELBASE mapping in TLB1[0] */
220 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
221 mtspr SPRN_MAS0,r6
222 lis r6,(MAS1_VALID|MAS1_IPROT)@h
223 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
224 mtspr SPRN_MAS1,r6
225 li r7,0
226 lis r6,KERNELBASE@h
227 ori r6,r6,KERNELBASE@l
228 rlwimi r6,r7,0,20,31
229 mtspr SPRN_MAS2,r6
230 li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
231 mtspr SPRN_MAS3,r7
232 tlbwe
233
234/* 7. Jump to KERNELBASE mapping */
235 li r7,0
236 bl 1f /* Find our address */
2371: mflr r9
238 rlwimi r6,r9,0,20,31
239 addi r6,r6,24
240 mtspr SPRN_SRR0,r6
241 mtspr SPRN_SRR1,r7
242 rfi /* start execution out of TLB1[0] entry */
243
244/* 8. Clear out the temp mapping */
245 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
246 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
247 mtspr SPRN_MAS0,r7
248 tlbre
249 mtspr SPRN_MAS1,r8
250 tlbwe
251 /* Invalidate TLB1 */
252 li r9,0x0c
253 tlbivax 0,r9
254#ifdef CONFIG_SMP
255 tlbsync
256#endif
257 msync
258
259 /* Establish the interrupt vector offsets */
260 SET_IVOR(0, CriticalInput);
261 SET_IVOR(1, MachineCheck);
262 SET_IVOR(2, DataStorage);
263 SET_IVOR(3, InstructionStorage);
264 SET_IVOR(4, ExternalInput);
265 SET_IVOR(5, Alignment);
266 SET_IVOR(6, Program);
267 SET_IVOR(7, FloatingPointUnavailable);
268 SET_IVOR(8, SystemCall);
269 SET_IVOR(9, AuxillaryProcessorUnavailable);
270 SET_IVOR(10, Decrementer);
271 SET_IVOR(11, FixedIntervalTimer);
272 SET_IVOR(12, WatchdogTimer);
273 SET_IVOR(13, DataTLBError);
274 SET_IVOR(14, InstructionTLBError);
275 SET_IVOR(15, Debug);
276 SET_IVOR(32, SPEUnavailable);
277 SET_IVOR(33, SPEFloatingPointData);
278 SET_IVOR(34, SPEFloatingPointRound);
279 SET_IVOR(35, PerformanceMonitor);
280
281 /* Establish the interrupt vector base */
282 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
283 mtspr SPRN_IVPR,r4
284
285 /* Setup the defaults for TLB entries */
286 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
287 mtspr SPRN_MAS4, r2
288
289#if 0
290 /* Enable DOZE */
291 mfspr r2,SPRN_HID0
292 oris r2,r2,HID0_DOZE@h
293 mtspr SPRN_HID0, r2
294#endif
295
296 /*
297 * This is where the main kernel code starts.
298 */
299
300 /* ptr to current */
301 lis r2,init_task@h
302 ori r2,r2,init_task@l
303
304 /* ptr to current thread */
305 addi r4,r2,THREAD /* init task's THREAD */
306 mtspr SPRN_SPRG3,r4
307
308 /* stack */
309 lis r1,init_thread_union@h
310 ori r1,r1,init_thread_union@l
311 li r0,0
312 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
313
314 bl early_init
315
316 mfspr r3,SPRN_TLB1CFG
317 andi. r3,r3,0xfff
318 lis r4,num_tlbcam_entries@ha
319 stw r3,num_tlbcam_entries@l(r4)
320/*
321 * Decide what sort of machine this is and initialize the MMU.
322 */
323 mr r3,r31
324 mr r4,r30
325 mr r5,r29
326 mr r6,r28
327 mr r7,r27
328 bl machine_init
329 bl MMU_init
330
331 /* Setup PTE pointers for the Abatron bdiGDB */
332 lis r6, swapper_pg_dir@h
333 ori r6, r6, swapper_pg_dir@l
334 lis r5, abatron_pteptrs@h
335 ori r5, r5, abatron_pteptrs@l
336 lis r4, KERNELBASE@h
337 ori r4, r4, KERNELBASE@l
338 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
339 stw r6, 0(r5)
340
341 /* Let's move on */
342 lis r4,start_kernel@h
343 ori r4,r4,start_kernel@l
344 lis r3,MSR_KERNEL@h
345 ori r3,r3,MSR_KERNEL@l
346 mtspr SPRN_SRR0,r4
347 mtspr SPRN_SRR1,r3
348 rfi /* change context and jump to start_kernel */
349
350/*
351 * Interrupt vector entry code
352 *
353 * The Book E MMUs are always on so we don't need to handle
354 * interrupts in real mode as with previous PPC processors. In
355 * this case we handle interrupts in the kernel virtual address
356 * space.
357 *
358 * Interrupt vectors are dynamically placed relative to the
359 * interrupt prefix as determined by the address of interrupt_base.
360 * The interrupt vectors offsets are programmed using the labels
361 * for each interrupt vector entry.
362 *
363 * Interrupt vectors must be aligned on a 16 byte boundary.
364 * We align on a 32 byte cache line boundary for good measure.
365 */
366
367interrupt_base:
368 /* Critical Input Interrupt */
369 CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
370
371 /* Machine Check Interrupt */
372 MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
373
374 /* Data Storage Interrupt */
375 START_EXCEPTION(DataStorage)
376 mtspr SPRN_SPRG0, r10 /* Save some working registers */
377 mtspr SPRN_SPRG1, r11
378 mtspr SPRN_SPRG4W, r12
379 mtspr SPRN_SPRG5W, r13
380 mfcr r11
381 mtspr SPRN_SPRG7W, r11
382
383 /*
384 * Check if it was a store fault, if not then bail
385 * because a user tried to access a kernel or
386 * read-protected page. Otherwise, get the
387 * offending address and handle it.
388 */
389 mfspr r10, SPRN_ESR
390 andis. r10, r10, ESR_ST@h
391 beq 2f
392
393 mfspr r10, SPRN_DEAR /* Get faulting address */
394
395 /* If we are faulting a kernel address, we have to use the
396 * kernel page tables.
397 */
398 lis r11, TASK_SIZE@h
399 ori r11, r11, TASK_SIZE@l
400 cmplw 0, r10, r11
401 bge 2f
402
403 /* Get the PGD for the current thread */
4043:
405 mfspr r11,SPRN_SPRG3
406 lwz r11,PGDIR(r11)
4074:
408 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
409 lwz r11, 0(r11) /* Get L1 entry */
410 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
411 beq 2f /* Bail if no table */
412
413 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
414 lwz r11, 0(r12) /* Get Linux PTE */
415
416 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
417 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
418 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
419 bne 2f /* Bail if not */
420
421 /* Update 'changed'. */
422 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
423 stw r11, 0(r12) /* Update Linux page table */
424
425 /* MAS2 not updated as the entry does exist in the tlb, this
426 fault taken to detect state transition (eg: COW -> DIRTY)
427 */
428 lis r12, MAS3_RPN@h
429 ori r12, r12, _PAGE_HWEXEC | MAS3_RPN@l
430 and r11, r11, r12
431 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
432 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
433
434 /* update search PID in MAS6, AS = 0 */
435 mfspr r12, SPRN_PID0
436 slwi r12, r12, 16
437 mtspr SPRN_MAS6, r12
438
439 /* find the TLB index that caused the fault. It has to be here. */
440 tlbsx 0, r10
441
442 mtspr SPRN_MAS3,r11
443 tlbwe
444
445 /* Done...restore registers and get out of here. */
446 mfspr r11, SPRN_SPRG7R
447 mtcr r11
448 mfspr r13, SPRN_SPRG5R
449 mfspr r12, SPRN_SPRG4R
450 mfspr r11, SPRN_SPRG1
451 mfspr r10, SPRN_SPRG0
452 rfi /* Force context change */
453
4542:
455 /*
456 * The bailout. Restore registers to pre-exception conditions
457 * and call the heavyweights to help us out.
458 */
459 mfspr r11, SPRN_SPRG7R
460 mtcr r11
461 mfspr r13, SPRN_SPRG5R
462 mfspr r12, SPRN_SPRG4R
463 mfspr r11, SPRN_SPRG1
464 mfspr r10, SPRN_SPRG0
465 b data_access
466
467 /* Instruction Storage Interrupt */
468 INSTRUCTION_STORAGE_EXCEPTION
469
470 /* External Input Interrupt */
471 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
472
473 /* Alignment Interrupt */
474 ALIGNMENT_EXCEPTION
475
476 /* Program Interrupt */
477 PROGRAM_EXCEPTION
478
479 /* Floating Point Unavailable Interrupt */
480 EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
481
482 /* System Call Interrupt */
483 START_EXCEPTION(SystemCall)
484 NORMAL_EXCEPTION_PROLOG
485 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
486
487 /* Auxillary Processor Unavailable Interrupt */
488 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
489
490 /* Decrementer Interrupt */
491 DECREMENTER_EXCEPTION
492
493 /* Fixed Internal Timer Interrupt */
494 /* TODO: Add FIT support */
495 EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
496
497 /* Watchdog Timer Interrupt */
498 /* TODO: Add watchdog support */
499 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
500
501 /* Data TLB Error Interrupt */
502 START_EXCEPTION(DataTLBError)
503 mtspr SPRN_SPRG0, r10 /* Save some working registers */
504 mtspr SPRN_SPRG1, r11
505 mtspr SPRN_SPRG4W, r12
506 mtspr SPRN_SPRG5W, r13
507 mfcr r11
508 mtspr SPRN_SPRG7W, r11
509 mfspr r10, SPRN_DEAR /* Get faulting address */
510
511 /* If we are faulting a kernel address, we have to use the
512 * kernel page tables.
513 */
514 lis r11, TASK_SIZE@h
515 ori r11, r11, TASK_SIZE@l
516 cmplw 5, r10, r11
517 blt 5, 3f
518 lis r11, swapper_pg_dir@h
519 ori r11, r11, swapper_pg_dir@l
520
521 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
522 rlwinm r12,r12,0,16,1
523 mtspr SPRN_MAS1,r12
524
525 b 4f
526
527 /* Get the PGD for the current thread */
5283:
529 mfspr r11,SPRN_SPRG3
530 lwz r11,PGDIR(r11)
531
5324:
533 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
534 lwz r11, 0(r11) /* Get L1 entry */
535 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
536 beq 2f /* Bail if no table */
537
538 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
539 lwz r11, 0(r12) /* Get Linux PTE */
540 andi. r13, r11, _PAGE_PRESENT
541 beq 2f
542
543 ori r11, r11, _PAGE_ACCESSED
544 stw r11, 0(r12)
545
546 /* Jump to common tlb load */
547 b finish_tlb_load
5482:
549 /* The bailout. Restore registers to pre-exception conditions
550 * and call the heavyweights to help us out.
551 */
552 mfspr r11, SPRN_SPRG7R
553 mtcr r11
554 mfspr r13, SPRN_SPRG5R
555 mfspr r12, SPRN_SPRG4R
556 mfspr r11, SPRN_SPRG1
557 mfspr r10, SPRN_SPRG0
558 b data_access
559
560 /* Instruction TLB Error Interrupt */
561 /*
562 * Nearly the same as above, except we get our
563 * information from different registers and bailout
564 * to a different point.
565 */
566 START_EXCEPTION(InstructionTLBError)
567 mtspr SPRN_SPRG0, r10 /* Save some working registers */
568 mtspr SPRN_SPRG1, r11
569 mtspr SPRN_SPRG4W, r12
570 mtspr SPRN_SPRG5W, r13
571 mfcr r11
572 mtspr SPRN_SPRG7W, r11
573 mfspr r10, SPRN_SRR0 /* Get faulting address */
574
575 /* If we are faulting a kernel address, we have to use the
576 * kernel page tables.
577 */
578 lis r11, TASK_SIZE@h
579 ori r11, r11, TASK_SIZE@l
580 cmplw 5, r10, r11
581 blt 5, 3f
582 lis r11, swapper_pg_dir@h
583 ori r11, r11, swapper_pg_dir@l
584
585 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
586 rlwinm r12,r12,0,16,1
587 mtspr SPRN_MAS1,r12
588
589 b 4f
590
591 /* Get the PGD for the current thread */
5923:
593 mfspr r11,SPRN_SPRG3
594 lwz r11,PGDIR(r11)
595
5964:
597 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
598 lwz r11, 0(r11) /* Get L1 entry */
599 rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
600 beq 2f /* Bail if no table */
601
602 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
603 lwz r11, 0(r12) /* Get Linux PTE */
604 andi. r13, r11, _PAGE_PRESENT
605 beq 2f
606
607 ori r11, r11, _PAGE_ACCESSED
608 stw r11, 0(r12)
609
610 /* Jump to common TLB load point */
611 b finish_tlb_load
612
6132:
614 /* The bailout. Restore registers to pre-exception conditions
615 * and call the heavyweights to help us out.
616 */
617 mfspr r11, SPRN_SPRG7R
618 mtcr r11
619 mfspr r13, SPRN_SPRG5R
620 mfspr r12, SPRN_SPRG4R
621 mfspr r11, SPRN_SPRG1
622 mfspr r10, SPRN_SPRG0
623 b InstructionStorage
624
625#ifdef CONFIG_SPE
626 /* SPE Unavailable */
627 START_EXCEPTION(SPEUnavailable)
628 NORMAL_EXCEPTION_PROLOG
629 bne load_up_spe
630 addi r3,r1,STACK_FRAME_OVERHEAD
631 EXC_XFER_EE_LITE(0x2010, KernelSPE)
632#else
633 EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
634#endif /* CONFIG_SPE */
635
636 /* SPE Floating Point Data */
637#ifdef CONFIG_SPE
638 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
639#else
640 EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
641#endif /* CONFIG_SPE */
642
643 /* SPE Floating Point Round */
644 EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
645
646 /* Performance Monitor */
647 EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD)
648
649
650 /* Debug Interrupt */
651 DEBUG_EXCEPTION
652
653/*
654 * Local functions
655 */
656 /*
657 * Data TLB exceptions will bail out to this point
658 * if they can't resolve the lightweight TLB fault.
659 */
660data_access:
661 NORMAL_EXCEPTION_PROLOG
662 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
663 stw r5,_ESR(r11)
664 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
665 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
666 bne 1f
667 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
6681:
669 addi r3,r1,STACK_FRAME_OVERHEAD
670 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
671
672/*
673
674 * Both the instruction and data TLB miss get to this
675 * point to load the TLB.
676 * r10 - EA of fault
677 * r11 - TLB (info from Linux PTE)
678 * r12, r13 - available to use
679 * CR5 - results of addr < TASK_SIZE
680 * MAS0, MAS1 - loaded with proper value when we get here
681 * MAS2, MAS3 - will need additional info from Linux PTE
682 * Upon exit, we reload everything and RFI.
683 */
684finish_tlb_load:
685 /*
686 * We set execute, because we don't have the granularity to
687 * properly set this at the page level (Linux problem).
688 * Many of these bits are software only. Bits we don't set
689 * here we (properly should) assume have the appropriate value.
690 */
691
692 mfspr r12, SPRN_MAS2
693 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
694 mtspr SPRN_MAS2, r12
695
696 bge 5, 1f
697
698 /* addr > TASK_SIZE */
699 li r10, (MAS3_UX | MAS3_UW | MAS3_UR)
700 andi. r13, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
701 andi. r12, r11, _PAGE_USER /* Test for _PAGE_USER */
702 iseleq r12, 0, r10
703 and r10, r12, r13
704 srwi r12, r10, 1
705 or r12, r12, r10 /* Copy user perms into supervisor */
706 b 2f
707
708 /* addr <= TASK_SIZE */
7091: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
710 ori r12, r12, (MAS3_SX | MAS3_SR)
711
7122: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
713 mtspr SPRN_MAS3, r11
714 tlbwe
715
716 /* Done...restore registers and get out of here. */
717 mfspr r11, SPRN_SPRG7R
718 mtcr r11
719 mfspr r13, SPRN_SPRG5R
720 mfspr r12, SPRN_SPRG4R
721 mfspr r11, SPRN_SPRG1
722 mfspr r10, SPRN_SPRG0
723 rfi /* Force context change */
724
725#ifdef CONFIG_SPE
726/* Note that the SPE support is closely modeled after the AltiVec
727 * support. Changes to one are likely to be applicable to the
728 * other! */
729load_up_spe:
730/*
731 * Disable SPE for the task which had SPE previously,
732 * and save its SPE registers in its thread_struct.
733 * Enables SPE for use in the kernel on return.
734 * On SMP we know the SPE units are free, since we give it up every
735 * switch. -- Kumar
736 */
737 mfmsr r5
738 oris r5,r5,MSR_SPE@h
739 mtmsr r5 /* enable use of SPE now */
740 isync
741/*
742 * For SMP, we don't do lazy SPE switching because it just gets too
743 * horrendously complex, especially when a task switches from one CPU
744 * to another. Instead we call giveup_spe in switch_to.
745 */
746#ifndef CONFIG_SMP
747 lis r3,last_task_used_spe@ha
748 lwz r4,last_task_used_spe@l(r3)
749 cmpi 0,r4,0
750 beq 1f
751 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
752 SAVE_32EVR(0,r10,r4)
753 evxor evr10, evr10, evr10 /* clear out evr10 */
754 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
755 li r5,THREAD_ACC
756 evstddx evr10, r4, r5 /* save off accumulator */
757 lwz r5,PT_REGS(r4)
758 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
759 lis r10,MSR_SPE@h
760 andc r4,r4,r10 /* disable SPE for previous task */
761 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7621:
763#endif /* CONFIG_SMP */
764 /* enable use of SPE after return */
765 oris r9,r9,MSR_SPE@h
766 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
767 li r4,1
768 li r10,THREAD_ACC
769 stw r4,THREAD_USED_SPE(r5)
770 evlddx evr4,r10,r5
771 evmra evr4,evr4
772 REST_32EVR(0,r10,r5)
773#ifndef CONFIG_SMP
774 subi r4,r5,THREAD
775 stw r4,last_task_used_spe@l(r3)
776#endif /* CONFIG_SMP */
777 /* restore registers and return */
7782: REST_4GPRS(3, r11)
779 lwz r10,_CCR(r11)
780 REST_GPR(1, r11)
781 mtcr r10
782 lwz r10,_LINK(r11)
783 mtlr r10
784 REST_GPR(10, r11)
785 mtspr SPRN_SRR1,r9
786 mtspr SPRN_SRR0,r12
787 REST_GPR(9, r11)
788 REST_GPR(12, r11)
789 lwz r11,GPR11(r11)
790 SYNC
791 rfi
792
793/*
794 * SPE unavailable trap from kernel - print a message, but let
795 * the task use SPE in the kernel until it returns to user mode.
796 */
797KernelSPE:
798 lwz r3,_MSR(r1)
799 oris r3,r3,MSR_SPE@h
800 stw r3,_MSR(r1) /* enable use of SPE after return */
801 lis r3,87f@h
802 ori r3,r3,87f@l
803 mr r4,r2 /* current */
804 lwz r5,_NIP(r1)
805 bl printk
806 b ret_from_except
80787: .string "SPE used in kernel (task=%p, pc=%x) \n"
808 .align 4,0
809
810#endif /* CONFIG_SPE */
811
812/*
813 * Global functions
814 */
815
816/*
817 * extern void loadcam_entry(unsigned int index)
818 *
819 * Load TLBCAM[index] entry in to the L2 CAM MMU
820 */
821_GLOBAL(loadcam_entry)
822 lis r4,TLBCAM@ha
823 addi r4,r4,TLBCAM@l
824 mulli r5,r3,20
825 add r3,r5,r4
826 lwz r4,0(r3)
827 mtspr SPRN_MAS0,r4
828 lwz r4,4(r3)
829 mtspr SPRN_MAS1,r4
830 lwz r4,8(r3)
831 mtspr SPRN_MAS2,r4
832 lwz r4,12(r3)
833 mtspr SPRN_MAS3,r4
834 tlbwe
835 isync
836 blr
837
838/*
839 * extern void giveup_altivec(struct task_struct *prev)
840 *
841 * The e500 core does not have an AltiVec unit.
842 */
843_GLOBAL(giveup_altivec)
844 blr
845
846#ifdef CONFIG_SPE
847/*
848 * extern void giveup_spe(struct task_struct *prev)
849 *
850 */
851_GLOBAL(giveup_spe)
852 mfmsr r5
853 oris r5,r5,MSR_SPE@h
854 SYNC
855 mtmsr r5 /* enable use of SPE now */
856 isync
857 cmpi 0,r3,0
858 beqlr- /* if no previous owner, done */
859 addi r3,r3,THREAD /* want THREAD of task */
860 lwz r5,PT_REGS(r3)
861 cmpi 0,r5,0
862 SAVE_32EVR(0, r4, r3)
863 evxor evr6, evr6, evr6 /* clear out evr6 */
864 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
865 li r4,THREAD_ACC
866 evstddx evr6, r4, r3 /* save off accumulator */
867 mfspr r6,SPRN_SPEFSCR
868 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
869 beq 1f
870 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
871 lis r3,MSR_SPE@h
872 andc r4,r4,r3 /* disable SPE for previous task */
873 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
8741:
875#ifndef CONFIG_SMP
876 li r5,0
877 lis r4,last_task_used_spe@ha
878 stw r5,last_task_used_spe@l(r4)
879#endif /* CONFIG_SMP */
880 blr
881#endif /* CONFIG_SPE */
882
883/*
884 * extern void giveup_fpu(struct task_struct *prev)
885 *
886 * The e500 core does not have an FPU.
887 */
888_GLOBAL(giveup_fpu)
889 blr
890
891/*
892 * extern void abort(void)
893 *
894 * At present, this routine just applies a system reset.
895 */
896_GLOBAL(abort)
897 li r13,0
898 mtspr SPRN_DBCR0,r13 /* disable all debug events */
899 mfmsr r13
900 ori r13,r13,MSR_DE@l /* Enable Debug Events */
901 mtmsr r13
902 mfspr r13,SPRN_DBCR0
903 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
904 mtspr SPRN_DBCR0,r13
905
906_GLOBAL(set_context)
907
908#ifdef CONFIG_BDI_SWITCH
909 /* Context switch the PTE pointer for the Abatron BDI2000.
910 * The PGDIR is the second parameter.
911 */
912 lis r5, abatron_pteptrs@h
913 ori r5, r5, abatron_pteptrs@l
914 stw r4, 0x4(r5)
915#endif
916 mtspr SPRN_PID,r3
917 isync /* Force context change */
918 blr
919
920/*
921 * We put a few things here that have to be page-aligned. This stuff
922 * goes at the beginning of the data segment, which is page-aligned.
923 */
924 .data
925_GLOBAL(sdata)
926_GLOBAL(empty_zero_page)
927 .space 4096
928_GLOBAL(swapper_pg_dir)
929 .space 4096
930
931/* Reserved 4k for the critical exception stack & 4k for the machine
932 * check stack per CPU for kernel mode exceptions */
933 .section .bss
934 .align 12
935exception_stack_bottom:
936 .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
937_GLOBAL(exception_stack_top)
938
939/*
940 * This space gets a copy of optional info passed to us by the bootstrap
941 * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
942 */
943_GLOBAL(cmd_line)
944 .space 512
945
946/*
947 * Room for two PTE pointers, usually the kernel and current user pointers
948 * to their respective root page table.
949 */
950abatron_pteptrs:
951 .space 8
952
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 01:07:47 -0500