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authorArthur Othieno <a.othieno@bluewin.ch>2005-09-03 18:55:51 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:05:59 -0400
commitac1ff0477cbe640a6a3652a0cd1aa78026f19246 (patch)
treef23577ee164c0ce7427fec85bc5c288c8251d13a /arch/ppc/kernel/cputable.c
parent66d2cc95d14b5d750a9c58209fddb62eb139eaab (diff)
[PATCH] ppc32: Re-order cputable for 750CXe DD2.4 entry
"745/755" (pvr_value:0x00083000) is a catch-all entry. Since arch/ppc/kernel/misc.S:identify_cpu() returns on first match, move this lower in the table so 750CXe DD2.4 (pvr_value:0x00083214) may be correctly enumerated. Signed-off-by: Arthur Othieno <a.othieno@bluewin.ch> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/kernel/cputable.c')
-rw-r--r--arch/ppc/kernel/cputable.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 61382341bb01..9ab2fad5e56d 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -198,20 +198,6 @@ struct cpu_spec cpu_specs[] = {
198 .num_pmcs = 4, 198 .num_pmcs = 4,
199 .cpu_setup = __setup_cpu_750 199 .cpu_setup = __setup_cpu_750
200 }, 200 },
201 { /* 745/755 */
202 .pvr_mask = 0xfffff000,
203 .pvr_value = 0x00083000,
204 .cpu_name = "745/755",
205 .cpu_features = CPU_FTR_COMMON |
206 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
207 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
208 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
209 .cpu_user_features = COMMON_PPC,
210 .icache_bsize = 32,
211 .dcache_bsize = 32,
212 .num_pmcs = 4,
213 .cpu_setup = __setup_cpu_750
214 },
215 { /* 750CX (80100 and 8010x?) */ 201 { /* 750CX (80100 and 8010x?) */
216 .pvr_mask = 0xfffffff0, 202 .pvr_mask = 0xfffffff0,
217 .pvr_value = 0x00080100, 203 .pvr_value = 0x00080100,
@@ -254,6 +240,20 @@ struct cpu_spec cpu_specs[] = {
254 .num_pmcs = 4, 240 .num_pmcs = 4,
255 .cpu_setup = __setup_cpu_750cx 241 .cpu_setup = __setup_cpu_750cx
256 }, 242 },
243 { /* 745/755 */
244 .pvr_mask = 0xfffff000,
245 .pvr_value = 0x00083000,
246 .cpu_name = "745/755",
247 .cpu_features = CPU_FTR_COMMON |
248 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
249 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
250 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
251 .cpu_user_features = COMMON_PPC,
252 .icache_bsize = 32,
253 .dcache_bsize = 32,
254 .num_pmcs = 4,
255 .cpu_setup = __setup_cpu_750
256 },
257 { /* 750FX rev 1.x */ 257 { /* 750FX rev 1.x */
258 .pvr_mask = 0xffffff00, 258 .pvr_mask = 0xffffff00,
259 .pvr_value = 0x70000100, 259 .pvr_value = 0x70000100,