diff options
author | Kumar Gala <galak@freescale.com> | 2005-09-03 18:55:55 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 03:06:00 -0400 |
commit | bbde630b553d349307fe719486bc06f8cf9c1a2d (patch) | |
tree | de7a71a39423c907301dd4eab6ccf31736227c24 /arch/ppc/kernel/cpu_setup_6xx.S | |
parent | e8834801bf9e2ee96c3ac29adf0ff6840afcd841 (diff) |
[PATCH] ppc32: Added cputable entry for 7448
Added cputable entry for 7448 as well adding it to checks for saving and
restoring of cpu state.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/kernel/cpu_setup_6xx.S')
-rw-r--r-- | arch/ppc/kernel/cpu_setup_6xx.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index 3fb1fb619d2c..bd037caa4055 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S | |||
@@ -327,6 +327,7 @@ _GLOBAL(__save_cpu_setup) | |||
327 | cmplwi cr4,r3,0x8002 /* 7457 */ | 327 | cmplwi cr4,r3,0x8002 /* 7457 */ |
328 | cmplwi cr5,r3,0x8003 /* 7447A */ | 328 | cmplwi cr5,r3,0x8003 /* 7447A */ |
329 | cmplwi cr6,r3,0x7000 /* 750FX */ | 329 | cmplwi cr6,r3,0x7000 /* 750FX */ |
330 | cmplwi cr7,r3,0x8004 /* 7448 */ | ||
330 | /* cr1 is 7400 || 7410 */ | 331 | /* cr1 is 7400 || 7410 */ |
331 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq | 332 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq |
332 | /* cr0 is 74xx */ | 333 | /* cr0 is 74xx */ |
@@ -334,6 +335,7 @@ _GLOBAL(__save_cpu_setup) | |||
334 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq | 335 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq |
335 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq | 336 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq |
336 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq | 337 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq |
338 | cror 4*cr0+eq,4*cr0+eq,4*cr7+eq | ||
337 | bne 1f | 339 | bne 1f |
338 | /* Backup 74xx specific regs */ | 340 | /* Backup 74xx specific regs */ |
339 | mfspr r4,SPRN_MSSCR0 | 341 | mfspr r4,SPRN_MSSCR0 |
@@ -396,6 +398,7 @@ _GLOBAL(__restore_cpu_setup) | |||
396 | cmplwi cr4,r3,0x8002 /* 7457 */ | 398 | cmplwi cr4,r3,0x8002 /* 7457 */ |
397 | cmplwi cr5,r3,0x8003 /* 7447A */ | 399 | cmplwi cr5,r3,0x8003 /* 7447A */ |
398 | cmplwi cr6,r3,0x7000 /* 750FX */ | 400 | cmplwi cr6,r3,0x7000 /* 750FX */ |
401 | cmplwi cr7,r3,0x8004 /* 7448 */ | ||
399 | /* cr1 is 7400 || 7410 */ | 402 | /* cr1 is 7400 || 7410 */ |
400 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq | 403 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq |
401 | /* cr0 is 74xx */ | 404 | /* cr0 is 74xx */ |
@@ -403,6 +406,7 @@ _GLOBAL(__restore_cpu_setup) | |||
403 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq | 406 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq |
404 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq | 407 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq |
405 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq | 408 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq |
409 | cror 4*cr0+eq,4*cr0+eq,4*cr7+eq | ||
406 | bne 2f | 410 | bne 2f |
407 | /* Restore 74xx specific regs */ | 411 | /* Restore 74xx specific regs */ |
408 | lwz r4,CS_MSSCR0(r5) | 412 | lwz r4,CS_MSSCR0(r5) |