[PATCH] powerpc: Merge bitops.h

Here's a revised version.  This re-introduces the set_bits() function
from ppc64, which I removed because I thought it was unused (it exists
on no other arch).  In fact it is used in the powermac interrupt code
(but not on pSeries).

- We use LARXL/STCXL macros to generate the right (32 or 64 bit)
  instructions, similar to LDL/STL from ppc_asm.h, used in fpu.S

- ppc32 previously used a full "sync" barrier at the end of
  test_and_*_bit(), whereas ppc64 used an "isync".  The merged version
  uses "isync", since I believe that's sufficient.

- The ppc64 versions of then minix_*() bitmap functions have changed
  semantics.  Previously on ppc64, these functions were big-endian
  (that is bit 0 was the LSB in the first 64-bit, big-endian word).
  On ppc32 (and x86, for that matter, they were little-endian.  As far
  as I can tell, the big-endian usage was simply wrong - I guess
  no-one ever tried to use minixfs on ppc64.

- On ppc32 find_next_bit() and find_next_zero_bit() are no longer
  inline (they were already out-of-line on ppc64).

- For ppc64, sched_find_first_bit() has moved from mmu_context.h to
  the merged bitops.  What it was doing in mmu_context.h in the first
  place, I have no idea.

- The fls() function is now implemented using the cntlzw instruction
  on ppc64, instead of generic_fls(), as it already was on ppc32.

- For ARCH=ppc, this patch requires adding arch/powerpc/lib to the
  arch/ppc/Makefile.  This in turn requires some changes to
  arch/powerpc/lib/Makefile which didn't correctly handle ARCH=ppc.

Built and running on G5.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 0 insertions, 126 deletions

diff --git a/arch/ppc/kernel/bitops.c b/arch/ppc/kernel/bitops.c
deleted file mode 100644
index 7f53d193968b..000000000000
--- a/arch/ppc/kernel/bitops.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (C) 1996 Paul Mackerras.
- */
-
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-
-/*
- * If the bitops are not inlined in bitops.h, they are defined here.
- *  -- paulus
- */
-#if !__INLINE_BITOPS
-void set_bit(int nr, volatile void * addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-        
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%3 \n\
-        or      %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc" );
-}
-
-void clear_bit(int nr, volatile void *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%3 \n\
-        andc    %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-
-void change_bit(int nr, volatile void *addr)
-{
-        unsigned long old;
-        unsigned long mask = 1 << (nr & 0x1f);
-        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
-
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%3 \n\
-        xor     %0,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-"       stwcx.  %0,0,%3 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-}
-
-int test_and_set_bit(int nr, volatile void *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        or      %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-
-        return (old & mask) != 0;
-}
-
-int test_and_clear_bit(int nr, volatile void *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        andc    %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-
-        return (old & mask) != 0;
-}
-
-int test_and_change_bit(int nr, volatile void *addr)
-{
-        unsigned int old, t;
-        unsigned int mask = 1 << (nr & 0x1f);
-        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
-
-        __asm__ __volatile__(SMP_WMB "\n\
-1:      lwarx   %0,0,%4 \n\
-        xor     %1,%0,%3 \n"
-        PPC405_ERR77(0,%4)
-"       stwcx.  %1,0,%4 \n\
-        bne     1b"
-        SMP_MB
-        : "=&r" (old), "=&r" (t), "=m" (*p)
-        : "r" (mask), "r" (p), "m" (*p)
-        : "cc");
-
-        return (old & mask) != 0;
-}
-#endif /* !__INLINE_BITOPS */