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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc/8xx_io/fec.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ppc/8xx_io/fec.c')
-rw-r--r--arch/ppc/8xx_io/fec.c1973
1 files changed, 1973 insertions, 0 deletions
diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c
new file mode 100644
index 000000000000..0730392dcc20
--- /dev/null
+++ b/arch/ppc/8xx_io/fec.c
@@ -0,0 +1,1973 @@
1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
11 * Includes support for the following PHYs: QS6612, LXT970, LXT971/2.
12 *
13 * Right now, I am very wasteful with the buffers. I allocate memory
14 * pages and then divide them into 2K frame buffers. This way I know I
15 * have buffers large enough to hold one frame within one buffer descriptor.
16 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
17 * will be much more memory efficient and will easily handle lots of
18 * small packets.
19 *
20 * Much better multiple PHY support by Magnus Damm.
21 * Copyright (c) 2000 Ericsson Radio Systems AB.
22 *
23 * Make use of MII for PHY control configurable.
24 * Some fixes.
25 * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering.
26 *
27 * Support for AMD AM79C874 added.
28 * Thomas Lange, thomas@corelatus.com
29 */
30
31#include <linux/config.h>
32#include <linux/kernel.h>
33#include <linux/sched.h>
34#include <linux/string.h>
35#include <linux/ptrace.h>
36#include <linux/errno.h>
37#include <linux/ioport.h>
38#include <linux/slab.h>
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/init.h>
42#include <linux/delay.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/skbuff.h>
46#include <linux/spinlock.h>
47#include <linux/bitops.h>
48#ifdef CONFIG_FEC_PACKETHOOK
49#include <linux/pkthook.h>
50#endif
51
52#include <asm/8xx_immap.h>
53#include <asm/pgtable.h>
54#include <asm/mpc8xx.h>
55#include <asm/irq.h>
56#include <asm/uaccess.h>
57#include <asm/commproc.h>
58
59#ifdef CONFIG_USE_MDIO
60/* Forward declarations of some structures to support different PHYs
61*/
62
63typedef struct {
64 uint mii_data;
65 void (*funct)(uint mii_reg, struct net_device *dev);
66} phy_cmd_t;
67
68typedef struct {
69 uint id;
70 char *name;
71
72 const phy_cmd_t *config;
73 const phy_cmd_t *startup;
74 const phy_cmd_t *ack_int;
75 const phy_cmd_t *shutdown;
76} phy_info_t;
77#endif /* CONFIG_USE_MDIO */
78
79/* The number of Tx and Rx buffers. These are allocated from the page
80 * pool. The code may assume these are power of two, so it is best
81 * to keep them that size.
82 * We don't need to allocate pages for the transmitter. We just use
83 * the skbuffer directly.
84 */
85#ifdef CONFIG_ENET_BIG_BUFFERS
86#define FEC_ENET_RX_PAGES 16
87#define FEC_ENET_RX_FRSIZE 2048
88#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
89#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
90#define TX_RING_SIZE 16 /* Must be power of two */
91#define TX_RING_MOD_MASK 15 /* for this to work */
92#else
93#define FEC_ENET_RX_PAGES 4
94#define FEC_ENET_RX_FRSIZE 2048
95#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
96#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
97#define TX_RING_SIZE 8 /* Must be power of two */
98#define TX_RING_MOD_MASK 7 /* for this to work */
99#endif
100
101/* Interrupt events/masks.
102*/
103#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
104#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
105#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
106#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
107#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
108#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
109#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
110#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
111#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
112#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
113
114/*
115*/
116#define FEC_ECNTRL_PINMUX 0x00000004
117#define FEC_ECNTRL_ETHER_EN 0x00000002
118#define FEC_ECNTRL_RESET 0x00000001
119
120#define FEC_RCNTRL_BC_REJ 0x00000010
121#define FEC_RCNTRL_PROM 0x00000008
122#define FEC_RCNTRL_MII_MODE 0x00000004
123#define FEC_RCNTRL_DRT 0x00000002
124#define FEC_RCNTRL_LOOP 0x00000001
125
126#define FEC_TCNTRL_FDEN 0x00000004
127#define FEC_TCNTRL_HBC 0x00000002
128#define FEC_TCNTRL_GTS 0x00000001
129
130/* Delay to wait for FEC reset command to complete (in us)
131*/
132#define FEC_RESET_DELAY 50
133
134/* The FEC stores dest/src/type, data, and checksum for receive packets.
135 */
136#define PKT_MAXBUF_SIZE 1518
137#define PKT_MINBUF_SIZE 64
138#define PKT_MAXBLR_SIZE 1520
139
140/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
147 */
148struct fec_enet_private {
149 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
150 struct sk_buff* tx_skbuff[TX_RING_SIZE];
151 ushort skb_cur;
152 ushort skb_dirty;
153
154 /* CPM dual port RAM relative addresses.
155 */
156 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
157 cbd_t *tx_bd_base;
158 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
159 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
160
161 /* Virtual addresses for the receive buffers because we can't
162 * do a __va() on them anymore.
163 */
164 unsigned char *rx_vaddr[RX_RING_SIZE];
165
166 struct net_device_stats stats;
167 uint tx_full;
168 spinlock_t lock;
169
170#ifdef CONFIG_USE_MDIO
171 uint phy_id;
172 uint phy_id_done;
173 uint phy_status;
174 uint phy_speed;
175 phy_info_t *phy;
176 struct tq_struct phy_task;
177
178 uint sequence_done;
179
180 uint phy_addr;
181#endif /* CONFIG_USE_MDIO */
182
183 int link;
184 int old_link;
185 int full_duplex;
186
187#ifdef CONFIG_FEC_PACKETHOOK
188 unsigned long ph_lock;
189 fec_ph_func *ph_rxhandler;
190 fec_ph_func *ph_txhandler;
191 __u16 ph_proto;
192 volatile __u32 *ph_regaddr;
193 void *ph_priv;
194#endif
195};
196
197static int fec_enet_open(struct net_device *dev);
198static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
199#ifdef CONFIG_USE_MDIO
200static void fec_enet_mii(struct net_device *dev);
201#endif /* CONFIG_USE_MDIO */
202static void fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
203#ifdef CONFIG_FEC_PACKETHOOK
204static void fec_enet_tx(struct net_device *dev, __u32 regval);
205static void fec_enet_rx(struct net_device *dev, __u32 regval);
206#else
207static void fec_enet_tx(struct net_device *dev);
208static void fec_enet_rx(struct net_device *dev);
209#endif
210static int fec_enet_close(struct net_device *dev);
211static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
212static void set_multicast_list(struct net_device *dev);
213static void fec_restart(struct net_device *dev, int duplex);
214static void fec_stop(struct net_device *dev);
215static ushort my_enet_addr[3];
216
217#ifdef CONFIG_USE_MDIO
218/* MII processing. We keep this as simple as possible. Requests are
219 * placed on the list (if there is room). When the request is finished
220 * by the MII, an optional function may be called.
221 */
222typedef struct mii_list {
223 uint mii_regval;
224 void (*mii_func)(uint val, struct net_device *dev);
225 struct mii_list *mii_next;
226} mii_list_t;
227
228#define NMII 20
229mii_list_t mii_cmds[NMII];
230mii_list_t *mii_free;
231mii_list_t *mii_head;
232mii_list_t *mii_tail;
233
234static int mii_queue(struct net_device *dev, int request,
235 void (*func)(uint, struct net_device *));
236
237/* Make MII read/write commands for the FEC.
238*/
239#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
240#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
241 (VAL & 0xffff))
242#define mk_mii_end 0
243#endif /* CONFIG_USE_MDIO */
244
245/* Transmitter timeout.
246*/
247#define TX_TIMEOUT (2*HZ)
248
249#ifdef CONFIG_USE_MDIO
250/* Register definitions for the PHY.
251*/
252
253#define MII_REG_CR 0 /* Control Register */
254#define MII_REG_SR 1 /* Status Register */
255#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
256#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
257#define MII_REG_ANAR 4 /* A-N Advertisement Register */
258#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
259#define MII_REG_ANER 6 /* A-N Expansion Register */
260#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
261#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
262
263/* values for phy_status */
264
265#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
266#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
267#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
268#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
269#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
270#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
271#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
272
273#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
274#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
275#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
276#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
277#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
278#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
279#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
280#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
281#endif /* CONFIG_USE_MDIO */
282
283#ifdef CONFIG_FEC_PACKETHOOK
284int
285fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun,
286 __u16 proto, volatile __u32 *regaddr, void *priv)
287{
288 struct fec_enet_private *fep;
289 int retval = 0;
290
291 fep = dev->priv;
292
293 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
294 /* Someone is messing with the packet hook */
295 return -EAGAIN;
296 }
297 if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) {
298 retval = -EBUSY;
299 goto out;
300 }
301 fep->ph_rxhandler = rxfun;
302 fep->ph_txhandler = txfun;
303 fep->ph_proto = proto;
304 fep->ph_regaddr = regaddr;
305 fep->ph_priv = priv;
306
307 out:
308 fep->ph_lock = 0;
309
310 return retval;
311}
312
313
314int
315fec_unregister_ph(struct net_device *dev)
316{
317 struct fec_enet_private *fep;
318 int retval = 0;
319
320 fep = dev->priv;
321
322 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
323 /* Someone is messing with the packet hook */
324 return -EAGAIN;
325 }
326
327 fep->ph_rxhandler = fep->ph_txhandler = NULL;
328 fep->ph_proto = 0;
329 fep->ph_regaddr = NULL;
330 fep->ph_priv = NULL;
331
332 fep->ph_lock = 0;
333
334 return retval;
335}
336
337EXPORT_SYMBOL(fec_register_ph);
338EXPORT_SYMBOL(fec_unregister_ph);
339
340#endif /* CONFIG_FEC_PACKETHOOK */
341
342static int
343fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
344{
345 struct fec_enet_private *fep;
346 volatile fec_t *fecp;
347 volatile cbd_t *bdp;
348
349 fep = dev->priv;
350 fecp = (volatile fec_t*)dev->base_addr;
351
352 if (!fep->link) {
353 /* Link is down or autonegotiation is in progress. */
354 return 1;
355 }
356
357 /* Fill in a Tx ring entry */
358 bdp = fep->cur_tx;
359
360#ifndef final_version
361 if (bdp->cbd_sc & BD_ENET_TX_READY) {
362 /* Ooops. All transmit buffers are full. Bail out.
363 * This should not happen, since dev->tbusy should be set.
364 */
365 printk("%s: tx queue full!.\n", dev->name);
366 return 1;
367 }
368#endif
369
370 /* Clear all of the status flags.
371 */
372 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
373
374 /* Set buffer length and buffer pointer.
375 */
376 bdp->cbd_bufaddr = __pa(skb->data);
377 bdp->cbd_datlen = skb->len;
378
379 /* Save skb pointer.
380 */
381 fep->tx_skbuff[fep->skb_cur] = skb;
382
383 fep->stats.tx_bytes += skb->len;
384 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
385
386 /* Push the data cache so the CPM does not get stale memory
387 * data.
388 */
389 flush_dcache_range((unsigned long)skb->data,
390 (unsigned long)skb->data + skb->len);
391
392 /* disable interrupts while triggering transmit */
393 spin_lock_irq(&fep->lock);
394
395 /* Send it on its way. Tell FEC its ready, interrupt when done,
396 * its the last BD of the frame, and to put the CRC on the end.
397 */
398
399 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
400 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
401
402 dev->trans_start = jiffies;
403
404 /* Trigger transmission start */
405 fecp->fec_x_des_active = 0x01000000;
406
407 /* If this was the last BD in the ring, start at the beginning again.
408 */
409 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
410 bdp = fep->tx_bd_base;
411 } else {
412 bdp++;
413 }
414
415 if (bdp->cbd_sc & BD_ENET_TX_READY) {
416 netif_stop_queue(dev);
417 fep->tx_full = 1;
418 }
419
420 fep->cur_tx = (cbd_t *)bdp;
421
422 spin_unlock_irq(&fep->lock);
423
424 return 0;
425}
426
427static void
428fec_timeout(struct net_device *dev)
429{
430 struct fec_enet_private *fep = dev->priv;
431
432 printk("%s: transmit timed out.\n", dev->name);
433 fep->stats.tx_errors++;
434#ifndef final_version
435 {
436 int i;
437 cbd_t *bdp;
438
439 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
440 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
441 (unsigned long)fep->dirty_tx,
442 (unsigned long)fep->cur_rx);
443
444 bdp = fep->tx_bd_base;
445 printk(" tx: %u buffers\n", TX_RING_SIZE);
446 for (i = 0 ; i < TX_RING_SIZE; i++) {
447 printk(" %08x: %04x %04x %08x\n",
448 (uint) bdp,
449 bdp->cbd_sc,
450 bdp->cbd_datlen,
451 bdp->cbd_bufaddr);
452 bdp++;
453 }
454
455 bdp = fep->rx_bd_base;
456 printk(" rx: %lu buffers\n", RX_RING_SIZE);
457 for (i = 0 ; i < RX_RING_SIZE; i++) {
458 printk(" %08x: %04x %04x %08x\n",
459 (uint) bdp,
460 bdp->cbd_sc,
461 bdp->cbd_datlen,
462 bdp->cbd_bufaddr);
463 bdp++;
464 }
465 }
466#endif
467 if (!fep->tx_full)
468 netif_wake_queue(dev);
469}
470
471/* The interrupt handler.
472 * This is called from the MPC core interrupt.
473 */
474static void
475fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
476{
477 struct net_device *dev = dev_id;
478 volatile fec_t *fecp;
479 uint int_events;
480#ifdef CONFIG_FEC_PACKETHOOK
481 struct fec_enet_private *fep = dev->priv;
482 __u32 regval;
483
484 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
485#endif
486 fecp = (volatile fec_t*)dev->base_addr;
487
488 /* Get the interrupt events that caused us to be here.
489 */
490 while ((int_events = fecp->fec_ievent) != 0) {
491 fecp->fec_ievent = int_events;
492 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
493 FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
494 printk("FEC ERROR %x\n", int_events);
495 }
496
497 /* Handle receive event in its own function.
498 */
499 if (int_events & FEC_ENET_RXF) {
500#ifdef CONFIG_FEC_PACKETHOOK
501 fec_enet_rx(dev, regval);
502#else
503 fec_enet_rx(dev);
504#endif
505 }
506
507 /* Transmit OK, or non-fatal error. Update the buffer
508 descriptors. FEC handles all errors, we just discover
509 them as part of the transmit process.
510 */
511 if (int_events & FEC_ENET_TXF) {
512#ifdef CONFIG_FEC_PACKETHOOK
513 fec_enet_tx(dev, regval);
514#else
515 fec_enet_tx(dev);
516#endif
517 }
518
519 if (int_events & FEC_ENET_MII) {
520#ifdef CONFIG_USE_MDIO
521 fec_enet_mii(dev);
522#else
523printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
524#endif /* CONFIG_USE_MDIO */
525 }
526
527 }
528}
529
530
531static void
532#ifdef CONFIG_FEC_PACKETHOOK
533fec_enet_tx(struct net_device *dev, __u32 regval)
534#else
535fec_enet_tx(struct net_device *dev)
536#endif
537{
538 struct fec_enet_private *fep;
539 volatile cbd_t *bdp;
540 struct sk_buff *skb;
541
542 fep = dev->priv;
543 /* lock while transmitting */
544 spin_lock(&fep->lock);
545 bdp = fep->dirty_tx;
546
547 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
548 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
549
550 skb = fep->tx_skbuff[fep->skb_dirty];
551 /* Check for errors. */
552 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
553 BD_ENET_TX_RL | BD_ENET_TX_UN |
554 BD_ENET_TX_CSL)) {
555 fep->stats.tx_errors++;
556 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
557 fep->stats.tx_heartbeat_errors++;
558 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
559 fep->stats.tx_window_errors++;
560 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
561 fep->stats.tx_aborted_errors++;
562 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
563 fep->stats.tx_fifo_errors++;
564 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
565 fep->stats.tx_carrier_errors++;
566 } else {
567#ifdef CONFIG_FEC_PACKETHOOK
568 /* Packet hook ... */
569 if (fep->ph_txhandler &&
570 ((struct ethhdr *)skb->data)->h_proto
571 == fep->ph_proto) {
572 fep->ph_txhandler((__u8*)skb->data, skb->len,
573 regval, fep->ph_priv);
574 }
575#endif
576 fep->stats.tx_packets++;
577 }
578
579#ifndef final_version
580 if (bdp->cbd_sc & BD_ENET_TX_READY)
581 printk("HEY! Enet xmit interrupt and TX_READY.\n");
582#endif
583 /* Deferred means some collisions occurred during transmit,
584 * but we eventually sent the packet OK.
585 */
586 if (bdp->cbd_sc & BD_ENET_TX_DEF)
587 fep->stats.collisions++;
588
589 /* Free the sk buffer associated with this last transmit.
590 */
591#if 0
592printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty);
593#endif
594 dev_kfree_skb_irq (skb/*, FREE_WRITE*/);
595 fep->tx_skbuff[fep->skb_dirty] = NULL;
596 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
597
598 /* Update pointer to next buffer descriptor to be transmitted.
599 */
600 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
601 bdp = fep->tx_bd_base;
602 else
603 bdp++;
604
605 /* Since we have freed up a buffer, the ring is no longer
606 * full.
607 */
608 if (fep->tx_full) {
609 fep->tx_full = 0;
610 if (netif_queue_stopped(dev))
611 netif_wake_queue(dev);
612 }
613#ifdef CONFIG_FEC_PACKETHOOK
614 /* Re-read register. Not exactly guaranteed to be correct,
615 but... */
616 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
617#endif
618 }
619 fep->dirty_tx = (cbd_t *)bdp;
620 spin_unlock(&fep->lock);
621}
622
623
624/* During a receive, the cur_rx points to the current incoming buffer.
625 * When we update through the ring, if the next incoming buffer has
626 * not been given to the system, we just set the empty indicator,
627 * effectively tossing the packet.
628 */
629static void
630#ifdef CONFIG_FEC_PACKETHOOK
631fec_enet_rx(struct net_device *dev, __u32 regval)
632#else
633fec_enet_rx(struct net_device *dev)
634#endif
635{
636 struct fec_enet_private *fep;
637 volatile fec_t *fecp;
638 volatile cbd_t *bdp;
639 struct sk_buff *skb;
640 ushort pkt_len;
641 __u8 *data;
642
643 fep = dev->priv;
644 fecp = (volatile fec_t*)dev->base_addr;
645
646 /* First, grab all of the stats for the incoming packet.
647 * These get messed up if we get called due to a busy condition.
648 */
649 bdp = fep->cur_rx;
650
651while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
652
653#ifndef final_version
654 /* Since we have allocated space to hold a complete frame,
655 * the last indicator should be set.
656 */
657 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
658 printk("FEC ENET: rcv is not +last\n");
659#endif
660
661 /* Check for errors. */
662 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
663 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
664 fep->stats.rx_errors++;
665 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
666 /* Frame too long or too short. */
667 fep->stats.rx_length_errors++;
668 }
669 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
670 fep->stats.rx_frame_errors++;
671 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
672 fep->stats.rx_crc_errors++;
673 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
674 fep->stats.rx_crc_errors++;
675 }
676
677 /* Report late collisions as a frame error.
678 * On this error, the BD is closed, but we don't know what we
679 * have in the buffer. So, just drop this frame on the floor.
680 */
681 if (bdp->cbd_sc & BD_ENET_RX_CL) {
682 fep->stats.rx_errors++;
683 fep->stats.rx_frame_errors++;
684 goto rx_processing_done;
685 }
686
687 /* Process the incoming frame.
688 */
689 fep->stats.rx_packets++;
690 pkt_len = bdp->cbd_datlen;
691 fep->stats.rx_bytes += pkt_len;
692 data = fep->rx_vaddr[bdp - fep->rx_bd_base];
693
694#ifdef CONFIG_FEC_PACKETHOOK
695 /* Packet hook ... */
696 if (fep->ph_rxhandler) {
697 if (((struct ethhdr *)data)->h_proto == fep->ph_proto) {
698 switch (fep->ph_rxhandler(data, pkt_len, regval,
699 fep->ph_priv)) {
700 case 1:
701 goto rx_processing_done;
702 break;
703 case 0:
704 break;
705 default:
706 fep->stats.rx_errors++;
707 goto rx_processing_done;
708 }
709 }
710 }
711
712 /* If it wasn't filtered - copy it to an sk buffer. */
713#endif
714
715 /* This does 16 byte alignment, exactly what we need.
716 * The packet length includes FCS, but we don't want to
717 * include that when passing upstream as it messes up
718 * bridging applications.
719 */
720 skb = dev_alloc_skb(pkt_len-4);
721
722 if (skb == NULL) {
723 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
724 fep->stats.rx_dropped++;
725 } else {
726 skb->dev = dev;
727 skb_put(skb,pkt_len-4); /* Make room */
728 eth_copy_and_sum(skb, data, pkt_len-4, 0);
729 skb->protocol=eth_type_trans(skb,dev);
730 netif_rx(skb);
731 }
732 rx_processing_done:
733
734 /* Clear the status flags for this buffer.
735 */
736 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
737
738 /* Mark the buffer empty.
739 */
740 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
741
742 /* Update BD pointer to next entry.
743 */
744 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
745 bdp = fep->rx_bd_base;
746 else
747 bdp++;
748
749#if 1
750 /* Doing this here will keep the FEC running while we process
751 * incoming frames. On a heavily loaded network, we should be
752 * able to keep up at the expense of system resources.
753 */
754 fecp->fec_r_des_active = 0x01000000;
755#endif
756#ifdef CONFIG_FEC_PACKETHOOK
757 /* Re-read register. Not exactly guaranteed to be correct,
758 but... */
759 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
760#endif
761 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
762 fep->cur_rx = (cbd_t *)bdp;
763
764#if 0
765 /* Doing this here will allow us to process all frames in the
766 * ring before the FEC is allowed to put more there. On a heavily
767 * loaded network, some frames may be lost. Unfortunately, this
768 * increases the interrupt overhead since we can potentially work
769 * our way back to the interrupt return only to come right back
770 * here.
771 */
772 fecp->fec_r_des_active = 0x01000000;
773#endif
774}
775
776
777#ifdef CONFIG_USE_MDIO
778static void
779fec_enet_mii(struct net_device *dev)
780{
781 struct fec_enet_private *fep;
782 volatile fec_t *ep;
783 mii_list_t *mip;
784 uint mii_reg;
785
786 fep = (struct fec_enet_private *)dev->priv;
787 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
788 mii_reg = ep->fec_mii_data;
789
790 if ((mip = mii_head) == NULL) {
791 printk("MII and no head!\n");
792 return;
793 }
794
795 if (mip->mii_func != NULL)
796 (*(mip->mii_func))(mii_reg, dev);
797
798 mii_head = mip->mii_next;
799 mip->mii_next = mii_free;
800 mii_free = mip;
801
802 if ((mip = mii_head) != NULL) {
803 ep->fec_mii_data = mip->mii_regval;
804
805 }
806}
807
808static int
809mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
810{
811 struct fec_enet_private *fep;
812 unsigned long flags;
813 mii_list_t *mip;
814 int retval;
815
816 /* Add PHY address to register command.
817 */
818 fep = dev->priv;
819 regval |= fep->phy_addr << 23;
820
821 retval = 0;
822
823 /* lock while modifying mii_list */
824 spin_lock_irqsave(&fep->lock, flags);
825
826 if ((mip = mii_free) != NULL) {
827 mii_free = mip->mii_next;
828 mip->mii_regval = regval;
829 mip->mii_func = func;
830 mip->mii_next = NULL;
831 if (mii_head) {
832 mii_tail->mii_next = mip;
833 mii_tail = mip;
834 } else {
835 mii_head = mii_tail = mip;
836 (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
837 }
838 } else {
839 retval = 1;
840 }
841
842 spin_unlock_irqrestore(&fep->lock, flags);
843
844 return(retval);
845}
846
847static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
848{
849 int k;
850
851 if(!c)
852 return;
853
854 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
855 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
856}
857
858static void mii_parse_sr(uint mii_reg, struct net_device *dev)
859{
860 struct fec_enet_private *fep = dev->priv;
861 volatile uint *s = &(fep->phy_status);
862
863 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
864
865 if (mii_reg & 0x0004)
866 *s |= PHY_STAT_LINK;
867 if (mii_reg & 0x0010)
868 *s |= PHY_STAT_FAULT;
869 if (mii_reg & 0x0020)
870 *s |= PHY_STAT_ANC;
871
872 fep->link = (*s & PHY_STAT_LINK) ? 1 : 0;
873}
874
875static void mii_parse_cr(uint mii_reg, struct net_device *dev)
876{
877 struct fec_enet_private *fep = dev->priv;
878 volatile uint *s = &(fep->phy_status);
879
880 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
881
882 if (mii_reg & 0x1000)
883 *s |= PHY_CONF_ANE;
884 if (mii_reg & 0x4000)
885 *s |= PHY_CONF_LOOP;
886}
887
888static void mii_parse_anar(uint mii_reg, struct net_device *dev)
889{
890 struct fec_enet_private *fep = dev->priv;
891 volatile uint *s = &(fep->phy_status);
892
893 *s &= ~(PHY_CONF_SPMASK);
894
895 if (mii_reg & 0x0020)
896 *s |= PHY_CONF_10HDX;
897 if (mii_reg & 0x0040)
898 *s |= PHY_CONF_10FDX;
899 if (mii_reg & 0x0080)
900 *s |= PHY_CONF_100HDX;
901 if (mii_reg & 0x00100)
902 *s |= PHY_CONF_100FDX;
903}
904#if 0
905static void mii_disp_reg(uint mii_reg, struct net_device *dev)
906{
907 printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff);
908}
909#endif
910
911/* ------------------------------------------------------------------------- */
912/* The Level one LXT970 is used by many boards */
913
914#ifdef CONFIG_FEC_LXT970
915
916#define MII_LXT970_MIRROR 16 /* Mirror register */
917#define MII_LXT970_IER 17 /* Interrupt Enable Register */
918#define MII_LXT970_ISR 18 /* Interrupt Status Register */
919#define MII_LXT970_CONFIG 19 /* Configuration Register */
920#define MII_LXT970_CSR 20 /* Chip Status Register */
921
922static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
923{
924 struct fec_enet_private *fep = dev->priv;
925 volatile uint *s = &(fep->phy_status);
926
927 *s &= ~(PHY_STAT_SPMASK);
928
929 if (mii_reg & 0x0800) {
930 if (mii_reg & 0x1000)
931 *s |= PHY_STAT_100FDX;
932 else
933 *s |= PHY_STAT_100HDX;
934 }
935 else {
936 if (mii_reg & 0x1000)
937 *s |= PHY_STAT_10FDX;
938 else
939 *s |= PHY_STAT_10HDX;
940 }
941}
942
943static phy_info_t phy_info_lxt970 = {
944 0x07810000,
945 "LXT970",
946
947 (const phy_cmd_t []) { /* config */
948#if 0
949// { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
950
951 /* Set default operation of 100-TX....for some reason
952 * some of these bits are set on power up, which is wrong.
953 */
954 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
955#endif
956 { mk_mii_read(MII_REG_CR), mii_parse_cr },
957 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
958 { mk_mii_end, }
959 },
960 (const phy_cmd_t []) { /* startup - enable interrupts */
961 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
962 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
963 { mk_mii_end, }
964 },
965 (const phy_cmd_t []) { /* ack_int */
966 /* read SR and ISR to acknowledge */
967
968 { mk_mii_read(MII_REG_SR), mii_parse_sr },
969 { mk_mii_read(MII_LXT970_ISR), NULL },
970
971 /* find out the current status */
972
973 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
974 { mk_mii_end, }
975 },
976 (const phy_cmd_t []) { /* shutdown - disable interrupts */
977 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
978 { mk_mii_end, }
979 },
980};
981
982#endif /* CONFIG_FEC_LXT970 */
983
984/* ------------------------------------------------------------------------- */
985/* The Level one LXT971 is used on some of my custom boards */
986
987#ifdef CONFIG_FEC_LXT971
988
989/* register definitions for the 971 */
990
991#define MII_LXT971_PCR 16 /* Port Control Register */
992#define MII_LXT971_SR2 17 /* Status Register 2 */
993#define MII_LXT971_IER 18 /* Interrupt Enable Register */
994#define MII_LXT971_ISR 19 /* Interrupt Status Register */
995#define MII_LXT971_LCR 20 /* LED Control Register */
996#define MII_LXT971_TCR 30 /* Transmit Control Register */
997
998/*
999 * I had some nice ideas of running the MDIO faster...
1000 * The 971 should support 8MHz and I tried it, but things acted really
1001 * weird, so 2.5 MHz ought to be enough for anyone...
1002 */
1003
1004static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1005{
1006 struct fec_enet_private *fep = dev->priv;
1007 volatile uint *s = &(fep->phy_status);
1008
1009 *s &= ~(PHY_STAT_SPMASK);
1010
1011 if (mii_reg & 0x4000) {
1012 if (mii_reg & 0x0200)
1013 *s |= PHY_STAT_100FDX;
1014 else
1015 *s |= PHY_STAT_100HDX;
1016 }
1017 else {
1018 if (mii_reg & 0x0200)
1019 *s |= PHY_STAT_10FDX;
1020 else
1021 *s |= PHY_STAT_10HDX;
1022 }
1023 if (mii_reg & 0x0008)
1024 *s |= PHY_STAT_FAULT;
1025}
1026
1027static phy_info_t phy_info_lxt971 = {
1028 0x0001378e,
1029 "LXT971",
1030
1031 (const phy_cmd_t []) { /* config */
1032// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1033 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1034 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1035 { mk_mii_end, }
1036 },
1037 (const phy_cmd_t []) { /* startup - enable interrupts */
1038 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1039 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1040
1041 /* Somehow does the 971 tell me that the link is down
1042 * the first read after power-up.
1043 * read here to get a valid value in ack_int */
1044
1045 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1046 { mk_mii_end, }
1047 },
1048 (const phy_cmd_t []) { /* ack_int */
1049 /* find out the current status */
1050
1051 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1052 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1053
1054 /* we only need to read ISR to acknowledge */
1055
1056 { mk_mii_read(MII_LXT971_ISR), NULL },
1057 { mk_mii_end, }
1058 },
1059 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1060 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1061 { mk_mii_end, }
1062 },
1063};
1064
1065#endif /* CONFIG_FEC_LXT970 */
1066
1067
1068/* ------------------------------------------------------------------------- */
1069/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
1070
1071#ifdef CONFIG_FEC_QS6612
1072
1073/* register definitions */
1074
1075#define MII_QS6612_MCR 17 /* Mode Control Register */
1076#define MII_QS6612_FTR 27 /* Factory Test Register */
1077#define MII_QS6612_MCO 28 /* Misc. Control Register */
1078#define MII_QS6612_ISR 29 /* Interrupt Source Register */
1079#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1080#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1081
1082static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1083{
1084 struct fec_enet_private *fep = dev->priv;
1085 volatile uint *s = &(fep->phy_status);
1086
1087 *s &= ~(PHY_STAT_SPMASK);
1088
1089 switch((mii_reg >> 2) & 7) {
1090 case 1: *s |= PHY_STAT_10HDX; break;
1091 case 2: *s |= PHY_STAT_100HDX; break;
1092 case 5: *s |= PHY_STAT_10FDX; break;
1093 case 6: *s |= PHY_STAT_100FDX; break;
1094 }
1095}
1096
1097static phy_info_t phy_info_qs6612 = {
1098 0x00181440,
1099 "QS6612",
1100
1101 (const phy_cmd_t []) { /* config */
1102// { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1103
1104 /* The PHY powers up isolated on the RPX,
1105 * so send a command to allow operation.
1106 */
1107
1108 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1109
1110 /* parse cr and anar to get some info */
1111
1112 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1113 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1114 { mk_mii_end, }
1115 },
1116 (const phy_cmd_t []) { /* startup - enable interrupts */
1117 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1118 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1119 { mk_mii_end, }
1120 },
1121 (const phy_cmd_t []) { /* ack_int */
1122
1123 /* we need to read ISR, SR and ANER to acknowledge */
1124
1125 { mk_mii_read(MII_QS6612_ISR), NULL },
1126 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1127 { mk_mii_read(MII_REG_ANER), NULL },
1128
1129 /* read pcr to get info */
1130
1131 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1132 { mk_mii_end, }
1133 },
1134 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1135 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1136 { mk_mii_end, }
1137 },
1138};
1139
1140#endif /* CONFIG_FEC_QS6612 */
1141
1142/* ------------------------------------------------------------------------- */
1143/* The Advanced Micro Devices AM79C874 is used on the ICU862 */
1144
1145#ifdef CONFIG_FEC_AM79C874
1146
1147/* register definitions for the 79C874 */
1148
1149#define MII_AM79C874_MFR 16 /* Miscellaneous Features Register */
1150#define MII_AM79C874_ICSR 17 /* Interrupt Control/Status Register */
1151#define MII_AM79C874_DR 18 /* Diagnostic Register */
1152#define MII_AM79C874_PMLR 19 /* Power Management & Loopback Register */
1153#define MII_AM79C874_MCR 21 /* Mode Control Register */
1154#define MII_AM79C874_DC 23 /* Disconnect Counter */
1155#define MII_AM79C874_REC 24 /* Receiver Error Counter */
1156
1157static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data)
1158{
1159 volatile struct fec_enet_private *fep = dev->priv;
1160 uint s = fep->phy_status;
1161
1162 s &= ~(PHY_STAT_SPMASK);
1163
1164 /* Register 18: Bit 10 is data rate, 11 is Duplex */
1165 switch ((mii_reg >> 10) & 3) {
1166 case 0: s |= PHY_STAT_10HDX; break;
1167 case 1: s |= PHY_STAT_100HDX; break;
1168 case 2: s |= PHY_STAT_10FDX; break;
1169 case 3: s |= PHY_STAT_100FDX; break;
1170 }
1171
1172 fep->phy_status = s;
1173}
1174
1175static phy_info_t phy_info_amd79c874 = {
1176 0x00022561,
1177 "AM79C874",
1178
1179 (const phy_cmd_t []) { /* config */
1180// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1181 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1182 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1183 { mk_mii_end, }
1184 },
1185 (const phy_cmd_t []) { /* startup - enable interrupts */
1186 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1187 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1188 { mk_mii_end, }
1189 },
1190 (const phy_cmd_t []) { /* ack_int */
1191 /* find out the current status */
1192
1193 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1194 { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr },
1195
1196 /* we only need to read ICSR to acknowledge */
1197
1198 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1199 { mk_mii_end, }
1200 },
1201 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1202 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1203 { mk_mii_end, }
1204 },
1205};
1206
1207#endif /* CONFIG_FEC_AM79C874 */
1208
1209static phy_info_t *phy_info[] = {
1210
1211#ifdef CONFIG_FEC_LXT970
1212 &phy_info_lxt970,
1213#endif /* CONFIG_FEC_LXT970 */
1214
1215#ifdef CONFIG_FEC_LXT971
1216 &phy_info_lxt971,
1217#endif /* CONFIG_FEC_LXT971 */
1218
1219#ifdef CONFIG_FEC_QS6612
1220 &phy_info_qs6612,
1221#endif /* CONFIG_FEC_QS6612 */
1222
1223#ifdef CONFIG_FEC_AM79C874
1224 &phy_info_amd79c874,
1225#endif /* CONFIG_FEC_AM79C874 */
1226
1227 NULL
1228};
1229
1230static void mii_display_status(struct net_device *dev)
1231{
1232 struct fec_enet_private *fep = dev->priv;
1233 volatile uint *s = &(fep->phy_status);
1234
1235 if (!fep->link && !fep->old_link) {
1236 /* Link is still down - don't print anything */
1237 return;
1238 }
1239
1240 printk("%s: status: ", dev->name);
1241
1242 if (!fep->link) {
1243 printk("link down");
1244 } else {
1245 printk("link up");
1246
1247 switch(*s & PHY_STAT_SPMASK) {
1248 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1249 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1250 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1251 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1252 default:
1253 printk(", Unknown speed/duplex");
1254 }
1255
1256 if (*s & PHY_STAT_ANC)
1257 printk(", auto-negotiation complete");
1258 }
1259
1260 if (*s & PHY_STAT_FAULT)
1261 printk(", remote fault");
1262
1263 printk(".\n");
1264}
1265
1266static void mii_display_config(struct net_device *dev)
1267{
1268 struct fec_enet_private *fep = dev->priv;
1269 volatile uint *s = &(fep->phy_status);
1270
1271 printk("%s: config: auto-negotiation ", dev->name);
1272
1273 if (*s & PHY_CONF_ANE)
1274 printk("on");
1275 else
1276 printk("off");
1277
1278 if (*s & PHY_CONF_100FDX)
1279 printk(", 100FDX");
1280 if (*s & PHY_CONF_100HDX)
1281 printk(", 100HDX");
1282 if (*s & PHY_CONF_10FDX)
1283 printk(", 10FDX");
1284 if (*s & PHY_CONF_10HDX)
1285 printk(", 10HDX");
1286 if (!(*s & PHY_CONF_SPMASK))
1287 printk(", No speed/duplex selected?");
1288
1289 if (*s & PHY_CONF_LOOP)
1290 printk(", loopback enabled");
1291
1292 printk(".\n");
1293
1294 fep->sequence_done = 1;
1295}
1296
1297static void mii_relink(struct net_device *dev)
1298{
1299 struct fec_enet_private *fep = dev->priv;
1300 int duplex;
1301
1302 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1303 mii_display_status(dev);
1304 fep->old_link = fep->link;
1305
1306 if (fep->link) {
1307 duplex = 0;
1308 if (fep->phy_status
1309 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1310 duplex = 1;
1311 fec_restart(dev, duplex);
1312 }
1313 else
1314 fec_stop(dev);
1315
1316#if 0
1317 enable_irq(fep->mii_irq);
1318#endif
1319
1320}
1321
1322static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1323{
1324 struct fec_enet_private *fep = dev->priv;
1325
1326 fep->phy_task.routine = (void *)mii_relink;
1327 fep->phy_task.data = dev;
1328 schedule_task(&fep->phy_task);
1329}
1330
1331static void mii_queue_config(uint mii_reg, struct net_device *dev)
1332{
1333 struct fec_enet_private *fep = dev->priv;
1334
1335 fep->phy_task.routine = (void *)mii_display_config;
1336 fep->phy_task.data = dev;
1337 schedule_task(&fep->phy_task);
1338}
1339
1340
1341
1342phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1343 { mk_mii_end, } };
1344phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1345 { mk_mii_end, } };
1346
1347
1348
1349/* Read remainder of PHY ID.
1350*/
1351static void
1352mii_discover_phy3(uint mii_reg, struct net_device *dev)
1353{
1354 struct fec_enet_private *fep;
1355 int i;
1356
1357 fep = dev->priv;
1358 fep->phy_id |= (mii_reg & 0xffff);
1359
1360 for(i = 0; phy_info[i]; i++)
1361 if(phy_info[i]->id == (fep->phy_id >> 4))
1362 break;
1363
1364 if(!phy_info[i])
1365 panic("%s: PHY id 0x%08x is not supported!\n",
1366 dev->name, fep->phy_id);
1367
1368 fep->phy = phy_info[i];
1369 fep->phy_id_done = 1;
1370
1371 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1372 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1373}
1374
1375/* Scan all of the MII PHY addresses looking for someone to respond
1376 * with a valid ID. This usually happens quickly.
1377 */
1378static void
1379mii_discover_phy(uint mii_reg, struct net_device *dev)
1380{
1381 struct fec_enet_private *fep;
1382 uint phytype;
1383
1384 fep = dev->priv;
1385
1386 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1387
1388 /* Got first part of ID, now get remainder.
1389 */
1390 fep->phy_id = phytype << 16;
1391 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1392 } else {
1393 fep->phy_addr++;
1394 if (fep->phy_addr < 32) {
1395 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1396 mii_discover_phy);
1397 } else {
1398 printk("fec: No PHY device found.\n");
1399 }
1400 }
1401}
1402#endif /* CONFIG_USE_MDIO */
1403
1404/* This interrupt occurs when the PHY detects a link change.
1405*/
1406static void
1407#ifdef CONFIG_RPXCLASSIC
1408mii_link_interrupt(void *dev_id)
1409#else
1410mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1411#endif
1412{
1413#ifdef CONFIG_USE_MDIO
1414 struct net_device *dev = dev_id;
1415 struct fec_enet_private *fep = dev->priv;
1416 volatile immap_t *immap = (immap_t *)IMAP_ADDR;
1417 volatile fec_t *fecp = &(immap->im_cpm.cp_fec);
1418 unsigned int ecntrl = fecp->fec_ecntrl;
1419
1420 /* We need the FEC enabled to access the MII
1421 */
1422 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1423 fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN;
1424 }
1425#endif /* CONFIG_USE_MDIO */
1426
1427#if 0
1428 disable_irq(fep->mii_irq); /* disable now, enable later */
1429#endif
1430
1431
1432#ifdef CONFIG_USE_MDIO
1433 mii_do_cmd(dev, fep->phy->ack_int);
1434 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1435
1436 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1437 fecp->fec_ecntrl = ecntrl; /* restore old settings */
1438 }
1439#else
1440printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
1441#endif /* CONFIG_USE_MDIO */
1442
1443}
1444
1445static int
1446fec_enet_open(struct net_device *dev)
1447{
1448 struct fec_enet_private *fep = dev->priv;
1449
1450 /* I should reset the ring buffers here, but I don't yet know
1451 * a simple way to do that.
1452 */
1453
1454#ifdef CONFIG_USE_MDIO
1455 fep->sequence_done = 0;
1456 fep->link = 0;
1457
1458 if (fep->phy) {
1459 mii_do_cmd(dev, fep->phy->ack_int);
1460 mii_do_cmd(dev, fep->phy->config);
1461 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1462 while(!fep->sequence_done)
1463 schedule();
1464
1465 mii_do_cmd(dev, fep->phy->startup);
1466 netif_start_queue(dev);
1467 return 0; /* Success */
1468 }
1469 return -ENODEV; /* No PHY we understand */
1470#else
1471 fep->link = 1;
1472 netif_start_queue(dev);
1473 return 0; /* Success */
1474#endif /* CONFIG_USE_MDIO */
1475
1476}
1477
1478static int
1479fec_enet_close(struct net_device *dev)
1480{
1481 /* Don't know what to do yet.
1482 */
1483 netif_stop_queue(dev);
1484 fec_stop(dev);
1485
1486 return 0;
1487}
1488
1489static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1490{
1491 struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv;
1492
1493 return &fep->stats;
1494}
1495
1496/* Set or clear the multicast filter for this adaptor.
1497 * Skeleton taken from sunlance driver.
1498 * The CPM Ethernet implementation allows Multicast as well as individual
1499 * MAC address filtering. Some of the drivers check to make sure it is
1500 * a group multicast address, and discard those that are not. I guess I
1501 * will do the same for now, but just remove the test if you want
1502 * individual filtering as well (do the upper net layers want or support
1503 * this kind of feature?).
1504 */
1505
1506static void set_multicast_list(struct net_device *dev)
1507{
1508 struct fec_enet_private *fep;
1509 volatile fec_t *ep;
1510
1511 fep = (struct fec_enet_private *)dev->priv;
1512 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
1513
1514 if (dev->flags&IFF_PROMISC) {
1515
1516 /* Log any net taps. */
1517 printk("%s: Promiscuous mode enabled.\n", dev->name);
1518 ep->fec_r_cntrl |= FEC_RCNTRL_PROM;
1519 } else {
1520
1521 ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM;
1522
1523 if (dev->flags & IFF_ALLMULTI) {
1524 /* Catch all multicast addresses, so set the
1525 * filter to all 1's.
1526 */
1527 ep->fec_hash_table_high = 0xffffffff;
1528 ep->fec_hash_table_low = 0xffffffff;
1529 }
1530#if 0
1531 else {
1532 /* Clear filter and add the addresses in the list.
1533 */
1534 ep->sen_gaddr1 = 0;
1535 ep->sen_gaddr2 = 0;
1536 ep->sen_gaddr3 = 0;
1537 ep->sen_gaddr4 = 0;
1538
1539 dmi = dev->mc_list;
1540
1541 for (i=0; i<dev->mc_count; i++) {
1542
1543 /* Only support group multicast for now.
1544 */
1545 if (!(dmi->dmi_addr[0] & 1))
1546 continue;
1547
1548 /* The address in dmi_addr is LSB first,
1549 * and taddr is MSB first. We have to
1550 * copy bytes MSB first from dmi_addr.
1551 */
1552 mcptr = (u_char *)dmi->dmi_addr + 5;
1553 tdptr = (u_char *)&ep->sen_taddrh;
1554 for (j=0; j<6; j++)
1555 *tdptr++ = *mcptr--;
1556
1557 /* Ask CPM to run CRC and set bit in
1558 * filter mask.
1559 */
1560 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG;
1561 /* this delay is necessary here -- Cort */
1562 udelay(10);
1563 while (cpmp->cp_cpcr & CPM_CR_FLG);
1564 }
1565 }
1566#endif
1567 }
1568}
1569
1570/* Initialize the FEC Ethernet on 860T.
1571 */
1572static int __init fec_enet_init(void)
1573{
1574 struct net_device *dev;
1575 struct fec_enet_private *fep;
1576 int i, j, k, err;
1577 unsigned char *eap, *iap, *ba;
1578 unsigned long mem_addr;
1579 volatile cbd_t *bdp;
1580 cbd_t *cbd_base;
1581 volatile immap_t *immap;
1582 volatile fec_t *fecp;
1583 bd_t *bd;
1584#ifdef CONFIG_SCC_ENET
1585 unsigned char tmpaddr[6];
1586#endif
1587
1588 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1589
1590 bd = (bd_t *)__res;
1591
1592 dev = alloc_etherdev(sizeof(*fep));
1593 if (!dev)
1594 return -ENOMEM;
1595
1596 fep = dev->priv;
1597
1598 fecp = &(immap->im_cpm.cp_fec);
1599
1600 /* Whack a reset. We should wait for this.
1601 */
1602 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1603 for (i = 0;
1604 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1605 ++i) {
1606 udelay(1);
1607 }
1608 if (i == FEC_RESET_DELAY) {
1609 printk ("FEC Reset timeout!\n");
1610 }
1611
1612 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1613 * this needs some work to get unique addresses.
1614 */
1615 eap = (unsigned char *)my_enet_addr;
1616 iap = bd->bi_enetaddr;
1617
1618#ifdef CONFIG_SCC_ENET
1619 /*
1620 * If a board has Ethernet configured both on a SCC and the
1621 * FEC, it needs (at least) 2 MAC addresses (we know that Sun
1622 * disagrees, but anyway). For the FEC port, we create
1623 * another address by setting one of the address bits above
1624 * something that would have (up to now) been allocated.
1625 */
1626 for (i=0; i<6; i++)
1627 tmpaddr[i] = *iap++;
1628 tmpaddr[3] |= 0x80;
1629 iap = tmpaddr;
1630#endif
1631
1632 for (i=0; i<6; i++) {
1633 dev->dev_addr[i] = *eap++ = *iap++;
1634 }
1635
1636 /* Allocate memory for buffer descriptors.
1637 */
1638 if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1639 printk("FEC init error. Need more space.\n");
1640 printk("FEC initialization failed.\n");
1641 return 1;
1642 }
1643 cbd_base = (cbd_t *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
1644
1645 /* Set receive and transmit descriptor base.
1646 */
1647 fep->rx_bd_base = cbd_base;
1648 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1649
1650 fep->skb_cur = fep->skb_dirty = 0;
1651
1652 /* Initialize the receive buffer descriptors.
1653 */
1654 bdp = fep->rx_bd_base;
1655 k = 0;
1656 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1657
1658 /* Allocate a page.
1659 */
1660 ba = (unsigned char *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
1661 /* BUG: no check for failure */
1662
1663 /* Initialize the BD for every fragment in the page.
1664 */
1665 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1666 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1667 bdp->cbd_bufaddr = mem_addr;
1668 fep->rx_vaddr[k++] = ba;
1669 mem_addr += FEC_ENET_RX_FRSIZE;
1670 ba += FEC_ENET_RX_FRSIZE;
1671 bdp++;
1672 }
1673 }
1674
1675 /* Set the last buffer to wrap.
1676 */
1677 bdp--;
1678 bdp->cbd_sc |= BD_SC_WRAP;
1679
1680#ifdef CONFIG_FEC_PACKETHOOK
1681 fep->ph_lock = 0;
1682 fep->ph_rxhandler = fep->ph_txhandler = NULL;
1683 fep->ph_proto = 0;
1684 fep->ph_regaddr = NULL;
1685 fep->ph_priv = NULL;
1686#endif
1687
1688 /* Install our interrupt handler.
1689 */
1690 if (request_irq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1691 panic("Could not allocate FEC IRQ!");
1692
1693#ifdef CONFIG_RPXCLASSIC
1694 /* Make Port C, bit 15 an input that causes interrupts.
1695 */
1696 immap->im_ioport.iop_pcpar &= ~0x0001;
1697 immap->im_ioport.iop_pcdir &= ~0x0001;
1698 immap->im_ioport.iop_pcso &= ~0x0001;
1699 immap->im_ioport.iop_pcint |= 0x0001;
1700 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1701
1702 /* Make LEDS reflect Link status.
1703 */
1704 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1705#endif
1706
1707#ifdef PHY_INTERRUPT
1708 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
1709 (0x80000000 >> PHY_INTERRUPT);
1710
1711 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0)
1712 panic("Could not allocate MII IRQ!");
1713#endif
1714
1715 dev->base_addr = (unsigned long)fecp;
1716
1717 /* The FEC Ethernet specific entries in the device structure. */
1718 dev->open = fec_enet_open;
1719 dev->hard_start_xmit = fec_enet_start_xmit;
1720 dev->tx_timeout = fec_timeout;
1721 dev->watchdog_timeo = TX_TIMEOUT;
1722 dev->stop = fec_enet_close;
1723 dev->get_stats = fec_enet_get_stats;
1724 dev->set_multicast_list = set_multicast_list;
1725
1726#ifdef CONFIG_USE_MDIO
1727 for (i=0; i<NMII-1; i++)
1728 mii_cmds[i].mii_next = &mii_cmds[i+1];
1729 mii_free = mii_cmds;
1730#endif /* CONFIG_USE_MDIO */
1731
1732 /* Configure all of port D for MII.
1733 */
1734 immap->im_ioport.iop_pdpar = 0x1fff;
1735
1736 /* Bits moved from Rev. D onward.
1737 */
1738 if ((mfspr(SPRN_IMMR) & 0xffff) < 0x0501)
1739 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1740 else
1741 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1742
1743#ifdef CONFIG_USE_MDIO
1744 /* Set MII speed to 2.5 MHz
1745 */
1746 fecp->fec_mii_speed = fep->phy_speed =
1747 (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1;
1748#else
1749 fecp->fec_mii_speed = 0; /* turn off MDIO */
1750#endif /* CONFIG_USE_MDIO */
1751
1752 err = register_netdev(dev);
1753 if (err) {
1754 free_netdev(dev);
1755 return err;
1756 }
1757
1758 printk ("%s: FEC ENET Version 0.2, FEC irq %d"
1759#ifdef PHY_INTERRUPT
1760 ", MII irq %d"
1761#endif
1762 ", addr ",
1763 dev->name, FEC_INTERRUPT
1764#ifdef PHY_INTERRUPT
1765 , PHY_INTERRUPT
1766#endif
1767 );
1768 for (i=0; i<6; i++)
1769 printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':');
1770
1771#ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */
1772 fec_restart (dev, 1);
1773#else /* always use half duplex mode only */
1774 fec_restart (dev, 0);
1775#endif
1776
1777#ifdef CONFIG_USE_MDIO
1778 /* Queue up command to detect the PHY and initialize the
1779 * remainder of the interface.
1780 */
1781 fep->phy_id_done = 0;
1782 fep->phy_addr = 0;
1783 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1784#endif /* CONFIG_USE_MDIO */
1785
1786 return 0;
1787}
1788module_init(fec_enet_init);
1789
1790/* This function is called to start or restart the FEC during a link
1791 * change. This only happens when switching between half and full
1792 * duplex.
1793 */
1794static void
1795fec_restart(struct net_device *dev, int duplex)
1796{
1797 struct fec_enet_private *fep;
1798 int i;
1799 volatile cbd_t *bdp;
1800 volatile immap_t *immap;
1801 volatile fec_t *fecp;
1802
1803 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1804
1805 fecp = &(immap->im_cpm.cp_fec);
1806
1807 fep = dev->priv;
1808
1809 /* Whack a reset. We should wait for this.
1810 */
1811 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1812 for (i = 0;
1813 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1814 ++i) {
1815 udelay(1);
1816 }
1817 if (i == FEC_RESET_DELAY) {
1818 printk ("FEC Reset timeout!\n");
1819 }
1820
1821 /* Set station address.
1822 */
1823 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1824 fecp->fec_addr_high = my_enet_addr[2];
1825
1826 /* Reset all multicast.
1827 */
1828 fecp->fec_hash_table_high = 0;
1829 fecp->fec_hash_table_low = 0;
1830
1831 /* Set maximum receive buffer size.
1832 */
1833 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1834 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1835
1836 /* Set receive and transmit descriptor base.
1837 */
1838 fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base));
1839 fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base));
1840
1841 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1842 fep->cur_rx = fep->rx_bd_base;
1843
1844 /* Reset SKB transmit buffers.
1845 */
1846 fep->skb_cur = fep->skb_dirty = 0;
1847 for (i=0; i<=TX_RING_MOD_MASK; i++) {
1848 if (fep->tx_skbuff[i] != NULL) {
1849 dev_kfree_skb(fep->tx_skbuff[i]);
1850 fep->tx_skbuff[i] = NULL;
1851 }
1852 }
1853
1854 /* Initialize the receive buffer descriptors.
1855 */
1856 bdp = fep->rx_bd_base;
1857 for (i=0; i<RX_RING_SIZE; i++) {
1858
1859 /* Initialize the BD for every fragment in the page.
1860 */
1861 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1862 bdp++;
1863 }
1864
1865 /* Set the last buffer to wrap.
1866 */
1867 bdp--;
1868 bdp->cbd_sc |= BD_SC_WRAP;
1869
1870 /* ...and the same for transmmit.
1871 */
1872 bdp = fep->tx_bd_base;
1873 for (i=0; i<TX_RING_SIZE; i++) {
1874
1875 /* Initialize the BD for every fragment in the page.
1876 */
1877 bdp->cbd_sc = 0;
1878 bdp->cbd_bufaddr = 0;
1879 bdp++;
1880 }
1881
1882 /* Set the last buffer to wrap.
1883 */
1884 bdp--;
1885 bdp->cbd_sc |= BD_SC_WRAP;
1886
1887 /* Enable MII mode.
1888 */
1889 if (duplex) {
1890 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */
1891 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */
1892 }
1893 else {
1894 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
1895 fecp->fec_x_cntrl = 0;
1896 }
1897 fep->full_duplex = duplex;
1898
1899 /* Enable big endian and don't care about SDMA FC.
1900 */
1901 fecp->fec_fun_code = 0x78000000;
1902
1903#ifdef CONFIG_USE_MDIO
1904 /* Set MII speed.
1905 */
1906 fecp->fec_mii_speed = fep->phy_speed;
1907#endif /* CONFIG_USE_MDIO */
1908
1909 /* Clear any outstanding interrupt.
1910 */
1911 fecp->fec_ievent = 0xffc0;
1912
1913 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1914
1915 /* Enable interrupts we wish to service.
1916 */
1917 fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB |
1918 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII );
1919
1920 /* And last, enable the transmit and receive processing.
1921 */
1922 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
1923 fecp->fec_r_des_active = 0x01000000;
1924}
1925
1926static void
1927fec_stop(struct net_device *dev)
1928{
1929 volatile immap_t *immap;
1930 volatile fec_t *fecp;
1931 struct fec_enet_private *fep;
1932 int i;
1933
1934 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1935
1936 fecp = &(immap->im_cpm.cp_fec);
1937
1938 if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0)
1939 return; /* already down */
1940
1941 fep = dev->priv;
1942
1943
1944 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
1945
1946 for (i = 0;
1947 ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY);
1948 ++i) {
1949 udelay(1);
1950 }
1951 if (i == FEC_RESET_DELAY) {
1952 printk ("FEC timeout on graceful transmit stop\n");
1953 }
1954
1955 /* Clear outstanding MII command interrupts.
1956 */
1957 fecp->fec_ievent = FEC_ENET_MII;
1958
1959 /* Enable MII command finished interrupt
1960 */
1961 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1962 fecp->fec_imask = FEC_ENET_MII;
1963
1964#ifdef CONFIG_USE_MDIO
1965 /* Set MII speed.
1966 */
1967 fecp->fec_mii_speed = fep->phy_speed;
1968#endif /* CONFIG_USE_MDIO */
1969
1970 /* Disable FEC
1971 */
1972 fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN);
1973}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 13:33:10 -0500