diff options
author | Simon Arlott <simon@fire.lp0.eu> | 2007-05-11 15:42:54 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2007-05-11 21:32:49 -0400 |
commit | a8de5ce9895367191df9b30804a0c67cfcc9f27a (patch) | |
tree | 8f99af81affca30d868bd9ee7c043639b905c4f8 /arch/ppc/4xx_io | |
parent | dab4d7984ee61c8eb25569b12e7a996f5aaef2ba (diff) |
[POWERPC] Spelling fixes: arch/ppc/
Spelling fixes in arch/ppc/.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/4xx_io')
-rw-r--r-- | arch/ppc/4xx_io/serial_sicc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c index e35483961b90..efa0a56e230b 100644 --- a/arch/ppc/4xx_io/serial_sicc.c +++ b/arch/ppc/4xx_io/serial_sicc.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Based on drivers/char/serial_amba.c, by ARM Ltd. | 4 | * Based on drivers/char/serial_amba.c, by ARM Ltd. |
5 | * | 5 | * |
6 | * Copyright 2001 IBM Crop. | 6 | * Copyright 2001 IBM Corp. |
7 | * Author: IBM China Research Lab | 7 | * Author: IBM China Research Lab |
8 | * Yudong Yang <yangyud@cn.ibm.com> | 8 | * Yudong Yang <yangyud@cn.ibm.com> |
9 | * Yi Ge <geyi@cn.ibm.com> | 9 | * Yi Ge <geyi@cn.ibm.com> |
@@ -155,16 +155,16 @@ | |||
155 | 155 | ||
156 | /* serial port transmit command register */ | 156 | /* serial port transmit command register */ |
157 | 157 | ||
158 | #define _TxCR_ET_MASK 0x80 /* transmiter enable mask */ | 158 | #define _TxCR_ET_MASK 0x80 /* transmitter enable mask */ |
159 | #define _TxCR_DME_MASK 0x60 /* dma mode mask */ | 159 | #define _TxCR_DME_MASK 0x60 /* dma mode mask */ |
160 | #define _TxCR_TIE_MASK 0x10 /* empty interrupt enable mask */ | 160 | #define _TxCR_TIE_MASK 0x10 /* empty interrupt enable mask */ |
161 | #define _TxCR_EIE_MASK 0x08 /* error interrupt enable mask */ | 161 | #define _TxCR_EIE_MASK 0x08 /* error interrupt enable mask */ |
162 | #define _TxCR_SPE_MASK 0x04 /* stop/pause mask */ | 162 | #define _TxCR_SPE_MASK 0x04 /* stop/pause mask */ |
163 | #define _TxCR_TB_MASK 0x02 /* transmit break mask */ | 163 | #define _TxCR_TB_MASK 0x02 /* transmit break mask */ |
164 | 164 | ||
165 | #define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmiter enabled */ | 165 | #define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmitter enabled */ |
166 | #define _TxCR_DME_DISABLE 0x00 /* transmiter disabled, TBR intr disabled */ | 166 | #define _TxCR_DME_DISABLE 0x00 /* transmitter disabled, TBR intr disabled */ |
167 | #define _TxCR_DME_TBR 0x20 /* transmiter disabled, TBR intr enabled */ | 167 | #define _TxCR_DME_TBR 0x20 /* transmitter disabled, TBR intr enabled */ |
168 | #define _TxCR_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */ | 168 | #define _TxCR_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */ |
169 | #define _TxCR_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */ | 169 | #define _TxCR_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */ |
170 | 170 | ||