Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (185 commits) powerpc: fix compile error with 85xx/p1010rdb.c powerpc: fix compile error with 85xx/p1023_rds.c powerpc/fsl: add MSI support for the Freescale hypervisor arch/powerpc/sysdev/fsl_rmu.c: introduce missing kfree powerpc/fsl: Add support for Integrated Flash Controller powerpc/fsl: update compatiable on fsl 16550 uart nodes powerpc/85xx: fix PCI and localbus properties in p1022ds.dts powerpc/85xx: re-enable ePAPR byte channel driver in corenet32_smp_defconfig powerpc/fsl: Update defconfigs to enable some standard FSL HW features powerpc: Add TBI PHY node to first MDIO bus sbc834x: put full compat string in board match check powerpc/fsl-pci: Allow 64-bit PCIe devices to DMA to any memory address powerpc: Fix unpaired probe_hcall_entry and probe_hcall_exit offb: Fix setting of the pseudo-palette for >8bpp offb: Add palette hack for qemu "standard vga" framebuffer offb: Fix bug in calculating requested vram size powerpc/boot: Change the WARN to INFO for boot wrapper overlap message powerpc/44x: Fix build error on currituck platform powerpc/boot: Change the load address for the wrapper to fit the kernel powerpc/44x: Enable CRASH_DUMP for 440x ... Fix up a trivial conflict in arch/powerpc/include/asm/cputime.h due to the additional sparse-checking code for cputime_t.
author: Linus Torvalds <torvalds@linux-foundation.org> 2012-01-06 20:58:22 -0500
committer: Linus Torvalds <torvalds@linux-foundation.org> 2012-01-06 20:58:22 -0500
commit: e4e88f31bcb5f05f24b9ae518d4ecb44e1a7774d (patch)
tree: 9eef6998f5bbd1a2c999011d9e0151f00c6e7297 /arch/powerpc
parent: 9753dfe19a85e7e45a34a56f4cb2048bb4f50e27 (diff)
parent: ef88e3911c0e0301e73fa3b3b2567aabdbe17cc4 (diff)
377 files changed, 21299 insertions, 15937 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index ead0bc68439d..692ac7588e20 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -87,6 +87,10 @@ config ARCH_HAS_ILOG2_U64
        bool
        default y if 64BIT
+config ARCH_HAS_CPU_IDLE_WAIT
+        bool
+        default y
 config GENERIC_HWEIGHT
        bool
        default y
@@ -133,6 +137,7 @@ config PPC
        select IRQ_PER_CPU
        select GENERIC_IRQ_SHOW
        select GENERIC_IRQ_SHOW_LEVEL
+        select IRQ_FORCED_THREADING
        select HAVE_RCU_TABLE_FREE if SMP
        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_BPF_JIT if (PPC64 && NET)
@@ -363,8 +368,9 @@ config KEXEC
 config CRASH_DUMP
        bool "Build a kdump crash kernel"
-        depends on PPC64 || 6xx || FSL_BOOKE
+        depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP && !PPC_47x)
-        select RELOCATABLE if PPC64 || FSL_BOOKE
+        select RELOCATABLE if PPC64 || 44x
+        select DYNAMIC_MEMSTART if FSL_BOOKE
        help
          Build a kernel suitable for use as a kdump capture kernel.
          The same kernel binary can be used as production kernel and dump
@@ -685,6 +691,10 @@ config FSL_LBC
          controller.  Also contains some common code used by
          drivers for specific local bus peripherals.
+config FSL_IFC
+        bool
+        depends on FSL_SOC
 config FSL_GTM
        bool
        depends on PPC_83xx || QUICC_ENGINE || CPM2
@@ -770,6 +780,10 @@ source "drivers/rapidio/Kconfig"
 endmenu
+config NONSTATIC_KERNEL
+        bool
+        default n
 menu "Advanced setup"
        depends on PPC32
@@ -819,13 +833,32 @@ config LOWMEM_CAM_NUM
        int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
        default 3
+config DYNAMIC_MEMSTART
+        bool "Enable page aligned dynamic load address for kernel (EXPERIMENTAL)"
+        depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || 44x)
+        select NONSTATIC_KERNEL
+        help
+          This option enables the kernel to be loaded at any page aligned
+          physical address. The kernel creates a mapping from KERNELBASE to 
+          the address where the kernel is loaded. The page size here implies
+          the TLB page size of the mapping for kernel on the particular platform.
+          Please refer to the init code for finding the TLB page size.
+          DYNAMIC_MEMSTART is an easy way of implementing pseudo-RELOCATABLE
+          kernel image, where the only restriction is the page aligned kernel
+          load address. When this option is enabled, the compile time physical 
+          address CONFIG_PHYSICAL_START is ignored.
+          This option is overridden by CONFIG_RELOCATABLE
 config RELOCATABLE
        bool "Build a relocatable kernel (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x)
+        depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && 44x
+        select NONSTATIC_KERNEL
        help
          This builds a kernel image that is capable of running at the
-          location the kernel is loaded at (some alignment restrictions may
+          location the kernel is loaded at, without any alignment restrictions.
-          exist).
+          This feature is a superset of DYNAMIC_MEMSTART and hence overrides it.
          One use is for the kexec on panic case where the recovery kernel
          must live at a different physical address than the primary
@@ -835,7 +868,11 @@ config RELOCATABLE
          it has been loaded at and the compile time physical addresses
          CONFIG_PHYSICAL_START is ignored.  However CONFIG_PHYSICAL_START
          setting can still be useful to bootwrappers that need to know the
-          load location of the kernel (eg. u-boot/mkimage).
+          load address of the kernel (eg. u-boot/mkimage).
+config RELOCATABLE_PPC32
+        def_bool y
+        depends on PPC32 && RELOCATABLE
 config PAGE_OFFSET_BOOL
        bool "Set custom page offset address"
@@ -865,7 +902,7 @@ config KERNEL_START_BOOL
 config KERNEL_START
        hex "Virtual address of kernel base" if KERNEL_START_BOOL
        default PAGE_OFFSET if PAGE_OFFSET_BOOL
-        default "0xc2000000" if CRASH_DUMP && !RELOCATABLE
+        default "0xc2000000" if CRASH_DUMP && !NONSTATIC_KERNEL
        default "0xc0000000"
 config PHYSICAL_START_BOOL
@@ -878,7 +915,7 @@ config PHYSICAL_START_BOOL
 config PHYSICAL_START
        hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
-        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !RELOCATABLE
+        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !NONSTATIC_KERNEL
        default "0x00000000"
 config PHYSICAL_ALIGN
@@ -924,6 +961,7 @@ endmenu
 if PPC64
 config RELOCATABLE
        bool "Build a relocatable kernel"
+        select NONSTATIC_KERNEL
        help
          This builds a kernel image that is capable of running anywhere
          in the RMA (real memory area) at any 16k-aligned base address.
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 1b8a9c905cf7..4ccb2a009f74 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -336,4 +336,16 @@ config PPC_EARLY_DEBUG_CPM_ADDR
          platform probing is done, all platforms selected must
          share the same address.
+config STRICT_DEVMEM
+        def_bool y
+        prompt "Filter access to /dev/mem"
+        help
+          This option restricts access to /dev/mem.  If this option is
+          disabled, you allow userspace access to all memory, including
+          kernel and userspace memory. Accidental memory access is likely
+          to be disastrous.
+          Memory access is required for experts who want to debug the kernel.
+          If you are unsure, say Y.
 endmenu
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 70ba0c0a1223..b8b105c01c64 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -63,9 +63,9 @@ override CC	+= -m$(CONFIG_WORD_SIZE)
 override AR     := GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR)
 endif
-LDFLAGS_vmlinux-yy := -Bstatic
+LDFLAGS_vmlinux-y := -Bstatic
-LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie
+LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) := -pie
-LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-yy)
+LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y)
 CFLAGS-$(CONFIG_PPC64)  := -mminimal-toc -mtraceback=no -mcall-aixdesc
 CFLAGS-$(CONFIG_PPC32)  := -ffixed-r2 -mmultiple
@@ -131,8 +131,7 @@ KBUILD_CFLAGS		+= -mno-sched-epilog
 endif
 cpu-as-$(CONFIG_4xx)            += -Wa,-m405
-cpu-as-$(CONFIG_6xx)            += -Wa,-maltivec
+cpu-as-$(CONFIG_ALTIVEC)        += -Wa,-maltivec
-cpu-as-$(CONFIG_POWER4)         += -Wa,-maltivec
 cpu-as-$(CONFIG_E500)           += -Wa,-me500
 cpu-as-$(CONFIG_E200)           += -Wa,-me200
@@ -166,7 +165,7 @@ all: zImage
 # With make 3.82 we cannot mix normal and wildcard targets
 BOOT_TARGETS1 := zImage zImage.initrd uImage
-BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.%
+BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
 PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 72ee8c1fba48..15986e70799c 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,7 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -79,7 +80,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
                cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
                virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
                cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
-                gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
+                gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
+                treeboot-currituck.c
 src-boot := $(src-wlib) $(src-plat) empty.c
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -199,6 +201,7 @@ image-$(CONFIG_EP405)			+= dtbImage.ep405
 image-$(CONFIG_HOTFOOT)                 += cuImage.hotfoot
 image-$(CONFIG_WALNUT)                  += treeImage.walnut
 image-$(CONFIG_ACADIA)                  += cuImage.acadia
+image-$(CONFIG_OBS600)                  += uImage.obs600
 # Board ports in arch/powerpc/platform/44x/Kconfig
 image-$(CONFIG_EBONY)                   += treeImage.ebony cuImage.ebony
@@ -212,6 +215,7 @@ image-$(CONFIG_WARP)			+= cuImage.warp
 image-$(CONFIG_YOSEMITE)                += cuImage.yosemite
 image-$(CONFIG_ISS4xx)                  += treeImage.iss4xx \
                                           treeImage.iss4xx-mpic
+image-$(CONFIG_CURRITUCK)                       += treeImage.currituck
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_MPC86XADS)               += cuImage.mpc866ads
@@ -316,6 +320,12 @@ $(obj)/zImage.iseries: vmlinux
 $(obj)/uImage: vmlinux $(wrapperbits)
        $(call if_changed,wrap,uboot)
+$(obj)/uImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
+$(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
 $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
        $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 645a7c964e5f..cc73f7a95e26 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -9,6 +9,12 @@
        })
 #define mtdcr(rn, val) \
        asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
+#define mfdcrx(rn) \
+        ({      \
+                unsigned long rval; \
+                asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
+                rval; \
+        })
 /* 440GP/440GX SDRAM controller DCRs */
 #define DCRN_SDRAM0_CFGADDR                             0x010
diff --git a/arch/powerpc/boot/div64.S b/arch/powerpc/boot/div64.S
index d271ab542673..bbcb8a4cc121 100644
--- a/arch/powerpc/boot/div64.S
+++ b/arch/powerpc/boot/div64.S
@@ -57,3 +57,55 @@ __div64_32:
        stw     r8,4(r3)
        mr      r3,r6           # return the remainder in r3
        blr
+/*
+ * Extended precision shifts.
+ *
+ * Updated to be valid for shift counts from 0 to 63 inclusive.
+ * -- Gabriel
+ *
+ * R3/R4 has 64 bit value
+ * R5    has shift count
+ * result in R3/R4
+ *
+ *  ashrdi3: arithmetic right shift (sign propagation)  
+ *  lshrdi3: logical right shift
+ *  ashldi3: left shift
+ */
+        .globl __ashrdi3
+__ashrdi3:
+        subfic  r6,r5,32
+        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
+        rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
+        sraw    r7,r3,r7        # t2 = MSW >> (count-32)
+        or      r4,r4,r6        # LSW |= t1
+        slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
+        sraw    r3,r3,r5        # MSW = MSW >> count
+        or      r4,r4,r7        # LSW |= t2
+        blr
+        .globl __ashldi3
+__ashldi3:
+        subfic  r6,r5,32
+        slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
+        slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
+        or      r3,r3,r6        # MSW |= t1
+        slw     r4,r4,r5        # LSW = LSW << count
+        or      r3,r3,r7        # MSW |= t2
+        blr
+        .globl __lshrdi3
+__lshrdi3:
+        subfic  r6,r5,32
+        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
+        srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
+        or      r4,r4,r6        # LSW |= t1
+        srw     r3,r3,r5        # MSW = MSW >> count
+        or      r4,r4,r7        # LSW |= t2
+        blr
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 261d10c4534b..227290db866d 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -256,7 +256,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <400000000>;
                        interrupts = <9 0x8>;
@@ -266,7 +266,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <400000000>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
new file mode 100644
index 000000000000..b801dd06e573
--- /dev/null
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -0,0 +1,237 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright © 2011 Tony Breeds IBM Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/memreserve/ 0x01f00000 0x00100000;     // spin table
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        model = "ibm,currituck";
+        compatible = "ibm,currituck";
+        dcr-parent = <&{/cpus/cpu@0}>;
+        aliases {
+                serial0 = &UART0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <0>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "ok";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <1>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x01f00000>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
+        };
+        MPIC: interrupt-controller {
+                compatible = "chrp,open-pic";
+                interrupt-controller;
+                dcr-reg = <0xffc00000 0x00040000>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+        plb {
+                compatible = "ibm,plb6";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                clock-frequency = <200000000>; // 200Mhz
+                POB0: opb {
+                        compatible = "ibm,opb-4xx", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* Wish there was a nicer way of specifying a full
+                         * 32-bit range
+                         */
+                        ranges = <0x00000000 0x00000200 0x00000000 0x80000000
+                                  0x80000000 0x00000200 0x80000000 0x80000000>;
+                        clock-frequency = <100000000>;
+                        UART0: serial@10000000 {
+                                device_type = "serial";
+                                compatible = "ns16750", "ns16550";
+                                reg = <0x10000000 0x00000008>;
+                                virtual-reg = <0xe1000000>;
+                                clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
+                                current-speed = <115200>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <34 2>;
+                        };
+                        IIC0: i2c@00000000 {
+                                compatible = "ibm,iic-currituck", "ibm,iic";
+                                reg = <0x0 0x00000014>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <79 2>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80", "m41st85";
+                                        reg = <0x68>;
+                                };
+                        };
+                };
+                PCIE0: pciex@10100000000 {              // 4xGBIF1
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x0>; /* port number */
+                        reg = <0x00000101 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000100 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x80 0x20>;
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000140 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
+                };
+                PCIE1: pciex@30100000000 {              // 4xGBIF0
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x1>; /* port number */
+                        reg = <0x00000301 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000300 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x60 0x20>;
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000340 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
+                };
+                PCIE2: pciex@38100000000 {              // 2xGBIF0
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x2>; /* port number */
+                        reg = <0x00000381 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000380 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0xA0 0x20>;
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x000003C0 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
+                };
+        };
+        chosen {
+                linux,stdout-path = &UART0;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
new file mode 100644
index 000000000000..89af62637707
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -0,0 +1,248 @@
+/*
+ * MPC8536 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x8000 */
+&pci0 {
+        compatible = "fsl,mpc8540-pci";
+        device_type = "pci";
+        interrupts = <24 0x2 0 0>;
+        bus-range = <0 0xff>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <25 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <25 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci2 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xb000 */
+&pci3 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <27 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <27 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8536-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8536-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8536-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+        /* mark compat w/8572 to get some erratum treatment */
+        gpio-controller@f000 {
+                compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
+        };
+        sata@18000 {
+                compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                reg = <0x18000 0x1000>;
+                cell-index = <1>;
+                interrupts = <74 0x2 0 0>;
+        };
+        sata@19000 {
+                compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                reg = <0x19000 0x1000>;
+                cell-index = <2>;
+                interrupts = <41 0x2 0 0>;
+        };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8536-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x80000>; // L2, 512K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-timer-0.dtsi"
+        usb@22000 {
+                compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                reg = <0x22000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <28 0x2 0 0>;
+        };
+        usb@23000 {
+                compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                reg = <0x23000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <46 0x2 0 0>;
+        };
+        ptp_clock@24e00 {
+                interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
+        };
+/include/ "pq3-etsec1-2.dtsi"
+        ethernet@26000 {
+                cell-index = <1>;
+        };
+        usb@2b000 {
+                compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
+                reg = <0x2b000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <60 0x2 0 0>;
+        };
+/include/ "pq3-esdhc-0.dtsi"
+/include/ "pq3-sec3.0-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,mpc8536-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
new file mode 100644
index 000000000000..7de45a784df6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * MPC8536 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8536";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8536@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
new file mode 100644
index 000000000000..b68eb119faef
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
@@ -0,0 +1,191 @@
+/*
+ * MPC8544 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x8000 */
+&pci0 {
+        compatible = "fsl,mpc8540-pci";
+        device_type = "pci";
+        interrupts = <24 0x2 0 0>;
+        bus-range = <0 0xff>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <25 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <25 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci2 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xb000 */
+&pci3 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <27 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <27 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8544-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <10>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8544-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8544-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2, 256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
+        ethernet@26000 {
+                cell-index = <1>;
+        };
+/include/ "pq3-sec2.1-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,mpc8544-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
new file mode 100644
index 000000000000..8777f9239d9e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
@@ -0,0 +1,63 @@
+/*
+ * MPC8544 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8544";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8544@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
new file mode 100644
index 000000000000..9d8023a69d7d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -0,0 +1,143 @@
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x8000 */
+&pci0 {
+        compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+        device_type = "pci";
+        interrupts = <24 0x2 0 0>;
+        bus-range = <0 0xff>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,mpc8540-pci";
+        device_type = "pci";
+        interrupts = <25 0x2 0 0>;
+        bus-range = <0 0xff>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+};
+/* controller at 0xa000 */
+&pci2 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8548-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <10>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8548-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8548-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x80000>; // L2, 512K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
+/include/ "pq3-etsec1-3.dtsi"
+/include/ "pq3-sec2.1-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,mpc8548-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
new file mode 100644
index 000000000000..289f1218d755
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -0,0 +1,62 @@
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8548";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8548@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
new file mode 100644
index 000000000000..64e7075a9cd4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
@@ -0,0 +1,270 @@
+/*
+ * MPC8568 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
+        interrupts = <19 2 0 0>;
+        sleep = <&pmc 0x08000000>;
+};
+/* controller at 0x8000 */
+&pci0 {
+        compatible = "fsl,mpc8540-pci";
+        device_type = "pci";
+        interrupts = <24 0x2 0 0>;
+        bus-range = <0 0xff>;
+        #interrupt-cells = <1>;
+        #size-cells = <2>;
+        #address-cells = <3>;
+        sleep = <&pmc 0x80000000>;
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        sleep = <&pmc 0x20000000>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <48 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,srio-rmu-handle = <&rmu>;
+        sleep = <&pmc 0x00080000>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8568-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <10>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8568-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8568-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+        i2c-sleep-nexus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                sleep = <&pmc 0x00000004>;
+                ranges;
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+        };
+        duart-sleep-nexus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                sleep = <&pmc 0x00000002>;
+                ranges;
+/include/ "pq3-duart-0.dtsi"
+        };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8568-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x80000>; // L2, 512K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+        dma@21300 {
+                sleep = <&pmc 0x00000400>;
+        };
+/include/ "pq3-etsec1-0.dtsi"
+        ethernet@24000 {
+                sleep = <&pmc 0x00000080>;
+        };
+/include/ "pq3-etsec1-1.dtsi"
+        ethernet@25000 {
+                sleep = <&pmc 0x00000040>;
+        };
+        par_io@e0100 {
+                reg = <0xe0100 0x100>;
+                device_type = "par_io";
+        };
+/include/ "pq3-sec2.1-0.dtsi"
+        crypto@30000 {
+                sleep = <&pmc 0x01000000>;
+        };
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-rmu-0.dtsi"
+        rmu@d3000 {
+                sleep = <&pmc 0x00040000>;
+        };
+        global-utilities@e0000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
+                reg = <0xe0000 0x1000>;
+                ranges = <0 0xe0000 0x1000>;
+                fsl,has-rstcr;
+                pmc: power@70 {
+                        compatible = "fsl,mpc8568-pmc",
+                                     "fsl,mpc8548-pmc";
+                        reg = <0x70 0x20>;
+                };
+        };
+};
+&qe {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "qe";
+        compatible = "fsl,qe";
+        sleep = <&pmc 0x00000800>;
+        brg-frequency = <0>;
+        bus-frequency = <396000000>;
+        fsl,qe-num-riscs = <2>;
+        fsl,qe-num-snums = <28>;
+        qeic: interrupt-controller@80 {
+                interrupt-controller;
+                compatible = "fsl,qe-ic";
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                reg = <0x80 0x80>;
+                interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
+                interrupt-parent = <&mpic>;
+        };
+        spi@4c0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,spi";
+                reg = <0x4c0 0x40>;
+                cell-index = <0>;
+                interrupts = <2>;
+                interrupt-parent = <&qeic>;
+        };
+        spi@500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cell-index = <1>;
+                compatible = "fsl,spi";
+                reg = <0x500 0x40>;
+                interrupts = <1>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@2000 {
+                cell-index = <1>;
+                reg = <0x2000 0x200>;
+                interrupts = <32>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@3000 {
+                cell-index = <2>;
+                reg = <0x3000 0x200>;
+                interrupts = <33>;
+                interrupt-parent = <&qeic>;
+        };
+        muram@10000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                ranges = <0x0 0x10000 0x10000>;
+                data-only@0 {
+                        compatible = "fsl,qe-muram-data",
+                                     "fsl,cpm-muram-data";
+                        reg = <0x0 0x10000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
new file mode 100644
index 000000000000..eacd62c5fe6c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
@@ -0,0 +1,65 @@
+/*
+ * MPC8568 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8568";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8568@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                        sleep = <&pmc 0x00008000        // core
+                                 &pmc 0x00004000>;      // timebase
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
new file mode 100644
index 000000000000..3e6346a4a183
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
@@ -0,0 +1,304 @@
+/*
+ * MPC8569 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+        sleep = <&pmc 0x08000000>;
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        sleep = <&pmc 0x20000000>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <48 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,srio-rmu-handle = <&rmu>;
+        sleep = <&pmc 0x00080000>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8569-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <10>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8569-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8569-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+        i2c-sleep-nexus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                sleep = <&pmc 0x00000004>;
+                ranges;
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+        };
+        duart-sleep-nexus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                sleep = <&pmc 0x00000002>;
+                ranges;
+/include/ "pq3-duart-0.dtsi"
+        };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8569-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x80000>; // L2, 512K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                sleep = <&pmc 0x00200000>;
+        };
+        par_io@e0100 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xe0100 0x100>;
+                ranges = <0x0 0xe0100 0x100>;
+                device_type = "par_io";
+        };
+/include/ "pq3-sec3.1-0.dtsi"
+        crypto@30000 {
+                sleep = <&pmc 0x01000000>;
+        };
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-rmu-0.dtsi"
+        rmu@d3000 {
+                sleep = <&pmc 0x00040000>;
+        };
+        global-utilities@e0000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
+                reg = <0xe0000 0x1000>;
+                ranges = <0 0xe0000 0x1000>;
+                fsl,has-rstcr;
+                pmc: power@70 {
+                        compatible = "fsl,mpc8569-pmc",
+                                     "fsl,mpc8548-pmc";
+                        reg = <0x70 0x20>;
+                };
+        };
+};
+&qe {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "qe";
+        compatible = "fsl,qe";
+        sleep = <&pmc 0x00000800>;
+        brg-frequency = <0>;
+        bus-frequency = <0>;
+        fsl,qe-num-riscs = <4>;
+        fsl,qe-num-snums = <46>;
+        qeic: interrupt-controller@80 {
+                interrupt-controller;
+                compatible = "fsl,qe-ic";
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                reg = <0x80 0x80>;
+                interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
+                interrupt-parent = <&mpic>;
+        };
+        timer@440 {
+                compatible = "fsl,mpc8569-qe-gtm",
+                             "fsl,qe-gtm", "fsl,gtm";
+                reg = <0x440 0x40>;
+                interrupts = <12 13 14 15>;
+                interrupt-parent = <&qeic>;
+                /* Filled in by U-Boot */
+                clock-frequency = <0>;
+        };
+        spi@4c0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
+                reg = <0x4c0 0x40>;
+                cell-index = <0>;
+                interrupts = <2>;
+                interrupt-parent = <&qeic>;
+        };
+        spi@500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cell-index = <1>;
+                compatible = "fsl,spi";
+                reg = <0x500 0x40>;
+                interrupts = <1>;
+                interrupt-parent = <&qeic>;
+        };
+        usb@6c0 {
+                compatible = "fsl,mpc8569-qe-usb",
+                             "fsl,mpc8323-qe-usb";
+                reg = <0x6c0 0x40 0x8b00 0x100>;
+                interrupts = <11>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@2000 {
+                cell-index = <1>;
+                reg = <0x2000 0x200>;
+                interrupts = <32>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@2200 {
+                cell-index = <3>;
+                reg = <0x2200 0x200>;
+                interrupts = <34>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@3000 {
+                cell-index = <2>;
+                reg = <0x3000 0x200>;
+                interrupts = <33>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@3200 {
+                cell-index = <4>;
+                reg = <0x3200 0x200>;
+                interrupts = <35>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@3400 {
+                cell-index = <6>;
+                reg = <0x3400 0x200>;
+                interrupts = <41>;
+                interrupt-parent = <&qeic>;
+        };
+        ucc@3600 {
+                cell-index = <8>;
+                reg = <0x3600 0x200>;
+                interrupts = <43>;
+                interrupt-parent = <&qeic>;
+        };
+        muram@10000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                ranges = <0x0 0x10000 0x20000>;
+                data-only@0 {
+                        compatible = "fsl,qe-muram-data",
+                                     "fsl,cpm-muram-data";
+                        reg = <0x0 0x20000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
new file mode 100644
index 000000000000..b07064d11930
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -0,0 +1,64 @@
+/*
+ * MPC8569 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8569";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                pci1 = &pci1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8569@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                        sleep = <&pmc 0x00008000        // core
+                                 &pmc 0x00004000>;      // timebase
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
new file mode 100644
index 000000000000..d44e25a48734
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
@@ -0,0 +1,196 @@
+/*
+ * MPC8572 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x8000 */
+&pci0 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <24 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <24 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <25 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <25 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci2 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,mpc8572-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,mpc8572-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+        memory-controller@6000 {
+                compatible = "fsl,mpc8572-memory-controller";
+                reg = <0x6000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-dma-1.dtsi"
+/include/ "pq3-gpio-0.dtsi"
+        gpio-controller@f000 {
+                compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
+        };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,mpc8572-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x100000>; // L2,1M
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-timer-0.dtsi"
+        ptp_clock@24e00 {
+                interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
+        };
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
+/include/ "pq3-etsec1-3.dtsi"
+/include/ "pq3-sec3.0-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,mpc8572-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
new file mode 100644
index 000000000000..ca188326c2ca
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
@@ -0,0 +1,70 @@
+/*
+ * MPC8572 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,MPC8572";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8572@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,8572@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
new file mode 100644
index 000000000000..bd9e163c764b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -0,0 +1,198 @@
+/*
+ * P1010/P1014 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        interrupts = <16 2 0 0 19 2 0 0>;
+};
+/* controller at 0x9000 */
+&pci0 {
+        compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p1010-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p1010-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p1010-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi0: spi@7000 {
+                fsl,espi-num-chipselects = <1>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+/include/ "pq3-sata2-0.dtsi"
+/include/ "pq3-sata2-1.dtsi"
+        can0: can@1c000 {
+                compatible = "fsl,p1010-flexcan";
+                reg = <0x1c000 0x1000>;
+                interrupts = <48 0x2 0 0>;
+        };
+        can1: can@1d000 {
+                compatible = "fsl,p1010-flexcan";
+                reg = <0x1d000 0x1000>;
+                interrupts = <61 0x2 0 0>;
+        };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p1010-l2-cache-controller",
+                                "fsl,p1014-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                fsl,sdhci-auto-cmd12;
+        };
+/include/ "pq3-sec4.4-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
+        enet0: ethernet@b0000 {
+                queue-group@b0000 {
+                        fsl,rx-bit-map = <0xff>;
+                        fsl,tx-bit-map = <0xff>;
+                };
+        };
+/include/ "pq3-etsec2-1.dtsi"
+        enet1: ethernet@b1000 {
+                queue-group@b1000 {
+                        fsl,rx-bit-map = <0xff>;
+                        fsl,tx-bit-map = <0xff>;
+                };
+        };
+/include/ "pq3-etsec2-2.dtsi"
+        enet2: ethernet@b2000 {
+                queue-group@b2000 {
+                        fsl,rx-bit-map = <0xff>;
+                        fsl,tx-bit-map = <0xff>;
+                };
+        };
+        global-utilities@e0000 {
+                compatible = "fsl,p1010-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
new file mode 100644
index 000000000000..7354a8f90ea5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
@@ -0,0 +1,64 @@
+/*
+ * P1010/P1014 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P1010";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                can0 = &can0;
+                can1 = &can1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P1010@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
new file mode 100644
index 000000000000..fc924c5ffebe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -0,0 +1,174 @@
+/*
+ * P1020/P1011 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x9000 */
+&pci0 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p1020-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p1020-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p1020-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p1020-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+/include/ "pq3-usb2-dr-1.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+/include/ "pq3-sec3.3-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
+        enet0: enet0_grp2: ethernet@b0000 {
+        };
+/include/ "pq3-etsec2-1.dtsi"
+        enet1: enet1_grp2: ethernet@b1000 {
+        };
+/include/ "pq3-etsec2-2.dtsi"
+        enet2: enet2_grp2: ethernet@b2000 {
+        };
+        global-utilities@e0000 {
+                compatible = "fsl,p1020-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
new file mode 100644
index 000000000000..6f0376e554eb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -0,0 +1,68 @@
+/*
+ * P1020/P1011 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P1020";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P1020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P1020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
new file mode 100644
index 000000000000..38ba54d1e32e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -0,0 +1,225 @@
+/*
+ * P1021/P1012 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x9000 */
+&pci0 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p1021-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p1021-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p1021-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p1021-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+/include/ "pq3-sec3.3-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
+        enet0: enet0_grp2: ethernet@b0000 {
+        };
+/include/ "pq3-etsec2-1.dtsi"
+        enet1: enet1_grp2: ethernet@b1000 {
+        };
+/include/ "pq3-etsec2-2.dtsi"
+        enet2: enet2_grp2: ethernet@b2000 {
+        };
+        global-utilities@e0000 {
+                compatible = "fsl,p1021-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
+&qe {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "qe";
+        compatible = "fsl,qe";
+        fsl,qe-num-riscs = <1>;
+        fsl,qe-num-snums = <28>;
+        qeic: interrupt-controller@80 {
+                interrupt-controller;
+                compatible = "fsl,qe-ic";
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                reg = <0x80 0x80>;
+                interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
+        };
+        ucc@2000 {
+                cell-index = <1>;
+                reg = <0x2000 0x200>;
+                interrupts = <32>;
+                interrupt-parent = <&qeic>;
+        };
+        mdio@2120 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x2120 0x18>;
+                compatible = "fsl,ucc-mdio";
+        };
+        ucc@2400 {
+                cell-index = <5>;
+                reg = <0x2400 0x200>;
+                interrupts = <40>;
+                interrupt-parent = <&qeic>;
+        };
+        muram@10000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                ranges = <0x0 0x10000 0x6000>;
+                data-only@0 {
+                        compatible = "fsl,qe-muram-data",
+                        "fsl,cpm-muram-data";
+                        reg = <0x0 0x6000>;
+                };
+        };
+};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
new file mode 100644
index 000000000000..4abd54bc3308
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -0,0 +1,68 @@
+/*
+ * P1021/P1012 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P1021";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P1021@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P1021@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
new file mode 100644
index 000000000000..16239b199d0a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -0,0 +1,235 @@
+/*
+ * P1022/P1013 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0x9000 */
+&pci0 {
+        compatible = "fsl,p1022-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xa000 */
+&pci1 {
+        compatible = "fsl,p1022-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0xb000 */
+&pci2 {
+        compatible = "fsl,p1022-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p1022-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p1022-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p1022-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-dma-1.dtsi"
+        dma@c300 {
+                dma00: dma-channel@0 {
+                        compatible = "fsl,ssi-dma-channel";
+                };
+                dma01: dma-channel@80 {
+                        compatible = "fsl,ssi-dma-channel";
+                };
+        };
+/include/ "pq3-gpio-0.dtsi"
+        display@10000 {
+                compatible = "fsl,diu", "fsl,p1022-diu";
+                reg = <0x10000 1000>;
+                interrupts = <64 2 0 0>;
+        };
+        ssi@15000 {
+                compatible = "fsl,mpc8610-ssi";
+                cell-index = <0>;
+                reg = <0x15000 0x100>;
+                interrupts = <75 2 0 0>;
+                fsl,playback-dma = <&dma00>;
+                fsl,capture-dma = <&dma01>;
+                fsl,fifo-depth = <15>;
+        };
+/include/ "pq3-sata2-0.dtsi"
+/include/ "pq3-sata2-1.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p1022-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+/include/ "pq3-usb2-dr-1.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                fsl,sdhci-auto-cmd12;
+        };
+/include/ "pq3-sec3.3-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
+        enet0: enet0_grp2: ethernet@b0000 {
+        };
+/include/ "pq3-etsec2-1.dtsi"
+        enet1: enet1_grp2: ethernet@b1000 {
+        };
+        global-utilities@e0000 {
+                compatible = "fsl,p1022-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+        power@e0070{
+                compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+                reg = <0xe0070 0x20>;
+        };
+};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
new file mode 100644
index 000000000000..e930f4f7ca89
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -0,0 +1,68 @@
+/*
+ * P1022/P1013 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P1022";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P1022@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P1022@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
new file mode 100644
index 000000000000..b06bb4cc1fe8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -0,0 +1,224 @@
+/*
+ * P1023/P1017 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0xa000 */
+&pci0 {
+        compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+        };
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+        };
+};
+/* controller at 0xb000 */
+&pci2 {
+        compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 0 0>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p1023-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p1023-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p1023-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p1023-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+        crypto: crypto@300000 {
+                compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x30000 0x10000>;
+                ranges = <0 0x30000 0x10000>;
+                interrupts = <58 2 0 0>;
+                sec_jr0: jr@1000 {
+                        compatible = "fsl,sec-v4.2-job-ring",
+                                     "fsl,sec-v4.0-job-ring";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <45 2 0 0>;
+                };
+                sec_jr1: jr@2000 {
+                        compatible = "fsl,sec-v4.2-job-ring",
+                                     "fsl,sec-v4.0-job-ring";
+                        reg = <0x2000 0x1000>;
+                        interrupts = <45 2 0 0>;
+                };
+                sec_jr2: jr@3000 {
+                        compatible = "fsl,sec-v4.2-job-ring",
+                                     "fsl,sec-v4.0-job-ring";
+                        reg = <0x3000 0x1000>;
+                        interrupts = <57 2 0 0>;
+                };
+                sec_jr3: jr@4000 {
+                        compatible = "fsl,sec-v4.2-job-ring",
+                                     "fsl,sec-v4.0-job-ring";
+                        reg = <0x4000 0x1000>;
+                        interrupts = <57 2 0 0>;
+                };
+                rtic@6000 {
+                        compatible = "fsl,sec-v4.2-rtic",
+                                     "fsl,sec-v4.0-rtic";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x6000 0x100>;
+                        ranges = <0x0 0x6100 0xe00>;
+                        rtic_a: rtic-a@0 {
+                                compatible = "fsl,sec-v4.2-rtic-memory",
+                                             "fsl,sec-v4.0-rtic-memory";
+                                reg = <0x00 0x20 0x100 0x80>;
+                        };
+                        rtic_b: rtic-b@20 {
+                                compatible = "fsl,sec-v4.2-rtic-memory",
+                                             "fsl,sec-v4.0-rtic-memory";
+                                reg = <0x20 0x20 0x200 0x80>;
+                        };
+                        rtic_c: rtic-c@40 {
+                                compatible = "fsl,sec-v4.2-rtic-memory",
+                                             "fsl,sec-v4.0-rtic-memory";
+                                reg = <0x40 0x20 0x300 0x80>;
+                        };
+                        rtic_d: rtic-d@60 {
+                                compatible = "fsl,sec-v4.2-rtic-memory",
+                                             "fsl,sec-v4.0-rtic-memory";
+                                reg = <0x60 0x20 0x500 0x80>;
+                        };
+                };
+        };
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,p1023-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
new file mode 100644
index 000000000000..ac45f6d93385
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -0,0 +1,76 @@
+/*
+ * P1023/P1017 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P1023";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P1023@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P1023@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
new file mode 100644
index 000000000000..c041050561a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -0,0 +1,194 @@
+/*
+ * P2020/P2010 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <19 2 0 0>;
+};
+/* controller at 0xa000 */
+&pci0 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <26 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <26 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0x9000 */
+&pci1 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <25 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <25 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+                        >;
+        };
+};
+/* controller at 0x8000 */
+&pci2 {
+        compatible = "fsl,mpc8548-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 255>;
+        clock-frequency = <33333333>;
+        interrupts = <24 2 0 0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <24 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+                        >;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,p2020-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,p2020-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <17 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,p2020-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <18 2 0 0>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-duart-0.dtsi"
+/include/ "pq3-espi-0.dtsi"
+        spi0: spi@7000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "pq3-dma-1.dtsi"
+/include/ "pq3-gpio-0.dtsi"
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,p2020-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x80000>; // L2,512K
+                interrupts = <16 2 0 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-usb2-dr-0.dtsi"
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-timer-0.dtsi"
+        ptp_clock@24e00 {
+                interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+        };
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
+/include/ "pq3-esdhc-0.dtsi"
+/include/ "pq3-sec3.1-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+        global-utilities@e0000 {
+                compatible = "fsl,p2020-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
new file mode 100644
index 000000000000..3213288641d1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -0,0 +1,69 @@
+/*
+ * P2020/P2010 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P2020";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P2020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P2020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
new file mode 100644
index 000000000000..234a399ddeb2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -0,0 +1,325 @@
+/*
+ * P2041/P2040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+/* controller at 0x202000 */
+&pci2 {
+        compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 13>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 13>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@42000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x42000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@43000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x43000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000>;
+                interrupts = <16 2 1 27>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x4000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,p2041-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        phy_type = "utmi";
+                        port0;
+                };
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
new file mode 100644
index 000000000000..2d0a40d6b10f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -0,0 +1,111 @@
+/*
+ * P2041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P2041";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500mc@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e500mc@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e500mc@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e500mc@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
new file mode 100644
index 000000000000..d41d08de7f7e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -0,0 +1,352 @@
+/*
+ * P3041 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+/* controller at 0x202000 */
+&pci2 {
+        compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 13>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 13>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+/* controller at 0x203000 */
+&pci3 {
+        compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 12>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 12>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 43 1 0 0
+                        0000 0 0 2 &mpic 0 1 0 0
+                        0000 0 0 3 &mpic 4 1 0 0
+                        0000 0 0 4 &mpic 8 1 0 0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@42000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x42000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@43000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x43000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000>;
+                interrupts = <16 2 1 27>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x4000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,p3041-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        phy_type = "utmi";
+                        port0;
+                };
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
new file mode 100644
index 000000000000..136def3536b6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -0,0 +1,112 @@
+/*
+ * P3041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P3041";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500mc@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e500mc@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e500mc@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e500mc@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
new file mode 100644
index 000000000000..a63edd195ae5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -0,0 +1,296 @@
+/*
+ * P3060 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,srio-rmu-handle = <&rmu>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@44000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu4>;
+                reg = <0x44000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@45000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu5>;
+                reg = <0x45000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@46000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu6>;
+                reg = <0x46000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@47000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu7>;
+                reg = <0x47000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p3060-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000
+                       0x11000 0x1000>;
+                interrupts = <16 2 1 27
+                              16 2 1 26>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x5000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+/include/ "qoriq-rmu-0.dtsi"
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,p3060-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+/include/ "qoriq-usb2-dr-0.dtsi"
+/include/ "qoriq-sec4.1-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
new file mode 100644
index 000000000000..00c8e70e7b90
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
@@ -0,0 +1,125 @@
+/*
+ * P3060 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P3060";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500mc@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e500mc@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu4: PowerPC,e500mc@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        next-level-cache = <&L2_4>;
+                        L2_4: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu5: PowerPC,e500mc@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        next-level-cache = <&L2_5>;
+                        L2_5: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu6: PowerPC,e500mc@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        next-level-cache = <&L2_6>;
+                        L2_6: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu7: PowerPC,e500mc@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        next-level-cache = <&L2_7>;
+                        L2_7: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
new file mode 100644
index 000000000000..8d35d2c1f694
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -0,0 +1,350 @@
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p4080-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p4080-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+/* controller at 0x202000 */
+&pci2 {
+        compatible = "fsl,p4080-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 13>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 13>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,srio-rmu-handle = <&rmu>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-ddr@13000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr2>;
+                reg = <0x13000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@42000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x42000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@43000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x43000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@44000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu4>;
+                reg = <0x44000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@45000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu5>;
+                reg = <0x45000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@46000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu6>;
+                reg = <0x46000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@47000 {
+                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu7>;
+                reg = <0x47000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        ddr2: memory-controller@9000 {
+                compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
+                reg = <0x9000 0x1000>;
+                interrupts = <16 2 1 22>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p4080-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000
+                       0x11000 0x1000>;
+                interrupts = <16 2 1 27
+                              16 2 1 26>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x5000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+/include/ "qoriq-rmu-0.dtsi"
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,p4080-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                voltage-ranges = <3300 3300>;
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+/include/ "qoriq-usb2-dr-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
new file mode 100644
index 000000000000..b9556ee3a639
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,143 @@
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P4080";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500mc@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e500mc@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e500mc@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e500mc@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu4: PowerPC,e500mc@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        next-level-cache = <&L2_4>;
+                        L2_4: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu5: PowerPC,e500mc@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        next-level-cache = <&L2_5>;
+                        L2_5: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu6: PowerPC,e500mc@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        next-level-cache = <&L2_6>;
+                        L2_6: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu7: PowerPC,e500mc@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        next-level-cache = <&L2_7>;
+                        L2_7: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
new file mode 100644
index 000000000000..914074b91a85
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -0,0 +1,355 @@
+/*
+ * P5020/5010 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&lbc {
+        compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
+        interrupts = <25 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+};
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 15>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 15>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+/* controller at 0x201000 */
+&pci1 {
+        compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 14>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 14>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+/* controller at 0x202000 */
+&pci2 {
+        compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 13>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 13>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+/* controller at 0x203000 */
+&pci3 {
+        compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        clock-frequency = <33333333>;
+        interrupts = <16 2 1 12>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <16 2 1 12>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 43 1 0 0
+                        0000 0 0 2 &mpic 0 1 0 0
+                        0000 0 0 3 &mpic 4 1 0 0
+                        0000 0 0 4 &mpic 8 1 0 0
+                        >;
+        };
+};
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,dcsr-npc";
+                reg = <0x1000 0x1000 0x1000000 0x8000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0xB0000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-ddr@13000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr2>;
+                reg = <0x13000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@40000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x40000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@41000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x41000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        ddr2: memory-controller@9000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
+                reg = <0x9000 0x1000>;
+                interrupts = <16 2 1 22>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000
+                       0x11000 0x1000>;
+                interrupts = <16 2 1 27
+                              16 2 1 26>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x4000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,qoriq-device-config-1.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                #sleep-cells = <1>;
+                fsl,liodn-bits = <12>;
+        };
+        pins: global-utilities@e0e00 {
+                compatible = "fsl,qoriq-pin-control-1.0";
+                reg = <0xe0e00 0x200>;
+                #sleep-cells = <2>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+                reg = <0xe1000 0x1000>;
+                clock-frequency = <0>;
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,qoriq-rcpm-1.0";
+                reg = <0xe2000 0x1000>;
+                #sleep-cells = <1>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,p5020-serdes";
+                reg        = <0xea000 0x1000>;
+        };
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        phy_type = "utmi";
+                        port0;
+                };
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
new file mode 100644
index 000000000000..ae823a47584e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -0,0 +1,96 @@
+/*
+ * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,P5020";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+                msi0 = &msi0;
+                msi1 = &msi1;
+                msi2 = &msi2;
+                crypto = &crypto;
+                sec_jr0 = &sec_jr0;
+                sec_jr1 = &sec_jr1;
+                sec_jr2 = &sec_jr2;
+                sec_jr3 = &sec_jr3;
+                rtic_a = &rtic_a;
+                rtic_b = &rtic_b;
+                rtic_c = &rtic_c;
+                rtic_d = &rtic_d;
+                sec_mon = &sec_mon;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e5500@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e5500@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
new file mode 100644
index 000000000000..b5b37ad30e75
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
@@ -0,0 +1,66 @@
+/*
+ * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+dma@21300 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,eloplus-dma";
+        reg = <0x21300 0x4>;
+        ranges = <0x0 0x21100 0x200>;
+        cell-index = <0>;
+        dma-channel@0 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x0 0x80>;
+                cell-index = <0>;
+                interrupts = <20 2 0 0>;
+        };
+        dma-channel@80 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x80 0x80>;
+                cell-index = <1>;
+                interrupts = <21 2 0 0>;
+        };
+        dma-channel@100 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x100 0x80>;
+                cell-index = <2>;
+                interrupts = <22 2 0 0>;
+        };
+        dma-channel@180 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x180 0x80>;
+                cell-index = <3>;
+                interrupts = <23 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
new file mode 100644
index 000000000000..28cb8a55d807
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
@@ -0,0 +1,66 @@
+/*
+ * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+dma@c300 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,eloplus-dma";
+        reg = <0xc300 0x4>;
+        ranges = <0x0 0xc100 0x200>;
+        cell-index = <1>;
+        dma-channel@0 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x0 0x80>;
+                cell-index = <0>;
+                interrupts = <76 2 0 0>;
+        };
+        dma-channel@80 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x80 0x80>;
+                cell-index = <1>;
+                interrupts = <77 2 0 0>;
+        };
+        dma-channel@100 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x100 0x80>;
+                cell-index = <2>;
+                interrupts = <78 2 0 0>;
+        };
+        dma-channel@180 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x180 0x80>;
+                cell-index = <3>;
+                interrupts = <79 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
new file mode 100644
index 000000000000..5e268fdb9d1f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -0,0 +1,51 @@
+/*
+ * PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+serial0: serial@4500 {
+        cell-index = <0>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x4500 0x100>;
+        clock-frequency = <0>;
+        interrupts = <42 2 0 0>;
+};
+serial1: serial@4600 {
+        cell-index = <1>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x4600 0x100>;
+        clock-frequency = <0>;
+        interrupts = <42 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
new file mode 100644
index 000000000000..5743433e278e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sdhc@2e000 {
+        compatible = "fsl,esdhc";
+        reg = <0x2e000 0x1000>;
+        interrupts = <72 0x2 0 0>;
+        /* Filled in by U-Boot */
+        clock-frequency = <0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
new file mode 100644
index 000000000000..75854b2e0391
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * PQ3 eSPI device tree stub [ controller @ offset 0x7000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+spi@7000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,mpc8536-espi";
+        reg = <0x7000 0x1000>;
+        interrupts = <59 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
new file mode 100644
index 000000000000..a1979ae334a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ethernet@24000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cell-index = <0>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "gianfar";
+        reg = <0x24000 0x1000>;
+        ranges = <0x0 0x24000 0x1000>;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+mdio@24520 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,gianfar-mdio";
+        reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
new file mode 100644
index 000000000000..4c4fdde1ec2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -0,0 +1,53 @@
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ethernet@25000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cell-index = <1>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "gianfar";
+        reg = <0x25000 0x1000>;
+        ranges = <0x0 0x25000 0x1000>;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+mdio@25520 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,gianfar-tbi";
+        reg = <0x25520 0x20>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
new file mode 100644
index 000000000000..4b8ab438668a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -0,0 +1,53 @@
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ethernet@26000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cell-index = <2>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "gianfar";
+        reg = <0x26000 0x1000>;
+        ranges = <0x0 0x26000 0x1000>;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+mdio@26520 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,gianfar-tbi";
+        reg = <0x26520 0x20>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
new file mode 100644
index 000000000000..40c9137729ae
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -0,0 +1,53 @@
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ethernet@27000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cell-index = <3>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "gianfar";
+        reg = <0x27000 0x1000>;
+        ranges = <0x0 0x27000 0x1000>;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+mdio@27520 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,gianfar-tbi";
+        reg = <0x27520 0x20>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
new file mode 100644
index 000000000000..efe2ca04bce8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
@@ -0,0 +1,39 @@
+/*
+ * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ptp_clock@24e00 {
+        compatible = "fsl,etsec-ptp";
+        reg = <0x24e00 0xb0>;
+        interrupts = <68 2 0 0 69 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
new file mode 100644
index 000000000000..1382fec9e8c5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
@@ -0,0 +1,60 @@
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+mdio@24000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,etsec2-mdio";
+        reg = <0x24000 0x1000 0xb0030 0x4>;
+};
+ethernet@b0000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "fsl,etsec2";
+        fsl,num_rx_queues = <0x8>;
+        fsl,num_tx_queues = <0x8>;
+        fsl,magic-packet;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        queue-group@b0000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb0000 0x1000>;
+                interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
new file mode 100644
index 000000000000..221cd2ea5b31
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
@@ -0,0 +1,60 @@
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+mdio@25000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,etsec2-tbi";
+        reg = <0x25000 0x1000 0xb1030 0x4>;
+};
+ethernet@b1000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "fsl,etsec2";
+        fsl,num_rx_queues = <0x8>;
+        fsl,num_tx_queues = <0x8>;
+        fsl,magic-packet;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        queue-group@b1000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb1000 0x1000>;
+                interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
new file mode 100644
index 000000000000..61456c317609
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
@@ -0,0 +1,59 @@
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+mdio@26000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,etsec2-tbi";
+        reg = <0x26000 0x1000 0xb1030 0x4>;
+};
+ethernet@b2000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "network";
+        model = "eTSEC";
+        compatible = "fsl,etsec2";
+        fsl,num_rx_queues = <0x8>;
+        fsl,num_tx_queues = <0x8>;
+        fsl,magic-packet;
+        local-mac-address = [ 00 00 00 00 00 00 ];
+        queue-group@b2000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb2000 0x1000>;
+                interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 000000000000..034ab8fac22f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,42 @@
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&enet0_grp2 {
+        queue-group@b4000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb4000 0x1000>;
+                interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 000000000000..3be9ba3b374e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,42 @@
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&enet1_grp2 {
+        queue-group@b5000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb5000 0x1000>;
+                interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 000000000000..02a33457048c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,42 @@
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&enet2_grp2 {
+        queue-group@b6000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xb6000 0x1000>;
+                interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
new file mode 100644
index 000000000000..72a3ef5945c1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * PQ3 GPIO device tree stub [ controller @ offset 0xf000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+gpio-controller@f000 {
+        #gpio-cells = <2>;
+        compatible = "fsl,pq3-gpio";
+        reg = <0xf000 0x100>;
+        interrupts = <47 0x2 0 0>;
+        gpio-controller;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
new file mode 100644
index 000000000000..d1dd6fb82a78
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 I2C device tree stub [ controller @ offset 0x3000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+i2c@3000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <0>;
+        compatible = "fsl-i2c";
+        reg = <0x3000 0x100>;
+        interrupts = <43 2 0 0>;
+        dfsrr;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
new file mode 100644
index 000000000000..a9bd803e2090
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 I2C device tree stub [ controller @ offset 0x3100 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+i2c@3100 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <1>;
+        compatible = "fsl-i2c";
+        reg = <0x3100 0x100>;
+        interrupts = <43 2 0 0>;
+        dfsrr;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
new file mode 100644
index 000000000000..8734cffae1a1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
@@ -0,0 +1,42 @@
+/*
+ * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+timer@42100 {
+        compatible = "fsl,mpic-global-timer";
+        reg = <0x42100 0x100 0x42300 4>;
+        interrupts = <4 0 3 0
+                      5 0 3 0
+                      6 0 3 0
+                      7 0 3 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
new file mode 100644
index 000000000000..5c8046065844
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -0,0 +1,66 @@
+/*
+ * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+mpic: pic@40000 {
+        interrupt-controller;
+        #address-cells = <0>;
+        #interrupt-cells = <4>;
+        reg = <0x40000 0x40000>;
+        compatible = "fsl,mpic";
+        device_type = "open-pic";
+};
+timer@41100 {
+        compatible = "fsl,mpic-global-timer";
+        reg = <0x41100 0x100 0x41300 4>;
+        interrupts = <0 0 3 0
+                      1 0 3 0
+                      2 0 3 0
+                      3 0 3 0>;
+};
+msi@41600 {
+        compatible = "fsl,mpic-msi";
+        reg = <0x41600 0x80>;
+        msi-available-ranges = <0 0x100>;
+        interrupts = <
+                0xe0 0 0 0
+                0xe1 0 0 0
+                0xe2 0 0 0
+                0xe3 0 0 0
+                0xe4 0 0 0
+                0xe5 0 0 0
+                0xe6 0 0 0
+                0xe7 0 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
new file mode 100644
index 000000000000..587ca9ffad7d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
@@ -0,0 +1,68 @@
+/*
+ * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+rmu: rmu@d3000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,srio-rmu";
+        reg = <0xd3000 0x500>;
+        ranges = <0x0 0xd3000 0x500>;
+        message-unit@0 {
+                compatible = "fsl,srio-msg-unit";
+                reg = <0x0 0x100>;
+                interrupts = <
+                        53 2 0 0 /* msg1_tx_irq */
+                        54 2 0 0>;/* msg1_rx_irq */
+        };
+        message-unit@100 {
+                compatible = "fsl,srio-msg-unit";
+                reg = <0x100 0x100>;
+                interrupts = <
+                        55 2 0 0  /* msg2_tx_irq */
+                        56 2 0 0>;/* msg2_rx_irq */
+        };
+        doorbell-unit@400 {
+                compatible = "fsl,srio-dbell-unit";
+                reg = <0x400 0x80>;
+                interrupts = <
+                        49 2 0 0  /* bell_outb_irq */
+                        50 2 0 0>;/* bell_inb_irq */
+        };
+        port-write-unit@4e0 {
+                compatible = "fsl,srio-port-write-unit";
+                reg = <0x4e0 0x20>;
+                interrupts = <48 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
new file mode 100644
index 000000000000..3c28dd08d38b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
@@ -0,0 +1,40 @@
+/*
+ * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sata@18000 {
+        compatible = "fsl,pq-sata-v2";
+        reg = <0x18000 0x1000>;
+        cell-index = <1>;
+        interrupts = <74 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
new file mode 100644
index 000000000000..eefaf2855e3b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
@@ -0,0 +1,40 @@
+/*
+ * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sata@19000 {
+        compatible = "fsl,pq-sata-v2";
+        reg = <0x19000 0x1000>;
+        cell-index = <2>;
+        interrupts = <41 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
new file mode 100644
index 000000000000..02a5c7ae72d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto@30000 {
+        compatible = "fsl,sec2.1", "fsl,sec2.0";
+        reg = <0x30000 0x10000>;
+        interrupts = <45 2 0 0>;
+        fsl,num-channels = <4>;
+        fsl,channel-fifo-len = <24>;
+        fsl,exec-units-mask = <0xfe>;
+        fsl,descriptor-types-mask = <0x12b0ebf>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
new file mode 100644
index 000000000000..bba1ba44ccf0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
@@ -0,0 +1,45 @@
+/*
+ * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto@30000 {
+        compatible = "fsl,sec3.0",
+                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+                     "fsl,sec2.0";
+        reg = <0x30000 0x10000>;
+        interrupts = <45 2 0 0 58 2 0 0>;
+        fsl,num-channels = <4>;
+        fsl,channel-fifo-len = <24>;
+        fsl,exec-units-mask = <0x9fe>;
+        fsl,descriptor-types-mask = <0x3ab0ebf>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
new file mode 100644
index 000000000000..8f0a5669bee5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
@@ -0,0 +1,45 @@
+/*
+ * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto@30000 {
+        compatible = "fsl,sec3.1", "fsl,sec3.0",
+                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+                     "fsl,sec2.0";
+        reg = <0x30000 0x10000>;
+        interrupts = <45 2 0 0 58 2 0 0>;
+        fsl,num-channels = <4>;
+        fsl,channel-fifo-len = <24>;
+        fsl,exec-units-mask = <0xbfe>;
+        fsl,descriptor-types-mask = <0x3ab0ebf>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
new file mode 100644
index 000000000000..c227f2748a24
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
@@ -0,0 +1,45 @@
+/*
+ * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto@30000 {
+        compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
+                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+                     "fsl,sec2.0";
+        reg = <0x30000 0x10000>;
+        interrupts = <45 2 0 0 58 2 0 0>;
+        fsl,num-channels = <4>;
+        fsl,channel-fifo-len = <24>;
+        fsl,exec-units-mask = <0x97c>;
+        fsl,descriptor-types-mask = <0x3a30abf>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
new file mode 100644
index 000000000000..bf957a7fca2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -0,0 +1,65 @@
+/*
+ * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto@30000 {
+        compatible = "fsl,sec4.4", "fsl,sec4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg              = <0x30000 0x10000>;
+        interrupts       = <58 2 0 0>;
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                reg        = <0x1000 0x1000>;
+                interrupts       = <45 2 0 0>;
+        };
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                reg        = <0x2000 0x1000>;
+                interrupts       = <45 2 0 0>;
+        };
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                reg        = <0x3000 0x1000>;
+                interrupts       = <45 2 0 0>;
+        };
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                reg        = <0x4000 0x1000>;
+                interrupts       = <45 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..185ab9dc3ecd
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * PQ3 USB DR device tree stub [ controller @ offset 0x22000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+usb@22000 {
+        compatible = "fsl-usb2-dr";
+        reg = <0x22000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <28 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
new file mode 100644
index 000000000000..fe24cd612fff
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * PQ3 USB DR device tree stub [ controller @ offset 0x23000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+usb@23000 {
+        compatible = "fsl-usb2-dr";
+        reg = <0x23000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <46 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
new file mode 100644
index 000000000000..1aebf3ea4ca5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
@@ -0,0 +1,66 @@
+/*
+ * QorIQ DMA device tree stub [ controller @ offset 0x100000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+dma0: dma@100300 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,eloplus-dma";
+        reg = <0x100300 0x4>;
+        ranges = <0x0 0x100100 0x200>;
+        cell-index = <0>;
+        dma-channel@0 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x0 0x80>;
+                cell-index = <0>;
+                interrupts = <28 2 0 0>;
+        };
+        dma-channel@80 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x80 0x80>;
+                cell-index = <1>;
+                interrupts = <29 2 0 0>;
+        };
+        dma-channel@100 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x100 0x80>;
+                cell-index = <2>;
+                interrupts = <30 2 0 0>;
+        };
+        dma-channel@180 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x180 0x80>;
+                cell-index = <3>;
+                interrupts = <31 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
new file mode 100644
index 000000000000..ecf5e180fe79
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
@@ -0,0 +1,66 @@
+/*
+ * QorIQ DMA device tree stub [ controller @ offset 0x101000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+dma1: dma@101300 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,eloplus-dma";
+        reg = <0x101300 0x4>;
+        ranges = <0x0 0x101100 0x200>;
+        cell-index = <1>;
+        dma-channel@0 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x0 0x80>;
+                cell-index = <0>;
+                interrupts = <32 2 0 0>;
+        };
+        dma-channel@80 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x80 0x80>;
+                cell-index = <1>;
+                interrupts = <33 2 0 0>;
+        };
+        dma-channel@100 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x100 0x80>;
+                cell-index = <2>;
+                interrupts = <34 2 0 0>;
+        };
+        dma-channel@180 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x180 0x80>;
+                cell-index = <3>;
+                interrupts = <35 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
new file mode 100644
index 000000000000..225c07b4e8ab
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
@@ -0,0 +1,51 @@
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+serial0: serial@11c500 {
+        cell-index = <0>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x11c500 0x100>;
+        clock-frequency = <0>;
+        interrupts = <36 2 0 0>;
+};
+serial1: serial@11c600 {
+        cell-index = <1>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x11c600 0x100>;
+        clock-frequency = <0>;
+        interrupts = <36 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
new file mode 100644
index 000000000000..d23233a56b91
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
@@ -0,0 +1,51 @@
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+serial2: serial@11d500 {
+        cell-index = <2>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x11d500 0x100>;
+        clock-frequency = <0>;
+        interrupts = <37 2 0 0>;
+};
+serial3: serial@11d600 {
+        cell-index = <3>;
+        device_type = "serial";
+        compatible = "fsl,ns16550", "ns16550";
+        reg = <0x11d600 0x100>;
+        clock-frequency = <0>;
+        interrupts = <37 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
new file mode 100644
index 000000000000..20835ae216c7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
@@ -0,0 +1,40 @@
+/*
+ * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sdhc: sdhc@114000 {
+        compatible = "fsl,esdhc";
+        reg = <0x114000 0x1000>;
+        interrupts = <48 2 0 0>;
+        clock-frequency = <0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
new file mode 100644
index 000000000000..6db06975e095
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+spi@110000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,mpc8536-espi";
+        reg = <0x110000 0x1000>;
+        interrupts = <53 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
new file mode 100644
index 000000000000..cf714f5f68bc
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x130000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+gpio0: gpio@130000 {
+        compatible = "fsl,qoriq-gpio";
+        reg = <0x130000 0x1000>;
+        interrupts = <55 2 0 0>;
+        #gpio-cells = <2>;
+        gpio-controller;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
new file mode 100644
index 000000000000..5f9bf7debe4c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * QorIQ I2C device tree stub [ controller @ offset 0x118000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+i2c@118000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <0>;
+        compatible = "fsl-i2c";
+        reg = <0x118000 0x100>;
+        interrupts = <38 2 0 0>;
+        dfsrr;
+};
+i2c@118100 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <1>;
+        compatible = "fsl-i2c";
+        reg = <0x118100 0x100>;
+        interrupts = <38 2 0 0>;
+        dfsrr;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
new file mode 100644
index 000000000000..7989bf5eeb53
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
@@ -0,0 +1,53 @@
+/*
+ * QorIQ I2C device tree stub [ controller @ offset 0x119000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+i2c@119000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <2>;
+        compatible = "fsl-i2c";
+        reg = <0x119000 0x100>;
+        interrupts = <39 2 0 0>;
+        dfsrr;
+};
+i2c@119100 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        cell-index = <3>;
+        compatible = "fsl-i2c";
+        reg = <0x119100 0x100>;
+        interrupts = <39 2 0 0>;
+        dfsrr;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
new file mode 100644
index 000000000000..b9bada6a87dc
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -0,0 +1,106 @@
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+mpic: pic@40000 {
+        interrupt-controller;
+        #address-cells = <0>;
+        #interrupt-cells = <4>;
+        reg = <0x40000 0x40000>;
+        compatible = "fsl,mpic", "chrp,open-pic";
+        device_type = "open-pic";
+        clock-frequency = <0x0>;
+};
+timer@41100 {
+        compatible = "fsl,mpic-global-timer";
+        reg = <0x41100 0x100 0x41300 4>;
+        interrupts = <0 0 3 0
+                      1 0 3 0
+                      2 0 3 0
+                      3 0 3 0>;
+};
+msi0: msi@41600 {
+        compatible = "fsl,mpic-msi";
+        reg = <0x41600 0x200>;
+        msi-available-ranges = <0 0x100>;
+        interrupts = <
+                0xe0 0 0 0
+                0xe1 0 0 0
+                0xe2 0 0 0
+                0xe3 0 0 0
+                0xe4 0 0 0
+                0xe5 0 0 0
+                0xe6 0 0 0
+                0xe7 0 0 0>;
+};
+msi1: msi@41800 {
+        compatible = "fsl,mpic-msi";
+        reg = <0x41800 0x200>;
+        msi-available-ranges = <0 0x100>;
+        interrupts = <
+                0xe8 0 0 0
+                0xe9 0 0 0
+                0xea 0 0 0
+                0xeb 0 0 0
+                0xec 0 0 0
+                0xed 0 0 0
+                0xee 0 0 0
+                0xef 0 0 0>;
+};
+msi2: msi@41a00 {
+        compatible = "fsl,mpic-msi";
+        reg = <0x41a00 0x200>;
+        msi-available-ranges = <0 0x100>;
+        interrupts = <
+                0xf0 0 0 0
+                0xf1 0 0 0
+                0xf2 0 0 0
+                0xf3 0 0 0
+                0xf4 0 0 0
+                0xf5 0 0 0
+                0xf6 0 0 0
+                0xf7 0 0 0>;
+};
+timer@42100 {
+        compatible = "fsl,mpic-global-timer";
+        reg = <0x42100 0x100 0x42300 4>;
+        interrupts = <4 0 3 0
+                      5 0 3 0
+                      6 0 3 0
+                      7 0 3 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
new file mode 100644
index 000000000000..ca7fec792e53
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
@@ -0,0 +1,68 @@
+/*
+ * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+rmu: rmu@d3000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,srio-rmu";
+        reg = <0xd3000 0x500>;
+        ranges = <0x0 0xd3000 0x500>;
+        message-unit@0 {
+                compatible = "fsl,srio-msg-unit";
+                reg = <0x0 0x100>;
+                interrupts = <
+                        60 2 0 0  /* msg1_tx_irq */
+                        61 2 0 0>;/* msg1_rx_irq */
+        };
+        message-unit@100 {
+                compatible = "fsl,srio-msg-unit";
+                reg = <0x100 0x100>;
+                interrupts = <
+                        62 2 0 0  /* msg2_tx_irq */
+                        63 2 0 0>;/* msg2_rx_irq */
+        };
+        doorbell-unit@400 {
+                compatible = "fsl,srio-dbell-unit";
+                reg = <0x400 0x80>;
+                interrupts = <
+                        56 2 0 0  /* bell_outb_irq */
+                        57 2 0 0>;/* bell_inb_irq */
+        };
+        port-write-unit@4e0 {
+                compatible = "fsl,srio-port-write-unit";
+                reg = <0x4e0 0x20>;
+                interrupts = <16 2 1 11>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
new file mode 100644
index 000000000000..b642047fdecf
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
@@ -0,0 +1,39 @@
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sata@220000 {
+        compatible = "fsl,pq-sata-v2";
+        reg = <0x220000 0x1000>;
+        interrupts = <68 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
new file mode 100644
index 000000000000..c57370259750
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
@@ -0,0 +1,39 @@
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+sata@221000 {
+        compatible = "fsl,pq-sata-v2";
+        reg = <0x221000 0x1000>;
+        interrupts = <69 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
new file mode 100644
index 000000000000..0cbbac329539
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,100 @@
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto: crypto@300000 {
+        compatible = "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x300000 0x10000>;
+        ranges = <0 0x300000 0x10000>;
+        interrupts = <92 2 0 0>;
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec-v4.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <88 2 0 0>;
+        };
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec-v4.0-job-ring";
+                reg = <0x2000 0x1000>;
+                interrupts = <89 2 0 0>;
+        };
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec-v4.0-job-ring";
+                reg = <0x3000 0x1000>;
+                interrupts = <90 2 0 0>;
+        };
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec-v4.0-job-ring";
+                reg = <0x4000 0x1000>;
+                interrupts = <91 2 0 0>;
+        };
+        rtic@6000 {
+                compatible = "fsl,sec-v4.0-rtic";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x6000 0x100>;
+                ranges = <0x0 0x6100 0xe00>;
+                rtic_a: rtic-a@0 {
+                        compatible = "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x00 0x20 0x100 0x80>;
+                };
+                rtic_b: rtic-b@20 {
+                        compatible = "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x20 0x20 0x200 0x80>;
+                };
+                rtic_c: rtic-c@40 {
+                        compatible = "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x40 0x20 0x300 0x80>;
+                };
+                rtic_d: rtic-d@60 {
+                        compatible = "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x60 0x20 0x500 0x80>;
+                };
+        };
+};
+sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v4.0-mon";
+        reg = <0x314000 0x1000>;
+        interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
new file mode 100644
index 000000000000..3308986bba0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
@@ -0,0 +1,109 @@
+/*
+ * QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto: crypto@300000 {
+        compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg              = <0x300000 0x10000>;
+        ranges           = <0 0x300000 0x10000>;
+        interrupts       = <92 2 0 0>;
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec-v4.1-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <88 2 0 0>;
+        };
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec-v4.1-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x2000 0x1000>;
+                interrupts = <89 2 0 0>;
+        };
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec-v4.1-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x3000 0x1000>;
+                interrupts = <90 2 0 0>;
+        };
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec-v4.1-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x4000 0x1000>;
+                interrupts = <91 2 0 0>;
+        };
+        rtic@6000 {
+                compatible = "fsl,sec-v4.1-rtic",
+                             "fsl,sec-v4.0-rtic";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x6000 0x100>;
+                ranges = <0x0 0x6100 0xe00>;
+                rtic_a: rtic-a@0 {
+                        compatible = "fsl,sec-v4.1-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x00 0x20 0x100 0x80>;
+                };
+                rtic_b: rtic-b@20 {
+                        compatible = "fsl,sec-v4.1-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x20 0x20 0x200 0x80>;
+                };
+                rtic_c: rtic-c@40 {
+                        compatible = "fsl,sec-v4.1-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x40 0x20 0x300 0x80>;
+                };
+                rtic_d: rtic-d@60 {
+                        compatible = "fsl,sec-v4.1-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x60 0x20 0x500 0x80>;
+                };
+        };
+};
+sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
+        reg = <0x314000 0x1000>;
+        interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
new file mode 100644
index 000000000000..7990e0d3d6f2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,109 @@
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+crypto: crypto@300000 {
+        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg              = <0x300000 0x10000>;
+        ranges           = <0 0x300000 0x10000>;
+        interrupts       = <92 2 0 0>;
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec-v4.2-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <88 2 0 0>;
+        };
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec-v4.2-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x2000 0x1000>;
+                interrupts = <89 2 0 0>;
+        };
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec-v4.2-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x3000 0x1000>;
+                interrupts = <90 2 0 0>;
+        };
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec-v4.2-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x4000 0x1000>;
+                interrupts = <91 2 0 0>;
+        };
+        rtic@6000 {
+                compatible = "fsl,sec-v4.2-rtic",
+                             "fsl,sec-v4.0-rtic";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x6000 0x100>;
+                ranges = <0x0 0x6100 0xe00>;
+                rtic_a: rtic-a@0 {
+                        compatible = "fsl,sec-v4.2-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x00 0x20 0x100 0x80>;
+                };
+                rtic_b: rtic-b@20 {
+                        compatible = "fsl,sec-v4.2-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x20 0x20 0x200 0x80>;
+                };
+                rtic_c: rtic-c@40 {
+                        compatible = "fsl,sec-v4.2-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x40 0x20 0x300 0x80>;
+                };
+                rtic_d: rtic-d@60 {
+                        compatible = "fsl,sec-v4.2-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x60 0x20 0x500 0x80>;
+                };
+        };
+};
+sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+        reg = <0x314000 0x1000>;
+        interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..4dd6f84c239c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+usb@211000 {
+        compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+        reg = <0x211000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <45 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
new file mode 100644
index 000000000000..f053835aa1c7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+usb@210000 {
+        compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+        reg = <0x210000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <44 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 2266bbb303d0..38dcb96c8e26 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -339,7 +339,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x2a 0x2>;
@@ -349,7 +349,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 429e87d9acef..5ab8932d09b7 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -337,7 +337,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index d81201ac2cad..d5341f5741aa 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -337,7 +337,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/klondike.dts b/arch/powerpc/boot/dts/klondike.dts
new file mode 100644
index 000000000000..8c9429033618
--- /dev/null
+++ b/arch/powerpc/boot/dts/klondike.dts
@@ -0,0 +1,227 @@
+/*
+ * Device Tree for Klondike (APM8018X) board.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tanmay Inamdar <tinamdar@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/dts-v1/;
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        model = "apm,klondike";
+        compatible = "apm,klondike";
+        dcr-parent = <&{/cpus/cpu@0}>;
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,apm8018x";
+                        reg = <0x00000000>;
+                        clock-frequency = <300000000>; /* Filled in by U-Boot */
+                        timebase-frequency = <300000000>; /* Filled in by U-Boot */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <16384>; /* 16 kB */
+                        d-cache-size = <16384>; /* 16 kB */
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
+        };
+        UIC0: interrupt-controller {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0x0c0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0x0d0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0x0e0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+        UIC3: interrupt-controller3 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <3>;
+                dcr-reg = <0x0f0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+        plb {
+                compatible = "ibm,plb4";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+                SDRAM0: memory-controller {
+                        compatible = "ibm,sdram-apm8018x";
+                        dcr-reg = <0x010 0x002>;
+                };
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal2";
+                        dcr-reg = <0x180 0x062>;
+                        num-tx-chans = <2>;
+                        num-rx-chans = <16>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&UIC1>;
+                        interrupts = </*TXEOB*/   0x6 0x4
+                                        /*RXEOB*/ 0x7 0x4
+                                        /*SERR*/  0x1 0x4
+                                        /*TXDE*/  0x2 0x4
+                                        /*RXDE*/  0x3 0x4>;
+                };
+                POB0: opb {
+                        compatible = "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x20000000 0x20000000 0x30000000
+                                  0x50000000 0x50000000 0x10000000
+                                  0x60000000 0x60000000 0x10000000
+                                  0xFE000000 0xFE000000 0x00010000>;
+                        dcr-reg = <0x100 0x020>;
+                        clock-frequency = <300000000>; /* Filled in by U-Boot */
+                        RGMII0: emac-rgmii@400a2000 {
+                                compatible = "ibm,rgmii";
+                                reg = <0x400a2000 0x00000010>;
+                                has-mdio;
+                        };
+                        TAH0: emac-tah@400a3000 {
+                                compatible = "ibm,tah";
+                                reg = <0x400a3000 0x100>;
+                        };
+                        TAH1: emac-tah@400a4000 {
+                                compatible = "ibm,tah";
+                                reg = <0x400a4000 0x100>;
+                        };
+                        EMAC0: ethernet@400a0000 {
+                                compatible = "ibm,emac4", "ibm-emac4sync";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0x0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
+                                reg = <0x400a0000 0x00000100>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0x0>;
+                                mal-rx-channel = <0x0>;
+                                cell-index = <0>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-address = <0x2>;
+                                turbo = "no";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+                        EMAC1: ethernet@400a1000 {
+                                compatible = "ibm,emac4", "ibm-emac4sync";
+                                status = "disabled";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0x0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
+                                reg = <0x400a1000 0x00000100>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <8>;
+                                cell-index = <1>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-address = <0x3>;
+                                turbo = "no";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+                };
+        };
+        chosen {
+                linux,stdout-path = "/plb/opb/serial@50001000";
+        };
+};
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index d16bae1230f7..983aee185793 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -80,7 +80,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <264000000>;
                        interrupts = <9 0x8>;
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 8d725d10882f..0a4545159e80 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
                serial0: serial@80004500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x80004500 0x8>;
                        clock-frequency = <97553800>;
                        current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
                serial1: serial@80004600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x80004600 0x8>;
                        clock-frequency = <97553800>;
                        current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index b13a11eb81b0..0e758b347cdb 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
                serial0: serial@80004500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x80004500 0x8>;
                        clock-frequency = <130041000>;
                        current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
                serial1: serial@80004600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x80004600 0x8>;
                        clock-frequency = <130041000>;
                        current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 697b3f6b78bf..22b0832b6c31 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -233,7 +233,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <9 0x8>;
@@ -243,7 +243,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a0bd1881081e..f66d10d95a8d 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -208,7 +208,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <9 0x8>;
@@ -218,7 +218,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index ac1eb320c7b4..1c836c6c5be6 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -261,7 +261,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -271,7 +271,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 4dd08c322979..811848e93aef 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -265,7 +265,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <9 0x8>;
@@ -275,7 +275,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <133333333>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 05ad8c98e527..da9c72ddc343 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -105,7 +105,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -115,7 +115,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index f4fadb23ad6f..ff7b15b340a3 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -83,7 +83,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -93,7 +93,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 505dc842d808..2608679d0d4a 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -283,7 +283,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;          // from bootloader
                        interrupts = <9 0x8>;
@@ -293,7 +293,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;          // from bootloader
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index eb732115f016..6cd044d8fb89 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -189,7 +189,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;          // from bootloader
                        interrupts = <9 0x8>;
@@ -199,7 +199,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;          // from bootloader
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 230febb9b72f..4552864082c2 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -242,7 +242,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -252,7 +252,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 45cfa1c50a2a..c0e450a551bf 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -136,7 +136,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <264000000>;
                        interrupts = <9 0x8>;
@@ -146,7 +146,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <264000000>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index bdf4459677b1..b6e9aec1d860 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -102,7 +102,7 @@
                serial0: serial@4500 {
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        interrupts = <9 8>;
                        interrupt-parent = <&ipic>;
@@ -112,7 +112,7 @@
                serial1: serial@4600 {
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        interrupts = <10 8>;
                        interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 855782c5e5ec..cfccef57cd1d 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -276,7 +276,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -286,7 +286,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index dbc1b988b29d..353deff1b7f6 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -321,7 +321,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
index 9ea783056969..ef4a305a0d0c 100644
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -304,7 +304,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -314,7 +314,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index f70cf6000839..538fcb927337 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -315,7 +315,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -325,7 +325,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 3447eb9f6e88..32333a908f3d 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -321,7 +321,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 645ec51cc6e1..5387092fdfb4 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -313,7 +313,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -323,7 +323,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 15560c619b04..46224c2430ff 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -319,7 +319,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -329,7 +329,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index a75c10eed269..c15881574fdc 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -9,24 +9,11 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8536si-pre.dtsi"
 / {
        model = "fsl,mpc8536ds";
        compatible = "fsl,mpc8536ds";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                pci3 = &pci3;
-        };
        cpus {
                #cpus = <1>;
@@ -45,403 +32,34 @@
                reg = <0 0 0 0>;        // Filled by U-Boot
        };
-        soc@ffe00000 {
+        lbc: localbus@ffe05000 {
-                #address-cells = <1>;
+                reg = <0 0xffe05000 0 0x1000>;
-                #size-cells = <1>;
+        };
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8536-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8536-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 0x2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8536-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 0x2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                        rtc@68 {
-                                compatible = "dallas,ds3232";
-                                reg = <0x68>;
-                                interrupts = <0 0x1>;
-                                interrupt-parent = <&mpic>;
-                        };
-                };
-                spi@7000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc8536-espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,espi-num-chipselects = <4>;
-                        flash@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,s25sl12801";
-                                reg = <0>;
-                                spi-max-frequency = <40000000>;
-                                partition@u-boot {
-                                        label = "u-boot";
-                                        reg = <0x00000000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@kernel {
-                                        label = "kernel";
-                                        reg = <0x00100000 0x00500000>;
-                                        read-only;
-                                };
-                                partition@dtb {
-                                        label = "dtb";
-                                        reg = <0x00600000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@fs {
-                                        label = "file system";
-                                        reg = <0x00700000 0x00900000>;
-                                };
-                        };
-                        flash@1 {
-                                compatible = "spansion,s25sl12801";
-                                reg = <1>;
-                                spi-max-frequency = <40000000>;
-                        };
-                        flash@2 {
-                                compatible = "spansion,s25sl12801";
-                                reg = <2>;
-                                spi-max-frequency = <40000000>;
-                        };
-                        flash@3 {
-                                compatible = "spansion,s25sl12801";
-                                reg = <3>;
-                                spi-max-frequency = <40000000>;
-                        };
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 4>;
-                        ranges = <0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                usb@22000 {
-                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x22000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
-                        phy_type = "ulpi";
-                };
-                usb@23000 {
-                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x23000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <46 0x2>;
-                        phy_type = "ulpi";
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 0x1>;
-                                        reg = <0>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 0x1>;
-                                        reg = <1>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet1: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                usb@2b000 {
-                        compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x2b000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <60 0x2>;
-                        dr_mode = "peripheral";
-                        phy_type = "ulpi";
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2>;
-                        interrupt-parent = <&mpic>;
-                        clock-frequency = <250000000>;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
-                                     "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x9fe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                sata@18000 {
-                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
-                        reg = <0x18000 0x1000>;
-                        cell-index = <1>;
-                        interrupts = <74 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                sata@19000 {
-                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
-                        reg = <0x19000 0x1000>;
-                        cell-index = <2>;
-                        interrupts = <41 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8548-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                        big-endian;
-                };
-                msi@41600 {
+        board_soc: soc: soc@ffe00000 {
-                        compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
+                ranges = <0x0 0 0xffe00000 0x100000>;
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
        };
        pci0: pci@ffe08000 {
-                compatible = "fsl,mpc8540-pci";
+                reg = <0 0xffe08000 0 0x1000>;
-                device_type = "pci";
+                ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
+                          0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x11 J17 Slot 1 */
-                        0x8800 0 0 1 &mpic 1 1
+                        0x8800 0 0 1 &mpic 1 1 0 0
-                        0x8800 0 0 2 &mpic 2 1
+                        0x8800 0 0 2 &mpic 2 1 0 0
-                        0x8800 0 0 3 &mpic 3 1
+                        0x8800 0 0 3 &mpic 3 1 0 0
-                        0x8800 0 0 4 &mpic 4 1>;
+                        0x8800 0 0 4 &mpic 4 1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 0x2>;
-                bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
-                          0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe08000 0 0x1000>;
        };
        pci1: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
                          0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0x98000000
                                  0x02000000 0 0x98000000
                                  0 0x08000000
@@ -453,31 +71,10 @@
        };
        pci2: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
                          0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0x90000000
                                  0x02000000 0 0x90000000
                                  0 0x08000000
@@ -489,32 +86,10 @@
        };
        pci3: pcie@ffe0b000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe0b000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
                          0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <27 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 8 1
-                        0000 0 0 2 &mpic 9 1
-                        0000 0 0 3 &mpic 10 1
-                        0000 0 0 4 &mpic 11 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0xa0000000
                                  0x02000000 0 0xa0000000
                                  0 0x20000000
@@ -525,3 +100,6 @@
                };
        };
 };
+/include/ "fsl/mpc8536si-post.dtsi"
+/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
new file mode 100644
index 000000000000..1462e4cf49d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -0,0 +1,141 @@
+/*
+ * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_soc {
+        i2c@3100 {
+                rtc@68 {
+                        compatible = "dallas,ds3232";
+                        reg = <0x68>;
+                        interrupts = <0 0x1 0 0>;
+                };
+        };
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>;
+                        partition@u-boot {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00100000>;
+                                read-only;
+                        };
+                        partition@kernel {
+                                label = "kernel";
+                                reg = <0x00100000 0x00500000>;
+                                read-only;
+                        };
+                        partition@dtb {
+                                label = "dtb";
+                                reg = <0x00600000 0x00100000>;
+                                read-only;
+                        };
+                        partition@fs {
+                                label = "file system";
+                                reg = <0x00700000 0x00900000>;
+                        };
+                };
+                flash@1 {
+                        compatible = "spansion,s25sl12801";
+                        reg = <1>;
+                        spi-max-frequency = <40000000>;
+                };
+                flash@2 {
+                        compatible = "spansion,s25sl12801";
+                        reg = <2>;
+                        spi-max-frequency = <40000000>;
+                };
+                flash@3 {
+                        compatible = "spansion,s25sl12801";
+                        reg = <3>;
+                        spi-max-frequency = <40000000>;
+                };
+        };
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+        usb@23000 {
+                phy_type = "ulpi";
+        };
+        enet0: ethernet@24000 {
+                tbi-handle = <&tbi0>;
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <10 0x1 0 0>;
+                        reg = <0>;
+                        device_type = "ethernet-phy";
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <10 0x1 0 0>;
+                        reg = <1>;
+                        device_type = "ethernet-phy";
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet2: ethernet@26000 {
+                tbi-handle = <&tbi1>;
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@26520 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,gianfar-tbi";
+                reg = <0x26520 0x20>;
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        usb@2b000 {
+                dr_mode = "peripheral";
+                phy_type = "ulpi";
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index d95b26021e62..8f4b929b1d1d 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,5 +1,5 @@
 /*
- * MPC8536 DS Device Tree Source
+ * MPC8536DS Device Tree Source (36-bit address map)
 *
 * Copyright 2008-2009 Freescale Semiconductor, Inc.
 *
@@ -9,24 +9,11 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8536si-pre.dtsi"
 / {
        model = "fsl,mpc8536ds";
        compatible = "fsl,mpc8536ds";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                pci3 = &pci3;
-        };
        cpus {
                #cpus = <1>;
@@ -45,351 +32,34 @@
                reg = <0 0 0 0>;        // Filled by U-Boot
        };
-        soc@fffe00000 {
+        lbc: localbus@ffe05000 {
-                #address-cells = <1>;
+                reg = <0 0xffe05000 0 0x1000>;
-                #size-cells = <1>;
+        };
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xf 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8536-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8536-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 0x2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8536-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 0x2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                        rtc@68 {
-                                compatible = "dallas,ds3232";
-                                reg = <0x68>;
-                                interrupts = <0 0x1>;
-                                interrupt-parent = <&mpic>;
-                        };
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 4>;
-                        ranges = <0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8536-dma-channel",
-                                             "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                usb@22000 {
-                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x22000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
-                        phy_type = "ulpi";
-                };
-                usb@23000 {
-                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x23000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <46 0x2>;
-                        phy_type = "ulpi";
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 0x1>;
-                                        reg = <0>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 0x1>;
-                                        reg = <1>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet1: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                usb@2b000 {
-                        compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x2b000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <60 0x2>;
-                        dr_mode = "peripheral";
-                        phy_type = "ulpi";
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2>;
-                        interrupt-parent = <&mpic>;
-                        clock-frequency = <250000000>;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
-                                     "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x9fe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                sata@18000 {
-                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
-                        reg = <0x18000 0x1000>;
-                        cell-index = <1>;
-                        interrupts = <74 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                sata@19000 {
-                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
-                        reg = <0x19000 0x1000>;
-                        cell-index = <2>;
-                        interrupts = <41 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8548-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                        big-endian;
-                };
-                msi@41600 {
+        board_soc: soc: soc@fffe00000 {
-                        compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
        };
-        pci0: pci@fffe08000 {
+        pci0: pci@ffe08000 {
-                compatible = "fsl,mpc8540-pci";
+                reg = <0xf 0xffe08000 0 0x1000>;
-                device_type = "pci";
+                ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x11 J17 Slot 1 */
-                        0x8800 0 0 1 &mpic 1 1
+                        0x8800 0 0 1 &mpic 1 1 0 0
-                        0x8800 0 0 2 &mpic 2 1
+                        0x8800 0 0 2 &mpic 2 1 0 0
-                        0x8800 0 0 3 &mpic 3 1
+                        0x8800 0 0 3 &mpic 3 1 0 0
-                        0x8800 0 0 4 &mpic 4 1>;
+                        0x8800 0 0 4 &mpic 4 1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 0x2>;
-                bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
-                          0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xf 0xffe08000 0 0x1000>;
        };
-        pci1: pcie@fffe09000 {
+        pci1: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe09000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
                          0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0xf8000000
                                  0x02000000 0 0xf8000000
                                  0 0x08000000
@@ -401,31 +71,10 @@
        };
        pci2: pcie@fffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe0a000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
                          0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0xf8000000
                                  0x02000000 0 0xf8000000
                                  0 0x08000000
@@ -437,32 +86,10 @@
        };
        pci3: pcie@fffe0b000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe0b000 0 0x1000>;
-                bus-range = <0 0xff>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <27 0x2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 8 1
-                        0000 0 0 2 &mpic 9 1
-                        0000 0 0 3 &mpic 10 1
-                        0000 0 0 4 &mpic 11 1
-                        >;
                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
                                  0 0x20000000
@@ -473,3 +100,6 @@
                };
        };
 };
+/include/ "fsl/mpc8536si-post.dtsi"
+/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 8d1bf0fd9268..f99fb110c97f 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -243,7 +243,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -253,7 +253,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 87ff96549fac..0f5e93912799 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -209,7 +209,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -219,7 +219,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index d793968743c9..e934987e882b 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -9,339 +9,52 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8544si-pre.dtsi"
 / {
        model = "MPC8544DS";
        compatible = "MPC8544DS", "MPC85xxDS";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                pci3 = &pci3;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8544@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
-                reg = <0x0 0x0>;        // Filled by U-Boot
+                reg = <0 0 0 0>;        // Filled by U-Boot
        };
-        soc8544@e0000000 {
+        lbc: localbus@e0005000 {
-                #address-cells = <1>;
+                reg = <0 0xe0005000 0 0x1000>;
-                #size-cells = <1>;
+        };
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xe0000000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <10>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8544-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8544-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8544-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2, 256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8544-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8544-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8544-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8544-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "TSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy0>;
-                        tbi-handle = <&tbi0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x0>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x1>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet1: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "TSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy1>;
-                        tbi-handle = <&tbi1>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8548-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xfe>;
-                        fsl,descriptor-types-mask = <0x12b0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
+        board_soc: soc: soc8544@e0000000 {
-                        compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
+                ranges = <0x0 0x0 0xe0000000 0x100000>;
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
        };
        pci0: pci@e0008000 {
-                compatible = "fsl,mpc8540-pci";
+                reg = <0 0xe0008000 0 0x1000>;
-                device_type = "pci";
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x11 J17 Slot 1 */
-                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
-                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
                        /* IDSEL 0x12 J16 Slot 2 */
-                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
-                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
-                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
+                        0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe0008000 0x1000>;
        };
        pci1: pcie@e0009000 {
-                compatible = "fsl,mpc8548-pcie";
+                reg = <0x0 0xe0009000 0x0 0x1000>;
-                device_type = "pci";
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
-                #interrupt-cells = <1>;
+                          0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe0009000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -353,31 +66,10 @@
        };
        pci2: pcie@e000a000 {
-                compatible = "fsl,mpc8548-pcie";
+                reg = <0x0 0xe000a000 0x0 0x1000>;
-                device_type = "pci";
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
-                #interrupt-cells = <1>;
+                          0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe000a000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
-                          0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x10000000
@@ -388,44 +80,11 @@
                };
        };
-        pci3: pcie@e000b000 {
+        board_pci3: pci3: pcie@e000b000 {
-                compatible = "fsl,mpc8548-pcie";
+                reg = <0x0 0xe000b000 0x0 0x1000>;
-                device_type = "pci";
+                ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
-                #interrupt-cells = <1>;
+                          0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe000b000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
-                          0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <27 2>;
-                interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
-                interrupt-map = <
-                        // IDSEL 0x1c  USB
-                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
-                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
-                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
-                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
-                        // IDSEL 0x1d  Audio
-                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-                        // IDSEL 0x1e Legacy
-                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
-                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-                        // IDSEL 0x1f IDE/SATA
-                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
-                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-                >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xb0000000
                                  0x2000000 0x0 0xb0000000
                                  0x0 0x100000
@@ -433,70 +92,14 @@
                                  0x1000000 0x0 0x0
                                  0x1000000 0x0 0x0
                                  0x0 0x100000>;
-                        uli1575@0 {
-                                reg = <0x0 0x0 0x0 0x0 0x0>;
-                                #size-cells = <2>;
-                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0xb0000000
-                                          0x2000000 0x0 0xb0000000
-                                          0x0 0x100000
-                                          0x1000000 0x0 0x0
-                                          0x1000000 0x0 0x0
-                                          0x0 0x100000>;
-                                isa@1e {
-                                        device_type = "isa";
-                                        #interrupt-cells = <2>;
-                                        #size-cells = <1>;
-                                        #address-cells = <2>;
-                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
-                                        ranges = <0x1 0x0
-                                                  0x1000000 0x0 0x0
-                                                  0x1000>;
-                                        interrupt-parent = <&i8259>;
-                                        i8259: interrupt-controller@20 {
-                                                reg = <0x1 0x20 0x2
-                                                       0x1 0xa0 0x2
-                                                       0x1 0x4d0 0x2>;
-                                                interrupt-controller;
-                                                device_type = "interrupt-controller";
-                                                #address-cells = <0>;
-                                                #interrupt-cells = <2>;
-                                                compatible = "chrp,iic";
-                                                interrupts = <9 2>;
-                                                interrupt-parent = <&mpic>;
-                                        };
-                                        i8042@60 {
-                                                #size-cells = <0>;
-                                                #address-cells = <1>;
-                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
-                                                interrupts = <1 3 12 3>;
-                                                interrupt-parent = <&i8259>;
-                                                keyboard@0 {
-                                                        reg = <0x0>;
-                                                        compatible = "pnpPNP,303";
-                                                };
-                                                mouse@1 {
-                                                        reg = <0x1>;
-                                                        compatible = "pnpPNP,f03";
-                                                };
-                                        };
-                                        rtc@70 {
-                                                compatible = "pnpPNP,b00";
-                                                reg = <0x1 0x70 0x2>;
-                                        };
-                                        gpio@400 {
-                                                reg = <0x1 0x400 0x80>;
-                                        };
-                                };
-                        };
                };
        };
 };
+/*
+ * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
+ * for interrupt-map & interrupt-map-mask
+ */
+/include/ "fsl/mpc8544si-post.dtsi"
+/include/ "mpc8544ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
new file mode 100644
index 000000000000..270f64b90f4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -0,0 +1,161 @@
+/*
+ * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_soc {
+        enet0: ethernet@24000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x0>;
+                        device_type = "ethernet-phy";
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x1>;
+                        device_type = "ethernet-phy";
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet2: ethernet@26000 {
+                phy-handle = <&phy1>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@26520 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+};
+&board_pci3 {
+        pcie@0 {
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                interrupt-map = <
+                        // IDSEL 0x1c  USB
+                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
+                        // IDSEL 0x1d  Audio
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+                        // IDSEL 0x1e Legacy
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+                        >;
+                uli1575@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        ranges = <0x2000000 0x0 0xb0000000
+                                  0x2000000 0x0 0xb0000000
+                                  0x0 0x100000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                        isa@1e {
+                                device_type = "isa";
+                                #interrupt-cells = <2>;
+                                #size-cells = <1>;
+                                #address-cells = <2>;
+                                reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                          0x1000>;
+                                interrupt-parent = <&i8259>;
+                                i8259: interrupt-controller@20 {
+                                        reg = <0x1 0x20 0x2
+                                               0x1 0xa0 0x2
+                                               0x1 0x4d0 0x2>;
+                                        interrupt-controller;
+                                        device_type = "interrupt-controller";
+                                        #address-cells = <0>;
+                                        #interrupt-cells = <2>;
+                                        compatible = "chrp,iic";
+                                        interrupts = <9 2 0 0>;
+                                        interrupt-parent = <&mpic>;
+                                };
+                                i8042@60 {
+                                        #size-cells = <0>;
+                                        #address-cells = <1>;
+                                        reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                        interrupts = <1 3 12 3>;
+                                        interrupt-parent =
+                                                <&i8259>;
+                                        keyboard@0 {
+                                                reg = <0x0>;
+                                                compatible = "pnpPNP,303";
+                                        };
+                                        mouse@1 {
+                                                reg = <0x1>;
+                                                compatible = "pnpPNP,f03";
+                                        };
+                                };
+                                rtc@70 {
+                                        compatible = "pnpPNP,b00";
+                                        reg = <0x1 0x70 0x2>;
+                                };
+                                gpio@400 {
+                                        reg = <0x1 0x400 0x80>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index a17a5572fb73..07b8dae0f46e 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -9,13 +9,11 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8548si-pre.dtsi"
 / {
        model = "MPC8548CDS";
        compatible = "MPC8548CDS", "MPC85xxCDS";
-        #address-cells = <1>;
-        #size-cells = <1>;
        aliases {
                ethernet0 = &enet0;
@@ -29,76 +27,19 @@
                pci2 = &pci2;
        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8548@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;       //  33 MHz, from uboot
-                        bus-frequency = <0>;    // 166 MHz
-                        clock-frequency = <0>;  // 825 MHz, from uboot
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
-                reg = <0x0 0x8000000>;  // 128M at 0x0
+                reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
        };
-        soc8548@e0000000 {
+        lbc: localbus@e0005000 {
-                #address-cells = <1>;
+                reg = <0 0xe0005000 0 0x1000>;
-                #size-cells = <1>;
+        };
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xe0000000 0x100000>;
-                bus-frequency = <0>;
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <10>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8548-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8548-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
+        soc: soc8548@e0000000 {
-                        compatible = "fsl,mpc8548-l2-cache-controller";
+                ranges = <0 0x0 0xe0000000 0x100000>;
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2, 512K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                        eeprom@50 {
                                compatible = "atmel,24c64";
                                reg = <0x50>;
@@ -116,351 +57,178 @@
                };
                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                        eeprom@50 {
                                compatible = "atmel,24c64";
                                reg = <0x50>;
                        };
                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8548-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8548-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8548-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8548-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
                        tbi-handle = <&tbi0>;
                        phy-handle = <&phy0>;
+                };
-                        mdio@520 {
+                mdio@24520 {
-                                #address-cells = <1>;
+                        phy0: ethernet-phy@0 {
-                                #size-cells = <0>;
+                                interrupts = <5 1 0 0>;
-                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x0>;
-                                reg = <0x520 0x20>;
+                                device_type = "ethernet-phy";
+                        };
-                                phy0: ethernet-phy@0 {
+                        phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
+                                interrupts = <5 1 0 0>;
-                                        interrupts = <5 1>;
+                                reg = <0x1>;
-                                        reg = <0x0>;
+                                device_type = "ethernet-phy";
-                                        device_type = "ethernet-phy";
+                        };
-                                };
+                        phy2: ethernet-phy@2 {
-                                phy1: ethernet-phy@1 {
+                                interrupts = <5 1 0 0>;
-                                        interrupt-parent = <&mpic>;
+                                reg = <0x2>;
-                                        interrupts = <5 1>;
+                                device_type = "ethernet-phy";
-                                        reg = <0x1>;
+                        };
-                                        device_type = "ethernet-phy";
+                        phy3: ethernet-phy@3 {
-                                };
+                                interrupts = <5 1 0 0>;
-                                phy2: ethernet-phy@2 {
+                                reg = <0x3>;
-                                        interrupt-parent = <&mpic>;
+                                device_type = "ethernet-phy";
-                                        interrupts = <5 1>;
+                        };
-                                        reg = <0x2>;
+                        tbi0: tbi-phy@11 {
-                                        device_type = "ethernet-phy";
+                                reg = <0x11>;
-                                };
+                                device_type = "tbi-phy";
-                                phy3: ethernet-phy@3 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <5 1>;
-                                        reg = <0x3>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
                        };
                };
                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
                        tbi-handle = <&tbi1>;
                        phy-handle = <&phy1>;
+                };
-                        mdio@520 {
+                mdio@25520 {
-                                #address-cells = <1>;
+                        tbi1: tbi-phy@11 {
-                                #size-cells = <0>;
+                                reg = <0x11>;
-                                compatible = "fsl,gianfar-tbi";
+                                device_type = "tbi-phy";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
                        };
                };
                enet2: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <2>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
                        tbi-handle = <&tbi2>;
                        phy-handle = <&phy2>;
+                };
-                        mdio@520 {
+                mdio@26520 {
-                                #address-cells = <1>;
+                        tbi2: tbi-phy@11 {
-                                #size-cells = <0>;
+                                reg = <0x11>;
-                                compatible = "fsl,gianfar-tbi";
+                                device_type = "tbi-phy";
-                                reg = <0x520 0x20>;
-                                tbi2: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
                        };
                };
                enet3: ethernet@27000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <3>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x27000 0x1000>;
-                        ranges = <0x0 0x27000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <37 2 38 2 39 2>;
-                        interrupt-parent = <&mpic>;
                        tbi-handle = <&tbi3>;
                        phy-handle = <&phy3>;
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi3: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;   // reg base, size
-                        clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;   // reg base, size
-                        clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
                };
-                global-utilities@e0000 {        //global utilities reg
+                mdio@27520 {
-                        compatible = "fsl,mpc8548-guts";
+                        tbi3: tbi-phy@11 {
-                        reg = <0xe0000 0x1000>;
+                                reg = <0x11>;
-                        fsl,has-rstcr;
+                                device_type = "tbi-phy";
-                };
+                        };
-                crypto@30000 {
-                        compatible = "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xfe>;
-                        fsl,descriptor-types-mask = <0x12b0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
                };
        };
        pci0: pci@e0008000 {
+                reg = <0 0xe0008000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x4 (PCIX Slot 2) */
-                        0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                        /* IDSEL 0x5 (PCIX Slot 3) */
-                        0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-                        0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
-                        0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
-                        0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
+                        0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
                        /* IDSEL 0x6 (PCIX Slot 4) */
-                        0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                        0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                        0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                        0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
+                        0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
                        /* IDSEL 0x8 (PCIX Slot 5) */
-                        0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                        /* IDSEL 0xC (Tsi310 bridge) */
-                        0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                        /* IDSEL 0x14 (Slot 2) */
-                        0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                        /* IDSEL 0x15 (Slot 3) */
-                        0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-                        0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
-                        0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
-                        0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
                        /* IDSEL 0x16 (Slot 4) */
-                        0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                        0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                        0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                        0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
+                        0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
                        /* IDSEL 0x18 (Slot 5) */
-                        0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                        /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
-                        0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+                        0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                bus-range = <0 0>;
-                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
-                          0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe0008000 0x1000>;
-                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
-                device_type = "pci";
                pci_bridge@1c {
                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                        interrupt-map = <
                                /* IDSEL 0x00 (PrPMC Site) */
-                                0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                                0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                                0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                                0000 0x0 0x0 0x4 &mpic 0x3 0x1
+                                0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                                /* IDSEL 0x04 (VIA chip) */
-                                0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                                0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                                0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                                0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
+                                0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
                                /* IDSEL 0x05 (8139) */
-                                0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
                                /* IDSEL 0x06 (Slot 6) */
-                                0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                                0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                                0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                                0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                                0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                                0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
+                                0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
                                /* IDESL 0x07 (Slot 7) */
-                                0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
-                                0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
+                                0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
-                                0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
+                                0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
-                                0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
+                                0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
                        reg = <0xe000 0x0 0x0 0x0 0x0>;
                        #interrupt-cells = <1>;
@@ -492,7 +260,7 @@
                                        #address-cells = <0>;
                                        #interrupt-cells = <2>;
                                        compatible = "chrp,iic";
-                                        interrupts = <0 1>;
+                                        interrupts = <0 1 0 0>;
                                        interrupt-parent = <&mpic>;
                                };
@@ -505,56 +273,25 @@
        };
        pci1: pci@e0009000 {
+                reg = <0 0xe0009000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x15 */
-                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
-                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
+                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-                bus-range = <0 0>;
-                ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
-                          0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe0009000 0x1000>;
-                compatible = "fsl,mpc8540-pci";
-                device_type = "pci";
        };
        pci2: pcie@e000a000 {
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                reg = <0 0xe000a000 0 0x1000>;
-                interrupt-map = <
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
-                        /* IDSEL 0x0 (PEX) */
-                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
-                clock-frequency = <33333333>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe000a000 0x1000>;
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -565,3 +302,5 @@
                };
        };
 };
+/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 5c5614f9eb17..fe10438613d6 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -209,7 +209,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -219,7 +219,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 647daf8e7291..09598bb5d443 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -9,60 +9,25 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8568si-pre.dtsi"
 / {
        model = "MPC8568EMDS";
        compatible = "MPC8568EMDS", "MPC85xxMDS";
-        #address-cells = <1>;
-        #size-cells = <1>;
        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                serial1 = &serial1;
                pci0 = &pci0;
                pci1 = &pci1;
-                rapidio0 = &rio0;
+                rapidio0 = &rio;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8568@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        sleep = <&pmc 0x00008000        // core
-                                 &pmc 0x00004000>;      // timebase
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
        };
        memory {
                device_type = "memory";
-                reg = <0x0 0x10000000>;
+                reg = <0x0 0x0 0x0 0x0>;
        };
-        localbus@e0005000 {
+        lbc: localbus@e0005000 {
-                #address-cells = <2>;
+                reg = <0x0 0xe0005000 0x0 0x1000>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
-                             "simple-bus";
-                reg = <0xe0005000 0x1000>;
-                interrupt-parent = <&mpic>;
-                interrupts = <19 2>;
                ranges = <0x0 0x0 0xfe000000 0x02000000
                          0x1 0x0 0xf8000000 0x00008000
                          0x2 0x0 0xf0000000 0x04000000
@@ -104,288 +69,65 @@
                };
        };
-        soc8568@e0000000 {
+        soc: soc8568@e0000000 {
-                #address-cells = <1>;
+                ranges = <0x0 0x0 0xe0000000 0x100000>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xe0000000 0x100000>;
-                bus-frequency = <0>;
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <10>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8568-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8568-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8568-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2, 512K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
                i2c-sleep-nexus {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "simple-bus";
-                        sleep = <&pmc 0x00000004>;
-                        ranges;
                        i2c@3000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                compatible = "fsl-i2c";
-                                reg = <0x3000 0x100>;
-                                interrupts = <43 2>;
-                                interrupt-parent = <&mpic>;
-                                dfsrr;
                                rtc@68 {
                                        compatible = "dallas,ds1374";
                                        reg = <0x68>;
-                                        interrupts = <3 1>;
+                                        interrupts = <3 1 0 0>;
-                                        interrupt-parent = <&mpic>;
                                };
                        };
+                };
-                        i2c@3100 {
+                enet0: ethernet@24000 {
-                                #address-cells = <1>;
+                        tbi-handle = <&tbi0>;
-                                #size-cells = <0>;
+                        phy-handle = <&phy2>;
-                                cell-index = <1>;
-                                compatible = "fsl-i2c";
-                                reg = <0x3100 0x100>;
-                                interrupts = <43 2>;
-                                interrupt-parent = <&mpic>;
-                                dfsrr;
-                        };
                };
-                dma@21300 {
+                mdio@24520 {
-                        #address-cells = <1>;
+                        phy0: ethernet-phy@7 {
-                        #size-cells = <1>;
+                                interrupts = <1 1 0 0>;
-                        compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
+                                reg = <0x7>;
-                        reg = <0x21300 0x4>;
+                                device_type = "ethernet-phy";
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        sleep = <&pmc 0x00000400>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8568-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
                        };
-                        dma-channel@80 {
+                        phy1: ethernet-phy@1 {
-                                compatible = "fsl,mpc8568-dma-channel",
+                                interrupts = <2 1 0 0>;
-                                                "fsl,eloplus-dma-channel";
+                                reg = <0x1>;
-                                reg = <0x80 0x80>;
+                                device_type = "ethernet-phy";
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
                        };
-                        dma-channel@100 {
+                        phy2: ethernet-phy@2 {
-                                compatible = "fsl,mpc8568-dma-channel",
+                                interrupts = <1 1 0 0>;
-                                                "fsl,eloplus-dma-channel";
+                                reg = <0x2>;
-                                reg = <0x100 0x80>;
+                                device_type = "ethernet-phy";
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
                        };
-                        dma-channel@180 {
+                        phy3: ethernet-phy@3 {
-                                compatible = "fsl,mpc8568-dma-channel",
+                                interrupts = <2 1 0 0>;
-                                                "fsl,eloplus-dma-channel";
+                                reg = <0x3>;
-                                reg = <0x180 0x80>;
+                                device_type = "ethernet-phy";
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
                        };
-                };
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
-                enet0: ethernet@24000 {
+                                device_type = "tbi-phy";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy2>;
-                        sleep = <&pmc 0x00000080>;
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@7 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <1 1>;
-                                        reg = <0x7>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <2 1>;
-                                        reg = <0x1>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy2: ethernet-phy@2 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <1 1>;
-                                        reg = <0x2>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy3: ethernet-phy@3 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <2 1>;
-                                        reg = <0x3>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
                        };
                };
                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
                        tbi-handle = <&tbi1>;
                        phy-handle = <&phy3>;
                        sleep = <&pmc 0x00000040>;
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
                };
-                duart-sleep-nexus {
+                mdio@25520 {
-                        #address-cells = <1>;
+                        tbi1: tbi-phy@11 {
-                        #size-cells = <1>;
+                                reg = <0x11>;
-                        compatible = "simple-bus";
+                                device_type = "tbi-phy";
-                        sleep = <&pmc 0x00000002>;
-                        ranges;
-                        serial0: serial@4500 {
-                                cell-index = <0>;
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x4500 0x100>;
-                                clock-frequency = <0>;
-                                interrupts = <42 2>;
-                                interrupt-parent = <&mpic>;
-                        };
-                        serial1: serial@4600 {
-                                cell-index = <1>;
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x4600 0x100>;
-                                clock-frequency = <0>;
-                                interrupts = <42 2>;
-                                interrupt-parent = <&mpic>;
                        };
                };
-                global-utilities@e0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
-                        reg = <0xe0000 0x1000>;
-                        ranges = <0 0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                        pmc: power@70 {
-                                compatible = "fsl,mpc8568-pmc",
-                                             "fsl,mpc8548-pmc";
-                                reg = <0x70 0x20>;
-                        };
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xfe>;
-                        fsl,descriptor-types-mask = <0x12b0ebf>;
-                        sleep = <&pmc 0x01000000>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
                par_io@e0100 {
-                        reg = <0xe0100 0x100>;
-                        device_type = "par_io";
                        num-ports = <7>;
                        pio1: ucc_pin@01 {
@@ -448,57 +190,21 @@
                };
        };
-        qe@e0080000 {
+        qe: qe@e0080000 {
-                #address-cells = <1>;
+                ranges = <0x0 0x0 0xe0080000 0x40000>;
-                #size-cells = <1>;
+                reg = <0x0 0xe0080000 0x0 0x480>;
-                device_type = "qe";
-                compatible = "fsl,qe";
-                ranges = <0x0 0xe0080000 0x40000>;
-                reg = <0xe0080000 0x480>;
-                sleep = <&pmc 0x00000800>;
-                brg-frequency = <0>;
-                bus-frequency = <396000000>;
-                fsl,qe-num-riscs = <2>;
-                fsl,qe-num-snums = <28>;
-                muram@10000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,qe-muram", "fsl,cpm-muram";
-                        ranges = <0x0 0x10000 0x10000>;
-                        data-only@0 {
-                                compatible = "fsl,qe-muram-data",
-                                             "fsl,cpm-muram-data";
-                                reg = <0x0 0x10000>;
-                        };
-                };
                spi@4c0 {
-                        cell-index = <0>;
-                        compatible = "fsl,spi";
-                        reg = <0x4c0 0x40>;
-                        interrupts = <2>;
-                        interrupt-parent = <&qeic>;
                        mode = "cpu";
                };
                spi@500 {
-                        cell-index = <1>;
-                        compatible = "fsl,spi";
-                        reg = <0x500 0x40>;
-                        interrupts = <1>;
-                        interrupt-parent = <&qeic>;
                        mode = "cpu";
                };
                enet2: ucc@2000 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <1>;
-                        reg = <0x2000 0x200>;
-                        interrupts = <32>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk16";
@@ -510,10 +216,6 @@
                enet3: ucc@3000 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <2>;
-                        reg = <0x3000 0x200>;
-                        interrupts = <33>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk16";
@@ -532,102 +234,57 @@
                         * gianfar's MDIO bus */
                        qe_phy0: ethernet-phy@07 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <1 1>;
+                                interrupts = <1 1 0 0>;
                                reg = <0x7>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy1: ethernet-phy@01 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
+                                interrupts = <2 1 0 0>;
                                reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy2: ethernet-phy@02 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <1 1>;
+                                interrupts = <1 1 0 0>;
                                reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy3: ethernet-phy@03 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
+                                interrupts = <2 1 0 0>;
                                reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
-                qeic: interrupt-controller@80 {
-                        interrupt-controller;
-                        compatible = "fsl,qe-ic";
-                        #address-cells = <0>;
-                        #interrupt-cells = <1>;
-                        reg = <0x80 0x80>;
-                        big-endian;
-                        interrupts = <46 2 46 2>; //high:30 low:30
-                        interrupt-parent = <&mpic>;
-                };
        };
        pci0: pci@e0008000 {
+                reg = <0x0 0xe0008000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x12 AD18 */
-                        0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
+                        0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
-                        0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
-                        0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
-                        0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
                        /* IDSEL 0x13 AD19 */
-                        0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
+                        0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
-                        0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
-                        0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
-                        0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
+                        0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
-                sleep = <&pmc 0x80000000>;
-                clock-frequency = <66666666>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe0008000 0x1000>;
-                compatible = "fsl,mpc8540-pci";
-                device_type = "pci";
        };
        /* PCI Express */
        pci1: pcie@e000a000 {
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
-                interrupt-map = <
+                          0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
+                reg = <0x0 0xe000a000 0x0 0x1000>;
-                        /* IDSEL 0x0 (PEX) */
-                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
-                          0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
-                sleep = <&pmc 0x20000000>;
-                clock-frequency = <33333333>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe000a000 0x1000>;
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x10000000
@@ -638,22 +295,11 @@
                };
        };
-        rio0: rapidio@e00c00000 {
+        rio: rapidio@e00c00000 {
-                #address-cells = <2>;
+                reg = <0x0 0xe00c0000 0x0 0x20000>;
-                #size-cells = <2>;
+                port1 {
-                compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
+                        ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
-                reg = <0xe00c0000 0x20000>;
+                };
-                ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
-                interrupts = <48 2 /* error     */
-                              49 2 /* bell_outb */
-                              50 2 /* bell_inb  */
-                              53 2 /* msg1_tx   */
-                              54 2 /* msg1_rx   */
-                              55 2 /* msg2_tx   */
-                              56 2 /* msg2_rx   */>;
-                interrupt-parent = <&mpic>;
-                sleep = <&pmc 0x00080000   /* controller */
-                         &pmc 0x00040000>; /* message unit */
        };
        leds {
@@ -672,3 +318,5 @@
                };
        };
 };
+/include/ "fsl/mpc8568si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 8b72eaff5b03..7e283c891b7f 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -9,66 +9,36 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8569si-pre.dtsi"
 / {
        model = "MPC8569EMDS";
        compatible = "fsl,MPC8569EMDS";
-        #address-cells = <1>;
+        #address-cells = <2>;
-        #size-cells = <1>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
        aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
                ethernet2 = &enet2;
                ethernet3 = &enet3;
                ethernet5 = &enet5;
                ethernet7 = &enet7;
-                pci1 = &pci1;
+                rapidio0 = &rio;
-                rapidio0 = &rio0;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8569@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        sleep = <&pmc 0x00008000        // core
-                                 &pmc 0x00004000>;      // timebase
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
        };
        memory {
                device_type = "memory";
        };
-        localbus@e0005000 {
+        lbc: localbus@e0005000 {
-                #address-cells = <2>;
+                reg = <0x0 0xe0005000 0x0 0x1000>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+                ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
-                reg = <0xe0005000 0x1000>;
+                          0x1 0x0 0x0 0xf8000000 0x00008000
-                interrupts = <19 2>;
+                          0x2 0x0 0x0 0xf0000000 0x04000000
-                interrupt-parent = <&mpic>;
+                          0x3 0x0 0x0 0xfc000000 0x00008000
-                sleep = <&pmc 0x08000000>;
+                          0x4 0x0 0x0 0xf8008000 0x00008000
+                          0x5 0x0 0x0 0xf8010000 0x00008000>;
-                ranges = <0x0 0x0 0xfe000000 0x02000000
-                          0x1 0x0 0xf8000000 0x00008000
-                          0x2 0x0 0xf0000000 0x04000000
-                          0x3 0x0 0xfc000000 0x00008000
-                          0x4 0x0 0xf8008000 0x00008000
-                          0x5 0x0 0xf8010000 0x00008000>;
                nor@0,0 {
                        #address-cells = <1>;
@@ -133,220 +103,25 @@
                };
        };
-        soc@e0000000 {
+        soc: soc@e0000000 {
-                #address-cells = <1>;
+                ranges = <0x0 0x0 0xe0000000 0x100000>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,mpc8569-immr", "simple-bus";
-                ranges = <0x0 0xe0000000 0x100000>;
-                bus-frequency = <0>;
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <10>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8569-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8569-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
                i2c-sleep-nexus {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "simple-bus";
-                        sleep = <&pmc 0x00000004>;
-                        ranges;
                        i2c@3000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                compatible = "fsl-i2c";
-                                reg = <0x3000 0x100>;
-                                interrupts = <43 2>;
-                                interrupt-parent = <&mpic>;
-                                dfsrr;
                                rtc@68 {
                                        compatible = "dallas,ds1374";
                                        reg = <0x68>;
-                                        interrupts = <3 1>;
+                                        interrupts = <3 1 0 0>;
-                                        interrupt-parent = <&mpic>;
                                };
                        };
-                        i2c@3100 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <1>;
-                                compatible = "fsl-i2c";
-                                reg = <0x3100 0x100>;
-                                interrupts = <43 2>;
-                                interrupt-parent = <&mpic>;
-                                dfsrr;
-                        };
-                };
-                duart-sleep-nexus {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "simple-bus";
-                        sleep = <&pmc 0x00000002>;
-                        ranges;
-                        serial0: serial@4500 {
-                                cell-index = <0>;
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x4500 0x100>;
-                                clock-frequency = <0>;
-                                interrupts = <42 2>;
-                                interrupt-parent = <&mpic>;
-                        };
-                        serial1: serial@4600 {
-                                cell-index = <1>;
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x4600 0x100>;
-                                clock-frequency = <0>;
-                                interrupts = <42 2>;
-                                interrupt-parent = <&mpic>;
-                        };
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8569-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2, 512K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
                };
-                dma@21300 {
+                sdhc@2e000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8569-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8569-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8569-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8569-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x8>;
-                        interrupt-parent = <&mpic>;
-                        sleep = <&pmc 0x00200000>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
                        status = "disabled";
                        sdhci,1-bit-only;
                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
-                                "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xbfe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                        sleep = <&pmc 0x01000000>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
-                        reg = <0xe0000 0x1000>;
-                        ranges = <0 0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                        pmc: power@70 {
-                                compatible = "fsl,mpc8569-pmc",
-                                             "fsl,mpc8548-pmc";
-                                reg = <0x70 0x20>;
-                        };
-                };
                par_io@e0100 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0xe0100 0x100>;
-                        ranges = <0x0 0xe0100 0x100>;
-                        device_type = "par_io";
                        num-ports = <7>;
                        qe_pio_e: gpio-controller@80 {
@@ -447,47 +222,11 @@
                };
        };
-        qe@e0080000 {
+        qe: qe@e0080000 {
-                #address-cells = <1>;
+                ranges = <0x0 0x0 0xe0080000 0x40000>;
-                #size-cells = <1>;
+                reg = <0x0 0xe0080000 0x0 0x480>;
-                device_type = "qe";
-                compatible = "fsl,qe";
-                ranges = <0x0 0xe0080000 0x40000>;
-                reg = <0xe0080000 0x480>;
-                sleep = <&pmc 0x00000800>;
-                brg-frequency = <0>;
-                bus-frequency = <0>;
-                fsl,qe-num-riscs = <4>;
-                fsl,qe-num-snums = <46>;
-                qeic: interrupt-controller@80 {
-                        interrupt-controller;
-                        compatible = "fsl,qe-ic";
-                        #address-cells = <0>;
-                        #interrupt-cells = <1>;
-                        reg = <0x80 0x80>;
-                        interrupts = <46 2 46 2>; //high:30 low:30
-                        interrupt-parent = <&mpic>;
-                };
-                timer@440 {
-                        compatible = "fsl,mpc8569-qe-gtm",
-                                     "fsl,qe-gtm", "fsl,gtm";
-                        reg = <0x440 0x40>;
-                        interrupts = <12 13 14 15>;
-                        interrupt-parent = <&qeic>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                };
                spi@4c0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
-                        reg = <0x4c0 0x40>;
-                        cell-index = <0>;
-                        interrupts = <2>;
-                        interrupt-parent = <&qeic>;
                        gpios = <&qe_pio_e 30 0>;
                        mode = "cpu-qe";
@@ -499,20 +238,10 @@
                };
                spi@500 {
-                        cell-index = <1>;
-                        compatible = "fsl,spi";
-                        reg = <0x500 0x40>;
-                        interrupts = <1>;
-                        interrupt-parent = <&qeic>;
                        mode = "cpu";
                };
                usb@6c0 {
-                        compatible = "fsl,mpc8569-qe-usb",
-                                     "fsl,mpc8323-qe-usb";
-                        reg = <0x6c0 0x40 0x8b00 0x100>;
-                        interrupts = <11>;
-                        interrupt-parent = <&qeic>;
                        fsl,fullspeed-clock = "clk5";
                        fsl,lowspeed-clock = "brg10";
                        gpios = <&qe_pio_f 3 0   /* USBOE */
@@ -527,10 +256,6 @@
                enet0: ucc@2000 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <1>;
-                        reg = <0x2000 0x200>;
-                        interrupts = <32>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk12";
@@ -548,35 +273,33 @@
                        qe_phy0: ethernet-phy@07 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <1 1>;
+                                interrupts = <1 1 0 0>;
                                reg = <0x7>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy1: ethernet-phy@01 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
+                                interrupts = <2 1 0 0>;
                                reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy2: ethernet-phy@02 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
+                                interrupts = <3 1 0 0>;
                                reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy3: ethernet-phy@03 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <4 1>;
+                                interrupts = <4 1 0 0>;
                                reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy5: ethernet-phy@04 {
-                                interrupt-parent = <&mpic>;
                                reg = <0x04>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy7: ethernet-phy@06 {
-                                interrupt-parent = <&mpic>;
                                reg = <0x6>;
                                device_type = "ethernet-phy";
                        };
@@ -610,10 +333,6 @@
                enet2: ucc@2200 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <3>;
-                        reg = <0x2200 0x200>;
-                        interrupts = <34>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk12";
@@ -637,10 +356,6 @@
                enet1: ucc@3000 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <2>;
-                        reg = <0x3000 0x200>;
-                        interrupts = <33>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk17";
@@ -664,10 +379,6 @@
                enet3: ucc@3200 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <4>;
-                        reg = <0x3200 0x200>;
-                        interrupts = <35>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk17";
@@ -691,10 +402,6 @@
                enet5: ucc@3400 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <6>;
-                        reg = <0x3400 0x200>;
-                        interrupts = <41>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "none";
@@ -706,10 +413,6 @@
                enet7: ucc@3600 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <8>;
-                        reg = <0x3600 0x200>;
-                        interrupts = <43>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "none";
@@ -717,50 +420,14 @@
                        phy-handle = <&qe_phy7>;
                        phy-connection-type = "sgmii";
                };
-                muram@10000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,qe-muram", "fsl,cpm-muram";
-                        ranges = <0x0 0x10000 0x20000>;
-                        data-only@0 {
-                                compatible = "fsl,qe-muram-data",
-                                             "fsl,cpm-muram-data";
-                                reg = <0x0 0x20000>;
-                        };
-                };
        };
        /* PCI Express */
        pci1: pcie@e000a000 {
-                compatible = "fsl,mpc8548-pcie";
+                reg = <0x0 0xe000a000 0x0 0x1000>;
-                device_type = "pci";
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
-                #interrupt-cells = <1>;
+                          0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xe000a000 0x1000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 (PEX) */
-                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
-                          0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
-                sleep = <&pmc 0x20000000>;
-                clock-frequency = <33333333>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x10000000
@@ -771,20 +438,15 @@
                };
        };
-        rio0: rapidio@e00c00000 {
+        rio: rapidio@e00c00000 {
-                #address-cells = <2>;
+                reg = <0x0 0xe00c0000 0x0 0x20000>;
-                #size-cells = <2>;
+                port1 {
-                compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
+                        ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
-                reg = <0xe00c0000 0x20000>;
+                };
-                ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
+                port2 {
-                interrupts = <48 2 /* error     */
+                        status = "disabled";
-                              49 2 /* bell_outb */
+                };
-                              50 2 /* bell_inb  */
-                              53 2 /* msg1_tx   */
-                              54 2 /* msg1_rx   */
-                              55 2 /* msg2_tx   */
-                              56 2 /* msg2_rx   */>;
-                interrupt-parent = <&mpic>;
-                sleep = <&pmc 0x00080000>;
        };
 };
+/include/ "fsl/mpc8569si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index f6c04d25e916..0c9f2955deb4 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -9,67 +9,18 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8572si-pre.dtsi"
 / {
        model = "fsl,MPC8572DS";
        compatible = "fsl,MPC8572DS";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8572@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,8572@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
        };
-        localbus@ffe05000 {
+        board_lbc: lbc: localbus@ffe05000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
                reg = <0 0xffe05000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
                ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
                          0x1 0x0 0x0 0xe0000000 0x08000000
@@ -78,601 +29,17 @@
                          0x4 0x0 0x0 0xffa40000 0x00040000
                          0x5 0x0 0x0 0xffa80000 0x00040000
                          0x6 0x0 0x0 0xffac0000 0x00040000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x8000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        ramdisk@0 {
-                                reg = <0x0 0x03000000>;
-                                read-only;
-                        };
-                        diagnostic@3000000 {
-                                reg = <0x03000000 0x00e00000>;
-                                read-only;
-                        };
-                        dink@3e00000 {
-                                reg = <0x03e00000 0x00200000>;
-                                read-only;
-                        };
-                        kernel@4000000 {
-                                reg = <0x04000000 0x00400000>;
-                                read-only;
-                        };
-                        jffs2@4400000 {
-                                reg = <0x04400000 0x03b00000>;
-                        };
-                        dtb@7f00000 {
-                                reg = <0x07f00000 0x00080000>;
-                                read-only;
-                        };
-                        u-boot@7f80000 {
-                                reg = <0x07f80000 0x00080000>;
-                                read-only;
-                        };
-                };
-                nand@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x2 0x0 0x40000>;
-                        u-boot@0 {
-                                reg = <0x0 0x02000000>;
-                                read-only;
-                        };
-                        jffs2@2000000 {
-                                reg = <0x02000000 0x10000000>;
-                        };
-                        ramdisk@12000000 {
-                                reg = <0x12000000 0x08000000>;
-                                read-only;
-                        };
-                        kernel@1a000000 {
-                                reg = <0x1a000000 0x04000000>;
-                        };
-                        dtb@1e000000 {
-                                reg = <0x1e000000 0x01000000>;
-                                read-only;
-                        };
-                        empty@1f000000 {
-                                reg = <0x1f000000 0x21000000>;
-                        };
-                };
-                nand@4,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x4 0x0 0x40000>;
-                };
-                nand@5,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x5 0x0 0x40000>;
-                };
-                nand@6,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x6 0x0 0x40000>;
-                };
        };
-        soc8572@ffe00000 {
+        board_soc: soc: soc8572@ffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
                ranges = <0x0 0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                memory-controller@6000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x6000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8572-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x100000>; // L2, 1M
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                dma@c300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
-                        reg = <0xc300 0x4>;
-                        ranges = <0x0 0xc100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <76 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <77 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <78 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <79 2>;
-                        };
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                ptp_clock@24E00 {
-                        compatible = "fsl,etsec-ptp";
-                        reg = <0x24E00 0xB0>;
-                        interrupts = <68 2 69 2 70 2 71 2>;
-                        interrupt-parent = < &mpic >;
-                        fsl,tclk-period = <5>;
-                        fsl,tmr-prsc = <200>;
-                        fsl,tmr-add = <0xAAAAAAAB>;
-                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
-                        fsl,tmr-fiper2 = <0x3B9AC9FB>;
-                        fsl,max-adj = <499999999>;
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x0>;
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x1>;
-                                };
-                                phy2: ethernet-phy@2 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x2>;
-                                };
-                                phy3: ethernet-phy@3 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x3>;
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet2: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <2>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi2>;
-                        phy-handle = <&phy2>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi2: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet3: ethernet@27000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <3>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x27000 0x1000>;
-                        ranges = <0x0 0x27000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <37 2 38 2 39 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi3>;
-                        phy-handle = <&phy3>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi3: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8572-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                msi@41600 {
-                        compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
-                                     "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x9fe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
        };
-        pci0: pcie@ffe08000 {
+        board_pci0: pci0: pcie@ffe08000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe08000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x11 func 0 - PCI slot 1 */
-                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 1 - PCI slot 1 */
-                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 2 - PCI slot 1 */
-                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 3 - PCI slot 1 */
-                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 4 - PCI slot 1 */
-                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 5 - PCI slot 1 */
-                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 6 - PCI slot 1 */
-                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 7 - PCI slot 1 */
-                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x12 func 0 - PCI slot 2 */
-                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 1 - PCI slot 2 */
-                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 2 - PCI slot 2 */
-                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 3 - PCI slot 2 */
-                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 4 - PCI slot 2 */
-                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 5 - PCI slot 2 */
-                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 6 - PCI slot 2 */
-                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 7 - PCI slot 2 */
-                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
-                        // IDSEL 0x1c  USB
-                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
-                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
-                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
-                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
-                        // IDSEL 0x1d  Audio
-                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-                        // IDSEL 0x1e Legacy
-                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
-                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-                        // IDSEL 0x1f IDE/SATA
-                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
-                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -680,99 +47,14 @@
                                  0x1000000 0x0 0x0
                                  0x1000000 0x0 0x0
                                  0x0 0x10000>;
-                        uli1575@0 {
-                                reg = <0x0 0x0 0x0 0x0 0x0>;
-                                #size-cells = <2>;
-                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0x80000000
-                                          0x2000000 0x0 0x80000000
-                                          0x0 0x20000000
-                                          0x1000000 0x0 0x0
-                                          0x1000000 0x0 0x0
-                                          0x0 0x10000>;
-                                isa@1e {
-                                        device_type = "isa";
-                                        #interrupt-cells = <2>;
-                                        #size-cells = <1>;
-                                        #address-cells = <2>;
-                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
-                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
-                                                  0x1000>;
-                                        interrupt-parent = <&i8259>;
-                                        i8259: interrupt-controller@20 {
-                                                reg = <0x1 0x20 0x2
-                                                       0x1 0xa0 0x2
-                                                       0x1 0x4d0 0x2>;
-                                                interrupt-controller;
-                                                device_type = "interrupt-controller";
-                                                #address-cells = <0>;
-                                                #interrupt-cells = <2>;
-                                                compatible = "chrp,iic";
-                                                interrupts = <9 2>;
-                                                interrupt-parent = <&mpic>;
-                                        };
-                                        i8042@60 {
-                                                #size-cells = <0>;
-                                                #address-cells = <1>;
-                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
-                                                interrupts = <1 3 12 3>;
-                                                interrupt-parent =
-                                                        <&i8259>;
-                                                keyboard@0 {
-                                                        reg = <0x0>;
-                                                        compatible = "pnpPNP,303";
-                                                };
-                                                mouse@1 {
-                                                        reg = <0x1>;
-                                                        compatible = "pnpPNP,f03";
-                                                };
-                                        };
-                                        rtc@70 {
-                                                compatible = "pnpPNP,b00";
-                                                reg = <0x1 0x70 0x2>;
-                                        };
-                                        gpio@400 {
-                                                reg = <0x1 0x400 0x80>;
-                                        };
-                                };
-                        };
                };
        };
        pci1: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -784,31 +66,10 @@
        };
        pci2: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xc0000000
                                  0x2000000 0x0 0xc0000000
                                  0x0 0x20000000
@@ -819,3 +80,11 @@
                };
        };
 };
+/*
+ * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask
+ */
+/include/ "fsl/mpc8572si-post.dtsi"
+/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
new file mode 100644
index 000000000000..c3d4fac0532a
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -0,0 +1,397 @@
+/*
+ * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+                ramdisk@0 {
+                        reg = <0x0 0x03000000>;
+                        read-only;
+                };
+                diagnostic@3000000 {
+                        reg = <0x03000000 0x00e00000>;
+                        read-only;
+                };
+                dink@3e00000 {
+                        reg = <0x03e00000 0x00200000>;
+                        read-only;
+                };
+                kernel@4000000 {
+                        reg = <0x04000000 0x00400000>;
+                        read-only;
+                };
+                jffs2@4400000 {
+                        reg = <0x04400000 0x03b00000>;
+                };
+                dtb@7f00000 {
+                        reg = <0x07f00000 0x00080000>;
+                        read-only;
+                };
+                u-boot@7f80000 {
+                        reg = <0x07f80000 0x00080000>;
+                        read-only;
+                };
+        };
+        nand@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8572-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x2 0x0 0x40000>;
+                u-boot@0 {
+                        reg = <0x0 0x02000000>;
+                        read-only;
+                };
+                jffs2@2000000 {
+                        reg = <0x02000000 0x10000000>;
+                };
+                ramdisk@12000000 {
+                        reg = <0x12000000 0x08000000>;
+                        read-only;
+                };
+                kernel@1a000000 {
+                        reg = <0x1a000000 0x04000000>;
+                };
+                dtb@1e000000 {
+                        reg = <0x1e000000 0x01000000>;
+                        read-only;
+                };
+                empty@1f000000 {
+                        reg = <0x1f000000 0x21000000>;
+                };
+        };
+        nand@4,0 {
+                compatible = "fsl,mpc8572-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x4 0x0 0x40000>;
+        };
+        nand@5,0 {
+                compatible = "fsl,mpc8572-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x5 0x0 0x40000>;
+        };
+        nand@6,0 {
+                compatible = "fsl,mpc8572-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x6 0x0 0x40000>;
+        };
+};
+&board_soc {
+        enet0: ethernet@24000 {
+                tbi-handle = <&tbi0>;
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x2>;
+                };
+                phy3: ethernet-phy@3 {
+                        interrupts = <10 1 0 0>;
+                        reg = <0x3>;
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        ptp_clock@24e00 {
+                fsl,tclk-period = <5>;
+                fsl,tmr-prsc = <200>;
+                fsl,tmr-add = <0xAAAAAAAB>;
+                fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                fsl,tmr-fiper2 = <0x3B9AC9FB>;
+                fsl,max-adj = <499999999>;
+        };
+        enet1: ethernet@25000 {
+                tbi-handle = <&tbi1>;
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@25520 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet2: ethernet@26000 {
+                tbi-handle = <&tbi2>;
+                phy-handle = <&phy2>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@26520 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet3: ethernet@27000 {
+                tbi-handle = <&tbi3>;
+                phy-handle = <&phy3>;
+                phy-connection-type = "rgmii-id";
+        };
+        mdio@27520 {
+                tbi3: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+};
+&board_pci0 {
+        pcie@0 {
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x11 func 0 - PCI slot 1 */
+                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 1 - PCI slot 1 */
+                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 2 - PCI slot 1 */
+                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 3 - PCI slot 1 */
+                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 4 - PCI slot 1 */
+                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 5 - PCI slot 1 */
+                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 6 - PCI slot 1 */
+                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x11 func 7 - PCI slot 1 */
+                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+                        /* IDSEL 0x12 func 0 - PCI slot 2 */
+                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 1 - PCI slot 2 */
+                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 2 - PCI slot 2 */
+                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 3 - PCI slot 2 */
+                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 4 - PCI slot 2 */
+                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 5 - PCI slot 2 */
+                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 6 - PCI slot 2 */
+                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        /* IDSEL 0x12 func 7 - PCI slot 2 */
+                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
+                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
+                        // IDSEL 0x1c  USB
+                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
+                        // IDSEL 0x1d  Audio
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+                        // IDSEL 0x1e Legacy
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+                        >;
+                uli1575@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                        isa@1e {
+                                device_type = "isa";
+                                #interrupt-cells = <2>;
+                                #size-cells = <1>;
+                                #address-cells = <2>;
+                                reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                          0x1000>;
+                                interrupt-parent = <&i8259>;
+                                i8259: interrupt-controller@20 {
+                                        reg = <0x1 0x20 0x2
+                                               0x1 0xa0 0x2
+                                               0x1 0x4d0 0x2>;
+                                        interrupt-controller;
+                                        device_type = "interrupt-controller";
+                                        #address-cells = <0>;
+                                        #interrupt-cells = <2>;
+                                        compatible = "chrp,iic";
+                                        interrupts = <9 2 0 0>;
+                                        interrupt-parent = <&mpic>;
+                                };
+                                i8042@60 {
+                                        #size-cells = <0>;
+                                        #address-cells = <1>;
+                                        reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                        interrupts = <1 3 12 3>;
+                                        interrupt-parent =
+                                                <&i8259>;
+                                        keyboard@0 {
+                                                reg = <0x0>;
+                                                compatible = "pnpPNP,303";
+                                        };
+                                        mouse@1 {
+                                                reg = <0x1>;
+                                                compatible = "pnpPNP,f03";
+                                        };
+                                };
+                                rtc@70 {
+                                        compatible = "pnpPNP,b00";
+                                        reg = <0x1 0x70 0x2>;
+                                };
+                                gpio@400 {
+                                        reg = <0x1 0x400 0x80>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
index f6365db3b97d..6c3d0b305e1b 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -1,5 +1,5 @@
 /*
- * MPC8572 DS Device Tree Source
+ * MPC8572DS Device Tree Source (36-bit address map)
 *
 * Copyright 2007-2009 Freescale Semiconductor Inc.
 *
@@ -9,67 +9,18 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/mpc8572si-pre.dtsi"
 / {
        model = "fsl,MPC8572DS";
        compatible = "fsl,MPC8572DS";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,8572@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,8572@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
        };
-        localbus@fffe05000 {
+        board_lbc: lbc: localbus@fffe05000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
                reg = <0xf 0xffe05000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
                          0x1 0x0 0xf 0xe0000000 0x08000000
@@ -78,588 +29,17 @@
                          0x4 0x0 0xf 0xffa40000 0x00040000
                          0x5 0x0 0xf 0xffa80000 0x00040000
                          0x6 0x0 0xf 0xffac0000 0x00040000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x8000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        ramdisk@0 {
-                                reg = <0x0 0x03000000>;
-                                read-only;
-                        };
-                        diagnostic@3000000 {
-                                reg = <0x03000000 0x00e00000>;
-                                read-only;
-                        };
-                        dink@3e00000 {
-                                reg = <0x03e00000 0x00200000>;
-                                read-only;
-                        };
-                        kernel@4000000 {
-                                reg = <0x04000000 0x00400000>;
-                                read-only;
-                        };
-                        jffs2@4400000 {
-                                reg = <0x04400000 0x03b00000>;
-                        };
-                        dtb@7f00000 {
-                                reg = <0x07f00000 0x00080000>;
-                                read-only;
-                        };
-                        u-boot@7f80000 {
-                                reg = <0x07f80000 0x00080000>;
-                                read-only;
-                        };
-                };
-                nand@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x2 0x0 0x40000>;
-                        u-boot@0 {
-                                reg = <0x0 0x02000000>;
-                                read-only;
-                        };
-                        jffs2@2000000 {
-                                reg = <0x02000000 0x10000000>;
-                        };
-                        ramdisk@12000000 {
-                                reg = <0x12000000 0x08000000>;
-                                read-only;
-                        };
-                        kernel@1a000000 {
-                                reg = <0x1a000000 0x04000000>;
-                        };
-                        dtb@1e000000 {
-                                reg = <0x1e000000 0x01000000>;
-                                read-only;
-                        };
-                        empty@1f000000 {
-                                reg = <0x1f000000 0x21000000>;
-                        };
-                };
-                nand@4,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x4 0x0 0x40000>;
-                };
-                nand@5,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x5 0x0 0x40000>;
-                };
-                nand@6,0 {
-                        compatible = "fsl,mpc8572-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x6 0x0 0x40000>;
-                };
        };
-        soc8572@fffe00000 {
+        board_soc: soc: soc8572@fffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
                ranges = <0x0 0xf 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                memory-controller@6000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x6000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8572-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x100000>; // L2, 1M
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                dma@c300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
-                        reg = <0xc300 0x4>;
-                        ranges = <0x0 0xc100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <76 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <77 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <78 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <79 2>;
-                        };
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x0>;
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x1>;
-                                };
-                                phy2: ethernet-phy@2 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x2>;
-                                };
-                                phy3: ethernet-phy@3 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x3>;
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet2: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <2>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi2>;
-                        phy-handle = <&phy2>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi2: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                enet3: ethernet@27000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <3>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x27000 0x1000>;
-                        ranges = <0x0 0x27000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <37 2 38 2 39 2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi3>;
-                        phy-handle = <&phy3>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-                                tbi3: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8572-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                msi@41600 {
-                        compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
-                                     "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x9fe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
        };
-        pci0: pcie@fffe08000 {
+        board_pci0: pci0: pcie@fffe08000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe08000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x11 func 0 - PCI slot 1 */
-                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 1 - PCI slot 1 */
-                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 2 - PCI slot 1 */
-                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 3 - PCI slot 1 */
-                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 4 - PCI slot 1 */
-                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 5 - PCI slot 1 */
-                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 6 - PCI slot 1 */
-                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 7 - PCI slot 1 */
-                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x12 func 0 - PCI slot 2 */
-                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 1 - PCI slot 2 */
-                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 2 - PCI slot 2 */
-                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 3 - PCI slot 2 */
-                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 4 - PCI slot 2 */
-                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 5 - PCI slot 2 */
-                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 6 - PCI slot 2 */
-                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 7 - PCI slot 2 */
-                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
-                        // IDSEL 0x1c  USB
-                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
-                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
-                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
-                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
-                        // IDSEL 0x1d  Audio
-                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-                        // IDSEL 0x1e Legacy
-                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
-                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-                        // IDSEL 0x1f IDE/SATA
-                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
-                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -667,99 +47,14 @@
                                  0x1000000 0x0 0x0
                                  0x1000000 0x0 0x0
                                  0x0 0x10000>;
-                        uli1575@0 {
-                                reg = <0x0 0x0 0x0 0x0 0x0>;
-                                #size-cells = <2>;
-                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0xe0000000
-                                          0x2000000 0x0 0xe0000000
-                                          0x0 0x20000000
-                                          0x1000000 0x0 0x0
-                                          0x1000000 0x0 0x0
-                                          0x0 0x10000>;
-                                isa@1e {
-                                        device_type = "isa";
-                                        #interrupt-cells = <2>;
-                                        #size-cells = <1>;
-                                        #address-cells = <2>;
-                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
-                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
-                                                  0x1000>;
-                                        interrupt-parent = <&i8259>;
-                                        i8259: interrupt-controller@20 {
-                                                reg = <0x1 0x20 0x2
-                                                       0x1 0xa0 0x2
-                                                       0x1 0x4d0 0x2>;
-                                                interrupt-controller;
-                                                device_type = "interrupt-controller";
-                                                #address-cells = <0>;
-                                                #interrupt-cells = <2>;
-                                                compatible = "chrp,iic";
-                                                interrupts = <9 2>;
-                                                interrupt-parent = <&mpic>;
-                                        };
-                                        i8042@60 {
-                                                #size-cells = <0>;
-                                                #address-cells = <1>;
-                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
-                                                interrupts = <1 3 12 3>;
-                                                interrupt-parent =
-                                                        <&i8259>;
-                                                keyboard@0 {
-                                                        reg = <0x0>;
-                                                        compatible = "pnpPNP,303";
-                                                };
-                                                mouse@1 {
-                                                        reg = <0x1>;
-                                                        compatible = "pnpPNP,f03";
-                                                };
-                                        };
-                                        rtc@70 {
-                                                compatible = "pnpPNP,b00";
-                                                reg = <0x1 0x70 0x2>;
-                                        };
-                                        gpio@400 {
-                                                reg = <0x1 0x400 0x80>;
-                                        };
-                                };
-                        };
                };
        };
        pci1: pcie@fffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -771,31 +66,10 @@
        };
        pci2: pcie@fffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -806,3 +80,11 @@
                };
        };
 };
+/*
+ * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask
+ */
+/include/ "fsl/mpc8572si-post.dtsi"
+/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 3375c2ab0c32..d34d12712125 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -14,494 +14,69 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "mpc8572ds.dts"
 / {
        model = "fsl,MPC8572DS";
        compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                serial0 = &serial0;
-                pci0 = &pci0;
-                pci1 = &pci1;
-        };
        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
                PowerPC,8572@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
                };
+                PowerPC,8572@1 {
+                        status = "disabled";
+                };
        };
-        memory {
+        localbus@ffe05000 {
-                device_type = "memory";
+                status = "disabled";
-                reg = <0x0 0x0>;        // Filled by U-Boot
        };
        soc8572@ffe00000 {
-                #address-cells = <1>;
+                serial@4600 {
-                #size-cells = <1>;
+                        status = "disabled";
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
                };
+                dma@c300 {
-                ecm@1000 {
+                        status = "disabled";
-                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
                };
+                gpio-controller@f000 {
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
                };
+                l2-cache-controller@20000 {
-                memory-controller@6000 {
-                        compatible = "fsl,mpc8572-memory-controller";
-                        reg = <0x6000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8572-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
                };
+                ethernet@26000 {
-                i2c@3000 {
+                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                };
+                mdio@26520 {
-                i2c@3100 {
+                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                };
+                ethernet@27000 {
-                dma@21300 {
+                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
                };
+                mdio@27520 {
-                enet0: ethernet@24000 {
+                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@0 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x0>;
-                                };
-                                phy1: ethernet-phy@1 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <10 1>;
-                                        reg = <0x1>;
-                                };
-                        };
                };
+                pic@40000 {
-                enet1: ethernet@25000 {
+                        protected-sources = <
-                        cell-index = <1>;
+                        31 32 33 37 38 39       /* enet2 enet3 */
-                        device_type = "network";
+                        76 77 78 79 26 42       /* dma2 pci2 serial*/
-                        model = "eTSEC";
+                        0xe4 0xe5 0xe6 0xe7     /* msi */
-                        compatible = "gianfar";
+                        >;
-                        reg = <0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
                };
                msi@41600 {
-                        compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
                        msi-available-ranges = <0 0x80>;
                        interrupts = <
                                0xe0 0
                                0xe1 0
                                0xe2 0
                                0xe3 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,mpc8572-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
-                                     "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x9fe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                        protected-sources = <
-                        31 32 33 37 38 39       /* enet2 enet3 */
-                        76 77 78 79 26 42       /* dma2 pci2 serial*/
-                        0xe4 0xe5 0xe6 0xe7     /* msi */
-                        >;
                };
-        };
+                timer@42100 {
+                        status = "disabled";
-        pci0: pcie@ffe08000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xffe08000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x11 func 0 - PCI slot 1 */
-                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 1 - PCI slot 1 */
-                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 2 - PCI slot 1 */
-                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 3 - PCI slot 1 */
-                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 4 - PCI slot 1 */
-                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 5 - PCI slot 1 */
-                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 6 - PCI slot 1 */
-                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x11 func 7 - PCI slot 1 */
-                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
-                        /* IDSEL 0x12 func 0 - PCI slot 2 */
-                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 1 - PCI slot 2 */
-                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 2 - PCI slot 2 */
-                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 3 - PCI slot 2 */
-                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 4 - PCI slot 2 */
-                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 5 - PCI slot 2 */
-                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 6 - PCI slot 2 */
-                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
-                        /* IDSEL 0x12 func 7 - PCI slot 2 */
-                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
-                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
-                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
-                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
-                        // IDSEL 0x1c  USB
-                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
-                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
-                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
-                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
-                        // IDSEL 0x1d  Audio
-                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-                        // IDSEL 0x1e Legacy
-                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
-                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-                        // IDSEL 0x1f IDE/SATA
-                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
-                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x10000>;
-                        uli1575@0 {
-                                reg = <0x0 0x0 0x0 0x0 0x0>;
-                                #size-cells = <2>;
-                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0x80000000
-                                          0x2000000 0x0 0x80000000
-                                          0x0 0x20000000
-                                          0x1000000 0x0 0x0
-                                          0x1000000 0x0 0x0
-                                          0x0 0x10000>;
-                                isa@1e {
-                                        device_type = "isa";
-                                        #interrupt-cells = <2>;
-                                        #size-cells = <1>;
-                                        #address-cells = <2>;
-                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
-                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
-                                                  0x1000>;
-                                        interrupt-parent = <&i8259>;
-                                        i8259: interrupt-controller@20 {
-                                                reg = <0x1 0x20 0x2
-                                                       0x1 0xa0 0x2
-                                                       0x1 0x4d0 0x2>;
-                                                interrupt-controller;
-                                                device_type = "interrupt-controller";
-                                                #address-cells = <0>;
-                                                #interrupt-cells = <2>;
-                                                compatible = "chrp,iic";
-                                                interrupts = <9 2>;
-                                                interrupt-parent = <&mpic>;
-                                        };
-                                        i8042@60 {
-                                                #size-cells = <0>;
-                                                #address-cells = <1>;
-                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
-                                                interrupts = <1 3 12 3>;
-                                                interrupt-parent =
-                                                        <&i8259>;
-                                                keyboard@0 {
-                                                        reg = <0x0>;
-                                                        compatible = "pnpPNP,303";
-                                                };
-                                                mouse@1 {
-                                                        reg = <0x1>;
-                                                        compatible = "pnpPNP,f03";
-                                                };
-                                        };
-                                        rtc@70 {
-                                                compatible = "pnpPNP,b00";
-                                                reg = <0x1 0x70 0x2>;
-                                        };
-                                        gpio@400 {
-                                                reg = <0x1 0x400 0x80>;
-                                        };
-                                };
-                        };
                };
        };
+        pcie@ffe0a000 {
-        pci1: pcie@ffe09000 {
+                status = "disabled";
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xffe09000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x10000>;
-                };
        };
 };
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index e7b477f6a3fe..d6a8fafc0d0d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -15,169 +15,74 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "mpc8572ds.dts"
 / {
        model = "fsl,MPC8572DS";
        compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        aliases {
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                pci2 = &pci2;
-        };
        cpus {
-                #address-cells = <1>;
+                PowerPC,8572@0 {
-                #size-cells = <0>;
+                        status = "disabled";
+                };
                PowerPC,8572@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        d-cache-line-size = <32>;       // 32 bytes
-                        i-cache-line-size = <32>;       // 32 bytes
-                        d-cache-size = <0x8000>;                // L1, 32K
-                        i-cache-size = <0x8000>;                // L1, 32K
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
                };
        };
-        memory {
+        localbus@ffe05000 {
-                device_type = "memory";
+                status = "disabled";
-                reg = <0x0 0x0>;        // Filled by U-Boot
        };
        soc8572@ffe00000 {
-                #address-cells = <1>;
+                ecm-law@0 {
-                #size-cells = <1>;
+                        status = "disabled";
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8572-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2, 512K
-                        interrupt-parent = <&mpic>;
                };
+                ecm@1000 {
-                dma@c300 {
+                        status = "disabled";
-                        #address-cells = <1>;
+                };
-                        #size-cells = <1>;
+                memory-controller@2000 {
-                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                        status = "disabled";
-                        reg = <0xc300 0x4>;
+                };
-                        ranges = <0x0 0xc100 0x200>;
+                memory-controller@6000 {
-                        cell-index = <0>;
+                        status = "disabled";
-                        dma-channel@0 {
+                };
-                                compatible = "fsl,mpc8572-dma-channel",
+                i2c@3000 {
-                                                "fsl,eloplus-dma-channel";
+                        status = "disabled";
-                                reg = <0x0 0x80>;
+                };
-                                cell-index = <0>;
+                i2c@3100 {
-                                interrupt-parent = <&mpic>;
+                        status = "disabled";
-                                interrupts = <76 2>;
+                };
-                        };
+                serial@4500 {
-                        dma-channel@80 {
+                        status = "disabled";
-                                compatible = "fsl,mpc8572-dma-channel",
+                };
-                                                "fsl,eloplus-dma-channel";
+                gpio-controller@f000 {
-                                reg = <0x80 0x80>;
+                        status = "disabled";
-                                cell-index = <1>;
+                };
-                                interrupt-parent = <&mpic>;
+                l2-cache-controller@20000 {
-                                interrupts = <77 2>;
+                        cache-size = <0x80000>; // L2, 512K
-                        };
+                };
-                        dma-channel@100 {
+                dma@21300 {
-                                compatible = "fsl,mpc8572-dma-channel",
+                        status = "disabled";
-                                                "fsl,eloplus-dma-channel";
+                };
-                                reg = <0x100 0x80>;
+                ethernet@24000 {
-                                cell-index = <2>;
+                        status = "disabled";
-                                interrupt-parent = <&mpic>;
-                                interrupts = <78 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8572-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <79 2>;
-                        };
                };
                mdio@24520 {
-                        #address-cells = <1>;
+                        status = "disabled";
-                        #size-cells = <0>;
-                        compatible = "fsl,gianfar-mdio";
-                        reg = <0x24520 0x20>;
-                        phy2: ethernet-phy@2 {
-                                interrupt-parent = <&mpic>;
-                                reg = <0x2>;
-                        };
-                        phy3: ethernet-phy@3 {
-                                interrupt-parent = <&mpic>;
-                                reg = <0x3>;
-                        };
                };
+                ptp_clock@24e00 {
-                enet2: ethernet@26000 {
+                        status = "disabled";
-                        cell-index = <2>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy2>;
-                        phy-connection-type = "rgmii-id";
                };
+                ethernet@25000 {
-                enet3: ethernet@27000 {
+                        status = "disabled";
-                        cell-index = <3>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x27000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <37 2 38 2 39 2>;
-                        interrupt-parent = <&mpic>;
-                        phy-handle = <&phy3>;
-                        phy-connection-type = "rgmii-id";
                };
+                mdio@25520 {
-                msi@41600 {
+                        status = "disabled";
-                        compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0x80 0x80>;
-                        interrupts = <
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
                };
+                crypto@30000 {
-                serial0: serial@4600 {
+                        status = "disabled";
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
                };
+                pic@40000 {
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
                        protected-sources = <
                        18 16 10 42 45 58       /* MEM L2 mdio serial crypto */
                        29 30 34 35 36 40       /* enet0 enet1 */
@@ -189,41 +94,25 @@
                        0xe0 0xe1 0xe2 0xe3     /* msi */
                        >;
                };
-        };
+                timer@41100 {
+                        status = "disabled";
-        pci2: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0xffe0a000 0x1000>;
-                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x10000>;
                };
+                msi@41600 {
+                        msi-available-ranges = <0x80 0x80>;
+                        interrupts = <
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                };
+                global-utilities@e0000 {
+                        status = "disabled";
+                };
+        };
+        pcie@ffe08000 {
+                status = "disabled";
+        };
+        pcie@ffe09000 {
+                status = "disabled";
        };
 };
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 83c3218cb4da..6a109a0ceac9 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -175,7 +175,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -186,7 +186,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 848320e4d3c4..1e8666ccbed8 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -26,13 +26,6 @@
                serial1 = &serial1;
                pci0 = &pci0;
                pci1 = &pci1;
-/*
- * Only one of Rapid IO or PCI can be present due to HW limitations and
- * due to the fact that the 2 now share address space in the new memory
- * map.  The most likely case is that we have PCI, so comment out the
- * rapidio node.  Leave it here for reference.
- */
-                /* rapidio0 = &rapidio0; */
        };
        cpus {
@@ -335,7 +328,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -345,7 +338,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <28 2>;
@@ -361,6 +354,41 @@
                        device_type = "open-pic";
                };
+                rmu: rmu@d3000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,srio-rmu";
+                        reg = <0xd3000 0x500>;
+                        ranges = <0x0 0xd3000 0x500>;
+                        message-unit@0 {
+                                compatible = "fsl,srio-msg-unit";
+                                reg = <0x0 0x100>;
+                                interrupts = <
+                                        53 2 /* msg1_tx_irq */
+                                        54 2>;/* msg1_rx_irq */
+                        };
+                        message-unit@100 {
+                                compatible = "fsl,srio-msg-unit";
+                                reg = <0x100 0x100>;
+                                interrupts = <
+                                        55 2  /* msg2_tx_irq */
+                                        56 2>;/* msg2_rx_irq */
+                        };
+                        doorbell-unit@400 {
+                                compatible = "fsl,srio-dbell-unit";
+                                reg = <0x400 0x80>;
+                                interrupts = <
+                                        49 2  /* bell_outb_irq */
+                                        50 2>;/* bell_inb_irq */
+                        };
+                        port-write-unit@4e0 {
+                                compatible = "fsl,srio-port-write-unit";
+                                reg = <0x4e0 0x20>;
+                                interrupts = <48 2>;
+                        };
+                };
                global-utilities@e0000 {
                        compatible = "fsl,mpc8641-guts";
                        reg = <0xe0000 0x1000>;
@@ -612,16 +640,27 @@
                };
        };
 /*
-        rapidio0: rapidio@ffec0000 {
+ * Only one of Rapid IO or PCI can be present due to HW limitations and
+ * due to the fact that the 2 now share address space in the new memory
+ * map.  The most likely case is that we have PCI, so comment out the
+ * rapidio node.  Leave it here for reference.
+        rapidio@ffec0000 {
+                reg = <0xffec0000 0x11000>;
+                compatible = "fsl,srio";
+                interrupt-parent = <&mpic>;
+                interrupts = <48 2>;
                #address-cells = <2>;
                #size-cells = <2>;
-                compatible = "fsl,rapidio-delta";
+                fsl,srio-rmu-handle = <&rmu>;
-                reg = <0xffec0000 0x20000>;
+                ranges;
-                ranges = <0 0 0x80000000 0 0x20000000>;
-                interrupt-parent = <&mpic>;
+                port1 {
-                // err_irq bell_outb_irq bell_inb_irq
+                        #address-cells = <2>;
-                //      msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
+                        #size-cells = <2>;
-                interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
+                        cell-index = <1>;
+                        ranges = <0 0 0x80000000 0 0x20000000>;
+                };
        };
 */
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
index 8be8e701e1d3..fd4cd4da60b5 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -328,7 +328,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -338,7 +338,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/obs600.dts b/arch/powerpc/boot/dts/obs600.dts
new file mode 100644
index 000000000000..18e7d79ee4c3
--- /dev/null
+++ b/arch/powerpc/boot/dts/obs600.dts
@@ -0,0 +1,314 @@
+/*
+ * Device Tree Source for PlatHome OpenBlockS 600 (405EX)
+ *
+ * Copyright 2011 Ben Herrenschmidt, IBM Corp.
+ *
+ * Based on Kilauea by:
+ *
+ * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        model = "PlatHome,OpenBlockS 600";
+        compatible = "plathome,obs600";
+        dcr-parent = <&{/cpus/cpu@0}>;
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                serial0 = &UART0;
+                serial1 = &UART1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,405EX";
+                        reg = <0x00000000>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+                        timebase-frequency = <0>; /* Filled in by U-Boot */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <16384>; /* 16 kB */
+                        d-cache-size = <16384>; /* 16 kB */
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
+        };
+        UIC0: interrupt-controller {
+                compatible = "ibm,uic-405ex", "ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0x0c0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic-405ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0x0d0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic-405ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0x0e0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+        CPM0: cpm {
+                compatible = "ibm,cpm";
+                dcr-access-method = "native";
+                dcr-reg = <0x0b0 0x003>;
+                unused-units = <0x00000000>;
+                idle-doze = <0x02000000>;
+                standby = <0xe3e74800>;
+        };
+        plb {
+                compatible = "ibm,plb-405ex", "ibm,plb4";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+                SDRAM0: memory-controller {
+                        compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
+                        dcr-reg = <0x010 0x002>;
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <0x5 0x4   /* ECC DED Error */
+                                      0x6 0x4>; /* ECC SEC Error */
+                };
+                CRYPTO: crypto@ef700000 {
+                        compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
+                        reg = <0xef700000 0x80400>;
+                        interrupt-parent = <&UIC0>;
+                        interrupts = <0x17 0x2>;
+                };
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
+                        dcr-reg = <0x180 0x062>;
+                        num-tx-chans = <2>;
+                        num-rx-chans = <2>;
+                        interrupt-parent = <&MAL0>;
+                        interrupts = <0x0 0x1 0x2 0x3 0x4>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
+                                        /*RXEOB*/ 0x1 &UIC0 0xb 0x4
+                                        /*SERR*/  0x2 &UIC1 0x0 0x4
+                                        /*TXDE*/  0x3 &UIC1 0x1 0x4
+                                        /*RXDE*/  0x4 &UIC1 0x2 0x4>;
+                        interrupt-map-mask = <0xffffffff>;
+                };
+                POB0: opb {
+                        compatible = "ibm,opb-405ex", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x80000000 0x80000000 0x10000000
+                                  0xef600000 0xef600000 0x00a00000
+                                  0xf0000000 0xf0000000 0x10000000>;
+                        dcr-reg = <0x0a0 0x005>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+                        EBC0: ebc {
+                                compatible = "ibm,ebc-405ex", "ibm,ebc";
+                                dcr-reg = <0x012 0x002>;
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                /* ranges property is supplied by U-Boot */
+                                interrupts = <0x5 0x1>;
+                                interrupt-parent = <&UIC1>;
+                                nor_flash@0,0 {
+                                        compatible = "amd,s29gl512n", "cfi-flash";
+                                        bank-width = <2>;
+                                        reg = <0x00000000 0x00000000 0x08000000>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        partition@0 {
+                                                label = "kernel + initrd";
+                                                reg = <0x00000000 0x03de0000>;
+                                        };
+                                        partition@3de0000 {
+                                                label = "user config area";
+                                                reg = <0x03de0000 0x00080000>;
+                                        };
+                                        partition@3e60000 {
+                                                label = "user program area";
+                                                reg = <0x03e60000 0x04000000>;
+                                        };
+                                        partition@7e60000 {
+                                                label = "flat device tree";
+                                                reg = <0x07e60000 0x00080000>;
+                                        };
+                                        partition@7ee0000 {
+                                                label = "test program";
+                                                reg = <0x07ee0000 0x00080000>;
+                                        };
+                                        partition@7f60000 {
+                                                label = "u-boot env";
+                                                reg = <0x07f60000 0x00040000>;
+                                        };
+                                        partition@7fa0000 {
+                                                label = "u-boot";
+                                                reg = <0x07fa0000 0x00060000>;
+                                        };
+                                };
+                        };
+                        UART0: serial@ef600200 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600200 0x00000008>;
+                                virtual-reg = <0xef600200>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x1a 0x4>;
+                        };
+                        UART1: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600300 0x00000008>;
+                                virtual-reg = <0xef600300>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x1 0x4>;
+                        };
+                        IIC0: i2c@ef600400 {
+                                compatible = "ibm,iic-405ex", "ibm,iic";
+                                reg = <0xef600400 0x00000014>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "dallas,ds1340";
+                                        reg = <0x68>;
+                                };
+                        };
+                        IIC1: i2c@ef600500 {
+                                compatible = "ibm,iic-405ex", "ibm,iic";
+                                reg = <0xef600500 0x00000014>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x7 0x4>;
+                        };
+                        RGMII0: emac-rgmii@ef600b00 {
+                                compatible = "ibm,rgmii-405ex", "ibm,rgmii";
+                                reg = <0xef600b00 0x00000104>;
+                                has-mdio;
+                        };
+                        EMAC0: ethernet@ef600900 {
+                                linux,network-index = <0x0>;
+                                device_type = "network";
+                                compatible = "ibm,emac-405ex", "ibm,emac4sync";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
+                                                /*Wake*/  0x1 &UIC1 0x1d 0x4>;
+                                reg = <0xef600900 0x000000c4>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+                        EMAC1: ethernet@ef600a00 {
+                                linux,network-index = <0x1>;
+                                device_type = "network";
+                                compatible = "ibm,emac-405ex", "ibm,emac4sync";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
+                                                /*Wake*/  0x1 &UIC1 0x1f 0x4>;
+                                reg = <0xef600a00 0x000000c4>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <1>;
+                                cell-index = <1>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+                        GPIO: gpio@ef600800 {
+                                device_type = "gpio";
+                                compatible = "ibm,gpio-405ex", "ibm,ppc4xx-gpio";
+                                reg = <0xef600800 0x50>;
+                        };
+                };
+        };
+        chosen {
+                linux,stdout-path = "/plb/opb/serial@ef600200";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index d6c669c888e9..b868d22984e9 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -9,230 +9,33 @@
 * option) any later version.
 */
-/include/ "p1010si.dtsi"
+/include/ "fsl/p1010si-pre.dtsi"
 / {
        model = "fsl,P1010RDB";
        compatible = "fsl,P1010RDB";
-        aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                can0 = &can0;
-                can1 = &can1;
-        };
        memory {
                device_type = "memory";
        };
-        ifc@ffe1e000 {
+        board_ifc: ifc: ifc@ffe1e000 {
                /* NOR, NAND Flashes and CPLD on board */
                ranges = <0x0 0x0 0x0 0xee000000 0x02000000
                          0x1 0x0 0x0 0xff800000 0x00010000
                          0x3 0x0 0x0 0xffb00000 0x00000020>;
+                reg = <0x0 0xffe1e000 0 0x2000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x2000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        partition@40000 {
-                                /* 256KB for DTB Image */
-                                reg = <0x00040000 0x00040000>;
-                                label = "NOR DTB Image";
-                        };
-                        partition@80000 {
-                                /* 7 MB for Linux Kernel Image */
-                                reg = <0x00080000 0x00700000>;
-                                label = "NOR Linux Kernel Image";
-                        };
-                        partition@800000 {
-                                /* 20MB for JFFS2 based Root file System */
-                                reg = <0x00800000 0x01400000>;
-                                label = "NOR JFFS2 Root File System";
-                        };
-                        partition@1f00000 {
-                                /* This location must not be altered  */
-                                /* 512KB for u-boot Bootloader Image */
-                                /* 512KB for u-boot Environment Variables */
-                                reg = <0x01f00000 0x00100000>;
-                                label = "NOR U-Boot Image";
-                                read-only;
-                        };
-                };
-                nand@1,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,ifc-nand";
-                        reg = <0x1 0x0 0x10000>;
-                        partition@0 {
-                                /* This location must not be altered  */
-                                /* 1MB for u-boot Bootloader Image */
-                                reg = <0x0 0x00100000>;
-                                label = "NAND U-Boot Image";
-                                read-only;
-                        };
-                        partition@100000 {
-                                /* 1MB for DTB Image */
-                                reg = <0x00100000 0x00100000>;
-                                label = "NAND DTB Image";
-                        };
-                        partition@200000 {
-                                /* 4MB for Linux Kernel Image */
-                                reg = <0x00200000 0x00400000>;
-                                label = "NAND Linux Kernel Image";
-                        };
-                        partition@600000 {
-                                /* 4MB for Compressed Root file System Image */
-                                reg = <0x00600000 0x00400000>;
-                                label = "NAND Compressed RFS Image";
-                        };
-                        partition@a00000 {
-                                /* 15MB for JFFS2 based Root file System */
-                                reg = <0x00a00000 0x00f00000>;
-                                label = "NAND JFFS2 Root File System";
-                        };
-                        partition@1900000 {
-                                /* 7MB for User Area */
-                                reg = <0x01900000 0x00700000>;
-                                label = "NAND User area";
-                        };
-                };
-                cpld@3,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p1010rdb-cpld";
-                        reg = <0x3 0x0 0x0000020>;
-                        bank-width = <1>;
-                        device-width = <1>;
-                };
        };
-        soc@ffe00000 {
+        board_soc: soc: soc@ffe00000 {
-                spi@7000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
-                        flash@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,s25sl12801";
-                                reg = <0>;
-                                spi-max-frequency = <50000000>;
-                                partition@0 {
-                                        /* 1MB for u-boot Bootloader Image */
-                                        /* 1MB for Environment */
-                                        reg = <0x0 0x00100000>;
-                                        label = "SPI Flash U-Boot Image";
-                                        read-only;
-                                };
-                                partition@100000 {
-                                        /* 512KB for DTB Image */
-                                        reg = <0x00100000 0x00080000>;
-                                        label = "SPI Flash DTB Image";
-                                };
-                                partition@180000 {
-                                        /* 4MB for Linux Kernel Image */
-                                        reg = <0x00180000 0x00400000>;
-                                        label = "SPI Flash Linux Kernel Image";
-                                };
-                                partition@580000 {
-                                        /* 4MB for Compressed RFS Image */
-                                        reg = <0x00580000 0x00400000>;
-                                        label = "SPI Flash Compressed RFSImage";
-                                };
-                                partition@980000 {
-                                        /* 6.5MB for JFFS2 based RFS */
-                                        reg = <0x00980000 0x00680000>;
-                                        label = "SPI Flash JFFS2 RFS";
-                                };
-                        };
-                };
-                usb@22000 {
-                        phy_type = "utmi";
-                };
-                mdio@24000 {
-                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x1>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
-                                reg = <0x0>;
-                        };
-                        phy2: ethernet-phy@2 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
-                                reg = <0x2>;
-                        };
-                };
-                enet0: ethernet@b0000 {
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                };
-                enet1: ethernet@b1000 {
-                        phy-handle = <&phy1>;
-                        tbi-handle = <&tbi0>;
-                        phy-connection-type = "sgmii";
-                };
-                enet2: ethernet@b2000 {
-                        phy-handle = <&phy2>;
-                        tbi-handle = <&tbi1>;
-                        phy-connection-type = "sgmii";
-                };
        };
        pci0: pcie@ffe09000 {
+                reg = <0 0xffe09000 0 0x1000>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                        interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -244,24 +47,10 @@
        };
        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                        interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -272,3 +61,6 @@
                };
        };
 };
+/include/ "p1010rdb.dtsi"
+/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
new file mode 100644
index 000000000000..d4c4a7730285
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -0,0 +1,234 @@
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_ifc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x2000000>;
+                bank-width = <2>;
+                device-width = <1>;
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+                partition@80000 {
+                        /* 7 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00700000>;
+                        label = "NOR Linux Kernel Image";
+                };
+                partition@800000 {
+                        /* 20MB for JFFS2 based Root file System */
+                        reg = <0x00800000 0x01400000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+                partition@1f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x01f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,ifc-nand";
+                reg = <0x1 0x0 0x10000>;
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+                partition@a00000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00f00000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+                partition@1900000 {
+                        /* 7MB for User Area */
+                        reg = <0x01900000 0x00700000>;
+                        label = "NAND User area";
+                };
+        };
+        cpld@3,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1010rdb-cpld";
+                reg = <0x3 0x0 0x0000020>;
+                bank-width = <1>;
+                device-width = <1>;
+        };
+};
+&board_soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "pericom,pt7c4338";
+                        reg = <0x68>;
+                };
+        };
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                        partition@0 {
+                                /* 1MB for u-boot Bootloader Image */
+                                /* 1MB for Environment */
+                                reg = <0x0 0x00100000>;
+                                label = "SPI Flash U-Boot Image";
+                                read-only;
+                        };
+                        partition@100000 {
+                                /* 512KB for DTB Image */
+                                reg = <0x00100000 0x00080000>;
+                                label = "SPI Flash DTB Image";
+                        };
+                        partition@180000 {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00180000 0x00400000>;
+                                label = "SPI Flash Linux Kernel Image";
+                        };
+                        partition@580000 {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00580000 0x00400000>;
+                                label = "SPI Flash Compressed RFSImage";
+                        };
+                        partition@980000 {
+                                /* 6.5MB for JFFS2 based RFS */
+                                reg = <0x00980000 0x00680000>;
+                                label = "SPI Flash JFFS2 RFS";
+                        };
+                };
+        };
+        usb@22000 {
+                phy_type = "utmi";
+                dr_mode = "host";
+        };
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x2>;
+                };
+                tbi-phy@3 {
+                        device-type = "tbi-phy";
+                        reg = <0x3>;
+                };
+        };
+        mdio@25000 {
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        mdio@26000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet0: ethernet@b0000 {
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy1>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "sgmii";
+        };
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy2>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/p1010rdb_36b.dts
new file mode 100644
index 000000000000..64776f4a4651
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_36b.dts
@@ -0,0 +1,89 @@
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/include/ "fsl/p1010si-pre.dtsi"
+/ {
+        model = "fsl,P1010RDB";
+        compatible = "fsl,P1010RDB";
+        memory {
+                device_type = "memory";
+        };
+        board_ifc: ifc: ifc@fffe1e000 {
+                /* NOR, NAND Flashes and CPLD on board */
+                ranges = <0x0 0x0 0xf 0xee000000 0x02000000
+                          0x1 0x0 0xf 0xff800000 0x00010000
+                          0x3 0x0 0xf 0xffb00000 0x00000020>;
+                reg = <0xf 0xffe1e000 0 0x2000>;
+        };
+        board_soc: soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+/include/ "p1010rdb.dtsi"
+/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
deleted file mode 100644
index cabe0a453ae6..000000000000
--- a/arch/powerpc/boot/dts/p1010si.dtsi
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * P1010si Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P1010";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,P1010@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-        };
-        ifc@ffe1e000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,ifc", "simple-bus";
-                reg = <0x0 0xffe1e000 0 0x2000>;
-                interrupts = <16 2 19 2>;
-                interrupt-parent = <&mpic>;
-        };
-        soc@ffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,p1010-immr", "simple-bus";
-                ranges = <0x0  0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p1010-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <16 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p1010-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                spi@7000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc8536-espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,espi-num-chipselects = <1>;
-                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,mpc8572-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2>;
-                        interrupt-parent = <&mpic>;
-                        gpio-controller;
-                };
-                sata@18000 {
-                        compatible = "fsl,pq-sata-v2";
-                        reg = <0x18000 0x1000>;
-                        cell-index = <1>;
-                        interrupts = <74 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                sata@19000 {
-                        compatible = "fsl,pq-sata-v2";
-                        reg = <0x19000 0x1000>;
-                        cell-index = <2>;
-                        interrupts = <41 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                can0: can@1c000 {
-                        compatible = "fsl,p1010-flexcan";
-                        reg = <0x1c000 0x1000>;
-                        interrupts = <48 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                can1: can@1d000 {
-                        compatible = "fsl,p1010-flexcan";
-                        reg = <0x1d000 0x1000>;
-                        interrupts = <61 0x2>;
-                        interrupt-parent = <&mpic>;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p1010-l2-cache-controller",
-                                        "fsl,p1014-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2,256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                usb@22000 {
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
-                        dr_mode = "host";
-                };
-                mdio@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-mdio";
-                        reg = <0x24000 0x1000 0xb0030 0x4>;
-                };
-                mdio@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-tbi";
-                        reg = <0x25000 0x1000 0xb1030 0x4>;
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                mdio@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-tbi";
-                        reg = <0x26000 0x1000 0xb1030 0x4>;
-                        tbi1: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x8>;
-                        interrupt-parent = <&mpic>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                        fsl,sdhci-auto-cmd12;
-                };
-                enet0: ethernet@b0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb0000 0x1000>;
-                                fsl,rx-bit-map = <0xff>;
-                                fsl,tx-bit-map = <0xff>;
-                                interrupts = <29 2 30 2 34 2>;
-                        };
-                };
-                enet1: ethernet@b1000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb1000 0x1000>;
-                                fsl,rx-bit-map = <0xff>;
-                                fsl,tx-bit-map = <0xff>;
-                                interrupts = <35 2 36 2 40 2>;
-                        };
-                };
-                enet2: ethernet@b2000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb2000 0x1000>;
-                                fsl,rx-bit-map = <0xff>;
-                                fsl,tx-bit-map = <0xff>;
-                                interrupts = <31 2 32 2 33 2>;
-                        };
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p1010-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p1010-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-        };
-        pci0: pcie@ffe09000 {
-                compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-        };
-        pci1: pcie@ffe0a000 {
-                compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-        };
-};
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index d6a8ae458137..518bf99b1f50 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,267 +9,33 @@
 * option) any later version.
 */
-/include/ "p1020si.dtsi"
+/include/ "fsl/p1020si-pre.dtsi"
 / {
        model = "fsl,P1020RDB";
        compatible = "fsl,P1020RDB";
-        aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                pci0 = &pci0;
-                pci1 = &pci1;
-        };
        memory {
                device_type = "memory";
        };
-        localbus@ffe05000 {
+        board_lbc: lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
                          0x1 0x0 0x0 0xffa00000 0x00040000
                          0x2 0x0 0x0 0xffb00000 0x00020000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x1000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        partition@0 {
-                                /* This location must not be altered  */
-                                /* 256KB for Vitesse 7385 Switch firmware */
-                                reg = <0x0 0x00040000>;
-                                label = "NOR (RO) Vitesse-7385 Firmware";
-                                read-only;
-                        };
-                        partition@40000 {
-                                /* 256KB for DTB Image */
-                                reg = <0x00040000 0x00040000>;
-                                label = "NOR (RO) DTB Image";
-                                read-only;
-                        };
-                        partition@80000 {
-                                /* 3.5 MB for Linux Kernel Image */
-                                reg = <0x00080000 0x00380000>;
-                                label = "NOR (RO) Linux Kernel Image";
-                                read-only;
-                        };
-                        partition@400000 {
-                                /* 11MB for JFFS2 based Root file System */
-                                reg = <0x00400000 0x00b00000>;
-                                label = "NOR (RW) JFFS2 Root File System";
-                        };
-                        partition@f00000 {
-                                /* This location must not be altered  */
-                                /* 512KB for u-boot Bootloader Image */
-                                /* 512KB for u-boot Environment Variables */
-                                reg = <0x00f00000 0x00100000>;
-                                label = "NOR (RO) U-Boot Image";
-                                read-only;
-                        };
-                };
-                nand@1,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p1020-fcm-nand",
-                                     "fsl,elbc-fcm-nand";
-                        reg = <0x1 0x0 0x40000>;
-                        partition@0 {
-                                /* This location must not be altered  */
-                                /* 1MB for u-boot Bootloader Image */
-                                reg = <0x0 0x00100000>;
-                                label = "NAND (RO) U-Boot Image";
-                                read-only;
-                        };
-                        partition@100000 {
-                                /* 1MB for DTB Image */
-                                reg = <0x00100000 0x00100000>;
-                                label = "NAND (RO) DTB Image";
-                                read-only;
-                        };
-                        partition@200000 {
-                                /* 4MB for Linux Kernel Image */
-                                reg = <0x00200000 0x00400000>;
-                                label = "NAND (RO) Linux Kernel Image";
-                                read-only;
-                        };
-                        partition@600000 {
-                                /* 4MB for Compressed Root file System Image */
-                                reg = <0x00600000 0x00400000>;
-                                label = "NAND (RO) Compressed RFS Image";
-                                read-only;
-                        };
-                        partition@a00000 {
-                                /* 7MB for JFFS2 based Root file System */
-                                reg = <0x00a00000 0x00700000>;
-                                label = "NAND (RW) JFFS2 Root File System";
-                        };
-                        partition@1100000 {
-                                /* 15MB for JFFS2 based Root file System */
-                                reg = <0x01100000 0x00f00000>;
-                                label = "NAND (RW) Writable User area";
-                        };
-                };
-                L2switch@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "vitesse-7385";
-                        reg = <0x2 0x0 0x20000>;
-                };
        };
-        soc@ffe00000 {
+        board_soc: soc: soc@ffe00000 {
-                i2c@3000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
-                        rtc@68 {
-                                compatible = "dallas,ds1339";
-                                reg = <0x68>;
-                        };
-                };
-                spi@7000 {
-                        fsl_m25p80@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
-                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
-                                modal = "s25sl128b";
-                                spi-max-frequency = <50000000>;
-                                mode = <0>;
-                                partition@0 {
-                                        /* 512KB for u-boot Bootloader Image */
-                                        reg = <0x0 0x00080000>;
-                                        label = "SPI (RO) U-Boot Image";
-                                        read-only;
-                                };
-                                partition@80000 {
-                                        /* 512KB for DTB Image */
-                                        reg = <0x00080000 0x00080000>;
-                                        label = "SPI (RO) DTB Image";
-                                        read-only;
-                                };
-                                partition@100000 {
-                                        /* 4MB for Linux Kernel Image */
-                                        reg = <0x00100000 0x00400000>;
-                                        label = "SPI (RO) Linux Kernel Image";
-                                        read-only;
-                                };
-                                partition@500000 {
-                                        /* 4MB for Compressed RFS Image */
-                                        reg = <0x00500000 0x00400000>;
-                                        label = "SPI (RO) Compressed RFS Image";
-                                        read-only;
-                                };
-                                partition@900000 {
-                                        /* 7MB for JFFS2 based RFS */
-                                        reg = <0x00900000 0x00700000>;
-                                        label = "SPI (RW) JFFS2 RFS";
-                                };
-                        };
-                };
-                mdio@24000 {
-                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x0>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
-                                reg = <0x1>;
-                        };
-                };
-                mdio@25000 {
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                enet0: ethernet@b0000 {
-                        fixed-link = <1 1 1000 0 0>;
-                        phy-connection-type = "rgmii-id";
-                };
-                enet1: ethernet@b1000 {
-                        phy-handle = <&phy0>;
-                        tbi-handle = <&tbi0>;
-                        phy-connection-type = "sgmii";
-                };
-                enet2: ethernet@b2000 {
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
-                usb@22000 {
-                        phy_type = "ulpi";
-                };
-                /* USB2 is shared with localbus, so it must be disabled
-                   by default. We can't put 'status = "disabled";' here
-                   since U-Boot doesn't clear the status property when
-                   it enables USB2. OTOH, U-Boot does create a new node
-                   when there isn't any. So, just comment it out.
-                usb@23000 {
-                        phy_type = "ulpi";
-                };
-                */
        };
        pci0: pcie@ffe09000 {
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                reg = <0 0xffe09000 0 0x1000>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -281,21 +47,10 @@
        };
        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -306,3 +61,6 @@
                };
        };
 };
+/include/ "p1020rdb.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb.dtsi b/arch/powerpc/boot/dts/p1020rdb.dtsi
new file mode 100644
index 000000000000..b5bd86f4baf2
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dtsi
@@ -0,0 +1,247 @@
+/*
+ * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR (RO) Vitesse-7385 Firmware";
+                        read-only;
+                };
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR (RO) DTB Image";
+                        read-only;
+                };
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR (RO) Linux Kernel Image";
+                        read-only;
+                };
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR (RW) JFFS2 Root File System";
+                };
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR (RO) U-Boot Image";
+                        read-only;
+                };
+        };
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1020-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND (RO) U-Boot Image";
+                        read-only;
+                };
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND (RO) DTB Image";
+                        read-only;
+                };
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND (RO) Linux Kernel Image";
+                        read-only;
+                };
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND (RO) Compressed RFS Image";
+                        read-only;
+                };
+                partition@a00000 {
+                        /* 7MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00700000>;
+                        label = "NAND (RW) JFFS2 Root File System";
+                };
+                partition@1100000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x01100000 0x00f00000>;
+                        label = "NAND (RW) Writable User area";
+                };
+        };
+        L2switch@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "vitesse-7385";
+                reg = <0x2 0x0 0x20000>;
+        };
+};
+&board_soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
+        };
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>; /* input clock */
+                        partition@u-boot {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "u-boot";
+                                read-only;
+                        };
+                        partition@dtb {
+                                /* 512KB for DTB Image */
+                                reg = <0x00080000 0x00080000>;
+                                label = "dtb";
+                                read-only;
+                        };
+                        partition@kernel {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "kernel";
+                                read-only;
+                        };
+                        partition@fs {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "file system";
+                                read-only;
+                        };
+                        partition@jffs-fs {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "file system jffs2";
+                        };
+                };
+        };
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+        /* USB2 is shared with localbus, so it must be disabled
+           by default. We can't put 'status = "disabled";' here
+           since U-Boot doesn't clear the status property when
+           it enables USB2. OTOH, U-Boot does create a new node
+           when there isn't any. So, just comment it out.
+        usb@23000 {
+                phy_type = "ulpi";
+        };
+        */
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <3 1>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 1>;
+                        reg = <0x1>;
+                };
+                tbi-phy@2 {
+                        device_type = "tbi-phy";
+                        reg = <0x2>;
+                };
+        };
+        mdio@25000 {
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet0: ethernet@b0000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+        };
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "sgmii";
+        };
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts b/arch/powerpc/boot/dts/p1020rdb_36b.dts
new file mode 100644
index 000000000000..bdbdb6097e57
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_36b.dts
@@ -0,0 +1,66 @@
+/*
+ * P1020 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020RDB";
+        compatible = "fsl,P1020RDB";
+        memory {
+                device_type = "memory";
+        };
+        board_lbc: lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xffa00000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00020000>;
+        };
+        board_soc: soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+/include/ "p1020rdb.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
index f0bf7f42f097..41b4585c5da8 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -16,7 +16,7 @@
 * option) any later version.
 */
-/include/ "p1020si.dtsi"
+/include/ "p1020rdb.dts"
 / {
        model = "fsl,P1020RDB";
@@ -32,7 +32,7 @@
        cpus {
                PowerPC,P1020@1 {
-                status = "disabled";
+                        status = "disabled";
                };
        };
@@ -45,169 +45,19 @@
        };
        soc@ffe00000 {
-                i2c@3000 {
-                        rtc@68 {
-                                compatible = "dallas,ds1339";
-                                reg = <0x68>;
-                        };
-                };
                serial1: serial@4600 {
                        status = "disabled";
                };
-                spi@7000 {
-                        fsl_m25p80@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
-                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
-                                spi-max-frequency = <40000000>;
-                                partition@0 {
-                                        /* 512KB for u-boot Bootloader Image */
-                                        reg = <0x0 0x00080000>;
-                                        label = "SPI (RO) U-Boot Image";
-                                        read-only;
-                                };
-                                partition@80000 {
-                                        /* 512KB for DTB Image */
-                                        reg = <0x00080000 0x00080000>;
-                                        label = "SPI (RO) DTB Image";
-                                        read-only;
-                                };
-                                partition@100000 {
-                                        /* 4MB for Linux Kernel Image */
-                                        reg = <0x00100000 0x00400000>;
-                                        label = "SPI (RO) Linux Kernel Image";
-                                        read-only;
-                                };
-                                partition@500000 {
-                                        /* 4MB for Compressed RFS Image */
-                                        reg = <0x00500000 0x00400000>;
-                                        label = "SPI (RO) Compressed RFS Image";
-                                        read-only;
-                                };
-                                partition@900000 {
-                                        /* 7MB for JFFS2 based RFS */
-                                        reg = <0x00900000 0x00700000>;
-                                        label = "SPI (RW) JFFS2 RFS";
-                                };
-                        };
-                };
-                mdio@24000 {
-                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x0>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <2 1>;
-                                reg = <0x1>;
-                        };
-                };
-                mdio@25000 {
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
                enet0: ethernet@b0000 {
                        status = "disabled";
                };
-                enet1: ethernet@b1000 {
-                        phy-handle = <&phy0>;
-                        tbi-handle = <&tbi0>;
-                        phy-connection-type = "sgmii";
-                };
-                enet2: ethernet@b2000 {
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
-                usb@22000 {
-                        phy_type = "ulpi";
-                };
-                /* USB2 is shared with localbus, so it must be disabled
-                   by default. We can't put 'status = "disabled";' here
-                   since U-Boot doesn't clear the status property when
-                   it enables USB2. OTOH, U-Boot does create a new node
-                   when there isn't any. So, just comment it out.
-                usb@23000 {
-                        phy_type = "ulpi";
-                };
-                */
                mpic: pic@40000 {
                        protected-sources = <
                        42 29 30 34     /* serial1, enet0-queue-group0 */
                        17 18 24 45     /* enet0-queue-group1, crypto */
                        >;
                };
-        };
-        pci0: pcie@ffe09000 {
-                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-        pci1: pcie@ffe0a000 {
-                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
        };
 };
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
index 6ec02204a44e..517453821884 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
@@ -15,7 +15,7 @@
 * option) any later version.
 */
-/include/ "p1020si.dtsi"
+/include/ "p1020rdb.dts"
 / {
        model = "fsl,P1020RDB";
@@ -28,7 +28,7 @@
        cpus {
                PowerPC,P1020@0 {
-                status = "disabled";
+                        status = "disabled";
                };
        };
@@ -85,12 +85,6 @@
                        status = "disabled";
                };
-                enet0: ethernet@b0000 {
-                        fixed-link = <1 1 1000 0 0>;
-                        phy-connection-type = "rgmii-id";
-                };
                enet1: ethernet@b1000 {
                        status = "disabled";
                };
@@ -135,7 +129,6 @@
                global-utilities@e0000 {        //global utilities block
                        status = "disabled";
                };
        };
        pci0: pcie@ffe09000 {
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
deleted file mode 100644
index 5c5acb66c3fc..000000000000
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * P1020si Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P1020";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,P1020@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,P1020@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        next-level-cache = <&L2>;
-                };
-        };
-        localbus@ffe05000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
-                reg = <0 0xffe05000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
-        };
-        soc@ffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,p1020-immr", "simple-bus";
-                ranges = <0x0  0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p1020-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <16 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p1020-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                spi@7000 {
-                        cell-index = <0>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        mode = "cpu";
-                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,mpc8572-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2>;
-                        interrupt-parent = <&mpic>;
-                        gpio-controller;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p1020-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2,256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                mdio@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-mdio";
-                        reg = <0x24000 0x1000 0xb0030 0x4>;
-                };
-                mdio@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-tbi";
-                        reg = <0x25000 0x1000 0xb1030 0x4>;
-                };
-                enet0: ethernet@b0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb0000 0x1000>;
-                                interrupts = <29 2 30 2 34 2>;
-                        };
-                        queue-group@1 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb4000 0x1000>;
-                                interrupts = <17 2 18 2 24 2>;
-                        };
-                };
-                enet1: ethernet@b1000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb1000 0x1000>;
-                                interrupts = <35 2 36 2 40 2>;
-                        };
-                        queue-group@1 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb5000 0x1000>;
-                                interrupts = <51 2 52 2 67 2>;
-                        };
-                };
-                enet2: ethernet@b2000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
-                        queue-group@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb2000 0x1000>;
-                                interrupts = <31 2 32 2 33 2>;
-                        };
-                        queue-group@1 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xb6000 0x1000>;
-                                interrupts = <25 2 26 2 27 2>;
-                        };
-                };
-                usb@22000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
-                };
-                /* USB2 is shared with localbus, so it must be disabled
-                   by default. We can't put 'status = "disabled";' here
-                   since U-Boot doesn't clear the status property when
-                   it enables USB2. OTOH, U-Boot does create a new node
-                   when there isn't any. So, just comment it out.
-                usb@23000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x23000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <46 0x2>;
-                        phy_type = "ulpi";
-                };
-                */
-                sdhci@2e000 {
-                        compatible = "fsl,p1020-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2>;
-                        interrupt-parent = <&mpic>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
-                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xbfe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p1020-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p1020-guts","fsl,p2020-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-        };
-        pci0: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-        };
-        pci1: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-        };
-};
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index ad5b85269004..d9540791e434 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -9,53 +9,22 @@
 * option) any later version.
 */
-/dts-v1/;
+/include/ "fsl/p1021si-pre.dtsi"
 / {
        model = "fsl,P1021";
        compatible = "fsl,P1021MDS";
-        #address-cells = <2>;
-        #size-cells = <2>;
        aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
                ethernet3 = &enet3;
                ethernet4 = &enet4;
-                pci0 = &pci0;
-                pci1 = &pci1;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,P1021@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,P1021@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        next-level-cache = <&L2>;
-                };
        };
        memory {
                device_type = "memory";
        };
-        localbus@ffe05000 {
+        lbc: localbus@ffe05000 {
-                #address-cells = <2>;
+                reg = <0x0 0xffe05000 0x0 0x1000>;
-                #size-cells = <1>;
-                compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
-                reg = <0 0xffe05000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
                /* NAND Flash, BCSR, PMC0/1*/
                ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
@@ -138,99 +107,26 @@
                };
        };
-        soc@ffe00000 {
+        soc: soc@ffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
                compatible = "fsl,p1021-immr", "simple-bus";
-                ranges = <0x0  0x0 0xffe00000 0x100000>;
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p1021-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <16 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p1021-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                        rtc@68 {
                                compatible = "dallas,ds1374";
                                reg = <0x68>;
                        };
                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
                spi@7000 {
-                        cell-index = <0>;
-                        #address-cells = <1>;
+                        flash@0 {
-                        #size-cells = <0>;
-                        compatible = "fsl,espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        espi,num-ss-bits = <4>;
-                        mode = "cpu";
-                        fsl_m25p80@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
+                                compatible = "spansion,s25sl12801";
                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
                                spi-max-frequency = <40000000>; /* input clock */
                                partition@u-boot {
                                        label = "u-boot-spi";
                                        reg = <0x00000000 0x00100000>;
@@ -253,237 +149,49 @@
                        };
                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,mpc8572-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2>;
-                        interrupt-parent = <&mpic>;
-                        gpio-controller;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p1021-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2,256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
                usb@22000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
                        phy_type = "ulpi";
                };
-                 mdio@24000 {
+                mdio@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-mdio";
-                        reg = <0x24000 0x1000 0xb0030 0x4>;
                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
+                                interrupts = <1 1 0 0>;
-                                interrupts = <1 1>;
                                reg = <0x0>;
                        };
                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
+                                interrupts = <2 1 0 0>;
-                                interrupts = <2 1>;
                                reg = <0x1>;
                        };
                        phy4: ethernet-phy@4 {
-                                interrupt-parent = <&mpic>;
                                reg = <0x4>;
                        };
+                        tbi-phy@5 {
+                                device_type = "tbi-phy";
+                                reg = <0x5>;
+                        };
                };
                mdio@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-tbi";
-                        reg = <0x25000 0x1000 0xb1030 0x4>;
                        tbi0: tbi-phy@11 {
                                reg = <0x11>;
                                device_type = "tbi-phy";
                        };
                };
-                enet0: ethernet@B0000 {
+                ethernet@b0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                        phy-connection-type = "rgmii-id";
-                        queue-group@0{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB0000 0x1000>;
-                                interrupts = <29 2 30 2 34 2>;
-                        };
-                        queue-group@1{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB4000 0x1000>;
-                                interrupts = <17 2 18 2 24 2>;
-                        };
                };
-                enet1: ethernet@B1000 {
+                ethernet@b1000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy4>;
                        tbi-handle = <&tbi0>;
                        phy-connection-type = "sgmii";
-                        queue-group@0{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB1000 0x1000>;
-                                interrupts = <35 2 36 2 40 2>;
-                        };
-                        queue-group@1{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB5000 0x1000>;
-                                interrupts = <51 2 52 2 67 2>;
-                        };
                };
-                enet2: ethernet@B2000 {
+                ethernet@b2000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                        phy-connection-type = "rgmii-id";
-                        queue-group@0{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB2000 0x1000>;
-                                interrupts = <31 2 32 2 33 2>;
-                        };
-                        queue-group@1{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB6000 0x1000>;
-                                interrupts = <25 2 26 2 27 2>;
-                        };
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,p1021-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2>;
-                        interrupt-parent = <&mpic>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.3", "fsl,sec3.1",
-                                     "fsl,sec3.0", "fsl,sec2.4",
-                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x97c>;
-                        fsl,descriptor-types-mask = <0x3a30abf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p1021-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p1021-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
                };
                par_io@e0100 {
@@ -499,8 +207,7 @@
                                        0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
                                        0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
                                        0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
-                                        0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9
+                                        0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
-*/
                                        0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
                                        0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
                                        0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
@@ -535,31 +242,10 @@
        };
        pci0: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -571,31 +257,10 @@
        };
        pci1: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xc0000000
                                  0x2000000 0x0 0xc0000000
                                  0x0 0x20000000
@@ -606,36 +271,16 @@
                };
        };
-        qe@ffe80000 {
+        qe: qe@ffe80000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "qe";
-                compatible = "fsl,qe";
                ranges = <0x0 0x0 0xffe80000 0x40000>;
                reg = <0 0xffe80000 0 0x480>;
                brg-frequency = <0>;
                bus-frequency = <0>;
-                fsl,qe-num-riscs = <1>;
-                fsl,qe-num-snums = <28>;
                status = "disabled"; /* no firmware loaded */
-                qeic: interrupt-controller@80 {
-                        interrupt-controller;
-                        compatible = "fsl,qe-ic";
-                        #address-cells = <0>;
-                        #interrupt-cells = <1>;
-                        reg = <0x80 0x80>;
-                        interrupts = <63 2 60 2>; //high:47 low:44
-                        interrupt-parent = <&mpic>;
-                };
                enet3: ucc@2000 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <1>;
-                        reg = <0x2000 0x200>;
-                        interrupts = <32>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "clk12";
                        tx-clock-name = "clk9";
@@ -645,20 +290,15 @@
                };
                mdio@2120 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x2120 0x18>;
-                        compatible = "fsl,ucc-mdio";
                        qe_phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <4 1>;
+                                interrupts = <4 1 0 0>;
                                reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy1: ethernet-phy@03 {
                                interrupt-parent = <&mpic>;
-                                interrupts = <5 1>;
+                                interrupts = <5 1 0 0>;
                                reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
@@ -671,10 +311,6 @@
                enet4: ucc@2400 {
                        device_type = "network";
                        compatible = "ucc_geth";
-                        cell-index = <5>;
-                        reg = <0x2400 0x200>;
-                        interrupts = <40>;
-                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        tx-clock-name = "clk13";
@@ -682,18 +318,7 @@
                        phy-handle = <&qe_phy1>;
                        phy-connection-type = "rmii";
                };
-                muram@10000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,qe-muram", "fsl,cpm-muram";
-                        ranges = <0x0 0x10000 0x6000>;
-                        data-only@0 {
-                                compatible = "fsl,qe-muram-data",
-                                "fsl,cpm-muram-data";
-                                reg = <0x0 0x6000>;
-                        };
-                };
        };
 };
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index b9b8719a6204..ef95717db4bc 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -8,57 +8,36 @@
 * kind, whether express or implied.
 */
-/dts-v1/;
+/include/ "fsl/p1022si-pre.dtsi"
 / {
-        model = "fsl,P1022";
+        model = "fsl,P1022DS";
        compatible = "fsl,P1022DS";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,P1022@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,P1022@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
        };
-        localbus@fffe05000 {
+        lbc: localbus@fffe05000 {
-                #address-cells = <2>;
+                reg = <0xf 0xffe05000 0 0x1000>;
-                #size-cells = <1>;
-                compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
-                reg = <0 0xffe05000 0 0x1000>;
-                interrupts = <19 2 0 0>;
                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
                          0x1 0x0 0xf 0xe0000000 0x08000000
-                          0x2 0x0 0x0 0xffa00000 0x00040000
+                          0x2 0x0 0xf 0xff800000 0x00040000
                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
+                /*
+                 * This node is used to access the pixis via "indirect" mode,
+                 * which is done by writing the pixis register index to chip
+                 * select 0 and the value to/from chip select 1.  Indirect
+                 * mode is the only way to access the pixis when DIU video
+                 * is enabled.  Note that this assumes that the first column
+                 * of the 'ranges' property above is the chip select number.
+                 */
+                board-control@0,0 {
+                        compatible = "fsl,p1022ds-indirect-pixis";
+                        reg = <0x0 0x0 1        /* CS0 */
+                               0x1 0x0 1>;      /* CS1 */
+                };
                nor@0,0 {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -161,51 +140,10 @@
                };
        };
-        soc@fffe00000 {
+        soc: soc@fffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,p1022-immr", "simple-bus";
                ranges = <0x0 0xf 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p1022-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <16 2 0 0>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p1022-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupts = <16 2 0 0>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2 0 0>;
-                        dfsrr;
-                };
                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2 0 0>;
-                        dfsrr;
                        wm8776:codec@1a {
                                compatible = "wlf,wm8776";
                                reg = <0x1a>;
@@ -216,41 +154,14 @@
                        };
                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2 0 0>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2 0 0>;
-                };
                spi@7000 {
-                        cell-index = <0>;
+                        flash@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2 0 0>;
-                        espi,num-ss-bits = <4>;
-                        mode = "cpu";
-                        fsl_m25p80@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
+                                compatible = "spansion,s25sl12801";
                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
                                spi-max-frequency = <40000000>; /* input clock */
                                partition@0 {
                                        label = "u-boot-spi";
                                        reg = <0x00000000 0x00100000>;
@@ -274,115 +185,20 @@
                };
                ssi@15000 {
-                        compatible = "fsl,mpc8610-ssi";
-                        cell-index = <0>;
-                        reg = <0x15000 0x100>;
-                        interrupts = <75 2 0 0>;
                        fsl,mode = "i2s-slave";
                        codec-handle = <&wm8776>;
-                        fsl,playback-dma = <&dma00>;
-                        fsl,capture-dma = <&dma01>;
-                        fsl,fifo-depth = <15>;
                        fsl,ssi-asynchronous;
                };
-                dma@c300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0xc300 0x4>;
-                        ranges = <0x0 0xc100 0x200>;
-                        cell-index = <1>;
-                        dma00: dma-channel@0 {
-                                compatible = "fsl,ssi-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <76 2 0 0>;
-                        };
-                        dma01: dma-channel@80 {
-                                compatible = "fsl,ssi-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <77 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <78 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <79 2 0 0>;
-                        };
-                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,mpc8572-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2 0 0>;
-                        gpio-controller;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p1022-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2, 256K
-                        interrupts = <16 2 0 0>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <20 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <21 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <22 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <23 2 0 0>;
-                        };
-                };
                usb@22000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        interrupts = <28 0x2 0 0>;
                        phy_type = "ulpi";
                };
-                mdio@24000 {
+                usb@23000 {
-                        #address-cells = <1>;
+                        status = "disabled";
-                        #size-cells = <0>;
+                };
-                        compatible = "fsl,etsec2-mdio";
-                        reg = <0x24000 0x1000 0xb0030 0x4>;
+                mdio@24000 {
                        phy0: ethernet-phy@0 {
                                interrupts = <3 1 0 0>;
                                reg = <0x1>;
@@ -391,189 +207,28 @@
                                interrupts = <9 1 0 0>;
                                reg = <0x2>;
                        };
+                        tbi-phy@2 {
+                                device_type = "tbi-phy";
+                                reg = <0x2>;
+                        };
                };
-                mdio@25000 {
+                ethernet@b0000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,etsec2-mdio";
-                        reg = <0x25000 0x1000 0xb1030 0x4>;
-                };
-                enet0: ethernet@B0000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        fsl,magic-packet;
-                        fsl,wake-on-filer;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
                        phy-handle = <&phy0>;
                        phy-connection-type = "rgmii-id";
-                        queue-group@0{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB0000 0x1000>;
-                                interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
-                        };
-                        queue-group@1{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB4000 0x1000>;
-                                interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
-                        };
                };
-                enet1: ethernet@B1000 {
+                ethernet@b1000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "fsl,etsec2";
-                        fsl,num_rx_queues = <0x8>;
-                        fsl,num_tx_queues = <0x8>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
                        phy-handle = <&phy1>;
                        phy-connection-type = "rgmii-id";
-                        queue-group@0{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB1000 0x1000>;
-                                interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
-                        };
-                        queue-group@1{
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xB5000 0x1000>;
-                                interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
-                        };
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,p1022-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2 0 0>;
-                        fsl,sdhci-auto-cmd12;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
-                                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
-                                     "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 0 0 58 2 0 0>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0x97c>;
-                        fsl,descriptor-types-mask = <0x3a30abf>;
-                };
-                sata@18000 {
-                        compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
-                        reg = <0x18000 0x1000>;
-                        cell-index = <1>;
-                        interrupts = <74 0x2 0 0>;
-                };
-                sata@19000 {
-                        compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
-                        reg = <0x19000 0x1000>;
-                        cell-index = <2>;
-                        interrupts = <41 0x2 0 0>;
-                };
-                power@e0070{
-                        compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
-                        reg = <0xe0070 0x20>;
-                };
-                display@10000 {
-                        compatible = "fsl,diu", "fsl,p1022-diu";
-                        reg = <0x10000 1000>;
-                        interrupts = <64 2 0 0>;
-                };
-                timer@41100 {
-                        compatible = "fsl,mpic-global-timer";
-                        reg = <0x41100 0x100 0x41300 4>;
-                        interrupts = <0 0 3 0
-                                      1 0 3 0
-                                      2 0 3 0
-                                      3 0 3 0>;
-                };
-                timer@42100 {
-                        compatible = "fsl,mpic-global-timer";
-                        reg = <0x42100 0x100 0x42300 4>;
-                        interrupts = <4 0 3 0
-                                      5 0 3 0
-                                      6 0 3 0
-                                      7 0 3 0>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p1022-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p1022-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
                };
        };
        pci0: pcie@fffe09000 {
-                compatible = "fsl,p1022-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
-                ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupts = <16 2 0 0>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -585,30 +240,11 @@
        };
        pci1: pcie@fffe0a000 {
-                compatible = "fsl,p1022-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupts = <16 2 0 0>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
-                        >;
                pcie@0 {
                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -619,32 +255,11 @@
                };
        };
        pci2: pcie@fffe0b000 {
-                compatible = "fsl,p1022-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0xf 0xffe0b000 0 0x1000>;
-                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
-                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupts = <16 2 0 0>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 8 1
-                        0000 0 0 2 &mpic 9 1
-                        0000 0 0 3 &mpic 10 1
-                        0000 0 0 4 &mpic 11 1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xe0000000
                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
@@ -655,3 +270,5 @@
                };
        };
 };
+/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d3b478242ea9..beb6cb12e59d 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -34,137 +34,30 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/dts-v1/;
+/include/ "fsl/p1023si-pre.dtsi"
 / {
        model = "fsl,P1023";
        compatible = "fsl,P1023RDS";
        #address-cells = <2>;
        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
-        aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,P1023@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-                cpu1: PowerPC,P1023@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        next-level-cache = <&L2>;
-                };
-        };
        memory {
                device_type = "memory";
        };
-        soc@ff600000 {
+        soc: soc@ff600000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,p1023-immr", "simple-bus";
                ranges = <0x0 0x0 0xff600000 0x200000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p1023-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <16 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p1023-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
                        rtc@68 {
                                compatible = "dallas,ds1374";
                                reg = <0x68>;
                        };
                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
                spi@7000 {
-                        cell-index = <0>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,espi-num-chipselects = <4>;
                        fsl_dataflash@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
@@ -186,197 +79,14 @@
                        };
                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,qoriq-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2>;
-                        interrupt-parent = <&mpic>;
-                        gpio-controller;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p1023-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x40000>; // L2,256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
                usb@22000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
                        dr_mode = "host";
                        phy_type = "ulpi";
                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x30000 0x10000>;
-                        ranges = <0 0x30000 0x10000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <58 2>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <45 2>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <45 2>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <57 2>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupts = <57 2>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.2-rtic",
-                                             "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                power@e0070{
-                        compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
-                                     "fsl,p1022-pmc";
-                        reg = <0xe0070 0x20>;
-                        etsec1_clk: soc-clk@B0{
-                                fsl,pmcdr-mask = <0x00000080>;
-                        };
-                        etsec2_clk: soc-clk@B1{
-                                fsl,pmcdr-mask = <0x00000040>;
-                        };
-                        etsec3_clk: soc-clk@B2{
-                                fsl,pmcdr-mask = <0x00000020>;
-                        };
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p1023-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p1023-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
        };
-        localbus@ff605000 {
+        lbc: localbus@ff605000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
                reg = <0 0xff605000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
                /* NOR Flash, BCSR */
                ranges = <0x0 0x0 0x0 0xee000000 0x02000000
@@ -428,34 +138,18 @@
        };
        pci0: pcie@ff60a000 {
-                compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
-                cell-index = <1>;
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xff60a000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
                        /* IRQ[0:3] are pulled up on board, set to active-low */
+                        interrupt-map-mask = <0xf800 0 0 7>;
                        interrupt-map = <
                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 0 1
+                                0000 0 0 1 &mpic 0 1 0 0
-                                0000 0 0 2 &mpic 1 1
+                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1
+                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1
+                                0000 0 0 4 &mpic 3 1 0 0
                                >;
                        ranges = <0x2000000 0x0 0xc0000000
                                  0x2000000 0x0 0xc0000000
@@ -467,38 +161,22 @@
                };
        };
-        pci1: pcie@ff609000 {
+        board_pci1: pci1: pcie@ff609000 {
-                compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
-                cell-index = <2>;
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xff609000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
                        /*
                         * IRQ[4:6] only for PCIe, set to active-high,
                         * IRQ[7] is pulled up on board, set to active-low
                         */
+                        interrupt-map-mask = <0xf800 0 0 7>;
                        interrupt-map = <
                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 4 2
+                                0000 0 0 1 &mpic 4 2 0 0
-                                0000 0 0 2 &mpic 5 2
+                                0000 0 0 2 &mpic 5 2 0 0
-                                0000 0 0 3 &mpic 6 2
+                                0000 0 0 3 &mpic 6 2 0 0
-                                0000 0 0 4 &mpic 7 1
+                                0000 0 0 4 &mpic 7 1 0 0
                                >;
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
@@ -511,37 +189,21 @@
        };
        pci2: pcie@ff60b000 {
-                cell-index = <3>;
-                compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
                reg = <0 0xff60b000 0 0x1000>;
-                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <16 2>;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
                        /*
                         * IRQ[8:10] are pulled up on board, set to active-low
                         * IRQ[11] only for PCIe, set to active-high,
                         */
+                        interrupt-map-mask = <0xf800 0 0 7>;
                        interrupt-map = <
                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 8 1
+                                0000 0 0 1 &mpic 8 1 0 0
-                                0000 0 0 2 &mpic 9 1
+                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1
+                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 2
+                                0000 0 0 4 &mpic 11 2 0 0
                                >;
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
@@ -553,3 +215,5 @@
                };
        };
 };
+/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 66f03d6477b2..237310cc7e6c 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -9,30 +9,17 @@
 * option) any later version.
 */
-/include/ "p2020si.dtsi"
+/include/ "fsl/p2020si-pre.dtsi"
 / {
        model = "fsl,P2020DS";
        compatible = "fsl,P2020DS";
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-        };
        memory {
                device_type = "memory";
        };
-        localbus@ffe05000 {
+        board_lbc: lbc: localbus@ffe05000 {
-                compatible = "fsl,elbc", "simple-bus";
                ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
                          0x1 0x0 0x0 0xe0000000 0x08000000
                          0x2 0x0 0x0 0xffa00000 0x00040000
@@ -40,203 +27,18 @@
                          0x4 0x0 0x0 0xffa40000 0x00040000
                          0x5 0x0 0x0 0xffa80000 0x00040000
                          0x6 0x0 0x0 0xffac0000 0x00040000>;
+                reg = <0 0xffe05000 0 0x1000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x8000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        ramdisk@0 {
-                                reg = <0x0 0x03000000>;
-                                read-only;
-                        };
-                        diagnostic@3000000 {
-                                reg = <0x03000000 0x00e00000>;
-                                read-only;
-                        };
-                        dink@3e00000 {
-                                reg = <0x03e00000 0x00200000>;
-                                read-only;
-                        };
-                        kernel@4000000 {
-                                reg = <0x04000000 0x00400000>;
-                                read-only;
-                        };
-                        jffs2@4400000 {
-                                reg = <0x04400000 0x03b00000>;
-                        };
-                        dtb@7f00000 {
-                                reg = <0x07f00000 0x00080000>;
-                                read-only;
-                        };
-                        u-boot@7f80000 {
-                                reg = <0x07f80000 0x00080000>;
-                                read-only;
-                        };
-                };
-                nand@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x2 0x0 0x40000>;
-                        u-boot@0 {
-                                reg = <0x0 0x02000000>;
-                                read-only;
-                        };
-                        jffs2@2000000 {
-                                reg = <0x02000000 0x10000000>;
-                        };
-                        ramdisk@12000000 {
-                                reg = <0x12000000 0x08000000>;
-                                read-only;
-                        };
-                        kernel@1a000000 {
-                                reg = <0x1a000000 0x04000000>;
-                        };
-                        dtb@1e000000 {
-                                reg = <0x1e000000 0x01000000>;
-                                read-only;
-                        };
-                        empty@1f000000 {
-                                reg = <0x1f000000 0x21000000>;
-                        };
-                };
-                board-control@3,0 {
-                        compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
-                        reg = <0x3 0x0 0x30>;
-                };
-                nand@4,0 {
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x4 0x0 0x40000>;
-                };
-                nand@5,0 {
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x5 0x0 0x40000>;
-                };
-                nand@6,0 {
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x6 0x0 0x40000>;
-                };
        };
-        soc@ffe00000 {
+        board_soc: soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
-                usb@22000 {
-                        phy_type = "ulpi";
-                };
-                mdio@24520 {
-                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x0>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x1>;
-                        };
-                        phy2: ethernet-phy@2 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x2>;
-                        };
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                mdio@25520 {
-                        tbi1: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                mdio@26520 {
-                        tbi2: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                ptp_clock@24E00 {
-                        compatible = "fsl,etsec-ptp";
-                        reg = <0x24E00 0xB0>;
-                        interrupts = <68 2 69 2 70 2>;
-                        interrupt-parent = < &mpic >;
-                        fsl,tclk-period = <5>;
-                        fsl,tmr-prsc = <200>;
-                        fsl,tmr-add = <0xCCCCCCCD>;
-                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
-                        fsl,tmr-fiper2 = <0x0001869B>;
-                        fsl,max-adj = <249999999>;
-                };
-                enet0: ethernet@24000 {
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                };
-                enet1: ethernet@25000 {
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
-                enet2: ethernet@26000 {
-                        tbi-handle = <&tbi2>;
-                        phy-handle = <&phy2>;
-                        phy-connection-type = "rgmii-id";
-                };
-                msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                };
        };
-        pci0: pcie@ffe08000 {
+        pci2: pcie@ffe08000 {
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                reg = <0 0xffe08000 0 0x1000>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x8 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x9 0x1
-                        0000 0x0 0x0 0x3 &mpic 0xa 0x1
-                        0000 0x0 0x0 0x4 &mpic 0xb 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -247,61 +49,11 @@
                };
        };
-        pci1: pcie@ffe09000 {
+        board_pci1: pci1: pcie@ffe09000 {
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                reg = <0 0xffe09000 0 0x1000>;
-                interrupt-map = <
-                        // IDSEL 0x11 func 0 - PCI slot 1
-                        0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 1 - PCI slot 1
-                        0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 2 - PCI slot 1
-                        0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 3 - PCI slot 1
-                        0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 4 - PCI slot 1
-                        0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 5 - PCI slot 1
-                        0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 6 - PCI slot 1
-                        0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x11 func 7 - PCI slot 1
-                        0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
-                        0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
-                        // IDSEL 0x1d  Audio
-                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-                        // IDSEL 0x1e Legacy
-                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
-                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-                        // IDSEL 0x1f IDE/SATA
-                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
-                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -309,89 +61,14 @@
                                  0x1000000 0x0 0x0
                                  0x1000000 0x0 0x0
                                  0x0 0x10000>;
-                        uli1575@0 {
-                                reg = <0x0 0x0 0x0 0x0 0x0>;
-                                #size-cells = <2>;
-                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0xa0000000
-                                          0x2000000 0x0 0xa0000000
-                                          0x0 0x20000000
-                                          0x1000000 0x0 0x0
-                                          0x1000000 0x0 0x0
-                                          0x0 0x10000>;
-                                isa@1e {
-                                        device_type = "isa";
-                                        #interrupt-cells = <2>;
-                                        #size-cells = <1>;
-                                        #address-cells = <2>;
-                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
-                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
-                                                  0x1000>;
-                                        interrupt-parent = <&i8259>;
-                                        i8259: interrupt-controller@20 {
-                                                reg = <0x1 0x20 0x2
-                                                       0x1 0xa0 0x2
-                                                       0x1 0x4d0 0x2>;
-                                                interrupt-controller;
-                                                device_type = "interrupt-controller";
-                                                #address-cells = <0>;
-                                                #interrupt-cells = <2>;
-                                                compatible = "chrp,iic";
-                                                interrupts = <4 1>;
-                                                interrupt-parent = <&mpic>;
-                                        };
-                                        i8042@60 {
-                                                #size-cells = <0>;
-                                                #address-cells = <1>;
-                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
-                                                interrupts = <1 3 12 3>;
-                                                interrupt-parent =
-                                                        <&i8259>;
-                                                keyboard@0 {
-                                                        reg = <0x0>;
-                                                        compatible = "pnpPNP,303";
-                                                };
-                                                mouse@1 {
-                                                        reg = <0x1>;
-                                                        compatible = "pnpPNP,f03";
-                                                };
-                                        };
-                                        rtc@70 {
-                                                compatible = "pnpPNP,b00";
-                                                reg = <0x1 0x70 0x2>;
-                                        };
-                                        gpio@400 {
-                                                reg = <0x1 0x400 0x80>;
-                                        };
-                                };
-                        };
                };
        };
-        pci2: pcie@ffe0a000 {
+        pci0: pcie@ffe0a000 {
                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                reg = <0 0xffe0a000 0 0x1000>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xc0000000
                                  0x2000000 0x0 0xc0000000
                                  0x0 0x20000000
@@ -402,3 +79,11 @@
                };
        };
 };
+/*
+ * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask
+ */
+/include/ "fsl/p2020si-post.dtsi"
+/include/ "p2020ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
new file mode 100644
index 000000000000..c1cf6cef4dd6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -0,0 +1,316 @@
+/*
+ * P2020DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&board_lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+                ramdisk@0 {
+                        reg = <0x0 0x03000000>;
+                        read-only;
+                };
+                diagnostic@3000000 {
+                        reg = <0x03000000 0x00e00000>;
+                        read-only;
+                };
+                dink@3e00000 {
+                        reg = <0x03e00000 0x00200000>;
+                        read-only;
+                };
+                kernel@4000000 {
+                        reg = <0x04000000 0x00400000>;
+                        read-only;
+                };
+                jffs2@4400000 {
+                        reg = <0x04400000 0x03b00000>;
+                };
+                dtb@7f00000 {
+                        reg = <0x07f00000 0x00080000>;
+                        read-only;
+                };
+                u-boot@7f80000 {
+                        reg = <0x07f80000 0x00080000>;
+                        read-only;
+                };
+        };
+        nand@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,elbc-fcm-nand";
+                reg = <0x2 0x0 0x40000>;
+                u-boot@0 {
+                        reg = <0x0 0x02000000>;
+                        read-only;
+                };
+                jffs2@2000000 {
+                        reg = <0x02000000 0x10000000>;
+                };
+                ramdisk@12000000 {
+                        reg = <0x12000000 0x08000000>;
+                        read-only;
+                };
+                kernel@1a000000 {
+                        reg = <0x1a000000 0x04000000>;
+                };
+                dtb@1e000000 {
+                        reg = <0x1e000000 0x01000000>;
+                        read-only;
+                };
+                empty@1f000000 {
+                        reg = <0x1f000000 0x21000000>;
+                };
+        };
+        board-control@3,0 {
+                compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
+                reg = <0x3 0x0 0x30>;
+        };
+        nand@4,0 {
+                compatible = "fsl,elbc-fcm-nand";
+                reg = <0x4 0x0 0x40000>;
+        };
+        nand@5,0 {
+                compatible = "fsl,elbc-fcm-nand";
+                reg = <0x5 0x0 0x40000>;
+        };
+        nand@6,0 {
+                compatible = "fsl,elbc-fcm-nand";
+                reg = <0x6 0x0 0x40000>;
+        };
+};
+&board_soc {
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x2>;
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        mdio@25520 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        mdio@26520 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+        ptp_clock@24e00 {
+                fsl,tclk-period = <5>;
+                fsl,tmr-prsc = <200>;
+                fsl,tmr-add = <0xCCCCCCCD>;
+                fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                fsl,tmr-fiper2 = <0x0001869B>;
+                fsl,max-adj = <249999999>;
+        };
+        enet0: ethernet@24000 {
+                tbi-handle = <&tbi0>;
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+        enet1: ethernet@25000 {
+                tbi-handle = <&tbi1>;
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+        enet2: ethernet@26000 {
+                tbi-handle = <&tbi2>;
+                phy-handle = <&phy2>;
+                phy-connection-type = "rgmii-id";
+        };
+};
+&board_pci1 {
+        pcie@0 {
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                interrupt-map = <
+                        // IDSEL 0x11 func 0 - PCI slot 1
+                        0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 1 - PCI slot 1
+                        0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 2 - PCI slot 1
+                        0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 3 - PCI slot 1
+                        0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 4 - PCI slot 1
+                        0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 5 - PCI slot 1
+                        0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 6 - PCI slot 1
+                        0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 7 - PCI slot 1
+                        0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x1d  Audio
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+                        // IDSEL 0x1e Legacy
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+                        >;
+                uli1575@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                        isa@1e {
+                                device_type = "isa";
+                                #interrupt-cells = <2>;
+                                #size-cells = <1>;
+                                #address-cells = <2>;
+                                reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                          0x1000>;
+                                interrupt-parent = <&i8259>;
+                                i8259: interrupt-controller@20 {
+                                        reg = <0x1 0x20 0x2
+                                               0x1 0xa0 0x2
+                                               0x1 0x4d0 0x2>;
+                                        interrupt-controller;
+                                        device_type = "interrupt-controller";
+                                        #address-cells = <0>;
+                                        #interrupt-cells = <2>;
+                                        compatible = "chrp,iic";
+                                        interrupts = <4 1 0 0>;
+                                        interrupt-parent = <&mpic>;
+                                };
+                                i8042@60 {
+                                        #size-cells = <0>;
+                                        #address-cells = <1>;
+                                        reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                        interrupts = <1 3 12 3>;
+                                        interrupt-parent =
+                                                <&i8259>;
+                                        keyboard@0 {
+                                                reg = <0x0>;
+                                                compatible = "pnpPNP,303";
+                                        };
+                                        mouse@1 {
+                                                reg = <0x1>;
+                                                compatible = "pnpPNP,f03";
+                                        };
+                                };
+                                rtc@70 {
+                                        compatible = "pnpPNP,b00";
+                                        reg = <0x1 0x70 0x2>;
+                                };
+                                gpio@400 {
+                                        reg = <0x1 0x400 0x80>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f3021e..26759a591712 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,7 +9,7 @@
 * option) any later version.
 */
-/include/ "p2020si.dtsi"
+/include/ "fsl/p2020si-pre.dtsi"
 / {
        model = "fsl,P2020RDB";
@@ -29,7 +29,8 @@
                device_type = "memory";
        };
-        localbus@ffe05000 {
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
                /* NOR and NAND Flashes */
                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -140,7 +141,9 @@
        };
-        soc@ffe00000 {
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
                i2c@3000 {
                        rtc@68 {
                                compatible = "dallas,ds1339";
@@ -148,17 +151,13 @@
                        };
                };
-        spi@7000 {
+                spi@7000 {
+                        flash@0 {
-                fsl_m25p80@0 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
+                                compatible = "spansion,s25sl12801";
                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
-                                modal = "s25sl128b";
                                spi-max-frequency = <50000000>;
-                                mode = <0>;
                                partition@0 {
                                        /* 512KB for u-boot Bootloader Image */
@@ -202,15 +201,17 @@
                mdio@24520 {
                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
+                                interrupts = <3 1 0 0>;
-                                interrupts = <3 1>;
                                reg = <0x0>;
-                                };
+                        };
                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
+                                interrupts = <3 1 0 0>;
-                                interrupts = <3 1>;
                                reg = <0x1>;
-                                };
+                        };
+                        tbi-phy@2 {
+                                device_type = "tbi-phy";
+                                reg = <0x2>;
+                        };
                };
                mdio@25520 {
@@ -224,11 +225,7 @@
                        status = "disabled";
                };
-                ptp_clock@24E00 {
+                ptp_clock@24e00 {
-                        compatible = "fsl,etsec-ptp";
-                        reg = <0x24E00 0xB0>;
-                        interrupts = <68 2 69 2 70 2>;
-                        interrupt-parent = < &mpic >;
                        fsl,tclk-period = <5>;
                        fsl,tmr-prsc = <200>;
                        fsl,tmr-add = <0xCCCCCCCD>;
@@ -252,29 +249,18 @@
                        phy-handle = <&phy1>;
                        phy-connection-type = "rgmii-id";
                };
        };
        pci0: pcie@ffe08000 {
+                reg = <0 0xffe08000 0 0x1000>;
                status = "disabled";
        };
        pci1: pcie@ffe09000 {
+                reg = <0 0xffe09000 0 0x1000>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                pcie@0 {
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
-                        pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0xa0000000
                                  0x2000000 0x0 0xa0000000
                                  0x0 0x20000000
@@ -286,21 +272,10 @@
        };
        pci2: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
                        ranges = <0x2000000 0x0 0x80000000
                                  0x2000000 0x0 0x80000000
                                  0x0 0x20000000
@@ -311,3 +286,5 @@
                };
        };
 };
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8ddddfccb6..66aac864c4cc 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,28 +14,16 @@
 * option) any later version.
 */
-/include/ "p2020si.dtsi"
+/include/ "p2020rdb.dts"
 / {
        model = "fsl,P2020RDB";
        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
-        aliases {
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                serial0 = &serial0;
-                pci0 = &pci0;
-        };
        cpus {
                PowerPC,P2020@1 {
-                status = "disabled";
+                        status = "disabled";
                };
-        };
-        memory {
-                device_type = "memory";
        };
        localbus@ffe05000 {
@@ -43,115 +31,18 @@
        };
        soc@ffe00000 {
-                i2c@3000 {
-                        rtc@68 {
-                                compatible = "dallas,ds1339";
-                                reg = <0x68>;
-                        };
-                };
                serial1: serial@4600 {
                        status = "disabled";
                };
-                spi@7000 {
-                        fsl_m25p80@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "fsl,espi-flash";
-                                reg = <0>;
-                                linux,modalias = "fsl_m25p80";
-                                modal = "s25sl128b";
-                                spi-max-frequency = <50000000>;
-                                mode = <0>;
-                                partition@0 {
-                                        /* 512KB for u-boot Bootloader Image */
-                                        reg = <0x0 0x00080000>;
-                                        label = "SPI (RO) U-Boot Image";
-                                        read-only;
-                                };
-                                partition@80000 {
-                                        /* 512KB for DTB Image */
-                                        reg = <0x00080000 0x00080000>;
-                                        label = "SPI (RO) DTB Image";
-                                        read-only;
-                                };
-                                partition@100000 {
-                                        /* 4MB for Linux Kernel Image */
-                                        reg = <0x00100000 0x00400000>;
-                                        label = "SPI (RO) Linux Kernel Image";
-                                        read-only;
-                                };
-                                partition@500000 {
-                                        /* 4MB for Compressed RFS Image */
-                                        reg = <0x00500000 0x00400000>;
-                                        label = "SPI (RO) Compressed RFS Image";
-                                        read-only;
-                                };
-                                partition@900000 {
-                                        /* 7MB for JFFS2 based RFS */
-                                        reg = <0x00900000 0x00700000>;
-                                        label = "SPI (RW) JFFS2 RFS";
-                                };
-                        };
-                };
                dma@c300 {
                        status = "disabled";
                };
-                usb@22000 {
-                        phy_type = "ulpi";
-                };
-                mdio@24520 {
-                        phy0: ethernet-phy@0 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x0>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupt-parent = <&mpic>;
-                                interrupts = <3 1>;
-                                reg = <0x1>;
-                        };
-                };
-                mdio@25520 {
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-                mdio@26520 {
-                        status = "disabled";
-                };
                enet0: ethernet@24000 {
                        status = "disabled";
                };
-                enet1: ethernet@25000 {
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "sgmii";
-                };
-                enet2: ethernet@26000 {
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
                mpic: pic@40000 {
                        protected-sources = <
                        42 76 77 78 79 /* serial1 , dma2 */
@@ -164,40 +55,12 @@
                msi@41600 {
                        status = "disabled";
                };
        };
        pci0: pcie@ffe08000 {
                status = "disabled";
        };
-        pci1: pcie@ffe09000 {
-                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
        pci2: pcie@ffe0a000 {
                status = "disabled";
        };
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 261c34ba45ec..9bd8ef493dd2 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,28 +15,18 @@
 * option) any later version.
 */
-/include/ "p2020si.dtsi"
+/include/ "p2020rdb.dts"
 / {
        model = "fsl,P2020RDB";
        compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
-        aliases {
-                ethernet0 = &enet0;
-                serial0 = &serial1;
-                pci1 = &pci1;
-        };
        cpus {
                PowerPC,P2020@0 {
-                status = "disabled";
+                        status = "disabled";
                };
        };
-        memory {
-                device_type = "memory";
-        };
        localbus@ffe05000 {
                status = "disabled";
        };
@@ -70,55 +60,10 @@
                        status = "disabled";
                };
-                dma@c300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0xc300 0x4>;
-                        ranges = <0x0 0xc100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <76 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <77 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <78 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <79 2>;
-                        };
-                };
                gpio: gpio-controller@f000 {
                        status = "disabled";
                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p2020-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2,512K
-                        interrupt-parent = <&mpic>;
-                };
                dma@21300 {
                        status = "disabled";
                };
@@ -139,12 +84,6 @@
                        status = "disabled";
                };
-                enet0: ethernet@24000 {
-                        fixed-link = <1 1 1000 0 0>;
-                        phy-connection-type = "rgmii-id";
-                };
                enet1: ethernet@25000 {
                        status = "disabled";
                };
@@ -170,22 +109,6 @@
                        >;
                };
-                msi@41600 {
-                        compatible = "fsl,p2020-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
                global-utilities@e0000 {        //global utilities block
                        status = "disabled";
                };
@@ -199,30 +122,4 @@
        pci1: pcie@ffe09000 {
                status = "disabled";
        };
-        pci2: pcie@ffe0a000 {
-                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
-                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
-                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
-                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
-                        >;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
 };
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
deleted file mode 100644
index 6def17f265d3..000000000000
--- a/arch/powerpc/boot/dts/p2020si.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * P2020 Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P2020";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                PowerPC,P2020@0 {
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-                PowerPC,P2020@1 {
-                        device_type = "cpu";
-                        reg = <0x1>;
-                        next-level-cache = <&L2>;
-                };
-        };
-        localbus@ffe05000 {
-                #address-cells = <2>;
-                #size-cells = <1>;
-                compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
-                reg = <0 0xffe05000 0 0x1000>;
-                interrupts = <19 2>;
-                interrupt-parent = <&mpic>;
-        };
-        soc@ffe00000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "fsl,p2020-immr", "simple-bus";
-                ranges = <0x0  0x0 0xffe00000 0x100000>;
-                bus-frequency = <0>;            // Filled out by uboot.
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <12>;
-                };
-                ecm@1000 {
-                        compatible = "fsl,p2020-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                memory-controller@2000 {
-                        compatible = "fsl,p2020-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <18 2>;
-                };
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <43 2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-                serial0: serial@4500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                serial1: serial@4600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x4600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <42 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                spi@7000 {
-                        cell-index = <0>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,espi";
-                        reg = <0x7000 0x1000>;
-                        interrupts = <59 0x2>;
-                        interrupt-parent = <&mpic>;
-                        mode = "cpu";
-                };
-                dma@c300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0xc300 0x4>;
-                        ranges = <0x0 0xc100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <76 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <77 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <78 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <79 2>;
-                        };
-                };
-                gpio: gpio-controller@f000 {
-                        #gpio-cells = <2>;
-                        compatible = "fsl,mpc8572-gpio";
-                        reg = <0xf000 0x100>;
-                        interrupts = <47 0x2>;
-                        interrupt-parent = <&mpic>;
-                        gpio-controller;
-                };
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,p2020-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <32>; // 32 bytes
-                        cache-size = <0x80000>; // L2,512K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <16 2>;
-                };
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-                usb@22000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x22000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <28 0x2>;
-                };
-                mdio@24520 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,gianfar-mdio";
-                        reg = <0x24520 0x20>;
-                };
-                mdio@25520 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,gianfar-tbi";
-                        reg = <0x26520 0x20>;
-                };
-                mdio@26520 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,gianfar-tbi";
-                        reg = <0x520 0x20>;
-                };
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2 30 2 34 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <35 2 36 2 40 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                enet2: ethernet@26000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <2>;
-                        device_type = "network";
-                        model = "eTSEC";
-                        compatible = "gianfar";
-                        reg = <0x26000 0x1000>;
-                        ranges = <0x0 0x26000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <31 2 32 2 33 2>;
-                        interrupt-parent = <&mpic>;
-                };
-                sdhci@2e000 {
-                        compatible = "fsl,p2020-esdhc", "fsl,esdhc";
-                        reg = <0x2e000 0x1000>;
-                        interrupts = <72 0x2>;
-                        interrupt-parent = <&mpic>;
-                        /* Filled in by U-Boot */
-                        clock-frequency = <0>;
-                };
-                crypto@30000 {
-                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
-                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
-                        reg = <0x30000 0x10000>;
-                        interrupts = <45 2 58 2>;
-                        interrupt-parent = <&mpic>;
-                        fsl,num-channels = <4>;
-                        fsl,channel-fifo-len = <24>;
-                        fsl,exec-units-mask = <0xbfe>;
-                        fsl,descriptor-types-mask = <0x3ab0ebf>;
-                };
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi@41600 {
-                        compatible = "fsl,p2020-msi", "fsl,mpic-msi";
-                        reg = <0x41600 0x80>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
-                        interrupt-parent = <&mpic>;
-                };
-                global-utilities@e0000 {        //global utilities block
-                        compatible = "fsl,p2020-guts";
-                        reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
-                };
-        };
-        pci0: pcie@ffe08000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe08000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <24 2>;
-        };
-        pci1: pcie@ffe09000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe09000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <25 2>;
-        };
-        pci2: pcie@ffe0a000 {
-                compatible = "fsl,mpc8548-pcie";
-                device_type = "pci";
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                reg = <0 0xffe0a000 0 0x1000>;
-                bus-range = <0 255>;
-                clock-frequency = <33333333>;
-                interrupt-parent = <&mpic>;
-                interrupts = <26 2>;
-        };
-};
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 79b6895027c0..4f957db01230 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -32,7 +32,7 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/include/ "p2041si.dtsi"
+/include/ "fsl/p2041si-pre.dtsi"
 / {
        model = "fsl,P2041RDB";
@@ -50,6 +50,8 @@
        };
        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
                spi@110000 {
                        flash@0 {
                                #address-cells = <1>;
@@ -106,7 +108,18 @@
                };
        };
-        localbus@ffe124000 {
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
+        lbc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x1000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000>;
@@ -122,6 +135,7 @@
                reg = <0xf 0xfe200000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                fsl,msi = <&msi0>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -137,6 +151,7 @@
                reg = <0xf 0xfe201000 0 0x1000>;
                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                fsl,msi = <&msi1>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -152,6 +167,7 @@
                reg = <0xf 0xfe202000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -163,3 +179,5 @@
                };
        };
 };
+/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2041si.dtsi b/arch/powerpc/boot/dts/p2041si.dtsi
deleted file mode 100644
index f7492edd0dfd..000000000000
--- a/arch/powerpc/boot/dts/p2041si.dtsi
+++ /dev/null
@@ -1,692 +0,0 @@
-/*
- * P2041 Silicon Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P2041";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                sdhc = &sdhc;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,e500mc@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e500mc@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu2: PowerPC,e500mc@2 {
-                        device_type = "cpu";
-                        reg = <2>;
-                        next-level-cache = <&L2_2>;
-                        L2_2: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu3: PowerPC,e500mc@3 {
-                        device_type = "cpu";
-                        reg = <3>;
-                        next-level-cache = <&L2_3>;
-                        L2_3: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-        };
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                dcsr-epu@0 {
-                        compatible = "fsl,dcsr-epu";
-                        interrupts = <52 2 0 0
-                                      84 2 0 0
-                                      85 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        reg = <0x0 0x1000>;
-                };
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr>;
-                        reg = <0x12000 0x1000>;
-                };
-                dcsr-nal@18000 {
-                        compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@42000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu2>;
-                        reg = <0x42000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@43000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu3>;
-                        reg = <0x43000 0x1000>;
-                };
-        };
-        soc: soc@ffe000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                soc-sram-error {
-                        compatible = "fsl,soc-sram-error";
-                        interrupts = <16 2 1 29>;
-                };
-                corenet-law@0 {
-                        compatible = "fsl,corenet-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <32>;
-                };
-                ddr: memory-controller@8000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
-                        reg = <0x8000 0x1000>;
-                        interrupts = <16 2 1 23>;
-                };
-                cpc: l3-cache-controller@10000 {
-                        compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
-                        reg = <0x10000 0x1000>;
-                        interrupts = <16 2 1 27>;
-                };
-                corenet-cf@18000 {
-                        compatible = "fsl,corenet-cf";
-                        reg = <0x18000 0x1000>;
-                        interrupts = <16 2 1 31>;
-                        fsl,ccf-num-csdids = <32>;
-                        fsl,ccf-num-snoopids = <32>;
-                };
-                iommu@20000 {
-                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                        reg = <0x20000 0x4000>;
-                        interrupts = <
-                                24 2 0 0
-                                16 2 1 30>;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic", "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi0: msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41600 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                msi1: msi@41800 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41800 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe8 0 0 0
-                                0xe9 0 0 0
-                                0xea 0 0 0
-                                0xeb 0 0 0
-                                0xec 0 0 0
-                                0xed 0 0 0
-                                0xee 0 0 0
-                                0xef 0 0 0>;
-                };
-                msi2: msi@41a00 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41a00 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xf0 0 0 0
-                                0xf1 0 0 0
-                                0xf2 0 0 0
-                                0xf3 0 0 0
-                                0xf4 0 0 0
-                                0xf5 0 0 0
-                                0xf6 0 0 0
-                                0xf7 0 0 0>;
-                };
-                guts: global-utilities@e0000 {
-                        compatible = "fsl,qoriq-device-config-1.0";
-                        reg = <0xe0000 0xe00>;
-                        fsl,has-rstcr;
-                        #sleep-cells = <1>;
-                        fsl,liodn-bits = <12>;
-                };
-                pins: global-utilities@e0e00 {
-                        compatible = "fsl,qoriq-pin-control-1.0";
-                        reg = <0xe0e00 0x200>;
-                        #sleep-cells = <2>;
-                };
-                clockgen: global-utilities@e1000 {
-                        compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
-                        reg = <0xe1000 0x1000>;
-                        clock-frequency = <0>;
-                };
-                rcpm: global-utilities@e2000 {
-                        compatible = "fsl,qoriq-rcpm-1.0";
-                        reg = <0xe2000 0x1000>;
-                        #sleep-cells = <1>;
-                };
-                sfp: sfp@e8000 {
-                        compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
-                        reg        = <0xe8000 0x1000>;
-                };
-                serdes: serdes@ea000 {
-                        compatible = "fsl,p2041-serdes";
-                        reg        = <0xea000 0x1000>;
-                };
-                dma0: dma@100300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
-                        reg = <0x100300 0x4>;
-                        ranges = <0x0 0x100100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <28 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <29 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <30 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <31 2 0 0>;
-                        };
-                };
-                dma1: dma@101300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
-                        reg = <0x101300 0x4>;
-                        ranges = <0x0 0x101100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <32 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <33 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <34 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p2041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <35 2 0 0>;
-                        };
-                };
-                spi@110000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
-                        reg = <0x110000 0x1000>;
-                        interrupts = <53 0x2 0 0>;
-                        fsl,espi-num-chipselects = <4>;
-                };
-                sdhc: sdhc@114000 {
-                        compatible = "fsl,p2041-esdhc", "fsl,esdhc";
-                        reg = <0x114000 0x1000>;
-                        interrupts = <48 2 0 0>;
-                        sdhci,auto-cmd12;
-                        clock-frequency = <0>;
-                };
-                i2c@118000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118000 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@118100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118100 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <2>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119000 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <3>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119100 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                serial0: serial@11c500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial1: serial@11c600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial2: serial@11d500 {
-                        cell-index = <2>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                serial3: serial@11d600 {
-                        cell-index = <3>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                gpio0: gpio@130000 {
-                        compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
-                        reg = <0x130000 0x1000>;
-                        interrupts = <55 2 0 0>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                };
-                usb0: usb@210000 {
-                        compatible = "fsl,p2041-usb2-mph",
-                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x210000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <44 0x2 0 0>;
-                        phy_type = "utmi";
-                        port0;
-                };
-                usb1: usb@211000 {
-                        compatible = "fsl,p2041-usb2-dr",
-                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x211000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <45 0x2 0 0>;
-                        phy_type = "utmi";
-                };
-                sata@220000 {
-                        compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
-                        reg = <0x220000 0x1000>;
-                        interrupts = <68 0x2 0 0>;
-                };
-                sata@221000 {
-                        compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
-                        reg = <0x221000 0x1000>;
-                        interrupts = <69 0x2 0 0>;
-                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x300000 0x10000>;
-                        ranges = <0 0x300000 0x10000>;
-                        interrupts = <92 2 0 0>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <88 2 0 0>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <89 2 0 0>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <90 2 0 0>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupts = <91 2 0 0>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.2-rtic",
-                                             "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                sec_mon: sec_mon@314000 {
-                        compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
-                        reg = <0x314000 0x1000>;
-                        interrupts = <93 2 0 0>;
-                };
-        };
-        localbus@ffe124000 {
-                compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
-                interrupts = <25 2 0 0>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-        };
-        pci0: pcie@ffe200000 {
-                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <33333333>;
-                fsl,msi = <&msi0>;
-                interrupts = <16 2 1 15>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 15>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 40 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                };
-        };
-        pci1: pcie@ffe201000 {
-                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0 0xff>;
-                clock-frequency = <33333333>;
-                fsl,msi = <&msi1>;
-                interrupts = <16 2 1 14>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 14>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 41 1 0 0
-                                0000 0 0 2 &mpic 5 1 0 0
-                                0000 0 0 3 &mpic 6 1 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                };
-        };
-        pci2: pcie@ffe202000 {
-                compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <33333333>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 13>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 13>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 42 1 0 0
-                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 1 0 0
-                                >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index bbd113b49a8f..f469145abaeb 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -32,7 +32,7 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/include/ "p3041si.dtsi"
+/include/ "fsl/p3041si-pre.dtsi"
 / {
        model = "fsl,P3041DS";
@@ -50,6 +50,8 @@
        };
        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
                spi@110000 {
                        flash@0 {
                                #address-cells = <1>;
@@ -99,7 +101,18 @@
                };
        };
-        localbus@ffe124000 {
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
+        lbc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x1000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                          2 0 0xf 0xffa00000 0x00040000
@@ -160,6 +173,7 @@
                reg = <0xf 0xfe200000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                fsl,msi = <&msi0>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -175,6 +189,7 @@
                reg = <0xf 0xfe201000 0 0x1000>;
                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                fsl,msi = <&msi1>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -190,6 +205,7 @@
                reg = <0xf 0xfe202000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -205,6 +221,7 @@
                reg = <0xf 0xfe203000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -216,3 +233,5 @@
                };
        };
 };
+/include/ "fsl/p3041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
deleted file mode 100644
index 87130b732bc7..000000000000
--- a/arch/powerpc/boot/dts/p3041si.dtsi
+++ /dev/null
@@ -1,729 +0,0 @@
-/*
- * P3041 Silicon Device Tree Source
- *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P3041";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                pci3 = &pci3;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                sdhc = &sdhc;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
-/*
-                rio0 = &rapidio0;
- */
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,e500mc@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e500mc@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu2: PowerPC,e500mc@2 {
-                        device_type = "cpu";
-                        reg = <2>;
-                        next-level-cache = <&L2_2>;
-                        L2_2: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu3: PowerPC,e500mc@3 {
-                        device_type = "cpu";
-                        reg = <3>;
-                        next-level-cache = <&L2_3>;
-                        L2_3: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-        };
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                dcsr-epu@0 {
-                        compatible = "fsl,dcsr-epu";
-                        interrupts = <52 2 0 0
-                                      84 2 0 0
-                                      85 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        reg = <0x0 0x1000>;
-                };
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr>;
-                        reg = <0x12000 0x1000>;
-                };
-                dcsr-nal@18000 {
-                        compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@42000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu2>;
-                        reg = <0x42000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@43000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu3>;
-                        reg = <0x43000 0x1000>;
-                };
-        };
-        soc: soc@ffe000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                soc-sram-error {
-                        compatible = "fsl,soc-sram-error";
-                        interrupts = <16 2 1 29>;
-                };
-                corenet-law@0 {
-                        compatible = "fsl,corenet-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <32>;
-                };
-                ddr: memory-controller@8000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
-                        reg = <0x8000 0x1000>;
-                        interrupts = <16 2 1 23>;
-                };
-                cpc: l3-cache-controller@10000 {
-                        compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
-                        reg = <0x10000 0x1000>;
-                        interrupts = <16 2 1 27>;
-                };
-                corenet-cf@18000 {
-                        compatible = "fsl,corenet-cf";
-                        reg = <0x18000 0x1000>;
-                        interrupts = <16 2 1 31>;
-                        fsl,ccf-num-csdids = <32>;
-                        fsl,ccf-num-snoopids = <32>;
-                };
-                iommu@20000 {
-                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                        reg = <0x20000 0x4000>;
-                        interrupts = <
-                                24 2 0 0
-                                16 2 1 30>;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic", "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi0: msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41600 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                msi1: msi@41800 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41800 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe8 0 0 0
-                                0xe9 0 0 0
-                                0xea 0 0 0
-                                0xeb 0 0 0
-                                0xec 0 0 0
-                                0xed 0 0 0
-                                0xee 0 0 0
-                                0xef 0 0 0>;
-                };
-                msi2: msi@41a00 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41a00 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xf0 0 0 0
-                                0xf1 0 0 0
-                                0xf2 0 0 0
-                                0xf3 0 0 0
-                                0xf4 0 0 0
-                                0xf5 0 0 0
-                                0xf6 0 0 0
-                                0xf7 0 0 0>;
-                };
-                guts: global-utilities@e0000 {
-                        compatible = "fsl,qoriq-device-config-1.0";
-                        reg = <0xe0000 0xe00>;
-                        fsl,has-rstcr;
-                        #sleep-cells = <1>;
-                        fsl,liodn-bits = <12>;
-                };
-                pins: global-utilities@e0e00 {
-                        compatible = "fsl,qoriq-pin-control-1.0";
-                        reg = <0xe0e00 0x200>;
-                        #sleep-cells = <2>;
-                };
-                clockgen: global-utilities@e1000 {
-                        compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
-                        reg = <0xe1000 0x1000>;
-                        clock-frequency = <0>;
-                };
-                rcpm: global-utilities@e2000 {
-                        compatible = "fsl,qoriq-rcpm-1.0";
-                        reg = <0xe2000 0x1000>;
-                        #sleep-cells = <1>;
-                };
-                sfp: sfp@e8000 {
-                        compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
-                        reg        = <0xe8000 0x1000>;
-                };
-                serdes: serdes@ea000 {
-                        compatible = "fsl,p3041-serdes";
-                        reg        = <0xea000 0x1000>;
-                };
-                dma0: dma@100300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
-                        reg = <0x100300 0x4>;
-                        ranges = <0x0 0x100100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <28 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <29 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <30 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <31 2 0 0>;
-                        };
-                };
-                dma1: dma@101300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
-                        reg = <0x101300 0x4>;
-                        ranges = <0x0 0x101100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <32 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <33 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <34 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p3041-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <35 2 0 0>;
-                        };
-                };
-                spi@110000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
-                        reg = <0x110000 0x1000>;
-                        interrupts = <53 0x2 0 0>;
-                        fsl,espi-num-chipselects = <4>;
-                };
-                sdhc: sdhc@114000 {
-                        compatible = "fsl,p3041-esdhc", "fsl,esdhc";
-                        reg = <0x114000 0x1000>;
-                        interrupts = <48 2 0 0>;
-                        sdhci,auto-cmd12;
-                        clock-frequency = <0>;
-                };
-                i2c@118000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118000 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@118100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118100 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <2>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119000 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <3>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119100 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                serial0: serial@11c500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial1: serial@11c600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial2: serial@11d500 {
-                        cell-index = <2>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                serial3: serial@11d600 {
-                        cell-index = <3>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                gpio0: gpio@130000 {
-                        compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
-                        reg = <0x130000 0x1000>;
-                        interrupts = <55 2 0 0>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                };
-                usb0: usb@210000 {
-                        compatible = "fsl,p3041-usb2-mph",
-                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x210000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <44 0x2 0 0>;
-                        phy_type = "utmi";
-                        port0;
-                };
-                usb1: usb@211000 {
-                        compatible = "fsl,p3041-usb2-dr",
-                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x211000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <45 0x2 0 0>;
-                        dr_mode = "host";
-                        phy_type = "utmi";
-                };
-                sata@220000 {
-                        compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
-                        reg = <0x220000 0x1000>;
-                        interrupts = <68 0x2 0 0>;
-                };
-                sata@221000 {
-                        compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
-                        reg = <0x221000 0x1000>;
-                        interrupts = <69 0x2 0 0>;
-                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg              = <0x300000 0x10000>;
-                        ranges           = <0 0x300000 0x10000>;
-                        interrupts       = <92 2 0 0>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <88 2 0 0>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <89 2 0 0>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <90 2 0 0>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupts = <91 2 0 0>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.2-rtic",
-                                             "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                sec_mon: sec_mon@314000 {
-                        compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
-                        reg = <0x314000 0x1000>;
-                        interrupts = <93 2 0 0>;
-                };
-        };
-/*
-        rapidio0: rapidio@ffe0c0000
-*/
-        localbus@ffe124000 {
-                compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
-                interrupts = <25 2 0 0>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-        };
-        pci0: pcie@ffe200000 {
-                compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi0>;
-                interrupts = <16 2 1 15>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 15>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 40 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                };
-        };
-        pci1: pcie@ffe201000 {
-                compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi1>;
-                interrupts = <16 2 1 14>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 14>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 41 1 0 0
-                                0000 0 0 2 &mpic 5 1 0 0
-                                0000 0 0 3 &mpic 6 1 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                };
-        };
-        pci2: pcie@ffe202000 {
-                compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 13>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 13>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 42 1 0 0
-                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 1 0 0
-                                >;
-                };
-        };
-        pci3: pcie@ffe203000 {
-                compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 12>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 12>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 43 1 0 0
-                                0000 0 0 2 &mpic 0 1 0 0
-                                0000 0 0 3 &mpic 4 1 0 0
-                                0000 0 0 4 &mpic 8 1 0 0
-                                >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
index 08b9193213e7..529042e4b9a2 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -32,7 +32,7 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/include/ "p3060si.dtsi"
+/include/ "fsl/p3060si-pre.dtsi"
 / {
        model = "fsl,P3060QDS";
@@ -50,6 +50,8 @@
        };
        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
                spi@110000 {
                        flash@0 {
                                #address-cells = <1>;
@@ -138,7 +140,7 @@
                };
        };
-        rapidio@ffe0c0000 {
+        rio: rapidio@ffe0c0000 {
                reg = <0xf 0xfe0c0000 0 0x11000>;
                port1 {
@@ -149,7 +151,7 @@
                };
        };
-        localbus@ffe124000 {
+        lbc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x1000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                          2 0 0xf 0xffa00000 0x00040000
@@ -210,6 +212,7 @@
                reg = <0xf 0xfe200000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                fsl,msi = <&msi0>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -225,6 +228,7 @@
                reg = <0xf 0xfe201000 0 0x1000>;
                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                fsl,msi = <&msi1>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -236,3 +240,5 @@
                };
        };
 };
+/include/ "fsl/p3060si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3060si.dtsi b/arch/powerpc/boot/dts/p3060si.dtsi
deleted file mode 100644
index 68947e157bbc..000000000000
--- a/arch/powerpc/boot/dts/p3060si.dtsi
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * P3060 Silicon Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P3060";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,e500mc@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e500mc@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu4: PowerPC,e500mc@4 {
-                        device_type = "cpu";
-                        reg = <4>;
-                        next-level-cache = <&L2_4>;
-                        L2_4: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu5: PowerPC,e500mc@5 {
-                        device_type = "cpu";
-                        reg = <5>;
-                        next-level-cache = <&L2_5>;
-                        L2_5: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu6: PowerPC,e500mc@6 {
-                        device_type = "cpu";
-                        reg = <6>;
-                        next-level-cache = <&L2_6>;
-                        L2_6: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu7: PowerPC,e500mc@7 {
-                        device_type = "cpu";
-                        reg = <7>;
-                        next-level-cache = <&L2_7>;
-                        L2_7: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-        };
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                dcsr-epu@0 {
-                        compatible = "fsl,dcsr-epu";
-                        interrupts = <52 2 0 0
-                                      84 2 0 0
-                                      85 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        reg = <0x0 0x1000>;
-                };
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr>;
-                        reg = <0x12000 0x1000>;
-                };
-                dcsr-nal@18000 {
-                        compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@44000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu4>;
-                        reg = <0x44000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@45000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu5>;
-                        reg = <0x45000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@46000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu6>;
-                        reg = <0x46000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@47000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu7>;
-                        reg = <0x47000 0x1000>;
-                };
-        };
-        soc: soc@ffe000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                soc-sram-error {
-                        compatible = "fsl,soc-sram-error";
-                        interrupts = <16 2 1 29>;
-                };
-                corenet-law@0 {
-                        compatible = "fsl,corenet-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <32>;
-                };
-                ddr: memory-controller@8000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
-                        reg = <0x8000 0x1000>;
-                        interrupts = <16 2 1 23>;
-                };
-                cpc: l3-cache-controller@10000 {
-                        compatible = "fsl,p3060-l3-cache-controller", "cache";
-                        reg = <0x10000 0x1000
-                               0x11000 0x1000>;
-                        interrupts = <16 2 1 27>;
-                };
-                corenet-cf@18000 {
-                        compatible = "fsl,corenet-cf";
-                        reg = <0x18000 0x1000>;
-                        interrupts = <16 2 1 31>;
-                        fsl,ccf-num-csdids = <32>;
-                        fsl,ccf-num-snoopids = <32>;
-                };
-                iommu@20000 {
-                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                        reg = <0x20000 0x5000>;
-                        interrupts = <
-                                24 2 0 0
-                                16 2 1 30>;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic", "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi0: msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41600 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                msi1: msi@41800 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41800 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe8 0 0 0
-                                0xe9 0 0 0
-                                0xea 0 0 0
-                                0xeb 0 0 0
-                                0xec 0 0 0
-                                0xed 0 0 0
-                                0xee 0 0 0
-                                0xef 0 0 0>;
-                };
-                msi2: msi@41a00 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41a00 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xf0 0 0 0
-                                0xf1 0 0 0
-                                0xf2 0 0 0
-                                0xf3 0 0 0
-                                0xf4 0 0 0
-                                0xf5 0 0 0
-                                0xf6 0 0 0
-                                0xf7 0 0 0>;
-                };
-                rmu: rmu@d3000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,srio-rmu";
-                        reg = <0xd3000 0x500>;
-                        ranges = <0x0 0xd3000 0x500>;
-                        message-unit@0 {
-                                compatible = "fsl,srio-msg-unit";
-                                reg = <0x0 0x100>;
-                                interrupts = <
-                                        60 2 0 0  /* msg1_tx_irq */
-                                        61 2 0 0>;/* msg1_rx_irq */
-                        };
-                        message-unit@100 {
-                                compatible = "fsl,srio-msg-unit";
-                                reg = <0x100 0x100>;
-                                interrupts = <
-                                        62 2 0 0  /* msg2_tx_irq */
-                                        63 2 0 0>;/* msg2_rx_irq */
-                        };
-                        doorbell-unit@400 {
-                                compatible = "fsl,srio-dbell-unit";
-                                reg = <0x400 0x80>;
-                                interrupts = <
-                                        56 2 0 0  /* bell_outb_irq */
-                                        57 2 0 0>;/* bell_inb_irq */
-                        };
-                        port-write-unit@4e0 {
-                                compatible = "fsl,srio-port-write-unit";
-                                reg = <0x4e0 0x20>;
-                                interrupts = <16 2 1 11>;
-                        };
-                };
-                guts: global-utilities@e0000 {
-                        compatible = "fsl,qoriq-device-config-1.0";
-                        reg = <0xe0000 0xe00>;
-                        fsl,has-rstcr;
-                        #sleep-cells = <1>;
-                        fsl,liodn-bits = <12>;
-                };
-                pins: global-utilities@e0e00 {
-                        compatible = "fsl,qoriq-pin-control-1.0";
-                        reg = <0xe0e00 0x200>;
-                        #sleep-cells = <2>;
-                };
-                clockgen: global-utilities@e1000 {
-                        compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
-                        reg = <0xe1000 0x1000>;
-                        clock-frequency = <0>;
-                };
-                rcpm: global-utilities@e2000 {
-                        compatible = "fsl,qoriq-rcpm-1.0";
-                        reg = <0xe2000 0x1000>;
-                        #sleep-cells = <1>;
-                };
-                sfp: sfp@e8000 {
-                        compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
-                        reg        = <0xe8000 0x1000>;
-                };
-                serdes: serdes@ea000 {
-                        compatible = "fsl,p3060-serdes";
-                        reg        = <0xea000 0x1000>;
-                };
-                dma0: dma@100300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
-                        reg = <0x100300 0x4>;
-                        ranges = <0x0 0x100100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <28 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <29 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <30 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <31 2 0 0>;
-                        };
-                };
-                dma1: dma@101300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
-                        reg = <0x101300 0x4>;
-                        ranges = <0x0 0x101100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <32 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <33 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <34 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p3060-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <35 2 0 0>;
-                        };
-                };
-                spi@110000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p3060-espi", "fsl,mpc8536-espi";
-                        reg = <0x110000 0x1000>;
-                        interrupts = <53 0x2 0 0>;
-                        fsl,espi-num-chipselects = <4>;
-                };
-                i2c@118000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118000 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@118100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118100 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <2>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119000 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <3>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119100 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                serial0: serial@11c500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial1: serial@11c600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial2: serial@11d500 {
-                        cell-index = <2>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                serial3: serial@11d600 {
-                        cell-index = <3>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                gpio0: gpio@130000 {
-                        compatible = "fsl,p3060-gpio", "fsl,qoriq-gpio";
-                        reg = <0x130000 0x1000>;
-                        interrupts = <55 2 0 0>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                };
-                usb0: usb@210000 {
-                        compatible = "fsl,p3060-usb2-mph",
-                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x210000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <44 0x2 0 0>;
-                };
-                usb1: usb@211000 {
-                        compatible = "fsl,p3060-usb2-dr",
-                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x211000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <45 0x2 0 0>;
-                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x300000 0x10000>;
-                        ranges = <0 0x300000 0x10000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <92 2 0 0>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <88 2 0 0>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <89 2 0 0>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <90 2 0 0>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <91 2 0 0>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.1-rtic", "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                sec_mon: sec_mon@314000 {
-                        compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
-                        reg = <0x314000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <93 2 0 0>;
-                };
-        };
-        rapidio@ffe0c0000 {
-                compatible = "fsl,srio";
-                interrupts = <16 2 1 11>;
-                #address-cells = <2>;
-                #size-cells = <2>;
-                fsl,srio-rmu-handle = <&rmu>;
-                ranges;
-                port1 {
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        cell-index = <1>;
-                };
-                port2 {
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        cell-index = <2>;
-                };
-        };
-        localbus@ffe124000 {
-                compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
-                interrupts = <25 2 0 0>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-        };
-        pci0: pcie@ffe200000 {
-                compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <33333333>;
-                fsl,msi = <&msi0>;
-                interrupts = <16 2 1 15>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 15>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 40 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                };
-        };
-        pci1: pcie@ffe201000 {
-                compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0 0xff>;
-                clock-frequency = <33333333>;
-                fsl,msi = <&msi1>;
-                interrupts = <16 2 1 14>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 14>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 41 1 0 0
-                                0000 0 0 2 &mpic 5 1 0 0
-                                0000 0 0 3 &mpic 6 1 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index c7916dc28014..6d60e54e50a0 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -32,7 +32,7 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/include/ "p4080si.dtsi"
+/include/ "fsl/p4080si-pre.dtsi"
 / {
        model = "fsl,P4080DS";
@@ -50,6 +50,9 @@
        };
        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
                spi@110000 {
                        flash@0 {
                                #address-cells = <1>;
@@ -105,12 +108,18 @@
                };
        };
-        rapidio0: rapidio@ffe0c0000 {
+        rio: rapidio@ffe0c0000 {
-                reg = <0xf 0xfe0c0000 0 0x20000>;
+                reg = <0xf 0xfe0c0000 0 0x11000>;
-                ranges = <0 0 0xc 0x20000000 0 0x01000000>;
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
        };
-        localbus@ffe124000 {
+        lbc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x1000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                          3 0 0xf 0xffdf0000 0x00008000>;
@@ -132,6 +141,7 @@
                reg = <0xf 0xfe200000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                fsl,msi = <&msi0>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -147,6 +157,7 @@
                reg = <0xf 0xfe201000 0 0x1000>;
                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                fsl,msi = <&msi1>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -162,6 +173,7 @@
                reg = <0xf 0xfe202000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -174,3 +186,5 @@
        };
 };
+/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
deleted file mode 100644
index f20c01ab2473..000000000000
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ /dev/null
@@ -1,755 +0,0 @@
-/*
- * P4080 Silicon Device Tree Source
- *
- * Copyright 2009-2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P4080";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                sdhc = &sdhc;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
-                rio0 = &rapidio0;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,e500mc@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e500mc@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu2: PowerPC,e500mc@2 {
-                        device_type = "cpu";
-                        reg = <2>;
-                        next-level-cache = <&L2_2>;
-                        L2_2: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu3: PowerPC,e500mc@3 {
-                        device_type = "cpu";
-                        reg = <3>;
-                        next-level-cache = <&L2_3>;
-                        L2_3: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu4: PowerPC,e500mc@4 {
-                        device_type = "cpu";
-                        reg = <4>;
-                        next-level-cache = <&L2_4>;
-                        L2_4: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu5: PowerPC,e500mc@5 {
-                        device_type = "cpu";
-                        reg = <5>;
-                        next-level-cache = <&L2_5>;
-                        L2_5: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu6: PowerPC,e500mc@6 {
-                        device_type = "cpu";
-                        reg = <6>;
-                        next-level-cache = <&L2_6>;
-                        L2_6: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu7: PowerPC,e500mc@7 {
-                        device_type = "cpu";
-                        reg = <7>;
-                        next-level-cache = <&L2_7>;
-                        L2_7: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-        };
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                dcsr-epu@0 {
-                        compatible = "fsl,dcsr-epu";
-                        interrupts = <52 2 0 0
-                                      84 2 0 0
-                                      85 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        reg = <0x0 0x1000>;
-                };
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr1>;
-                        reg = <0x12000 0x1000>;
-                };
-                dcsr-ddr@13000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr2>;
-                        reg = <0x13000 0x1000>;
-                };
-                dcsr-nal@18000 {
-                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@42000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu2>;
-                        reg = <0x42000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@43000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu3>;
-                        reg = <0x43000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@44000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu4>;
-                        reg = <0x44000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@45000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu5>;
-                        reg = <0x45000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@46000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu6>;
-                        reg = <0x46000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@47000 {
-                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu7>;
-                        reg = <0x47000 0x1000>;
-                };
-        };
-        soc: soc@ffe000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                soc-sram-error {
-                        compatible = "fsl,soc-sram-error";
-                        interrupts = <16 2 1 29>;
-                };
-                corenet-law@0 {
-                        compatible = "fsl,corenet-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <32>;
-                };
-                ddr1: memory-controller@8000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
-                        reg = <0x8000 0x1000>;
-                        interrupts = <16 2 1 23>;
-                };
-                ddr2: memory-controller@9000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
-                        reg = <0x9000 0x1000>;
-                        interrupts = <16 2 1 22>;
-                };
-                cpc: l3-cache-controller@10000 {
-                        compatible = "fsl,p4080-l3-cache-controller", "cache";
-                        reg = <0x10000 0x1000
-                               0x11000 0x1000>;
-                        interrupts = <16 2 1 27
-                                      16 2 1 26>;
-                };
-                corenet-cf@18000 {
-                        compatible = "fsl,corenet-cf";
-                        reg = <0x18000 0x1000>;
-                        interrupts = <16 2 1 31>;
-                        fsl,ccf-num-csdids = <32>;
-                        fsl,ccf-num-snoopids = <32>;
-                };
-                iommu@20000 {
-                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                        reg = <0x20000 0x5000>;
-                        interrupts = <
-                                24 2 0 0
-                                16 2 1 30>;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic", "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi0: msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41600 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                msi1: msi@41800 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41800 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe8 0 0 0
-                                0xe9 0 0 0
-                                0xea 0 0 0
-                                0xeb 0 0 0
-                                0xec 0 0 0
-                                0xed 0 0 0
-                                0xee 0 0 0
-                                0xef 0 0 0>;
-                };
-                msi2: msi@41a00 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41a00 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xf0 0 0 0
-                                0xf1 0 0 0
-                                0xf2 0 0 0
-                                0xf3 0 0 0
-                                0xf4 0 0 0
-                                0xf5 0 0 0
-                                0xf6 0 0 0
-                                0xf7 0 0 0>;
-                };
-                guts: global-utilities@e0000 {
-                        compatible = "fsl,qoriq-device-config-1.0";
-                        reg = <0xe0000 0xe00>;
-                        fsl,has-rstcr;
-                        #sleep-cells = <1>;
-                        fsl,liodn-bits = <12>;
-                };
-                pins: global-utilities@e0e00 {
-                        compatible = "fsl,qoriq-pin-control-1.0";
-                        reg = <0xe0e00 0x200>;
-                        #sleep-cells = <2>;
-                };
-                clockgen: global-utilities@e1000 {
-                        compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
-                        reg = <0xe1000 0x1000>;
-                        clock-frequency = <0>;
-                };
-                rcpm: global-utilities@e2000 {
-                        compatible = "fsl,qoriq-rcpm-1.0";
-                        reg = <0xe2000 0x1000>;
-                        #sleep-cells = <1>;
-                };
-                sfp: sfp@e8000 {
-                        compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
-                        reg        = <0xe8000 0x1000>;
-                };
-                serdes: serdes@ea000 {
-                        compatible = "fsl,p4080-serdes";
-                        reg        = <0xea000 0x1000>;
-                };
-                dma0: dma@100300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
-                        reg = <0x100300 0x4>;
-                        ranges = <0x0 0x100100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <28 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <29 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <30 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <31 2 0 0>;
-                        };
-                };
-                dma1: dma@101300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
-                        reg = <0x101300 0x4>;
-                        ranges = <0x0 0x101100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <32 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <33 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <34 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p4080-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <35 2 0 0>;
-                        };
-                };
-                spi@110000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
-                        reg = <0x110000 0x1000>;
-                        interrupts = <53 0x2 0 0>;
-                        fsl,espi-num-chipselects = <4>;
-                };
-                sdhc: sdhc@114000 {
-                        compatible = "fsl,p4080-esdhc", "fsl,esdhc";
-                        reg = <0x114000 0x1000>;
-                        interrupts = <48 2 0 0>;
-                        voltage-ranges = <3300 3300>;
-                        sdhci,auto-cmd12;
-                        clock-frequency = <0>;
-                };
-                i2c@118000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118000 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@118100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118100 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <2>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119000 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <3>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119100 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                serial0: serial@11c500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial1: serial@11c600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial2: serial@11d500 {
-                        cell-index = <2>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                serial3: serial@11d600 {
-                        cell-index = <3>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                gpio0: gpio@130000 {
-                        compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
-                        reg = <0x130000 0x1000>;
-                        interrupts = <55 2 0 0>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                };
-                usb0: usb@210000 {
-                        compatible = "fsl,p4080-usb2-mph",
-                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x210000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <44 0x2 0 0>;
-                };
-                usb1: usb@211000 {
-                        compatible = "fsl,p4080-usb2-dr",
-                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x211000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <45 0x2 0 0>;
-                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x300000 0x10000>;
-                        ranges = <0 0x300000 0x10000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <92 2 0 0>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <88 2 0 0>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <89 2 0 0>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <90 2 0 0>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <91 2 0 0>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                sec_mon: sec_mon@314000 {
-                        compatible = "fsl,sec-v4.0-mon";
-                        reg = <0x314000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <93 2 0 0>;
-                };
-        };
-        rapidio0: rapidio@ffe0c0000 {
-                #address-cells = <2>;
-                #size-cells = <2>;
-                compatible = "fsl,rapidio-delta";
-                interrupts = <
-                        16 2 1 11 /* err_irq */
-                        56 2 0 0  /* bell_outb_irq */
-                        57 2 0 0  /* bell_inb_irq */
-                        60 2 0 0  /* msg1_tx_irq */
-                        61 2 0 0  /* msg1_rx_irq */
-                        62 2 0 0  /* msg2_tx_irq */
-                        63 2 0 0>; /* msg2_rx_irq */
-        };
-        localbus@ffe124000 {
-                compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
-                interrupts = <25 2 0 0>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-        };
-        pci0: pcie@ffe200000 {
-                compatible = "fsl,p4080-pcie";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi0>;
-                interrupts = <16 2 1 15>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 15>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 40 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                };
-        };
-        pci1: pcie@ffe201000 {
-                compatible = "fsl,p4080-pcie";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi1>;
-                interrupts = <16 2 1 14>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 14>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 41 1 0 0
-                                0000 0 0 2 &mpic 5 1 0 0
-                                0000 0 0 3 &mpic 6 1 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                };
-        };
-        pci2: pcie@ffe202000 {
-                compatible = "fsl,p4080-pcie";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 13>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 13>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 42 1 0 0
-                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 1 0 0
-                                >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index e6d40999ccd7..1c250684c902 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -32,7 +32,7 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-/include/ "p5020si.dtsi"
+/include/ "fsl/p5020si-pre.dtsi"
 / {
        model = "fsl,P5020DS";
@@ -50,6 +50,8 @@
        };
        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
                spi@110000 {
                        flash@0 {
                                #address-cells = <1>;
@@ -99,7 +101,18 @@
                };
        };
-        localbus@ffe124000 {
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
+        lbc: localbus@ffe124000 {
                reg = <0xf 0xfe124000 0 0x1000>;
                ranges = <0 0 0xf 0xe8000000 0x08000000
                          2 0 0xf 0xffa00000 0x00040000
@@ -160,7 +173,7 @@
                reg = <0xf 0xfe200000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                fsl,msi = <&msi0>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -176,6 +189,7 @@
                reg = <0xf 0xfe201000 0 0x1000>;
                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                fsl,msi = <&msi1>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -191,6 +205,7 @@
                reg = <0xf 0xfe202000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -206,6 +221,7 @@
                reg = <0xf 0xfe203000 0 0x1000>;
                ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
                          0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+                fsl,msi = <&msi2>;
                pcie@0 {
                        ranges = <0x02000000 0 0xe0000000
                                  0x02000000 0 0xe0000000
@@ -217,3 +233,5 @@
                };
        };
 };
+/include/ "fsl/p5020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
deleted file mode 100644
index e7948ad71fa3..000000000000
--- a/arch/powerpc/boot/dts/p5020si.dtsi
+++ /dev/null
@@ -1,716 +0,0 @@
-/*
- * P5020 Silicon Device Tree Source
- *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/dts-v1/;
-/ {
-        compatible = "fsl,P5020";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-                pci3 = &pci3;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                sdhc = &sdhc;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
-/*
-                rio0 = &rapidio0;
- */
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: PowerPC,e5500@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e5500@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-        };
-        dcsr: dcsr@f00000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,dcsr", "simple-bus";
-                dcsr-epu@0 {
-                        compatible = "fsl,dcsr-epu";
-                        interrupts = <52 2 0 0
-                                      84 2 0 0
-                                      85 2 0 0>;
-                        interrupt-parent = <&mpic>;
-                        reg = <0x0 0x1000>;
-                };
-                dcsr-npc {
-                        compatible = "fsl,dcsr-npc";
-                        reg = <0x1000 0x1000 0x1000000 0x8000>;
-                };
-                dcsr-nxc@2000 {
-                        compatible = "fsl,dcsr-nxc";
-                        reg = <0x2000 0x1000>;
-                };
-                dcsr-corenet {
-                        compatible = "fsl,dcsr-corenet";
-                        reg = <0x8000 0x1000 0xB0000 0x1000>;
-                };
-                dcsr-dpaa@9000 {
-                        compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
-                        reg = <0x9000 0x1000>;
-                };
-                dcsr-ocn@11000 {
-                        compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
-                        reg = <0x11000 0x1000>;
-                };
-                dcsr-ddr@12000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr1>;
-                        reg = <0x12000 0x1000>;
-                };
-                dcsr-ddr@13000 {
-                        compatible = "fsl,dcsr-ddr";
-                        dev-handle = <&ddr2>;
-                        reg = <0x13000 0x1000>;
-                };
-                dcsr-nal@18000 {
-                        compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
-                        reg = <0x18000 0x1000>;
-                };
-                dcsr-rcpm@22000 {
-                        compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
-                        reg = <0x22000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@40000 {
-                        compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu0>;
-                        reg = <0x40000 0x1000>;
-                };
-                dcsr-cpu-sb-proxy@41000 {
-                        compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                        cpu-handle = <&cpu1>;
-                        reg = <0x41000 0x1000>;
-                };
-        };
-        soc: soc@ffe000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                soc-sram-error {
-                        compatible = "fsl,soc-sram-error";
-                        interrupts = <16 2 1 29>;
-                };
-                corenet-law@0 {
-                        compatible = "fsl,corenet-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <32>;
-                };
-                ddr1: memory-controller@8000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
-                        reg = <0x8000 0x1000>;
-                        interrupts = <16 2 1 23>;
-                };
-                ddr2: memory-controller@9000 {
-                        compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
-                        reg = <0x9000 0x1000>;
-                        interrupts = <16 2 1 22>;
-                };
-                cpc: l3-cache-controller@10000 {
-                        compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
-                        reg = <0x10000 0x1000
-                               0x11000 0x1000>;
-                        interrupts = <16 2 1 27
-                                      16 2 1 26>;
-                };
-                corenet-cf@18000 {
-                        compatible = "fsl,corenet-cf";
-                        reg = <0x18000 0x1000>;
-                        interrupts = <16 2 1 31>;
-                        fsl,ccf-num-csdids = <32>;
-                        fsl,ccf-num-snoopids = <32>;
-                };
-                iommu@20000 {
-                        compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                        reg = <0x20000 0x4000>;
-                        interrupts = <
-                                24 2 0 0
-                                16 2 1 30>;
-                };
-                mpic: pic@40000 {
-                        clock-frequency = <0>;
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <4>;
-                        reg = <0x40000 0x40000>;
-                        compatible = "fsl,mpic", "chrp,open-pic";
-                        device_type = "open-pic";
-                };
-                msi0: msi@41600 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41600 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe0 0 0 0
-                                0xe1 0 0 0
-                                0xe2 0 0 0
-                                0xe3 0 0 0
-                                0xe4 0 0 0
-                                0xe5 0 0 0
-                                0xe6 0 0 0
-                                0xe7 0 0 0>;
-                };
-                msi1: msi@41800 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41800 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xe8 0 0 0
-                                0xe9 0 0 0
-                                0xea 0 0 0
-                                0xeb 0 0 0
-                                0xec 0 0 0
-                                0xed 0 0 0
-                                0xee 0 0 0
-                                0xef 0 0 0>;
-                };
-                msi2: msi@41a00 {
-                        compatible = "fsl,mpic-msi";
-                        reg = <0x41a00 0x200>;
-                        msi-available-ranges = <0 0x100>;
-                        interrupts = <
-                                0xf0 0 0 0
-                                0xf1 0 0 0
-                                0xf2 0 0 0
-                                0xf3 0 0 0
-                                0xf4 0 0 0
-                                0xf5 0 0 0
-                                0xf6 0 0 0
-                                0xf7 0 0 0>;
-                };
-                guts: global-utilities@e0000 {
-                        compatible = "fsl,qoriq-device-config-1.0";
-                        reg = <0xe0000 0xe00>;
-                        fsl,has-rstcr;
-                        #sleep-cells = <1>;
-                        fsl,liodn-bits = <12>;
-                };
-                pins: global-utilities@e0e00 {
-                        compatible = "fsl,qoriq-pin-control-1.0";
-                        reg = <0xe0e00 0x200>;
-                        #sleep-cells = <2>;
-                };
-                clockgen: global-utilities@e1000 {
-                        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
-                        reg = <0xe1000 0x1000>;
-                        clock-frequency = <0>;
-                };
-                rcpm: global-utilities@e2000 {
-                        compatible = "fsl,qoriq-rcpm-1.0";
-                        reg = <0xe2000 0x1000>;
-                        #sleep-cells = <1>;
-                };
-                sfp: sfp@e8000 {
-                        compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
-                        reg        = <0xe8000 0x1000>;
-                };
-                serdes: serdes@ea000 {
-                        compatible = "fsl,p5020-serdes";
-                        reg        = <0xea000 0x1000>;
-                };
-                dma0: dma@100300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
-                        reg = <0x100300 0x4>;
-                        ranges = <0x0 0x100100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <28 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <29 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <30 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <31 2 0 0>;
-                        };
-                };
-                dma1: dma@101300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
-                        reg = <0x101300 0x4>;
-                        ranges = <0x0 0x101100 0x200>;
-                        cell-index = <1>;
-                        dma-channel@0 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupts = <32 2 0 0>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupts = <33 2 0 0>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupts = <34 2 0 0>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,p5020-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupts = <35 2 0 0>;
-                        };
-                };
-                spi@110000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
-                        reg = <0x110000 0x1000>;
-                        interrupts = <53 0x2 0 0>;
-                        fsl,espi-num-chipselects = <4>;
-                };
-                sdhc: sdhc@114000 {
-                        compatible = "fsl,p5020-esdhc", "fsl,esdhc";
-                        reg = <0x114000 0x1000>;
-                        interrupts = <48 2 0 0>;
-                        sdhci,auto-cmd12;
-                        clock-frequency = <0>;
-                };
-                i2c@118000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118000 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@118100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x118100 0x100>;
-                        interrupts = <38 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <2>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119000 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                i2c@119100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <3>;
-                        compatible = "fsl-i2c";
-                        reg = <0x119100 0x100>;
-                        interrupts = <39 2 0 0>;
-                        dfsrr;
-                };
-                serial0: serial@11c500 {
-                        cell-index = <0>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial1: serial@11c600 {
-                        cell-index = <1>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11c600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <36 2 0 0>;
-                };
-                serial2: serial@11d500 {
-                        cell-index = <2>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d500 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                serial3: serial@11d600 {
-                        cell-index = <3>;
-                        device_type = "serial";
-                        compatible = "ns16550";
-                        reg = <0x11d600 0x100>;
-                        clock-frequency = <0>;
-                        interrupts = <37 2 0 0>;
-                };
-                gpio0: gpio@130000 {
-                        compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
-                        reg = <0x130000 0x1000>;
-                        interrupts = <55 2 0 0>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                };
-                usb0: usb@210000 {
-                        compatible = "fsl,p5020-usb2-mph",
-                                        "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-                        reg = <0x210000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <44 0x2 0 0>;
-                        phy_type = "utmi";
-                        port0;
-                };
-                usb1: usb@211000 {
-                        compatible = "fsl,p5020-usb2-dr",
-                                        "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-                        reg = <0x211000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <45 0x2 0 0>;
-                        dr_mode = "host";
-                        phy_type = "utmi";
-                };
-                sata@220000 {
-                        compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
-                        reg = <0x220000 0x1000>;
-                        interrupts = <68 0x2 0 0>;
-                };
-                sata@221000 {
-                        compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
-                        reg = <0x221000 0x1000>;
-                        interrupts = <69 0x2 0 0>;
-                };
-                crypto: crypto@300000 {
-                        compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg              = <0x300000 0x10000>;
-                        ranges           = <0 0x300000 0x10000>;
-                        interrupts       = <92 2 0 0>;
-                        sec_jr0: jr@1000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <88 2 0 0>;
-                        };
-                        sec_jr1: jr@2000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <89 2 0 0>;
-                        };
-                        sec_jr2: jr@3000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <90 2 0 0>;
-                        };
-                        sec_jr3: jr@4000 {
-                                compatible = "fsl,sec-v4.2-job-ring",
-                                             "fsl,sec-v4.0-job-ring";
-                                reg = <0x4000 0x1000>;
-                                interrupts = <91 2 0 0>;
-                        };
-                        rtic@6000 {
-                                compatible = "fsl,sec-v4.2-rtic",
-                                             "fsl,sec-v4.0-rtic";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x6000 0x100>;
-                                ranges = <0x0 0x6100 0xe00>;
-                                rtic_a: rtic-a@0 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x00 0x20 0x100 0x80>;
-                                };
-                                rtic_b: rtic-b@20 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x20 0x20 0x200 0x80>;
-                                };
-                                rtic_c: rtic-c@40 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x40 0x20 0x300 0x80>;
-                                };
-                                rtic_d: rtic-d@60 {
-                                        compatible = "fsl,sec-v4.2-rtic-memory",
-                                                     "fsl,sec-v4.0-rtic-memory";
-                                        reg = <0x60 0x20 0x500 0x80>;
-                                };
-                        };
-                };
-                sec_mon: sec_mon@314000 {
-                        compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
-                        reg = <0x314000 0x1000>;
-                        interrupts = <93 2 0 0>;
-                };
-        };
-/*
-        rapidio0: rapidio@ffe0c0000
-*/
-        localbus@ffe124000 {
-                compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
-                interrupts = <25 2 0 0>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-        };
-        pci0: pcie@ffe200000 {
-                compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi0>;
-                interrupts = <16 2 1 15>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 15>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 40 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                };
-        };
-        pci1: pcie@ffe201000 {
-                compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi1>;
-                interrupts = <16 2 1 14>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 14>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 41 1 0 0
-                                0000 0 0 2 &mpic 5 1 0 0
-                                0000 0 0 3 &mpic 6 1 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                };
-        };
-        pci2: pcie@ffe202000 {
-                compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 13>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 13>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 42 1 0 0
-                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 1 0 0
-                                >;
-                };
-        };
-        pci3: pcie@ffe203000 {
-                compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
-                device_type = "pci";
-                #size-cells = <2>;
-                #address-cells = <3>;
-                bus-range = <0x0 0xff>;
-                clock-frequency = <0x1fca055>;
-                fsl,msi = <&msi2>;
-                interrupts = <16 2 1 12>;
-                pcie@0 {
-                        reg = <0 0 0 0 0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        device_type = "pci";
-                        interrupts = <16 2 1 12>;
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 43 1 0 0
-                                0000 0 0 2 &mpic 0 1 0 0
-                                0000 0 0 3 &mpic 4 1 0 0
-                                0000 0 0 4 &mpic 8 1 0 0
-                                >;
-                };
-        };
-};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 0dc90f9bd814..b1e45a8537a5 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -222,7 +222,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <9 0x8>;
@@ -232,7 +232,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 94a332251710..77be77116c2e 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -316,7 +316,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <0x2a 0x2>;
@@ -326,7 +326,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <0x2a 0x2>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index ee5538feb455..56bebce87842 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -347,7 +347,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -357,7 +357,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index 38c35404bdc3..134a5ff917e1 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -199,7 +199,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -209,7 +209,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index eab680ce10da..2a555738517e 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -74,7 +74,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x20>;
                        clock-frequency = <97553800>; /* Hz */
                        current-speed = <115200>;
@@ -85,7 +85,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x20>;
                        clock-frequency = <97553800>; /* Hz */
                        current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
index 49efd44057d7..4f166b01c1b6 100644
--- a/arch/powerpc/boot/dts/stxssa8555.dts
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -210,7 +210,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -220,7 +220,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 0a4cedbdcb55..ed264d9ae356 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -250,7 +250,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -260,7 +260,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index f49d09181312..925242115814 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -224,7 +224,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -234,7 +234,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index d918752b1200..6e1ac50852a4 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -305,7 +305,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        current-speed = <115200>;
@@ -316,7 +316,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 988d887c97fc..161e75eac7f7 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -305,7 +305,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        current-speed = <115200>;
@@ -316,7 +316,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 81bad8cd3756..aa6ff0d3dd9a 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -224,7 +224,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
@@ -234,7 +234,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
index ac0a617b4299..cc00f4ddd9a7 100644
--- a/arch/powerpc/boot/dts/xcalibur1501.dts
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -531,7 +531,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -542,7 +542,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
index c41a80c55e47..8fd7b7031357 100644
--- a/arch/powerpc/boot/dts/xpedite5200.dts
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -333,7 +333,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        current-speed = <115200>;
@@ -344,7 +344,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
index c0efcbb45137..0baa8283d08c 100644
--- a/arch/powerpc/boot/dts/xpedite5200_xmon.dts
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -337,7 +337,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        current-speed = <9600>;
@@ -348,7 +348,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
index db7faf5ebb39..53c1c6a9752f 100644
--- a/arch/powerpc/boot/dts/xpedite5301.dts
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -441,7 +441,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -452,7 +452,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
index c364ca6ff7d0..215225983150 100644
--- a/arch/powerpc/boot/dts/xpedite5330.dts
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -477,7 +477,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -488,7 +488,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
index 7a8a4afd56cf..11dbda10d756 100644
--- a/arch/powerpc/boot/dts/xpedite5370.dts
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -439,7 +439,7 @@
                serial0: serial@4500 {
                        cell-index = <0>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4500 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
@@ -450,7 +450,7 @@
                serial1: serial@4600 {
                        cell-index = <1>;
                        device_type = "serial";
-                        compatible = "ns16550";
+                        compatible = "fsl,ns16550", "ns16550";
                        reg = <0x4600 0x100>;
                        clock-frequency = <0>;
                        interrupts = <42 2>;
diff --git a/arch/powerpc/boot/treeboot-currituck.c b/arch/powerpc/boot/treeboot-currituck.c
new file mode 100644
index 000000000000..925ae43b7467
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-currituck.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright © 2011 Tony Breeds IBM Corporation
+ *
+ * Based on earlier code:
+ *   Copyright (C) Paul Mackerras 1997.
+ *
+ *   Matt Porter <mporter@kernel.crashing.org>
+ *   Copyright 2002-2005 MontaVista Software Inc.
+ *
+ *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *   Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ *    Copyright 2007 David Gibson, IBM Corporation.
+ *    Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
+ *    Copyright © 2011 David Kleikamp IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "reg.h"
+#include "io.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+#include "libfdt.h"
+BSS_STACK(4096);
+#define MAX_RANKS       0x4
+#define DDR3_MR0CF      0x80010011U
+static unsigned long long ibm_currituck_memsize;
+static unsigned long long ibm_currituck_detect_memsize(void)
+{
+        u32 reg;
+        unsigned i;
+        unsigned long long memsize = 0;
+        for(i = 0; i < MAX_RANKS; i++){
+                reg = mfdcrx(DDR3_MR0CF + i);
+                if (!(reg & 1))
+                        continue;
+                reg &= 0x0000f000;
+                reg >>= 12;
+                memsize += (0x800000ULL << reg);
+        }
+        return memsize;
+}
+static void ibm_currituck_fixups(void)
+{
+        void *devp = finddevice("/");
+        u32 dma_ranges[7];
+        dt_fixup_memory(0x0ULL,  ibm_currituck_memsize);
+        while ((devp = find_node_by_devtype(devp, "pci"))) {
+                if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) {
+                        printf("%s: Failed to get dma-ranges\r\n", __func__);
+                        continue;
+                }
+                dma_ranges[5] = ibm_currituck_memsize >> 32;
+                dma_ranges[6] = ibm_currituck_memsize & 0xffffffffUL;
+                setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges));
+        }
+}
+#define SPRN_PIR        0x11E   /* Processor Indentification Register */
+void platform_init(void)
+{
+        unsigned long end_of_ram, avail_ram;
+        u32 pir_reg;
+        int node, size;
+        const u32 *timebase;
+        ibm_currituck_memsize = ibm_currituck_detect_memsize();
+        if (ibm_currituck_memsize >> 32)
+                end_of_ram = ~0UL;
+        else
+                end_of_ram = ibm_currituck_memsize;
+        avail_ram = end_of_ram - (unsigned long)_end;
+        simple_alloc_init(_end, avail_ram, 128, 64);
+        platform_ops.fixups = ibm_currituck_fixups;
+        platform_ops.exit = ibm44x_dbcr_reset;
+        pir_reg = mfspr(SPRN_PIR);
+        /* Make sure FDT blob is sane */
+        if (fdt_check_header(_dtb_start) != 0)
+                fatal("Invalid device tree blob\n");
+        node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+                                             "cpu", sizeof("cpu"));
+        if (!node)
+                fatal("Cannot find cpu node\n");
+        timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+        if (timebase && (size == 4))
+                timebase_period_ns = 1000000000 / *timebase;
+        fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index c74531af72c0..f090e6d2907e 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -163,7 +163,7 @@ coff)
    link_address='0x500000'
    pie=
    ;;
-miboot|uboot)
+miboot|uboot*)
    # miboot and U-boot want just the bare bits, not an ELF binary
    ext=bin
    objflags="-O binary"
@@ -244,6 +244,9 @@ gamecube|wii)
    link_address='0x600000'
    platformo="$object/$platform-head.o $object/$platform.o"
    ;;
+treeboot-currituck)
+    link_address='0x1000000'
+    ;;
 treeboot-iss4xx-mpic)
    platformo="$object/treeboot-iss4xx.o"
    ;;
@@ -257,6 +260,8 @@ vmz="$tmpdir/`basename \"$kernel\"`.$ext"
 if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
    ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
+    strip_size=$(stat -c %s $vmz.$$)
    if [ -n "$gzip" ]; then
        gzip -n -f -9 "$vmz.$$"
    fi
@@ -266,6 +271,24 @@ if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
    else
        vmz="$vmz.$$"
    fi
+else
+    # Calculate the vmlinux.strip size
+    ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
+    strip_size=$(stat -c %s $vmz.$$)
+    rm -f $vmz.$$
+fi
+# Round the size to next higher MB limit
+round_size=$(((strip_size + 0xfffff) & 0xfff00000))
+round_size=0x$(printf "%x" $round_size)
+link_addr=$(printf "%d" $link_address)
+if [ $link_addr -lt $strip_size ]; then
+    echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
+                "overlaps the address of the wrapper($link_address)"
+    echo "INFO: Fixing the link_address of wrapper to ($round_size)"
+    link_address=$round_size
 fi
 vmz="$vmz$gzip"
@@ -291,6 +314,26 @@ uboot)
    fi
    exit 0
    ;;
+uboot-obs600)
+    rm -f "$ofile"
+    # obs600 wants a multi image with an initrd, so we need to put a fake
+    # one in even when building a "normal" image.
+    if [ -n "$initrd" ]; then
+        real_rd="$initrd"
+    else
+        real_rd=`mktemp`
+        echo "\0" >>"$real_rd"
+    fi
+    ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
+        $uboot_version -d "$vmz":"$real_rd":"$dtb" "$ofile"
+    if [ -z "$initrd" ]; then
+        rm -f "$real_rd"
+    fi
+    if [ -z "$cacheit" ]; then
+        rm -f "$vmz"
+    fi
+    exit 0
+    ;;
 esac
 addsec() {
diff --git a/arch/powerpc/configs/40x/klondike_defconfig b/arch/powerpc/configs/40x/klondike_defconfig
new file mode 100644
index 000000000000..c0d228dc73dc
--- /dev/null
+++ b/arch/powerpc/configs/40x/klondike_defconfig
@@ -0,0 +1,55 @@
+CONFIG_40x=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_WALNUT is not set
+CONFIG_APM8018X=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_MIGRATION is not set
+# CONFIG_SUSPEND is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=35000
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_SAS_ATTRS=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_CRAMFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_AVERAGE=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_FTRACE is not set
diff --git a/arch/powerpc/configs/40x/obs600_defconfig b/arch/powerpc/configs/40x/obs600_defconfig
new file mode 100644
index 000000000000..91c110dad2d6
--- /dev/null
+++ b/arch/powerpc/configs/40x/obs600_defconfig
@@ -0,0 +1,83 @@
+CONFIG_40x=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_WALNUT is not set
+CONFIG_OBS600=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_MATH_EMULATION=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_NDFC=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=35000
+CONFIG_NETDEVICES=y
+CONFIG_IBM_EMAC=y
+CONFIG_IBM_EMAC_RXB=256
+CONFIG_IBM_EMAC_TXB=256
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IBM_IIC=y
+CONFIG_SENSORS_LM75=y
+CONFIG_THERMAL=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_EXT2_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/44x/currituck_defconfig b/arch/powerpc/configs/44x/currituck_defconfig
new file mode 100644
index 000000000000..4192322f8a7f
--- /dev/null
+++ b/arch/powerpc/configs/44x/currituck_defconfig
@@ -0,0 +1,110 @@
+CONFIG_44x=y
+CONFIG_SMP=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PPC_47x=y
+# CONFIG_EBONY is not set
+CONFIG_CURRITUCK=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_100=y
+CONFIG_MATH_EMULATION=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_SIL24=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_E1000E=y
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NLS_DEFAULT="n"
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_XMON=y
+CONFIG_XMON_DEFAULT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0x10000000
+CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x200
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig
index a6eb6ad05b2d..ca00cf750d3e 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -25,7 +25,8 @@ CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="root=/dev/issblk0"
 # CONFIG_PCI is not set
 CONFIG_ADVANCED_OPTIONS=y
-CONFIG_RELOCATABLE=y
+CONFIG_NONSTATIC_KERNEL=y
+CONFIG_DYNAMIC_MEMSTART=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig
new file mode 100644
index 000000000000..acf7fb280464
--- /dev/null
+++ b/arch/powerpc/configs/chroma_defconfig
@@ -0,0 +1,307 @@
+CONFIG_PPC64=y
+CONFIG_PPC_BOOK3E_64=y
+# CONFIG_VIRT_CPU_ACCOUNTING is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=256
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_NAMESPACES=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_INITRAMFS_COMPRESSION_GZIP=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_COUNTERS=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_SCOM_DEBUGFS=y
+CONFIG_PPC_A2_DD2=y
+CONFIG_KVM_GUEST=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_NUMA=y
+# CONFIG_MIGRATION is not set
+CONFIG_PPC_64K_PAGES=y
+CONFIG_SCHED_SMT=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_SECCOMP is not set
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEASPM is not set
+CONFIG_PCI_MSI=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NET_TCPPROBE=y
+# CONFIG_WIRELESS is not set
+CONFIG_NET_9P=y
+CONFIG_NET_9P_DEBUG=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_MISC_DEVICES=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_MV=y
+CONFIG_SATA_SIL=y
+CONFIG_PATA_CMD64X=y
+CONFIG_PATA_MARVELL=y
+CONFIG_PATA_SIL680=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_LINEAR=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_E1000E=y
+CONFIG_TIGON3=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=1024
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1511=y
+CONFIG_RTC_DRV_DS1553=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=y
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_LIBCRC32C=m
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_PPC_EMULATED_STATS=y
+CONFIG_XMON=y
+CONFIG_XMON_DEFAULT=y
+CONFIG_VIRQ_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_VIRTUALIZATION=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index f087de6ec03f..f8aef205d222 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -37,6 +37,8 @@ CONFIG_FSL_LBC=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 # CONFIG_PCIEASPM is not set
+CONFIG_RAPIDIO=y
+CONFIG_FSL_RIO=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -94,17 +96,17 @@ CONFIG_SATA_SIL24=y
 CONFIG_SATA_SIL=y
 CONFIG_PATA_SIL680=y
 CONFIG_NETDEVICES=y
-CONFIG_VITESSE_PHY=y
+CONFIG_FSL_PQ_MDIO=y
-CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_E1000=y
 CONFIG_E1000E=y
-CONFIG_FSL_PQ_MDIO=y
+CONFIG_VITESSE_PHY=y
+CONFIG_FIXED_PHY=y
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_PPC_EPAPR_HV_BYTECHAN=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_EXTENDED=y
@@ -155,6 +157,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 782822c32d15..7ed8d4cf2719 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,8 @@ CONFIG_P5020_DS=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BINFMT_MISC=m
+CONFIG_RAPIDIO=y
+CONFIG_FSL_RIO=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -57,7 +59,6 @@ CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -81,6 +82,7 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index a1e5a178a4ac..f37a2ab48881 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,5 +1,4 @@
 CONFIG_PPC_85xx=y
-CONFIG_PHYS_64BIT=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -93,15 +92,14 @@ CONFIG_SATA_FSL=y
 CONFIG_PATA_ALI=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
+CONFIG_FS_ENET=y
+CONFIG_UCC_GETH=y
+CONFIG_GIANFAR=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_CICADA_PHY=y
 CONFIG_VITESSE_PHY=y
 CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_FS_ENET=y
-CONFIG_GIANFAR=y
-CONFIG_UCC_GETH=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -120,6 +118,9 @@ CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_SPI=y
+CONFIG_SPI_FSL_ESPI=y
 CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
@@ -163,6 +164,10 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
 CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
 CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_RTC_CLASS=y
@@ -182,6 +187,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
@@ -213,4 +219,5 @@ CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
 CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index dd1e41386c4c..abdcd317cda7 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -1,5 +1,4 @@
 CONFIG_PPC_85xx=y
-CONFIG_PHYS_64BIT=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_EXPERIMENTAL=y
@@ -26,6 +25,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
@@ -94,15 +94,14 @@ CONFIG_SATA_FSL=y
 CONFIG_PATA_ALI=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
+CONFIG_FS_ENET=y
+CONFIG_UCC_GETH=y
+CONFIG_GIANFAR=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_CICADA_PHY=y
 CONFIG_VITESSE_PHY=y
 CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_FS_ENET=y
-CONFIG_GIANFAR=y
-CONFIG_UCC_GETH=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -121,6 +120,9 @@ CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_SPI=y
+CONFIG_SPI_FSL_ESPI=y
 CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
@@ -164,6 +166,10 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
 CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
 CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_RTC_CLASS=y
@@ -183,6 +189,7 @@ CONFIG_VFAT_FS=y
 CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
@@ -214,4 +221,5 @@ CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
 CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 535711fcb13c..2156e077859b 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -390,6 +390,11 @@ CONFIG_HUGETLBFS=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index 185c292b0f1c..ded867871e97 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -6,10 +6,10 @@ CONFIG_NR_CPUS=2
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_NAMESPACES=y
+CONFIG_SPARSE_IRQ=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_EMBEDDED=y
 # CONFIG_PERF_EVENTS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
@@ -17,6 +17,7 @@ CONFIG_PROFILING=y
 CONFIG_OPROFILE=m
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+# CONFIG_PPC_POWERNV is not set
 # CONFIG_PPC_PSERIES is not set
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_PS3=y
@@ -27,14 +28,14 @@ CONFIG_PS3_VRAM=m
 CONFIG_PS3_LPM=m
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=y
 CONFIG_KEXEC=y
-CONFIG_SPARSE_IRQ=y
 # CONFIG_SPARSEMEM_VMEMMAP is not set
 CONFIG_SCHED_SMT=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE=""
-CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
 # CONFIG_SECCOMP is not set
 # CONFIG_PCI is not set
@@ -81,20 +82,23 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_DM=m
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_GELIC_NET=y
 CONFIG_GELIC_WIRELESS=y
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_XILINX is not set
 CONFIG_USB_USBNET=m
 # CONFIG_USB_NET_CDCETHER is not set
+# CONFIG_USB_NET_CDC_NCM is not set
 # CONFIG_USB_NET_NET1080 is not set
 # CONFIG_USB_NET_CDC_SUBSET is not set
 # CONFIG_USB_NET_ZAURUS is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPPOE=m
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_JOYDEV=m
@@ -135,22 +139,21 @@ CONFIG_USB=m
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
 CONFIG_USB_MON=m
 CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_EHCI_HCD_PPC_OF is not set
 CONFIG_USB_OHCI_HCD=m
 CONFIG_USB_STORAGE=m
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PS3=m
+CONFIG_RTC_DRV_PS3=y
+# CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=m
 CONFIG_EXT3_FS=m
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT4_FS=y
-CONFIG_INOTIFY=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
@@ -167,19 +170,17 @@ CONFIG_CIFS=m
 CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_CRC_CCITT=m
 CONFIG_CRC_T10DIF=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_PROVE_LOCKING=y
 CONFIG_DEBUG_LOCKDEP=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_WRITECOUNT=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_DEBUG_LIST=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_STACKOVERFLOW=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index a72f2415a647..30e7d0d20e49 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -304,6 +304,11 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d51df17c7e6f..7e313f1ed183 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -34,3 +34,5 @@ header-y += termios.h
 header-y += types.h
 header-y += ucontext.h
 header-y += unistd.h
+generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e30442c539ce..ad55a1ccb9fb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -201,6 +201,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0400000000000000)
 #define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0800000000000000)
 #define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x1000000000000000)
+#define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x2000000000000000)
 #ifndef __ASSEMBLY__
@@ -425,7 +426,7 @@ extern const char *powerpc_base_platform;
            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE)
+            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -437,7 +438,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 6ec1c380a4d6..487d46ff68a1 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -110,11 +110,11 @@ static inline u64 cputime64_to_jiffies64(const cputime_t ct)
 /*
 * Convert cputime <-> microseconds
 */
-extern u64 __cputime_msec_factor;
+extern u64 __cputime_usec_factor;
 static inline unsigned long cputime_to_usecs(const cputime_t ct)
 {
-        return mulhdu((__force u64) ct, __cputime_msec_factor) * USEC_PER_MSEC;
+        return mulhdu((__force u64) ct, __cputime_usec_factor);
 }
 static inline cputime_t usecs_to_cputime(const unsigned long us)
@@ -127,7 +127,7 @@ static inline cputime_t usecs_to_cputime(const unsigned long us)
        sec = us / 1000000;
        if (ct) {
                ct *= tb_ticks_per_sec;
-                do_div(ct, 1000);
+                do_div(ct, 1000000);
        }
        if (sec)
                ct += (cputime_t) sec * tb_ticks_per_sec;
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 000000000000..b955012939a2
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#define FSL_IFC_BANK_COUNT 4
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA                         0xFFFF0000
+#define CSPR_BA_SHIFT                   16
+#define CSPR_PORT_SIZE                  0x00000180
+#define CSPR_PORT_SIZE_SHIFT            7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8                0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16               0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32               0x00000180
+/* Write Protect */
+#define CSPR_WP                         0x00000040
+#define CSPR_WP_SHIFT                   6
+/* Machine Select */
+#define CSPR_MSEL                       0x00000006
+#define CSPR_MSEL_SHIFT                 1
+/* NOR */
+#define CSPR_MSEL_NOR                   0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND                  0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM                  0x00000004
+/* Bank Valid */
+#define CSPR_V                          0x00000001
+#define CSPR_V_SHIFT                    0
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK                  0xFFFF0000
+#define IFC_AMASK_SHIFT                 16
+#define IFC_AMASK(n)                    (IFC_AMASK_MASK << \
+                                        (__ilog2(n) - IFC_AMASK_SHIFT))
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN            0x80000000
+#define CSOR_NAND_ECC_MODE_MASK         0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4            0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8            0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN            0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK              0x01800000
+#define CSOR_NAND_RAL_SHIFT             20
+#define CSOR_NAND_RAL_1                 0x00000000
+#define CSOR_NAND_RAL_2                 0x00800000
+#define CSOR_NAND_RAL_3                 0x01000000
+#define CSOR_NAND_RAL_4                 0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK              0x00180000
+#define CSOR_NAND_PGS_SHIFT             16
+#define CSOR_NAND_PGS_512               0x00000000
+#define CSOR_NAND_PGS_2K                0x00080000
+#define CSOR_NAND_PGS_4K                0x00100000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK             0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT            13
+#define CSOR_NAND_SPRZ_16               0x00000000
+#define CSOR_NAND_SPRZ_64               0x00002000
+#define CSOR_NAND_SPRZ_128              0x00004000
+#define CSOR_NAND_SPRZ_210              0x00006000
+#define CSOR_NAND_SPRZ_218              0x00008000
+#define CSOR_NAND_SPRZ_224              0x0000A000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK               0x00000700
+#define CSOR_NAND_PB_SHIFT              8
+#define CSOR_NAND_PB(n)         ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK             0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT            2
+#define CSOR_NAND_TRHZ_20               0x00000000
+#define CSOR_NAND_TRHZ_40               0x00000004
+#define CSOR_NAND_TRHZ_60               0x00000008
+#define CSOR_NAND_TRHZ_80               0x0000000C
+#define CSOR_NAND_TRHZ_100              0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD                 0x00000001
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN       0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN                0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN         0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK               0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT        13
+#define CSOR_NOR_ADM_SHIFT(n)   ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR     0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR       0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK              0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT             2
+#define CSOR_NOR_TRHZ_20                0x00000000
+#define CSOR_NOR_TRHZ_40                0x00000004
+#define CSOR_NOR_TRHZ_60                0x00000008
+#define CSOR_NOR_TRHZ_80                0x0000000C
+#define CSOR_NOR_TRHZ_100               0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD                  0x00000001
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL         0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC           0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN           0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN                0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK             0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT            24
+#define CSOR_GPCM_GPTO(n)       ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT             0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT             0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK              0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT       13
+#define CSOR_GPCM_ADM_SHIFT(n)  ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK          0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT         7
+#define CSOR_GPCM_GAPERRD(n)    (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK             0x0000001C
+#define CSOR_GPCM_TRHZ_20               0x00000000
+#define CSOR_GPCM_TRHZ_40               0x00000004
+#define CSOR_GPCM_TRHZ_60               0x00000008
+#define CSOR_GPCM_TRHZ_80               0x0000000C
+#define CSOR_GPCM_TRHZ_100              0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD                 0x00000001
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0           0x80000000
+#define IFC_RB_STAT_READY_CS1           0x40000000
+#define IFC_RB_STAT_READY_CS2           0x20000000
+#define IFC_RB_STAT_READY_CS3           0x10000000
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK                    0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL            0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME          0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT    11
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER          0x80000000
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN          0x80000000
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN   0x80000000
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ       0x80000000
+#define IFC_CM_ERATTR0_ERAID            0x0FF00000
+#define IFC_CM_ERATTR0_ERAID_SHIFT      20
+#define IFC_CM_ERATTR0_ESRCID           0x0000FF00
+#define IFC_CM_ERATTR0_ESRCID_SHIFT     8
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK                    0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK            0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT           24
+#define IFC_CCR_CLK_DIV(n)              ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK            0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT           16
+#define IFC_CCR_CLK_DLY(n)              ((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN              0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL          0x00000800
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE         0x80000000
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT             0x80000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0    0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1    0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK    0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT   12
+#define IFC_NAND_NCFGR_NUM_LOOP(n)      ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK    0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT   0
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0              0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT        24
+#define IFC_NAND_FCR0_CMD1              0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT        16
+#define IFC_NAND_FCR0_CMD2              0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT        8
+#define IFC_NAND_FCR0_CMD3              0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT        0
+#define IFC_NAND_FCR1_CMD4              0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT        24
+#define IFC_NAND_FCR1_CMD5              0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT        16
+#define IFC_NAND_FCR1_CMD6              0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT        8
+#define IFC_NAND_FCR1_CMD7              0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT        0
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS                 0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK            0x00000FFF
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC                     0x000001FF
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0               0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT         26
+#define IFC_NAND_FIR0_OP1               0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT         20
+#define IFC_NAND_FIR0_OP2               0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT         14
+#define IFC_NAND_FIR0_OP3               0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT         8
+#define IFC_NAND_FIR0_OP4               0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT         2
+#define IFC_NAND_FIR1_OP5               0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT         26
+#define IFC_NAND_FIR1_OP6               0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT         20
+#define IFC_NAND_FIR1_OP7               0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT         14
+#define IFC_NAND_FIR1_OP8               0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT         8
+#define IFC_NAND_FIR1_OP9               0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT         2
+#define IFC_NAND_FIR2_OP10              0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT        26
+#define IFC_NAND_FIR2_OP11              0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT        20
+#define IFC_NAND_FIR2_OP12              0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT        14
+#define IFC_NAND_FIR2_OP13              0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT        8
+#define IFC_NAND_FIR2_OP14              0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT        2
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+        IFC_FIR_OP_NOP,
+        IFC_FIR_OP_CA0,
+        IFC_FIR_OP_CA1,
+        IFC_FIR_OP_CA2,
+        IFC_FIR_OP_CA3,
+        IFC_FIR_OP_RA0,
+        IFC_FIR_OP_RA1,
+        IFC_FIR_OP_RA2,
+        IFC_FIR_OP_RA3,
+        IFC_FIR_OP_CMD0,
+        IFC_FIR_OP_CMD1,
+        IFC_FIR_OP_CMD2,
+        IFC_FIR_OP_CMD3,
+        IFC_FIR_OP_CMD4,
+        IFC_FIR_OP_CMD5,
+        IFC_FIR_OP_CMD6,
+        IFC_FIR_OP_CMD7,
+        IFC_FIR_OP_CW0,
+        IFC_FIR_OP_CW1,
+        IFC_FIR_OP_CW2,
+        IFC_FIR_OP_CW3,
+        IFC_FIR_OP_CW4,
+        IFC_FIR_OP_CW5,
+        IFC_FIR_OP_CW6,
+        IFC_FIR_OP_CW7,
+        IFC_FIR_OP_WBCD,
+        IFC_FIR_OP_RBCD,
+        IFC_FIR_OP_BTRD,
+        IFC_FIR_OP_RDSTAT,
+        IFC_FIR_OP_NWAIT,
+        IFC_FIR_OP_WFR,
+        IFC_FIR_OP_SBRD,
+        IFC_FIR_OP_UA,
+        IFC_FIR_OP_RB,
+};
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL                   0x0C000000
+#define IFC_NAND_CSEL_SHIFT             26
+#define IFC_NAND_CSEL_CS0               0x00000000
+#define IFC_NAND_CSEL_CS1               0x04000000
+#define IFC_NAND_CSEL_CS2               0x08000000
+#define IFC_NAND_CSEL_CS3               0x0C000000
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT      0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS      0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM      0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB      0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD       0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD  0x00000800
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC         0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER       0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER        0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER       0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN      0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN     0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK          0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n)      (0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n)      (0xFF << (24 - (n)*8))
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN        0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN   0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN      0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN       0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN      0x02000000
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN            0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN       0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN          0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN           0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN          0x02000000
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK           0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0       0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1       0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2       0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3       0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ   0x00080000
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0               0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1               0x00FF0000
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT  24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT  16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK   0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT  8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK   0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT  0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT  24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT  16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK   0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT  8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK   0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT  0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT  24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT  16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK  0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK  0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK  0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK  0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK  0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK  0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK        0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT       25
+#define IFC_NAND_NCR_FTOCNT(n)  ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD   0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD  0x20000000
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0             0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1             0x00FF0000
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR      0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER         0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER        0x01000000
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR      0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN         0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN        0x01000000
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR    0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN       0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN      0x01000000
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID         0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID           0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0        0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1        0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2        0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3        0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ     0x00000001
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP        0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER        0x00000F00
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK                  0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK        0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT       24
+#define IFC_NORCR_NUM_PHASE(n)  ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK           0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT          16
+#define IFC_NORCR_STOCNT(n)     ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER        0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER         0x01000000
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN       0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN        0x01000000
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN        0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN         0x01000000
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID        0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID          0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0       0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1       0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2       0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3       0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ    0x00000001
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT              0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE              0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE        0x00000001
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY               0x80000000  /* GPCM is busy */
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+        __be32 ncfgr;
+        u32 res1[0x4];
+        __be32 nand_fcr0;
+        __be32 nand_fcr1;
+        u32 res2[0x8];
+        __be32 row0;
+        u32 res3;
+        __be32 col0;
+        u32 res4;
+        __be32 row1;
+        u32 res5;
+        __be32 col1;
+        u32 res6;
+        __be32 row2;
+        u32 res7;
+        __be32 col2;
+        u32 res8;
+        __be32 row3;
+        u32 res9;
+        __be32 col3;
+        u32 res10[0x24];
+        __be32 nand_fbcr;
+        u32 res11;
+        __be32 nand_fir0;
+        __be32 nand_fir1;
+        __be32 nand_fir2;
+        u32 res12[0x10];
+        __be32 nand_csel;
+        u32 res13;
+        __be32 nandseq_strt;
+        u32 res14;
+        __be32 nand_evter_stat;
+        u32 res15;
+        __be32 pgrdcmpl_evt_stat;
+        u32 res16[0x2];
+        __be32 nand_evter_en;
+        u32 res17[0x2];
+        __be32 nand_evter_intr_en;
+        u32 res18[0x2];
+        __be32 nand_erattr0;
+        __be32 nand_erattr1;
+        u32 res19[0x10];
+        __be32 nand_fsr;
+        u32 res20;
+        __be32 nand_eccstat[4];
+        u32 res21[0x20];
+        __be32 nanndcr;
+        u32 res22[0x2];
+        __be32 nand_autoboot_trgr;
+        u32 res23;
+        __be32 nand_mdr;
+        u32 res24[0x5C];
+};
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+        __be32 nor_evter_stat;
+        u32 res1[0x2];
+        __be32 nor_evter_en;
+        u32 res2[0x2];
+        __be32 nor_evter_intr_en;
+        u32 res3[0x2];
+        __be32 nor_erattr0;
+        __be32 nor_erattr1;
+        __be32 nor_erattr2;
+        u32 res4[0x4];
+        __be32 norcr;
+        u32 res5[0xEF];
+};
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+        __be32 gpcm_evter_stat;
+        u32 res1[0x2];
+        __be32 gpcm_evter_en;
+        u32 res2[0x2];
+        __be32 gpcm_evter_intr_en;
+        u32 res3[0x2];
+        __be32 gpcm_erattr0;
+        __be32 gpcm_erattr1;
+        __be32 gpcm_erattr2;
+        __be32 gpcm_stat;
+        u32 res4[0x1F3];
+};
+/*
+ * IFC Controller Registers
+ */
+struct fsl_ifc_regs {
+        __be32 ifc_rev;
+        u32 res1[0x3];
+        struct {
+                __be32 cspr;
+                u32 res2[0x2];
+        } cspr_cs[FSL_IFC_BANK_COUNT];
+        u32 res3[0x18];
+        struct {
+                __be32 amask;
+                u32 res4[0x2];
+        } amask_cs[FSL_IFC_BANK_COUNT];
+        u32 res5[0x18];
+        struct {
+                __be32 csor;
+                u32 res6[0x2];
+        } csor_cs[FSL_IFC_BANK_COUNT];
+        u32 res7[0x18];
+        struct {
+                __be32 ftim[4];
+                u32 res8[0x8];
+        } ftim_cs[FSL_IFC_BANK_COUNT];
+        u32 res9[0x60];
+        __be32 rb_stat;
+        u32 res10[0x2];
+        __be32 ifc_gcr;
+        u32 res11[0x2];
+        __be32 cm_evter_stat;
+        u32 res12[0x2];
+        __be32 cm_evter_en;
+        u32 res13[0x2];
+        __be32 cm_evter_intr_en;
+        u32 res14[0x2];
+        __be32 cm_erattr0;
+        __be32 cm_erattr1;
+        u32 res15[0x2];
+        __be32 ifc_ccr;
+        __be32 ifc_csr;
+        u32 res16[0x2EB];
+        struct fsl_ifc_nand ifc_nand;
+        struct fsl_ifc_nor ifc_nor;
+        struct fsl_ifc_gpcm ifc_gpcm;
+};
+extern unsigned int convert_ifc_address(phys_addr_t addr_base);
+extern int fsl_ifc_find(phys_addr_t addr_base);
+/* overview of the fsl ifc controller */
+struct fsl_ifc_ctrl {
+        /* device info */
+        struct device                   *dev;
+        struct fsl_ifc_regs __iomem     *regs;
+        int                             irq;
+        int                             nand_irq;
+        spinlock_t                      lock;
+        void                            *nand;
+        u32 nand_stat;
+        wait_queue_head_t nand_wait;
+};
+extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8a0b5ece8f76..420b45368fcf 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -238,8 +238,6 @@ struct fsl_lbc_regs {
 #define FPAR_LP_CI_SHIFT      0
        __be32 fbcr;            /**< Flash Byte Count Register */
 #define FBCR_BC      0x00000FFF
-        u8 res11[0x8];
-        u8 res8[0xF00];
 };
 /*
@@ -294,6 +292,11 @@ struct fsl_lbc_ctrl {
        /* status read from LTESR by irq handler */
        unsigned int                    irq_status;
+#ifdef CONFIG_SUSPEND
+        /* save regs when system go to deep-sleep */
+        struct fsl_lbc_regs             *saved_regs;
+#endif
 };
 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 86004930a78e..dfdb95bc59a5 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
 #include <asm/page.h>
 extern struct kmem_cache *hugepte_cache;
-extern void __init reserve_hugetlb_gpages(void);
 static inline pte_t *hugepd_page(hugepd_t hpd)
 {
@@ -22,14 +21,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
                                    unsigned pdshift)
 {
        /*
-         * On 32-bit, we have multiple higher-level table entries that point to
+         * On FSL BookE, we have multiple higher-level table entries that
-         * the same hugepte.  Just use the first one since they're all
+         * point to the same hugepte.  Just use the first one since they're all
         * identical.  So for that case, idx=0.
         */
        unsigned long idx = 0;
        pte_t *dir = hugepd_page(*hpdp);
-#ifdef CONFIG_PPC64
+#ifndef CONFIG_PPC_FSL_BOOK3E
        idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
 #endif
@@ -53,7 +52,8 @@ static inline int is_hugepage_only_range(struct mm_struct *mm,
 }
 #endif
-void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte);
+void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
+                            pte_t pte);
 void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
@@ -124,7 +124,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
                                             unsigned long addr, pte_t *ptep,
                                             pte_t pte, int dirty)
 {
+#ifdef HUGETLB_NEED_PRELOAD
+        /*
+         * The "return 1" forces a call of update_mmu_cache, which will write a
+         * TLB entry.  Without this, platforms that don't do a write of the TLB
+         * entry in the TLB miss handler asm will fault ad infinitum.
+         */
+        ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+        return 1;
+#else
        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+#endif
 }
 static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -142,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
 }
 #else /* ! CONFIG_HUGETLB_PAGE */
-static inline void reserve_hugetlb_gpages(void)
-{
-        pr_err("Cannot reserve gpages without hugetlb enabled\n");
-}
 static inline void flush_hugetlb_page(struct vm_area_struct *vma,
                                      unsigned long vmaddr)
 {
 }
+#endif /* CONFIG_HUGETLB_PAGE */
+/*
+ * FSL Book3E platforms require special gpage handling - the gpages
+ * are reserved early in the boot process by memblock instead of via
+ * the .dts as on IBM platforms.
+ */
+#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
+extern void __init reserve_hugetlb_gpages(void);
+#else
+static inline void reserve_hugetlb_gpages(void)
+{
+}
 #endif
 #endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
index bffd062adf79..c9776202d7ec 100644
--- a/arch/powerpc/include/asm/kdump.h
+++ b/arch/powerpc/include/asm/kdump.h
@@ -32,11 +32,11 @@
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_RELOCATABLE)
+#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_NONSTATIC_KERNEL)
 extern void reserve_kdump_trampoline(void);
 extern void setup_kdump_trampoline(void);
 #else
-/* !CRASH_DUMP || RELOCATABLE */
+/* !CRASH_DUMP || !NONSTATIC_KERNEL */
 static inline void reserve_kdump_trampoline(void) { ; }
 static inline void setup_kdump_trampoline(void) { ; }
 #endif
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index f921eb121d39..16d7e33d35e9 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -49,7 +49,6 @@
 #define KEXEC_STATE_REAL_MODE 2
 #ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
 #include <asm/reg.h>
 typedef void (*crash_shutdown_t)(void);
@@ -73,11 +72,6 @@ extern void kexec_smp_wait(void);	/* get and clear naca physid, wait for
                                          master to copy new code to 0 */
 extern int crashing_cpu;
 extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
-extern cpumask_t cpus_in_sr;
-static inline int kexec_sr_activated(int cpu)
-{
-        return cpumask_test_cpu(cpu, &cpus_in_sr);
-}
 struct kimage;
 struct pt_regs;
@@ -94,7 +88,6 @@ extern void reserve_crashkernel(void);
 extern void machine_kexec_mask_interrupts(void);
 #else /* !CONFIG_KEXEC */
-static inline int kexec_sr_activated(int cpu) { return 0; }
 static inline void crash_kexec_secondary(struct pt_regs *regs) { }
 static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
index f77c708c67a0..233f9ecae761 100644
--- a/arch/powerpc/include/asm/lv1call.h
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -231,7 +231,7 @@ LV1_CALL(allocate_memory,                               4, 2,   0 )
 LV1_CALL(write_htab_entry,                              4, 0,   1 )
 LV1_CALL(construct_virtual_address_space,               3, 2,   2 )
 LV1_CALL(invalidate_htab_entries,                       5, 0,   3 )
-LV1_CALL(get_virtual_address_space_id_of_ppe,           1, 1,   4 )
+LV1_CALL(get_virtual_address_space_id_of_ppe,           0, 1,   4 )
 LV1_CALL(query_logical_partition_address_region_info,   1, 5,   6 )
 LV1_CALL(select_virtual_address_space,                  1, 0,   7 )
 LV1_CALL(pause,                                         1, 0,   9 )
@@ -264,7 +264,7 @@ LV1_CALL(configure_execution_time_variable,             1, 0,  77 )
 LV1_CALL(get_spe_irq_outlet,                            2, 1,  78 )
 LV1_CALL(set_spe_privilege_state_area_1_register,       3, 0,  79 )
 LV1_CALL(create_repository_node,                        6, 0,  90 )
-LV1_CALL(get_repository_node_value,                     5, 2,  91 )
+LV1_CALL(read_repository_node,                          5, 2,  91 )
 LV1_CALL(modify_repository_node_value,                  6, 0,  92 )
 LV1_CALL(remove_repository_node,                        4, 0,  93 )
 LV1_CALL(read_htab_entries,                             2, 5,  95 )
@@ -276,7 +276,7 @@ LV1_CALL(construct_io_irq_outlet,                       1, 1, 120 )
 LV1_CALL(destruct_io_irq_outlet,                        1, 0, 121 )
 LV1_CALL(map_htab,                                      1, 1, 122 )
 LV1_CALL(unmap_htab,                                    1, 0, 123 )
-LV1_CALL(get_version_info,                              0, 1, 127 )
+LV1_CALL(get_version_info,                              0, 2, 127 )
 LV1_CALL(insert_htab_entry,                             6, 3, 158 )
 LV1_CALL(read_virtual_uart,                             3, 1, 162 )
 LV1_CALL(write_virtual_uart,                            3, 1, 163 )
@@ -294,9 +294,9 @@ LV1_CALL(unmap_device_dma_region,                       4, 0, 177 )
 LV1_CALL(net_add_multicast_address,                     4, 0, 185 )
 LV1_CALL(net_remove_multicast_address,                  4, 0, 186 )
 LV1_CALL(net_start_tx_dma,                              4, 0, 187 )
-LV1_CALL(net_stop_tx_dma,                               3, 0, 188 )
+LV1_CALL(net_stop_tx_dma,                               2, 0, 188 )
 LV1_CALL(net_start_rx_dma,                              4, 0, 189 )
-LV1_CALL(net_stop_rx_dma,                               3, 0, 190 )
+LV1_CALL(net_stop_rx_dma,                               2, 0, 190 )
 LV1_CALL(net_set_interrupt_status_indicator,            4, 0, 191 )
 LV1_CALL(net_set_interrupt_mask,                        4, 0, 193 )
 LV1_CALL(net_control,                                   6, 2, 194 )
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index b540d6fcedd6..bf37931d1ad6 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -213,6 +213,9 @@ struct machdep_calls {
         * allow assignment/enabling of the device. */
        int  (*pcibios_enable_device_hook)(struct pci_dev *);
+        /* Called after scan and before resource survey */
+        void (*pcibios_fixup_phb)(struct pci_controller *hose);
        /* Called to shutdown machine specific hardware not already controlled
         * by other drivers.
         */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 0260ea5ec3c2..f5f89cafebd0 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -214,6 +214,10 @@ typedef struct {
        unsigned int    id;
        unsigned int    active;
        unsigned long   vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+        struct spinlock *cop_lockp;     /* guard cop related stuff */
+        unsigned long acop;             /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
 #ifdef CONFIG_PPC_MM_SLICES
        u64 low_slices_psize;   /* SLB page size encodings */
        u64 high_slices_psize;  /* 4 bits per slice for now */
@@ -254,6 +258,13 @@ extern int mmu_vmemmap_psize;
 #ifdef CONFIG_PPC64
 extern unsigned long linear_map_top;
+/*
+ * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
+ * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
+ * return 1, indicating that the tlb requires preloading.
+ */
+#define HUGETLB_NEED_PRELOAD
 #endif
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index db645ec842bd..412ba493cb98 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -312,10 +312,9 @@ extern void slb_set_size(u16 size);
 * (i.e. everything above 0xC000000000000000), except the very top
 * segment, which simplifies several things.
 *
- *      - We allow for 15 significant bits of ESID and 20 bits of
+ *      - We allow for 16 significant bits of ESID and 19 bits of
- * context for user addresses.  i.e. 8T (43 bits) of address space for
+ * context for user addresses.  i.e. 16T (44 bits) of address space for
- * up to 1M contexts (although the page table structure and context
+ * up to half a million contexts.
- * allocation will need changes to take advantage of this).
 *
 *      - The scramble function gives robust scattering in the hash
 * table (at least based on some initial results).  The previous
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e6fae49e0b74..67b4d9837236 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -251,6 +251,9 @@ struct mpic_irq_save {
 /* The instance data of a given MPIC */
 struct mpic
 {
+        /* The OpenFirmware dt node for this MPIC */
+        struct device_node *node;
        /* The remapper for this MPIC */
        struct irq_host         *irqhost;
@@ -293,6 +296,9 @@ struct mpic
        /* Register access method */
        enum mpic_reg_type      reg_type;
+        /* The physical base address of the MPIC */
+        phys_addr_t paddr;
        /* The various ioremap'ed bases */
        struct mpic_reg_bank    gregs;
        struct mpic_reg_bank    tmregs;
@@ -331,11 +337,11 @@ struct mpic
 * Note setting any ID (leaving those bits to 0) means standard MPIC
 */
-/* This is the primary controller, only that one has IPIs and
+/*
- * has afinity control. A non-primary MPIC always uses CPU0
+ * This is a secondary ("chained") controller; it only uses the CPU0
- * registers only
+ * registers.  Primary controllers have IPIs and affinity control.
 */
-#define MPIC_PRIMARY                    0x00000001
+#define MPIC_SECONDARY                  0x00000001
 /* Set this for a big-endian MPIC */
 #define MPIC_BIG_ENDIAN                 0x00000002
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 2893e8f5406d..a4b28f165b6c 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -109,6 +109,14 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 #define OPAL_PCI_RESET                          49
+#define OPAL_PCI_GET_HUB_DIAG_DATA              50
+#define OPAL_PCI_GET_PHB_DIAG_DATA              51
+#define OPAL_PCI_FENCE_PHB                      52
+#define OPAL_PCI_REINIT                         53
+#define OPAL_PCI_MASK_PE_ERROR                  54
+#define OPAL_SET_SLOT_LED_STATUS                55
+#define OPAL_GET_EPOW_STATUS                    56
+#define OPAL_SET_SYSTEM_ATTENTION_LED           57
 #ifndef __ASSEMBLY__
@@ -169,7 +177,11 @@ enum OpalPendingState {
        OPAL_EVENT_NVRAM = 0x2,
        OPAL_EVENT_RTC = 0x4,
        OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-        OPAL_EVENT_CONSOLE_INPUT = 0x10
+        OPAL_EVENT_CONSOLE_INPUT = 0x10,
+        OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
+        OPAL_EVENT_ERROR_LOG = 0x40,
+        OPAL_EVENT_EPOW = 0x80,
+        OPAL_EVENT_LED_STATUS = 0x100
 };
 /* Machine check related definitions */
@@ -258,13 +270,49 @@ enum OpalPeAction {
        OPAL_MAP_PE = 1
 };
+enum OpalPeltvAction {
+        OPAL_REMOVE_PE_FROM_DOMAIN = 0,
+        OPAL_ADD_PE_TO_DOMAIN = 1
+};
+enum OpalMveEnableAction {
+        OPAL_DISABLE_MVE = 0,
+        OPAL_ENABLE_MVE = 1
+};
 enum OpalPciResetAndReinitScope {
        OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
        OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
-        OPAL_PCI_IODA_RESET = 6,
+        OPAL_PCI_IODA_TABLE_RESET = 6,
+};
+enum OpalPciResetState {
+        OPAL_DEASSERT_RESET = 0,
+        OPAL_ASSERT_RESET = 1
 };
-enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
+enum OpalPciMaskAction {
+        OPAL_UNMASK_ERROR_TYPE = 0,
+        OPAL_MASK_ERROR_TYPE = 1
+};
+enum OpalSlotLedType {
+        OPAL_SLOT_LED_ID_TYPE = 0,
+        OPAL_SLOT_LED_FAULT_TYPE = 1
+};
+enum OpalLedAction {
+        OPAL_TURN_OFF_LED = 0,
+        OPAL_TURN_ON_LED = 1,
+        OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
+};
+enum OpalEpowStatus {
+        OPAL_EPOW_NONE = 0,
+        OPAL_EPOW_UPS = 1,
+        OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
+        OPAL_EPOW_OVER_INTERNAL_TEMP = 3
+};
 struct opal_machine_check_event {
        enum OpalMCE_Version    version:8;      /* 0x00 */
@@ -314,8 +362,74 @@ struct opal_machine_check_event {
        } u;
 };
+/**
+ * This structure defines the overlay which will be used to store PHB error
+ * data upon request.
+ */
+enum {
+        OPAL_P7IOC_NUM_PEST_REGS = 128,
+};
+struct OpalIoP7IOCPhbErrorData {
+        uint32_t brdgCtl;
+        // P7IOC utl regs
+        uint32_t portStatusReg;
+        uint32_t rootCmplxStatus;
+        uint32_t busAgentStatus;
+        // P7IOC cfg regs
+        uint32_t deviceStatus;
+        uint32_t slotStatus;
+        uint32_t linkStatus;
+        uint32_t devCmdStatus;
+        uint32_t devSecStatus;
+        // cfg AER regs
+        uint32_t rootErrorStatus;
+        uint32_t uncorrErrorStatus;
+        uint32_t corrErrorStatus;
+        uint32_t tlpHdr1;
+        uint32_t tlpHdr2;
+        uint32_t tlpHdr3;
+        uint32_t tlpHdr4;
+        uint32_t sourceId;
+        uint32_t rsv3;
+        // Record data about the call to allocate a buffer.
+        uint64_t errorClass;
+        uint64_t correlator;
+        //P7IOC MMIO Error Regs
+        uint64_t p7iocPlssr;                // n120
+        uint64_t p7iocCsr;                  // n110
+        uint64_t lemFir;                    // nC00
+        uint64_t lemErrorMask;              // nC18
+        uint64_t lemWOF;                    // nC40
+        uint64_t phbErrorStatus;            // nC80
+        uint64_t phbFirstErrorStatus;       // nC88
+        uint64_t phbErrorLog0;              // nCC0
+        uint64_t phbErrorLog1;              // nCC8
+        uint64_t mmioErrorStatus;           // nD00
+        uint64_t mmioFirstErrorStatus;      // nD08
+        uint64_t mmioErrorLog0;             // nD40
+        uint64_t mmioErrorLog1;             // nD48
+        uint64_t dma0ErrorStatus;           // nD80
+        uint64_t dma0FirstErrorStatus;      // nD88
+        uint64_t dma0ErrorLog0;             // nDC0
+        uint64_t dma0ErrorLog1;             // nDC8
+        uint64_t dma1ErrorStatus;           // nE00
+        uint64_t dma1FirstErrorStatus;      // nE08
+        uint64_t dma1ErrorLog0;             // nE40
+        uint64_t dma1ErrorLog1;             // nE48
+        uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
+        uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
+};
 typedef struct oppanel_line {
-        /* XXX */
+        const char *    line;
+        uint64_t        line_len;
 } oppanel_line_t;
 /* API functions */
@@ -413,6 +527,15 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
                                        uint64_t pci_mem_size);
 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_fence_phb(uint64_t phb_id);
+int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
+int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
+int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
+int64_t opal_get_epow_status(uint64_t *status);
+int64_t opal_set_system_attention_led(uint8_t led_action);
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 17722c73ba2e..269c05a36d91 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -135,6 +135,7 @@ struct paca_struct {
        u8 hard_enabled;                /* set if irqs are enabled in MSR */
        u8 io_sync;                     /* writel() needs spin_unlock sync */
        u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
+        u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
 #ifdef CONFIG_PPC_POWERNV
        /* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index dd9c4fd038e0..f072e974f8a2 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -92,20 +92,34 @@ extern unsigned int HPAGE_SHIFT;
 #define PAGE_OFFSET     ASM_CONST(CONFIG_PAGE_OFFSET)
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
-#if defined(CONFIG_RELOCATABLE)
+#if defined(CONFIG_NONSTATIC_KERNEL)
 #ifndef __ASSEMBLY__
 extern phys_addr_t memstart_addr;
 extern phys_addr_t kernstart_addr;
+#ifdef CONFIG_RELOCATABLE_PPC32
+extern long long virt_phys_offset;
 #endif
+#endif /* __ASSEMBLY__ */
 #define PHYSICAL_START  kernstart_addr
-#else
+#else   /* !CONFIG_NONSTATIC_KERNEL */
 #define PHYSICAL_START  ASM_CONST(CONFIG_PHYSICAL_START)
 #endif
+/* See Description below for VIRT_PHYS_OFFSET */
+#ifdef CONFIG_RELOCATABLE_PPC32
+#define VIRT_PHYS_OFFSET virt_phys_offset
+#else
+#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
+#endif
 #ifdef CONFIG_PPC64
 #define MEMORY_START    0UL
-#elif defined(CONFIG_RELOCATABLE)
+#elif defined(CONFIG_NONSTATIC_KERNEL)
 #define MEMORY_START    memstart_addr
 #else
 #define MEMORY_START    (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
@@ -125,12 +139,77 @@ extern phys_addr_t kernstart_addr;
 * determine MEMORY_START until then.  However we can determine PHYSICAL_START
 * from information at hand (program counter, TLB lookup).
 *
+ * On BookE with RELOCATABLE (RELOCATABLE_PPC32)
+ *
+ *   With RELOCATABLE_PPC32,  we support loading the kernel at any physical 
+ *   address without any restriction on the page alignment.
+ *
+ *   We find the runtime address of _stext and relocate ourselves based on 
+ *   the following calculation:
+ *
+ *        virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
+ *                              MODULO(_stext.run,256M)
+ *   and create the following mapping:
+ *
+ *        ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
+ *
+ *   When we process relocations, we cannot depend on the
+ *   existing equation for the __va()/__pa() translations:
+ *
+ *         __va(x) = (x)  - PHYSICAL_START + KERNELBASE
+ *
+ *   Where:
+ *       PHYSICAL_START = kernstart_addr = Physical address of _stext
+ *       KERNELBASE = Compiled virtual address of _stext.
+ *
+ *   This formula holds true iff, kernel load address is TLB page aligned.
+ *
+ *   In our case, we need to also account for the shift in the kernel Virtual 
+ *   address.
+ *
+ *   E.g.,
+ *
+ *   Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
+ *   In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
+ *
+ *   Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
+ *                 = 0xbc100000 , which is wrong.
+ *
+ *   Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
+ *              according to our mapping.
+ *
+ *   Hence we use the following formula to get the translations right:
+ *
+ *        __va(x) = (x) - [ PHYSICAL_START - Effective KERNELBASE ]
+ *
+ *        Where :
+ *              PHYSICAL_START = dynamic load address.(kernstart_addr variable)
+ *              Effective KERNELBASE = virtual_base =
+ *                                   = ALIGN_DOWN(KERNELBASE,256M) +
+ *                                              MODULO(PHYSICAL_START,256M)
+ *
+ *      To make the cost of __va() / __pa() more light weight, we introduce
+ *      a new variable virt_phys_offset, which will hold :
+ *
+ *      virt_phys_offset = Effective KERNELBASE - PHYSICAL_START
+ *                       = ALIGN_DOWN(KERNELBASE,256M) - 
+ *                              ALIGN_DOWN(PHYSICALSTART,256M)
+ *
+ *      Hence :
+ *
+ *      __va(x) = x - PHYSICAL_START + Effective KERNELBASE
+ *              = x + virt_phys_offset
+ *
+ *              and
+ *      __pa(x) = x + PHYSICAL_START - Effective KERNELBASE
+ *              = x - virt_phys_offset
+ *              
 * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use
 * the other definitions for __va & __pa.
 */
 #ifdef CONFIG_BOOKE
-#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START + KERNELBASE))
+#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))
-#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
+#define __pa(x) ((unsigned long)(x) - VIRT_PHYS_OFFSET)
 #else
 #define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START))
 #define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
@@ -290,6 +369,7 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
 extern void copy_user_page(void *to, void *from, unsigned long vaddr,
                struct page *p);
 extern int page_is_ram(unsigned long pfn);
+extern int devmem_is_allowed(unsigned long pfn);
 #ifdef CONFIG_PPC_SMLPAR
 void arch_free_page(struct page *page, int order);
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede6bc0d..fed85e6290e1 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do {						\
 #ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_PPC_MM_SLICES
 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif
 #endif /* !CONFIG_HUGETLB_PAGE */
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 56b879ab3a40..882b6aa6c857 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -153,8 +153,8 @@ struct pci_dn {
        int     pci_ext_config_space;   /* for pci devices */
-#ifdef CONFIG_EEH
        struct  pci_dev *pcidev;        /* back-pointer to the pci device */
+#ifdef CONFIG_EEH
        int     class_code;             /* pci device class */
        int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
        int     eeh_config_addr;
@@ -164,6 +164,10 @@ struct pci_dn {
        int     eeh_false_positives;    /* # times this device reported #ff's */
        u32     config_space[16];       /* saved PCI config space */
 #endif
+#define IODA_INVALID_PE         (-1)
+#ifdef CONFIG_PPC_POWERNV
+        int     pe_number;
+#endif
 };
 /* Get the pointer to a device_node's pci_dn */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 49c3de582be0..1c92013466e3 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -184,8 +184,6 @@ extern void of_scan_pci_bridge(struct pci_dev *dev);
 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
-extern int pci_read_irq_line(struct pci_dev *dev);
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
                                         unsigned long pfn,
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 88b0bd925a8b..2e0e4110f7ae 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,9 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
                                            _PAGE_COHERENT | _PAGE_WRITETHRU))
+#define pgprot_cached_noncoherent(prot) \
+                (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
 #define pgprot_writecombine pgprot_noncached_wc
 struct file;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index eb11a446720e..b585bff1a022 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -382,6 +382,9 @@ static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
 }
 #endif
+extern unsigned long cpuidle_disable;
+enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 559da199edb5..7fdc2c0b7fa0 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -951,6 +951,7 @@
 #define PVR_403GCX      0x00201400
 #define PVR_405GP       0x40110000
 #define PVR_476         0x11a52000
+#define PVR_476FPE      0x7ff50000
 #define PVR_STB03XXX    0x40310000
 #define PVR_NP405H      0x41410000
 #define PVR_NP405L      0x41610000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 03c48e819c8e..500fe1dc43e6 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
 #define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
 #endif
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP      0x15F   /* Hypervisor Available Coprocessor Register */
+#endif
 /* Bit definitions for CCR1. */
 #define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define CCR1_TCS        0x00000080 /* Timer Clock Select */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 41f69ae79d4e..01c143bb77ae 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -245,6 +245,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
+#ifdef CONFIG_PPC_RTAS_DAEMON
+extern void rtas_cancel_event_scan(void);
+#else
+static inline void rtas_cancel_event_scan(void) { }
+#endif
 /* Error types logged.  */
 #define ERR_FLAG_ALREADY_LOGGED 0x0
 #define ERR_FLAG_BOOT           0x1     /* log was pulled from NVRAM on boot */
@@ -307,5 +313,17 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
 extern void __cpuinit rtas_give_timebase(void);
 extern void __cpuinit rtas_take_timebase(void);
+#ifdef CONFIG_PPC_RTAS
+static inline int page_is_rtas_user_buf(unsigned long pfn)
+{
+        unsigned long paddr = (pfn << PAGE_SHIFT);
+        if (paddr >= rtas_rmo_buf && paddr < (rtas_rmo_buf + RTAS_RMOBUF_MAX))
+                return 1;
+        return 0;
+}
+#else
+static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;}
+#endif
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
deleted file mode 100644
index bb1e2cdeb9bf..000000000000
--- a/arch/powerpc/include/asm/rwsem.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _ASM_POWERPC_RWSEM_H
-#define _ASM_POWERPC_RWSEM_H
-#ifndef _LINUX_RWSEM_H
-#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
-#endif
-#ifdef __KERNEL__
-/*
- * R/W semaphores for PPC using the stuff in lib/rwsem.c.
- * Adapted largely from include/asm-i386/rwsem.h
- * by Paul Mackerras <paulus@samba.org>.
- */
-/*
- * the semaphore definition
- */
-#ifdef CONFIG_PPC64
-# define RWSEM_ACTIVE_MASK              0xffffffffL
-#else
-# define RWSEM_ACTIVE_MASK              0x0000ffffL
-#endif
-#define RWSEM_UNLOCKED_VALUE            0x00000000L
-#define RWSEM_ACTIVE_BIAS               0x00000001L
-#define RWSEM_WAITING_BIAS              (-RWSEM_ACTIVE_MASK-1)
-#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-/*
- * lock for reading
- */
-static inline void __down_read(struct rw_semaphore *sem)
-{
-        if (unlikely(atomic_long_inc_return((atomic_long_t *)&sem->count) <= 0))
-                rwsem_down_read_failed(sem);
-}
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-        long tmp;
-        while ((tmp = sem->count) >= 0) {
-                if (tmp == cmpxchg(&sem->count, tmp,
-                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
-                        return 1;
-                }
-        }
-        return 0;
-}
-/*
- * lock for writing
- */
-static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
-{
-        long tmp;
-        tmp = atomic_long_add_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                     (atomic_long_t *)&sem->count);
-        if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
-                rwsem_down_write_failed(sem);
-}
-static inline void __down_write(struct rw_semaphore *sem)
-{
-        __down_write_nested(sem, 0);
-}
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-        long tmp;
-        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                      RWSEM_ACTIVE_WRITE_BIAS);
-        return tmp == RWSEM_UNLOCKED_VALUE;
-}
-/*
- * unlock after reading
- */
-static inline void __up_read(struct rw_semaphore *sem)
-{
-        long tmp;
-        tmp = atomic_long_dec_return((atomic_long_t *)&sem->count);
-        if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
-                rwsem_wake(sem);
-}
-/*
- * unlock after writing
- */
-static inline void __up_write(struct rw_semaphore *sem)
-{
-        if (unlikely(atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                 (atomic_long_t *)&sem->count) < 0))
-                rwsem_wake(sem);
-}
-/*
- * implement atomic add functionality
- */
-static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
-{
-        atomic_long_add(delta, (atomic_long_t *)&sem->count);
-}
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-        long tmp;
-        tmp = atomic_long_add_return(-RWSEM_WAITING_BIAS,
-                                     (atomic_long_t *)&sem->count);
-        if (tmp < 0)
-                rwsem_downgrade_wake(sem);
-}
-/*
- * implement exchange and add functionality
- */
-static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
-{
-        return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
-}
-#endif  /* __KERNEL__ */
-#endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index e30a13d1ee76..c377457d1b89 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -193,8 +193,8 @@ extern void cacheable_memzero(void *p, unsigned int nb);
 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern int die(const char *, struct pt_regs *, long);
 extern void _exception(int, struct pt_regs *, int, unsigned long);
+extern void die(const char *, struct pt_regs *, long);
 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #ifdef CONFIG_BOOKE_WDT
@@ -221,6 +221,15 @@ extern unsigned long klimit;
 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+void cpu_idle_wait(void);
+#ifdef CONFIG_PSERIES_IDLE
+extern void update_smt_snooze_delay(int snooze);
+extern int pseries_notify_cpuidle_add_cpu(int cpu);
+#else
+static inline void update_smt_snooze_delay(int snooze) {}
+static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
+#endif
 /*
 * Atomic exchange
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index f663634cccc9..743f36b38e5d 100644
--- a/arch/powerpc/include/asm/tce.h
+++ b/arch/powerpc/include/asm/tce.h
@@ -26,10 +26,14 @@
 /*
 * Tces come in two formats, one for the virtual bus and a different
- * format for PCI
+ * format for PCI.  PCI TCEs can have hardware or software maintianed
+ * coherency.
 */
-#define TCE_VB  0
+#define TCE_VB                  0
-#define TCE_PCI 1
+#define TCE_PCI                 1
+#define TCE_PCI_SWINV_CREATE    2
+#define TCE_PCI_SWINV_FREE      4
+#define TCE_PCI_SWINV_PAIR      8
 /* TCE page size is 4096 bytes (1 << 12) */
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index fe6f7c2c9c68..7eb10fb96cd0 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -219,5 +219,7 @@ DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
 extern void secondary_cpu_time_init(void);
 extern void iSeries_time_init_early(void);
+DECLARE_PER_CPU(u64, decrementers_next_tb);
 #endif /* __KERNEL__ */
 #endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 8947b9827bc4..d82e94e6c2b4 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -5,8 +5,11 @@
 * This is here because we used to use l64 for 64bit powerpc
 * and we don't want to impact user mode with our change to ll64
 * in the kernel.
+ *
+ * However, some user programs are fine with this.  They can
+ * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
 */
-#if defined(__powerpc64__) && !defined(__KERNEL__)
+#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
 # include <asm-generic/int-l64.h>
 #else
 # include <asm-generic/int-ll64.h>
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index ce4f7f179117..ee728e433aa2 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -85,6 +85,8 @@ extra-$(CONFIG_FSL_BOOKE)	:= head_fsl_booke.o
 extra-$(CONFIG_8xx)             := head_8xx.o
 extra-y                         += vmlinux.lds
+obj-$(CONFIG_RELOCATABLE_PPC32) += reloc_32.o
 obj-$(CONFIG_PPC32)             += entry_32.o setup_32.o
 obj-$(CONFIG_PPC64)             += dma-iommu.o iommu.o
 obj-$(CONFIG_KGDB)              += kgdb.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 7c5324f1ec9c..04caee7d9bc1 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -208,6 +208,7 @@ int main(void)
        DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
        DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
        DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
+        DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
 #endif /* CONFIG_PPC64 */
        /* RTAS */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818feaa7a5..ebc62f42a237 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
         * core local but doing it always won't hurt
         */
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
        /* Make sure ACOP starts out as zero */
        li      r3,0
        mtspr   SPRN_ACOP,r3
+        /* Skip the following if we are in Guest mode */
+        mfmsr   r3
+        andis.  r0,r3,MSR_GS@h
+        bne     _icswx_skip_guest
        /* Enable icswx instruction */
        mfspr   r3,SPRN_A2_CCR2
        ori     r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
        /* Unmask all CTs in HACOP */
        li      r3,-1
        mtspr   SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
        /* Enable doorbell */
        mfspr   r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index edae5bb06f1f..81db9e2a8a20 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1505,6 +1505,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .machine_check          = machine_check_4xx,
                .platform               = "ppc405",
        },
+        {       /* APM8018X */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x7ff11432,
+                .cpu_name               = "APM8018X",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
        {       /* default match */
                .pvr_mask               = 0x00000000,
                .pvr_value              = 0x00000000,
@@ -1830,6 +1843,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .machine_check          = machine_check_47x,
                .platform               = "ppc470",
        },
+        { /* 476fpe */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x7ff50000,
+                .cpu_name               = "476fpe",
+                .cpu_features           = CPU_FTRS_47X | CPU_FTR_476_DD2,
+                .cpu_user_features      = COMMON_USER_BOOKE |
+                        PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_47x |
+                        MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 128,
+                .machine_check          = machine_check_47x,
+                .platform               = "ppc470",
+        },
        { /* 476 iss */
                .pvr_mask               = 0xffff0000,
                .pvr_value              = 0x00050000,
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index d879809d5c45..28be3452e67a 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -10,85 +10,85 @@
 *
 */
-#undef DEBUG
 #include <linux/kernel.h>
 #include <linux/smp.h>
 #include <linux/reboot.h>
 #include <linux/kexec.h>
-#include <linux/bootmem.h>
 #include <linux/export.h>
 #include <linux/crash_dump.h>
 #include <linux/delay.h>
-#include <linux/elf.h>
-#include <linux/elfcore.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/types.h>
-#include <linux/memblock.h>
 #include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/kexec.h>
 #include <asm/kdump.h>
 #include <asm/prom.h>
-#include <asm/firmware.h>
 #include <asm/smp.h>
 #include <asm/system.h>
 #include <asm/setjmp.h>
-#ifdef DEBUG
+/*
-#include <asm/udbg.h>
+ * The primary CPU waits a while for all secondary CPUs to enter. This is to
-#define DBG(fmt...) udbg_printf(fmt)
+ * avoid sending an IPI if the secondary CPUs are entering
-#else
+ * crash_kexec_secondary on their own (eg via a system reset).
-#define DBG(fmt...)
+ *
-#endif
+ * The secondary timeout has to be longer than the primary. Both timeouts are
+ * in milliseconds.
+ */
+#define PRIMARY_TIMEOUT         500
+#define SECONDARY_TIMEOUT       1000
-/* This keeps a track of which one is crashing cpu. */
+#define IPI_TIMEOUT             10000
+#define REAL_MODE_TIMEOUT       10000
+/* This keeps a track of which one is the crashing cpu. */
 int crashing_cpu = -1;
-static cpumask_t cpus_in_crash = CPU_MASK_NONE;
+static atomic_t cpus_in_crash;
-cpumask_t cpus_in_sr = CPU_MASK_NONE;
+static int time_to_dump;
 #define CRASH_HANDLER_MAX 3
 /* NULL terminated list of shutdown handles */
 static crash_shutdown_t crash_shutdown_handles[CRASH_HANDLER_MAX+1];
 static DEFINE_SPINLOCK(crash_handlers_lock);
+static unsigned long crash_shutdown_buf[JMP_BUF_LEN];
+static int crash_shutdown_cpu = -1;
+static int handle_fault(struct pt_regs *regs)
+{
+        if (crash_shutdown_cpu == smp_processor_id())
+                longjmp(crash_shutdown_buf, 1);
+        return 0;
+}
 #ifdef CONFIG_SMP
-static atomic_t enter_on_soft_reset = ATOMIC_INIT(0);
 void crash_ipi_callback(struct pt_regs *regs)
 {
+        static cpumask_t cpus_state_saved = CPU_MASK_NONE;
        int cpu = smp_processor_id();
        if (!cpu_online(cpu))
                return;
        hard_irq_disable();
-        if (!cpumask_test_cpu(cpu, &cpus_in_crash))
+        if (!cpumask_test_cpu(cpu, &cpus_state_saved)) {
                crash_save_cpu(regs, cpu);
-        cpumask_set_cpu(cpu, &cpus_in_crash);
+                cpumask_set_cpu(cpu, &cpus_state_saved);
-        /*
-         * Entered via soft-reset - could be the kdump
-         * process is invoked using soft-reset or user activated
-         * it if some CPU did not respond to an IPI.
-         * For soft-reset, the secondary CPU can enter this func
-         * twice. 1 - using IPI, and 2. soft-reset.
-         * Tell the kexec CPU that entered via soft-reset and ready
-         * to go down.
-         */
-        if (cpumask_test_cpu(cpu, &cpus_in_sr)) {
-                cpumask_clear_cpu(cpu, &cpus_in_sr);
-                atomic_inc(&enter_on_soft_reset);
        }
+        atomic_inc(&cpus_in_crash);
+        smp_mb__after_atomic_inc();
        /*
         * Starting the kdump boot.
         * This barrier is needed to make sure that all CPUs are stopped.
-         * If not, soft-reset will be invoked to bring other CPUs.
         */
-        while (!cpumask_test_cpu(crashing_cpu, &cpus_in_crash))
+        while (!time_to_dump)
                cpu_relax();
        if (ppc_md.kexec_cpu_down)
@@ -103,106 +103,99 @@ void crash_ipi_callback(struct pt_regs *regs)
        /* NOTREACHED */
 }
-/*
- * Wait until all CPUs are entered via soft-reset.
- */
-static void crash_soft_reset_check(int cpu)
-{
-        unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
-        cpumask_clear_cpu(cpu, &cpus_in_sr);
-        while (atomic_read(&enter_on_soft_reset) != ncpus)
-                cpu_relax();
-}
 static void crash_kexec_prepare_cpus(int cpu)
 {
        unsigned int msecs;
        unsigned int ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
+        int tries = 0;
+        int (*old_handler)(struct pt_regs *regs);
+        printk(KERN_EMERG "Sending IPI to other CPUs\n");
        crash_send_ipi(crash_ipi_callback);
        smp_wmb();
+again:
        /*
         * FIXME: Until we will have the way to stop other CPUs reliably,
         * the crash CPU will send an IPI and wait for other CPUs to
         * respond.
-         * Delay of at least 10 seconds.
         */
-        printk(KERN_EMERG "Sending IPI to other cpus...\n");
+        msecs = IPI_TIMEOUT;
-        msecs = 10000;
+        while ((atomic_read(&cpus_in_crash) < ncpus) && (--msecs > 0))
-        while ((cpumask_weight(&cpus_in_crash) < ncpus) && (--msecs > 0)) {
-                cpu_relax();
                mdelay(1);
-        }
        /* Would it be better to replace the trap vector here? */
+        if (atomic_read(&cpus_in_crash) >= ncpus) {
+                printk(KERN_EMERG "IPI complete\n");
+                return;
+        }
+        printk(KERN_EMERG "ERROR: %d cpu(s) not responding\n",
+                ncpus - atomic_read(&cpus_in_crash));
        /*
-         * FIXME: In case if we do not get all CPUs, one possibility: ask the
+         * If we have a panic timeout set then we can't wait indefinitely
-         * user to do soft reset such that we get all.
+         * for someone to activate system reset. We also give up on the
-         * Soft-reset will be used until better mechanism is implemented.
+         * second time through if system reset fail to work.
         */
-        if (cpumask_weight(&cpus_in_crash) < ncpus) {
+        if ((panic_timeout > 0) || (tries > 0))
-                printk(KERN_EMERG "done waiting: %d cpu(s) not responding\n",
+                return;
-                        ncpus - cpumask_weight(&cpus_in_crash));
-                printk(KERN_EMERG "Activate soft-reset to stop other cpu(s)\n");
-                cpumask_clear(&cpus_in_sr);
-                atomic_set(&enter_on_soft_reset, 0);
-                while (cpumask_weight(&cpus_in_crash) < ncpus)
-                        cpu_relax();
-        }
        /*
-         * Make sure all CPUs are entered via soft-reset if the kdump is
+         * A system reset will cause all CPUs to take an 0x100 exception.
-         * invoked using soft-reset.
+         * The primary CPU returns here via setjmp, and the secondary
+         * CPUs reexecute the crash_kexec_secondary path.
         */
-        if (cpumask_test_cpu(cpu, &cpus_in_sr))
+        old_handler = __debugger;
-                crash_soft_reset_check(cpu);
+        __debugger = handle_fault;
-        /* Leave the IPI callback set */
+        crash_shutdown_cpu = smp_processor_id();
+        if (setjmp(crash_shutdown_buf) == 0) {
+                printk(KERN_EMERG "Activate system reset (dumprestart) "
+                                  "to stop other cpu(s)\n");
+                /*
+                 * A system reset will force all CPUs to execute the
+                 * crash code again. We need to reset cpus_in_crash so we
+                 * wait for everyone to do this.
+                 */
+                atomic_set(&cpus_in_crash, 0);
+                smp_mb();
+                while (atomic_read(&cpus_in_crash) < ncpus)
+                        cpu_relax();
+        }
+        crash_shutdown_cpu = -1;
+        __debugger = old_handler;
+        tries++;
+        goto again;
 }
 /*
- * This function will be called by secondary cpus or by kexec cpu
+ * This function will be called by secondary cpus.
- * if soft-reset is activated to stop some CPUs.
 */
 void crash_kexec_secondary(struct pt_regs *regs)
 {
-        int cpu = smp_processor_id();
        unsigned long flags;
-        int msecs = 5;
+        int msecs = SECONDARY_TIMEOUT;
        local_irq_save(flags);
-        /* Wait 5ms if the kexec CPU is not entered yet. */
+        /* Wait for the primary crash CPU to signal its progress */
        while (crashing_cpu < 0) {
                if (--msecs < 0) {
-                        /*
+                        /* No response, kdump image may not have been loaded */
-                         * Either kdump image is not loaded or
-                         * kdump process is not started - Probably xmon
-                         * exited using 'x'(exit and recover) or
-                         * kexec_should_crash() failed for all running tasks.
-                         */
-                        cpumask_clear_cpu(cpu, &cpus_in_sr);
                        local_irq_restore(flags);
                        return;
                }
                mdelay(1);
-                cpu_relax();
-        }
-        if (cpu == crashing_cpu) {
-                /*
-                 * Panic CPU will enter this func only via soft-reset.
-                 * Wait until all secondary CPUs entered and
-                 * then start kexec boot.
-                 */
-                crash_soft_reset_check(cpu);
-                cpumask_set_cpu(crashing_cpu, &cpus_in_crash);
-                if (ppc_md.kexec_cpu_down)
-                        ppc_md.kexec_cpu_down(1, 0);
-                machine_kexec(kexec_crash_image);
-                /* NOTREACHED */
        }
        crash_ipi_callback(regs);
 }
@@ -211,7 +204,7 @@ void crash_kexec_secondary(struct pt_regs *regs)
 static void crash_kexec_prepare_cpus(int cpu)
 {
        /*
-         * move the secondarys to us so that we can copy
+         * move the secondaries to us so that we can copy
         * the new kernel 0-0x100 safely
         *
         * do this if kexec in setup.c ?
@@ -225,7 +218,6 @@ static void crash_kexec_prepare_cpus(int cpu)
 void crash_kexec_secondary(struct pt_regs *regs)
 {
-        cpumask_clear(&cpus_in_sr);
 }
 #endif  /* CONFIG_SMP */
@@ -236,7 +228,7 @@ static void crash_kexec_wait_realmode(int cpu)
        unsigned int msecs;
        int i;
-        msecs = 10000;
+        msecs = REAL_MODE_TIMEOUT;
        for (i=0; i < nr_cpu_ids && msecs > 0; i++) {
                if (i == cpu)
                        continue;
@@ -308,22 +300,11 @@ int crash_shutdown_unregister(crash_shutdown_t handler)
 }
 EXPORT_SYMBOL(crash_shutdown_unregister);
-static unsigned long crash_shutdown_buf[JMP_BUF_LEN];
-static int crash_shutdown_cpu = -1;
-static int handle_fault(struct pt_regs *regs)
-{
-        if (crash_shutdown_cpu == smp_processor_id())
-                longjmp(crash_shutdown_buf, 1);
-        return 0;
-}
 void default_machine_crash_shutdown(struct pt_regs *regs)
 {
        unsigned int i;
        int (*old_handler)(struct pt_regs *regs);
        /*
         * This function is only called after the system
         * has panicked or is otherwise in a critical state.
@@ -341,15 +322,26 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
         * such that another IPI will not be sent.
         */
        crashing_cpu = smp_processor_id();
-        crash_save_cpu(regs, crashing_cpu);
+        /*
+         * If we came in via system reset, wait a while for the secondary
+         * CPUs to enter.
+         */
+        if (TRAP(regs) == 0x100)
+                mdelay(PRIMARY_TIMEOUT);
        crash_kexec_prepare_cpus(crashing_cpu);
-        cpumask_set_cpu(crashing_cpu, &cpus_in_crash);
+        crash_save_cpu(regs, crashing_cpu);
+        time_to_dump = 1;
        crash_kexec_wait_realmode(crashing_cpu);
        machine_kexec_mask_interrupts();
        /*
-         * Call registered shutdown routines savely.  Swap out
+         * Call registered shutdown routines safely.  Swap out
         * __debugger_fault_handler, and replace on exit.
         */
        old_handler = __debugger_fault_handler;
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 424afb6b8fba..b3ba5163eae2 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -28,7 +28,7 @@
 #define DBG(fmt...)
 #endif
-#ifndef CONFIG_RELOCATABLE
+#ifndef CONFIG_NONSTATIC_KERNEL
 void __init reserve_kdump_trampoline(void)
 {
        memblock_reserve(0, KDUMP_RESERVE_LIMIT);
@@ -67,7 +67,7 @@ void __init setup_kdump_trampoline(void)
        DBG(" <- setup_kdump_trampoline()\n");
 }
-#endif /* CONFIG_RELOCATABLE */
+#endif /* CONFIG_NONSTATIC_KERNEL */
 static int __init parse_savemaxmem(char *p)
 {
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index cf9c69b9189c..d4be7bb3dbdf 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -65,7 +65,7 @@ BEGIN_FTR_SECTION
        lbz     r0,PACAPROCSTART(r13)
        cmpwi   r0,0x80
        bne     1f
-        li      r0,0
+        li      r0,1
        stb     r0,PACAPROCSTART(r13)
        b       kvm_start_guest
 1:
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index b725dab0f88a..7dd2981bcc50 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -64,6 +64,35 @@ _ENTRY(_start);
        mr      r31,r3          /* save device tree ptr */
        li      r24,0           /* CPU number */
+#ifdef CONFIG_RELOCATABLE
+/*
+ * Relocate ourselves to the current runtime address.
+ * This is called only by the Boot CPU.
+ * "relocate" is called with our current runtime virutal
+ * address.
+ * r21 will be loaded with the physical runtime address of _stext
+ */
+        bl      0f                              /* Get our runtime address */
+0:      mflr    r21                             /* Make it accessible */
+        addis   r21,r21,(_stext - 0b)@ha
+        addi    r21,r21,(_stext - 0b)@l         /* Get our current runtime base */
+        /*
+         * We have the runtime (virutal) address of our base.
+         * We calculate our shift of offset from a 256M page.
+         * We could map the 256M page we belong to at PAGE_OFFSET and
+         * get going from there.
+         */
+        lis     r4,KERNELBASE@h
+        ori     r4,r4,KERNELBASE@l
+        rlwinm  r6,r21,0,4,31                   /* r6 = PHYS_START % 256M */
+        rlwinm  r5,r4,0,4,31                    /* r5 = KERNELBASE % 256M */
+        subf    r3,r5,r6                        /* r3 = r6 - r5 */
+        add     r3,r4,r3                        /* Required Virutal Address */
+        bl      relocate
+#endif
        bl      init_cpu_state
        /*
@@ -88,6 +117,65 @@ _ENTRY(_start);
 #ifdef CONFIG_RELOCATABLE
        /*
+         * Relocatable kernel support based on processing of dynamic
+         * relocation entries.
+         *
+         * r25 will contain RPN/ERPN for the start address of memory
+         * r21 will contain the current offset of _stext
+         */
+        lis     r3,kernstart_addr@ha
+        la      r3,kernstart_addr@l(r3)
+        /*
+         * Compute the kernstart_addr.
+         * kernstart_addr => (r6,r8)
+         * kernstart_addr & ~0xfffffff => (r6,r7)
+         */
+        rlwinm  r6,r25,0,28,31  /* ERPN. Bits 32-35 of Address */
+        rlwinm  r7,r25,0,0,3    /* RPN - assuming 256 MB page size */
+        rlwinm  r8,r21,0,4,31   /* r8 = (_stext & 0xfffffff) */
+        or      r8,r7,r8        /* Compute the lower 32bit of kernstart_addr */
+        /* Store kernstart_addr */
+        stw     r6,0(r3)        /* higher 32bit */
+        stw     r8,4(r3)        /* lower 32bit  */
+        /*
+         * Compute the virt_phys_offset :
+         * virt_phys_offset = stext.run - kernstart_addr
+         *
+         * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff)
+         * When we relocate, we have :
+         *
+         *      (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff)
+         *
+         * hence:
+         *  virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
+         *
+         */
+        /* KERNELBASE&~0xfffffff => (r4,r5) */
+        li      r4, 0           /* higer 32bit */
+        lis     r5,KERNELBASE@h
+        rlwinm  r5,r5,0,0,3     /* Align to 256M, lower 32bit */
+        /*
+         * 64bit subtraction.
+         */
+        subfc   r5,r7,r5
+        subfe   r4,r6,r4
+        /* Store virt_phys_offset */
+        lis     r3,virt_phys_offset@ha
+        la      r3,virt_phys_offset@l(r3)
+        stw     r4,0(r3)
+        stw     r5,4(r3)
+#elif defined(CONFIG_DYNAMIC_MEMSTART)
+        /*
+         * Mapping based, page aligned dynamic kernel loading.
+         *
         * r25 will contain RPN/ERPN for the start address of memory
         *
         * Add the difference between KERNELBASE and PAGE_OFFSET to the
@@ -732,6 +820,8 @@ _GLOBAL(init_cpu_state)
        /* We use the PVR to differenciate 44x cores from 476 */
        mfspr   r3,SPRN_PVR
        srwi    r3,r3,16
+        cmplwi  cr0,r3,PVR_476FPE@h
+        beq     head_start_47x
        cmplwi  cr0,r3,PVR_476@h
        beq     head_start_47x
        cmplwi  cr0,r3,PVR_476_ISS@h
@@ -800,12 +890,29 @@ skpinv:	addi	r4,r4,1				/* Increment */
 /*
 * Configure and load pinned entry into TLB slot 63.
 */
+#ifdef CONFIG_NONSTATIC_KERNEL
+        /*
+         * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT
+         * entries of the initial mapping set by the boot loader.
+         * The XLAT entry is stored in r25
+         */
+        /* Read the XLAT entry for our current mapping */
+        tlbre   r25,r23,PPC44x_TLB_XLAT
+        lis     r3,KERNELBASE@h
+        ori     r3,r3,KERNELBASE@l
+        /* Use our current RPN entry */
+        mr      r4,r25
+#else
        lis     r3,PAGE_OFFSET@h
        ori     r3,r3,PAGE_OFFSET@l
        /* Kernel is at the base of RAM */
        li r4, 0                        /* Load the kernel physical address */
+#endif
        /* Load the kernel PID = 0 */
        li      r0,0
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 9f5d210ddf3f..d5d78c4ceef6 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -197,7 +197,7 @@ _ENTRY(__early_start)
        bl      early_init
-#ifdef CONFIG_RELOCATABLE
+#ifdef CONFIG_DYNAMIC_MEMSTART
        lis     r3,kernstart_addr@ha
        la      r3,kernstart_addr@l(r3)
 #ifdef CONFIG_PHYS_64BIT
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 9c3cd490b1bd..7c66ce13da89 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -39,9 +39,13 @@
 #define cpu_should_die()        0
 #endif
+unsigned long cpuidle_disable = IDLE_NO_OVERRIDE;
+EXPORT_SYMBOL(cpuidle_disable);
 static int __init powersave_off(char *arg)
 {
        ppc_md.power_save = NULL;
+        cpuidle_disable = IDLE_POWERSAVE_OFF;
        return 0;
 }
 __setup("powersave=off", powersave_off);
@@ -113,6 +117,29 @@ void cpu_idle(void)
        }
 }
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs come out of the old
+ * idle loop and start using the new idle loop.
+ * Required while changing idle handler on SMP systems.
+ * Caller must have changed idle handler to the new value before the call.
+ * This window may be larger on shared systems.
+ */
+void cpu_idle_wait(void)
+{
+        int cpu;
+        smp_mb();
+        /* kick all the CPUs so that they exit out of old idle routine */
+        get_online_cpus();
+        for_each_online_cpu(cpu) {
+                if (cpu != smp_processor_id())
+                        smp_send_reschedule(cpu);
+        }
+        put_online_cpus();
+}
+EXPORT_SYMBOL_GPL(cpu_idle_wait);
 int powersave_nap;
 #ifdef CONFIG_SYSCTL
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 3a70845a51c7..fcdff198da4b 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -54,6 +54,7 @@ _GLOBAL(power7_idle)
        li      r0,0
        stb     r0,PACASOFTIRQEN(r13)   /* we'll hard-enable shortly */
        stb     r0,PACAHARDIRQEN(r13)
+        stb     r0,PACA_NAPSTATELOST(r13)
        /* Continue saving state */
        SAVE_GPR(2, r1)
@@ -86,6 +87,9 @@ _GLOBAL(power7_wakeup_loss)
        rfid
 _GLOBAL(power7_wakeup_noloss)
+        lbz     r0,PACA_NAPSTATELOST(r13)
+        cmpwi   r0,0
+        bne     .power7_wakeup_loss
        ld      r1,PACAR1(r13)
        ld      r4,_MSR(r1)
        ld      r5,_NIP(r1)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5c3c46948d94..701d4aceb4f4 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -115,6 +115,15 @@ static inline notrace void set_soft_enabled(unsigned long enable)
        : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
 }
+static inline notrace void decrementer_check_overflow(void)
+{
+        u64 now = get_tb_or_rtc();
+        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
+        if (now >= *next_tb)
+                set_dec(1);
+}
 notrace void arch_local_irq_restore(unsigned long en)
 {
        /*
@@ -164,24 +173,21 @@ notrace void arch_local_irq_restore(unsigned long en)
         */
        local_paca->hard_enabled = en;
-#ifndef CONFIG_BOOKE
+        /*
-        /* On server, re-trigger the decrementer if it went negative since
+         * Trigger the decrementer if we have a pending event. Some processors
-         * some processors only trigger on edge transitions of the sign bit.
+         * only trigger on edge transitions of the sign bit. We might also
-         *
+         * have disabled interrupts long enough that the decrementer wrapped
-         * BookE has a level sensitive decrementer (latches in TSR) so we
+         * to positive.
-         * don't need that
         */
-        if ((int)mfspr(SPRN_DEC) < 0)
+        decrementer_check_overflow();
-                mtspr(SPRN_DEC, 1);
-#endif /* CONFIG_BOOKE */
        /*
         * Force the delivery of pending soft-disabled interrupts on PS3.
         * Any HV call will have this side effect.
         */
        if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
-                u64 tmp;
+                u64 tmp, tmp2;
-                lv1_get_version_info(&tmp);
+                lv1_get_version_info(&tmp, &tmp2);
        }
        __hard_irq_enable();
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index a2158a395d96..c957b1202bdc 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -125,7 +125,7 @@ void __init reserve_crashkernel(void)
        crash_size = resource_size(&crashk_res);
-#ifndef CONFIG_RELOCATABLE
+#ifndef CONFIG_NONSTATIC_KERNEL
        if (crashk_res.start != KDUMP_KERNELBASE)
                printk("Crash kernel location must be 0x%x\n",
                                KDUMP_KERNELBASE);
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 458ed3bee663..fa4a573d6716 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -214,7 +214,7 @@ char __devinit *pcibios_setup(char *str)
 * If the interrupt is used, then gets the interrupt line from the
 * openfirmware and sets it in the pci_dev and pci_config line.
 */
-int pci_read_irq_line(struct pci_dev *pci_dev)
+static int pci_read_irq_line(struct pci_dev *pci_dev)
 {
        struct of_irq oirq;
        unsigned int virq;
@@ -283,7 +283,6 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
        return 0;
 }
-EXPORT_SYMBOL(pci_read_irq_line);
 /*
 * Platform support for /proc/bus/pci/X/Y mmap()s,
@@ -921,18 +920,22 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                struct resource *res = dev->resource + i;
                if (!res->flags)
                        continue;
-                /* On platforms that have PCI_PROBE_ONLY set, we don't
-                 * consider 0 as an unassigned BAR value. It's technically
+                /* If we're going to re-assign everything, we mark all resources
-                 * a valid value, but linux doesn't like it... so when we can
+                 * as unset (and 0-base them). In addition, we mark BARs starting
-                 * re-assign things, we do so, but if we can't, we keep it
+                 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
-                 * around and hope for the best...
+                 * since in that case, we don't want to re-assign anything
                 */
-                if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) {
+                if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
-                        pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
+                    (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
-                                 pci_name(dev), i,
+                        /* Only print message if not re-assigning */
-                                 (unsigned long long)res->start,
+                        if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
-                                 (unsigned long long)res->end,
+                                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
-                                 (unsigned int)res->flags);
+                                         "is unassigned\n",
+                                         pci_name(dev), i,
+                                         (unsigned long long)res->start,
+                                         (unsigned long long)res->end,
+                                         (unsigned int)res->flags);
                        res->end -= res->start;
                        res->start = 0;
                        res->flags |= IORESOURCE_UNSET;
@@ -1042,6 +1045,16 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                if (i >= 3 && bus->self->transparent)
                        continue;
+                /* If we are going to re-assign everything, mark the resource
+                 * as unset and move it down to 0
+                 */
+                if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
+                        res->flags |= IORESOURCE_UNSET;
+                        res->end -= res->start;
+                        res->start = 0;
+                        continue;
+                }
                pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
                         pci_name(dev), i,
                         (unsigned long long)res->start,\
@@ -1262,18 +1275,15 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
        pci_bus_for_each_resource(bus, res, i) {
                if (!res || !res->flags || res->start > res->end || res->parent)
                        continue;
+                /* If the resource was left unset at this point, we clear it */
+                if (res->flags & IORESOURCE_UNSET)
+                        goto clear_resource;
                if (bus->parent == NULL)
                        pr = (res->flags & IORESOURCE_IO) ?
                                &ioport_resource : &iomem_resource;
                else {
-                        /* Don't bother with non-root busses when
-                         * re-assigning all resources. We clear the
-                         * resource flags as if they were colliding
-                         * and as such ensure proper re-allocation
-                         * later.
-                         */
-                        if (pci_has_flag(PCI_REASSIGN_ALL_RSRC))
-                                goto clear_resource;
                        pr = pci_find_parent_resource(bus->self, res);
                        if (pr == res) {
                                /* this happens when the generic PCI
@@ -1304,9 +1314,9 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
                        if (reparent_resources(pr, res) == 0)
                                continue;
                }
-                printk(KERN_WARNING "PCI: Cannot allocate resource region "
+                pr_warning("PCI: Cannot allocate resource region "
-                       "%d of PCI bridge %d, will remap\n", i, bus->number);
+                           "%d of PCI bridge %d, will remap\n", i, bus->number);
-clear_resource:
+        clear_resource:
                res->start = res->end = 0;
                res->flags = 0;
        }
@@ -1451,16 +1461,11 @@ void __init pcibios_resource_survey(void)
 {
        struct pci_bus *b;
-        /* Allocate and assign resources. If we re-assign everything, then
+        /* Allocate and assign resources */
-         * we skip the allocate phase
-         */
        list_for_each_entry(b, &pci_root_buses, node)
                pcibios_allocate_bus_resources(b);
+        pcibios_allocate_resources(0);
-        if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
+        pcibios_allocate_resources(1);
-                pcibios_allocate_resources(0);
-                pcibios_allocate_resources(1);
-        }
        /* Before we start assigning unassigned resource, we try to reserve
         * the low IO area and the VGA memory area if they intersect the
@@ -1732,6 +1737,12 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
        if (mode == PCI_PROBE_NORMAL)
                hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
+        /* Platform gets a chance to do some global fixups before
+         * we proceed to resource allocation
+         */
+        if (ppc_md.pcibios_fixup_phb)
+                ppc_md.pcibios_fixup_phb(hose);
        /* Configure PCI Express settings */
        if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
                struct pci_bus *child;
@@ -1747,10 +1758,13 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
 {
        int i, class = dev->class >> 8;
+        /* When configured as agent, programing interface = 1 */
+        int prog_if = dev->class & 0xf;
        if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
             class == PCI_CLASS_BRIDGE_OTHER) &&
                (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
+                (prog_if == 0) &&
                (dev->bus->parent == NULL)) {
                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                        dev->resource[i].start = 0;
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 4e69deb89b37..dd9e4a04bf79 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -50,6 +50,9 @@ void * __devinit update_dn_pci_info(struct device_node *dn, void *data)
        dn->data = pdn;
        pdn->node = dn;
        pdn->phb = phb;
+#ifdef CONFIG_PPC_POWERNV
+        pdn->pe_number = IODA_INVALID_PE;
+#endif
        regs = of_get_property(dn, "reg", NULL);
        if (regs) {
                /* First register entry is addr (00BBSS00)  */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 6457574c0b2f..ebe5766781aa 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -584,16 +584,32 @@ static struct regbit {
        unsigned long bit;
        const char *name;
 } msr_bits[] = {
+#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
+        {MSR_SF,        "SF"},
+        {MSR_HV,        "HV"},
+#endif
+        {MSR_VEC,       "VEC"},
+        {MSR_VSX,       "VSX"},
+#ifdef CONFIG_BOOKE
+        {MSR_CE,        "CE"},
+#endif
        {MSR_EE,        "EE"},
        {MSR_PR,        "PR"},
        {MSR_FP,        "FP"},
-        {MSR_VEC,       "VEC"},
-        {MSR_VSX,       "VSX"},
        {MSR_ME,        "ME"},
-        {MSR_CE,        "CE"},
+#ifdef CONFIG_BOOKE
        {MSR_DE,        "DE"},
+#else
+        {MSR_SE,        "SE"},
+        {MSR_BE,        "BE"},
+#endif
        {MSR_IR,        "IR"},
        {MSR_DR,        "DR"},
+        {MSR_PMM,       "PMM"},
+#ifndef CONFIG_BOOKE
+        {MSR_RI,        "RI"},
+        {MSR_LE,        "LE"},
+#endif
        {0,             NULL}
 };
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index cc584865b3df..eca626ea3f23 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -742,7 +742,7 @@ static unsigned char ibm_architecture_vec[] = {
        W(0xffffffff),                  /* virt_base */
        W(0xffffffff),                  /* virt_size */
        W(0xffffffff),                  /* load_base */
-        W(64),                          /* 64MB min RMA */
+        W(256),                         /* 256MB min RMA */
        W(0xffffffff),                  /* full client load */
        0,                              /* min RMA percentage of total RAM */
        48,                             /* max log_2(hash table size) */
@@ -1224,14 +1224,6 @@ static void __init prom_init_mem(void)
        RELOC(alloc_bottom) = PAGE_ALIGN((unsigned long)&RELOC(_end) + 0x4000);
-        /* Check if we have an initrd after the kernel, if we do move our bottom
-         * point to after it
-         */
-        if (RELOC(prom_initrd_start)) {
-                if (RELOC(prom_initrd_end) > RELOC(alloc_bottom))
-                        RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(prom_initrd_end));
-        }
        /*
         * If prom_memory_limit is set we reduce the upper limits *except* for
         * alloc_top_high. This must be the real top of RAM so we can put
@@ -1269,6 +1261,15 @@ static void __init prom_init_mem(void)
        RELOC(alloc_top) = RELOC(rmo_top);
        RELOC(alloc_top_high) = RELOC(ram_top);
+        /*
+         * Check if we have an initrd after the kernel but still inside
+         * the RMO.  If we do move our bottom point to after it.
+         */
+        if (RELOC(prom_initrd_start) &&
+            RELOC(prom_initrd_start) < RELOC(rmo_top) &&
+            RELOC(prom_initrd_end) > RELOC(alloc_bottom))
+                RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(prom_initrd_end));
        prom_printf("memory layout at init:\n");
        prom_printf("  memory_limit : %x (16 MB aligned)\n", RELOC(prom_memory_limit));
        prom_printf("  alloc_bottom : %x\n", RELOC(alloc_bottom));
@@ -2079,7 +2080,7 @@ static void __init prom_check_displays(void)
                /* Setup a usable color table when the appropriate
                 * method is available. Should update this to set-colors */
                clut = RELOC(default_colors);
-                for (i = 0; i < 32; i++, clut += 3)
+                for (i = 0; i < 16; i++, clut += 3)
                        if (prom_set_color(ih, i, clut[0], clut[1],
                                           clut[2]) != 0)
                                break;
@@ -2844,7 +2845,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
        RELOC(of_platform) = prom_find_machine_type();
        prom_printf("Detected machine type: %x\n", RELOC(of_platform));
-#ifndef CONFIG_RELOCATABLE
+#ifndef CONFIG_NONSTATIC_KERNEL
        /* Bail if this is a kdump kernel. */
        if (PHYSICAL_START > 0)
                prom_panic("Error: You can't boot a kdump kernel from OF!\n");
@@ -2969,9 +2970,11 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
        /*
         * in case stdin is USB and still active on IBM machines...
         * Unfortunately quiesce crashes on some powermacs if we have
-         * closed stdin already (in particular the powerbook 101).
+         * closed stdin already (in particular the powerbook 101). It
+         * appears that the OPAL version of OFW doesn't like it either.
         */
-        if (RELOC(of_platform) != PLATFORM_POWERMAC)
+        if (RELOC(of_platform) != PLATFORM_POWERMAC &&
+            RELOC(of_platform) != PLATFORM_OPAL)
                prom_close_stdin();
        /*
@@ -2987,8 +2990,12 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
         * is common to us and kexec
         */
        hdr = RELOC(dt_header_start);
-        prom_printf("returning from prom_init\n");
-        prom_debug("->dt_header_start=0x%x\n", hdr);
+        /* Don't print anything after quiesce under OPAL, it crashes OFW */
+        if (RELOC(of_platform) != PLATFORM_OPAL) {
+                prom_printf("returning from prom_init\n");
+                prom_debug("->dt_header_start=0x%x\n", hdr);
+        }
 #ifdef CONFIG_PPC32
        reloc_got2(-offset);
diff --git a/arch/powerpc/kernel/reloc_32.S b/arch/powerpc/kernel/reloc_32.S
new file mode 100644
index 000000000000..ef46ba6e094f
--- /dev/null
+++ b/arch/powerpc/kernel/reloc_32.S
@@ -0,0 +1,208 @@
+/*
+ * Code to process dynamic relocations for PPC32.
+ *
+ * Copyrights (C) IBM Corporation, 2011.
+ *      Author: Suzuki Poulose <suzuki@in.ibm.com>
+ *
+ *  - Based on ppc64 code - reloc_64.S
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#include <asm/ppc_asm.h>
+/* Dynamic section table entry tags */
+DT_RELA = 7                     /* Tag for Elf32_Rela section */
+DT_RELASZ = 8                   /* Size of the Rela relocs */
+DT_RELAENT = 9                  /* Size of one Rela reloc entry */
+STN_UNDEF = 0                   /* Undefined symbol index */
+STB_LOCAL = 0                   /* Local binding for the symbol */
+R_PPC_ADDR16_LO = 4             /* Lower half of (S+A) */
+R_PPC_ADDR16_HI = 5             /* Upper half of (S+A) */
+R_PPC_ADDR16_HA = 6             /* High Adjusted (S+A) */
+R_PPC_RELATIVE = 22
+/*
+ * r3 = desired final address
+ */
+_GLOBAL(relocate)
+        mflr    r0              /* Save our LR */
+        bl      0f              /* Find our current runtime address */
+0:      mflr    r12             /* Make it accessible */
+        mtlr    r0
+        lwz     r11, (p_dyn - 0b)(r12)
+        add     r11, r11, r12   /* runtime address of .dynamic section */
+        lwz     r9, (p_rela - 0b)(r12)
+        add     r9, r9, r12     /* runtime address of .rela.dyn section */
+        lwz     r10, (p_st - 0b)(r12)
+        add     r10, r10, r12   /* runtime address of _stext section */
+        lwz     r13, (p_sym - 0b)(r12)
+        add     r13, r13, r12   /* runtime address of .dynsym section */
+        /*
+         * Scan the dynamic section for RELA, RELASZ entries
+         */
+        li      r6, 0
+        li      r7, 0
+        li      r8, 0
+1:      lwz     r5, 0(r11)      /* ELF_Dyn.d_tag */
+        cmpwi   r5, 0           /* End of ELF_Dyn[] */
+        beq     eodyn
+        cmpwi   r5, DT_RELA
+        bne     relasz
+        lwz     r7, 4(r11)      /* r7 = rela.link */
+        b       skip
+relasz:
+        cmpwi   r5, DT_RELASZ
+        bne     relaent
+        lwz     r8, 4(r11)      /* r8 = Total Rela relocs size */
+        b       skip
+relaent:
+        cmpwi   r5, DT_RELAENT
+        bne     skip
+        lwz     r6, 4(r11)      /* r6 = Size of one Rela reloc */
+skip:
+        addi    r11, r11, 8
+        b       1b
+eodyn:                          /* End of Dyn Table scan */
+        /* Check if we have found all the entries */
+        cmpwi   r7, 0
+        beq     done
+        cmpwi   r8, 0
+        beq     done
+        cmpwi   r6, 0
+        beq     done
+        /*
+         * Work out the current offset from the link time address of .rela
+         * section.
+         *  cur_offset[r7] = rela.run[r9] - rela.link [r7]
+         *  _stext.link[r12] = _stext.run[r10] - cur_offset[r7]
+         *  final_offset[r3] = _stext.final[r3] - _stext.link[r12]
+         */
+        subf    r7, r7, r9      /* cur_offset */
+        subf    r12, r7, r10
+        subf    r3, r12, r3     /* final_offset */
+        subf    r8, r6, r8      /* relaz -= relaent */
+        /*
+         * Scan through the .rela table and process each entry
+         * r9   - points to the current .rela table entry
+         * r13  - points to the symbol table
+         */
+        /*
+         * Check if we have a relocation based on symbol
+         * r5 will hold the value of the symbol.
+         */
+applyrela:
+        lwz     r4, 4(r9)               /* r4 = rela.r_info */
+        srwi    r5, r4, 8               /* ELF32_R_SYM(r_info) */
+        cmpwi   r5, STN_UNDEF   /* sym == STN_UNDEF ? */
+        beq     get_type        /* value = 0 */
+        /* Find the value of the symbol at index(r5) */
+        slwi    r5, r5, 4               /* r5 = r5 * sizeof(Elf32_Sym) */
+        add     r12, r13, r5    /* r12 = &__dyn_sym[Index] */
+        /*
+         * GNU ld has a bug, where dynamic relocs based on
+         * STB_LOCAL symbols, the value should be assumed
+         * to be zero. - Alan Modra
+         */
+        /* XXX: Do we need to check if we are using GNU ld ? */
+        lbz     r5, 12(r12)     /* r5 = dyn_sym[Index].st_info */
+        extrwi  r5, r5, 4, 24   /* r5 = ELF32_ST_BIND(r5) */
+        cmpwi   r5, STB_LOCAL   /* st_value = 0, ld bug */
+        beq     get_type        /* We have r5 = 0 */
+        lwz     r5, 4(r12)      /* r5 = __dyn_sym[Index].st_value */
+get_type:
+        /* Load the relocation type to r4 */
+        extrwi  r4, r4, 8, 24   /* r4 = ELF32_R_TYPE(r_info) = ((char*)r4)[3] */
+        /* R_PPC_RELATIVE */
+        cmpwi   r4, R_PPC_RELATIVE
+        bne     hi16
+        lwz     r4, 0(r9)       /* r_offset */
+        lwz     r0, 8(r9)       /* r_addend */
+        add     r0, r0, r3      /* final addend */
+        stwx    r0, r4, r7      /* memory[r4+r7]) = (u32)r0 */
+        b       nxtrela         /* continue */
+        /* R_PPC_ADDR16_HI */
+hi16:
+        cmpwi   r4, R_PPC_ADDR16_HI
+        bne     ha16
+        lwz     r4, 0(r9)       /* r_offset */
+        lwz     r0, 8(r9)       /* r_addend */
+        add     r0, r0, r3
+        add     r0, r0, r5      /* r0 = (S+A+Offset) */
+        extrwi  r0, r0, 16, 0   /* r0 = (r0 >> 16) */
+        b       store_half
+        /* R_PPC_ADDR16_HA */
+ha16:
+        cmpwi   r4, R_PPC_ADDR16_HA
+        bne     lo16
+        lwz     r4, 0(r9)       /* r_offset */
+        lwz     r0, 8(r9)       /* r_addend */
+        add     r0, r0, r3
+        add     r0, r0, r5      /* r0 = (S+A+Offset) */
+        extrwi  r5, r0, 1, 16   /* Extract bit 16 */
+        extrwi  r0, r0, 16, 0   /* r0 = (r0 >> 16) */
+        add     r0, r0, r5      /* Add it to r0 */
+        b       store_half
+        /* R_PPC_ADDR16_LO */
+lo16:
+        cmpwi   r4, R_PPC_ADDR16_LO
+        bne     nxtrela
+        lwz     r4, 0(r9)       /* r_offset */
+        lwz     r0, 8(r9)       /* r_addend */
+        add     r0, r0, r3
+        add     r0, r0, r5      /* r0 = (S+A+Offset) */
+        extrwi  r0, r0, 16, 16  /* r0 &= 0xffff */
+        /* Fall through to */
+        /* Store half word */
+store_half:
+        sthx    r0, r4, r7      /* memory[r4+r7] = (u16)r0 */
+nxtrela:
+        /*
+         * We have to flush the modified instructions to the
+         * main storage from the d-cache. And also, invalidate the
+         * cached instructions in i-cache which has been modified.
+         *
+         * We delay the sync / isync operation till the end, since
+         * we won't be executing the modified instructions until
+         * we return from here.
+         */
+        dcbst   r4,r7
+        sync                    /* Ensure the data is flushed before icbi */
+        icbi    r4,r7
+        cmpwi   r8, 0           /* relasz = 0 ? */
+        ble     done
+        add     r9, r9, r6      /* move to next entry in the .rela table */
+        subf    r8, r6, r8      /* relasz -= relaent */
+        b       applyrela
+done:
+        sync                    /* Wait for the flush to finish */
+        isync                   /* Discard prefetched instructions */
+        blr
+p_dyn:          .long   __dynamic_start - 0b
+p_rela:         .long   __rela_dyn_start - 0b
+p_sym:          .long   __dynamic_symtab - 0b
+p_st:           .long   _stext - 0b
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index e037c7494fd8..4174b4b23246 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -568,6 +568,12 @@ static void rtas_flash_firmware(int reboot_type)
        }
        /*
+         * Just before starting the firmware flash, cancel the event scan work
+         * to avoid any soft lockup issues.
+         */
+        rtas_cancel_event_scan();
+        /*
         * NOTE: the "first" block must be under 4GB, so we create
         * an entry with no data blocks in the reserved buffer in
         * the kernel data segment.
diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c
index 481ef064c8f1..1045ff49cc6d 100644
--- a/arch/powerpc/kernel/rtasd.c
+++ b/arch/powerpc/kernel/rtasd.c
@@ -472,6 +472,13 @@ static void start_event_scan(void)
                                 &event_scan_work, event_scan_delay);
 }
+/* Cancel the rtas event scan work */
+void rtas_cancel_event_scan(void)
+{
+        cancel_delayed_work_sync(&event_scan_work);
+}
+EXPORT_SYMBOL_GPL(rtas_cancel_event_scan);
 static int __init rtas_init(void)
 {
        struct proc_dir_entry *entry;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index fb9bb46e7e88..4cb8f1e9d044 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -35,6 +35,8 @@
 #include <linux/pci.h>
 #include <linux/lockdep.h>
 #include <linux/memblock.h>
+#include <linux/hugetlb.h>
 #include <asm/io.h>
 #include <asm/kdump.h>
 #include <asm/prom.h>
@@ -64,6 +66,7 @@
 #include <asm/mmu_context.h>
 #include <asm/code-patching.h>
 #include <asm/kvm_ppc.h>
+#include <asm/hugetlb.h>
 #include "setup.h"
@@ -217,6 +220,13 @@ void __init early_setup(unsigned long dt_ptr)
        /* Initialize the hash table or TLB handling */
        early_init_mmu();
+        /*
+         * Reserve any gigantic pages requested on the command line.
+         * memblock needs to have been initialized by the time this is
+         * called since this will reserve memory.
+         */
+        reserve_hugetlb_gpages();
        DBG(" <- early_setup()\n");
 }
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 6df70907d60a..f0abe92f63f2 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -187,7 +187,8 @@ int smp_request_message_ipi(int virq, int msg)
                return 1;
        }
 #endif
-        err = request_irq(virq, smp_ipi_action[msg], IRQF_PERCPU,
+        err = request_irq(virq, smp_ipi_action[msg],
+                          IRQF_PERCPU | IRQF_NO_THREAD,
                          smp_ipi_name[msg], 0);
        WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
                virq, smp_ipi_name[msg], err);
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index ce035c1905f0..6fdf5ffe8c44 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -18,6 +18,7 @@
 #include <asm/machdep.h>
 #include <asm/smp.h>
 #include <asm/pmc.h>
+#include <asm/system.h>
 #include "cacheinfo.h"
@@ -51,6 +52,7 @@ static ssize_t store_smt_snooze_delay(struct sys_device *dev,
                return -EINVAL;
        per_cpu(smt_snooze_delay, cpu->sysdev.id) = snooze;
+        update_smt_snooze_delay(snooze);
        return count;
 }
@@ -177,11 +179,13 @@ SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 SYSFS_PMCSETUP(purr, SPRN_PURR);
 SYSFS_PMCSETUP(spurr, SPRN_SPURR);
 SYSFS_PMCSETUP(dscr, SPRN_DSCR);
+SYSFS_PMCSETUP(pir, SPRN_PIR);
 static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 static SYSDEV_ATTR(spurr, 0600, show_spurr, NULL);
 static SYSDEV_ATTR(dscr, 0600, show_dscr, store_dscr);
 static SYSDEV_ATTR(purr, 0600, show_purr, store_purr);
+static SYSDEV_ATTR(pir, 0400, show_pir, NULL);
 unsigned long dscr_default = 0;
 EXPORT_SYMBOL(dscr_default);
@@ -392,6 +396,9 @@ static void __cpuinit register_cpu_online(unsigned int cpu)
        if (cpu_has_feature(CPU_FTR_DSCR))
                sysdev_create_file(s, &attr_dscr);
+        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
+                sysdev_create_file(s, &attr_pir);
 #endif /* CONFIG_PPC64 */
        cacheinfo_cpu_online(cpu);
@@ -462,6 +469,9 @@ static void unregister_cpu_online(unsigned int cpu)
        if (cpu_has_feature(CPU_FTR_DSCR))
                sysdev_remove_file(s, &attr_dscr);
+        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
+                sysdev_remove_file(s, &attr_pir);
 #endif /* CONFIG_PPC64 */
        cacheinfo_cpu_offline(cpu);
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 522bb1dfc353..567dd7c3ac2a 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -86,8 +86,6 @@ static struct clocksource clocksource_rtc = {
        .rating       = 400,
        .flags        = CLOCK_SOURCE_IS_CONTINUOUS,
        .mask         = CLOCKSOURCE_MASK(64),
-        .shift        = 22,
-        .mult         = 0,      /* To be filled in */
        .read         = rtc_read,
 };
@@ -97,8 +95,6 @@ static struct clocksource clocksource_timebase = {
        .rating       = 400,
        .flags        = CLOCK_SOURCE_IS_CONTINUOUS,
        .mask         = CLOCKSOURCE_MASK(64),
-        .shift        = 22,
-        .mult         = 0,      /* To be filled in */
        .read         = timebase_read,
 };
@@ -110,22 +106,16 @@ static void decrementer_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *dev);
 static struct clock_event_device decrementer_clockevent = {
-       .name           = "decrementer",
+        .name           = "decrementer",
-       .rating         = 200,
+        .rating         = 200,
-       .shift          = 0,     /* To be filled in */
+        .irq            = 0,
-       .mult           = 0,     /* To be filled in */
+        .set_next_event = decrementer_set_next_event,
-       .irq            = 0,
+        .set_mode       = decrementer_set_mode,
-       .set_next_event = decrementer_set_next_event,
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
-       .set_mode       = decrementer_set_mode,
-       .features       = CLOCK_EVT_FEAT_ONESHOT,
 };
-struct decrementer_clock {
+DEFINE_PER_CPU(u64, decrementers_next_tb);
-        struct clock_event_device event;
+static DEFINE_PER_CPU(struct clock_event_device, decrementers);
-        u64 next_tb;
-};
-static DEFINE_PER_CPU(struct decrementer_clock, decrementers);
 #ifdef CONFIG_PPC_ISERIES
 static unsigned long __initdata iSeries_recal_titan;
@@ -168,13 +158,13 @@ EXPORT_SYMBOL_GPL(ppc_tb_freq);
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 /*
 * Factors for converting from cputime_t (timebase ticks) to
- * jiffies, milliseconds, seconds, and clock_t (1/USER_HZ seconds).
+ * jiffies, microseconds, seconds, and clock_t (1/USER_HZ seconds).
 * These are all stored as 0.64 fixed-point binary fractions.
 */
 u64 __cputime_jiffies_factor;
 EXPORT_SYMBOL(__cputime_jiffies_factor);
-u64 __cputime_msec_factor;
+u64 __cputime_usec_factor;
-EXPORT_SYMBOL(__cputime_msec_factor);
+EXPORT_SYMBOL(__cputime_usec_factor);
 u64 __cputime_sec_factor;
 EXPORT_SYMBOL(__cputime_sec_factor);
 u64 __cputime_clockt_factor;
@@ -192,8 +182,8 @@ static void calc_cputime_factors(void)
        div128_by_32(HZ, 0, tb_ticks_per_sec, &res);
        __cputime_jiffies_factor = res.result_low;
-        div128_by_32(1000, 0, tb_ticks_per_sec, &res);
+        div128_by_32(1000000, 0, tb_ticks_per_sec, &res);
-        __cputime_msec_factor = res.result_low;
+        __cputime_usec_factor = res.result_low;
        div128_by_32(1, 0, tb_ticks_per_sec, &res);
        __cputime_sec_factor = res.result_low;
        div128_by_32(USER_HZ, 0, tb_ticks_per_sec, &res);
@@ -441,7 +431,7 @@ EXPORT_SYMBOL(profile_pc);
 /* 
 * This function recalibrates the timebase based on the 49-bit time-of-day
 * value in the Titan chip.  The Titan is much more accurate than the value
- * returned by the service processor for the timebase frequency.  
+ * returned by the service processor for the timebase frequency.
 */
 static int __init iSeries_tb_recal(void)
@@ -576,9 +566,8 @@ void arch_irq_work_raise(void)
 void timer_interrupt(struct pt_regs * regs)
 {
        struct pt_regs *old_regs;
-        struct decrementer_clock *decrementer =  &__get_cpu_var(decrementers);
+        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
-        struct clock_event_device *evt = &decrementer->event;
+        struct clock_event_device *evt = &__get_cpu_var(decrementers);
-        u64 now;
        /* Ensure a positive value is written to the decrementer, or else
         * some CPUs will continue to take decrementer exceptions.
@@ -613,16 +602,9 @@ void timer_interrupt(struct pt_regs * regs)
                get_lppaca()->int_dword.fields.decr_int = 0;
 #endif
-        now = get_tb_or_rtc();
+        *next_tb = ~(u64)0;
-        if (now >= decrementer->next_tb) {
+        if (evt->event_handler)
-                decrementer->next_tb = ~(u64)0;
+                evt->event_handler(evt);
-                if (evt->event_handler)
-                        evt->event_handler(evt);
-        } else {
-                now = decrementer->next_tb - now;
-                if (now <= DECREMENTER_MAX)
-                        set_dec((int)now);
-        }
 #ifdef CONFIG_PPC_ISERIES
        if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending())
@@ -650,9 +632,9 @@ static void generic_suspend_disable_irqs(void)
         * with suspending.
         */
-        set_dec(0x7fffffff);
+        set_dec(DECREMENTER_MAX);
        local_irq_disable();
-        set_dec(0x7fffffff);
+        set_dec(DECREMENTER_MAX);
 }
 static void generic_suspend_enable_irqs(void)
@@ -824,9 +806,8 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
        ++vdso_data->tb_update_count;
        smp_mb();
-        /* XXX this assumes clock->shift == 22 */
+        /* 19342813113834067 ~= 2^(20+64) / 1e9 */
-        /* 4611686018 ~= 2^(20+64-22) / 1e9 */
+        new_tb_to_xs = (u64) mult * (19342813113834067ULL >> clock->shift);
-        new_tb_to_xs = (u64) mult * 4611686018ULL;
        new_stamp_xsec = (u64) wall_time->tv_nsec * XSEC_PER_SEC;
        do_div(new_stamp_xsec, 1000000000);
        new_stamp_xsec += (u64) wall_time->tv_sec * XSEC_PER_SEC;
@@ -877,9 +858,7 @@ static void __init clocksource_init(void)
        else
                clock = &clocksource_timebase;
-        clock->mult = clocksource_hz2mult(tb_ticks_per_sec, clock->shift);
+        if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
-        if (clocksource_register(clock)) {
                printk(KERN_ERR "clocksource: %s is already registered\n",
                       clock->name);
                return;
@@ -892,7 +871,7 @@ static void __init clocksource_init(void)
 static int decrementer_set_next_event(unsigned long evt,
                                      struct clock_event_device *dev)
 {
-        __get_cpu_var(decrementers).next_tb = get_tb_or_rtc() + evt;
+        __get_cpu_var(decrementers_next_tb) = get_tb_or_rtc() + evt;
        set_dec(evt);
        return 0;
 }
@@ -904,34 +883,9 @@ static void decrementer_set_mode(enum clock_event_mode mode,
                decrementer_set_next_event(DECREMENTER_MAX, dev);
 }
-static inline uint64_t div_sc64(unsigned long ticks, unsigned long nsec,
-                                int shift)
-{
-        uint64_t tmp = ((uint64_t)ticks) << shift;
-        do_div(tmp, nsec);
-        return tmp;
-}
-static void __init setup_clockevent_multiplier(unsigned long hz)
-{
-        u64 mult, shift = 32;
-        while (1) {
-                mult = div_sc64(hz, NSEC_PER_SEC, shift);
-                if (mult && (mult >> 32UL) == 0UL)
-                        break;
-                shift--;
-        }
-        decrementer_clockevent.shift = shift;
-        decrementer_clockevent.mult = mult;
-}
 static void register_decrementer_clockevent(int cpu)
 {
-        struct clock_event_device *dec = &per_cpu(decrementers, cpu).event;
+        struct clock_event_device *dec = &per_cpu(decrementers, cpu);
        *dec = decrementer_clockevent;
        dec->cpumask = cpumask_of(cpu);
@@ -946,7 +900,8 @@ static void __init init_decrementer_clockevent(void)
 {
        int cpu = smp_processor_id();
-        setup_clockevent_multiplier(ppc_tb_freq);
+        clockevents_calc_mult_shift(&decrementer_clockevent, ppc_tb_freq, 4);
        decrementer_clockevent.max_delta_ns =
                clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent);
        decrementer_clockevent.min_delta_ns =
@@ -1014,10 +969,10 @@ void __init time_init(void)
        boot_tb = get_tb_or_rtc();
        /* If platform provided a timezone (pmac), we correct the time */
-        if (timezone_offset) {
+        if (timezone_offset) {
                sys_tz.tz_minuteswest = -timezone_offset / 60;
                sys_tz.tz_dsttime = 0;
-        }
+        }
        vdso_data->tb_update_count = 0;
        vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5459d148a0f6..c091527efd89 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -98,18 +98,14 @@ static void pmac_backlight_unblank(void)
 static inline void pmac_backlight_unblank(void) { }
 #endif
-int die(const char *str, struct pt_regs *regs, long err)
+static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int die_owner = -1;
+static unsigned int die_nest_count;
+static int die_counter;
+static unsigned __kprobes long oops_begin(struct pt_regs *regs)
 {
-        static struct {
+        int cpu;
-                raw_spinlock_t lock;
-                u32 lock_owner;
-                int lock_owner_depth;
-        } die = {
-                .lock =                 __RAW_SPIN_LOCK_UNLOCKED(die.lock),
-                .lock_owner =           -1,
-                .lock_owner_depth =     0
-        };
-        static int die_counter;
        unsigned long flags;
        if (debugger(regs))
@@ -117,66 +113,109 @@ int die(const char *str, struct pt_regs *regs, long err)
        oops_enter();
-        if (die.lock_owner != raw_smp_processor_id()) {
+        /* racy, but better than risking deadlock. */
-                console_verbose();
+        raw_local_irq_save(flags);
-                raw_spin_lock_irqsave(&die.lock, flags);
+        cpu = smp_processor_id();
-                die.lock_owner = smp_processor_id();
+        if (!arch_spin_trylock(&die_lock)) {
-                die.lock_owner_depth = 0;
+                if (cpu == die_owner)
-                bust_spinlocks(1);
+                        /* nested oops. should stop eventually */;
-                if (machine_is(powermac))
+                else
-                        pmac_backlight_unblank();
+                        arch_spin_lock(&die_lock);
-        } else {
-                local_save_flags(flags);
        }
+        die_nest_count++;
+        die_owner = cpu;
+        console_verbose();
+        bust_spinlocks(1);
+        if (machine_is(powermac))
+                pmac_backlight_unblank();
+        return flags;
+}
-        if (++die.lock_owner_depth < 3) {
+static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
-                printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
+                               int signr)
-#ifdef CONFIG_PREEMPT
+{
-                printk("PREEMPT ");
+        bust_spinlocks(0);
-#endif
+        die_owner = -1;
-#ifdef CONFIG_SMP
+        add_taint(TAINT_DIE);
-                printk("SMP NR_CPUS=%d ", NR_CPUS);
+        die_nest_count--;
-#endif
+        oops_exit();
-#ifdef CONFIG_DEBUG_PAGEALLOC
+        printk("\n");
-                printk("DEBUG_PAGEALLOC ");
+        if (!die_nest_count)
-#endif
+                /* Nest count reaches zero, release the lock. */
-#ifdef CONFIG_NUMA
+                arch_spin_unlock(&die_lock);
-                printk("NUMA ");
+        raw_local_irq_restore(flags);
-#endif
-                printk("%s\n", ppc_md.name ? ppc_md.name : "");
-                if (notify_die(DIE_OOPS, str, regs, err, 255,
+        /*
-                               SIGSEGV) == NOTIFY_STOP)
+         * A system reset (0x100) is a request to dump, so we always send
-                        return 1;
+         * it through the crashdump code.
+         */
+        if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
+                crash_kexec(regs);
-                print_modules();
+                /*
-                show_regs(regs);
+                 * We aren't the primary crash CPU. We need to send it
-        } else {
+                 * to a holding pattern to avoid it ending up in the panic
-                printk("Recursive die() failure, output suppressed\n");
+                 * code.
+                 */
+                crash_kexec_secondary(regs);
        }
-        bust_spinlocks(0);
+        if (!signr)
-        die.lock_owner = -1;
+                return;
-        add_taint(TAINT_DIE);
-        raw_spin_unlock_irqrestore(&die.lock, flags);
-        if (kexec_should_crash(current) ||
+        /*
-                kexec_sr_activated(smp_processor_id()))
+         * While our oops output is serialised by a spinlock, output
-                crash_kexec(regs);
+         * from panic() called below can race and corrupt it. If we
-        crash_kexec_secondary(regs);
+         * know we are going to panic, delay for 1 second so we have a
+         * chance to get clean backtraces from all CPUs that are oopsing.
+         */
+        if (in_interrupt() || panic_on_oops || !current->pid ||
+            is_global_init(current)) {
+                mdelay(MSEC_PER_SEC);
+        }
        if (in_interrupt())
                panic("Fatal exception in interrupt");
        if (panic_on_oops)
                panic("Fatal exception");
+        do_exit(signr);
+}
-        oops_exit();
+static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
-        do_exit(err);
+{
+        printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
+#ifdef CONFIG_PREEMPT
+        printk("PREEMPT ");
+#endif
+#ifdef CONFIG_SMP
+        printk("SMP NR_CPUS=%d ", NR_CPUS);
+#endif
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        printk("DEBUG_PAGEALLOC ");
+#endif
+#ifdef CONFIG_NUMA
+        printk("NUMA ");
+#endif
+        printk("%s\n", ppc_md.name ? ppc_md.name : "");
+        if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
+                return 1;
+        print_modules();
+        show_regs(regs);
        return 0;
 }
+void die(const char *str, struct pt_regs *regs, long err)
+{
+        unsigned long flags = oops_begin(regs);
+        if (__die(str, regs, err))
+                err = 0;
+        oops_end(flags, regs, err);
+}
 void user_single_step_siginfo(struct task_struct *tsk,
                                struct pt_regs *regs, siginfo_t *info)
 {
@@ -195,10 +234,11 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
                        "at %016lx nip %016lx lr %016lx code %x\n";
        if (!user_mode(regs)) {
-                if (die("Exception in kernel mode", regs, signr))
+                die("Exception in kernel mode", regs, signr);
-                        return;
+                return;
-        } else if (show_unhandled_signals &&
+        }
-                   unhandled_signal(current, signr)) {
+        if (show_unhandled_signals && unhandled_signal(current, signr)) {
                printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
                                   current->comm, current->pid, signr,
                                   addr, regs->nip, regs->link, code);
@@ -220,25 +260,8 @@ void system_reset_exception(struct pt_regs *regs)
                        return;
        }
-#ifdef CONFIG_KEXEC
-        cpumask_set_cpu(smp_processor_id(), &cpus_in_sr);
-#endif
        die("System Reset", regs, SIGABRT);
-        /*
-         * Some CPUs when released from the debugger will execute this path.
-         * These CPUs entered the debugger via a soft-reset. If the CPU was
-         * hung before entering the debugger it will return to the hung
-         * state when exiting this function.  This causes a problem in
-         * kdump since the hung CPU(s) will not respond to the IPI sent
-         * from kdump. To prevent the problem we call crash_kexec_secondary()
-         * here. If a kdump had not been initiated or we exit the debugger
-         * with the "exit and recover" command (x) crash_kexec_secondary()
-         * will return after 5ms and the CPU returns to its previous state.
-         */
-        crash_kexec_secondary(regs);
        /* Must die if the interrupt is not recoverable */
        if (!(regs->msr & MSR_RI))
                panic("Unrecoverable System Reset");
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 920276c0f6a1..710a54005dfb 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -170,7 +170,13 @@ SECTIONS
        }
 #ifdef CONFIG_RELOCATABLE
        . = ALIGN(8);
-        .dynsym : AT(ADDR(.dynsym) - LOAD_OFFSET) { *(.dynsym) }
+        .dynsym : AT(ADDR(.dynsym) - LOAD_OFFSET)
+        {
+#ifdef CONFIG_RELOCATABLE_PPC32
+                __dynamic_symtab = .;
+#endif
+                *(.dynsym)
+        }
        .dynstr : AT(ADDR(.dynstr) - LOAD_OFFSET) { *(.dynstr) }
        .dynamic : AT(ADDR(.dynamic) - LOAD_OFFSET)
        {
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 44d8829334ab..5c8b26183f50 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -112,6 +112,9 @@ kvm_start_guest:
        stbcix  r0, r5, r6              /* clear it */
        stwcix  r8, r5, r7              /* EOI it */
+        /* NV GPR values from power7_idle() will no longer be valid */
+        stb     r0, PACA_NAPSTATELOST(r13)
 .global kvmppc_hv_entry
 kvmppc_hv_entry:
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 166a6a0ad544..7735a2c2e6d9 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -16,13 +16,15 @@ obj-$(CONFIG_HAS_IOMEM)	+= devres.o
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                           memcpy_64.o usercopy_64.o mem_64.o string.o \
-                           checksum_wrappers_64.o hweight_64.o
+                           checksum_wrappers_64.o hweight_64.o \
+                           copyuser_power7.o
 obj-$(CONFIG_XMON)      += sstep.o ldstfp.o
 obj-$(CONFIG_KPROBES)   += sstep.o ldstfp.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += sstep.o ldstfp.o
 ifeq ($(CONFIG_PPC64),y)
 obj-$(CONFIG_SMP)       += locks.o
+obj-$(CONFIG_ALTIVEC)   += copyuser_power7_vmx.o
 endif
 obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 578b625d6a3c..773d38f90aaa 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -11,6 +11,12 @@
        .align  7
 _GLOBAL(__copy_tofrom_user)
+BEGIN_FTR_SECTION
+        nop
+FTR_SECTION_ELSE
+        b       __copy_tofrom_user_power7
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
+_GLOBAL(__copy_tofrom_user_base)
        /* first check for a whole page copy on a page boundary */
        cmpldi  cr1,r5,16
        cmpdi   cr6,r5,4096
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
new file mode 100644
index 000000000000..497db7b23bb1
--- /dev/null
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -0,0 +1,683 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2011
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/ppc_asm.h>
+#define STACKFRAMESIZE  256
+#define STK_REG(i)      (112 + ((i)-14)*8)
+        .macro err1
+100:
+        .section __ex_table,"a"
+        .align 3
+        .llong 100b,.Ldo_err1
+        .previous
+        .endm
+        .macro err2
+200:
+        .section __ex_table,"a"
+        .align 3
+        .llong 200b,.Ldo_err2
+        .previous
+        .endm
+#ifdef CONFIG_ALTIVEC
+        .macro err3
+300:
+        .section __ex_table,"a"
+        .align 3
+        .llong 300b,.Ldo_err3
+        .previous
+        .endm
+        .macro err4
+400:
+        .section __ex_table,"a"
+        .align 3
+        .llong 400b,.Ldo_err4
+        .previous
+        .endm
+.Ldo_err4:
+        ld      r16,STK_REG(r16)(r1)
+        ld      r15,STK_REG(r15)(r1)
+        ld      r14,STK_REG(r14)(r1)
+.Ldo_err3:
+        bl      .exit_vmx_copy
+        ld      r0,STACKFRAMESIZE+16(r1)
+        mtlr    r0
+        b       .Lexit
+#endif /* CONFIG_ALTIVEC */
+.Ldo_err2:
+        ld      r22,STK_REG(r22)(r1)
+        ld      r21,STK_REG(r21)(r1)
+        ld      r20,STK_REG(r20)(r1)
+        ld      r19,STK_REG(r19)(r1)
+        ld      r18,STK_REG(r18)(r1)
+        ld      r17,STK_REG(r17)(r1)
+        ld      r16,STK_REG(r16)(r1)
+        ld      r15,STK_REG(r15)(r1)
+        ld      r14,STK_REG(r14)(r1)
+.Lexit:
+        addi    r1,r1,STACKFRAMESIZE
+.Ldo_err1:
+        ld      r3,48(r1)
+        ld      r4,56(r1)
+        ld      r5,64(r1)
+        b       __copy_tofrom_user_base
+_GLOBAL(__copy_tofrom_user_power7)
+#ifdef CONFIG_ALTIVEC
+        cmpldi  r5,16
+        cmpldi  cr1,r5,4096
+        std     r3,48(r1)
+        std     r4,56(r1)
+        std     r5,64(r1)
+        blt     .Lshort_copy
+        bgt     cr1,.Lvmx_copy
+#else
+        cmpldi  r5,16
+        std     r3,48(r1)
+        std     r4,56(r1)
+        std     r5,64(r1)
+        blt     .Lshort_copy
+#endif
+.Lnonvmx_copy:
+        /* Get the source 8B aligned */
+        neg     r6,r4
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-3)
+        bf      cr7*4+3,1f
+err1;   lbz     r0,0(r4)
+        addi    r4,r4,1
+err1;   stb     r0,0(r3)
+        addi    r3,r3,1
+1:      bf      cr7*4+2,2f
+err1;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err1;   sth     r0,0(r3)
+        addi    r3,r3,2
+2:      bf      cr7*4+1,3f
+err1;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err1;   stw     r0,0(r3)
+        addi    r3,r3,4
+3:      sub     r5,r5,r6
+        cmpldi  r5,128
+        blt     5f
+        mflr    r0
+        stdu    r1,-STACKFRAMESIZE(r1)
+        std     r14,STK_REG(r14)(r1)
+        std     r15,STK_REG(r15)(r1)
+        std     r16,STK_REG(r16)(r1)
+        std     r17,STK_REG(r17)(r1)
+        std     r18,STK_REG(r18)(r1)
+        std     r19,STK_REG(r19)(r1)
+        std     r20,STK_REG(r20)(r1)
+        std     r21,STK_REG(r21)(r1)
+        std     r22,STK_REG(r22)(r1)
+        std     r0,STACKFRAMESIZE+16(r1)
+        srdi    r6,r5,7
+        mtctr   r6
+        /* Now do cacheline (128B) sized loads and stores. */
+        .align  5
+4:
+err2;   ld      r0,0(r4)
+err2;   ld      r6,8(r4)
+err2;   ld      r7,16(r4)
+err2;   ld      r8,24(r4)
+err2;   ld      r9,32(r4)
+err2;   ld      r10,40(r4)
+err2;   ld      r11,48(r4)
+err2;   ld      r12,56(r4)
+err2;   ld      r14,64(r4)
+err2;   ld      r15,72(r4)
+err2;   ld      r16,80(r4)
+err2;   ld      r17,88(r4)
+err2;   ld      r18,96(r4)
+err2;   ld      r19,104(r4)
+err2;   ld      r20,112(r4)
+err2;   ld      r21,120(r4)
+        addi    r4,r4,128
+err2;   std     r0,0(r3)
+err2;   std     r6,8(r3)
+err2;   std     r7,16(r3)
+err2;   std     r8,24(r3)
+err2;   std     r9,32(r3)
+err2;   std     r10,40(r3)
+err2;   std     r11,48(r3)
+err2;   std     r12,56(r3)
+err2;   std     r14,64(r3)
+err2;   std     r15,72(r3)
+err2;   std     r16,80(r3)
+err2;   std     r17,88(r3)
+err2;   std     r18,96(r3)
+err2;   std     r19,104(r3)
+err2;   std     r20,112(r3)
+err2;   std     r21,120(r3)
+        addi    r3,r3,128
+        bdnz    4b
+        clrldi  r5,r5,(64-7)
+        ld      r14,STK_REG(r14)(r1)
+        ld      r15,STK_REG(r15)(r1)
+        ld      r16,STK_REG(r16)(r1)
+        ld      r17,STK_REG(r17)(r1)
+        ld      r18,STK_REG(r18)(r1)
+        ld      r19,STK_REG(r19)(r1)
+        ld      r20,STK_REG(r20)(r1)
+        ld      r21,STK_REG(r21)(r1)
+        ld      r22,STK_REG(r22)(r1)
+        addi    r1,r1,STACKFRAMESIZE
+        /* Up to 127B to go */
+5:      srdi    r6,r5,4
+        mtocrf  0x01,r6
+6:      bf      cr7*4+1,7f
+err1;   ld      r0,0(r4)
+err1;   ld      r6,8(r4)
+err1;   ld      r7,16(r4)
+err1;   ld      r8,24(r4)
+err1;   ld      r9,32(r4)
+err1;   ld      r10,40(r4)
+err1;   ld      r11,48(r4)
+err1;   ld      r12,56(r4)
+        addi    r4,r4,64
+err1;   std     r0,0(r3)
+err1;   std     r6,8(r3)
+err1;   std     r7,16(r3)
+err1;   std     r8,24(r3)
+err1;   std     r9,32(r3)
+err1;   std     r10,40(r3)
+err1;   std     r11,48(r3)
+err1;   std     r12,56(r3)
+        addi    r3,r3,64
+        /* Up to 63B to go */
+7:      bf      cr7*4+2,8f
+err1;   ld      r0,0(r4)
+err1;   ld      r6,8(r4)
+err1;   ld      r7,16(r4)
+err1;   ld      r8,24(r4)
+        addi    r4,r4,32
+err1;   std     r0,0(r3)
+err1;   std     r6,8(r3)
+err1;   std     r7,16(r3)
+err1;   std     r8,24(r3)
+        addi    r3,r3,32
+        /* Up to 31B to go */
+8:      bf      cr7*4+3,9f
+err1;   ld      r0,0(r4)
+err1;   ld      r6,8(r4)
+        addi    r4,r4,16
+err1;   std     r0,0(r3)
+err1;   std     r6,8(r3)
+        addi    r3,r3,16
+9:      clrldi  r5,r5,(64-4)
+        /* Up to 15B to go */
+.Lshort_copy:
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+err1;   lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+err1;   lwz     r6,4(r4)
+        addi    r4,r4,8
+err1;   stw     r0,0(r3)
+err1;   stw     r6,4(r3)
+        addi    r3,r3,8
+12:     bf      cr7*4+1,13f
+err1;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err1;   stw     r0,0(r3)
+        addi    r3,r3,4
+13:     bf      cr7*4+2,14f
+err1;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err1;   sth     r0,0(r3)
+        addi    r3,r3,2
+14:     bf      cr7*4+3,15f
+err1;   lbz     r0,0(r4)
+err1;   stb     r0,0(r3)
+15:     li      r3,0
+        blr
+.Lunwind_stack_nonvmx_copy:
+        addi    r1,r1,STACKFRAMESIZE
+        b       .Lnonvmx_copy
+#ifdef CONFIG_ALTIVEC
+.Lvmx_copy:
+        mflr    r0
+        std     r0,16(r1)
+        stdu    r1,-STACKFRAMESIZE(r1)
+        bl      .enter_vmx_copy
+        cmpwi   r3,0
+        ld      r0,STACKFRAMESIZE+16(r1)
+        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r4,STACKFRAMESIZE+56(r1)
+        ld      r5,STACKFRAMESIZE+64(r1)
+        mtlr    r0
+        beq     .Lunwind_stack_nonvmx_copy
+        /*
+         * If source and destination are not relatively aligned we use a
+         * slower permute loop.
+         */
+        xor     r6,r4,r3
+        rldicl. r6,r6,0,(64-4)
+        bne     .Lvmx_unaligned_copy
+        /* Get the destination 16B aligned */
+        neg     r6,r3
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-4)
+        bf      cr7*4+3,1f
+err3;   lbz     r0,0(r4)
+        addi    r4,r4,1
+err3;   stb     r0,0(r3)
+        addi    r3,r3,1
+1:      bf      cr7*4+2,2f
+err3;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err3;   sth     r0,0(r3)
+        addi    r3,r3,2
+2:      bf      cr7*4+1,3f
+err3;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err3;   stw     r0,0(r3)
+        addi    r3,r3,4
+3:      bf      cr7*4+0,4f
+err3;   ld      r0,0(r4)
+        addi    r4,r4,8
+err3;   std     r0,0(r3)
+        addi    r3,r3,8
+4:      sub     r5,r5,r6
+        /* Get the desination 128B aligned */
+        neg     r6,r3
+        srdi    r7,r6,4
+        mtocrf  0x01,r7
+        clrldi  r6,r6,(64-7)
+        li      r9,16
+        li      r10,32
+        li      r11,48
+        bf      cr7*4+3,5f
+err3;   lvx     vr1,r0,r4
+        addi    r4,r4,16
+err3;   stvx    vr1,r0,r3
+        addi    r3,r3,16
+5:      bf      cr7*4+2,6f
+err3;   lvx     vr1,r0,r4
+err3;   lvx     vr0,r4,r9
+        addi    r4,r4,32
+err3;   stvx    vr1,r0,r3
+err3;   stvx    vr0,r3,r9
+        addi    r3,r3,32
+6:      bf      cr7*4+1,7f
+err3;   lvx     vr3,r0,r4
+err3;   lvx     vr2,r4,r9
+err3;   lvx     vr1,r4,r10
+err3;   lvx     vr0,r4,r11
+        addi    r4,r4,64
+err3;   stvx    vr3,r0,r3
+err3;   stvx    vr2,r3,r9
+err3;   stvx    vr1,r3,r10
+err3;   stvx    vr0,r3,r11
+        addi    r3,r3,64
+7:      sub     r5,r5,r6
+        srdi    r6,r5,7
+        std     r14,STK_REG(r14)(r1)
+        std     r15,STK_REG(r15)(r1)
+        std     r16,STK_REG(r16)(r1)
+        li      r12,64
+        li      r14,80
+        li      r15,96
+        li      r16,112
+        mtctr   r6
+        /*
+         * Now do cacheline sized loads and stores. By this stage the
+         * cacheline stores are also cacheline aligned.
+         */
+        .align  5
+8:
+err4;   lvx     vr7,r0,r4
+err4;   lvx     vr6,r4,r9
+err4;   lvx     vr5,r4,r10
+err4;   lvx     vr4,r4,r11
+err4;   lvx     vr3,r4,r12
+err4;   lvx     vr2,r4,r14
+err4;   lvx     vr1,r4,r15
+err4;   lvx     vr0,r4,r16
+        addi    r4,r4,128
+err4;   stvx    vr7,r0,r3
+err4;   stvx    vr6,r3,r9
+err4;   stvx    vr5,r3,r10
+err4;   stvx    vr4,r3,r11
+err4;   stvx    vr3,r3,r12
+err4;   stvx    vr2,r3,r14
+err4;   stvx    vr1,r3,r15
+err4;   stvx    vr0,r3,r16
+        addi    r3,r3,128
+        bdnz    8b
+        ld      r14,STK_REG(r14)(r1)
+        ld      r15,STK_REG(r15)(r1)
+        ld      r16,STK_REG(r16)(r1)
+        /* Up to 127B to go */
+        clrldi  r5,r5,(64-7)
+        srdi    r6,r5,4
+        mtocrf  0x01,r6
+        bf      cr7*4+1,9f
+err3;   lvx     vr3,r0,r4
+err3;   lvx     vr2,r4,r9
+err3;   lvx     vr1,r4,r10
+err3;   lvx     vr0,r4,r11
+        addi    r4,r4,64
+err3;   stvx    vr3,r0,r3
+err3;   stvx    vr2,r3,r9
+err3;   stvx    vr1,r3,r10
+err3;   stvx    vr0,r3,r11
+        addi    r3,r3,64
+9:      bf      cr7*4+2,10f
+err3;   lvx     vr1,r0,r4
+err3;   lvx     vr0,r4,r9
+        addi    r4,r4,32
+err3;   stvx    vr1,r0,r3
+err3;   stvx    vr0,r3,r9
+        addi    r3,r3,32
+10:     bf      cr7*4+3,11f
+err3;   lvx     vr1,r0,r4
+        addi    r4,r4,16
+err3;   stvx    vr1,r0,r3
+        addi    r3,r3,16
+        /* Up to 15B to go */
+11:     clrldi  r5,r5,(64-4)
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+err3;   ld      r0,0(r4)
+        addi    r4,r4,8
+err3;   std     r0,0(r3)
+        addi    r3,r3,8
+12:     bf      cr7*4+1,13f
+err3;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err3;   stw     r0,0(r3)
+        addi    r3,r3,4
+13:     bf      cr7*4+2,14f
+err3;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err3;   sth     r0,0(r3)
+        addi    r3,r3,2
+14:     bf      cr7*4+3,15f
+err3;   lbz     r0,0(r4)
+err3;   stb     r0,0(r3)
+15:     addi    r1,r1,STACKFRAMESIZE
+        b       .exit_vmx_copy          /* tail call optimise */
+.Lvmx_unaligned_copy:
+        /* Get the destination 16B aligned */
+        neg     r6,r3
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-4)
+        bf      cr7*4+3,1f
+err3;   lbz     r0,0(r4)
+        addi    r4,r4,1
+err3;   stb     r0,0(r3)
+        addi    r3,r3,1
+1:      bf      cr7*4+2,2f
+err3;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err3;   sth     r0,0(r3)
+        addi    r3,r3,2
+2:      bf      cr7*4+1,3f
+err3;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err3;   stw     r0,0(r3)
+        addi    r3,r3,4
+3:      bf      cr7*4+0,4f
+err3;   lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+err3;   lwz     r7,4(r4)
+        addi    r4,r4,8
+err3;   stw     r0,0(r3)
+err3;   stw     r7,4(r3)
+        addi    r3,r3,8
+4:      sub     r5,r5,r6
+        /* Get the desination 128B aligned */
+        neg     r6,r3
+        srdi    r7,r6,4
+        mtocrf  0x01,r7
+        clrldi  r6,r6,(64-7)
+        li      r9,16
+        li      r10,32
+        li      r11,48
+        lvsl    vr16,0,r4       /* Setup permute control vector */
+err3;   lvx     vr0,0,r4
+        addi    r4,r4,16
+        bf      cr7*4+3,5f
+err3;   lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        addi    r4,r4,16
+err3;   stvx    vr8,r0,r3
+        addi    r3,r3,16
+        vor     vr0,vr1,vr1
+5:      bf      cr7*4+2,6f
+err3;   lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+err3;   lvx     vr0,r4,r9
+        vperm   vr9,vr1,vr0,vr16
+        addi    r4,r4,32
+err3;   stvx    vr8,r0,r3
+err3;   stvx    vr9,r3,r9
+        addi    r3,r3,32
+6:      bf      cr7*4+1,7f
+err3;   lvx     vr3,r0,r4
+        vperm   vr8,vr0,vr3,vr16
+err3;   lvx     vr2,r4,r9
+        vperm   vr9,vr3,vr2,vr16
+err3;   lvx     vr1,r4,r10
+        vperm   vr10,vr2,vr1,vr16
+err3;   lvx     vr0,r4,r11
+        vperm   vr11,vr1,vr0,vr16
+        addi    r4,r4,64
+err3;   stvx    vr8,r0,r3
+err3;   stvx    vr9,r3,r9
+err3;   stvx    vr10,r3,r10
+err3;   stvx    vr11,r3,r11
+        addi    r3,r3,64
+7:      sub     r5,r5,r6
+        srdi    r6,r5,7
+        std     r14,STK_REG(r14)(r1)
+        std     r15,STK_REG(r15)(r1)
+        std     r16,STK_REG(r16)(r1)
+        li      r12,64
+        li      r14,80
+        li      r15,96
+        li      r16,112
+        mtctr   r6
+        /*
+         * Now do cacheline sized loads and stores. By this stage the
+         * cacheline stores are also cacheline aligned.
+         */
+        .align  5
+8:
+err4;   lvx     vr7,r0,r4
+        vperm   vr8,vr0,vr7,vr16
+err4;   lvx     vr6,r4,r9
+        vperm   vr9,vr7,vr6,vr16
+err4;   lvx     vr5,r4,r10
+        vperm   vr10,vr6,vr5,vr16
+err4;   lvx     vr4,r4,r11
+        vperm   vr11,vr5,vr4,vr16
+err4;   lvx     vr3,r4,r12
+        vperm   vr12,vr4,vr3,vr16
+err4;   lvx     vr2,r4,r14
+        vperm   vr13,vr3,vr2,vr16
+err4;   lvx     vr1,r4,r15
+        vperm   vr14,vr2,vr1,vr16
+err4;   lvx     vr0,r4,r16
+        vperm   vr15,vr1,vr0,vr16
+        addi    r4,r4,128
+err4;   stvx    vr8,r0,r3
+err4;   stvx    vr9,r3,r9
+err4;   stvx    vr10,r3,r10
+err4;   stvx    vr11,r3,r11
+err4;   stvx    vr12,r3,r12
+err4;   stvx    vr13,r3,r14
+err4;   stvx    vr14,r3,r15
+err4;   stvx    vr15,r3,r16
+        addi    r3,r3,128
+        bdnz    8b
+        ld      r14,STK_REG(r14)(r1)
+        ld      r15,STK_REG(r15)(r1)
+        ld      r16,STK_REG(r16)(r1)
+        /* Up to 127B to go */
+        clrldi  r5,r5,(64-7)
+        srdi    r6,r5,4
+        mtocrf  0x01,r6
+        bf      cr7*4+1,9f
+err3;   lvx     vr3,r0,r4
+        vperm   vr8,vr0,vr3,vr16
+err3;   lvx     vr2,r4,r9
+        vperm   vr9,vr3,vr2,vr16
+err3;   lvx     vr1,r4,r10
+        vperm   vr10,vr2,vr1,vr16
+err3;   lvx     vr0,r4,r11
+        vperm   vr11,vr1,vr0,vr16
+        addi    r4,r4,64
+err3;   stvx    vr8,r0,r3
+err3;   stvx    vr9,r3,r9
+err3;   stvx    vr10,r3,r10
+err3;   stvx    vr11,r3,r11
+        addi    r3,r3,64
+9:      bf      cr7*4+2,10f
+err3;   lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+err3;   lvx     vr0,r4,r9
+        vperm   vr9,vr1,vr0,vr16
+        addi    r4,r4,32
+err3;   stvx    vr8,r0,r3
+err3;   stvx    vr9,r3,r9
+        addi    r3,r3,32
+10:     bf      cr7*4+3,11f
+err3;   lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        addi    r4,r4,16
+err3;   stvx    vr8,r0,r3
+        addi    r3,r3,16
+        /* Up to 15B to go */
+11:     clrldi  r5,r5,(64-4)
+        addi    r4,r4,-16       /* Unwind the +16 load offset */
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+err3;   lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+err3;   lwz     r6,4(r4)
+        addi    r4,r4,8
+err3;   stw     r0,0(r3)
+err3;   stw     r6,4(r3)
+        addi    r3,r3,8
+12:     bf      cr7*4+1,13f
+err3;   lwz     r0,0(r4)
+        addi    r4,r4,4
+err3;   stw     r0,0(r3)
+        addi    r3,r3,4
+13:     bf      cr7*4+2,14f
+err3;   lhz     r0,0(r4)
+        addi    r4,r4,2
+err3;   sth     r0,0(r3)
+        addi    r3,r3,2
+14:     bf      cr7*4+3,15f
+err3;   lbz     r0,0(r4)
+err3;   stb     r0,0(r3)
+15:     addi    r1,r1,STACKFRAMESIZE
+        b       .exit_vmx_copy          /* tail call optimise */
+#endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/copyuser_power7_vmx.c b/arch/powerpc/lib/copyuser_power7_vmx.c
new file mode 100644
index 000000000000..6e1efadac48b
--- /dev/null
+++ b/arch/powerpc/lib/copyuser_power7_vmx.c
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2011
+ *
+ * Authors: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
+ *          Anton Blanchard <anton@au.ibm.com>
+ */
+#include <linux/uaccess.h>
+#include <linux/hardirq.h>
+int enter_vmx_copy(void)
+{
+        if (in_interrupt())
+                return 0;
+        /* This acts as preempt_disable() as well and will make
+         * enable_kernel_altivec(). We need to disable page faults
+         * as they can call schedule and thus make us lose the VMX
+         * context. So on page faults, we just fail which will cause
+         * a fallback to the normal non-vmx copy.
+         */
+        pagefault_disable();
+        enable_kernel_altivec();
+        return 1;
+}
+/*
+ * This function must return 0 because we tail call optimise when calling
+ * from __copy_tofrom_user_power7 which returns 0 on success.
+ */
+int exit_vmx_copy(void)
+{
+        pagefault_enable();
+        return 0;
+}
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index f60e006d90c3..388b95e1a009 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -78,11 +78,7 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
                "tlbwe  %1,%3,%5\n"
                "tlbwe  %0,%3,%6\n"
        :
-#ifdef CONFIG_PPC47x
-        : "r" (PPC47x_TLB2_S_RWX),
-#else
        : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
-#endif
          "r" (phys),
          "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
          "r" (entry),
@@ -221,7 +217,7 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 {
        u64 size;
-#ifndef CONFIG_RELOCATABLE
+#ifndef CONFIG_NONSTATIC_KERNEL
        /* We don't currently support the first MEMBLOCK not mapping 0
         * physical on those processors
         */
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 991ee813d2a8..3787b61f7d20 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_PPC_STD_MMU_32)	+= ppc_mmu_32.o
 obj-$(CONFIG_PPC_STD_MMU)       += hash_low_$(CONFIG_WORD_SIZE).o \
                                   tlb_hash$(CONFIG_WORD_SIZE).o \
                                   mmu_context_hash$(CONFIG_WORD_SIZE).o
+obj-$(CONFIG_PPC_ICSWX)         += icswx.o
+obj-$(CONFIG_PPC_ICSWX_PID)     += icswx_pid.o
 obj-$(CONFIG_40x)               += 40x_mmu.o
 obj-$(CONFIG_44x)               += 44x_mmu.o
 obj-$(CONFIG_PPC_FSL_BOOK3E)    += fsl_booke_mmu.o
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c96d37f..2f0d1b032a89 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -44,6 +44,8 @@
 #include <asm/siginfo.h>
 #include <mm/mmu_decl.h>
+#include "icswx.h"
 #ifdef CONFIG_KPROBES
 static inline int notify_page_fault(struct pt_regs *regs)
 {
@@ -143,6 +145,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
        is_write = error_code & ESR_DST;
 #endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+        /*
+         * we need to do this early because this "data storage
+         * interrupt" does not update the DAR/DEAR so we don't want to
+         * look at it
+         */
+        if (error_code & ICSWX_DSI_UCT) {
+                int ret;
+                ret = acop_handle_fault(regs, address, error_code);
+                if (ret)
+                        return ret;
+        }
+#endif
        if (notify_page_fault(regs))
                return 0;
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 343ad0b87261..3bc700655fc8 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -37,31 +37,32 @@ static inline int book3e_tlb_exists(unsigned long ea, unsigned long pid)
        return found;
 }
-void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte)
+void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
+                            pte_t pte)
 {
        unsigned long mas1, mas2;
        u64 mas7_3;
        unsigned long psize, tsize, shift;
        unsigned long flags;
+        struct mm_struct *mm;
 #ifdef CONFIG_PPC_FSL_BOOK3E
-        int index, lz, ncams;
+        int index, ncams;
-        struct vm_area_struct *vma;
 #endif
        if (unlikely(is_kernel_addr(ea)))
                return;
+        mm = vma->vm_mm;
 #ifdef CONFIG_PPC_MM_SLICES
-        psize = mmu_get_tsize(get_slice_psize(mm, ea));
+        psize = get_slice_psize(mm, ea);
-        tsize = mmu_get_psize(psize);
+        tsize = mmu_get_tsize(psize);
        shift = mmu_psize_defs[psize].shift;
 #else
-        vma = find_vma(mm, ea);
+        psize = vma_mmu_pagesize(vma);
-        psize = vma_mmu_pagesize(vma);  /* returns actual size in bytes */
+        shift = __ilog2(psize);
-        asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
+        tsize = shift - 10;
-        shift = 31 - lz;
-        tsize = 21 - lz;
 #endif
        /*
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 8558b572e55d..a8b3cc7d90fe 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -29,22 +29,22 @@ unsigned int HPAGE_SHIFT;
 /*
 * Tracks gpages after the device tree is scanned and before the
- * huge_boot_pages list is ready.  On 64-bit implementations, this is
+ * huge_boot_pages list is ready.  On non-Freescale implementations, this is
- * just used to track 16G pages and so is a single array.  32-bit
+ * just used to track 16G pages and so is a single array.  FSL-based
- * implementations may have more than one gpage size due to limitations
+ * implementations may have more than one gpage size, so we need multiple
- * of the memory allocators, so we need multiple arrays
+ * arrays
 */
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_FSL_BOOK3E
-#define MAX_NUMBER_GPAGES       1024
-static u64 gpage_freearray[MAX_NUMBER_GPAGES];
-static unsigned nr_gpages;
-#else
 #define MAX_NUMBER_GPAGES       128
 struct psize_gpages {
        u64 gpage_list[MAX_NUMBER_GPAGES];
        unsigned int nr_gpages;
 };
 static struct psize_gpages gpage_freearray[MMU_PAGE_COUNT];
+#else
+#define MAX_NUMBER_GPAGES       1024
+static u64 gpage_freearray[MAX_NUMBER_GPAGES];
+static unsigned nr_gpages;
 #endif
 static inline int shift_to_mmu_psize(unsigned int shift)
@@ -115,12 +115,12 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
        struct kmem_cache *cachep;
        pte_t *new;
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_FSL_BOOK3E
-        cachep = PGT_CACHE(pdshift - pshift);
-#else
        int i;
        int num_hugepd = 1 << (pshift - pdshift);
        cachep = hugepte_cache;
+#else
+        cachep = PGT_CACHE(pdshift - pshift);
 #endif
        new = kmem_cache_zalloc(cachep, GFP_KERNEL|__GFP_REPEAT);
@@ -132,12 +132,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
                return -ENOMEM;
        spin_lock(&mm->page_table_lock);
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_FSL_BOOK3E
-        if (!hugepd_none(*hpdp))
-                kmem_cache_free(cachep, new);
-        else
-                hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
-#else
        /*
         * We have multiple higher-level entries that point to the same
         * actual pte location.  Fill in each as we go and backtrack on error.
@@ -156,11 +151,28 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
                        hpdp->pd = 0;
                kmem_cache_free(cachep, new);
        }
+#else
+        if (!hugepd_none(*hpdp))
+                kmem_cache_free(cachep, new);
+        else
+                hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
 #endif
        spin_unlock(&mm->page_table_lock);
        return 0;
 }
+/*
+ * These macros define how to determine which level of the page table holds
+ * the hpdp.
+ */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+#define HUGEPD_PGD_SHIFT PGDIR_SHIFT
+#define HUGEPD_PUD_SHIFT PUD_SHIFT
+#else
+#define HUGEPD_PGD_SHIFT PUD_SHIFT
+#define HUGEPD_PUD_SHIFT PMD_SHIFT
+#endif
 pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
 {
        pgd_t *pg;
@@ -173,12 +185,13 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
        addr &= ~(sz-1);
        pg = pgd_offset(mm, addr);
-        if (pshift >= PUD_SHIFT) {
+        if (pshift >= HUGEPD_PGD_SHIFT) {
                hpdp = (hugepd_t *)pg;
        } else {
                pdshift = PUD_SHIFT;
                pu = pud_alloc(mm, pg, addr);
-                if (pshift >= PMD_SHIFT) {
+                if (pshift >= HUGEPD_PUD_SHIFT) {
                        hpdp = (hugepd_t *)pu;
                } else {
                        pdshift = PMD_SHIFT;
@@ -198,7 +211,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
        return hugepte_offset(hpdp, addr, pdshift);
 }
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
 /* Build list of addresses of gigantic pages.  This function is used in early
 * boot before the buddy or bootmem allocator is setup.
 */
@@ -318,7 +331,7 @@ void __init reserve_hugetlb_gpages(void)
        }
 }
-#else /* PPC64 */
+#else /* !PPC_FSL_BOOK3E */
 /* Build list of addresses of gigantic pages.  This function is used in early
 * boot before the buddy or bootmem allocator is setup.
@@ -356,7 +369,7 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
        return 0;
 }
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
 #define HUGEPD_FREELIST_SIZE \
        ((PAGE_SIZE - sizeof(struct hugepd_freelist)) / sizeof(pte_t))
@@ -416,11 +429,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
        unsigned long pdmask = ~((1UL << pdshift) - 1);
        unsigned int num_hugepd = 1;
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_FSL_BOOK3E
-        unsigned int shift = hugepd_shift(*hpdp);
+        /* Note: On fsl the hpdp may be the first of several */
-#else
-        /* Note: On 32-bit the hpdp may be the first of several */
        num_hugepd = (1 << (hugepd_shift(*hpdp) - pdshift));
+#else
+        unsigned int shift = hugepd_shift(*hpdp);
 #endif
        start &= pdmask;
@@ -438,10 +451,11 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
                hpdp->pd = 0;
        tlb->need_flush = 1;
-#ifdef CONFIG_PPC64
-        pgtable_free_tlb(tlb, hugepte, pdshift - shift);
+#ifdef CONFIG_PPC_FSL_BOOK3E
-#else
        hugepd_free(tlb, hugepte);
+#else
+        pgtable_free_tlb(tlb, hugepte, pdshift - shift);
 #endif
 }
@@ -454,14 +468,23 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
        unsigned long start;
        start = addr;
-        pmd = pmd_offset(pud, addr);
        do {
+                pmd = pmd_offset(pud, addr);
                next = pmd_addr_end(addr, end);
                if (pmd_none(*pmd))
                        continue;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+                /*
+                 * Increment next by the size of the huge mapping since
+                 * there may be more than one entry at this level for a
+                 * single hugepage, but all of them point to
+                 * the same kmem cache that holds the hugepte.
+                 */
+                next = addr + (1 << hugepd_shift(*(hugepd_t *)pmd));
+#endif
                free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT,
                                  addr, next, floor, ceiling);
-        } while (pmd++, addr = next, addr != end);
+        } while (addr = next, addr != end);
        start &= PUD_MASK;
        if (start < floor)
@@ -488,8 +511,8 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
        unsigned long start;
        start = addr;
-        pud = pud_offset(pgd, addr);
        do {
+                pud = pud_offset(pgd, addr);
                next = pud_addr_end(addr, end);
                if (!is_hugepd(pud)) {
                        if (pud_none_or_clear_bad(pud))
@@ -497,10 +520,19 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd,
                        hugetlb_free_pmd_range(tlb, pud, addr, next, floor,
                                               ceiling);
                } else {
+#ifdef CONFIG_PPC_FSL_BOOK3E
+                        /*
+                         * Increment next by the size of the huge mapping since
+                         * there may be more than one entry at this level for a
+                         * single hugepage, but all of them point to
+                         * the same kmem cache that holds the hugepte.
+                         */
+                        next = addr + (1 << hugepd_shift(*(hugepd_t *)pud));
+#endif
                        free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT,
                                          addr, next, floor, ceiling);
                }
-        } while (pud++, addr = next, addr != end);
+        } while (addr = next, addr != end);
        start &= PGDIR_MASK;
        if (start < floor)
@@ -555,12 +587,12 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb,
                                continue;
                        hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling);
                } else {
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_PPC_FSL_BOOK3E
                        /*
                         * Increment next by the size of the huge mapping since
-                         * on 32-bit there may be more than one entry at the pgd
+                         * there may be more than one entry at the pgd level
-                         * level for a single hugepage, but all of them point to
+                         * for a single hugepage, but all of them point to the
-                         * the same kmem cache that holds the hugepte.
+                         * same kmem cache that holds the hugepte.
                         */
                        next = addr + (1 << hugepd_shift(*(hugepd_t *)pgd));
 #endif
@@ -698,19 +730,17 @@ int gup_hugepd(hugepd_t *hugepd, unsigned pdshift,
        return 1;
 }
+#ifdef CONFIG_PPC_MM_SLICES
 unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
                                        unsigned long len, unsigned long pgoff,
                                        unsigned long flags)
 {
-#ifdef CONFIG_PPC_MM_SLICES
        struct hstate *hstate = hstate_file(file);
        int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
        return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
-#else
-        return get_unmapped_area(file, addr, len, pgoff, flags);
-#endif
 }
+#endif
 unsigned long vma_mmu_pagesize(struct vm_area_struct *vma)
 {
@@ -784,7 +814,7 @@ static int __init hugepage_setup_sz(char *str)
 }
 __setup("hugepagesz=", hugepage_setup_sz);
-#ifdef CONFIG_FSL_BOOKE
+#ifdef CONFIG_PPC_FSL_BOOK3E
 struct kmem_cache *hugepte_cache;
 static int __init hugetlbpage_init(void)
 {
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 000000000000..5d9a59eaad93
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,273 @@
+/*
+ *  ICSWX and ACOP Management
+ *
+ *  Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include "icswx.h"
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has no
+ * address, and the processor does not perform an MMU access to
+ * authenticate the transaction. The command portion of the PowerBus
+ * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
+ * Process ID (PID), which the coprocessor compares to the authorized
+ * LPID and PID held in the coprocessor, to determine if the process
+ * is authorized to generate the transaction.  The data of the COP_REQ
+ * transaction is 128-byte or less in size and is placed in cacheable
+ * memory on a 128-byte cache line boundary.
+ *
+ * The task to use a coprocessor should use use_cop() to mark the use
+ * of the Coprocessor Type (CT) and context switching. On a server
+ * class processor, the PID register is used only for coprocessor
+ * management + * and so a coprocessor PID is allocated before
+ * executing icswx + * instruction. Drop_cop() is used to free the
+ * coprocessor PID.
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+void switch_cop(struct mm_struct *next)
+{
+#ifdef CONFIG_ICSWX_PID
+        mtspr(SPRN_PID, next->context.cop_pid);
+#endif
+        mtspr(SPRN_ACOP, next->context.acop);
+}
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise.
+ * The returned PID will be fed to the coprocessor to determine if an
+ * icswx transaction is authenticated.
+ */
+int use_cop(unsigned long acop, struct mm_struct *mm)
+{
+        int ret;
+        if (!cpu_has_feature(CPU_FTR_ICSWX))
+                return -ENODEV;
+        if (!mm || !acop)
+                return -EINVAL;
+        /* The page_table_lock ensures mm_users won't change under us */
+        spin_lock(&mm->page_table_lock);
+        spin_lock(mm->context.cop_lockp);
+        ret = get_cop_pid(mm);
+        if (ret < 0)
+                goto out;
+        /* update acop */
+        mm->context.acop |= acop;
+        sync_cop(mm);
+        /*
+         * If this is a threaded process then there might be other threads
+         * running. We need to send an IPI to force them to pick up any
+         * change in PID and ACOP.
+         */
+        if (atomic_read(&mm->mm_users) > 1)
+                smp_call_function(sync_cop, mm, 1);
+out:
+        spin_unlock(mm->context.cop_lockp);
+        spin_unlock(&mm->page_table_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(use_cop);
+/**
+ * Stop using a coprocessor.
+ * @acop: mask of coprocessor to be stopped.
+ * @mm: The mm the coprocessor associated with.
+ */
+void drop_cop(unsigned long acop, struct mm_struct *mm)
+{
+        int free_pid;
+        if (!cpu_has_feature(CPU_FTR_ICSWX))
+                return;
+        if (WARN_ON_ONCE(!mm))
+                return;
+        /* The page_table_lock ensures mm_users won't change under us */
+        spin_lock(&mm->page_table_lock);
+        spin_lock(mm->context.cop_lockp);
+        mm->context.acop &= ~acop;
+        free_pid = disable_cop_pid(mm);
+        sync_cop(mm);
+        /*
+         * If this is a threaded process then there might be other threads
+         * running. We need to send an IPI to force them to pick up any
+         * change in PID and ACOP.
+         */
+        if (atomic_read(&mm->mm_users) > 1)
+                smp_call_function(sync_cop, mm, 1);
+        if (free_pid != COP_PID_NONE)
+                free_cop_pid(free_pid);
+        spin_unlock(mm->context.cop_lockp);
+        spin_unlock(&mm->page_table_lock);
+}
+EXPORT_SYMBOL_GPL(drop_cop);
+static int acop_use_cop(int ct)
+{
+        /* todo */
+        return -1;
+}
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+        u32 inst;
+        u32 __user *p;
+        p = (u32 __user *)regs->nip;
+        if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+                return 0;
+        if (__get_user(inst, p))
+                return 0;
+        return inst;
+}
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ *              processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+                      unsigned long error_code)
+{
+        int ct;
+        u32 inst = 0;
+        if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+                pr_info("No coprocessors available");
+                _exception(SIGILL, regs, ILL_ILLOPN, address);
+        }
+        if (!user_mode(regs)) {
+                /* this could happen if the HV denies the
+                 * kernel access, for now we just die */
+                die("ICSWX from kernel failed", regs, SIGSEGV);
+        }
+        /* Some implementations leave us a hint for the CT */
+        ct = ICSWX_GET_CT_HINT(error_code);
+        if (ct < 0) {
+                /* we have to peek at the instruction word to figure out CT */
+                u32 ccw;
+                u32 rs;
+                inst = acop_get_inst(regs);
+                if (inst == 0)
+                        return -1;
+                rs = (inst >> (31 - 10)) & 0x1f;
+                ccw = regs->gpr[rs];
+                ct = (ccw >> 16) & 0x3f;
+        }
+        if (!acop_use_cop(ct))
+                return 0;
+        /* at this point the CT is unknown to the system */
+        pr_warn("%s[%d]: Coprocessor %d is unavailable",
+                current->comm, current->pid, ct);
+        /* get inst if we don't already have it */
+        if (inst == 0) {
+                inst = acop_get_inst(regs);
+                if (inst == 0)
+                        return -1;
+        }
+        /* Check if the instruction is the "record form" */
+        if (inst & 1) {
+                /*
+                 * the instruction is "record" form so we can reject
+                 * using CR0
+                 */
+                regs->ccr &= ~(0xful << 28);
+                regs->ccr |= ICSWX_RC_NOT_FOUND << 28;
+                /* Move on to the next instruction */
+                regs->nip += 4;
+        } else {
+                /*
+                 * There is no architected mechanism to report a bad
+                 * CT so we could either SIGILL or report nothing.
+                 * Since the non-record version should only bu used
+                 * for "hints" or "don't care" we should probably do
+                 * nothing.  However, I could see how some people
+                 * might want an SIGILL so it here if you want it.
+                 */
+#ifdef CONFIG_PPC_ICSWX_USE_SIGILL
+                _exception(SIGILL, regs, ILL_ILLOPN, address);
+#else
+                regs->nip += 4;
+#endif
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(acop_handle_fault);
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
new file mode 100644
index 000000000000..42176bd0884c
--- /dev/null
+++ b/arch/powerpc/mm/icswx.h
@@ -0,0 +1,62 @@
+#ifndef _ARCH_POWERPC_MM_ICSWX_H_
+#define _ARCH_POWERPC_MM_ICSWX_H_
+/*
+ *  ICSWX and ACOP Management
+ *
+ *  Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#include <asm/mmu_context.h>
+/* also used to denote that PIDs are not used */
+#define COP_PID_NONE 0
+static inline void sync_cop(void *arg)
+{
+        struct mm_struct *mm = arg;
+        if (mm == current->active_mm)
+                switch_cop(current->active_mm);
+}
+#ifdef CONFIG_PPC_ICSWX_PID
+extern int get_cop_pid(struct mm_struct *mm);
+extern int disable_cop_pid(struct mm_struct *mm);
+extern void free_cop_pid(int free_pid);
+#else
+#define get_cop_pid(m) (COP_PID_NONE)
+#define disable_cop_pid(m) (COP_PID_NONE)
+#define free_cop_pid(p)
+#endif
+/*
+ * These are implementation bits for architected registers.  If this
+ * ever becomes architecture the should be moved to reg.h et. al.
+ */
+/* UCT is the same bit for Server and Embedded */
+#define ICSWX_DSI_UCT           0x00004000  /* Unavailable Coprocessor Type */
+#ifdef CONFIG_PPC_BOOK3E
+/* Embedded implementation gives us no hints as to what the CT is */
+#define ICSWX_GET_CT_HINT(x) (-1)
+#else
+/* Server implementation contains the CT value in the DSISR */
+#define ICSWX_DSISR_CTMASK      0x00003f00
+#define ICSWX_GET_CT_HINT(x)    (((x) & ICSWX_DSISR_CTMASK) >> 8)
+#endif
+#define ICSWX_RC_STARTED        0x8     /* The request has been started */
+#define ICSWX_RC_NOT_IDLE       0x4     /* No coprocessor found idle */
+#define ICSWX_RC_NOT_FOUND      0x2     /* No coprocessor found */
+#define ICSWX_RC_UNDEFINED      0x1     /* Reserved */
+extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+                             unsigned long error_code);
+#endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
diff --git a/arch/powerpc/mm/icswx_pid.c b/arch/powerpc/mm/icswx_pid.c
new file mode 100644
index 000000000000..91e30eb7d054
--- /dev/null
+++ b/arch/powerpc/mm/icswx_pid.c
@@ -0,0 +1,87 @@
+/*
+ *  ICSWX and ACOP/PID Management
+ *
+ *  Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/idr.h>
+#include <linux/module.h>
+#include "icswx.h"
+#define COP_PID_MIN (COP_PID_NONE + 1)
+#define COP_PID_MAX (0xFFFF)
+static DEFINE_SPINLOCK(mmu_context_acop_lock);
+static DEFINE_IDA(cop_ida);
+static int new_cop_pid(struct ida *ida, int min_id, int max_id,
+                       spinlock_t *lock)
+{
+        int index;
+        int err;
+again:
+        if (!ida_pre_get(ida, GFP_KERNEL))
+                return -ENOMEM;
+        spin_lock(lock);
+        err = ida_get_new_above(ida, min_id, &index);
+        spin_unlock(lock);
+        if (err == -EAGAIN)
+                goto again;
+        else if (err)
+                return err;
+        if (index > max_id) {
+                spin_lock(lock);
+                ida_remove(ida, index);
+                spin_unlock(lock);
+                return -ENOMEM;
+        }
+        return index;
+}
+int get_cop_pid(struct mm_struct *mm)
+{
+        int pid;
+        if (mm->context.cop_pid == COP_PID_NONE) {
+                pid = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
+                                  &mmu_context_acop_lock);
+                if (pid >= 0)
+                        mm->context.cop_pid = pid;
+        }
+        return mm->context.cop_pid;
+}
+int disable_cop_pid(struct mm_struct *mm)
+{
+        int free_pid = COP_PID_NONE;
+        if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
+                free_pid = mm->context.cop_pid;
+                mm->context.cop_pid = COP_PID_NONE;
+        }
+        return free_pid;
+}
+void free_cop_pid(int free_pid)
+{
+        spin_lock(&mmu_context_acop_lock);
+        ida_remove(&cop_ida, free_pid);
+        spin_unlock(&mmu_context_acop_lock);
+}
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 58861fa1220e..6157be2a7049 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -65,6 +65,13 @@ phys_addr_t memstart_addr = (phys_addr_t)~0ull;
 EXPORT_SYMBOL(memstart_addr);
 phys_addr_t kernstart_addr;
 EXPORT_SYMBOL(kernstart_addr);
+#ifdef CONFIG_RELOCATABLE_PPC32
+/* Used in __va()/__pa() */
+long long virt_phys_offset;
+EXPORT_SYMBOL(virt_phys_offset);
+#endif
 phys_addr_t lowmem_end_addr;
 int boot_mapsize;
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 8e2eb6611b0b..d974b79a3068 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -51,6 +51,7 @@
 #include <asm/vdso.h>
 #include <asm/fixmap.h>
 #include <asm/swiotlb.h>
+#include <asm/rtas.h>
 #include "mmu_decl.h"
@@ -553,7 +554,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
 #if (defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_PPC_FSL_BOOK3E)) \
        && defined(CONFIG_HUGETLB_PAGE)
        if (is_vm_hugetlb_page(vma))
-                book3e_hugetlb_preload(vma->vm_mm, address, *ptep);
+                book3e_hugetlb_preload(vma, address, *ptep);
 #endif
 }
@@ -585,3 +586,23 @@ static int add_system_ram_resources(void)
        return 0;
 }
 subsys_initcall(add_system_ram_resources);
+#ifdef CONFIG_STRICT_DEVMEM
+/*
+ * devmem_is_allowed(): check to see if /dev/mem access to a certain address
+ * is valid. The argument is a physical page number.
+ *
+ * Access has to be given to non-kernel-ram areas as well, these contain the
+ * PCI mmio resources as well as potential bios/acpi data regions.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+        if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+                return 0;
+        if (!page_is_ram(pfn))
+                return 1;
+        if (page_is_rtas_user_buf(pfn))
+                return 1;
+        return 0;
+}
+#endif /* CONFIG_STRICT_DEVMEM */
diff --git a/arch/powerpc/mm/mmap_64.c b/arch/powerpc/mm/mmap_64.c
index 5a783d8e8e8e..67a42ed0d2fc 100644
--- a/arch/powerpc/mm/mmap_64.c
+++ b/arch/powerpc/mm/mmap_64.c
@@ -53,14 +53,6 @@ static inline int mmap_is_legacy(void)
        return sysctl_legacy_va_layout;
 }
-/*
- * Since get_random_int() returns the same value within a 1 jiffy window,
- * we will almost always get the same randomisation for the stack and mmap
- * region. This will mean the relative distance between stack and mmap will
- * be the same.
- *
- * To avoid this we can shift the randomness by 1 bit.
- */
 static unsigned long mmap_rnd(void)
 {
        unsigned long rnd = 0;
@@ -68,11 +60,11 @@ static unsigned long mmap_rnd(void)
        if (current->flags & PF_RANDOMIZE) {
                /* 8MB for 32bit, 1GB for 64bit */
                if (is_32bit_task())
-                        rnd = (long)(get_random_int() % (1<<(22-PAGE_SHIFT)));
+                        rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
                else
-                        rnd = (long)(get_random_int() % (1<<(29-PAGE_SHIFT)));
+                        rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
        }
-        return (rnd << PAGE_SHIFT) * 2;
+        return rnd << PAGE_SHIFT;
 }
 static inline unsigned long mmap_base(void)
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index ca988a3d5fb2..40677aa0190e 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -24,200 +24,7 @@
 #include <asm/mmu_context.h>
-#ifdef CONFIG_PPC_ICSWX
+#include "icswx.h"
-/*
- * The processor and its L2 cache cause the icswx instruction to
- * generate a COP_REQ transaction on PowerBus. The transaction has
- * no address, and the processor does not perform an MMU access
- * to authenticate the transaction. The command portion of the
- * PowerBus COP_REQ transaction includes the LPAR_ID (LPID) and
- * the coprocessor Process ID (PID), which the coprocessor compares
- * to the authorized LPID and PID held in the coprocessor, to determine
- * if the process is authorized to generate the transaction.
- * The data of the COP_REQ transaction is 128-byte or less and is
- * placed in cacheable memory on a 128-byte cache line boundary.
- *
- * The task to use a coprocessor should use use_cop() to allocate
- * a coprocessor PID before executing icswx instruction. use_cop()
- * also enables the coprocessor context switching. Drop_cop() is
- * used to free the coprocessor PID.
- *
- * Example:
- * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
- * Each HFI have multiple windows. Each HFI window serves as a
- * network device sending to and receiving from HFI network.
- * HFI immediate send function uses icswx instruction. The immediate
- * send function allows small (single cache-line) packets be sent
- * without using the regular HFI send FIFO and doorbell, which are
- * much slower than immediate send.
- *
- * For each task intending to use HFI immediate send, the HFI driver
- * calls use_cop() to obtain a coprocessor PID for the task.
- * The HFI driver then allocate a free HFI window and save the
- * coprocessor PID to the HFI window to allow the task to use the
- * HFI window.
- *
- * The HFI driver repeatedly creates immediate send packets and
- * issues icswx instruction to send data through the HFI window.
- * The HFI compares the coprocessor PID in the CPU PID register
- * to the PID held in the HFI window to determine if the transaction
- * is allowed.
- *
- * When the task to release the HFI window, the HFI driver calls
- * drop_cop() to release the coprocessor PID.
- */
-#define COP_PID_NONE 0
-#define COP_PID_MIN (COP_PID_NONE + 1)
-#define COP_PID_MAX (0xFFFF)
-static DEFINE_SPINLOCK(mmu_context_acop_lock);
-static DEFINE_IDA(cop_ida);
-void switch_cop(struct mm_struct *next)
-{
-        mtspr(SPRN_PID, next->context.cop_pid);
-        mtspr(SPRN_ACOP, next->context.acop);
-}
-static int new_cop_pid(struct ida *ida, int min_id, int max_id,
-                       spinlock_t *lock)
-{
-        int index;
-        int err;
-again:
-        if (!ida_pre_get(ida, GFP_KERNEL))
-                return -ENOMEM;
-        spin_lock(lock);
-        err = ida_get_new_above(ida, min_id, &index);
-        spin_unlock(lock);
-        if (err == -EAGAIN)
-                goto again;
-        else if (err)
-                return err;
-        if (index > max_id) {
-                spin_lock(lock);
-                ida_remove(ida, index);
-                spin_unlock(lock);
-                return -ENOMEM;
-        }
-        return index;
-}
-static void sync_cop(void *arg)
-{
-        struct mm_struct *mm = arg;
-        if (mm == current->active_mm)
-                switch_cop(current->active_mm);
-}
-/**
- * Start using a coprocessor.
- * @acop: mask of coprocessor to be used.
- * @mm: The mm the coprocessor to associate with. Most likely current mm.
- *
- * Return a positive PID if successful. Negative errno otherwise.
- * The returned PID will be fed to the coprocessor to determine if an
- * icswx transaction is authenticated.
- */
-int use_cop(unsigned long acop, struct mm_struct *mm)
-{
-        int ret;
-        if (!cpu_has_feature(CPU_FTR_ICSWX))
-                return -ENODEV;
-        if (!mm || !acop)
-                return -EINVAL;
-        /* The page_table_lock ensures mm_users won't change under us */
-        spin_lock(&mm->page_table_lock);
-        spin_lock(mm->context.cop_lockp);
-        if (mm->context.cop_pid == COP_PID_NONE) {
-                ret = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
-                                  &mmu_context_acop_lock);
-                if (ret < 0)
-                        goto out;
-                mm->context.cop_pid = ret;
-        }
-        mm->context.acop |= acop;
-        sync_cop(mm);
-        /*
-         * If this is a threaded process then there might be other threads
-         * running. We need to send an IPI to force them to pick up any
-         * change in PID and ACOP.
-         */
-        if (atomic_read(&mm->mm_users) > 1)
-                smp_call_function(sync_cop, mm, 1);
-        ret = mm->context.cop_pid;
-out:
-        spin_unlock(mm->context.cop_lockp);
-        spin_unlock(&mm->page_table_lock);
-        return ret;
-}
-EXPORT_SYMBOL_GPL(use_cop);
-/**
- * Stop using a coprocessor.
- * @acop: mask of coprocessor to be stopped.
- * @mm: The mm the coprocessor associated with.
- */
-void drop_cop(unsigned long acop, struct mm_struct *mm)
-{
-        int free_pid = COP_PID_NONE;
-        if (!cpu_has_feature(CPU_FTR_ICSWX))
-                return;
-        if (WARN_ON_ONCE(!mm))
-                return;
-        /* The page_table_lock ensures mm_users won't change under us */
-        spin_lock(&mm->page_table_lock);
-        spin_lock(mm->context.cop_lockp);
-        mm->context.acop &= ~acop;
-        if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
-                free_pid = mm->context.cop_pid;
-                mm->context.cop_pid = COP_PID_NONE;
-        }
-        sync_cop(mm);
-        /*
-         * If this is a threaded process then there might be other threads
-         * running. We need to send an IPI to force them to pick up any
-         * change in PID and ACOP.
-         */
-        if (atomic_read(&mm->mm_users) > 1)
-                smp_call_function(sync_cop, mm, 1);
-        if (free_pid != COP_PID_NONE) {
-                spin_lock(&mmu_context_acop_lock);
-                ida_remove(&cop_ida, free_pid);
-                spin_unlock(&mmu_context_acop_lock);
-        }
-        spin_unlock(mm->context.cop_lockp);
-        spin_unlock(&mm->page_table_lock);
-}
-EXPORT_SYMBOL_GPL(drop_cop);
-#endif /* CONFIG_PPC_ICSWX */
 static DEFINE_SPINLOCK(mmu_context_lock);
 static DEFINE_IDA(mmu_context_ida);
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index e6eea0ac80c8..c0189c169bbb 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -386,7 +386,7 @@ static void __init get_n_mem_cells(int *n_addr_cells, int *n_size_cells)
        of_node_put(memory);
 }
-static unsigned long __devinit read_n_cells(int n, const unsigned int **buf)
+static unsigned long read_n_cells(int n, const unsigned int **buf)
 {
        unsigned long result = 0;
@@ -947,7 +947,7 @@ static struct notifier_block __cpuinitdata ppc64_numa_nb = {
        .priority = 1 /* Must run before sched domains notifier. */
 };
-static void mark_reserved_regions_for_nid(int nid)
+static void __init mark_reserved_regions_for_nid(int nid)
 {
        struct pglist_data *node = NODE_DATA(nid);
        struct memblock_region *reg;
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index dc4a5f385e41..ff672bd8fea9 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -94,11 +94,11 @@
        srdi    r15,r16,60              /* get region */
        rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
-        bne-    dtlb_miss_fault_bolted
+        bne-    dtlb_miss_fault_bolted  /* Bail if fault addr is invalid */
        rlwinm  r10,r11,32-19,27,27
        rlwimi  r10,r11,32-16,19,19
-        cmpwi   r15,0
+        cmpwi   r15,0                   /* user vs kernel check */
        ori     r10,r10,_PAGE_PRESENT
        oris    r11,r10,_PAGE_ACCESSED@h
@@ -120,44 +120,38 @@ tlb_miss_common_bolted:
        rldicl  r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
        cmpldi  cr0,r14,0
        clrrdi  r15,r15,3
-        beq     tlb_miss_fault_bolted
+        beq     tlb_miss_fault_bolted   /* No PGDIR, bail */
 BEGIN_MMU_FTR_SECTION
        /* Set the TLB reservation and search for existing entry. Then load
         * the entry.
         */
        PPC_TLBSRX_DOT(0,r16)
-        ldx     r14,r14,r15
+        ldx     r14,r14,r15             /* grab pgd entry */
-        beq     normal_tlb_miss_done
+        beq     normal_tlb_miss_done    /* tlb exists already, bail */
 MMU_FTR_SECTION_ELSE
-        ldx     r14,r14,r15
+        ldx     r14,r14,r15             /* grab pgd entry */
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
 #ifndef CONFIG_PPC_64K_PAGES
        rldicl  r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
        clrrdi  r15,r15,3
+        cmpdi   cr0,r14,0
-        cmpldi  cr0,r14,0
+        bge     tlb_miss_fault_bolted   /* Bad pgd entry or hugepage; bail */
-        beq     tlb_miss_fault_bolted
+        ldx     r14,r14,r15             /* grab pud entry */
-        ldx     r14,r14,r15
 #endif /* CONFIG_PPC_64K_PAGES */
        rldicl  r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
        clrrdi  r15,r15,3
+        cmpdi   cr0,r14,0
-        cmpldi  cr0,r14,0
+        bge     tlb_miss_fault_bolted
-        beq     tlb_miss_fault_bolted
+        ldx     r14,r14,r15             /* Grab pmd entry */
-        ldx     r14,r14,r15
        rldicl  r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
        clrrdi  r15,r15,3
+        cmpdi   cr0,r14,0
-        cmpldi  cr0,r14,0
+        bge     tlb_miss_fault_bolted
-        beq     tlb_miss_fault_bolted
+        ldx     r14,r14,r15             /* Grab PTE, normal (!huge) page */
-        ldx     r14,r14,r15
        /* Check if required permissions are met */
        andc.   r15,r11,r14
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 573ba3b69d1f..df32a838dcfa 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -52,7 +52,7 @@
 * indirect page table entries.
 */
 #ifdef CONFIG_PPC_BOOK3E_MMU
-#ifdef CONFIG_FSL_BOOKE
+#ifdef CONFIG_PPC_FSL_BOOK3E
 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
        [MMU_PAGE_4K] = {
                .shift  = 12,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 153022971daa..baae85584b1c 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -100,6 +100,16 @@ config XILINX_VIRTEX_GENERIC_BOARD
          Most Virtex designs should use this unless it needs to do some
          special configuration at board probe time.
+config OBS600
+        bool "OpenBlockS 600"
+        depends on 40x
+        default n
+        select 405EX
+        select PPC40x_SIMPLE
+        help
+          This option enables support for PlatHome OpenBlockS 600 server
 config PPC40x_SIMPLE
        bool "Simple PowerPC 40x board support"
        depends on 40x
@@ -186,3 +196,14 @@ config IBM405_ERR51
 #       bool
 #       depends on !STB03xxx && PPC4xx_DMA
 #       default y
+#
+config APM8018X
+        bool "APM8018X"
+        depends on 40x
+        default n
+        select PPC40x_SIMPLE
+        help
+          This option enables support for the AppliedMicro APM8018X evaluation
+          board.
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index e8dd5c5df7d9..97612068fae3 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -55,7 +55,9 @@ static const char *board[] __initdata = {
        "amcc,haleakala",
        "amcc,kilauea",
        "amcc,makalu",
-        "est,hotfoot"
+        "apm,klondike",
+        "est,hotfoot",
+        "plathome,obs600"
 };
 static int __init ppc40x_probe(void)
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 762322ce24a9..5d5aaf6c91aa 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -186,6 +186,16 @@ config ISS4xx
        help
          This option enables support for the IBM ISS simulation environment
+config CURRITUCK
+        bool "IBM Currituck (476fpe) Support"
+        depends on PPC_47x
+        default n
+        select SWIOTLB
+        select 476FPE
+        select PPC4xx_PCI_EXPRESS
+        help
+          This option enables support for the IBM Currituck (476fpe) evaluation board
 config ICON
        bool "Icon"
        depends on 44x
@@ -308,6 +318,10 @@ config 460SX
        select IBM_EMAC_ZMII
        select IBM_EMAC_TAH
+config 476FPE
+        bool
+        select PPC_FPU
 config APM821xx
        bool
        select PPC_FPU
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 553db6007217..d03833abec09 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
 obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
 obj-$(CONFIG_ISS4xx)    += iss4xx.o
 obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
+obj-$(CONFIG_CURRITUCK) += currituck.o
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
new file mode 100644
index 000000000000..3f6229b5dee0
--- /dev/null
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -0,0 +1,204 @@
+/*
+ * Currituck board specific routines
+ *
+ * Copyright © 2011 Tony Breeds IBM Corporation
+ *
+ * Based on earlier code:
+ *    Matt Porter <mporter@kernel.crashing.org>
+ *    Copyright 2002-2005 MontaVista Software Inc.
+ *
+ *    Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *    Copyright (c) 2003-2005 Zultys Technologies
+ *
+ *    Rewritten and ported to the merged powerpc tree:
+ *    Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
+ *    Copyright © 2011 David Kliekamp IBM Corporation
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/memblock.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/rtc.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/ppc4xx.h>
+#include <asm/mpic.h>
+#include <asm/mmu.h>
+#include <linux/pci.h>
+static __initdata struct of_device_id ppc47x_of_bus[] = {
+        { .compatible = "ibm,plb4", },
+        { .compatible = "ibm,plb6", },
+        { .compatible = "ibm,opb", },
+        { .compatible = "ibm,ebc", },
+        {},
+};
+/* The EEPROM is missing and the default values are bogus.  This forces USB in
+ * to EHCI mode */
+static void __devinit quirk_ppc_currituck_usb_fixup(struct pci_dev *dev)
+{
+        if (of_machine_is_compatible("ibm,currituck")) {
+                pci_write_config_dword(dev, 0xe0, 0x0114231f);
+                pci_write_config_dword(dev, 0xe4, 0x00006c40);
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(0x1033, 0x0035, quirk_ppc_currituck_usb_fixup);
+static int __init ppc47x_device_probe(void)
+{
+        of_platform_bus_probe(NULL, ppc47x_of_bus, NULL);
+        return 0;
+}
+machine_device_initcall(ppc47x, ppc47x_device_probe);
+/* We can have either UICs or MPICs */
+static void __init ppc47x_init_irq(void)
+{
+        struct device_node *np;
+        /* Find top level interrupt controller */
+        for_each_node_with_property(np, "interrupt-controller") {
+                if (of_get_property(np, "interrupts", NULL) == NULL)
+                        break;
+        }
+        if (np == NULL)
+                panic("Can't find top level interrupt controller");
+        /* Check type and do appropriate initialization */
+        if (of_device_is_compatible(np, "chrp,open-pic")) {
+                /* The MPIC driver will get everything it needs from the
+                 * device-tree, just pass 0 to all arguments
+                 */
+                struct mpic *mpic =
+                        mpic_alloc(np, 0, 0, 0, 0, " MPIC     ");
+                BUG_ON(mpic == NULL);
+                mpic_init(mpic);
+                ppc_md.get_irq = mpic_get_irq;
+        } else
+                panic("Unrecognized top level interrupt controller");
+}
+#ifdef CONFIG_SMP
+static void __cpuinit smp_ppc47x_setup_cpu(int cpu)
+{
+        mpic_setup_this_cpu();
+}
+static int __cpuinit smp_ppc47x_kick_cpu(int cpu)
+{
+        struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
+        const u64 *spin_table_addr_prop;
+        u32 *spin_table;
+        extern void start_secondary_47x(void);
+        BUG_ON(cpunode == NULL);
+        /* Assume spin table. We could test for the enable-method in
+         * the device-tree but currently there's little point as it's
+         * our only supported method
+         */
+        spin_table_addr_prop =
+                of_get_property(cpunode, "cpu-release-addr", NULL);
+        if (spin_table_addr_prop == NULL) {
+                pr_err("CPU%d: Can't start, missing cpu-release-addr !\n",
+                       cpu);
+                return 1;
+        }
+        /* Assume it's mapped as part of the linear mapping. This is a bit
+         * fishy but will work fine for now
+         *
+         * XXX: Is there any reason to assume differently?
+         */
+        spin_table = (u32 *)__va(*spin_table_addr_prop);
+        pr_debug("CPU%d: Spin table mapped at %p\n", cpu, spin_table);
+        spin_table[3] = cpu;
+        smp_wmb();
+        spin_table[1] = __pa(start_secondary_47x);
+        mb();
+        return 0;
+}
+static struct smp_ops_t ppc47x_smp_ops = {
+        .probe          = smp_mpic_probe,
+        .message_pass   = smp_mpic_message_pass,
+        .setup_cpu      = smp_ppc47x_setup_cpu,
+        .kick_cpu       = smp_ppc47x_kick_cpu,
+        .give_timebase  = smp_generic_give_timebase,
+        .take_timebase  = smp_generic_take_timebase,
+};
+static void __init ppc47x_smp_init(void)
+{
+        if (mmu_has_feature(MMU_FTR_TYPE_47x))
+                smp_ops = &ppc47x_smp_ops;
+}
+#else /* CONFIG_SMP */
+static void __init ppc47x_smp_init(void) { }
+#endif /* CONFIG_SMP */
+static void __init ppc47x_setup_arch(void)
+{
+        /* No need to check the DMA config as we /know/ our windows are all of
+         * RAM.  Lets hope that doesn't change */
+#ifdef CONFIG_SWIOTLB
+        if (memblock_end_of_DRAM() > 0xffffffff) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+        ppc47x_smp_init();
+}
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init ppc47x_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        if (!of_flat_dt_is_compatible(root, "ibm,currituck"))
+                return 0;
+        return 1;
+}
+/* Use USB controller should have been hardware swizzled but it wasn't :( */
+static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
+{
+        if (dev->vendor == 0x1033 && (dev->device == 0x0035 ||
+                                      dev->device == 0x00e0)) {
+                dev->irq = irq_create_mapping(NULL, 47);
+                pr_info("%s: Mapping irq 47 %d\n", __func__, dev->irq);
+        }
+}
+define_machine(ppc47x) {
+        .name                   = "PowerPC 47x",
+        .probe                  = ppc47x_probe,
+        .progress               = udbg_progress,
+        .init_IRQ               = ppc47x_init_irq,
+        .setup_arch             = ppc47x_setup_arch,
+        .pci_irq_fixup          = ppc47x_pci_irq_fixup,
+        .restart                = ppc4xx_reset_system,
+        .calibrate_decr         = generic_calibrate_decr,
+};
diff --git a/arch/powerpc/platforms/44x/iss4xx.c b/arch/powerpc/platforms/44x/iss4xx.c
index 19395f18b1db..5b8cdbb82f80 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -71,7 +71,7 @@ static void __init iss4xx_init_irq(void)
                /* The MPIC driver will get everything it needs from the
                 * device-tree, just pass 0 to all arguments
                 */
-                struct mpic *mpic = mpic_alloc(np, 0, MPIC_PRIMARY, 0, 0,
+                struct mpic *mpic = mpic_alloc(np, 0, 0, 0, 0,
                                               " MPIC     ");
                BUG_ON(mpic == NULL);
                mpic_init(mpic);
diff --git a/arch/powerpc/platforms/83xx/asp834x.c b/arch/powerpc/platforms/83xx/asp834x.c
index aa0d84d22585..464ea8e0292d 100644
--- a/arch/powerpc/platforms/83xx/asp834x.c
+++ b/arch/powerpc/platforms/83xx/asp834x.c
@@ -36,38 +36,7 @@ static void __init asp834x_setup_arch(void)
        mpc834x_usb_cfg();
 }
-static void __init asp834x_init_IRQ(void)
+machine_device_initcall(asp834x, mpc83xx_declare_of_platform_devices);
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        of_node_put(np);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
-static struct __initdata of_device_id asp8347_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init asp8347_declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, asp8347_ids, NULL);
-        return 0;
-}
-machine_device_initcall(asp834x, asp8347_declare_of_platform_devices);
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -82,7 +51,7 @@ define_machine(asp834x) {
        .name                   = "ASP8347E",
        .probe                  = asp834x_probe,
        .setup_arch             = asp834x_setup_arch,
-        .init_IRQ               = asp834x_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index c55129f5760a..65eb792a0d00 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -51,15 +51,14 @@
 */
 static void __init mpc83xx_km_setup_arch(void)
 {
+#ifdef CONFIG_QUICC_ENGINE
        struct device_node *np;
+#endif
        if (ppc_md.progress)
                ppc_md.progress("kmpbec83xx_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
        qe_reset();
@@ -122,54 +121,7 @@ static void __init mpc83xx_km_setup_arch(void)
 #endif                          /* CONFIG_QUICC_ENGINE */
 }
-static struct of_device_id kmpbec83xx_ids[] = {
+machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
-        {},
-};
-static int __init kmeter_declare_of_platform_devices(void)
-{
-        /* Publish the QE devices */
-        of_platform_bus_probe(NULL, kmpbec83xx_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc83xx_km, kmeter_declare_of_platform_devices);
-static void __init mpc83xx_km_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "ipic");
-                if (!np)
-                        return;
-        }
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
-}
 /* list of the supported boards */
 static char *board[] __initdata = {
@@ -198,7 +150,7 @@ define_machine(mpc83xx_km) {
        .name           = "mpc83xx-km-platform",
        .probe          = mpc83xx_km_probe,
        .setup_arch     = mpc83xx_km_setup_arch,
-        .init_IRQ       = mpc83xx_km_init_IRQ,
+        .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index f01806c940e1..125336f750c6 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -11,10 +11,15 @@
 #include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
 #include <asm/io.h>
 #include <asm/hw_irq.h>
+#include <asm/ipic.h>
+#include <asm/qe_ic.h>
 #include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
 #include "mpc83xx.h"
@@ -65,3 +70,75 @@ long __init mpc83xx_time_init(void)
        return 0;
 }
+void __init mpc83xx_ipic_init_IRQ(void)
+{
+        struct device_node *np;
+        /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
+        np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
+        if (!np)
+                np = of_find_node_by_type(NULL, "ipic");
+        if (!np)
+                return;
+        ipic_init(np, 0);
+        of_node_put(np);
+        /* Initialize the default interrupt mapping priorities,
+         * in case the boot rom changed something on us.
+         */
+        ipic_set_default_priority();
+}
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc83xx_qe_init_IRQ(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (!np) {
+                np = of_find_node_by_type(NULL, "qeic");
+                if (!np)
+                        return;
+        }
+        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+        of_node_put(np);
+}
+void __init mpc83xx_ipic_and_qe_init_IRQ(void)
+{
+        mpc83xx_ipic_init_IRQ();
+        mpc83xx_qe_init_IRQ();
+}
+#endif /* CONFIG_QUICC_ENGINE */
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus" },
+        { .compatible = "gianfar" },
+        { .compatible = "gpio-leds", },
+        { .type = "qe", },
+        { .compatible = "fsl,qe", },
+        {},
+};
+int __init mpc83xx_declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+        return 0;
+}
+#ifdef CONFIG_PCI
+void __init mpc83xx_setup_pci(void)
+{
+        struct device_node *np;
+        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
+                mpc83xx_add_bridge(np);
+        for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
+                mpc83xx_add_bridge(np);
+}
+#endif
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
index d0c4e15b7794..4f2d9fea77b7 100644
--- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -27,36 +27,13 @@
 */
 static void __init mpc830x_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
-                mpc83xx_add_bridge(np);
-#endif
        mpc831x_usb_cfg();
 }
-static void __init mpc830x_rdb_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
 static const char *board[] __initdata = {
        "MPC8308RDB",
        "fsl,mpc8308rdb",
@@ -72,24 +49,13 @@ static int __init mpc830x_rdb_probe(void)
        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(mpc830x_rdb, mpc83xx_declare_of_platform_devices);
-        { .compatible = "simple-bus" },
-        { .compatible = "gianfar" },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
 define_machine(mpc830x_rdb) {
        .name                   = "MPC830x RDB",
        .probe                  = mpc830x_rdb_probe,
        .setup_arch             = mpc830x_rdb_setup_arch,
-        .init_IRQ               = mpc830x_rdb_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index f859ead49a8d..fa25977c52de 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -28,38 +28,13 @@
 */
 static void __init mpc831x_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc831x_rdb_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-        for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
-                mpc83xx_add_bridge(np);
-#endif
        mpc831x_usb_cfg();
 }
-static void __init mpc831x_rdb_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
 static const char *board[] __initdata = {
        "MPC8313ERDB",
        "fsl,mpc8315erdb",
@@ -74,25 +49,13 @@ static int __init mpc831x_rdb_probe(void)
        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(mpc831x_rdb, mpc83xx_declare_of_platform_devices);
-        { .compatible = "simple-bus" },
-        { .compatible = "gianfar" },
-        { .compatible = "gpio-leds", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc831x_rdb, declare_of_platform_devices);
 define_machine(mpc831x_rdb) {
        .name                   = "MPC831x RDB",
        .probe                  = mpc831x_rdb_probe,
        .setup_arch             = mpc831x_rdb_setup_arch,
-        .init_IRQ               = mpc831x_rdb_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 32a52896822f..e36bc611dd6e 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -72,10 +72,7 @@ static void __init mpc832x_sys_setup_arch(void)
                of_node_put(np);
        }
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
        qe_reset();
@@ -101,51 +98,7 @@ static void __init mpc832x_sys_setup_arch(void)
 #endif                          /* CONFIG_QUICC_ENGINE */
 }
-static struct of_device_id mpc832x_ids[] = {
+machine_device_initcall(mpc832x_mds, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
-        {},
-};
-static int __init mpc832x_declare_of_platform_devices(void)
-{
-        /* Publish the QE devices */
-        of_platform_bus_probe(NULL, mpc832x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc832x_mds, mpc832x_declare_of_platform_devices);
-static void __init mpc832x_sys_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -161,7 +114,7 @@ define_machine(mpc832x_mds) {
        .name           = "MPC832x MDS",
        .probe          = mpc832x_sys_probe,
        .setup_arch     = mpc832x_sys_setup_arch,
-        .init_IRQ       = mpc832x_sys_init_IRQ,
+        .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 17f99745f0e4..eff5baabc3fb 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -193,17 +193,14 @@ machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
 */
 static void __init mpc832x_rdb_setup_arch(void)
 {
-#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
+#if defined(CONFIG_QUICC_ENGINE)
        struct device_node *np;
 #endif
        if (ppc_md.progress)
                ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
        qe_reset();
@@ -218,52 +215,7 @@ static void __init mpc832x_rdb_setup_arch(void)
 #endif                          /* CONFIG_QUICC_ENGINE */
 }
-static struct of_device_id mpc832x_ids[] = {
+machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
-        {},
-};
-static int __init mpc832x_declare_of_platform_devices(void)
-{
-        /* Publish the QE devices */
-        of_platform_bus_probe(NULL, mpc832x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
-static void __init mpc832x_rdb_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -279,7 +231,7 @@ define_machine(mpc832x_rdb) {
        .name           = "MPC832x RDB",
        .probe          = mpc832x_rdb_probe,
        .setup_arch     = mpc832x_rdb_setup_arch,
-        .init_IRQ       = mpc832x_rdb_init_IRQ,
+        .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index 6b45969567d4..39849dd1b5bb 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -41,13 +41,12 @@
 static struct of_device_id __initdata mpc834x_itx_ids[] = {
        { .compatible = "fsl,pq2pro-localbus", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
        {},
 };
 static int __init mpc834x_itx_declare_of_platform_devices(void)
 {
+        mpc83xx_declare_of_platform_devices();
        return of_platform_bus_probe(NULL, mpc834x_itx_ids, NULL);
 }
 machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices);
@@ -59,37 +58,14 @@ machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices);
 */
 static void __init mpc834x_itx_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc834x_itx_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
        mpc834x_usb_cfg();
 }
-static void __init mpc834x_itx_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
@@ -104,7 +80,7 @@ define_machine(mpc834x_itx) {
        .name                   = "MPC834x ITX",
        .probe                  = mpc834x_itx_probe,
        .setup_arch             = mpc834x_itx_setup_arch,
-        .init_IRQ               = mpc834x_itx_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc834x_mds.c b/arch/powerpc/platforms/83xx/mpc834x_mds.c
index 041c5177e737..5828d8e97c37 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_mds.c
@@ -77,51 +77,15 @@ static int mpc834xemds_usb_cfg(void)
 */
 static void __init mpc834x_mds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc834x_mds_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
        mpc834xemds_usb_cfg();
 }
-static void __init mpc834x_mds_init_IRQ(void)
+machine_device_initcall(mpc834x_mds, mpc83xx_declare_of_platform_devices);
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
-static struct of_device_id mpc834x_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init mpc834x_declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, mpc834x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc834x_mds, mpc834x_declare_of_platform_devices);
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -137,7 +101,7 @@ define_machine(mpc834x_mds) {
        .name                   = "MPC834x MDS",
        .probe                  = mpc834x_mds_probe,
        .setup_arch             = mpc834x_mds_setup_arch,
-        .init_IRQ               = mpc834x_mds_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 934cc8c46bbc..ad8e4bcd7d55 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -80,10 +80,7 @@ static void __init mpc836x_mds_setup_arch(void)
                of_node_put(np);
        }
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
        qe_reset();
@@ -144,23 +141,7 @@ static void __init mpc836x_mds_setup_arch(void)
 #endif                          /* CONFIG_QUICC_ENGINE */
 }
-static struct of_device_id mpc836x_ids[] = {
+machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
-        {},
-};
-static int __init mpc836x_declare_of_platform_devices(void)
-{
-        /* Publish the QE devices */
-        of_platform_bus_probe(NULL, mpc836x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
 #ifdef CONFIG_QE_USB
 static int __init mpc836x_usb_cfg(void)
@@ -226,34 +207,6 @@ err:
 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
 #endif /* CONFIG_QE_USB */
-static void __init mpc836x_mds_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
@@ -268,7 +221,7 @@ define_machine(mpc836x_mds) {
        .name           = "MPC836x MDS",
        .probe          = mpc836x_mds_probe,
        .setup_arch     = mpc836x_mds_setup_arch,
-        .init_IRQ       = mpc836x_mds_init_IRQ,
+        .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index b0090aac9642..f8769d713d61 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -27,61 +27,19 @@
 #include "mpc83xx.h"
-static struct of_device_id __initdata mpc836x_rdk_ids[] = {
+machine_device_initcall(mpc836x_rdk, mpc83xx_declare_of_platform_devices);
-        { .compatible = "simple-bus", },
-        {},
-};
-static int __init mpc836x_rdk_declare_of_platform_devices(void)
-{
-        return of_platform_bus_probe(NULL, mpc836x_rdk_ids, NULL);
-}
-machine_device_initcall(mpc836x_rdk, mpc836x_rdk_declare_of_platform_devices);
 static void __init mpc836x_rdk_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc836x_rdk_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
        qe_reset();
 #endif
 }
-static void __init mpc836x_rdk_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /*
-         * Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np)
-                return;
-        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-        of_node_put(np);
-#endif
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened.
 */
@@ -96,7 +54,7 @@ define_machine(mpc836x_rdk) {
        .name           = "MPC836x RDK",
        .probe          = mpc836x_rdk_probe,
        .setup_arch     = mpc836x_rdk_setup_arch,
-        .init_IRQ       = mpc836x_rdk_init_IRQ,
+        .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
        .get_irq        = ipic_get_irq,
        .restart        = mpc83xx_restart,
        .time_init      = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 83068322abd1..e53a60b6c863 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -79,54 +79,14 @@ out:
 */
 static void __init mpc837x_mds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc837x_mds_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-        for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
-                mpc83xx_add_bridge(np);
-#endif
        mpc837xmds_usb_cfg();
 }
-static struct of_device_id mpc837x_ids[] = {
+machine_device_initcall(mpc837x_mds, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init mpc837x_declare_of_platform_devices(void)
-{
-        /* Publish platform_device */
-        of_platform_bus_probe(NULL, mpc837x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc837x_mds, mpc837x_declare_of_platform_devices);
-static void __init mpc837x_mds_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -142,7 +102,7 @@ define_machine(mpc837x_mds) {
        .name                   = "MPC837x MDS",
        .probe                  = mpc837x_mds_probe,
        .setup_arch             = mpc837x_mds_setup_arch,
-        .init_IRQ               = mpc837x_mds_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 7bafbf2ec0f9..16c9c9cbbb7f 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -50,56 +50,15 @@ static void mpc837x_rdb_sd_cfg(void)
 */
 static void __init mpc837x_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc837x_rdb_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-        for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
-                mpc83xx_add_bridge(np);
-#endif
        mpc837x_usb_cfg();
        mpc837x_rdb_sd_cfg();
 }
-static struct of_device_id mpc837x_ids[] = {
+machine_device_initcall(mpc837x_rdb, mpc83xx_declare_of_platform_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        { .compatible = "gpio-leds", },
-        {},
-};
-static int __init mpc837x_declare_of_platform_devices(void)
-{
-        /* Publish platform_device */
-        of_platform_bus_probe(NULL, mpc837x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc837x_rdb, mpc837x_declare_of_platform_devices);
-static void __init mpc837x_rdb_init_IRQ(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-}
 static const char *board[] __initdata = {
        "fsl,mpc8377rdb",
@@ -121,7 +80,7 @@ define_machine(mpc837x_rdb) {
        .name                   = "MPC837x RDB/WLAN",
        .probe                  = mpc837x_rdb_probe,
        .setup_arch             = mpc837x_rdb_setup_arch,
-        .init_IRQ               = mpc837x_rdb_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 82a434510d83..0cf74d7ea1c5 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -70,5 +70,21 @@ extern long mpc83xx_time_init(void);
 extern int mpc837x_usb_cfg(void);
 extern int mpc834x_usb_cfg(void);
 extern int mpc831x_usb_cfg(void);
+extern void mpc83xx_ipic_init_IRQ(void);
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc83xx_qe_init_IRQ(void);
+extern void mpc83xx_ipic_and_qe_init_IRQ(void);
+#else
+static inline void __init mpc83xx_qe_init_IRQ(void) {}
+#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
+#endif /* CONFIG_QUICC_ENGINE */
+#ifdef CONFIG_PCI
+extern void mpc83xx_setup_pci(void);
+#else
+#define mpc83xx_setup_pci()     do {} while (0)
+#endif
+extern int mpc83xx_declare_of_platform_devices(void);
 #endif                          /* __MPC83XX_H__ */
diff --git a/arch/powerpc/platforms/83xx/sbc834x.c b/arch/powerpc/platforms/83xx/sbc834x.c
index af41d8c810a8..8a81d7640b1f 100644
--- a/arch/powerpc/platforms/83xx/sbc834x.c
+++ b/arch/powerpc/platforms/83xx/sbc834x.c
@@ -48,52 +48,13 @@
 */
 static void __init sbc834x_setup_arch(void)
 {
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("sbc834x_setup_arch()", 0);
-#ifdef CONFIG_PCI
+        mpc83xx_setup_pci();
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
-                mpc83xx_add_bridge(np);
-#endif
 }
-static void __init sbc834x_init_IRQ(void)
+machine_device_initcall(sbc834x, mpc83xx_declare_of_platform_devices);
-{
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "ipic");
-        if (!np)
-                return;
-        ipic_init(np, 0);
-        /* Initialize the default interrupt mapping priorities,
-         * in case the boot rom changed something on us.
-         */
-        ipic_set_default_priority();
-        of_node_put(np);
-}
-static struct __initdata of_device_id sbc834x_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init sbc834x_declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, sbc834x_ids, NULL);
-        return 0;
-}
-machine_device_initcall(sbc834x, sbc834x_declare_of_platform_devices);
 /*
 * Called very early, MMU is off, device-tree isn't unflattened
@@ -102,14 +63,14 @@ static int __init sbc834x_probe(void)
 {
        unsigned long root = of_get_flat_dt_root();
-        return of_flat_dt_is_compatible(root, "SBC834x");
+        return of_flat_dt_is_compatible(root, "SBC834xE");
 }
 define_machine(sbc834x) {
-        .name                   = "SBC834x",
+        .name                   = "SBC834xE",
        .probe                  = sbc834x_probe,
        .setup_arch             = sbc834x_setup_arch,
-        .init_IRQ               = sbc834x_init_IRQ,
+        .init_IRQ               = mpc83xx_ipic_init_IRQ,
        .get_irq                = ipic_get_irq,
        .restart                = mpc83xx_restart,
        .time_init              = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index bc5acb95917a..9cb2d4320dcc 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -3,6 +3,8 @@
 #
 obj-$(CONFIG_SMP) += smp.o
+obj-y += common.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
new file mode 100644
index 000000000000..9fef5302adc1
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -0,0 +1,66 @@
+/*
+ * Routines common to most mpc85xx-based boards.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/of_platform.h>
+#include <sysdev/cpm2_pic.h>
+#include "mpc85xx.h"
+static struct of_device_id __initdata mpc85xx_common_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .name = "cpm", },
+        { .name = "localbus", },
+        { .compatible = "gianfar", },
+        { .compatible = "fsl,qe", },
+        { .compatible = "fsl,cpm2", },
+        { .compatible = "fsl,srio", },
+        {},
+};
+int __init mpc85xx_common_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
+}
+#ifdef CONFIG_CPM2
+static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        int cascade_irq;
+        while ((cascade_irq = cpm2_get_irq()) >= 0)
+                generic_handle_irq(cascade_irq);
+        chip->irq_eoi(&desc->irq_data);
+}
+void __init mpc85xx_cpm2_pic_init(void)
+{
+        struct device_node *np;
+        int irq;
+        /* Setup CPM2 PIC */
+        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
+        if (np == NULL) {
+                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+                return;
+        }
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq == NO_IRQ) {
+                of_node_put(np);
+                printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
+                return;
+        }
+        cpm2_pic_init(np);
+        of_node_put(np);
+        irq_set_chained_handler(irq, cpm2_cascade);
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 802ad110b757..07e3e6c47371 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -31,32 +31,18 @@
 #include <linux/of_platform.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "smp.h"
 void __init corenet_ds_pic_init(void)
 {
        struct mpic *mpic;
-        struct resource r;
+        unsigned int flags = MPIC_BIG_ENDIAN |
-        struct device_node *np = NULL;
-        unsigned int flags = MPIC_PRIMARY | MPIC_BIG_ENDIAN |
                                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
-        np = of_find_node_by_type(np, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
        if (ppc_md.get_irq == mpic_get_coreint_irq)
                flags |= MPIC_ENABLE_COREINT;
-        mpic = mpic_alloc(np, r.start, flags, 0, 256, " OpenPIC  ");
+        mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
        mpic_init(mpic);
@@ -65,10 +51,6 @@ void __init corenet_ds_pic_init(void)
 /*
 * Setup the architecture
 */
-#ifdef CONFIG_SMP
-void __init mpc85xx_smp_init(void);
-#endif
 void __init corenet_ds_setup_arch(void)
 {
 #ifdef CONFIG_PCI
@@ -77,9 +59,7 @@ void __init corenet_ds_setup_arch(void)
 #endif
        dma_addr_t max = 0xffffffff;
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
 #ifdef CONFIG_PCI
        for_each_node_by_type(np, "pci") {
@@ -112,7 +92,7 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
                .compatible     = "simple-bus"
        },
        {
-                .compatible     = "fsl,rapidio-delta",
+                .compatible     = "fsl,srio",
        },
        {
                .compatible     = "fsl,p4080-pcie",
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index c46f9359be15..20f75d7819c6 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -35,6 +35,7 @@
 #include <asm/cpm2.h>
 #include <sysdev/cpm2_pic.h>
+#include "mpc85xx.h"
 #define KSI8560_CPLD_HVR                0x04 /* Hardware Version Register */
 #define KSI8560_CPLD_PVR                0x08 /* PLD Version Register */
@@ -54,60 +55,15 @@ static void machine_restart(char *cmd)
        for (;;);
 }
-static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        int cascade_irq;
-        while ((cascade_irq = cpm2_get_irq()) >= 0)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
 static void __init ksi8560_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np;
-#ifdef CONFIG_CPM2
-        int irq;
-#endif
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
-#ifdef CONFIG_CPM2
+        mpc85xx_cpm2_pic_init();
-        /* Setup CPM2 PIC */
-        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
-                return;
-        }
-        irq = irq_of_parse_and_map(np, 0);
-        cpm2_pic_init(np);
-        of_node_put(np);
-        irq_set_chained_handler(irq, cpm2_cascade);
-#endif
 }
 #ifdef CONFIG_CPM2
@@ -215,22 +171,7 @@ static void ksi8560_show_cpuinfo(struct seq_file *m)
        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(ksi8560, mpc85xx_common_publish_devices);
-        { .type = "soc", },
-        { .type = "simple-bus", },
-        { .name = "cpm", },
-        { .name = "localbus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(ksi8560, declare_of_platform_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index f79f2f102141..cf266826682e 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -32,31 +32,15 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 void __init mpc8536_ds_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                          MPIC_WANTS_RESET |
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                          MPIC_PRIMARY | MPIC_WANTS_RESET |
                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
@@ -104,19 +88,7 @@ static void __init mpc8536_ds_setup_arch(void)
        printk("MPC8536 DS board from Freescale Semiconductor\n");
 }
-static struct of_device_id __initdata mpc8536_ds_ids[] = {
+machine_device_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init mpc8536_ds_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, mpc8536_ds_ids, NULL);
-}
-machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices);
 machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
new file mode 100644
index 000000000000..2aa7c5dc2c7f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -0,0 +1,11 @@
+#ifndef MPC85xx_H
+#define MPC85xx_H
+extern int mpc85xx_common_publish_devices(void);
+#ifdef CONFIG_CPM2
+extern void mpc85xx_cpm2_pic_init(void);
+#else
+static inline void __init mpc85xx_cpm2_pic_init(void) {}
+#endif /* CONFIG_CPM2 */
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 3b2c9bb66199..3bebb5173bfc 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -35,6 +35,8 @@
 #include <sysdev/cpm2_pic.h>
 #endif
+#include "mpc85xx.h"
 #ifdef CONFIG_PCI
 static int mpc85xx_exclude_device(struct pci_controller *hose,
                                   u_char bus, u_char devfn)
@@ -46,63 +48,15 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 }
 #endif /* CONFIG_PCI */
-#ifdef CONFIG_CPM2
-static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        int cascade_irq;
-        while ((cascade_irq = cpm2_get_irq()) >= 0)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
-#endif /* CONFIG_CPM2 */
 static void __init mpc85xx_ads_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np = NULL;
-#ifdef CONFIG_CPM2
-        int irq;
-#endif
-        np = of_find_node_by_type(np, "open-pic");
-        if (!np) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
-#ifdef CONFIG_CPM2
+        mpc85xx_cpm2_pic_init();
-        /* Setup CPM2 PIC */
-        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
-                return;
-        }
-        irq = irq_of_parse_and_map(np, 0);
-        cpm2_pic_init(np);
-        of_node_put(np);
-        irq_set_chained_handler(irq, cpm2_cascade);
-#endif
 }
 /*
@@ -221,23 +175,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
-        { .name = "soc", },
-        { .type = "soc", },
-        { .name = "cpm", },
-        { .name = "localbus", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(mpc85xx_ads, declare_of_platform_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 66cb8d64079f..40f03da616a9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -46,6 +46,8 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 /* CADMUS info */
 /* xxx - galak, move into device tree */
 #define CADMUS_BASE (0xf8004000)
@@ -177,7 +179,7 @@ static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 static struct irqaction mpc85xxcds_8259_irqaction = {
        .handler = mpc85xx_8259_cascade_action,
-        .flags = IRQF_SHARED,
+        .flags = IRQF_SHARED | IRQF_NO_THREAD,
        .name = "8259 cascade",
 };
 #endif /* PPC_I8259 */
@@ -186,30 +188,10 @@ static struct irqaction mpc85xxcds_8259_irqaction = {
 static void __init mpc85xx_cds_pic_init(void)
 {
        struct mpic *mpic;
-        struct resource r;
+        mpic = mpic_alloc(NULL, 0,
-        struct device_node *np = NULL;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        np = of_find_node_by_type(np, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        /* Return the mpic node */
-        of_node_put(np);
        mpic_init(mpic);
 }
@@ -330,19 +312,7 @@ static int __init mpc85xx_cds_probe(void)
        return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        return of_platform_bus_probe(NULL, of_bus_ids, NULL);
-}
-machine_device_initcall(mpc85xx_cds, declare_of_platform_devices);
 define_machine(mpc85xx_cds) {
        .name           = "MPC85xx CDS",
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 1b9a8cf1873a..eefbb91e1d61 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -35,6 +35,9 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "smp.h"
+#include "mpc85xx.h"
 #undef DEBUG
@@ -60,43 +63,27 @@ static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
 void __init mpc85xx_ds_pic_init(void)
 {
        struct mpic *mpic;
-        struct resource r;
-        struct device_node *np;
 #ifdef CONFIG_PPC_I8259
+        struct device_node *np;
        struct device_node *cascade_node = NULL;
        int cascade_irq;
 #endif
        unsigned long root = of_get_flat_dt_root();
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
        if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
-                mpic = mpic_alloc(np, r.start,
+                mpic = mpic_alloc(NULL, 0,
-                        MPIC_PRIMARY |
                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                        MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
        } else {
-                mpic = mpic_alloc(np, r.start,
+                mpic = mpic_alloc(NULL, 0,
-                          MPIC_PRIMARY | MPIC_WANTS_RESET |
+                          MPIC_WANTS_RESET |
                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                          MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
        }
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 #ifdef CONFIG_PPC_I8259
@@ -152,9 +139,6 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 /*
 * Setup the architecture
 */
-#ifdef CONFIG_SMP
-extern void __init mpc85xx_smp_init(void);
-#endif
 static void __init mpc85xx_ds_setup_arch(void)
 {
 #ifdef CONFIG_PCI
@@ -187,9 +171,7 @@ static void __init mpc85xx_ds_setup_arch(void)
        ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
 #ifdef CONFIG_SWIOTLB
        if (memblock_end_of_DRAM() > max) {
@@ -219,21 +201,9 @@ static int __init mpc8544_ds_probe(void)
        return 0;
 }
-static struct of_device_id __initdata mpc85xxds_ids[] = {
+machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
-        { .type = "soc", },
+machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
-        { .compatible = "soc", },
+machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices);
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init mpc85xxds_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
-}
-machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
-machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
-machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
 machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a23a3ff634c5..1d15a0cd2c82 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,9 @@
 #include <asm/qe_ic.h>
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
+#include "smp.h"
+#include "mpc85xx.h"
 #undef DEBUG
 #ifdef DEBUG
@@ -153,30 +156,7 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
 * Setup the architecture
 *
 */
-#ifdef CONFIG_SMP
-extern void __init mpc85xx_smp_init(void);
-#endif
 #ifdef CONFIG_QUICC_ENGINE
-static struct of_device_id mpc85xx_qe_ids[] __initdata = {
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
-        { },
-};
-static void __init mpc85xx_publish_qe_devices(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
-        if (!of_device_is_available(np)) {
-                of_node_put(np);
-                return;
-        }
-        of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
-}
 static void __init mpc85xx_mds_reset_ucc_phys(void)
 {
        struct device_node *np;
@@ -347,7 +327,6 @@ static void __init mpc85xx_mds_qeic_init(void)
        of_node_put(np);
 }
 #else
-static void __init mpc85xx_publish_qe_devices(void) { }
 static void __init mpc85xx_mds_qe_init(void) { }
 static void __init mpc85xx_mds_qeic_init(void) { }
 #endif  /* CONFIG_QUICC_ENGINE */
@@ -381,9 +360,7 @@ static void __init mpc85xx_mds_setup_arch(void)
        }
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
        mpc85xx_mds_qe_init();
@@ -429,24 +406,11 @@ machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
 static struct of_device_id mpc85xx_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        { .compatible = "fsl,rapidio-delta", },
        { .compatible = "fsl,mpc8548-guts", },
        { .compatible = "gpio-leds", },
        {},
 };
-static struct of_device_id p1021_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
 static int __init mpc85xx_publish_devices(void)
 {
        if (machine_is(mpc8568_mds))
@@ -454,23 +418,15 @@ static int __init mpc85xx_publish_devices(void)
        if (machine_is(mpc8569_mds))
                simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
+        mpc85xx_common_publish_devices();
        of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
-        mpc85xx_publish_qe_devices();
-        return 0;
-}
-static int __init p1021_publish_devices(void)
-{
-        of_platform_bus_probe(NULL, p1021_ids, NULL);
-        mpc85xx_publish_qe_devices();
        return 0;
 }
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
-machine_device_initcall(p1021_mds, p1021_publish_devices);
+machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices);
 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
@@ -478,26 +434,11 @@ machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 static void __init mpc85xx_mds_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-        struct device_node *np = NULL;
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (!np)
-                return;
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
        mpc85xx_mds_qeic_init();
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index f5ff9110c97e..ccf520e890be 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -29,6 +29,9 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "smp.h"
+#include "mpc85xx.h"
 #undef DEBUG
@@ -42,49 +45,28 @@
 void __init mpc85xx_rdb_pic_init(void)
 {
        struct mpic *mpic;
-        struct resource r;
-        struct device_node *np;
        unsigned long root = of_get_flat_dt_root();
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
        if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
-                mpic = mpic_alloc(np, r.start,
+                mpic = mpic_alloc(NULL, 0,
-                        MPIC_PRIMARY |
                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                        MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
        } else {
-                mpic = mpic_alloc(np, r.start,
+                mpic = mpic_alloc(NULL, 0,
-                  MPIC_PRIMARY | MPIC_WANTS_RESET |
+                  MPIC_WANTS_RESET |
                  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                  MPIC_SINGLE_DEST_CPU,
                  0, 256, " OpenPIC  ");
        }
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
 /*
 * Setup the architecture
 */
-#ifdef CONFIG_SMP
-extern void __init mpc85xx_smp_init(void);
-#endif
 static void __init mpc85xx_rdb_setup_arch(void)
 {
 #ifdef CONFIG_PCI
@@ -102,27 +84,12 @@ static void __init mpc85xx_rdb_setup_arch(void)
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
        printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
 }
-static struct of_device_id __initdata mpc85xxrdb_ids[] = {
+machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
-        { .type = "soc", },
+machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init mpc85xxrdb_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
-}
-machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
-machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index d7387fa7f534..538bc3f57e9d 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -28,33 +28,18 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 void __init p1010_rdb_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+          MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-        struct device_node *np;
+          MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET |
-          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
          0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
@@ -81,18 +66,7 @@ static void __init p1010_rdb_setup_arch(void)
        printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
 }
-static struct of_device_id __initdata p1010rdb_ids[] = {
+machine_device_initcall(p1010_rdb, mpc85xx_common_publish_devices);
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        {},
-};
-static int __init p1010rdb_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, p1010rdb_ids, NULL);
-}
-machine_device_initcall(p1010_rdb, p1010rdb_publish_devices);
 machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
 /*
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index fda15716fada..bb3d84f4046f 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -26,6 +26,9 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
 #include <asm/fsl_guts.h>
+#include "smp.h"
+#include "mpc85xx.h"
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
@@ -238,38 +241,15 @@ p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
 void __init p1022_ds_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                MPIC_WANTS_RESET |
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (!np) {
-                pr_err("Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                pr_err("Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                MPIC_PRIMARY | MPIC_WANTS_RESET |
                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
                MPIC_SINGLE_DEST_CPU,
                0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
-#ifdef CONFIG_SMP
-void __init mpc85xx_smp_init(void);
-#endif
 /*
 * Setup the architecture
 */
@@ -309,9 +289,7 @@ static void __init p1022_ds_setup_arch(void)
        diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
 #ifdef CONFIG_SWIOTLB
        if (memblock_end_of_DRAM() > max) {
@@ -325,10 +303,6 @@ static void __init p1022_ds_setup_arch(void)
 }
 static struct of_device_id __initdata p1022_ds_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
        /* So that the DMA channel nodes can be probed individually: */
        { .compatible = "fsl,eloplus-dma", },
        {},
@@ -336,6 +310,7 @@ static struct of_device_id __initdata p1022_ds_ids[] = {
 static int __init p1022_ds_publish_devices(void)
 {
+        mpc85xx_common_publish_devices();
        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
 }
 machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 835e0b335bfa..d951e7027bb6 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -30,19 +30,18 @@
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/mpic.h>
+#include "smp.h"
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 /* ************************************************************************
 *
 * Setup the architecture
 *
 */
-#ifdef CONFIG_SMP
-void __init mpc85xx_smp_init(void);
-#endif
 static void __init mpc85xx_rds_setup_arch(void)
 {
        struct device_node *np;
@@ -87,53 +86,19 @@ static void __init mpc85xx_rds_setup_arch(void)
                fsl_add_bridge(np, 0);
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
-}
-static struct of_device_id p1023_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .compatible = "simple-bus", },
-        {},
-};
-static int __init p1023_publish_devices(void)
-{
-        of_platform_bus_probe(NULL, p1023_ids, NULL);
-        return 0;
 }
-machine_device_initcall(p1023_rds, p1023_publish_devices);
+machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices);
 static void __init mpc85xx_rds_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-        struct device_node *np = NULL;
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (!np) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
                0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index 14632a971225..184a50784617 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -48,35 +48,16 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 static int sbc_rev;
 static void __init sbc8548_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np = NULL;
-        np = of_find_node_by_type(np, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        /* Return the mpic node */
-        of_node_put(np);
        mpic_init(mpic);
 }
@@ -149,21 +130,7 @@ static void sbc8548_show_cpuinfo(struct seq_file *m)
        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(sbc8548, mpc85xx_common_publish_devices);
-        { .name = "soc", },
-        { .type = "soc", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(sbc8548, declare_of_platform_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index cebd786dc334..940752e93051 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -32,68 +32,22 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 #ifdef CONFIG_CPM2
 #include <asm/cpm2.h>
 #include <sysdev/cpm2_pic.h>
 #endif
-#ifdef CONFIG_CPM2
-static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        int cascade_irq;
-        while ((cascade_irq = cpm2_get_irq()) >= 0)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
-#endif /* CONFIG_CPM2 */
 static void __init sbc8560_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np = NULL;
-#ifdef CONFIG_CPM2
-        int irq;
-#endif
-        np = of_find_node_by_type(np, "open-pic");
-        if (!np) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
-#ifdef CONFIG_CPM2
+        mpc85xx_cpm2_pic_init();
-        /* Setup CPM2 PIC */
-        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
-                return;
-        }
-        irq = irq_of_parse_and_map(np, 0);
-        cpm2_pic_init(np);
-        of_node_put(np);
-        irq_set_chained_handler(irq, cpm2_cascade);
-#endif
 }
 /*
@@ -208,23 +162,7 @@ static void sbc8560_show_cpuinfo(struct seq_file *m)
        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
-        { .name = "soc", },
-        { .type = "soc", },
-        { .name = "cpm", },
-        { .name = "localbus", },
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(sbc8560, declare_of_platform_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 2df4785ffd4e..ff4249044a3c 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -27,6 +27,7 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/mpic.h>
+#include "smp.h"
 extern void __early_start(void);
diff --git a/arch/powerpc/platforms/85xx/smp.h b/arch/powerpc/platforms/85xx/smp.h
new file mode 100644
index 000000000000..e2b44933ff19
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/smp.h
@@ -0,0 +1,15 @@
+#ifndef POWERPC_85XX_SMP_H_
+#define POWERPC_85XX_SMP_H_ 1
+#include <linux/init.h>
+#ifdef CONFIG_SMP
+void __init mpc85xx_smp_init(void);
+#else
+static inline void mpc85xx_smp_init(void)
+{
+        /* Nothing to do */
+}
+#endif
+#endif /* not POWERPC_85XX_SMP_H_ */
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index 747d8fb3ab82..18f635906b27 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -41,32 +41,17 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 #include "socrates_fpga_pic.h"
 static void __init socrates_pic_init(void)
 {
-        struct mpic *mpic;
-        struct resource r;
        struct device_node *np;
-        np = of_find_node_by_type(NULL, "open-pic");
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        if (!np) {
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
        np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic");
@@ -96,17 +81,7 @@ static void __init socrates_setup_arch(void)
 #endif
 }
-static struct of_device_id __initdata socrates_of_bus_ids[] = {
+machine_device_initcall(socrates, mpc85xx_common_publish_devices);
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init socrates_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL);
-}
-machine_device_initcall(socrates, socrates_publish_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index 5387e9f06bdb..e9e5234b4e76 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -40,70 +40,21 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 #ifdef CONFIG_CPM2
 #include <asm/cpm2.h>
-#include <sysdev/cpm2_pic.h>
-static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        int cascade_irq;
-        while ((cascade_irq = cpm2_get_irq()) >= 0)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
 #endif /* CONFIG_CPM2 */
 static void __init stx_gp3_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np;
-#ifdef CONFIG_CPM2
-        int irq;
-#endif
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (!np) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
-#ifdef CONFIG_CPM2
+        mpc85xx_cpm2_pic_init();
-        /* Setup CPM2 PIC */
-        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
-                return;
-        }
-        irq = irq_of_parse_and_map(np, 0);
-        if (irq == NO_IRQ) {
-                of_node_put(np);
-                printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
-                return;
-        }
-        cpm2_pic_init(np);
-        of_node_put(np);
-        irq_set_chained_handler(irq, cpm2_cascade);
-#endif
 }
 /*
@@ -144,19 +95,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(stx_gp3, mpc85xx_common_publish_devices);
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(stx_gp3, declare_of_platform_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 325de772725a..bf7c89fb75bb 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -38,70 +38,21 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "mpc85xx.h"
 #ifdef CONFIG_CPM2
 #include <asm/cpm2.h>
-#include <sysdev/cpm2_pic.h>
-static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        int cascade_irq;
-        while ((cascade_irq = cpm2_get_irq()) >= 0)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
 #endif /* CONFIG_CPM2 */
 static void __init tqm85xx_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
-        struct device_node *np;
-#ifdef CONFIG_CPM2
-        int irq;
-#endif
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (!np) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Could not map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
-#ifdef CONFIG_CPM2
+        mpc85xx_cpm2_pic_init();
-        /* Setup CPM2 PIC */
-        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
-                return;
-        }
-        irq = irq_of_parse_and_map(np, 0);
-        if (irq == NO_IRQ) {
-                of_node_put(np);
-                printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
-                return;
-        }
-        cpm2_pic_init(np);
-        of_node_put(np);
-        irq_set_chained_handler(irq, cpm2_cascade);
-#endif
 }
 /*
@@ -173,19 +124,7 @@ static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
                tqm85xx_ti1520_fixup);
-static struct of_device_id __initdata of_bus_ids[] = {
+machine_device_initcall(tqm85xx, mpc85xx_common_publish_devices);
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init declare_of_platform_devices(void)
-{
-        of_platform_bus_probe(NULL, of_bus_ids, NULL);
-        return 0;
-}
-machine_device_initcall(tqm85xx, declare_of_platform_devices);
 static const char *board[] __initdata = {
        "tqc,tqm8540",
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index a9dc5e795123..3a69f8b77de6 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -32,6 +32,9 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include "smp.h"
+#include "mpc85xx.h"
 /* A few bit definitions needed for fixups on some boards */
 #define MPC85xx_L2CTL_L2E               0x80000000 /* L2 enable */
@@ -40,29 +43,11 @@
 void __init xes_mpc85xx_pic_init(void)
 {
-        struct mpic *mpic;
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        struct resource r;
+                          MPIC_WANTS_RESET |
-        struct device_node *np;
-        np = of_find_node_by_type(NULL, "open-pic");
-        if (np == NULL) {
-                printk(KERN_ERR "Could not find open-pic node\n");
-                return;
-        }
-        if (of_address_to_resource(np, 0, &r)) {
-                printk(KERN_ERR "Failed to map mpic register space\n");
-                of_node_put(np);
-                return;
-        }
-        mpic = mpic_alloc(np, r.start,
-                          MPIC_PRIMARY | MPIC_WANTS_RESET |
                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);
-        of_node_put(np);
        mpic_init(mpic);
 }
@@ -136,9 +121,6 @@ static int primary_phb_addr;
 /*
 * Setup the architecture
 */
-#ifdef CONFIG_SMP
-extern void __init mpc85xx_smp_init(void);
-#endif
 static void __init xes_mpc85xx_setup_arch(void)
 {
 #ifdef CONFIG_PCI
@@ -172,26 +154,12 @@ static void __init xes_mpc85xx_setup_arch(void)
        }
 #endif
-#ifdef CONFIG_SMP
        mpc85xx_smp_init();
-#endif
 }
-static struct of_device_id __initdata xes_mpc85xx_ids[] = {
+machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
-        { .type = "soc", },
+machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
-        { .compatible = "soc", },
+machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
-        { .compatible = "simple-bus", },
-        { .compatible = "gianfar", },
-        {},
-};
-static int __init xes_mpc85xx_publish_devices(void)
-{
-        return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
-}
-machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
-machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
-machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
 /*
 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index b11c3535f350..569262ca499a 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -161,7 +161,7 @@ mpc86xx_time_init(void)
 static __initdata struct of_device_id of_bus_ids[] = {
        { .compatible = "simple-bus", },
-        { .compatible = "fsl,rapidio-delta", },
+        { .compatible = "fsl,srio", },
        { .compatible = "gianfar", },
        {},
 };
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c
index 8ef8960abda6..52bbfa031531 100644
--- a/arch/powerpc/platforms/86xx/pic.c
+++ b/arch/powerpc/platforms/86xx/pic.c
@@ -31,26 +31,16 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
 void __init mpc86xx_init_irq(void)
 {
-        struct mpic *mpic;
-        struct device_node *np;
-        struct resource res;
 #ifdef CONFIG_PPC_I8259
+        struct device_node *np;
        struct device_node *cascade_node = NULL;
        int cascade_irq;
 #endif
-        /* Determine PIC address. */
+        struct mpic *mpic = mpic_alloc(NULL, 0,
-        np = of_find_node_by_type(NULL, "open-pic");
+                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-        if (np == NULL)
+                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
-                return;
-        of_address_to_resource(np, 0, &res);
-        mpic = mpic_alloc(np, res.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET |
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
-                        MPIC_SINGLE_DEST_CPU,
                        0, 256, " MPIC     ");
-        of_node_put(np);
        BUG_ON(mpic == NULL);
        mpic_init(mpic);
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 3fe6d927ad70..31e1adeaa92a 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -211,6 +211,12 @@ config PPC_PASEMI_CPUFREQ
 endmenu
+menu "CPUIdle driver"
+source "drivers/cpuidle/Kconfig"
+endmenu
 config PPC601_SYNC_FIX
        bool "Workarounds for PPC601 bugs"
        depends on 6xx && (PPC_PREP || PPC_PMAC)
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index fbecae0fbb49..425db18580a2 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -174,7 +174,6 @@ config BOOKE
 config FSL_BOOKE
        bool
        depends on (E200 || E500) && PPC32
-        select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT
        default y
 # this is for common code between PPC32 & PPC64 FSL BOOKE
@@ -182,6 +181,7 @@ config PPC_FSL_BOOK3E
        bool
        select FSL_EMB_PERFMON
        select PPC_SMP_MUXED_IPI
+        select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
        default y if FSL_BOOKE
 config PTE_64BIT
@@ -236,7 +236,7 @@ config VSX
 config PPC_ICSWX
        bool "Support for PowerPC icswx coprocessor instruction"
-        depends on POWER4
+        depends on POWER4 || PPC_A2
        default n
        ---help---
@@ -252,6 +252,25 @@ config PPC_ICSWX
          If in doubt, say N here.
+config PPC_ICSWX_PID
+        bool "icswx requires direct PID management"
+        depends on PPC_ICSWX && POWER4
+        default y
+        ---help---
+          The PID register in server is used explicitly for ICSWX.  In
+          embedded systems PID managment is done by the system.
+config PPC_ICSWX_USE_SIGILL
+        bool "Should a bad CT cause a SIGILL?"
+        depends on PPC_ICSWX
+        default n
+        ---help---
+          Should a bad CT used for "non-record form ICSWX" cause an
+          illegal intruction signal or should it be silent as
+          architected.
+          If in doubt, say N here.
 config SPE
        bool "SPE Support"
        depends on E200 || (E500 && !PPC_E500MC)
@@ -290,7 +309,7 @@ config PPC_BOOK3E_MMU
 config PPC_MM_SLICES
        bool
-        default y if (PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
+        default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
        default n
 config VIRT_CPU_ACCOUNTING
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 592c3d51b817..ae9fc7bc17d6 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -1037,6 +1037,8 @@ static int __init cell_iommu_fixed_mapping_init(void)
        /* The fixed mapping is only supported on axon machines */
        np = of_find_node_by_name(NULL, "axon");
+        of_node_put(np);
        if (!np) {
                pr_debug("iommu: fixed mapping disabled, no axons found\n");
                return -1;
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 0fc9b7256126..62002a7edfed 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -184,24 +184,10 @@ static int __init cell_publish_devices(void)
 }
 machine_subsys_initcall(cell, cell_publish_devices);
-static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct mpic *mpic = irq_desc_get_handler_data(desc);
-        unsigned int virq;
-        virq = mpic_get_one_irq(mpic);
-        if (virq != NO_IRQ)
-                generic_handle_irq(virq);
-        chip->irq_eoi(&desc->irq_data);
-}
 static void __init mpic_init_IRQ(void)
 {
        struct device_node *dn;
        struct mpic *mpic;
-        unsigned int virq;
        for (dn = NULL;
             (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
@@ -211,19 +197,10 @@ static void __init mpic_init_IRQ(void)
                /* The MPIC driver will get everything it needs from the
                 * device-tree, just pass 0 to all arguments
                 */
-                mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
+                mpic = mpic_alloc(dn, 0, MPIC_SECONDARY, 0, 0, " MPIC     ");
                if (mpic == NULL)
                        continue;
                mpic_init(mpic);
-                virq = irq_of_parse_and_map(dn, 0);
-                if (virq == NO_IRQ)
-                        continue;
-                printk(KERN_INFO "%s : hooking up to IRQ %d\n",
-                       dn->full_name, virq);
-                irq_set_handler_data(virq, mpic);
-                irq_set_chained_handler(virq, cell_mpic_cascade);
        }
 }
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 122786498419..f1f17bb2c33c 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -435,8 +435,7 @@ static void __init chrp_find_openpic(void)
        if (len > 1)
                isu_size = iranges[3];
-        chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY,
+        chrp_mpic = mpic_alloc(np, opaddr, 0, isu_size, 0, " MPIC    ");
-                               isu_size, 0, " MPIC    ");
        if (chrp_mpic == NULL) {
                printk(KERN_ERR "Failed to allocate MPIC structure\n");
                goto bail;
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index 2e9bcf6444c8..9cfcf20c0560 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -148,30 +148,14 @@ static void __init holly_setup_arch(void)
 static void __init holly_init_IRQ(void)
 {
        struct mpic *mpic;
-        phys_addr_t mpic_paddr = 0;
-        struct device_node *tsi_pic;
 #ifdef CONFIG_PCI
        unsigned int cascade_pci_irq;
        struct device_node *tsi_pci;
        struct device_node *cascade_node = NULL;
 #endif
-        tsi_pic = of_find_node_by_type(NULL, "open-pic");
+        mpic = mpic_alloc(NULL, 0,
-        if (tsi_pic) {
+                        MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
-                unsigned int size;
-                const void *prop = of_get_property(tsi_pic, "reg", &size);
-                mpic_paddr = of_translate_address(tsi_pic, prop);
-        }
-        if (mpic_paddr == 0) {
-                printk(KERN_ERR "%s: No tsi108 PIC found !\n", __func__);
-                return;
-        }
-        pr_debug("%s: tsi108 pic phys_addr = 0x%x\n", __func__, (u32) mpic_paddr);
-        mpic = mpic_alloc(tsi_pic, mpic_paddr,
-                        MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
                        MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
                        24,
                        NR_IRQS-4, /* num_sources used */
@@ -179,7 +163,7 @@ static void __init holly_init_IRQ(void)
        BUG_ON(mpic == NULL);
-        mpic_assign_isu(mpic, 0, mpic_paddr + 0x100);
+        mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
        mpic_init(mpic);
@@ -204,7 +188,6 @@ static void __init holly_init_IRQ(void)
 #endif
        /* Configure MPIC outputs to CPU0 */
        tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
-        of_node_put(tsi_pic);
 }
 void holly_show_cpuinfo(struct seq_file *m)
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index 244f997de791..bcfad92c9cec 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -81,29 +81,19 @@ static void __init linkstation_setup_arch(void)
 static void __init linkstation_init_IRQ(void)
 {
        struct mpic *mpic;
-        struct device_node *dnp;
-        const u32 *prop;
-        int size;
-        phys_addr_t paddr;
-        dnp = of_find_node_by_type(NULL, "open-pic");
+        mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
-        if (dnp == NULL)
+                        4, 32, " EPIC     ");
-                return;
-        prop = of_get_property(dnp, "reg", &size);
-        paddr = (phys_addr_t)of_translate_address(dnp, prop);
-        mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, 4, 32, " EPIC     ");
        BUG_ON(mpic == NULL);
        /* PCI IRQs */
-        mpic_assign_isu(mpic, 0, paddr + 0x10200);
+        mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200);
        /* I2C */
-        mpic_assign_isu(mpic, 1, paddr + 0x11000);
+        mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000);
        /* ttyS0, ttyS1 */
-        mpic_assign_isu(mpic, 2, paddr + 0x11100);
+        mpic_assign_isu(mpic, 2, mpic->paddr + 0x11100);
        mpic_init(mpic);
 }
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index f8f33e16c6b6..f3350d786f5b 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -102,31 +102,14 @@ static void __init mpc7448_hpc2_setup_arch(void)
 static void __init mpc7448_hpc2_init_IRQ(void)
 {
        struct mpic *mpic;
-        phys_addr_t mpic_paddr = 0;
-        struct device_node *tsi_pic;
 #ifdef CONFIG_PCI
        unsigned int cascade_pci_irq;
        struct device_node *tsi_pci;
        struct device_node *cascade_node = NULL;
 #endif
-        tsi_pic = of_find_node_by_type(NULL, "open-pic");
+        mpic = mpic_alloc(NULL, 0,
-        if (tsi_pic) {
+                        MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
-                unsigned int size;
-                const void *prop = of_get_property(tsi_pic, "reg", &size);
-                mpic_paddr = of_translate_address(tsi_pic, prop);
-        }
-        if (mpic_paddr == 0) {
-                printk("%s: No tsi108 PIC found !\n", __func__);
-                return;
-        }
-        DBG("%s: tsi108 pic phys_addr = 0x%x\n", __func__,
-            (u32) mpic_paddr);
-        mpic = mpic_alloc(tsi_pic, mpic_paddr,
-                        MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
                        MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
                        24,
                        NR_IRQS-4, /* num_sources used */
@@ -134,7 +117,7 @@ static void __init mpc7448_hpc2_init_IRQ(void)
        BUG_ON(mpic == NULL);
-        mpic_assign_isu(mpic, 0, mpic_paddr + 0x100);
+        mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
        mpic_init(mpic);
@@ -159,7 +142,6 @@ static void __init mpc7448_hpc2_init_IRQ(void)
 #endif
        /* Configure MPIC outputs to CPU0 */
        tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
-        of_node_put(tsi_pic);
 }
 void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index f1eebcae9bf0..afa638834965 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -83,35 +83,17 @@ static void __init storcenter_setup_arch(void)
 static void __init storcenter_init_IRQ(void)
 {
        struct mpic *mpic;
-        struct device_node *dnp;
-        const void *prop;
-        int size;
-        phys_addr_t paddr;
-        dnp = of_find_node_by_type(NULL, "open-pic");
-        if (dnp == NULL)
-                return;
-        prop = of_get_property(dnp, "reg", &size);
-        if (prop == NULL) {
-                of_node_put(dnp);
-                return;
-        }
-        paddr = (phys_addr_t)of_translate_address(dnp, prop);
-        mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET,
-                        16, 32, " OpenPIC  ");
-        of_node_put(dnp);
+        mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
+                        16, 32, " OpenPIC  ");
        BUG_ON(mpic == NULL);
        /*
         * 16 Serial Interrupts followed by 16 Internal Interrupts.
         * I2C is the second internal, so it is at 17, 0x11020.
         */
-        mpic_assign_isu(mpic, 0, paddr + 0x10200);
+        mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200);
-        mpic_assign_isu(mpic, 1, paddr + 0x11000);
+        mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000);
        mpic_init(mpic);
 }
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index dd2e48b28508..401e3f3f74c8 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -207,6 +207,54 @@ static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
                return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
 }
+static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
+                                  int len, u32 *val)
+{
+        volatile void __iomem *addr;
+        addr = hose->cfg_addr;
+        addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
+        switch (len) {
+        case 1:
+                *val = in_8(addr);
+                break;
+        case 2:
+                *val = in_be16(addr);
+                break;
+        default:
+                *val = in_be32(addr);
+                break;
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
+                                  int len, u32 val)
+{
+        volatile void __iomem *addr;
+        addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
+        if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
+                return PCIBIOS_SUCCESSFUL;
+        switch (len) {
+        case 1:
+                out_8(addr, val);
+                break;
+        case 2:
+                out_be16(addr, val);
+                break;
+        default:
+                out_be32(addr, val);
+                break;
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
                             int offset, int len, u32 *val)
 {
@@ -217,6 +265,9 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
        if (hose == NULL)
                return PCIBIOS_DEVICE_NOT_FOUND;
+        if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
+                return u3_ht_root_read_config(hose, offset, len, val);
        if (offset > 0xff)
                return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -252,6 +303,9 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
        if (hose == NULL)
                return PCIBIOS_DEVICE_NOT_FOUND;
+        if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
+                return u3_ht_root_write_config(hose, offset, len, val);
        if (offset > 0xff)
                return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -428,6 +482,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
         * reg_property and using some accessor functions instead
         */
        hose->cfg_data = ioremap(0xf2000000, 0x02000000);
+        hose->cfg_addr = ioremap(0xf8070000, 0x1000);
        hose->first_busno = 0;
        hose->last_busno = 0xef;
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index 4c372047c94e..0bcbfe7b2c55 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -221,7 +221,7 @@ static void __init maple_init_IRQ(void)
        unsigned long openpic_addr = 0;
        int naddr, n, i, opplen, has_isus = 0;
        struct mpic *mpic;
-        unsigned int flags = MPIC_PRIMARY;
+        unsigned int flags = 0;
        /* Locate MPIC in the device-tree. Note that there is a bug
         * in Maple device-tree where the type of the controller is
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index 6f3558210554..98b7a7c13176 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -224,7 +224,7 @@ static __init void pas_init_IRQ(void)
        openpic_addr = of_read_number(opprop, naddr);
        printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
-        mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
+        mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
        nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
        if (nmiprop)
@@ -234,7 +234,7 @@ static __init void pas_init_IRQ(void)
                          mpic_flags, 0, 0, "PASEMI-OPIC");
        BUG_ON(!mpic);
-        mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
+        mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
        mpic_init(mpic);
        /* The NMI/MCK source needs to be prio 15 */
        if (nmiprop) {
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 901bfbddc3dd..7761aabfc293 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -52,13 +52,8 @@ struct device_node *of_irq_dflt_pic;
 /* Default addresses */
 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
-#define GC_LEVEL_MASK           0x3ff00000
-#define OHARE_LEVEL_MASK        0x1ff00000
-#define HEATHROW_LEVEL_MASK     0x1ff00000
 static int max_irqs;
 static int max_real_irqs;
-static u32 level_mask[4];
 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
@@ -217,8 +212,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
        for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
                int i = irq >> 5;
                bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
-                /* We must read level interrupts from the level register */
+                bits |= in_le32(&pmac_irq_hw[i]->level);
-                bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
                bits &= ppc_cached_irq_mask[i];
                if (bits == 0)
                        continue;
@@ -248,8 +242,7 @@ static unsigned int pmac_pic_get_irq(void)
        for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
                int i = irq >> 5;
                bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
-                /* We must read level interrupts from the level register */
+                bits |= in_le32(&pmac_irq_hw[i]->level);
-                bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
                bits &= ppc_cached_irq_mask[i];
                if (bits == 0)
                        continue;
@@ -284,19 +277,14 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
                             irq_hw_number_t hw)
 {
-        int level;
        if (hw >= max_irqs)
                return -EINVAL;
        /* Mark level interrupts, set delayed disable for edge ones and set
         * handlers
         */
-        level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
+        irq_set_status_flags(virq, IRQ_LEVEL);
-        if (level)
+        irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
-                irq_set_status_flags(virq, IRQ_LEVEL);
-        irq_set_chip_and_handler(virq, &pmac_pic,
-                                 level ? handle_level_irq : handle_edge_irq);
        return 0;
 }
@@ -334,21 +322,14 @@ static void __init pmac_pic_probe_oldstyle(void)
        if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
                max_irqs = max_real_irqs = 32;
-                level_mask[0] = GC_LEVEL_MASK;
        } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
                max_irqs = max_real_irqs = 32;
-                level_mask[0] = OHARE_LEVEL_MASK;
                /* We might have a second cascaded ohare */
                slave = of_find_node_by_name(NULL, "pci106b,7");
-                if (slave) {
+                if (slave)
                        max_irqs = 64;
-                        level_mask[1] = OHARE_LEVEL_MASK;
-                }
        } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
                max_irqs = max_real_irqs = 64;
-                level_mask[0] = HEATHROW_LEVEL_MASK;
-                level_mask[1] = 0;
                /* We might have a second cascaded heathrow */
                slave = of_find_node_by_name(master, "mac-io");
@@ -363,11 +344,8 @@ static void __init pmac_pic_probe_oldstyle(void)
                }
                /* We found a slave */
-                if (slave) {
+                if (slave)
                        max_irqs = 128;
-                        level_mask[2] = HEATHROW_LEVEL_MASK;
-                        level_mask[3] = 0;
-                }
        }
        BUG_ON(master == NULL);
@@ -464,18 +442,6 @@ int of_irq_map_oldworld(struct device_node *device, int index,
 }
 #endif /* CONFIG_PPC32 */
-static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct mpic *mpic = irq_desc_get_handler_data(desc);
-        unsigned int cascade_irq = mpic_get_one_irq(mpic);
-        if (cascade_irq != NO_IRQ)
-                generic_handle_irq(cascade_irq);
-        chip->irq_eoi(&desc->irq_data);
-}
 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
 {
 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
@@ -498,14 +464,8 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
                                                int master)
 {
        const char *name = master ? " MPIC 1   " : " MPIC 2   ";
-        struct resource r;
        struct mpic *mpic;
-        unsigned int flags = master ? MPIC_PRIMARY : 0;
+        unsigned int flags = master ? 0 : MPIC_SECONDARY;
-        int rc;
-        rc = of_address_to_resource(np, 0, &r);
-        if (rc)
-                return NULL;
        pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
@@ -519,7 +479,7 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
        if (master && (flags & MPIC_BIG_ENDIAN))
                flags |= MPIC_U3_HT_IRQS;
-        mpic = mpic_alloc(np, r.start, flags, 0, 0, name);
+        mpic = mpic_alloc(np, 0, flags, 0, 0, name);
        if (mpic == NULL)
                return NULL;
@@ -532,7 +492,6 @@ static int __init pmac_pic_probe_mpic(void)
 {
        struct mpic *mpic1, *mpic2;
        struct device_node *np, *master = NULL, *slave = NULL;
-        unsigned int cascade;
        /* We can have up to 2 MPICs cascaded */
        for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
@@ -568,27 +527,14 @@ static int __init pmac_pic_probe_mpic(void)
        of_node_put(master);
-        /* No slave, let's go out */
+        /* Set up a cascaded controller, if present */
-        if (slave == NULL)
+        if (slave) {
-                return 0;
+                mpic2 = pmac_setup_one_mpic(slave, 0);
+                if (mpic2 == NULL)
-        /* Get/Map slave interrupt */
+                        printk(KERN_ERR "Failed to setup slave MPIC\n");
-        cascade = irq_of_parse_and_map(slave, 0);
-        if (cascade == NO_IRQ) {
-                printk(KERN_ERR "Failed to map cascade IRQ\n");
-                return 0;
-        }
-        mpic2 = pmac_setup_one_mpic(slave, 0);
-        if (mpic2 == NULL) {
-                printk(KERN_ERR "Failed to setup slave MPIC\n");
                of_node_put(slave);
-                return 0;
        }
-        irq_set_handler_data(cascade, mpic2);
-        irq_set_chained_handler(cascade, pmac_u3_cascade);
-        of_node_put(slave);
        return 0;
 }
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 96580b189ec2..970ea1de4298 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -494,11 +494,15 @@ static int __init pmac_declare_of_platform_devices(void)
                return -1;
        np = of_find_node_by_name(NULL, "valkyrie");
-        if (np)
+        if (np) {
                of_platform_device_create(np, "valkyrie", NULL);
+                of_node_put(np);
+        }
        np = of_find_node_by_name(NULL, "platinum");
-        if (np)
+        if (np) {
                of_platform_device_create(np, "platinum", NULL);
+                of_node_put(np);
+        }
        np = of_find_node_by_type(NULL, "smu");
        if (np) {
                of_platform_device_create(np, "smu", NULL);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 9b6a820bdd7d..44d769258ebf 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -200,7 +200,7 @@ static int psurge_secondary_ipi_init(void)
        if (psurge_secondary_virq)
                rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
-                        IRQF_PERCPU, "IPI", NULL);
+                        IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
        if (rc)
                pr_err("Failed to setup secondary cpu IPI\n");
@@ -408,13 +408,13 @@ static int __init smp_psurge_kick_cpu(int nr)
 static struct irqaction psurge_irqaction = {
        .handler = psurge_ipi_intr,
-        .flags = IRQF_PERCPU,
+        .flags = IRQF_PERCPU | IRQF_NO_THREAD,
        .name = "primary IPI",
 };
 static void __init smp_psurge_setup_cpu(int cpu_nr)
 {
-        if (cpu_nr != 0)
+        if (cpu_nr != 0 || !psurge_start)
                return;
        /* reset the entry point so if we get another intr we won't
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 31853008b418..bcc3cb48a44e 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -2,4 +2,4 @@ obj-y			+= setup.o opal-takeover.o opal-wrappers.o opal.o
 obj-y                   += opal-rtc.o opal-nvram.o
 obj-$(CONFIG_SMP)       += smp.o
-obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o
+obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o pci-ioda.o
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 4a3f46d8533e..3bb07e5e43cd 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -99,3 +99,11 @@ OPAL_CALL(opal_write_oppanel,			OPAL_WRITE_OPPANEL);
 OPAL_CALL(opal_pci_map_pe_dma_window,           OPAL_PCI_MAP_PE_DMA_WINDOW);
 OPAL_CALL(opal_pci_map_pe_dma_window_real,      OPAL_PCI_MAP_PE_DMA_WINDOW_REAL);
 OPAL_CALL(opal_pci_reset,                       OPAL_PCI_RESET);
+OPAL_CALL(opal_pci_get_hub_diag_data,           OPAL_PCI_GET_HUB_DIAG_DATA);
+OPAL_CALL(opal_pci_get_phb_diag_data,           OPAL_PCI_GET_PHB_DIAG_DATA);
+OPAL_CALL(opal_pci_fence_phb,                   OPAL_PCI_FENCE_PHB);
+OPAL_CALL(opal_pci_reinit,                      OPAL_PCI_REINIT);
+OPAL_CALL(opal_pci_mask_pe_error,               OPAL_PCI_MASK_PE_ERROR);
+OPAL_CALL(opal_set_slot_led_status,             OPAL_SET_SLOT_LED_STATUS);
+OPAL_CALL(opal_get_epow_status,                 OPAL_GET_EPOW_STATUS);
+OPAL_CALL(opal_set_system_attention_led,        OPAL_SET_SYSTEM_ATTENTION_LED);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
new file mode 100644
index 000000000000..f31162cfdaa9
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -0,0 +1,1330 @@
+/*
+ * Support PCI/PCIe on PowerNV platforms
+ *
+ * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#undef DEBUG
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/msi.h>
+#include <asm/sections.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/ppc-pci.h>
+#include <asm/opal.h>
+#include <asm/iommu.h>
+#include <asm/tce.h>
+#include <asm/abs_addr.h>
+#include "powernv.h"
+#include "pci.h"
+struct resource_wrap {
+        struct list_head        link;
+        resource_size_t         size;
+        resource_size_t         align;
+        struct pci_dev          *dev;   /* Set if it's a device */
+        struct pci_bus          *bus;   /* Set if it's a bridge */
+};
+static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe,
+                       struct va_format *vaf)
+{
+        char pfix[32];
+        if (pe->pdev)
+                strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
+        else
+                sprintf(pfix, "%04x:%02x     ",
+                        pci_domain_nr(pe->pbus), pe->pbus->number);
+        return printk("pci %s%s: [PE# %.3d] %pV", level, pfix, pe->pe_number, vaf);
+}
+#define define_pe_printk_level(func, kern_level)                \
+static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...)     \
+{                                                               \
+        struct va_format vaf;                                   \
+        va_list args;                                           \
+        int r;                                                  \
+                                                                \
+        va_start(args, fmt);                                    \
+                                                                \
+        vaf.fmt = fmt;                                          \
+        vaf.va = &args;                                         \
+                                                                \
+        r = __pe_printk(kern_level, pe, &vaf);                  \
+        va_end(args);                                           \
+                                                                \
+        return r;                                               \
+}                                                               \
+define_pe_printk_level(pe_err, KERN_ERR);
+define_pe_printk_level(pe_warn, KERN_WARNING);
+define_pe_printk_level(pe_info, KERN_INFO);
+/* Calculate resource usage & alignment requirement of a single
+ * device. This will also assign all resources within the device
+ * for a given type starting at 0 for the biggest one and then
+ * assigning in decreasing order of size.
+ */
+static void __devinit pnv_ioda_calc_dev(struct pci_dev *dev, unsigned int flags,
+                                        resource_size_t *size,
+                                        resource_size_t *align)
+{
+        resource_size_t start;
+        struct resource *r;
+        int i;
+        pr_devel("  -> CDR %s\n", pci_name(dev));
+        *size = *align = 0;
+        /* Clear the resources out and mark them all unset */
+        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
+                r = &dev->resource[i];
+                if (!(r->flags & flags))
+                    continue;
+                if (r->start) {
+                        r->end -= r->start;
+                        r->start = 0;
+                }
+                r->flags |= IORESOURCE_UNSET;
+        }
+        /* We currently keep all memory resources together, we
+         * will handle prefetch & 64-bit separately in the future
+         * but for now we stick everybody in M32
+         */
+        start = 0;
+        for (;;) {
+                resource_size_t max_size = 0;
+                int max_no = -1;
+                /* Find next biggest resource */
+                for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
+                        r = &dev->resource[i];
+                        if (!(r->flags & IORESOURCE_UNSET) ||
+                            !(r->flags & flags))
+                                continue;
+                        if (resource_size(r) > max_size) {
+                                max_size = resource_size(r);
+                                max_no = i;
+                        }
+                }
+                if (max_no < 0)
+                        break;
+                r = &dev->resource[max_no];
+                if (max_size > *align)
+                        *align = max_size;
+                *size += max_size;
+                r->start = start;
+                start += max_size;
+                r->end = r->start + max_size - 1;
+                r->flags &= ~IORESOURCE_UNSET;
+                pr_devel("  ->     R%d %016llx..%016llx\n",
+                         max_no, r->start, r->end);
+        }
+        pr_devel("  <- CDR %s size=%llx align=%llx\n",
+                 pci_name(dev), *size, *align);
+}
+/* Allocate a resource "wrap" for a given device or bridge and
+ * insert it at the right position in the sorted list
+ */
+static void __devinit pnv_ioda_add_wrap(struct list_head *list,
+                                        struct pci_bus *bus,
+                                        struct pci_dev *dev,
+                                        resource_size_t size,
+                                        resource_size_t align)
+{
+        struct resource_wrap *w1, *w = kzalloc(sizeof(*w), GFP_KERNEL);
+        w->size = size;
+        w->align = align;
+        w->dev = dev;
+        w->bus = bus;
+        list_for_each_entry(w1, list, link) {
+                if (w1->align < align) {
+                        list_add_tail(&w->link, &w1->link);
+                        return;
+                }
+        }
+        list_add_tail(&w->link, list);
+}
+/* Offset device resources of a given type */
+static void __devinit pnv_ioda_offset_dev(struct pci_dev *dev,
+                                          unsigned int flags,
+                                          resource_size_t offset)
+{
+        struct resource *r;
+        int i;
+        pr_devel("  -> ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
+        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
+                r = &dev->resource[i];
+                if (r->flags & flags) {
+                        dev->resource[i].start += offset;
+                        dev->resource[i].end += offset;
+                }
+        }
+        pr_devel("  <- ODR %s [%x] +%016llx\n", pci_name(dev), flags, offset);
+}
+/* Offset bus resources (& all children) of a given type */
+static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
+                                          unsigned int flags,
+                                          resource_size_t offset)
+{
+        struct resource *r;
+        struct pci_dev *dev;
+        struct pci_bus *cbus;
+        int i;
+        pr_devel("  -> OBR %s [%x] +%016llx\n",
+                 bus->self ? pci_name(bus->self) : "root", flags, offset);
+        for (i = 0; i < 2; i++) {
+                r = bus->resource[i];
+                if (r && (r->flags & flags)) {
+                        bus->resource[i]->start += offset;
+                        bus->resource[i]->end += offset;
+                }
+        }
+        list_for_each_entry(dev, &bus->devices, bus_list)
+                pnv_ioda_offset_dev(dev, flags, offset);
+        list_for_each_entry(cbus, &bus->children, node)
+                pnv_ioda_offset_bus(cbus, flags, offset);
+        pr_devel("  <- OBR %s [%x]\n",
+                 bus->self ? pci_name(bus->self) : "root", flags);
+}
+/* This is the guts of our IODA resource allocation. This is called
+ * recursively for each bus in the system. It calculates all the
+ * necessary size and requirements for children and assign them
+ * resources such that:
+ *
+ *   - Each function fits in it's own contiguous set of IO/M32
+ *     segment
+ *
+ *   - All segments behind a P2P bridge are contiguous and obey
+ *     alignment constraints of those bridges
+ */
+static void __devinit pnv_ioda_calc_bus(struct pci_bus *bus, unsigned int flags,
+                                        resource_size_t *size,
+                                        resource_size_t *align)
+{
+        struct pci_controller *hose = pci_bus_to_host(bus);
+        struct pnv_phb *phb = hose->private_data;
+        resource_size_t dev_size, dev_align, start;
+        resource_size_t min_align, min_balign;
+        struct pci_dev *cdev;
+        struct pci_bus *cbus;
+        struct list_head head;
+        struct resource_wrap *w;
+        unsigned int bres;
+        *size = *align = 0;
+        pr_devel("-> CBR %s [%x]\n",
+                 bus->self ? pci_name(bus->self) : "root", flags);
+        /* Calculate alignment requirements based on the type
+         * of resource we are working on
+         */
+        if (flags & IORESOURCE_IO) {
+                bres = 0;
+                min_align = phb->ioda.io_segsize;
+                min_balign = 0x1000;
+        } else {
+                bres = 1;
+                min_align = phb->ioda.m32_segsize;
+                min_balign = 0x100000;
+        }
+        /* Gather all our children resources ordered by alignment */
+        INIT_LIST_HEAD(&head);
+        /*   - Busses */
+        list_for_each_entry(cbus, &bus->children, node) {
+                pnv_ioda_calc_bus(cbus, flags, &dev_size, &dev_align);
+                pnv_ioda_add_wrap(&head, cbus, NULL, dev_size, dev_align);
+        }
+        /*   - Devices */
+        list_for_each_entry(cdev, &bus->devices, bus_list) {
+                pnv_ioda_calc_dev(cdev, flags, &dev_size, &dev_align);
+                /* Align them to segment size */
+                if (dev_align < min_align)
+                        dev_align = min_align;
+                pnv_ioda_add_wrap(&head, NULL, cdev, dev_size, dev_align);
+        }
+        if (list_empty(&head))
+                goto empty;
+        /* Now we can do two things: assign offsets to them within that
+         * level and get our total alignment & size requirements. The
+         * assignment algorithm is going to be uber-trivial for now, we
+         * can try to be smarter later at filling out holes.
+         */
+        start = bus->self ? 0 : bus->resource[bres]->start;
+        /* Don't hand out IO 0 */
+        if ((flags & IORESOURCE_IO) && !bus->self)
+                start += 0x1000;
+        while(!list_empty(&head)) {
+                w = list_first_entry(&head, struct resource_wrap, link);
+                list_del(&w->link);
+                if (w->size) {
+                        if (start) {
+                                start = ALIGN(start, w->align);
+                                if (w->dev)
+                                        pnv_ioda_offset_dev(w->dev,flags,start);
+                                else if (w->bus)
+                                        pnv_ioda_offset_bus(w->bus,flags,start);
+                        }
+                        if (w->align > *align)
+                                *align = w->align;
+                }
+                start += w->size;
+                kfree(w);
+        }
+        *size = start;
+        /* Align and setup bridge resources */
+        *align = max_t(resource_size_t, *align,
+                       max_t(resource_size_t, min_align, min_balign));
+        *size = ALIGN(*size,
+                      max_t(resource_size_t, min_align, min_balign));
+ empty:
+        /* Only setup P2P's, not the PHB itself */
+        if (bus->self) {
+                WARN_ON(bus->resource[bres] == NULL);
+                bus->resource[bres]->start = 0;
+                bus->resource[bres]->flags = (*size) ? flags : 0;
+                bus->resource[bres]->end = (*size) ? (*size - 1) : 0;
+                /* Clear prefetch bus resources for now */
+                bus->resource[2]->flags = 0;
+        }
+        pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
+                 bus->self ? pci_name(bus->self) : "root", flags,*size,*align);
+}
+static struct pci_dn *pnv_ioda_get_pdn(struct pci_dev *dev)
+{
+        struct device_node *np;
+        np = pci_device_to_OF_node(dev);
+        if (!np)
+                return NULL;
+        return PCI_DN(np);
+}
+static void __devinit pnv_ioda_setup_pe_segments(struct pci_dev *dev)
+{
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+        unsigned int pe, i;
+        resource_size_t pos;
+        struct resource io_res;
+        struct resource m32_res;
+        struct pci_bus_region region;
+        int rc;
+        /* Anything not referenced in the device-tree gets PE#0 */
+        pe = pdn ? pdn->pe_number : 0;
+        /* Calculate the device min/max */
+        io_res.start = m32_res.start = (resource_size_t)-1;
+        io_res.end = m32_res.end = 0;
+        io_res.flags = IORESOURCE_IO;
+        m32_res.flags = IORESOURCE_MEM;
+        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
+                struct resource *r = NULL;
+                if (dev->resource[i].flags & IORESOURCE_IO)
+                        r = &io_res;
+                if (dev->resource[i].flags & IORESOURCE_MEM)
+                        r = &m32_res;
+                if (!r)
+                        continue;
+                if (dev->resource[i].start < r->start)
+                        r->start = dev->resource[i].start;
+                if (dev->resource[i].end > r->end)
+                        r->end = dev->resource[i].end;
+        }
+        /* Setup IO segments */
+        if (io_res.start < io_res.end) {
+                pcibios_resource_to_bus(dev, &region, &io_res);
+                pos = region.start;
+                i = pos / phb->ioda.io_segsize;
+                while(i < phb->ioda.total_pe && pos <= region.end) {
+                        if (phb->ioda.io_segmap[i]) {
+                                pr_err("%s: Trying to use IO seg #%d which is"
+                                       " already used by PE# %d\n",
+                                       pci_name(dev), i,
+                                       phb->ioda.io_segmap[i]);
+                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
+                                break;
+                        }
+                        phb->ioda.io_segmap[i] = pe;
+                        rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
+                                                         OPAL_IO_WINDOW_TYPE,
+                                                         0, i);
+                        if (rc != OPAL_SUCCESS) {
+                                pr_err("%s: OPAL error %d setting up mapping"
+                                       " for IO seg# %d\n",
+                                       pci_name(dev), rc, i);
+                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
+                                break;
+                        }
+                        pos += phb->ioda.io_segsize;
+                        i++;
+                };
+        }
+        /* Setup M32 segments */
+        if (m32_res.start < m32_res.end) {
+                pcibios_resource_to_bus(dev, &region, &m32_res);
+                pos = region.start;
+                i = pos / phb->ioda.m32_segsize;
+                while(i < phb->ioda.total_pe && pos <= region.end) {
+                        if (phb->ioda.m32_segmap[i]) {
+                                pr_err("%s: Trying to use M32 seg #%d which is"
+                                       " already used by PE# %d\n",
+                                       pci_name(dev), i,
+                                       phb->ioda.m32_segmap[i]);
+                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
+                                break;
+                        }
+                        phb->ioda.m32_segmap[i] = pe;
+                        rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe,
+                                                         OPAL_M32_WINDOW_TYPE,
+                                                         0, i);
+                        if (rc != OPAL_SUCCESS) {
+                                pr_err("%s: OPAL error %d setting up mapping"
+                                       " for M32 seg# %d\n",
+                                       pci_name(dev), rc, i);
+                                /* XXX DO SOMETHING TO DISABLE DEVICE ? */
+                                break;
+                        }
+                        pos += phb->ioda.m32_segsize;
+                        i++;
+                }
+        }
+}
+/* Check if a resource still fits in the total IO or M32 range
+ * for a given PHB
+ */
+static int __devinit pnv_ioda_resource_fit(struct pci_controller *hose,
+                                           struct resource *r)
+{
+        struct resource *bounds;
+        if (r->flags & IORESOURCE_IO)
+                bounds = &hose->io_resource;
+        else if (r->flags & IORESOURCE_MEM)
+                bounds = &hose->mem_resources[0];
+        else
+                return 1;
+        if (r->start >= bounds->start && r->end <= bounds->end)
+                return 1;
+        r->flags = 0;
+        return 0;
+}
+static void __devinit pnv_ioda_update_resources(struct pci_bus *bus)
+{
+        struct pci_controller *hose = pci_bus_to_host(bus);
+        struct pci_bus *cbus;
+        struct pci_dev *cdev;
+        unsigned int i;
+        /* We used to clear all device enables here. However it looks like
+         * clearing MEM enable causes Obsidian (IPR SCS) to go bonkers,
+         * and shoot fatal errors to the PHB which in turns fences itself
+         * and we can't recover from that ... yet. So for now, let's leave
+         * the enables as-is and hope for the best.
+         */
+        /* Check if bus resources fit in our IO or M32 range */
+        for (i = 0; bus->self && (i < 2); i++) {
+                struct resource *r = bus->resource[i];
+                if (r && !pnv_ioda_resource_fit(hose, r))
+                        pr_err("%s: Bus %d resource %d disabled, no room\n",
+                               pci_name(bus->self), bus->number, i);
+        }
+        /* Update self if it's not a PHB */
+        if (bus->self)
+                pci_setup_bridge(bus);
+        /* Update child devices */
+        list_for_each_entry(cdev, &bus->devices, bus_list) {
+                /* Check if resource fits, if not, disabled it */
+                for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
+                        struct resource *r = &cdev->resource[i];
+                        if (!pnv_ioda_resource_fit(hose, r))
+                                pr_err("%s: Resource %d disabled, no room\n",
+                                       pci_name(cdev), i);
+                }
+                /* Assign segments */
+                pnv_ioda_setup_pe_segments(cdev);
+                /* Update HW BARs */
+                for (i = 0; i <= PCI_ROM_RESOURCE; i++)
+                        pci_update_resource(cdev, i);
+        }
+        /* Update child busses */
+        list_for_each_entry(cbus, &bus->children, node)
+                pnv_ioda_update_resources(cbus);
+}
+static int __devinit pnv_ioda_alloc_pe(struct pnv_phb *phb)
+{
+        unsigned long pe;
+        do {
+                pe = find_next_zero_bit(phb->ioda.pe_alloc,
+                                        phb->ioda.total_pe, 0);
+                if (pe >= phb->ioda.total_pe)
+                        return IODA_INVALID_PE;
+        } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
+        phb->ioda.pe_array[pe].pe_number = pe;
+        return pe;
+}
+static void __devinit pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
+{
+        WARN_ON(phb->ioda.pe_array[pe].pdev);
+        memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
+        clear_bit(pe, phb->ioda.pe_alloc);
+}
+/* Currently those 2 are only used when MSIs are enabled, this will change
+ * but in the meantime, we need to protect them to avoid warnings
+ */
+#ifdef CONFIG_PCI_MSI
+static struct pnv_ioda_pe * __devinit __pnv_ioda_get_one_pe(struct pci_dev *dev)
+{
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+        if (!pdn)
+                return NULL;
+        if (pdn->pe_number == IODA_INVALID_PE)
+                return NULL;
+        return &phb->ioda.pe_array[pdn->pe_number];
+}
+static struct pnv_ioda_pe * __devinit pnv_ioda_get_pe(struct pci_dev *dev)
+{
+        struct pnv_ioda_pe *pe = __pnv_ioda_get_one_pe(dev);
+        while (!pe && dev->bus->self) {
+                dev = dev->bus->self;
+                pe = __pnv_ioda_get_one_pe(dev);
+                if (pe)
+                        pe = pe->bus_pe;
+        }
+        return pe;
+}
+#endif /* CONFIG_PCI_MSI */
+static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
+                                           struct pnv_ioda_pe *pe)
+{
+        struct pci_dev *parent;
+        uint8_t bcomp, dcomp, fcomp;
+        long rc, rid_end, rid;
+        /* Bus validation ? */
+        if (pe->pbus) {
+                int count;
+                dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
+                fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
+                parent = pe->pbus->self;
+                count = pe->pbus->subordinate - pe->pbus->secondary + 1;
+                switch(count) {
+                case  1: bcomp = OpalPciBusAll;         break;
+                case  2: bcomp = OpalPciBus7Bits;       break;
+                case  4: bcomp = OpalPciBus6Bits;       break;
+                case  8: bcomp = OpalPciBus5Bits;       break;
+                case 16: bcomp = OpalPciBus4Bits;       break;
+                case 32: bcomp = OpalPciBus3Bits;       break;
+                default:
+                        pr_err("%s: Number of subordinate busses %d"
+                               " unsupported\n",
+                               pci_name(pe->pbus->self), count);
+                        /* Do an exact match only */
+                        bcomp = OpalPciBusAll;
+                }
+                rid_end = pe->rid + (count << 8);
+        } else {
+                parent = pe->pdev->bus->self;
+                bcomp = OpalPciBusAll;
+                dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
+                fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
+                rid_end = pe->rid + 1;
+        }
+        /* Associate PE in PELT */
+        rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
+                             bcomp, dcomp, fcomp, OPAL_MAP_PE);
+        if (rc) {
+                pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
+                return -ENXIO;
+        }
+        opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
+                                  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
+        /* Add to all parents PELT-V */
+        while (parent) {
+                struct pci_dn *pdn = pnv_ioda_get_pdn(parent);
+                if (pdn && pdn->pe_number != IODA_INVALID_PE) {
+                        rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
+                                                pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
+                        /* XXX What to do in case of error ? */
+                }
+                parent = parent->bus->self;
+        }
+        /* Setup reverse map */
+        for (rid = pe->rid; rid < rid_end; rid++)
+                phb->ioda.pe_rmap[rid] = pe->pe_number;
+        /* Setup one MVTs on IODA1 */
+        if (phb->type == PNV_PHB_IODA1) {
+                pe->mve_number = pe->pe_number;
+                rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
+                                      pe->pe_number);
+                if (rc) {
+                        pe_err(pe, "OPAL error %ld setting up MVE %d\n",
+                               rc, pe->mve_number);
+                        pe->mve_number = -1;
+                } else {
+                        rc = opal_pci_set_mve_enable(phb->opal_id,
+                                                     pe->mve_number, OPAL_ENABLE_MVE);
+                        if (rc) {
+                                pe_err(pe, "OPAL error %ld enabling MVE %d\n",
+                                       rc, pe->mve_number);
+                                pe->mve_number = -1;
+                        }
+                }
+        } else if (phb->type == PNV_PHB_IODA2)
+                pe->mve_number = 0;
+        return 0;
+}
+static void __devinit pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
+                                                 struct pnv_ioda_pe *pe)
+{
+        struct pnv_ioda_pe *lpe;
+        list_for_each_entry(lpe, &phb->ioda.pe_list, link) {
+                if (lpe->dma_weight < pe->dma_weight) {
+                        list_add_tail(&pe->link, &lpe->link);
+                        return;
+                }
+        }
+        list_add_tail(&pe->link, &phb->ioda.pe_list);
+}
+static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
+{
+        /* This is quite simplistic. The "base" weight of a device
+         * is 10. 0 means no DMA is to be accounted for it.
+         */
+        /* If it's a bridge, no DMA */
+        if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
+                return 0;
+        /* Reduce the weight of slow USB controllers */
+        if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
+            dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
+            dev->class == PCI_CLASS_SERIAL_USB_EHCI)
+                return 3;
+        /* Increase the weight of RAID (includes Obsidian) */
+        if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
+                return 15;
+        /* Default */
+        return 10;
+}
+static struct pnv_ioda_pe * __devinit pnv_ioda_setup_dev_PE(struct pci_dev *dev)
+{
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+        struct pnv_ioda_pe *pe;
+        int pe_num;
+        if (!pdn) {
+                pr_err("%s: Device tree node not associated properly\n",
+                           pci_name(dev));
+                return NULL;
+        }
+        if (pdn->pe_number != IODA_INVALID_PE)
+                return NULL;
+        /* PE#0 has been pre-set */
+        if (dev->bus->number == 0)
+                pe_num = 0;
+        else
+                pe_num = pnv_ioda_alloc_pe(phb);
+        if (pe_num == IODA_INVALID_PE) {
+                pr_warning("%s: Not enough PE# available, disabling device\n",
+                           pci_name(dev));
+                return NULL;
+        }
+        /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
+         * pointer in the PE data structure, both should be destroyed at the
+         * same time. However, this needs to be looked at more closely again
+         * once we actually start removing things (Hotplug, SR-IOV, ...)
+         *
+         * At some point we want to remove the PDN completely anyways
+         */
+        pe = &phb->ioda.pe_array[pe_num];
+        pci_dev_get(dev);
+        pdn->pcidev = dev;
+        pdn->pe_number = pe_num;
+        pe->pdev = dev;
+        pe->pbus = NULL;
+        pe->tce32_seg = -1;
+        pe->mve_number = -1;
+        pe->rid = dev->bus->number << 8 | pdn->devfn;
+        pe_info(pe, "Associated device to PE\n");
+        if (pnv_ioda_configure_pe(phb, pe)) {
+                /* XXX What do we do here ? */
+                if (pe_num)
+                        pnv_ioda_free_pe(phb, pe_num);
+                pdn->pe_number = IODA_INVALID_PE;
+                pe->pdev = NULL;
+                pci_dev_put(dev);
+                return NULL;
+        }
+        /* Assign a DMA weight to the device */
+        pe->dma_weight = pnv_ioda_dma_weight(dev);
+        if (pe->dma_weight != 0) {
+                phb->ioda.dma_weight += pe->dma_weight;
+                phb->ioda.dma_pe_count++;
+        }
+        /* Link the PE */
+        pnv_ioda_link_pe_by_weight(phb, pe);
+        return pe;
+}
+static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
+{
+        struct pci_dev *dev;
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+                if (pdn == NULL) {
+                        pr_warn("%s: No device node associated with device !\n",
+                                pci_name(dev));
+                        continue;
+                }
+                pci_dev_get(dev);
+                pdn->pcidev = dev;
+                pdn->pe_number = pe->pe_number;
+                pe->dma_weight += pnv_ioda_dma_weight(dev);
+                if (dev->subordinate)
+                        pnv_ioda_setup_same_PE(dev->subordinate, pe);
+        }
+}
+static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
+                                            struct pnv_ioda_pe *ppe)
+{
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct pci_bus *bus = dev->subordinate;
+        struct pnv_ioda_pe *pe;
+        int pe_num;
+        if (!bus) {
+                pr_warning("%s: Bridge without a subordinate bus !\n",
+                           pci_name(dev));
+                return;
+        }
+        pe_num = pnv_ioda_alloc_pe(phb);
+        if (pe_num == IODA_INVALID_PE) {
+                pr_warning("%s: Not enough PE# available, disabling bus\n",
+                           pci_name(dev));
+                return;
+        }
+        pe = &phb->ioda.pe_array[pe_num];
+        ppe->bus_pe = pe;
+        pe->pbus = bus;
+        pe->pdev = NULL;
+        pe->tce32_seg = -1;
+        pe->mve_number = -1;
+        pe->rid = bus->secondary << 8;
+        pe->dma_weight = 0;
+        pe_info(pe, "Secondary busses %d..%d associated with PE\n",
+                bus->secondary, bus->subordinate);
+        if (pnv_ioda_configure_pe(phb, pe)) {
+                /* XXX What do we do here ? */
+                if (pe_num)
+                        pnv_ioda_free_pe(phb, pe_num);
+                pe->pbus = NULL;
+                return;
+        }
+        /* Associate it with all child devices */
+        pnv_ioda_setup_same_PE(bus, pe);
+        /* Account for one DMA PE if at least one DMA capable device exist
+         * below the bridge
+         */
+        if (pe->dma_weight != 0) {
+                phb->ioda.dma_weight += pe->dma_weight;
+                phb->ioda.dma_pe_count++;
+        }
+        /* Link the PE */
+        pnv_ioda_link_pe_by_weight(phb, pe);
+}
+static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
+{
+        struct pci_dev *dev;
+        struct pnv_ioda_pe *pe;
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                pe = pnv_ioda_setup_dev_PE(dev);
+                if (pe == NULL)
+                        continue;
+                /* Leaving the PCIe domain ... single PE# */
+                if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
+                        pnv_ioda_setup_bus_PE(dev, pe);
+                else if (dev->subordinate)
+                        pnv_ioda_setup_PEs(dev->subordinate);
+        }
+}
+static void __devinit pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb,
+                                                 struct pci_dev *dev)
+{
+        /* We delay DMA setup after we have assigned all PE# */
+}
+static void __devinit pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
+                                             struct pci_bus *bus)
+{
+        struct pci_dev *dev;
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                set_iommu_table_base(&dev->dev, &pe->tce32_table);
+                if (dev->subordinate)
+                        pnv_ioda_setup_bus_dma(pe, dev->subordinate);
+        }
+}
+static void __devinit pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
+                                                struct pnv_ioda_pe *pe,
+                                                unsigned int base,
+                                                unsigned int segs)
+{
+        struct page *tce_mem = NULL;
+        const __be64 *swinvp;
+        struct iommu_table *tbl;
+        unsigned int i;
+        int64_t rc;
+        void *addr;
+        /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
+#define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
+        /* XXX FIXME: Handle 64-bit only DMA devices */
+        /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
+        /* XXX FIXME: Allocate multi-level tables on PHB3 */
+        /* We shouldn't already have a 32-bit DMA associated */
+        if (WARN_ON(pe->tce32_seg >= 0))
+                return;
+        /* Grab a 32-bit TCE table */
+        pe->tce32_seg = base;
+        pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
+                (base << 28), ((base + segs) << 28) - 1);
+        /* XXX Currently, we allocate one big contiguous table for the
+         * TCEs. We only really need one chunk per 256M of TCE space
+         * (ie per segment) but that's an optimization for later, it
+         * requires some added smarts with our get/put_tce implementation
+         */
+        tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
+                                   get_order(TCE32_TABLE_SIZE * segs));
+        if (!tce_mem) {
+                pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
+                goto fail;
+        }
+        addr = page_address(tce_mem);
+        memset(addr, 0, TCE32_TABLE_SIZE * segs);
+        /* Configure HW */
+        for (i = 0; i < segs; i++) {
+                rc = opal_pci_map_pe_dma_window(phb->opal_id,
+                                              pe->pe_number,
+                                              base + i, 1,
+                                              __pa(addr) + TCE32_TABLE_SIZE * i,
+                                              TCE32_TABLE_SIZE, 0x1000);
+                if (rc) {
+                        pe_err(pe, " Failed to configure 32-bit TCE table,"
+                               " err %ld\n", rc);
+                        goto fail;
+                }
+        }
+        /* Setup linux iommu table */
+        tbl = &pe->tce32_table;
+        pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
+                                  base << 28);
+        /* OPAL variant of P7IOC SW invalidated TCEs */
+        swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
+        if (swinvp) {
+                /* We need a couple more fields -- an address and a data
+                 * to or.  Since the bus is only printed out on table free
+                 * errors, and on the first pass the data will be a relative
+                 * bus number, print that out instead.
+                 */
+                tbl->it_busno = 0;
+                tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
+                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE
+                        | TCE_PCI_SWINV_PAIR;
+        }
+        iommu_init_table(tbl, phb->hose->node);
+        if (pe->pdev)
+                set_iommu_table_base(&pe->pdev->dev, tbl);
+        else
+                pnv_ioda_setup_bus_dma(pe, pe->pbus);
+        return;
+ fail:
+        /* XXX Failure: Try to fallback to 64-bit only ? */
+        if (pe->tce32_seg >= 0)
+                pe->tce32_seg = -1;
+        if (tce_mem)
+                __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
+}
+static void __devinit pnv_ioda_setup_dma(struct pnv_phb *phb)
+{
+        struct pci_controller *hose = phb->hose;
+        unsigned int residual, remaining, segs, tw, base;
+        struct pnv_ioda_pe *pe;
+        /* If we have more PE# than segments available, hand out one
+         * per PE until we run out and let the rest fail. If not,
+         * then we assign at least one segment per PE, plus more based
+         * on the amount of devices under that PE
+         */
+        if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
+                residual = 0;
+        else
+                residual = phb->ioda.tce32_count -
+                        phb->ioda.dma_pe_count;
+        pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
+                hose->global_number, phb->ioda.tce32_count);
+        pr_info("PCI: %d PE# for a total weight of %d\n",
+                phb->ioda.dma_pe_count, phb->ioda.dma_weight);
+        /* Walk our PE list and configure their DMA segments, hand them
+         * out one base segment plus any residual segments based on
+         * weight
+         */
+        remaining = phb->ioda.tce32_count;
+        tw = phb->ioda.dma_weight;
+        base = 0;
+        list_for_each_entry(pe, &phb->ioda.pe_list, link) {
+                if (!pe->dma_weight)
+                        continue;
+                if (!remaining) {
+                        pe_warn(pe, "No DMA32 resources available\n");
+                        continue;
+                }
+                segs = 1;
+                if (residual) {
+                        segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
+                        if (segs > remaining)
+                                segs = remaining;
+                }
+                pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
+                        pe->dma_weight, segs);
+                pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
+                remaining -= segs;
+                base += segs;
+        }
+}
+#ifdef CONFIG_PCI_MSI
+static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
+                                  unsigned int hwirq, unsigned int is_64,
+                                  struct msi_msg *msg)
+{
+        struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
+        unsigned int xive_num = hwirq - phb->msi_base;
+        uint64_t addr64;
+        uint32_t addr32, data;
+        int rc;
+        /* No PE assigned ? bail out ... no MSI for you ! */
+        if (pe == NULL)
+                return -ENXIO;
+        /* Check if we have an MVE */
+        if (pe->mve_number < 0)
+                return -ENXIO;
+        /* Assign XIVE to PE */
+        rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
+        if (rc) {
+                pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
+                        pci_name(dev), rc, xive_num);
+                return -EIO;
+        }
+        if (is_64) {
+                rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
+                                     &addr64, &data);
+                if (rc) {
+                        pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
+                                pci_name(dev), rc);
+                        return -EIO;
+                }
+                msg->address_hi = addr64 >> 32;
+                msg->address_lo = addr64 & 0xfffffffful;
+        } else {
+                rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
+                                     &addr32, &data);
+                if (rc) {
+                        pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
+                                pci_name(dev), rc);
+                        return -EIO;
+                }
+                msg->address_hi = 0;
+                msg->address_lo = addr32;
+        }
+        msg->data = data;
+        pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
+                 " address=%x_%08x data=%x PE# %d\n",
+                 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
+                 msg->address_hi, msg->address_lo, data, pe->pe_number);
+        return 0;
+}
+static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
+{
+        unsigned int bmap_size;
+        const __be32 *prop = of_get_property(phb->hose->dn,
+                                             "ibm,opal-msi-ranges", NULL);
+        if (!prop) {
+                /* BML Fallback */
+                prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
+        }
+        if (!prop)
+                return;
+        phb->msi_base = be32_to_cpup(prop);
+        phb->msi_count = be32_to_cpup(prop + 1);
+        bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
+        phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
+        if (!phb->msi_map) {
+                pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
+                       phb->hose->global_number);
+                return;
+        }
+        phb->msi_setup = pnv_pci_ioda_msi_setup;
+        phb->msi32_support = 1;
+        pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
+                phb->msi_count, phb->msi_base);
+}
+#else
+static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
+#endif /* CONFIG_PCI_MSI */
+/* This is the starting point of our IODA specific resource
+ * allocation process
+ */
+static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
+{
+        resource_size_t size, align;
+        struct pci_bus *child;
+        /* Associate PEs per functions */
+        pnv_ioda_setup_PEs(hose->bus);
+        /* Calculate all resources */
+        pnv_ioda_calc_bus(hose->bus, IORESOURCE_IO, &size, &align);
+        pnv_ioda_calc_bus(hose->bus, IORESOURCE_MEM, &size, &align);
+        /* Apply then to HW */
+        pnv_ioda_update_resources(hose->bus);
+        /* Setup DMA */
+        pnv_ioda_setup_dma(hose->private_data);
+        /* Configure PCI Express settings */
+        list_for_each_entry(child, &hose->bus->children, node) {
+                struct pci_dev *self = child->self;
+                if (!self)
+                        continue;
+                pcie_bus_configure_settings(child, self->pcie_mpss);
+        }
+}
+/* Prevent enabling devices for which we couldn't properly
+ * assign a PE
+ */
+static int __devinit pnv_pci_enable_device_hook(struct pci_dev *dev)
+{
+        struct pci_dn *pdn = pnv_ioda_get_pdn(dev);
+        if (!pdn || pdn->pe_number == IODA_INVALID_PE)
+                return -EINVAL;
+        return 0;
+}
+static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
+                               u32 devfn)
+{
+        return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
+}
+void __init pnv_pci_init_ioda1_phb(struct device_node *np)
+{
+        struct pci_controller *hose;
+        static int primary = 1;
+        struct pnv_phb *phb;
+        unsigned long size, m32map_off, iomap_off, pemap_off;
+        const u64 *prop64;
+        u64 phb_id;
+        void *aux;
+        long rc;
+        pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name);
+        prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
+        if (!prop64) {
+                pr_err("  Missing \"ibm,opal-phbid\" property !\n");
+                return;
+        }
+        phb_id = be64_to_cpup(prop64);
+        pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
+        phb = alloc_bootmem(sizeof(struct pnv_phb));
+        if (phb) {
+                memset(phb, 0, sizeof(struct pnv_phb));
+                phb->hose = hose = pcibios_alloc_controller(np);
+        }
+        if (!phb || !phb->hose) {
+                pr_err("PCI: Failed to allocate PCI controller for %s\n",
+                       np->full_name);
+                return;
+        }
+        spin_lock_init(&phb->lock);
+        /* XXX Use device-tree */
+        hose->first_busno = 0;
+        hose->last_busno = 0xff;
+        hose->private_data = phb;
+        phb->opal_id = phb_id;
+        phb->type = PNV_PHB_IODA1;
+        /* Detect specific models for error handling */
+        if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
+                phb->model = PNV_PHB_MODEL_P7IOC;
+        else
+                phb->model = PNV_PHB_MODEL_UNKNOWN;
+        /* We parse "ranges" now since we need to deduce the register base
+         * from the IO base
+         */
+        pci_process_bridge_OF_ranges(phb->hose, np, primary);
+        primary = 0;
+        /* Magic formula from Milton */
+        phb->regs = of_iomap(np, 0);
+        if (phb->regs == NULL)
+                pr_err("  Failed to map registers !\n");
+        /* XXX This is hack-a-thon. This needs to be changed so that:
+         *  - we obtain stuff like PE# etc... from device-tree
+         *  - we properly re-allocate M32 ourselves
+         *    (the OFW one isn't very good)
+         */
+        /* Initialize more IODA stuff */
+        phb->ioda.total_pe = 128;
+        phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
+        /* OFW Has already off top 64k of M32 space (MSI space) */
+        phb->ioda.m32_size += 0x10000;
+        phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
+        phb->ioda.m32_pci_base = hose->mem_resources[0].start -
+                hose->pci_mem_offset;
+        phb->ioda.io_size = hose->pci_io_size;
+        phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
+        phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
+        /* Allocate aux data & arrays */
+        size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
+        m32map_off = size;
+        size += phb->ioda.total_pe;
+        iomap_off = size;
+        size += phb->ioda.total_pe;
+        pemap_off = size;
+        size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
+        aux = alloc_bootmem(size);
+        memset(aux, 0, size);
+        phb->ioda.pe_alloc = aux;
+        phb->ioda.m32_segmap = aux + m32map_off;
+        phb->ioda.io_segmap = aux + iomap_off;
+        phb->ioda.pe_array = aux + pemap_off;
+        set_bit(0, phb->ioda.pe_alloc);
+        INIT_LIST_HEAD(&phb->ioda.pe_list);
+        /* Calculate how many 32-bit TCE segments we have */
+        phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
+        /* Clear unusable m64 */
+        hose->mem_resources[1].flags = 0;
+        hose->mem_resources[1].start = 0;
+        hose->mem_resources[1].end = 0;
+        hose->mem_resources[2].flags = 0;
+        hose->mem_resources[2].start = 0;
+        hose->mem_resources[2].end = 0;
+#if 0
+        rc = opal_pci_set_phb_mem_window(opal->phb_id,
+                                         window_type,
+                                         window_num,
+                                         starting_real_address,
+                                         starting_pci_address,
+                                         segment_size);
+#endif
+        pr_info("  %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
+                phb->ioda.total_pe,
+                phb->ioda.m32_size, phb->ioda.m32_segsize,
+                phb->ioda.io_size, phb->ioda.io_segsize);
+        if (phb->regs)  {
+                pr_devel(" BUID     = 0x%016llx\n", in_be64(phb->regs + 0x100));
+                pr_devel(" PHB2_CR  = 0x%016llx\n", in_be64(phb->regs + 0x160));
+                pr_devel(" IO_BAR   = 0x%016llx\n", in_be64(phb->regs + 0x170));
+                pr_devel(" IO_BAMR  = 0x%016llx\n", in_be64(phb->regs + 0x178));
+                pr_devel(" IO_SAR   = 0x%016llx\n", in_be64(phb->regs + 0x180));
+                pr_devel(" M32_BAR  = 0x%016llx\n", in_be64(phb->regs + 0x190));
+                pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198));
+                pr_devel(" M32_SAR  = 0x%016llx\n", in_be64(phb->regs + 0x1a0));
+        }
+        phb->hose->ops = &pnv_pci_ops;
+        /* Setup RID -> PE mapping function */
+        phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
+        /* Setup TCEs */
+        phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
+        /* Setup MSI support */
+        pnv_pci_init_ioda_msis(phb);
+        /* We set both probe_only and PCI_REASSIGN_ALL_RSRC. This is an
+         * odd combination which essentially means that we skip all resource
+         * fixups and assignments in the generic code, and do it all
+         * ourselves here
+         */
+        pci_probe_only = 1;
+        ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
+        ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
+        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
+        /* Reset IODA tables to a clean state */
+        rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
+        if (rc)
+                pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
+        opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
+}
+void __init pnv_pci_init_ioda_hub(struct device_node *np)
+{
+        struct device_node *phbn;
+        const u64 *prop64;
+        u64 hub_id;
+        pr_info("Probing IODA IO-Hub %s\n", np->full_name);
+        prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
+        if (!prop64) {
+                pr_err(" Missing \"ibm,opal-hubid\" property !\n");
+                return;
+        }
+        hub_id = be64_to_cpup(prop64);
+        pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
+        /* Count child PHBs */
+        for_each_child_of_node(np, phbn) {
+                /* Look for IODA1 PHBs */
+                if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
+                        pnv_pci_init_ioda1_phb(phbn);
+        }
+}
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 4c80f7c77d56..264967770c3a 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -137,6 +137,7 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
        phb->hose->private_data = phb;
        phb->opal_id = phb_id;
        phb->type = PNV_PHB_P5IOC2;
+        phb->model = PNV_PHB_MODEL_P5IOC2;
        phb->regs = of_iomap(np, 0);
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 85bb66d7f933..a70bc1e385eb 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -144,6 +144,112 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
 }
 #endif /* CONFIG_PCI_MSI */
+static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
+{
+        struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
+        int i;
+        pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
+        pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);
+        pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
+        pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
+        pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);
+        pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
+        pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
+        pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
+        pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
+        pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);
+        pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
+        pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
+        pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
+        pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
+        pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
+        pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
+        pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
+        pr_info("  sourceId             = 0x%08x\n", data->sourceId);
+        pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
+        pr_info("  correlator           = 0x%016llx\n", data->correlator);
+        pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
+        pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
+        pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
+        pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
+        pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
+        pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
+        pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
+        pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
+        pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
+        pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
+        pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
+        pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
+        pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
+        pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
+        pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
+        pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
+        pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
+        pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
+        pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
+        pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
+        pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);
+        for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
+                if ((data->pestA[i] >> 63) == 0 &&
+                    (data->pestB[i] >> 63) == 0)
+                        continue;
+                pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
+                pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
+        }
+}
+static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
+{
+        switch(phb->model) {
+        case PNV_PHB_MODEL_P7IOC:
+                pnv_pci_dump_p7ioc_diag_data(phb);
+                break;
+        default:
+                pr_warning("PCI %d: Can't decode this PHB diag data\n",
+                           phb->hose->global_number);
+        }
+}
+static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
+{
+        unsigned long flags, rc;
+        int has_diag;
+        spin_lock_irqsave(&phb->lock, flags);
+        rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
+        has_diag = (rc == OPAL_SUCCESS);
+        rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
+                                       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
+        if (rc) {
+                pr_warning("PCI %d: Failed to clear EEH freeze state"
+                           " for PE#%d, err %ld\n",
+                           phb->hose->global_number, pe_no, rc);
+                /* For now, let's only display the diag buffer when we fail to clear
+                 * the EEH status. We'll do more sensible things later when we have
+                 * proper EEH support. We need to make sure we don't pollute ourselves
+                 * with the normal errors generated when probing empty slots
+                 */
+                if (has_diag)
+                        pnv_pci_dump_phb_diag_data(phb);
+                else
+                        pr_warning("PCI %d: No diag data available\n",
+                                   phb->hose->global_number);
+        }
+        spin_unlock_irqrestore(&phb->lock, flags);
+}
 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
                                     u32 bdfn)
 {
@@ -165,15 +271,8 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
        }
        cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
                bdfn, pe_no, fstate);
-        if (fstate != 0) {
+        if (fstate != 0)
-                rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
+                pnv_pci_handle_eeh_config(phb, pe_no);
-                                              OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
-                if (rc) {
-                        pr_warning("PCI %d: Failed to clear EEH freeze state"
-                                   " for PE#%d, err %lld\n",
-                                   phb->hose->global_number, pe_no, rc);
-                }
-        }
 }
 static int pnv_pci_read_config(struct pci_bus *bus,
@@ -257,12 +356,54 @@ struct pci_ops pnv_pci_ops = {
        .write = pnv_pci_write_config,
 };
+static void pnv_tce_invalidate(struct iommu_table *tbl,
+                               u64 *startp, u64 *endp)
+{
+        u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
+        unsigned long start, end, inc;
+        start = __pa(startp);
+        end = __pa(endp);
+        /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
+        if (tbl->it_busno) {
+                start <<= 12;
+                end <<= 12;
+                inc = 128 << 12;
+                start |= tbl->it_busno;
+                end |= tbl->it_busno;
+        }
+        /* p7ioc-style invalidation, 2 TCEs per write */
+        else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
+                start |= (1ull << 63);
+                end |= (1ull << 63);
+                inc = 16;
+        }
+        /* Default (older HW) */
+        else
+                inc = 128;
+        end |= inc - 1;         /* round up end to be different than start */
+        mb(); /* Ensure above stores are visible */
+        while (start <= end) {
+                __raw_writeq(start, invalidate);
+                start += inc;
+        }
+        /* The iommu layer will do another mb() for us on build() and
+         * we don't care on free()
+         */
+}
 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
                         unsigned long uaddr, enum dma_data_direction direction,
                         struct dma_attrs *attrs)
 {
        u64 proto_tce;
-        u64 *tcep;
+        u64 *tcep, *tces;
        u64 rpn;
        proto_tce = TCE_PCI_READ; // Read allowed
@@ -270,25 +411,33 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
        if (direction != DMA_TO_DEVICE)
                proto_tce |= TCE_PCI_WRITE;
-        tcep = ((u64 *)tbl->it_base) + index;
+        tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
+        rpn = __pa(uaddr) >> TCE_SHIFT;
-        while (npages--) {
+        while (npages--)
-                /* can't move this out since we might cross LMB boundary */
+                *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
-                rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
-                *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
+        /* Some implementations won't cache invalid TCEs and thus may not
+         * need that flush. We'll probably turn it_type into a bit mask
+         * of flags if that becomes the case
+         */
+        if (tbl->it_type & TCE_PCI_SWINV_CREATE)
+                pnv_tce_invalidate(tbl, tces, tcep - 1);
-                uaddr += TCE_PAGE_SIZE;
-                tcep++;
-        }
        return 0;
 }
 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
 {
-        u64 *tcep = ((u64 *)tbl->it_base) + index;
+        u64 *tcep, *tces;
+        tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
        while (npages--)
                *(tcep++) = 0;
+        if (tbl->it_type & TCE_PCI_SWINV_FREE)
+                pnv_tce_invalidate(tbl, tces, tcep - 1);
 }
 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
@@ -308,13 +457,14 @@ static struct iommu_table * __devinit
 pnv_pci_setup_bml_iommu(struct pci_controller *hose)
 {
        struct iommu_table *tbl;
-        const __be64 *basep;
+        const __be64 *basep, *swinvp;
        const __be32 *sizep;
        basep = of_get_property(hose->dn, "linux,tce-base", NULL);
        sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
        if (basep == NULL || sizep == NULL) {
-                pr_err("PCI: %s has missing tce entries !\n", hose->dn->full_name);
+                pr_err("PCI: %s has missing tce entries !\n",
+                       hose->dn->full_name);
                return NULL;
        }
        tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
@@ -323,6 +473,15 @@ pnv_pci_setup_bml_iommu(struct pci_controller *hose)
        pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
                                  be32_to_cpup(sizep), 0);
        iommu_init_table(tbl, hose->node);
+        /* Deal with SW invalidated TCEs when needed (BML way) */
+        swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
+                                 NULL);
+        if (swinvp) {
+                tbl->it_busno = swinvp[1];
+                tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
+                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
+        }
        return tbl;
 }
@@ -356,6 +515,13 @@ static void __devinit pnv_pci_dma_dev_setup(struct pci_dev *pdev)
                pnv_pci_dma_fallback_setup(hose, pdev);
 }
+/* Fixup wrong class code in p7ioc root complex */
+static void __devinit pnv_p7ioc_rc_quirk(struct pci_dev *dev)
+{
+        dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
 static int pnv_pci_probe_mode(struct pci_bus *bus)
 {
        struct pci_controller *hose = pci_bus_to_host(bus);
@@ -400,12 +566,24 @@ void __init pnv_pci_init(void)
                init_pci_config_tokens();
                find_and_init_phbs();
 #endif /* CONFIG_PPC_POWERNV_RTAS */
-        } else {
+        }
-                /* OPAL is here, do our normal stuff */
+        /* OPAL is here, do our normal stuff */
+        else {
+                int found_ioda = 0;
+                /* Look for IODA IO-Hubs. We don't support mixing IODA
+                 * and p5ioc2 due to the need to change some global
+                 * probing flags
+                 */
+                for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
+                        pnv_pci_init_ioda_hub(np);
+                        found_ioda = 1;
+                }
                /* Look for p5ioc2 IO-Hubs */
-                for_each_compatible_node(np, NULL, "ibm,p5ioc2")
+                if (!found_ioda)
-                        pnv_pci_init_p5ioc2_hub(np);
+                        for_each_compatible_node(np, NULL, "ibm,p5ioc2")
+                                pnv_pci_init_p5ioc2_hub(np);
        }
        /* Setup the linkage between OF nodes and PHBs */
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index d4dbc4950936..8bc479634643 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -9,9 +9,63 @@ enum pnv_phb_type {
        PNV_PHB_IODA2,
 };
+/* Precise PHB model for error management */
+enum pnv_phb_model {
+        PNV_PHB_MODEL_UNKNOWN,
+        PNV_PHB_MODEL_P5IOC2,
+        PNV_PHB_MODEL_P7IOC,
+};
+#define PNV_PCI_DIAG_BUF_SIZE   4096
+/* Data associated with a PE, including IOMMU tracking etc.. */
+struct pnv_ioda_pe {
+        /* A PE can be associated with a single device or an
+         * entire bus (& children). In the former case, pdev
+         * is populated, in the later case, pbus is.
+         */
+        struct pci_dev          *pdev;
+        struct pci_bus          *pbus;
+        /* Effective RID (device RID for a device PE and base bus
+         * RID with devfn 0 for a bus PE)
+         */
+        unsigned int            rid;
+        /* PE number */
+        unsigned int            pe_number;
+        /* "Weight" assigned to the PE for the sake of DMA resource
+         * allocations
+         */
+        unsigned int            dma_weight;
+        /* This is a PCI-E -> PCI-X bridge, this points to the
+         * corresponding bus PE
+         */
+        struct pnv_ioda_pe      *bus_pe;
+        /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
+        int                     tce32_seg;
+        int                     tce32_segcount;
+        struct iommu_table      tce32_table;
+        /* XXX TODO: Add support for additional 64-bit iommus */
+        /* MSIs. MVE index is identical for for 32 and 64 bit MSI
+         * and -1 if not supported. (It's actually identical to the
+         * PE number)
+         */
+        int                     mve_number;
+        /* Link in list of PE#s */
+        struct list_head        link;
+};
 struct pnv_phb {
        struct pci_controller   *hose;
        enum pnv_phb_type       type;
+        enum pnv_phb_model      model;
        u64                     opal_id;
        void __iomem            *regs;
        spinlock_t              lock;
@@ -34,7 +88,52 @@ struct pnv_phb {
                struct {
                        struct iommu_table iommu_table;
                } p5ioc2;
+                struct {
+                        /* Global bridge info */
+                        unsigned int            total_pe;
+                        unsigned int            m32_size;
+                        unsigned int            m32_segsize;
+                        unsigned int            m32_pci_base;
+                        unsigned int            io_size;
+                        unsigned int            io_segsize;
+                        unsigned int            io_pci_base;
+                        /* PE allocation bitmap */
+                        unsigned long           *pe_alloc;
+                        /* M32 & IO segment maps */
+                        unsigned int            *m32_segmap;
+                        unsigned int            *io_segmap;
+                        struct pnv_ioda_pe      *pe_array;
+                        /* Reverse map of PEs, will have to extend if
+                         * we are to support more than 256 PEs, indexed
+                         * bus { bus, devfn }
+                         */
+                        unsigned char           pe_rmap[0x10000];
+                        /* 32-bit TCE tables allocation */
+                        unsigned long           tce32_count;
+                        /* Total "weight" for the sake of DMA resources
+                         * allocation
+                         */
+                        unsigned int            dma_weight;
+                        unsigned int            dma_pe_count;
+                        /* Sorted list of used PE's, sorted at
+                         * boot for resource allocation purposes
+                         */
+                        struct list_head        pe_list;
+                } ioda;
        };
+        /* PHB status structure */
+        union {
+                unsigned char                   blob[PNV_PCI_DIAG_BUF_SIZE];
+                struct OpalIoP7IOCPhbErrorData  p7ioc;
+        } diag;
 };
 extern struct pci_ops pnv_pci_ops;
@@ -43,6 +142,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                      void *tce_mem, u64 tce_size,
                                      u64 dma_offset);
 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
+extern void pnv_pci_init_ioda_hub(struct device_node *np);
 #endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index e87736685243..17210c526c52 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -75,7 +75,7 @@ int __devinit pnv_smp_kick_cpu(int nr)
        /* On OPAL v2 the CPU are still spinning inside OPAL itself,
         * get them back now
         */
-        if (firmware_has_feature(FW_FEATURE_OPALv2)) {
+        if (!paca[nr].cpu_start && firmware_has_feature(FW_FEATURE_OPALv2)) {
                pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
                rc = opal_start_cpu(pcpu, start_here);
                if (rc != OPAL_SUCCESS)
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 1d6f4f478fe2..617efa12a3a5 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -31,18 +31,18 @@
 #if defined(DEBUG)
 #define DBG udbg_printf
+#define FAIL udbg_printf
 #else
-#define DBG pr_debug
+#define DBG pr_devel
+#define FAIL pr_debug
 #endif
 /**
 * struct ps3_bmp - a per cpu irq status and mask bitmap structure
 * @status: 256 bit status bitmap indexed by plug
- * @unused_1:
+ * @unused_1: Alignment
 * @mask: 256 bit mask bitmap indexed by plug
- * @unused_2:
+ * @unused_2: Alignment
- * @lock:
- * @ipi_debug_brk_mask:
 *
 * The HV maintains per SMT thread mappings of HV outlet to HV plug on
 * behalf of the guest.  These mappings are implemented as 256 bit guest
@@ -73,21 +73,24 @@ struct ps3_bmp {
                unsigned long mask;
                u64 unused_2[3];
        };
-        u64 ipi_debug_brk_mask;
-        spinlock_t lock;
 };
 /**
 * struct ps3_private - a per cpu data structure
 * @bmp: ps3_bmp structure
+ * @bmp_lock: Syncronize access to bmp.
+ * @ipi_debug_brk_mask: Mask for debug break IPIs
 * @ppe_id: HV logical_ppe_id
 * @thread_id: HV thread_id
+ * @ipi_mask: Mask of IPI virqs
 */
 struct ps3_private {
        struct ps3_bmp bmp __attribute__ ((aligned (PS3_BMP_MINALIGN)));
+        spinlock_t bmp_lock;
        u64 ppe_id;
        u64 thread_id;
+        unsigned long ipi_debug_brk_mask;
        unsigned long ipi_mask;
 };
@@ -105,7 +108,7 @@ static void ps3_chip_mask(struct irq_data *d)
        struct ps3_private *pd = irq_data_get_irq_chip_data(d);
        unsigned long flags;
-        pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
+        DBG("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
                pd->thread_id, d->irq);
        local_irq_save(flags);
@@ -126,7 +129,7 @@ static void ps3_chip_unmask(struct irq_data *d)
        struct ps3_private *pd = irq_data_get_irq_chip_data(d);
        unsigned long flags;
-        pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
+        DBG("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__,
                pd->thread_id, d->irq);
        local_irq_save(flags);
@@ -190,19 +193,19 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
        *virq = irq_create_mapping(NULL, outlet);
        if (*virq == NO_IRQ) {
-                pr_debug("%s:%d: irq_create_mapping failed: outlet %lu\n",
+                FAIL("%s:%d: irq_create_mapping failed: outlet %lu\n",
                        __func__, __LINE__, outlet);
                result = -ENOMEM;
                goto fail_create;
        }
-        pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__,
+        DBG("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__,
                outlet, cpu, *virq);
        result = irq_set_chip_data(*virq, pd);
        if (result) {
-                pr_debug("%s:%d: irq_set_chip_data failed\n",
+                FAIL("%s:%d: irq_set_chip_data failed\n",
                        __func__, __LINE__);
                goto fail_set;
        }
@@ -228,13 +231,13 @@ static int ps3_virq_destroy(unsigned int virq)
 {
        const struct ps3_private *pd = irq_get_chip_data(virq);
-        pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
+        DBG("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
                __LINE__, pd->ppe_id, pd->thread_id, virq);
        irq_set_chip_data(virq, NULL);
        irq_dispose_mapping(virq);
-        pr_debug("%s:%d <-\n", __func__, __LINE__);
+        DBG("%s:%d <-\n", __func__, __LINE__);
        return 0;
 }
@@ -257,7 +260,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
        result = ps3_virq_setup(cpu, outlet, virq);
        if (result) {
-                pr_debug("%s:%d: ps3_virq_setup failed\n", __func__, __LINE__);
+                FAIL("%s:%d: ps3_virq_setup failed\n", __func__, __LINE__);
                goto fail_setup;
        }
@@ -269,7 +272,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
                outlet, 0);
        if (result) {
-                pr_info("%s:%d: lv1_connect_irq_plug_ext failed: %s\n",
+                FAIL("%s:%d: lv1_connect_irq_plug_ext failed: %s\n",
                __func__, __LINE__, ps3_result(result));
                result = -EPERM;
                goto fail_connect;
@@ -298,7 +301,7 @@ int ps3_irq_plug_destroy(unsigned int virq)
        int result;
        const struct ps3_private *pd = irq_get_chip_data(virq);
-        pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
+        DBG("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
                __LINE__, pd->ppe_id, pd->thread_id, virq);
        ps3_chip_mask(irq_get_irq_data(virq));
@@ -306,7 +309,7 @@ int ps3_irq_plug_destroy(unsigned int virq)
        result = lv1_disconnect_irq_plug_ext(pd->ppe_id, pd->thread_id, virq);
        if (result)
-                pr_info("%s:%d: lv1_disconnect_irq_plug_ext failed: %s\n",
+                FAIL("%s:%d: lv1_disconnect_irq_plug_ext failed: %s\n",
                __func__, __LINE__, ps3_result(result));
        ps3_virq_destroy(virq);
@@ -334,7 +337,7 @@ int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq)
        result = lv1_construct_event_receive_port(&outlet);
        if (result) {
-                pr_debug("%s:%d: lv1_construct_event_receive_port failed: %s\n",
+                FAIL("%s:%d: lv1_construct_event_receive_port failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                *virq = NO_IRQ;
                return result;
@@ -360,14 +363,14 @@ int ps3_event_receive_port_destroy(unsigned int virq)
 {
        int result;
-        pr_debug(" -> %s:%d virq %u\n", __func__, __LINE__, virq);
+        DBG(" -> %s:%d virq %u\n", __func__, __LINE__, virq);
        ps3_chip_mask(irq_get_irq_data(virq));
        result = lv1_destruct_event_receive_port(virq_to_hw(virq));
        if (result)
-                pr_debug("%s:%d: lv1_destruct_event_receive_port failed: %s\n",
+                FAIL("%s:%d: lv1_destruct_event_receive_port failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
        /*
@@ -375,7 +378,7 @@ int ps3_event_receive_port_destroy(unsigned int virq)
         * calls from interrupt context (smp_call_function) when kexecing.
         */
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        DBG(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
@@ -411,7 +414,7 @@ int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
                dev->dev_id, virq_to_hw(*virq), dev->interrupt_id);
        if (result) {
-                pr_debug("%s:%d: lv1_connect_interrupt_event_receive_port"
+                FAIL("%s:%d: lv1_connect_interrupt_event_receive_port"
                        " failed: %s\n", __func__, __LINE__,
                        ps3_result(result));
                ps3_event_receive_port_destroy(*virq);
@@ -419,7 +422,7 @@ int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
                return result;
        }
-        pr_debug("%s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
+        DBG("%s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
                dev->interrupt_id, *virq);
        return 0;
@@ -433,14 +436,14 @@ int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
        int result;
-        pr_debug(" -> %s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
+        DBG(" -> %s:%d: interrupt_id %u, virq %u\n", __func__, __LINE__,
                dev->interrupt_id, virq);
        result = lv1_disconnect_interrupt_event_receive_port(dev->bus_id,
                dev->dev_id, virq_to_hw(virq), dev->interrupt_id);
        if (result)
-                pr_debug("%s:%d: lv1_disconnect_interrupt_event_receive_port"
+                FAIL("%s:%d: lv1_disconnect_interrupt_event_receive_port"
                        " failed: %s\n", __func__, __LINE__,
                        ps3_result(result));
@@ -455,7 +458,7 @@ int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
        result = ps3_virq_destroy(virq);
        BUG_ON(result);
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        DBG(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
 EXPORT_SYMBOL(ps3_sb_event_receive_port_destroy);
@@ -480,7 +483,7 @@ int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
        result = lv1_construct_io_irq_outlet(interrupt_id, &outlet);
        if (result) {
-                pr_debug("%s:%d: lv1_construct_io_irq_outlet failed: %s\n",
+                FAIL("%s:%d: lv1_construct_io_irq_outlet failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                return result;
        }
@@ -510,7 +513,7 @@ int ps3_io_irq_destroy(unsigned int virq)
        result = lv1_destruct_io_irq_outlet(outlet);
        if (result)
-                pr_debug("%s:%d: lv1_destruct_io_irq_outlet failed: %s\n",
+                FAIL("%s:%d: lv1_destruct_io_irq_outlet failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
        return result;
@@ -542,7 +545,7 @@ int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
        result = lv1_configure_virtual_uart_irq(lpar_addr, &outlet);
        if (result) {
-                pr_debug("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
+                FAIL("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                return result;
        }
@@ -562,7 +565,7 @@ int ps3_vuart_irq_destroy(unsigned int virq)
        result = lv1_deconfigure_virtual_uart_irq();
        if (result) {
-                pr_debug("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
+                FAIL("%s:%d: lv1_configure_virtual_uart_irq failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                return result;
        }
@@ -595,7 +598,7 @@ int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
        result = lv1_get_spe_irq_outlet(spe_id, class, &outlet);
        if (result) {
-                pr_debug("%s:%d: lv1_get_spe_irq_outlet failed: %s\n",
+                FAIL("%s:%d: lv1_get_spe_irq_outlet failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                return result;
        }
@@ -626,7 +629,7 @@ int ps3_spe_irq_destroy(unsigned int virq)
 static void _dump_64_bmp(const char *header, const u64 *p, unsigned cpu,
        const char* func, int line)
 {
-        pr_debug("%s:%d: %s %u {%04lx_%04lx_%04lx_%04lx}\n",
+        pr_debug("%s:%d: %s %u {%04llx_%04llx_%04llx_%04llx}\n",
                func, line, header, cpu,
                *p >> 48, (*p >> 32) & 0xffff, (*p >> 16) & 0xffff,
                *p & 0xffff);
@@ -635,7 +638,7 @@ static void _dump_64_bmp(const char *header, const u64 *p, unsigned cpu,
 static void __maybe_unused _dump_256_bmp(const char *header,
        const u64 *p, unsigned cpu, const char* func, int line)
 {
-        pr_debug("%s:%d: %s %u {%016lx:%016lx:%016lx:%016lx}\n",
+        pr_debug("%s:%d: %s %u {%016llx:%016llx:%016llx:%016llx}\n",
                func, line, header, cpu, p[0], p[1], p[2], p[3]);
 }
@@ -644,10 +647,10 @@ static void _dump_bmp(struct ps3_private* pd, const char* func, int line)
 {
        unsigned long flags;
-        spin_lock_irqsave(&pd->bmp.lock, flags);
+        spin_lock_irqsave(&pd->bmp_lock, flags);
        _dump_64_bmp("stat", &pd->bmp.status, pd->thread_id, func, line);
-        _dump_64_bmp("mask", &pd->bmp.mask, pd->thread_id, func, line);
+        _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line);
-        spin_unlock_irqrestore(&pd->bmp.lock, flags);
+        spin_unlock_irqrestore(&pd->bmp_lock, flags);
 }
 #define dump_mask(_x) _dump_mask(_x, __func__, __LINE__)
@@ -656,9 +659,9 @@ static void __maybe_unused _dump_mask(struct ps3_private *pd,
 {
        unsigned long flags;
-        spin_lock_irqsave(&pd->bmp.lock, flags);
+        spin_lock_irqsave(&pd->bmp_lock, flags);
-        _dump_64_bmp("mask", &pd->bmp.mask, pd->thread_id, func, line);
+        _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line);
-        spin_unlock_irqrestore(&pd->bmp.lock, flags);
+        spin_unlock_irqrestore(&pd->bmp_lock, flags);
 }
 #else
 static void dump_bmp(struct ps3_private* pd) {};
@@ -667,7 +670,7 @@ static void dump_bmp(struct ps3_private* pd) {};
 static int ps3_host_map(struct irq_host *h, unsigned int virq,
        irq_hw_number_t hwirq)
 {
-        pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq,
+        DBG("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq,
                virq);
        irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
@@ -690,10 +693,10 @@ void __init ps3_register_ipi_debug_brk(unsigned int cpu, unsigned int virq)
 {
        struct ps3_private *pd = &per_cpu(ps3_private, cpu);
-        pd->bmp.ipi_debug_brk_mask = 0x8000000000000000UL >> virq;
+        set_bit(63 - virq, &pd->ipi_debug_brk_mask);
-        pr_debug("%s:%d: cpu %u, virq %u, mask %llxh\n", __func__, __LINE__,
+        DBG("%s:%d: cpu %u, virq %u, mask %lxh\n", __func__, __LINE__,
-                cpu, virq, pd->bmp.ipi_debug_brk_mask);
+                cpu, virq, pd->ipi_debug_brk_mask);
 }
 void __init ps3_register_ipi_irq(unsigned int cpu, unsigned int virq)
@@ -714,14 +717,14 @@ static unsigned int ps3_get_irq(void)
        /* check for ipi break first to stop this cpu ASAP */
-        if (x & pd->bmp.ipi_debug_brk_mask)
+        if (x & pd->ipi_debug_brk_mask)
-                x &= pd->bmp.ipi_debug_brk_mask;
+                x &= pd->ipi_debug_brk_mask;
        asm volatile("cntlzd %0,%1" : "=r" (plug) : "r" (x));
        plug &= 0x3f;
        if (unlikely(plug == NO_IRQ)) {
-                pr_debug("%s:%d: no plug found: thread_id %llu\n", __func__,
+                DBG("%s:%d: no plug found: thread_id %llu\n", __func__,
                        __LINE__, pd->thread_id);
                dump_bmp(&per_cpu(ps3_private, 0));
                dump_bmp(&per_cpu(ps3_private, 1));
@@ -760,9 +763,9 @@ void __init ps3_init_IRQ(void)
                lv1_get_logical_ppe_id(&pd->ppe_id);
                pd->thread_id = get_hard_smp_processor_id(cpu);
-                spin_lock_init(&pd->bmp.lock);
+                spin_lock_init(&pd->bmp_lock);
-                pr_debug("%s:%d: ppe_id %llu, thread_id %llu, bmp %lxh\n",
+                DBG("%s:%d: ppe_id %llu, thread_id %llu, bmp %lxh\n",
                        __func__, __LINE__, pd->ppe_id, pd->thread_id,
                        ps3_mm_phys_to_lpar(__pa(&pd->bmp)));
@@ -770,7 +773,7 @@ void __init ps3_init_IRQ(void)
                        pd->thread_id, ps3_mm_phys_to_lpar(__pa(&pd->bmp)));
                if (result)
-                        pr_debug("%s:%d: lv1_configure_irq_state_bitmap failed:"
+                        FAIL("%s:%d: lv1_configure_irq_state_bitmap failed:"
                                " %s\n", __func__, __LINE__,
                                ps3_result(result));
        }
diff --git a/arch/powerpc/platforms/ps3/repository.c b/arch/powerpc/platforms/ps3/repository.c
index ca40f6afd35d..7bdfea336f5e 100644
--- a/arch/powerpc/platforms/ps3/repository.c
+++ b/arch/powerpc/platforms/ps3/repository.c
@@ -44,7 +44,7 @@ static void _dump_field(const char *hdr, u64 n, const char *func, int line)
                s[i] = (in[i] <= 126 && in[i] >= 32) ? in[i] : '.';
        s[i] = 0;
-        pr_debug("%s:%d: %s%016llx : %s\n", func, line, hdr, n, s);
+        pr_devel("%s:%d: %s%016llx : %s\n", func, line, hdr, n, s);
 #endif
 }
@@ -53,7 +53,7 @@ static void _dump_field(const char *hdr, u64 n, const char *func, int line)
 static void _dump_node_name(unsigned int lpar_id, u64 n1, u64 n2, u64 n3,
        u64 n4, const char *func, int line)
 {
-        pr_debug("%s:%d: lpar: %u\n", func, line, lpar_id);
+        pr_devel("%s:%d: lpar: %u\n", func, line, lpar_id);
        _dump_field("n1: ", n1, func, line);
        _dump_field("n2: ", n2, func, line);
        _dump_field("n3: ", n3, func, line);
@@ -65,13 +65,13 @@ static void _dump_node_name(unsigned int lpar_id, u64 n1, u64 n2, u64 n3,
 static void _dump_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
        u64 v1, u64 v2, const char *func, int line)
 {
-        pr_debug("%s:%d: lpar: %u\n", func, line, lpar_id);
+        pr_devel("%s:%d: lpar: %u\n", func, line, lpar_id);
        _dump_field("n1: ", n1, func, line);
        _dump_field("n2: ", n2, func, line);
        _dump_field("n3: ", n3, func, line);
        _dump_field("n4: ", n4, func, line);
-        pr_debug("%s:%d: v1: %016llx\n", func, line, v1);
+        pr_devel("%s:%d: v1: %016llx\n", func, line, v1);
-        pr_debug("%s:%d: v2: %016llx\n", func, line, v2);
+        pr_devel("%s:%d: v2: %016llx\n", func, line, v2);
 }
 /**
@@ -131,11 +131,11 @@ static int read_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
                lpar_id = id;
        }
-        result = lv1_get_repository_node_value(lpar_id, n1, n2, n3, n4, &v1,
+        result = lv1_read_repository_node(lpar_id, n1, n2, n3, n4, &v1,
                &v2);
        if (result) {
-                pr_debug("%s:%d: lv1_get_repository_node_value failed: %s\n",
+                pr_warn("%s:%d: lv1_read_repository_node failed: %s\n",
                        __func__, __LINE__, ps3_result(result));
                dump_node_name(lpar_id, n1, n2, n3, n4);
                return -ENOENT;
@@ -149,10 +149,10 @@ static int read_node(unsigned int lpar_id, u64 n1, u64 n2, u64 n3, u64 n4,
                *_v2 = v2;
        if (v1 && !_v1)
-                pr_debug("%s:%d: warning: discarding non-zero v1: %016llx\n",
+                pr_devel("%s:%d: warning: discarding non-zero v1: %016llx\n",
                        __func__, __LINE__, v1);
        if (v2 && !_v2)
-                pr_debug("%s:%d: warning: discarding non-zero v2: %016llx\n",
+                pr_devel("%s:%d: warning: discarding non-zero v2: %016llx\n",
                        __func__, __LINE__, v2);
        return 0;
@@ -323,16 +323,16 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
        result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev);
        if (result) {
-                pr_debug("%s:%d read_bus_num_dev failed\n", __func__, __LINE__);
+                pr_devel("%s:%d read_bus_num_dev failed\n", __func__, __LINE__);
                return result;
        }
-        pr_debug("%s:%d: bus_type %u, bus_index %u, bus_id %llu, num_dev %u\n",
+        pr_devel("%s:%d: bus_type %u, bus_index %u, bus_id %llu, num_dev %u\n",
                __func__, __LINE__, tmp.bus_type, tmp.bus_index, tmp.bus_id,
                num_dev);
        if (tmp.dev_index >= num_dev) {
-                pr_debug("%s:%d: no device found\n", __func__, __LINE__);
+                pr_devel("%s:%d: no device found\n", __func__, __LINE__);
                return -ENODEV;
        }
@@ -340,7 +340,7 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
                &tmp.dev_type);
        if (result) {
-                pr_debug("%s:%d read_dev_type failed\n", __func__, __LINE__);
+                pr_devel("%s:%d read_dev_type failed\n", __func__, __LINE__);
                return result;
        }
@@ -348,12 +348,12 @@ int ps3_repository_find_device(struct ps3_repository_device *repo)
                &tmp.dev_id);
        if (result) {
-                pr_debug("%s:%d ps3_repository_read_dev_id failed\n", __func__,
+                pr_devel("%s:%d ps3_repository_read_dev_id failed\n", __func__,
                __LINE__);
                return result;
        }
-        pr_debug("%s:%d: found: dev_type %u, dev_index %u, dev_id %llu\n",
+        pr_devel("%s:%d: found: dev_type %u, dev_index %u, dev_id %llu\n",
                __func__, __LINE__, tmp.dev_type, tmp.dev_index, tmp.dev_id);
        *repo = tmp;
@@ -367,14 +367,14 @@ int ps3_repository_find_device_by_id(struct ps3_repository_device *repo,
        struct ps3_repository_device tmp;
        unsigned int num_dev;
-        pr_debug(" -> %s:%u: find device by id %llu:%llu\n", __func__, __LINE__,
+        pr_devel(" -> %s:%u: find device by id %llu:%llu\n", __func__, __LINE__,
                 bus_id, dev_id);
        for (tmp.bus_index = 0; tmp.bus_index < 10; tmp.bus_index++) {
                result = ps3_repository_read_bus_id(tmp.bus_index,
                                                    &tmp.bus_id);
                if (result) {
-                        pr_debug("%s:%u read_bus_id(%u) failed\n", __func__,
+                        pr_devel("%s:%u read_bus_id(%u) failed\n", __func__,
                                 __LINE__, tmp.bus_index);
                        return result;
                }
@@ -382,23 +382,23 @@ int ps3_repository_find_device_by_id(struct ps3_repository_device *repo,
                if (tmp.bus_id == bus_id)
                        goto found_bus;
-                pr_debug("%s:%u: skip, bus_id %llu\n", __func__, __LINE__,
+                pr_devel("%s:%u: skip, bus_id %llu\n", __func__, __LINE__,
                         tmp.bus_id);
        }
-        pr_debug(" <- %s:%u: bus not found\n", __func__, __LINE__);
+        pr_devel(" <- %s:%u: bus not found\n", __func__, __LINE__);
        return result;
 found_bus:
        result = ps3_repository_read_bus_type(tmp.bus_index, &tmp.bus_type);
        if (result) {
-                pr_debug("%s:%u read_bus_type(%u) failed\n", __func__,
+                pr_devel("%s:%u read_bus_type(%u) failed\n", __func__,
                         __LINE__, tmp.bus_index);
                return result;
        }
        result = ps3_repository_read_bus_num_dev(tmp.bus_index, &num_dev);
        if (result) {
-                pr_debug("%s:%u read_bus_num_dev failed\n", __func__,
+                pr_devel("%s:%u read_bus_num_dev failed\n", __func__,
                         __LINE__);
                return result;
        }
@@ -408,7 +408,7 @@ found_bus:
                                                    tmp.dev_index,
                                                    &tmp.dev_id);
                if (result) {
-                        pr_debug("%s:%u read_dev_id(%u:%u) failed\n", __func__,
+                        pr_devel("%s:%u read_dev_id(%u:%u) failed\n", __func__,
                                 __LINE__, tmp.bus_index, tmp.dev_index);
                        return result;
                }
@@ -416,21 +416,21 @@ found_bus:
                if (tmp.dev_id == dev_id)
                        goto found_dev;
-                pr_debug("%s:%u: skip, dev_id %llu\n", __func__, __LINE__,
+                pr_devel("%s:%u: skip, dev_id %llu\n", __func__, __LINE__,
                         tmp.dev_id);
        }
-        pr_debug(" <- %s:%u: dev not found\n", __func__, __LINE__);
+        pr_devel(" <- %s:%u: dev not found\n", __func__, __LINE__);
        return result;
 found_dev:
        result = ps3_repository_read_dev_type(tmp.bus_index, tmp.dev_index,
                                              &tmp.dev_type);
        if (result) {
-                pr_debug("%s:%u read_dev_type failed\n", __func__, __LINE__);
+                pr_devel("%s:%u read_dev_type failed\n", __func__, __LINE__);
                return result;
        }
-        pr_debug(" <- %s:%u: found: type (%u:%u) index (%u:%u) id (%llu:%llu)\n",
+        pr_devel(" <- %s:%u: found: type (%u:%u) index (%u:%u) id (%llu:%llu)\n",
                 __func__, __LINE__, tmp.bus_type, tmp.dev_type, tmp.bus_index,
                 tmp.dev_index, tmp.bus_id, tmp.dev_id);
        *repo = tmp;
@@ -443,18 +443,18 @@ int __devinit ps3_repository_find_devices(enum ps3_bus_type bus_type,
        int result = 0;
        struct ps3_repository_device repo;
-        pr_debug(" -> %s:%d: find bus_type %u\n", __func__, __LINE__, bus_type);
+        pr_devel(" -> %s:%d: find bus_type %u\n", __func__, __LINE__, bus_type);
        repo.bus_type = bus_type;
        result = ps3_repository_find_bus(repo.bus_type, 0, &repo.bus_index);
        if (result) {
-                pr_debug(" <- %s:%u: bus not found\n", __func__, __LINE__);
+                pr_devel(" <- %s:%u: bus not found\n", __func__, __LINE__);
                return result;
        }
        result = ps3_repository_read_bus_id(repo.bus_index, &repo.bus_id);
        if (result) {
-                pr_debug("%s:%d read_bus_id(%u) failed\n", __func__, __LINE__,
+                pr_devel("%s:%d read_bus_id(%u) failed\n", __func__, __LINE__,
                         repo.bus_index);
                return result;
        }
@@ -469,13 +469,13 @@ int __devinit ps3_repository_find_devices(enum ps3_bus_type bus_type,
                result = callback(&repo);
                if (result) {
-                        pr_debug("%s:%d: abort at callback\n", __func__,
+                        pr_devel("%s:%d: abort at callback\n", __func__,
                                __LINE__);
                        break;
                }
        }
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        pr_devel(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
@@ -489,7 +489,7 @@ int ps3_repository_find_bus(enum ps3_bus_type bus_type, unsigned int from,
        for (i = from; i < 10; i++) {
                error = ps3_repository_read_bus_type(i, &type);
                if (error) {
-                        pr_debug("%s:%d read_bus_type failed\n",
+                        pr_devel("%s:%d read_bus_type failed\n",
                                __func__, __LINE__);
                        *bus_index = UINT_MAX;
                        return error;
@@ -509,7 +509,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
        int result = 0;
        unsigned int res_index;
-        pr_debug("%s:%d: find intr_type %u\n", __func__, __LINE__, intr_type);
+        pr_devel("%s:%d: find intr_type %u\n", __func__, __LINE__, intr_type);
        *interrupt_id = UINT_MAX;
@@ -521,7 +521,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
                        repo->dev_index, res_index, &t, &id);
                if (result) {
-                        pr_debug("%s:%d read_dev_intr failed\n",
+                        pr_devel("%s:%d read_dev_intr failed\n",
                                __func__, __LINE__);
                        return result;
                }
@@ -535,7 +535,7 @@ int ps3_repository_find_interrupt(const struct ps3_repository_device *repo,
        if (res_index == 10)
                return -ENODEV;
-        pr_debug("%s:%d: found intr_type %u at res_index %u\n",
+        pr_devel("%s:%d: found intr_type %u at res_index %u\n",
                __func__, __LINE__, intr_type, res_index);
        return result;
@@ -547,7 +547,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
        int result = 0;
        unsigned int res_index;
-        pr_debug("%s:%d: find reg_type %u\n", __func__, __LINE__, reg_type);
+        pr_devel("%s:%d: find reg_type %u\n", __func__, __LINE__, reg_type);
        *bus_addr = *len = 0;
@@ -560,7 +560,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
                        repo->dev_index, res_index, &t, &a, &l);
                if (result) {
-                        pr_debug("%s:%d read_dev_reg failed\n",
+                        pr_devel("%s:%d read_dev_reg failed\n",
                                __func__, __LINE__);
                        return result;
                }
@@ -575,7 +575,7 @@ int ps3_repository_find_reg(const struct ps3_repository_device *repo,
        if (res_index == 10)
                return -ENODEV;
-        pr_debug("%s:%d: found reg_type %u at res_index %u\n",
+        pr_devel("%s:%d: found reg_type %u at res_index %u\n",
                __func__, __LINE__, reg_type, res_index);
        return result;
@@ -1009,7 +1009,7 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
        int result = 0;
        unsigned int res_index;
-        pr_debug(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
+        pr_devel(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
                repo->bus_index, repo->dev_index);
        for (res_index = 0; res_index < 10; res_index++) {
@@ -1021,13 +1021,13 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
                if (result) {
                        if (result !=  LV1_NO_ENTRY)
-                                pr_debug("%s:%d ps3_repository_read_dev_intr"
+                                pr_devel("%s:%d ps3_repository_read_dev_intr"
                                        " (%u:%u) failed\n", __func__, __LINE__,
                                        repo->bus_index, repo->dev_index);
                        break;
                }
-                pr_debug("%s:%d (%u:%u) intr_type %u, interrupt_id %u\n",
+                pr_devel("%s:%d (%u:%u) intr_type %u, interrupt_id %u\n",
                        __func__, __LINE__, repo->bus_index, repo->dev_index,
                        intr_type, interrupt_id);
        }
@@ -1042,18 +1042,18 @@ int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
                if (result) {
                        if (result !=  LV1_NO_ENTRY)
-                                pr_debug("%s:%d ps3_repository_read_dev_reg"
+                                pr_devel("%s:%d ps3_repository_read_dev_reg"
                                        " (%u:%u) failed\n", __func__, __LINE__,
                                        repo->bus_index, repo->dev_index);
                        break;
                }
-                pr_debug("%s:%d (%u:%u) reg_type %u, bus_addr %lxh, len %lxh\n",
+                pr_devel("%s:%d (%u:%u) reg_type %u, bus_addr %llxh, len %llxh\n",
                        __func__, __LINE__, repo->bus_index, repo->dev_index,
                        reg_type, bus_addr, len);
        }
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        pr_devel(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
@@ -1063,22 +1063,22 @@ static int dump_stor_dev_info(struct ps3_repository_device *repo)
        unsigned int num_regions, region_index;
        u64 port, blk_size, num_blocks;
-        pr_debug(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
+        pr_devel(" -> %s:%d: (%u:%u)\n", __func__, __LINE__,
                repo->bus_index, repo->dev_index);
        result = ps3_repository_read_stor_dev_info(repo->bus_index,
                repo->dev_index, &port, &blk_size, &num_blocks, &num_regions);
        if (result) {
-                pr_debug("%s:%d ps3_repository_read_stor_dev_info"
+                pr_devel("%s:%d ps3_repository_read_stor_dev_info"
                        " (%u:%u) failed\n", __func__, __LINE__,
                        repo->bus_index, repo->dev_index);
                goto out;
        }
-        pr_debug("%s:%d  (%u:%u): port %lu, blk_size %lu, num_blocks "
+        pr_devel("%s:%d  (%u:%u): port %llu, blk_size %llu, num_blocks "
-                 "%lu, num_regions %u\n",
+                 "%llu, num_regions %u\n",
-                 __func__, __LINE__, repo->bus_index, repo->dev_index, port,
+                 __func__, __LINE__, repo->bus_index, repo->dev_index,
-                 blk_size, num_blocks, num_regions);
+                port, blk_size, num_blocks, num_regions);
        for (region_index = 0; region_index < num_regions; region_index++) {
                unsigned int region_id;
@@ -1088,19 +1088,20 @@ static int dump_stor_dev_info(struct ps3_repository_device *repo)
                        repo->dev_index, region_index, &region_id,
                        &region_start, &region_size);
                if (result) {
-                         pr_debug("%s:%d ps3_repository_read_stor_dev_region"
+                         pr_devel("%s:%d ps3_repository_read_stor_dev_region"
                                  " (%u:%u) failed\n", __func__, __LINE__,
                                  repo->bus_index, repo->dev_index);
                        break;
                }
-                pr_debug("%s:%d (%u:%u) region_id %u, start %lxh, size %lxh\n",
+                pr_devel("%s:%d (%u:%u) region_id %u, start %lxh, size %lxh\n",
                        __func__, __LINE__, repo->bus_index, repo->dev_index,
-                        region_id, region_start, region_size);
+                        region_id, (unsigned long)region_start,
+                        (unsigned long)region_size);
        }
 out:
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        pr_devel(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
@@ -1109,7 +1110,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
 {
        int result = 0;
-        pr_debug(" -> %s:%d: bus_%u\n", __func__, __LINE__, repo->bus_index);
+        pr_devel(" -> %s:%d: bus_%u\n", __func__, __LINE__, repo->bus_index);
        for (repo->dev_index = 0; repo->dev_index < num_dev;
                repo->dev_index++) {
@@ -1118,7 +1119,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
                        repo->dev_index, &repo->dev_type);
                if (result) {
-                        pr_debug("%s:%d ps3_repository_read_dev_type"
+                        pr_devel("%s:%d ps3_repository_read_dev_type"
                                " (%u:%u) failed\n", __func__, __LINE__,
                                repo->bus_index, repo->dev_index);
                        break;
@@ -1128,15 +1129,15 @@ static int dump_device_info(struct ps3_repository_device *repo,
                        repo->dev_index, &repo->dev_id);
                if (result) {
-                        pr_debug("%s:%d ps3_repository_read_dev_id"
+                        pr_devel("%s:%d ps3_repository_read_dev_id"
                                " (%u:%u) failed\n", __func__, __LINE__,
                                repo->bus_index, repo->dev_index);
                        continue;
                }
-                pr_debug("%s:%d  (%u:%u): dev_type %u, dev_id %lu\n", __func__,
+                pr_devel("%s:%d  (%u:%u): dev_type %u, dev_id %lu\n", __func__,
                        __LINE__, repo->bus_index, repo->dev_index,
-                        repo->dev_type, repo->dev_id);
+                        repo->dev_type, (unsigned long)repo->dev_id);
                ps3_repository_dump_resource_info(repo);
@@ -1144,7 +1145,7 @@ static int dump_device_info(struct ps3_repository_device *repo,
                        dump_stor_dev_info(repo);
        }
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        pr_devel(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
@@ -1153,7 +1154,7 @@ int ps3_repository_dump_bus_info(void)
        int result = 0;
        struct ps3_repository_device repo;
-        pr_debug(" -> %s:%d\n", __func__, __LINE__);
+        pr_devel(" -> %s:%d\n", __func__, __LINE__);
        memset(&repo, 0, sizeof(repo));
@@ -1164,7 +1165,7 @@ int ps3_repository_dump_bus_info(void)
                        &repo.bus_type);
                if (result) {
-                        pr_debug("%s:%d read_bus_type(%u) failed\n",
+                        pr_devel("%s:%d read_bus_type(%u) failed\n",
                                __func__, __LINE__, repo.bus_index);
                        break;
                }
@@ -1173,32 +1174,32 @@ int ps3_repository_dump_bus_info(void)
                        &repo.bus_id);
                if (result) {
-                        pr_debug("%s:%d read_bus_id(%u) failed\n",
+                        pr_devel("%s:%d read_bus_id(%u) failed\n",
                                __func__, __LINE__, repo.bus_index);
                        continue;
                }
                if (repo.bus_index != repo.bus_id)
-                        pr_debug("%s:%d bus_index != bus_id\n",
+                        pr_devel("%s:%d bus_index != bus_id\n",
                                __func__, __LINE__);
                result = ps3_repository_read_bus_num_dev(repo.bus_index,
                        &num_dev);
                if (result) {
-                        pr_debug("%s:%d read_bus_num_dev(%u) failed\n",
+                        pr_devel("%s:%d read_bus_num_dev(%u) failed\n",
                                __func__, __LINE__, repo.bus_index);
                        continue;
                }
-                pr_debug("%s:%d bus_%u: bus_type %u, bus_id %lu, num_dev %u\n",
+                pr_devel("%s:%d bus_%u: bus_type %u, bus_id %lu, num_dev %u\n",
                        __func__, __LINE__, repo.bus_index, repo.bus_type,
-                        repo.bus_id, num_dev);
+                        (unsigned long)repo.bus_id, num_dev);
                dump_device_info(&repo, num_dev);
        }
-        pr_debug(" <- %s:%d\n", __func__, __LINE__);
+        pr_devel(" <- %s:%d\n", __func__, __LINE__);
        return result;
 }
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index e8ec1b2bfffd..2d664c5a83b0 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -193,10 +193,12 @@ static int ps3_set_dabr(unsigned long dabr)
 static void __init ps3_setup_arch(void)
 {
+        u64 tmp;
        DBG(" -> %s:%d\n", __func__, __LINE__);
-        lv1_get_version_info(&ps3_firmware_version.raw);
+        lv1_get_version_info(&ps3_firmware_version.raw, &tmp);
        printk(KERN_INFO "PS3 firmware version %u.%u.%u\n",
               ps3_firmware_version.major, ps3_firmware_version.minor,
               ps3_firmware_version.rev);
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c
index efc1cd8c034a..4b35166229fe 100644
--- a/arch/powerpc/platforms/ps3/smp.c
+++ b/arch/powerpc/platforms/ps3/smp.c
@@ -57,7 +57,7 @@ static void ps3_smp_message_pass(int cpu, int msg)
                        " (%d)\n", __func__, __LINE__, cpu, msg, result);
 }
-static int ps3_smp_probe(void)
+static int __init ps3_smp_probe(void)
 {
        int cpu;
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index 451fad1c92a8..e17fa1432d80 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -154,7 +154,7 @@ static unsigned long get_vas_id(void)
        u64 id;
        lv1_get_logical_ppe_id(&id);
-        lv1_get_virtual_address_space_id_of_ppe(id, &id);
+        lv1_get_virtual_address_space_id_of_ppe(&id);
        return id;
 }
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index c81f6bb9c10f..ae7b6d41fed3 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -120,3 +120,12 @@ config DTL
          which are accessible through a debugfs file.
          Say N if you are unsure.
+config PSERIES_IDLE
+        tristate "Cpuidle driver for pSeries platforms"
+        depends on CPU_IDLE
+        depends on PPC_PSERIES
+        default y
+        help
+          Select this option to enable processor idle state management
+          through cpuidle subsystem.
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 3556e402cbf5..236db46b4078 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PHYP_DUMP)		+= phyp_dump.o
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_DTL)               += dtl.o
 obj-$(CONFIG_IO_EVENT_IRQ)      += io_event_irq.o
+obj-$(CONFIG_PSERIES_IDLE)      += processor_idle.o
 ifeq ($(CONFIG_PPC_PSERIES),y)
 obj-$(CONFIG_SUSPEND)           += suspend.o
diff --git a/arch/powerpc/platforms/pseries/hvCall_inst.c b/arch/powerpc/platforms/pseries/hvCall_inst.c
index f106662f4381..c9311cfdfcac 100644
--- a/arch/powerpc/platforms/pseries/hvCall_inst.c
+++ b/arch/powerpc/platforms/pseries/hvCall_inst.c
@@ -109,7 +109,7 @@ static void probe_hcall_entry(void *ignored, unsigned long opcode, unsigned long
        if (opcode > MAX_HCALL_OPCODE)
                return;
-        h = &get_cpu_var(hcall_stats)[opcode / 4];
+        h = &__get_cpu_var(hcall_stats)[opcode / 4];
        h->tb_start = mftb();
        h->purr_start = mfspr(SPRN_PURR);
 }
@@ -126,8 +126,6 @@ static void probe_hcall_exit(void *ignored, unsigned long opcode, unsigned long
        h->num_calls++;
        h->tb_total += mftb() - h->tb_start;
        h->purr_total += mfspr(SPRN_PURR) - h->purr_start;
-        put_cpu_var(hcall_stats);
 }
 static int __init hcall_inst_init(void)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index b719d9709730..c442f2b1980f 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -52,13 +52,42 @@
 #include "plpar_wrappers.h"
+static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
+                                      u64 *startp, u64 *endp)
+{
+        u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
+        unsigned long start, end, inc;
+        start = __pa(startp);
+        end = __pa(endp);
+        inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
+        /* If this is non-zero, change the format.  We shift the
+         * address and or in the magic from the device tree. */
+        if (tbl->it_busno) {
+                start <<= 12;
+                end <<= 12;
+                inc <<= 12;
+                start |= tbl->it_busno;
+                end |= tbl->it_busno;
+        }
+        end |= inc - 1; /* round up end to be different than start */
+        mb(); /* Make sure TCEs in memory are written */
+        while (start <= end) {
+                out_be64(invalidate, start);
+                start += inc;
+        }
+}
 static int tce_build_pSeries(struct iommu_table *tbl, long index,
                              long npages, unsigned long uaddr,
                              enum dma_data_direction direction,
                              struct dma_attrs *attrs)
 {
        u64 proto_tce;
-        u64 *tcep;
+        u64 *tcep, *tces;
        u64 rpn;
        proto_tce = TCE_PCI_READ; // Read allowed
@@ -66,7 +95,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
        if (direction != DMA_TO_DEVICE)
                proto_tce |= TCE_PCI_WRITE;
-        tcep = ((u64 *)tbl->it_base) + index;
+        tces = tcep = ((u64 *)tbl->it_base) + index;
        while (npages--) {
                /* can't move this out since we might cross MEMBLOCK boundary */
@@ -76,18 +105,24 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index,
                uaddr += TCE_PAGE_SIZE;
                tcep++;
        }
+        if (tbl->it_type == TCE_PCI_SWINV_CREATE)
+                tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
        return 0;
 }
 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 {
-        u64 *tcep;
+        u64 *tcep, *tces;
-        tcep = ((u64 *)tbl->it_base) + index;
+        tces = tcep = ((u64 *)tbl->it_base) + index;
        while (npages--)
                *(tcep++) = 0;
+        if (tbl->it_type == TCE_PCI_SWINV_FREE)
+                tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 }
 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
@@ -425,7 +460,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
                                 struct iommu_table *tbl)
 {
        struct device_node *node;
-        const unsigned long *basep;
+        const unsigned long *basep, *sw_inval;
        const u32 *sizep;
        node = phb->dn;
@@ -462,6 +497,22 @@ static void iommu_table_setparms(struct pci_controller *phb,
        tbl->it_index = 0;
        tbl->it_blocksize = 16;
        tbl->it_type = TCE_PCI;
+        sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
+        if (sw_inval) {
+                /*
+                 * This property contains information on how to
+                 * invalidate the TCE entry.  The first property is
+                 * the base MMIO address used to invalidate entries.
+                 * The second property tells us the format of the TCE
+                 * invalidate (whether it needs to be shifted) and
+                 * some magic routing info to add to our invalidate
+                 * command.
+                 */
+                tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
+                tbl->it_busno = sw_inval[1]; /* overload this with magic */
+                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
+        }
 }
 /*
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 52d429be6c76..948e0e3b3547 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -554,6 +554,7 @@ void __trace_hcall_entry(unsigned long opcode, unsigned long *args)
                goto out;
        (*depth)++;
+        preempt_disable();
        trace_hcall_entry(opcode, args);
        if (opcode == H_CEDE)
                rcu_idle_enter();
@@ -580,6 +581,7 @@ void __trace_hcall_exit(long opcode, unsigned long retval,
        if (opcode == H_CEDE)
                rcu_idle_exit();
        trace_hcall_exit(opcode, retval, retbuf);
+        preempt_enable();
        (*depth)--;
 out:
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index a76b22844d18..330a57b7c17c 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -625,6 +625,8 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
 {
        static unsigned int oops_count = 0;
        static bool panicking = false;
+        static DEFINE_SPINLOCK(lock);
+        unsigned long flags;
        size_t text_len;
        unsigned int err_type = ERR_TYPE_KERNEL_PANIC_GZ;
        int rc = -1;
@@ -655,6 +657,9 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
        if (clobbering_unread_rtas_event())
                return;
+        if (!spin_trylock_irqsave(&lock, flags))
+                return;
        if (big_oops_buf) {
                text_len = capture_last_msgs(old_msgs, old_len,
                        new_msgs, new_len, big_oops_buf, big_oops_buf_sz);
@@ -670,4 +675,6 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
        (void) nvram_write_os_partition(&oops_log_partition, oops_buf,
                (int) (sizeof(*oops_len) + *oops_len), err_type, ++oops_count);
+        spin_unlock_irqrestore(&lock, flags);
 }
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
new file mode 100644
index 000000000000..085fd3f45ad2
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -0,0 +1,329 @@
+/*
+ *  processor_idle - idle state cpuidle driver.
+ *  Adapted from drivers/idle/intel_idle.c and
+ *  drivers/acpi/processor_idle.c
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu.h>
+#include <asm/paca.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+#include <asm/machdep.h>
+#include <asm/firmware.h>
+#include "plpar_wrappers.h"
+#include "pseries.h"
+struct cpuidle_driver pseries_idle_driver = {
+        .name =         "pseries_idle",
+        .owner =        THIS_MODULE,
+};
+#define MAX_IDLE_STATE_COUNT    2
+static int max_idle_state = MAX_IDLE_STATE_COUNT - 1;
+static struct cpuidle_device __percpu *pseries_cpuidle_devices;
+static struct cpuidle_state *cpuidle_state_table;
+void update_smt_snooze_delay(int snooze)
+{
+        struct cpuidle_driver *drv = cpuidle_get_driver();
+        if (drv)
+                drv->states[0].target_residency = snooze;
+}
+static inline void idle_loop_prolog(unsigned long *in_purr, ktime_t *kt_before)
+{
+        *kt_before = ktime_get_real();
+        *in_purr = mfspr(SPRN_PURR);
+        /*
+         * Indicate to the HV that we are idle. Now would be
+         * a good time to find other work to dispatch.
+         */
+        get_lppaca()->idle = 1;
+}
+static inline  s64 idle_loop_epilog(unsigned long in_purr, ktime_t kt_before)
+{
+        get_lppaca()->wait_state_cycles += mfspr(SPRN_PURR) - in_purr;
+        get_lppaca()->idle = 0;
+        return ktime_to_us(ktime_sub(ktime_get_real(), kt_before));
+}
+static int snooze_loop(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        unsigned long in_purr;
+        ktime_t kt_before;
+        unsigned long start_snooze;
+        long snooze = drv->states[0].target_residency;
+        idle_loop_prolog(&in_purr, &kt_before);
+        if (snooze) {
+                start_snooze = get_tb() + snooze * tb_ticks_per_usec;
+                local_irq_enable();
+                set_thread_flag(TIF_POLLING_NRFLAG);
+                while ((snooze < 0) || (get_tb() < start_snooze)) {
+                        if (need_resched() || cpu_is_offline(dev->cpu))
+                                goto out;
+                        ppc64_runlatch_off();
+                        HMT_low();
+                        HMT_very_low();
+                }
+                HMT_medium();
+                clear_thread_flag(TIF_POLLING_NRFLAG);
+                smp_mb();
+                local_irq_disable();
+        }
+out:
+        HMT_medium();
+        dev->last_residency =
+                (int)idle_loop_epilog(in_purr, kt_before);
+        return index;
+}
+static int dedicated_cede_loop(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        unsigned long in_purr;
+        ktime_t kt_before;
+        idle_loop_prolog(&in_purr, &kt_before);
+        get_lppaca()->donate_dedicated_cpu = 1;
+        ppc64_runlatch_off();
+        HMT_medium();
+        cede_processor();
+        get_lppaca()->donate_dedicated_cpu = 0;
+        dev->last_residency =
+                (int)idle_loop_epilog(in_purr, kt_before);
+        return index;
+}
+static int shared_cede_loop(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        unsigned long in_purr;
+        ktime_t kt_before;
+        idle_loop_prolog(&in_purr, &kt_before);
+        /*
+         * Yield the processor to the hypervisor.  We return if
+         * an external interrupt occurs (which are driven prior
+         * to returning here) or if a prod occurs from another
+         * processor. When returning here, external interrupts
+         * are enabled.
+         */
+        cede_processor();
+        dev->last_residency =
+                (int)idle_loop_epilog(in_purr, kt_before);
+        return index;
+}
+/*
+ * States for dedicated partition case.
+ */
+static struct cpuidle_state dedicated_states[MAX_IDLE_STATE_COUNT] = {
+        { /* Snooze */
+                .name = "snooze",
+                .desc = "snooze",
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 0,
+                .target_residency = 0,
+                .enter = &snooze_loop },
+        { /* CEDE */
+                .name = "CEDE",
+                .desc = "CEDE",
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 1,
+                .target_residency = 10,
+                .enter = &dedicated_cede_loop },
+};
+/*
+ * States for shared partition case.
+ */
+static struct cpuidle_state shared_states[MAX_IDLE_STATE_COUNT] = {
+        { /* Shared Cede */
+                .name = "Shared Cede",
+                .desc = "Shared Cede",
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 0,
+                .target_residency = 0,
+                .enter = &shared_cede_loop },
+};
+int pseries_notify_cpuidle_add_cpu(int cpu)
+{
+        struct cpuidle_device *dev =
+                        per_cpu_ptr(pseries_cpuidle_devices, cpu);
+        if (dev && cpuidle_get_driver()) {
+                cpuidle_disable_device(dev);
+                cpuidle_enable_device(dev);
+        }
+        return 0;
+}
+/*
+ * pseries_cpuidle_driver_init()
+ */
+static int pseries_cpuidle_driver_init(void)
+{
+        int idle_state;
+        struct cpuidle_driver *drv = &pseries_idle_driver;
+        drv->state_count = 0;
+        for (idle_state = 0; idle_state < MAX_IDLE_STATE_COUNT; ++idle_state) {
+                if (idle_state > max_idle_state)
+                        break;
+                /* is the state not enabled? */
+                if (cpuidle_state_table[idle_state].enter == NULL)
+                        continue;
+                drv->states[drv->state_count] = /* structure copy */
+                        cpuidle_state_table[idle_state];
+                if (cpuidle_state_table == dedicated_states)
+                        drv->states[drv->state_count].target_residency =
+                                __get_cpu_var(smt_snooze_delay);
+                drv->state_count += 1;
+        }
+        return 0;
+}
+/* pseries_idle_devices_uninit(void)
+ * unregister cpuidle devices and de-allocate memory
+ */
+static void pseries_idle_devices_uninit(void)
+{
+        int i;
+        struct cpuidle_device *dev;
+        for_each_possible_cpu(i) {
+                dev = per_cpu_ptr(pseries_cpuidle_devices, i);
+                cpuidle_unregister_device(dev);
+        }
+        free_percpu(pseries_cpuidle_devices);
+        return;
+}
+/* pseries_idle_devices_init()
+ * allocate, initialize and register cpuidle device
+ */
+static int pseries_idle_devices_init(void)
+{
+        int i;
+        struct cpuidle_driver *drv = &pseries_idle_driver;
+        struct cpuidle_device *dev;
+        pseries_cpuidle_devices = alloc_percpu(struct cpuidle_device);
+        if (pseries_cpuidle_devices == NULL)
+                return -ENOMEM;
+        for_each_possible_cpu(i) {
+                dev = per_cpu_ptr(pseries_cpuidle_devices, i);
+                dev->state_count = drv->state_count;
+                dev->cpu = i;
+                if (cpuidle_register_device(dev)) {
+                        printk(KERN_DEBUG \
+                                "cpuidle_register_device %d failed!\n", i);
+                        return -EIO;
+                }
+        }
+        return 0;
+}
+/*
+ * pseries_idle_probe()
+ * Choose state table for shared versus dedicated partition
+ */
+static int pseries_idle_probe(void)
+{
+        if (!firmware_has_feature(FW_FEATURE_SPLPAR))
+                return -ENODEV;
+        if (cpuidle_disable != IDLE_NO_OVERRIDE)
+                return -ENODEV;
+        if (max_idle_state == 0) {
+                printk(KERN_DEBUG "pseries processor idle disabled.\n");
+                return -EPERM;
+        }
+        if (get_lppaca()->shared_proc)
+                cpuidle_state_table = shared_states;
+        else
+                cpuidle_state_table = dedicated_states;
+        return 0;
+}
+static int __init pseries_processor_idle_init(void)
+{
+        int retval;
+        retval = pseries_idle_probe();
+        if (retval)
+                return retval;
+        pseries_cpuidle_driver_init();
+        retval = cpuidle_register_driver(&pseries_idle_driver);
+        if (retval) {
+                printk(KERN_DEBUG "Registration of pseries driver failed.\n");
+                return retval;
+        }
+        retval = pseries_idle_devices_init();
+        if (retval) {
+                pseries_idle_devices_uninit();
+                cpuidle_unregister_driver(&pseries_idle_driver);
+                return retval;
+        }
+        printk(KERN_DEBUG "pseries_idle_driver registered\n");
+        return 0;
+}
+static void __exit pseries_processor_idle_exit(void)
+{
+        pseries_idle_devices_uninit();
+        cpuidle_unregister_driver(&pseries_idle_driver);
+        return;
+}
+module_init(pseries_processor_idle_init);
+module_exit(pseries_processor_idle_exit);
+MODULE_AUTHOR("Deepthi Dharwar <deepthi@linux.vnet.ibm.com>");
+MODULE_DESCRIPTION("Cpuidle driver for POWER");
+MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 24c7162f11d9..9a3dda07566f 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -57,4 +57,7 @@ extern struct device_node *dlpar_configure_connector(u32);
 extern int dlpar_attach_node(struct device_node *);
 extern int dlpar_detach_node(struct device_node *);
+/* Snooze Delay, pseries_idle */
+DECLARE_PER_CPU(long, smt_snooze_delay);
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index c3408ca8855e..f79f1278dfca 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -39,6 +39,7 @@
 #include <linux/irq.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
+#include <linux/cpuidle.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
@@ -74,9 +75,6 @@ EXPORT_SYMBOL(CMO_PageSize);
 int fwnmi_active;  /* TRUE if an FWNMI handler is present */
-static void pseries_shared_idle_sleep(void);
-static void pseries_dedicated_idle_sleep(void);
 static struct device_node *pSeries_mpic_node;
 static void pSeries_show_cpuinfo(struct seq_file *m)
@@ -192,8 +190,7 @@ static void __init pseries_mpic_init_IRQ(void)
        BUG_ON(openpic_addr == 0);
        /* Setup the openpic driver */
-        mpic = mpic_alloc(pSeries_mpic_node, openpic_addr,
+        mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 0,
-                          MPIC_PRIMARY,
                          16, 250, /* isu size, irq count */
                          " MPIC     ");
        BUG_ON(mpic == NULL);
@@ -352,8 +349,25 @@ static int alloc_dispatch_log_kmem_cache(void)
 }
 early_initcall(alloc_dispatch_log_kmem_cache);
+static void pSeries_idle(void)
+{
+        /* This would call on the cpuidle framework, and the back-end pseries
+         * driver to  go to idle states
+         */
+        if (cpuidle_idle_call()) {
+                /* On error, execute default handler
+                 * to go into low thread priority and possibly
+                 * low power mode.
+                 */
+                HMT_low();
+                HMT_very_low();
+        }
+}
 static void __init pSeries_setup_arch(void)
 {
+        panic_timeout = 10;
        /* Discover PIC type and setup ppc_md accordingly */
        pseries_discover_pic();
@@ -374,18 +388,9 @@ static void __init pSeries_setup_arch(void)
        pSeries_nvram_init();
-        /* Choose an idle loop */
        if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
                vpa_init(boot_cpuid);
-                if (get_lppaca()->shared_proc) {
+                ppc_md.power_save = pSeries_idle;
-                        printk(KERN_DEBUG "Using shared processor idle loop\n");
-                        ppc_md.power_save = pseries_shared_idle_sleep;
-                } else {
-                        printk(KERN_DEBUG "Using dedicated idle loop\n");
-                        ppc_md.power_save = pseries_dedicated_idle_sleep;
-                }
-        } else {
-                printk(KERN_DEBUG "Using default idle loop\n");
        }
        if (firmware_has_feature(FW_FEATURE_LPAR))
@@ -586,80 +591,6 @@ static int __init pSeries_probe(void)
        return 1;
 }
-DECLARE_PER_CPU(long, smt_snooze_delay);
-static void pseries_dedicated_idle_sleep(void)
-{ 
-        unsigned int cpu = smp_processor_id();
-        unsigned long start_snooze;
-        unsigned long in_purr, out_purr;
-        long snooze = __get_cpu_var(smt_snooze_delay);
-        /*
-         * Indicate to the HV that we are idle. Now would be
-         * a good time to find other work to dispatch.
-         */
-        get_lppaca()->idle = 1;
-        get_lppaca()->donate_dedicated_cpu = 1;
-        in_purr = mfspr(SPRN_PURR);
-        /*
-         * We come in with interrupts disabled, and need_resched()
-         * has been checked recently.  If we should poll for a little
-         * while, do so.
-         */
-        if (snooze) {
-                start_snooze = get_tb() + snooze * tb_ticks_per_usec;
-                local_irq_enable();
-                set_thread_flag(TIF_POLLING_NRFLAG);
-                while ((snooze < 0) || (get_tb() < start_snooze)) {
-                        if (need_resched() || cpu_is_offline(cpu))
-                                goto out;
-                        ppc64_runlatch_off();
-                        HMT_low();
-                        HMT_very_low();
-                }
-                HMT_medium();
-                clear_thread_flag(TIF_POLLING_NRFLAG);
-                smp_mb();
-                local_irq_disable();
-                if (need_resched() || cpu_is_offline(cpu))
-                        goto out;
-        }
-        cede_processor();
-out:
-        HMT_medium();
-        out_purr = mfspr(SPRN_PURR);
-        get_lppaca()->wait_state_cycles += out_purr - in_purr;
-        get_lppaca()->donate_dedicated_cpu = 0;
-        get_lppaca()->idle = 0;
-}
-static void pseries_shared_idle_sleep(void)
-{
-        /*
-         * Indicate to the HV that we are idle. Now would be
-         * a good time to find other work to dispatch.
-         */
-        get_lppaca()->idle = 1;
-        /*
-         * Yield the processor to the hypervisor.  We return if
-         * an external interrupt occurs (which are driven prior
-         * to returning here) or if a prod occurs from another
-         * processor. When returning here, external interrupts
-         * are enabled.
-         */
-        cede_processor();
-        get_lppaca()->idle = 0;
-}
 static int pSeries_pci_probe_mode(struct pci_bus *bus)
 {
        if (firmware_has_feature(FW_FEATURE_LPAR))
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 26e93fd4c62b..bbc3c42f6730 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -148,6 +148,7 @@ static void __devinit smp_xics_setup_cpu(int cpu)
        set_cpu_current_state(cpu, CPU_STATE_ONLINE);
        set_default_offline_state(cpu);
 #endif
+        pseries_notify_cpuidle_add_cpu(cpu);
 }
 static int __devinit smp_pSeries_kick_cpu(int nr)
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index bd560c786ed6..57d22a2f4ba9 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,20 +1,28 @@
 config PPC_WSP
        bool
        select PPC_A2
+        select GENERIC_TBSYNC
+        select PPC_ICSWX
        select PPC_SCOM
        select PPC_XICS
        select PPC_ICP_NATIVE
        select PCI
        select PPC_IO_WORKAROUNDS if PCI
        select PPC_INDIRECT_PIO if PCI
+        select PPC_WSP_COPRO
        default n
 menu "WSP platform selection"
        depends on PPC_BOOK3E_64
 config PPC_PSR2
-        bool "PSR-2 platform"
+        bool "PowerEN System Reference Platform 2"
-        select GENERIC_TBSYNC
+        select EPAPR_BOOT
+        select PPC_WSP
+        default y
+config PPC_CHROMA
+        bool "PowerEN PCIe Chroma Card"
        select EPAPR_BOOT
        select PPC_WSP
        default y
diff --git a/arch/powerpc/platforms/wsp/Makefile b/arch/powerpc/platforms/wsp/Makefile
index a1486b436f02..56817ac98fc9 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -1,8 +1,10 @@
 ccflags-y                       += -mno-minimal-toc
-obj-y                           += setup.o ics.o
+obj-y                           += setup.o ics.o wsp.o
-obj-$(CONFIG_PPC_PSR2)          += psr2.o opb_pic.o
+obj-$(CONFIG_PPC_PSR2)          += psr2.o
+obj-$(CONFIG_PPC_CHROMA)        += chroma.o h8.o
+obj-$(CONFIG_PPC_WSP)           += opb_pic.o
 obj-$(CONFIG_PPC_WSP)           += scom_wsp.o
 obj-$(CONFIG_SMP)               += smp.o scom_smp.o
 obj-$(CONFIG_PCI)               += wsp_pci.o
-obj-$(CONFIG_PCI_MSI)           += msi.o
-\ No newline at end of file
+obj-$(CONFIG_PCI_MSI)           += msi.o
diff --git a/arch/powerpc/platforms/wsp/chroma.c b/arch/powerpc/platforms/wsp/chroma.c
new file mode 100644
index 000000000000..ca6fa26f6e63
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/chroma.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008-2011, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+#include <linux/time.h>
+#include <asm/machdep.h>
+#include <asm/system.h>
+#include <asm/udbg.h>
+#include "ics.h"
+#include "wsp.h"
+void __init chroma_setup_arch(void)
+{
+        wsp_setup_arch();
+        wsp_setup_h8();
+}
+static int __init chroma_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        if (!of_flat_dt_is_compatible(root, "ibm,wsp-chroma"))
+                return 0;
+        return 1;
+}
+define_machine(chroma_md) {
+        .name                   = "Chroma PCIe",
+        .probe                  = chroma_probe,
+        .setup_arch             = chroma_setup_arch,
+        .restart                = wsp_h8_restart,
+        .power_off              = wsp_h8_power_off,
+        .halt                   = wsp_halt,
+        .calibrate_decr         = generic_calibrate_decr,
+        .init_IRQ               = wsp_setup_irq,
+        .progress               = udbg_progress,
+        .power_save             = book3e_idle,
+};
+machine_arch_initcall(chroma_md, wsp_probe_devices);
diff --git a/arch/powerpc/platforms/wsp/h8.c b/arch/powerpc/platforms/wsp/h8.c
new file mode 100644
index 000000000000..d18e6cc19df3
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/h8.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2008-2011, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include "wsp.h"
+/*
+ * The UART connection to the H8 is over ttyS1 which is just a 16550.
+ * We assume that FW has it setup right and no one messes with it.
+ */
+static u8 __iomem *h8;
+#define RBR 0           /* Receiver Buffer Register */
+#define THR 0           /* Transmitter Holding Register */
+#define LSR 5           /* Line Status Register */
+#define LSR_DR 0x01     /* LSR value for Data-Ready */
+#define LSR_THRE 0x20   /* LSR value for Transmitter-Holding-Register-Empty */
+static void wsp_h8_putc(int c)
+{
+        u8 lsr;
+        do {
+                lsr = readb(h8 + LSR);
+        } while ((lsr & LSR_THRE) != LSR_THRE);
+        writeb(c, h8 + THR);
+}
+static int wsp_h8_getc(void)
+{
+        u8 lsr;
+        do {
+                lsr = readb(h8 + LSR);
+        } while ((lsr & LSR_DR) != LSR_DR);
+        return readb(h8 + RBR);
+}
+static void wsp_h8_puts(const char *s, int sz)
+{
+        int i;
+        for (i = 0; i < sz; i++) {
+                wsp_h8_putc(s[i]);
+                /* no flow control so wait for echo */
+                wsp_h8_getc();
+        }
+        wsp_h8_putc('\r');
+        wsp_h8_putc('\n');
+}
+static void wsp_h8_terminal_cmd(const char *cmd, int sz)
+{
+        hard_irq_disable();
+        wsp_h8_puts(cmd, sz);
+        /* should never return, but just in case */
+        for (;;)
+                continue;
+}
+void wsp_h8_restart(char *cmd)
+{
+        static const char restart[] = "warm-reset";
+        (void)cmd;
+        wsp_h8_terminal_cmd(restart, sizeof(restart) - 1);
+}
+void wsp_h8_power_off(void)
+{
+        static const char off[] = "power-off";
+        wsp_h8_terminal_cmd(off, sizeof(off) - 1);
+}
+static void __iomem *wsp_h8_getaddr(void)
+{
+        struct device_node *aliases;
+        struct device_node *uart;
+        struct property *path;
+        void __iomem *va = NULL;
+        /*
+         * there is nothing in the devtree to tell us which is mapped
+         * to the H8, but se know it is the second serial port.
+         */
+        aliases = of_find_node_by_path("/aliases");
+        if (aliases == NULL)
+                return NULL;
+        path = of_find_property(aliases, "serial1", NULL);
+        if (path == NULL)
+                goto out;
+        uart = of_find_node_by_path(path->value);
+        if (uart == NULL)
+                goto out;
+        va = of_iomap(uart, 0);
+        /* remove it so no one messes with it */
+        of_detach_node(uart);
+        of_node_put(uart);
+out:
+        of_node_put(aliases);
+        return va;
+}
+void __init wsp_setup_h8(void)
+{
+        h8 = wsp_h8_getaddr();
+        /* Devtree change? lets hard map it anyway */
+        if (h8 == NULL) {
+                pr_warn("UART to H8 could not be found");
+                h8 = ioremap(0xffc0008000ULL, 0x100);
+        }
+}
diff --git a/arch/powerpc/platforms/wsp/opb_pic.c b/arch/powerpc/platforms/wsp/opb_pic.c
index be05631a3c1c..19f353dfcd03 100644
--- a/arch/powerpc/platforms/wsp/opb_pic.c
+++ b/arch/powerpc/platforms/wsp/opb_pic.c
@@ -320,7 +320,8 @@ void __init opb_pic_init(void)
                }
                /* Attach opb interrupt handler to new virtual IRQ */
-                rc = request_irq(virq, opb_irq_handler, 0, "OPB LS Cascade", opb);
+                rc = request_irq(virq, opb_irq_handler, IRQF_NO_THREAD,
+                                 "OPB LS Cascade", opb);
                if (rc) {
                        printk("opb: request_irq failed: %d\n", rc);
                        continue;
diff --git a/arch/powerpc/platforms/wsp/psr2.c b/arch/powerpc/platforms/wsp/psr2.c
index 166f2e4b4bee..0c1ae06d0be1 100644
--- a/arch/powerpc/platforms/wsp/psr2.c
+++ b/arch/powerpc/platforms/wsp/psr2.c
@@ -14,10 +14,10 @@
 #include <linux/mm.h>
 #include <linux/of.h>
 #include <linux/smp.h>
+#include <linux/time.h>
 #include <asm/machdep.h>
 #include <asm/system.h>
-#include <asm/time.h>
 #include <asm/udbg.h>
 #include "ics.h"
@@ -27,7 +27,8 @@
 static void psr2_spin(void)
 {
        hard_irq_disable();
-        for (;;) ;
+        for (;;)
+                continue;
 }
 static void psr2_restart(char *cmd)
@@ -35,65 +36,32 @@ static void psr2_restart(char *cmd)
        psr2_spin();
 }
-static int psr2_probe_devices(void)
-{
-        struct device_node *np;
-        /* Our RTC is a ds1500. It seems to be programatically compatible
-         * with the ds1511 for which we have a driver so let's use that
-         */
-        np = of_find_compatible_node(NULL, NULL, "dallas,ds1500");
-        if (np != NULL) {
-                struct resource res;
-                if (of_address_to_resource(np, 0, &res) == 0)
-                        platform_device_register_simple("ds1511", 0, &res, 1);
-        }
-        return 0;
-}
-machine_arch_initcall(psr2_md, psr2_probe_devices);
-static void __init psr2_setup_arch(void)
-{
-        /* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000;
-        scom_init_wsp();
-        /* Setup SMP callback */
-#ifdef CONFIG_SMP
-        a2_setup_smp();
-#endif
-#ifdef CONFIG_PCI
-        wsp_setup_pci();
-#endif
-}
 static int __init psr2_probe(void)
 {
        unsigned long root = of_get_flat_dt_root();
+        if (of_flat_dt_is_compatible(root, "ibm,wsp-chroma")) {
+                /* chroma systems also claim they are psr2s */
+                return 0;
+        }
        if (!of_flat_dt_is_compatible(root, "ibm,psr2"))
                return 0;
        return 1;
 }
-static void __init psr2_init_irq(void)
-{
-        wsp_init_irq();
-        opb_pic_init();
-}
 define_machine(psr2_md) {
        .name                   = "PSR2 A2",
        .probe                  = psr2_probe,
-        .setup_arch             = psr2_setup_arch,
+        .setup_arch             = wsp_setup_arch,
        .restart                = psr2_restart,
        .power_off              = psr2_spin,
        .halt                   = psr2_spin,
        .calibrate_decr         = generic_calibrate_decr,
-        .init_IRQ               = psr2_init_irq,
+        .init_IRQ               = wsp_setup_irq,
        .progress               = udbg_progress,
        .power_save             = book3e_idle,
 };
+machine_arch_initcall(psr2_md, wsp_probe_devices);
diff --git a/arch/powerpc/platforms/wsp/wsp.c b/arch/powerpc/platforms/wsp/wsp.c
new file mode 100644
index 000000000000..d25cc96c21b8
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/wsp.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2008-2011, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/smp.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <asm/scom.h>
+#include "wsp.h"
+#include "ics.h"
+#define WSP_SOC_COMPATIBLE      "ibm,wsp-soc"
+#define PBIC_COMPATIBLE         "ibm,wsp-pbic"
+#define COPRO_COMPATIBLE        "ibm,wsp-coprocessor"
+static int __init wsp_probe_buses(void)
+{
+        static __initdata struct of_device_id bus_ids[] = {
+                /*
+                 * every node in between needs to be here or you won't
+                 * find it
+                 */
+                { .compatible = WSP_SOC_COMPATIBLE, },
+                { .compatible = PBIC_COMPATIBLE, },
+                { .compatible = COPRO_COMPATIBLE, },
+                {},
+        };
+        of_platform_bus_probe(NULL, bus_ids, NULL);
+        return 0;
+}
+void __init wsp_setup_arch(void)
+{
+        /* init to some ~sane value until calibrate_delay() runs */
+        loops_per_jiffy = 50000000;
+        scom_init_wsp();
+        /* Setup SMP callback */
+#ifdef CONFIG_SMP
+        a2_setup_smp();
+#endif
+#ifdef CONFIG_PCI
+        wsp_setup_pci();
+#endif
+}
+void __init wsp_setup_irq(void)
+{
+        wsp_init_irq();
+        opb_pic_init();
+}
+int __init wsp_probe_devices(void)
+{
+        struct device_node *np;
+        /* Our RTC is a ds1500. It seems to be programatically compatible
+         * with the ds1511 for which we have a driver so let's use that
+         */
+        np = of_find_compatible_node(NULL, NULL, "dallas,ds1500");
+        if (np != NULL) {
+                struct resource res;
+                if (of_address_to_resource(np, 0, &res) == 0)
+                        platform_device_register_simple("ds1511", 0, &res, 1);
+        }
+        wsp_probe_buses();
+        return 0;
+}
+void wsp_halt(void)
+{
+        u64 val;
+        scom_map_t m;
+        struct device_node *dn;
+        struct device_node *mine;
+        struct device_node *me;
+        me = of_get_cpu_node(smp_processor_id(), NULL);
+        mine = scom_find_parent(me);
+        /* This will halt all the A2s but not power off the chip */
+        for_each_node_with_property(dn, "scom-controller") {
+                if (dn == mine)
+                        continue;
+                m = scom_map(dn, 0, 1);
+                /* read-modify-write it so the HW probe does not get
+                 * confused */
+                val = scom_read(m, 0);
+                val |= 1;
+                scom_write(m, 0, val);
+                scom_unmap(m);
+        }
+        m = scom_map(mine, 0, 1);
+        val = scom_read(m, 0);
+        val |= 1;
+        scom_write(m, 0, val);
+        /* should never return */
+        scom_unmap(m);
+}
diff --git a/arch/powerpc/platforms/wsp/wsp.h b/arch/powerpc/platforms/wsp/wsp.h
index 33479818f62a..10c1d1fff362 100644
--- a/arch/powerpc/platforms/wsp/wsp.h
+++ b/arch/powerpc/platforms/wsp/wsp.h
@@ -6,15 +6,25 @@
 /* Devtree compatible strings for major devices */
 #define PCIE_COMPATIBLE     "ibm,wsp-pciex"
+extern void wsp_setup_arch(void);
+extern void wsp_setup_irq(void);
+extern int wsp_probe_devices(void);
+extern void wsp_halt(void);
 extern void wsp_setup_pci(void);
 extern void scom_init_wsp(void);
 extern void a2_setup_smp(void);
 extern int a2_scom_startup_cpu(unsigned int lcpu, int thr_idx,
                               struct device_node *np);
-int smp_a2_cpu_bootable(unsigned int nr);
+extern int smp_a2_cpu_bootable(unsigned int nr);
-int __devinit smp_a2_kick_cpu(int nr);
+extern int __devinit smp_a2_kick_cpu(int nr);
+extern void opb_pic_init(void);
-void opb_pic_init(void);
+/* chroma specific managment */
+extern void wsp_h8_restart(char *cmd);
+extern void wsp_h8_power_off(void);
+extern void __init wsp_setup_h8(void);
 #endif /*  __WSP_H */
diff --git a/arch/powerpc/relocs_check.pl b/arch/powerpc/relocs_check.pl
index d2571096c3e9..7f5b83808862 100755
--- a/arch/powerpc/relocs_check.pl
+++ b/arch/powerpc/relocs_check.pl
@@ -32,8 +32,18 @@ while (<FD>) {
        next if (!/\s+R_/);
        # These relocations are okay
-        next if (/R_PPC64_RELATIVE/ or /R_PPC64_NONE/ or
+        # On PPC64:
-                 /R_PPC64_ADDR64\s+mach_/);
+        #       R_PPC64_RELATIVE, R_PPC64_NONE, R_PPC64_ADDR64
+        # On PPC:
+        #       R_PPC_RELATIVE, R_PPC_ADDR16_HI, 
+        #       R_PPC_ADDR16_HA,R_PPC_ADDR16_LO,
+        #       R_PPC_NONE
+        next if (/\bR_PPC64_RELATIVE\b/ or /\bR_PPC64_NONE\b/ or
+                 /\bR_PPC64_ADDR64\s+mach_/);
+        next if (/\bR_PPC_ADDR16_LO\b/ or /\bR_PPC_ADDR16_HI\b/ or
+                 /\bR_PPC_ADDR16_HA\b/ or /\bR_PPC_RELATIVE\b/ or
+                 /\bR_PPC_NONE\b/);
        # If we see this type of relcoation it's an idication that
        # we /may/ be using an old version of binutils.
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 84e13253aec5..5e37b4717864 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,10 +17,11 @@ obj-$(CONFIG_FSL_SOC)		+= fsl_soc.o
 obj-$(CONFIG_FSL_PCI)           += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)           += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
+obj-$(CONFIG_FSL_IFC)           += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)           += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)       += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)       += simple_gpio.o
-obj-$(CONFIG_FSL_RIO)           += fsl_rio.o
+obj-$(CONFIG_FSL_RIO)           += fsl_rio.o fsl_rmu.o
 obj-$(CONFIG_TSI108_BRIDGE)     += tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE)      += qe_lib/
 obj-$(CONFIG_PPC_BESTCOMM)      += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
new file mode 100644
index 000000000000..b31f19f61031
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Freescale Integrated Flash Controller
+ *
+ * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <asm/prom.h>
+#include <asm/fsl_ifc.h>
+struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+/*
+ * convert_ifc_address - convert the base address
+ * @addr_base:  base address of the memory bank
+ */
+unsigned int convert_ifc_address(phys_addr_t addr_base)
+{
+        return addr_base & CSPR_BA;
+}
+EXPORT_SYMBOL(convert_ifc_address);
+/*
+ * fsl_ifc_find - find IFC bank
+ * @addr_base:  base address of the memory bank
+ *
+ * This function walks IFC banks comparing "Base address" field of the CSPR
+ * registers with the supplied addr_base argument. When bases match this
+ * function returns bank number (starting with 0), otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_ifc_find(phys_addr_t addr_base)
+{
+        int i = 0;
+        if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
+                return -ENODEV;
+        for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
+                __be32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
+                if (cspr & CSPR_V && (cspr & CSPR_BA) ==
+                                convert_ifc_address(addr_base))
+                        return i;
+        }
+        return -ENOENT;
+}
+EXPORT_SYMBOL(fsl_ifc_find);
+static int __devinit fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
+{
+        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+        /*
+         * Clear all the common status and event registers
+         */
+        if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
+                out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+        /* enable all error and events */
+        out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
+        /* enable all error and event interrupts */
+        out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
+        out_be32(&ifc->cm_erattr0, 0x0);
+        out_be32(&ifc->cm_erattr1, 0x0);
+        return 0;
+}
+static int fsl_ifc_ctrl_remove(struct platform_device *dev)
+{
+        struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
+        free_irq(ctrl->nand_irq, ctrl);
+        free_irq(ctrl->irq, ctrl);
+        irq_dispose_mapping(ctrl->nand_irq);
+        irq_dispose_mapping(ctrl->irq);
+        iounmap(ctrl->regs);
+        dev_set_drvdata(&dev->dev, NULL);
+        kfree(ctrl);
+        return 0;
+}
+/*
+ * NAND events are split between an operational interrupt which only
+ * receives OPC, and an error interrupt that receives everything else,
+ * including non-NAND errors.  Whichever interrupt gets to it first
+ * records the status and wakes the wait queue.
+ */
+static DEFINE_SPINLOCK(nand_irq_lock);
+static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
+{
+        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+        unsigned long flags;
+        u32 stat;
+        spin_lock_irqsave(&nand_irq_lock, flags);
+        stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
+        if (stat) {
+                out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
+                ctrl->nand_stat = stat;
+                wake_up(&ctrl->nand_wait);
+        }
+        spin_unlock_irqrestore(&nand_irq_lock, flags);
+        return stat;
+}
+static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
+{
+        struct fsl_ifc_ctrl *ctrl = data;
+        if (check_nand_stat(ctrl))
+                return IRQ_HANDLED;
+        return IRQ_NONE;
+}
+/*
+ * NOTE: This interrupt is used to report ifc events of various kinds,
+ * such as transaction errors on the chipselects.
+ */
+static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
+{
+        struct fsl_ifc_ctrl *ctrl = data;
+        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+        u32 err_axiid, err_srcid, status, cs_err, err_addr;
+        irqreturn_t ret = IRQ_NONE;
+        /* read for chip select error */
+        cs_err = in_be32(&ifc->cm_evter_stat);
+        if (cs_err) {
+                dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
+                                "any memory bank 0x%08X\n", cs_err);
+                /* clear the chip select error */
+                out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+                /* read error attribute registers print the error information */
+                status = in_be32(&ifc->cm_erattr0);
+                err_addr = in_be32(&ifc->cm_erattr1);
+                if (status & IFC_CM_ERATTR0_ERTYP_READ)
+                        dev_err(ctrl->dev, "Read transaction error"
+                                "CM_ERATTR0 0x%08X\n", status);
+                else
+                        dev_err(ctrl->dev, "Write transaction error"
+                                "CM_ERATTR0 0x%08X\n", status);
+                err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
+                                        IFC_CM_ERATTR0_ERAID_SHIFT;
+                dev_err(ctrl->dev, "AXI ID of the error"
+                                        "transaction 0x%08X\n", err_axiid);
+                err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
+                                        IFC_CM_ERATTR0_ESRCID_SHIFT;
+                dev_err(ctrl->dev, "SRC ID of the error"
+                                        "transaction 0x%08X\n", err_srcid);
+                dev_err(ctrl->dev, "Transaction Address corresponding to error"
+                                        "ERADDR 0x%08X\n", err_addr);
+                ret = IRQ_HANDLED;
+        }
+        if (check_nand_stat(ctrl))
+                ret = IRQ_HANDLED;
+        return ret;
+}
+/*
+ * fsl_ifc_ctrl_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code allocates all of
+ * the resources needed for the controller only.  The
+ * resources for the NAND banks themselves are allocated
+ * in the chip probe function.
+*/
+static int __devinit fsl_ifc_ctrl_probe(struct platform_device *dev)
+{
+        int ret = 0;
+        dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
+        fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
+        if (!fsl_ifc_ctrl_dev)
+                return -ENOMEM;
+        dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
+        /* IOMAP the entire IFC region */
+        fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
+        if (!fsl_ifc_ctrl_dev->regs) {
+                dev_err(&dev->dev, "failed to get memory region\n");
+                ret = -ENODEV;
+                goto err;
+        }
+        /* get the Controller level irq */
+        fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+        if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
+                dev_err(&dev->dev, "failed to get irq resource "
+                                                        "for IFC\n");
+                ret = -ENODEV;
+                goto err;
+        }
+        /* get the nand machine irq */
+        fsl_ifc_ctrl_dev->nand_irq =
+                        irq_of_parse_and_map(dev->dev.of_node, 1);
+        if (fsl_ifc_ctrl_dev->nand_irq == NO_IRQ) {
+                dev_err(&dev->dev, "failed to get irq resource "
+                                                "for NAND Machine\n");
+                ret = -ENODEV;
+                goto err;
+        }
+        fsl_ifc_ctrl_dev->dev = &dev->dev;
+        ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
+        if (ret < 0)
+                goto err;
+        init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
+        ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
+                          "fsl-ifc", fsl_ifc_ctrl_dev);
+        if (ret != 0) {
+                dev_err(&dev->dev, "failed to install irq (%d)\n",
+                        fsl_ifc_ctrl_dev->irq);
+                goto err_irq;
+        }
+        ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq, 0,
+                          "fsl-ifc-nand", fsl_ifc_ctrl_dev);
+        if (ret != 0) {
+                dev_err(&dev->dev, "failed to install irq (%d)\n",
+                        fsl_ifc_ctrl_dev->nand_irq);
+                goto err_nandirq;
+        }
+        return 0;
+err_nandirq:
+        free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
+        irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
+err_irq:
+        free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
+        irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
+err:
+        return ret;
+}
+static const struct of_device_id fsl_ifc_match[] = {
+        {
+                .compatible = "fsl,ifc",
+        },
+        {},
+};
+static struct platform_driver fsl_ifc_ctrl_driver = {
+        .driver = {
+                .name   = "fsl-ifc",
+                .of_match_table = fsl_ifc_match,
+        },
+        .probe       = fsl_ifc_ctrl_probe,
+        .remove      = fsl_ifc_ctrl_remove,
+};
+module_platform_driver(fsl_ifc_ctrl_driver);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index d5c3c90ee698..483126d7b3c0 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -332,6 +332,38 @@ err:
        return ret;
 }
+#ifdef CONFIG_SUSPEND
+/* save lbc registers */
+static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
+        struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+        ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
+        if (!ctrl->saved_regs)
+                return -ENOMEM;
+        _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
+        return 0;
+}
+/* restore lbc registers */
+static int fsl_lbc_resume(struct platform_device *pdev)
+{
+        struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
+        struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+        if (ctrl->saved_regs) {
+                _memcpy_toio(lbc, ctrl->saved_regs,
+                                sizeof(struct fsl_lbc_regs));
+                kfree(ctrl->saved_regs);
+                ctrl->saved_regs = NULL;
+        }
+        return 0;
+}
+#endif /* CONFIG_SUSPEND */
 static const struct of_device_id fsl_lbc_match[] = {
        { .compatible = "fsl,elbc", },
        { .compatible = "fsl,pq3-localbus", },
@@ -346,6 +378,10 @@ static struct platform_driver fsl_lbc_ctrl_driver = {
                .of_match_table = fsl_lbc_match,
        },
        .probe = fsl_lbc_ctrl_probe,
+#ifdef CONFIG_SUSPEND
+        .suspend     = fsl_lbc_suspend,
+        .resume      = fsl_lbc_resume,
+#endif
 };
 static int __init fsl_lbc_init(void)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index e5c344d336ea..ecb5c1946d22 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -23,6 +23,8 @@
 #include <asm/hw_irq.h>
 #include <asm/ppc-pci.h>
 #include <asm/mpic.h>
+#include <asm/fsl_hcalls.h>
 #include "fsl_msi.h"
 #include "fsl_pci.h"
@@ -148,14 +150,49 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 {
+        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
+        struct device_node *np;
+        phandle phandle = 0;
        int rc, hwirq = -ENOMEM;
        unsigned int virq;
        struct msi_desc *entry;
        struct msi_msg msg;
        struct fsl_msi *msi_data;
+        /*
+         * If the PCI node has an fsl,msi property, then we need to use it
+         * to find the specific MSI.
+         */
+        np = of_parse_phandle(hose->dn, "fsl,msi", 0);
+        if (np) {
+                if (of_device_is_compatible(np, "fsl,mpic-msi") ||
+                    of_device_is_compatible(np, "fsl,vmpic-msi"))
+                        phandle = np->phandle;
+                else {
+                        dev_err(&pdev->dev,
+                                "node %s has an invalid fsl,msi phandle %u\n",
+                                hose->dn->full_name, np->phandle);
+                        return -EINVAL;
+                }
+        }
        list_for_each_entry(entry, &pdev->msi_list, list) {
+                /*
+                 * Loop over all the MSI devices until we find one that has an
+                 * available interrupt.
+                 */
                list_for_each_entry(msi_data, &msi_head, list) {
+                        /*
+                         * If the PCI node has an fsl,msi property, then we
+                         * restrict our search to the corresponding MSI node.
+                         * The simplest way is to skip over MSI nodes with the
+                         * wrong phandle. Under the Freescale hypervisor, this
+                         * has the additional benefit of skipping over MSI
+                         * nodes that are not mapped in the PAMU.
+                         */
+                        if (phandle && (phandle != msi_data->phandle))
+                                continue;
                        hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
                        if (hwirq >= 0)
                                break;
@@ -163,16 +200,14 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                if (hwirq < 0) {
                        rc = hwirq;
-                        pr_debug("%s: fail allocating msi interrupt\n",
+                        dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
-                                        __func__);
                        goto out_free;
                }
                virq = irq_create_mapping(msi_data->irqhost, hwirq);
                if (virq == NO_IRQ) {
-                        pr_debug("%s: fail mapping hwirq 0x%x\n",
+                        dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
-                                        __func__, hwirq);
                        msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
                        rc = -ENOSPC;
                        goto out_free;
@@ -201,6 +236,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
        u32 intr_index;
        u32 have_shift = 0;
        struct fsl_msi_cascade_data *cascade_data;
+        unsigned int ret;
        cascade_data = irq_get_handler_data(irq);
        msi_data = cascade_data->msi_data;
@@ -232,6 +268,14 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
        case FSL_PIC_IP_IPIC:
                msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
                break;
+        case FSL_PIC_IP_VMPIC:
+                ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
+                if (ret) {
+                        pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
+                               "irq %u (ret=%u)\n", irq, ret);
+                        msir_value = 0;
+                }
+                break;
        }
        while (msir_value) {
@@ -249,6 +293,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
        switch (msi_data->feature & FSL_PIC_IP_MASK) {
        case FSL_PIC_IP_MPIC:
+        case FSL_PIC_IP_VMPIC:
                chip->irq_eoi(idata);
                break;
        case FSL_PIC_IP_IPIC:
@@ -278,7 +323,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
        }
        if (msi->bitmap.bitmap)
                msi_bitmap_free(&msi->bitmap);
-        iounmap(msi->msi_regs);
+        if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
+                iounmap(msi->msi_regs);
        kfree(msi);
        return 0;
@@ -350,25 +396,37 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
                goto error_out;
        }
-        /* Get the MSI reg base */
+        /*
-        err = of_address_to_resource(dev->dev.of_node, 0, &res);
+         * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
-        if (err) {
+         * property.  Instead, we use hypercalls to access the MSI.
-                dev_err(&dev->dev, "%s resource error!\n",
+         */
+        if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
+                err = of_address_to_resource(dev->dev.of_node, 0, &res);
+                if (err) {
+                        dev_err(&dev->dev, "invalid resource for node %s\n",
                                dev->dev.of_node->full_name);
-                goto error_out;
+                        goto error_out;
-        }
+                }
-        msi->msi_regs = ioremap(res.start, resource_size(&res));
+                msi->msi_regs = ioremap(res.start, resource_size(&res));
-        if (!msi->msi_regs) {
+                if (!msi->msi_regs) {
-                dev_err(&dev->dev, "ioremap problem failed\n");
+                        dev_err(&dev->dev, "could not map node %s\n",
-                goto error_out;
+                                dev->dev.of_node->full_name);
+                        goto error_out;
+                }
+                msi->msiir_offset =
+                        features->msiir_offset + (res.start & 0xfffff);
        }
        msi->feature = features->fsl_pic_ip;
        msi->irqhost->host_data = msi;
-        msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
+        /*
+         * Remember the phandle, so that we can match with any PCI nodes
+         * that have an "fsl,msi" property.
+         */
+        msi->phandle = dev->dev.of_node->phandle;
        rc = fsl_msi_init_allocator(msi);
        if (rc) {
@@ -437,6 +495,11 @@ static const struct fsl_msi_feature ipic_msi_feature = {
        .msiir_offset = 0x38,
 };
+static const struct fsl_msi_feature vmpic_msi_feature = {
+        .fsl_pic_ip = FSL_PIC_IP_VMPIC,
+        .msiir_offset = 0,
+};
 static const struct of_device_id fsl_of_msi_ids[] = {
        {
                .compatible = "fsl,mpic-msi",
@@ -446,6 +509,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
                .compatible = "fsl,ipic-msi",
                .data = (void *)&ipic_msi_feature,
        },
+        {
+                .compatible = "fsl,vmpic-msi",
+                .data = (void *)&vmpic_msi_feature,
+        },
        {}
 };
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 1313abbc5200..f6c646a52541 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -13,15 +13,17 @@
 #ifndef _POWERPC_SYSDEV_FSL_MSI_H
 #define _POWERPC_SYSDEV_FSL_MSI_H
+#include <linux/of.h>
 #include <asm/msi_bitmap.h>
 #define NR_MSI_REG              8
 #define IRQS_PER_MSI_REG        32
 #define NR_MSI_IRQS     (NR_MSI_REG * IRQS_PER_MSI_REG)
-#define FSL_PIC_IP_MASK 0x0000000F
+#define FSL_PIC_IP_MASK   0x0000000F
-#define FSL_PIC_IP_MPIC 0x00000001
+#define FSL_PIC_IP_MPIC   0x00000001
-#define FSL_PIC_IP_IPIC 0x00000002
+#define FSL_PIC_IP_IPIC   0x00000002
+#define FSL_PIC_IP_VMPIC  0x00000003
 struct fsl_msi {
        struct irq_host *irqhost;
@@ -36,6 +38,8 @@ struct fsl_msi {
        struct msi_bitmap bitmap;
        struct list_head list;          /* support multiple MSI banks */
+        phandle phandle;
 };
 #endif /* _POWERPC_SYSDEV_FSL_MSI_H */
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ce547e00473..3b61e8cf3421 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -65,6 +65,30 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose)
 }
 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+#define MAX_PHYS_ADDR_BITS      40
+static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
+static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+        /*
+         * Fixup PCI devices that are able to DMA to above the physical
+         * address width of the SoC such that we can address any internal
+         * SoC address from across PCI if needed
+         */
+        if ((dev->bus == &pci_bus_type) &&
+            dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
+                set_dma_ops(dev, &dma_direct_ops);
+                set_dma_offset(dev, pci64_dma_offset);
+        }
+        *dev->dma_mask = dma_mask;
+        return 0;
+}
 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
        unsigned int index, const struct resource *res,
        resource_size_t offset)
@@ -113,6 +137,8 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
        u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
                        PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
        char *name = hose->dn->full_name;
+        const u64 *reg;
+        int len;
        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
                 (u64)rsrc->start, (u64)resource_size(rsrc));
@@ -205,6 +231,33 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
        /* Setup inbound mem window */
        mem = memblock_end_of_DRAM();
+        /*
+         * The msi-address-64 property, if it exists, indicates the physical
+         * address of the MSIIR register.  Normally, this register is located
+         * inside CCSR, so the ATMU that covers all of CCSR is used. But if
+         * this property exists, then we normally need to create a new ATMU
+         * for it.  For now, however, we cheat.  The only entity that creates
+         * this property is the Freescale hypervisor, and the address is
+         * specified in the partition configuration.  Typically, the address
+         * is located in the page immediately after the end of DDR.  If so, we
+         * can avoid allocating a new ATMU by extending the DDR ATMU by one
+         * page.
+         */
+        reg = of_get_property(hose->dn, "msi-address-64", &len);
+        if (reg && (len == sizeof(u64))) {
+                u64 address = be64_to_cpup(reg);
+                if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
+                        pr_info("%s: extending DDR ATMU to cover MSIIR", name);
+                        mem += PAGE_SIZE;
+                } else {
+                        /* TODO: Create a new ATMU for MSIIR */
+                        pr_warn("%s: msi-address-64 address of %llx is "
+                                "unsupported\n", name, address);
+                }
+        }
        sz = min(mem, paddr_lo);
        mem_log = __ilog2_u64(sz);
@@ -228,6 +281,37 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
                hose->dma_window_base_cur = 0x00000000;
                hose->dma_window_size = (resource_size_t)sz;
+                /*
+                 * if we have >4G of memory setup second PCI inbound window to
+                 * let devices that are 64-bit address capable to work w/o
+                 * SWIOTLB and access the full range of memory
+                 */
+                if (sz != mem) {
+                        mem_log = __ilog2_u64(mem);
+                        /* Size window up if we dont fit in exact power-of-2 */
+                        if ((1ull << mem_log) != mem)
+                                mem_log++;
+                        piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
+                        /* Setup inbound memory window */
+                        out_be32(&pci->piw[win_idx].pitar,  0x00000000);
+                        out_be32(&pci->piw[win_idx].piwbear,
+                                        pci64_dma_offset >> 44);
+                        out_be32(&pci->piw[win_idx].piwbar,
+                                        pci64_dma_offset >> 12);
+                        out_be32(&pci->piw[win_idx].piwar,  piwar);
+                        /*
+                         * install our own dma_set_mask handler to fixup dma_ops
+                         * and dma_offset
+                         */
+                        ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
+                        pr_info("%s: Setup 64-bit PCI DMA window\n", name);
+                }
        } else {
                u64 paddr = 0;
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 22ffccd8bef5..a4c4f4a932d8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
 * - Added Port-Write message handling
 * - Added Machine Check exception handling
 *
- * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
 * Zhang Wei <wei.zhang@freescale.com>
 *
 * Copyright 2005 MontaVista Software, Inc.
@@ -28,240 +28,33 @@
 #include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
-#include <linux/rio.h>
-#include <linux/rio_drv.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
-#include <linux/kfifo.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
 #include <asm/machdep.h>
-#include <asm/uaccess.h>
-#undef DEBUG_PW /* Port-Write debugging */
+#include "fsl_rio.h"
-/* RapidIO definition irq, which read from OF-tree */
+#undef DEBUG_PW /* Port-Write debugging */
-#define IRQ_RIO_BELL(m)         (((struct rio_priv *)(m->priv))->bellirq)
-#define IRQ_RIO_TX(m)           (((struct rio_priv *)(m->priv))->txirq)
-#define IRQ_RIO_RX(m)           (((struct rio_priv *)(m->priv))->rxirq)
-#define IRQ_RIO_PW(m)           (((struct rio_priv *)(m->priv))->pwirq)
-#define IPWSR_CLEAR             0x98
-#define OMSR_CLEAR              0x1cb3
-#define IMSR_CLEAR              0x491
-#define IDSR_CLEAR              0x91
-#define ODSR_CLEAR              0x1c00
-#define LTLEECSR_ENABLE_ALL     0xFFC000FC
-#define ESCSR_CLEAR             0x07120204
-#define IECSR_CLEAR             0x80000000
 #define RIO_PORT1_EDCSR         0x0640
 #define RIO_PORT2_EDCSR         0x0680
 #define RIO_PORT1_IECSR         0x10130
 #define RIO_PORT2_IECSR         0x101B0
-#define RIO_IM0SR               0x13064
-#define RIO_IM1SR               0x13164
-#define RIO_OM0SR               0x13004
-#define RIO_OM1SR               0x13104
-#define RIO_ATMU_REGS_OFFSET    0x10c00
-#define RIO_P_MSG_REGS_OFFSET   0x11000
-#define RIO_S_MSG_REGS_OFFSET   0x13000
 #define RIO_GCCSR               0x13c
 #define RIO_ESCSR               0x158
+#define ESCSR_CLEAR             0x07120204
 #define RIO_PORT2_ESCSR         0x178
 #define RIO_CCSR                0x15c
-#define RIO_LTLEDCSR            0x0608
 #define RIO_LTLEDCSR_IER        0x80000000
 #define RIO_LTLEDCSR_PRT        0x01000000
-#define RIO_LTLEECSR            0x060c
+#define IECSR_CLEAR             0x80000000
-#define RIO_EPWISR              0x10010
 #define RIO_ISR_AACR            0x10120
 #define RIO_ISR_AACR_AA         0x1     /* Accept All ID */
-#define RIO_MAINT_WIN_SIZE      0x400000
-#define RIO_DBELL_WIN_SIZE      0x1000
-#define RIO_MSG_OMR_MUI         0x00000002
-#define RIO_MSG_OSR_TE          0x00000080
-#define RIO_MSG_OSR_QOI         0x00000020
-#define RIO_MSG_OSR_QFI         0x00000010
-#define RIO_MSG_OSR_MUB         0x00000004
-#define RIO_MSG_OSR_EOMI        0x00000002
-#define RIO_MSG_OSR_QEI         0x00000001
-#define RIO_MSG_IMR_MI          0x00000002
-#define RIO_MSG_ISR_TE          0x00000080
-#define RIO_MSG_ISR_QFI         0x00000010
-#define RIO_MSG_ISR_DIQI        0x00000001
-#define RIO_IPWMR_SEN           0x00100000
-#define RIO_IPWMR_QFIE          0x00000100
-#define RIO_IPWMR_EIE           0x00000020
-#define RIO_IPWMR_CQ            0x00000002
-#define RIO_IPWMR_PWE           0x00000001
-#define RIO_IPWSR_QF            0x00100000
-#define RIO_IPWSR_TE            0x00000080
-#define RIO_IPWSR_QFI           0x00000010
-#define RIO_IPWSR_PWD           0x00000008
-#define RIO_IPWSR_PWB           0x00000004
-/* EPWISR Error match value */
-#define RIO_EPWISR_PINT1        0x80000000
-#define RIO_EPWISR_PINT2        0x40000000
-#define RIO_EPWISR_MU           0x00000002
-#define RIO_EPWISR_PW           0x00000001
-#define RIO_MSG_DESC_SIZE       32
-#define RIO_MSG_BUFFER_SIZE     4096
-#define RIO_MIN_TX_RING_SIZE    2
-#define RIO_MAX_TX_RING_SIZE    2048
-#define RIO_MIN_RX_RING_SIZE    2
-#define RIO_MAX_RX_RING_SIZE    2048
-#define DOORBELL_DMR_DI         0x00000002
-#define DOORBELL_DSR_TE         0x00000080
-#define DOORBELL_DSR_QFI        0x00000010
-#define DOORBELL_DSR_DIQI       0x00000001
-#define DOORBELL_TID_OFFSET     0x02
-#define DOORBELL_SID_OFFSET     0x04
-#define DOORBELL_INFO_OFFSET    0x06
-#define DOORBELL_MESSAGE_SIZE   0x08
-#define DBELL_SID(x)            (*(u16 *)(x + DOORBELL_SID_OFFSET))
-#define DBELL_TID(x)            (*(u16 *)(x + DOORBELL_TID_OFFSET))
-#define DBELL_INF(x)            (*(u16 *)(x + DOORBELL_INFO_OFFSET))
-struct rio_atmu_regs {
-        u32 rowtar;
-        u32 rowtear;
-        u32 rowbar;
-        u32 pad2;
-        u32 rowar;
-        u32 pad3[3];
-};
-struct rio_msg_regs {
-        u32 omr;        /* 0xD_3000 - Outbound message 0 mode register */
-        u32 osr;        /* 0xD_3004 - Outbound message 0 status register */
-        u32 pad1;
-        u32 odqdpar;    /* 0xD_300C - Outbound message 0 descriptor queue
-                           dequeue pointer address register */
-        u32 pad2;
-        u32 osar;       /* 0xD_3014 - Outbound message 0 source address
-                           register */
-        u32 odpr;       /* 0xD_3018 - Outbound message 0 destination port
-                           register */
-        u32 odatr;      /* 0xD_301C - Outbound message 0 destination attributes
-                           Register*/
-        u32 odcr;       /* 0xD_3020 - Outbound message 0 double-word count
-                           register */
-        u32 pad3;
-        u32 odqepar;    /* 0xD_3028 - Outbound message 0 descriptor queue
-                           enqueue pointer address register */
-        u32 pad4[13];
-        u32 imr;        /* 0xD_3060 - Inbound message 0 mode register */
-        u32 isr;        /* 0xD_3064 - Inbound message 0 status register */
-        u32 pad5;
-        u32 ifqdpar;    /* 0xD_306C - Inbound message 0 frame queue dequeue
-                           pointer address register*/
-        u32 pad6;
-        u32 ifqepar;    /* 0xD_3074 - Inbound message 0 frame queue enqueue
-                           pointer address register */
-        u32 pad7[226];
-        u32 odmr;       /* 0xD_3400 - Outbound doorbell mode register */
-        u32 odsr;       /* 0xD_3404 - Outbound doorbell status register */
-        u32 res0[4];
-        u32 oddpr;      /* 0xD_3418 - Outbound doorbell destination port
-                           register */
-        u32 oddatr;     /* 0xD_341c - Outbound doorbell destination attributes
-                           register */
-        u32 res1[3];
-        u32 odretcr;    /* 0xD_342C - Outbound doorbell retry error threshold
-                           configuration register */
-        u32 res2[12];
-        u32 dmr;        /* 0xD_3460 - Inbound doorbell mode register */
-        u32 dsr;        /* 0xD_3464 - Inbound doorbell status register */
-        u32 pad8;
-        u32 dqdpar;     /* 0xD_346C - Inbound doorbell queue dequeue Pointer
-                           address register */
-        u32 pad9;
-        u32 dqepar;     /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
-                           address register */
-        u32 pad10[26];
-        u32 pwmr;       /* 0xD_34E0 - Inbound port-write mode register */
-        u32 pwsr;       /* 0xD_34E4 - Inbound port-write status register */
-        u32 epwqbar;    /* 0xD_34E8 - Extended Port-Write Queue Base Address
-                           register */
-        u32 pwqbar;     /* 0xD_34EC - Inbound port-write queue base address
-                           register */
-};
-struct rio_tx_desc {
-        u32 res1;
-        u32 saddr;
-        u32 dport;
-        u32 dattr;
-        u32 res2;
-        u32 res3;
-        u32 dwcnt;
-        u32 res4;
-};
-struct rio_dbell_ring {
-        void *virt;
-        dma_addr_t phys;
-};
-struct rio_msg_tx_ring {
-        void *virt;
-        dma_addr_t phys;
-        void *virt_buffer[RIO_MAX_TX_RING_SIZE];
-        dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
-        int tx_slot;
-        int size;
-        void *dev_id;
-};
-struct rio_msg_rx_ring {
-        void *virt;
-        dma_addr_t phys;
-        void *virt_buffer[RIO_MAX_RX_RING_SIZE];
-        int rx_slot;
-        int size;
-        void *dev_id;
-};
-struct rio_port_write_msg {
-        void *virt;
-        dma_addr_t phys;
-        u32 msg_count;
-        u32 err_count;
-        u32 discard_count;
-};
-struct rio_priv {
-        struct device *dev;
-        void __iomem *regs_win;
-        struct rio_atmu_regs __iomem *atmu_regs;
-        struct rio_atmu_regs __iomem *maint_atmu_regs;
-        struct rio_atmu_regs __iomem *dbell_atmu_regs;
-        void __iomem *dbell_win;
-        void __iomem *maint_win;
-        struct rio_msg_regs __iomem *msg_regs;
-        struct rio_dbell_ring dbell_ring;
-        struct rio_msg_tx_ring msg_tx_ring;
-        struct rio_msg_rx_ring msg_rx_ring;
-        struct rio_port_write_msg port_write_msg;
-        int bellirq;
-        int txirq;
-        int rxirq;
-        int pwirq;
-        struct work_struct pw_work;
-        struct kfifo pw_fifo;
-        spinlock_t pw_fifo_lock;
-};
 #define __fsl_read_rio_config(x, addr, err, op)         \
        __asm__ __volatile__(                           \
@@ -279,7 +72,12 @@ struct rio_priv {
                : "=r" (err), "=r" (x)                  \
                : "b" (addr), "i" (-EFAULT), "0" (err))
-static void __iomem *rio_regs_win;
+void __iomem *rio_regs_win;
+void __iomem *rmu_regs_win;
+resource_size_t rio_law_start;
+struct fsl_rio_dbell *dbell;
+struct fsl_rio_pw *pw;
 #ifdef CONFIG_E500
 int fsl_rio_mcheck_exception(struct pt_regs *regs)
@@ -311,42 +109,6 @@ EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
 #endif
 /**
- * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
- * @mport: RapidIO master port info
- * @index: ID of RapidIO interface
- * @destid: Destination ID of target device
- * @data: 16-bit info field of RapidIO doorbell message
- *
- * Sends a MPC85xx doorbell message. Returns %0 on success or
- * %-EINVAL on failure.
- */
-static int fsl_rio_doorbell_send(struct rio_mport *mport,
-                                int index, u16 destid, u16 data)
-{
-        struct rio_priv *priv = mport->priv;
-        pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
-                 index, destid, data);
-        switch (mport->phy_type) {
-        case RIO_PHY_PARALLEL:
-                out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
-                out_be16(priv->dbell_win, data);
-                break;
-        case RIO_PHY_SERIAL:
-                /* In the serial version silicons, such as MPC8548, MPC8641,
-                 * below operations is must be.
-                 */
-                out_be32(&priv->msg_regs->odmr, 0x00000000);
-                out_be32(&priv->msg_regs->odretcr, 0x00000004);
-                out_be32(&priv->msg_regs->oddpr, destid << 16);
-                out_be32(&priv->msg_regs->oddatr, data);
-                out_be32(&priv->msg_regs->odmr, 0x00000001);
-                break;
-        }
-        return 0;
-}
-/**
 * fsl_local_config_read - Generate a MPC85xx local config space read
 * @mport: RapidIO master port info
 * @index: ID of RapdiIO interface
@@ -384,8 +146,8 @@ static int fsl_local_config_write(struct rio_mport *mport,
 {
        struct rio_priv *priv = mport->priv;
        pr_debug
-            ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
+                ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
-             index, offset, data);
+                index, offset, data);
        out_be32(priv->regs_win + offset, data);
        return 0;
@@ -413,8 +175,9 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
        u32 rval, err = 0;
        pr_debug
-            ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
+                ("fsl_rio_config_read:"
-             index, destid, hopcount, offset, len);
+                " index %d destid %d hopcount %d offset %8.8x len %d\n",
+                index, destid, hopcount, offset, len);
        /* 16MB maintenance window possible */
        /* allow only aligned access to maintenance registers */
@@ -423,7 +186,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
        out_be32(&priv->maint_atmu_regs->rowtar,
                 (destid << 22) | (hopcount << 12) | (offset >> 12));
-        out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
+        out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
        data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
        switch (len) {
@@ -470,8 +233,9 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
        struct rio_priv *priv = mport->priv;
        u8 *data;
        pr_debug
-            ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
+                ("fsl_rio_config_write:"
-             index, destid, hopcount, offset, len, val);
+                " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
+                index, destid, hopcount, offset, len, val);
        /* 16MB maintenance windows possible */
        /* allow only aligned access to maintenance registers */
@@ -480,7 +244,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
        out_be32(&priv->maint_atmu_regs->rowtar,
                 (destid << 22) | (hopcount << 12) | (offset >> 12));
-        out_be32(&priv->maint_atmu_regs->rowtear,  (destid >> 10));
+        out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
        data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
        switch (len) {
@@ -500,590 +264,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
        return 0;
 }
-/**
+void fsl_rio_port_error_handler(int offset)
- * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
- * @mport: Master port with outbound message queue
- * @rdev: Target of outbound message
- * @mbox: Outbound mailbox
- * @buffer: Message to add to outbound queue
- * @len: Length of message
- *
- * Adds the @buffer message to the MPC85xx outbound message queue. Returns
- * %0 on success or %-EINVAL on failure.
- */
-static int
-fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
-                        void *buffer, size_t len)
-{
-        struct rio_priv *priv = mport->priv;
-        u32 omr;
-        struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
-                                        + priv->msg_tx_ring.tx_slot;
-        int ret = 0;
-        pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
-                 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
-        if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
-                ret = -EINVAL;
-                goto out;
-        }
-        /* Copy and clear rest of buffer */
-        memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
-                        len);
-        if (len < (RIO_MAX_MSG_SIZE - 4))
-                memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
-                                + len, 0, RIO_MAX_MSG_SIZE - len);
-        switch (mport->phy_type) {
-        case RIO_PHY_PARALLEL:
-                /* Set mbox field for message */
-                desc->dport = mbox & 0x3;
-                /* Enable EOMI interrupt, set priority, and set destid */
-                desc->dattr = 0x28000000 | (rdev->destid << 2);
-                break;
-        case RIO_PHY_SERIAL:
-                /* Set mbox field for message, and set destid */
-                desc->dport = (rdev->destid << 16) | (mbox & 0x3);
-                /* Enable EOMI interrupt and priority */
-                desc->dattr = 0x28000000;
-                break;
-        }
-        /* Set transfer size aligned to next power of 2 (in double words) */
-        desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
-        /* Set snooping and source buffer address */
-        desc->saddr = 0x00000004
-                | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
-        /* Increment enqueue pointer */
-        omr = in_be32(&priv->msg_regs->omr);
-        out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
-        /* Go to next descriptor */
-        if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
-                priv->msg_tx_ring.tx_slot = 0;
-      out:
-        return ret;
-}
-/**
- * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
- * @irq: Linux interrupt number
- * @dev_instance: Pointer to interrupt-specific data
- *
- * Handles outbound message interrupts. Executes a register outbound
- * mailbox event handler and acks the interrupt occurrence.
- */
-static irqreturn_t
-fsl_rio_tx_handler(int irq, void *dev_instance)
-{
-        int osr;
-        struct rio_mport *port = (struct rio_mport *)dev_instance;
-        struct rio_priv *priv = port->priv;
-        osr = in_be32(&priv->msg_regs->osr);
-        if (osr & RIO_MSG_OSR_TE) {
-                pr_info("RIO: outbound message transmission error\n");
-                out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
-                goto out;
-        }
-        if (osr & RIO_MSG_OSR_QOI) {
-                pr_info("RIO: outbound message queue overflow\n");
-                out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
-                goto out;
-        }
-        if (osr & RIO_MSG_OSR_EOMI) {
-                u32 dqp = in_be32(&priv->msg_regs->odqdpar);
-                int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
-                port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
-                                slot);
-                /* Ack the end-of-message interrupt */
-                out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
-        }
-      out:
-        return IRQ_HANDLED;
-}
-/**
- * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
- * @mport: Master port implementing the outbound message unit
- * @dev_id: Device specific pointer to pass on event
- * @mbox: Mailbox to open
- * @entries: Number of entries in the outbound mailbox ring
- *
- * Initializes buffer ring, request the outbound message interrupt,
- * and enables the outbound message unit. Returns %0 on success and
- * %-EINVAL or %-ENOMEM on failure.
- */
-static int
-fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
-{
-        int i, j, rc = 0;
-        struct rio_priv *priv = mport->priv;
-        if ((entries < RIO_MIN_TX_RING_SIZE) ||
-            (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
-                rc = -EINVAL;
-                goto out;
-        }
-        /* Initialize shadow copy ring */
-        priv->msg_tx_ring.dev_id = dev_id;
-        priv->msg_tx_ring.size = entries;
-        for (i = 0; i < priv->msg_tx_ring.size; i++) {
-                priv->msg_tx_ring.virt_buffer[i] =
-                        dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
-                                &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
-                if (!priv->msg_tx_ring.virt_buffer[i]) {
-                        rc = -ENOMEM;
-                        for (j = 0; j < priv->msg_tx_ring.size; j++)
-                                if (priv->msg_tx_ring.virt_buffer[j])
-                                        dma_free_coherent(priv->dev,
-                                                        RIO_MSG_BUFFER_SIZE,
-                                                        priv->msg_tx_ring.
-                                                        virt_buffer[j],
-                                                        priv->msg_tx_ring.
-                                                        phys_buffer[j]);
-                        goto out;
-                }
-        }
-        /* Initialize outbound message descriptor ring */
-        priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
-                                priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
-                                &priv->msg_tx_ring.phys, GFP_KERNEL);
-        if (!priv->msg_tx_ring.virt) {
-                rc = -ENOMEM;
-                goto out_dma;
-        }
-        memset(priv->msg_tx_ring.virt, 0,
-                        priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
-        priv->msg_tx_ring.tx_slot = 0;
-        /* Point dequeue/enqueue pointers at first entry in ring */
-        out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
-        out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
-        /* Configure for snooping */
-        out_be32(&priv->msg_regs->osar, 0x00000004);
-        /* Clear interrupt status */
-        out_be32(&priv->msg_regs->osr, 0x000000b3);
-        /* Hook up outbound message handler */
-        rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
-                         "msg_tx", (void *)mport);
-        if (rc < 0)
-                goto out_irq;
-        /*
-         * Configure outbound message unit
-         *      Snooping
-         *      Interrupts (all enabled, except QEIE)
-         *      Chaining mode
-         *      Disable
-         */
-        out_be32(&priv->msg_regs->omr, 0x00100220);
-        /* Set number of entries */
-        out_be32(&priv->msg_regs->omr,
-                 in_be32(&priv->msg_regs->omr) |
-                 ((get_bitmask_order(entries) - 2) << 12));
-        /* Now enable the unit */
-        out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
-      out:
-        return rc;
-      out_irq:
-        dma_free_coherent(priv->dev,
-                          priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
-                          priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
-      out_dma:
-        for (i = 0; i < priv->msg_tx_ring.size; i++)
-                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
-                                  priv->msg_tx_ring.virt_buffer[i],
-                                  priv->msg_tx_ring.phys_buffer[i]);
-        return rc;
-}
-/**
- * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
- * @mport: Master port implementing the outbound message unit
- * @mbox: Mailbox to close
- *
- * Disables the outbound message unit, free all buffers, and
- * frees the outbound message interrupt.
- */
-static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
-{
-        struct rio_priv *priv = mport->priv;
-        /* Disable inbound message unit */
-        out_be32(&priv->msg_regs->omr, 0);
-        /* Free ring */
-        dma_free_coherent(priv->dev,
-                          priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
-                          priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
-        /* Free interrupt */
-        free_irq(IRQ_RIO_TX(mport), (void *)mport);
-}
-/**
- * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
- * @irq: Linux interrupt number
- * @dev_instance: Pointer to interrupt-specific data
- *
- * Handles inbound message interrupts. Executes a registered inbound
- * mailbox event handler and acks the interrupt occurrence.
- */
-static irqreturn_t
-fsl_rio_rx_handler(int irq, void *dev_instance)
-{
-        int isr;
-        struct rio_mport *port = (struct rio_mport *)dev_instance;
-        struct rio_priv *priv = port->priv;
-        isr = in_be32(&priv->msg_regs->isr);
-        if (isr & RIO_MSG_ISR_TE) {
-                pr_info("RIO: inbound message reception error\n");
-                out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
-                goto out;
-        }
-        /* XXX Need to check/dispatch until queue empty */
-        if (isr & RIO_MSG_ISR_DIQI) {
-                /*
-                 * We implement *only* mailbox 0, but can receive messages
-                 * for any mailbox/letter to that mailbox destination. So,
-                 * make the callback with an unknown/invalid mailbox number
-                 * argument.
-                 */
-                port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
-                /* Ack the queueing interrupt */
-                out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
-        }
-      out:
-        return IRQ_HANDLED;
-}
-/**
- * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
- * @mport: Master port implementing the inbound message unit
- * @dev_id: Device specific pointer to pass on event
- * @mbox: Mailbox to open
- * @entries: Number of entries in the inbound mailbox ring
- *
- * Initializes buffer ring, request the inbound message interrupt,
- * and enables the inbound message unit. Returns %0 on success
- * and %-EINVAL or %-ENOMEM on failure.
- */
-static int
-fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
-{
-        int i, rc = 0;
-        struct rio_priv *priv = mport->priv;
-        if ((entries < RIO_MIN_RX_RING_SIZE) ||
-            (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
-                rc = -EINVAL;
-                goto out;
-        }
-        /* Initialize client buffer ring */
-        priv->msg_rx_ring.dev_id = dev_id;
-        priv->msg_rx_ring.size = entries;
-        priv->msg_rx_ring.rx_slot = 0;
-        for (i = 0; i < priv->msg_rx_ring.size; i++)
-                priv->msg_rx_ring.virt_buffer[i] = NULL;
-        /* Initialize inbound message ring */
-        priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
-                                priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
-                                &priv->msg_rx_ring.phys, GFP_KERNEL);
-        if (!priv->msg_rx_ring.virt) {
-                rc = -ENOMEM;
-                goto out;
-        }
-        /* Point dequeue/enqueue pointers at first entry in ring */
-        out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
-        out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
-        /* Clear interrupt status */
-        out_be32(&priv->msg_regs->isr, 0x00000091);
-        /* Hook up inbound message handler */
-        rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
-                         "msg_rx", (void *)mport);
-        if (rc < 0) {
-                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
-                                  priv->msg_tx_ring.virt_buffer[i],
-                                  priv->msg_tx_ring.phys_buffer[i]);
-                goto out;
-        }
-        /*
-         * Configure inbound message unit:
-         *      Snooping
-         *      4KB max message size
-         *      Unmask all interrupt sources
-         *      Disable
-         */
-        out_be32(&priv->msg_regs->imr, 0x001b0060);
-        /* Set number of queue entries */
-        setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
-        /* Now enable the unit */
-        setbits32(&priv->msg_regs->imr, 0x1);
-      out:
-        return rc;
-}
-/**
- * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
- * @mport: Master port implementing the inbound message unit
- * @mbox: Mailbox to close
- *
- * Disables the inbound message unit, free all buffers, and
- * frees the inbound message interrupt.
- */
-static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
-{
-        struct rio_priv *priv = mport->priv;
-        /* Disable inbound message unit */
-        out_be32(&priv->msg_regs->imr, 0);
-        /* Free ring */
-        dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
-                          priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
-        /* Free interrupt */
-        free_irq(IRQ_RIO_RX(mport), (void *)mport);
-}
-/**
- * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
- * @mport: Master port implementing the inbound message unit
- * @mbox: Inbound mailbox number
- * @buf: Buffer to add to inbound queue
- *
- * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
- * %0 on success or %-EINVAL on failure.
- */
-static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
-{
-        int rc = 0;
-        struct rio_priv *priv = mport->priv;
-        pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
-                 priv->msg_rx_ring.rx_slot);
-        if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
-                printk(KERN_ERR
-                       "RIO: error adding inbound buffer %d, buffer exists\n",
-                       priv->msg_rx_ring.rx_slot);
-                rc = -EINVAL;
-                goto out;
-        }
-        priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
-        if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
-                priv->msg_rx_ring.rx_slot = 0;
-      out:
-        return rc;
-}
-/**
- * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
- * @mport: Master port implementing the inbound message unit
- * @mbox: Inbound mailbox number
- *
- * Gets the next available inbound message from the inbound message queue.
- * A pointer to the message is returned on success or NULL on failure.
- */
-static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
-{
-        struct rio_priv *priv = mport->priv;
-        u32 phys_buf, virt_buf;
-        void *buf = NULL;
-        int buf_idx;
-        phys_buf = in_be32(&priv->msg_regs->ifqdpar);
-        /* If no more messages, then bail out */
-        if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
-                goto out2;
-        virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
-                                                - priv->msg_rx_ring.phys);
-        buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
-        buf = priv->msg_rx_ring.virt_buffer[buf_idx];
-        if (!buf) {
-                printk(KERN_ERR
-                       "RIO: inbound message copy failed, no buffers\n");
-                goto out1;
-        }
-        /* Copy max message size, caller is expected to allocate that big */
-        memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
-        /* Clear the available buffer */
-        priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
-      out1:
-        setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
-      out2:
-        return buf;
-}
-/**
- * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
- * @irq: Linux interrupt number
- * @dev_instance: Pointer to interrupt-specific data
- *
- * Handles doorbell interrupts. Parses a list of registered
- * doorbell event handlers and executes a matching event handler.
- */
-static irqreturn_t
-fsl_rio_dbell_handler(int irq, void *dev_instance)
-{
-        int dsr;
-        struct rio_mport *port = (struct rio_mport *)dev_instance;
-        struct rio_priv *priv = port->priv;
-        dsr = in_be32(&priv->msg_regs->dsr);
-        if (dsr & DOORBELL_DSR_TE) {
-                pr_info("RIO: doorbell reception error\n");
-                out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
-                goto out;
-        }
-        if (dsr & DOORBELL_DSR_QFI) {
-                pr_info("RIO: doorbell queue full\n");
-                out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
-        }
-        /* XXX Need to check/dispatch until queue empty */
-        if (dsr & DOORBELL_DSR_DIQI) {
-                u32 dmsg =
-                    (u32) priv->dbell_ring.virt +
-                    (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
-                struct rio_dbell *dbell;
-                int found = 0;
-                pr_debug
-                    ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
-                     DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
-                list_for_each_entry(dbell, &port->dbells, node) {
-                        if ((dbell->res->start <= DBELL_INF(dmsg)) &&
-                            (dbell->res->end >= DBELL_INF(dmsg))) {
-                                found = 1;
-                                break;
-                        }
-                }
-                if (found) {
-                        dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
-                                    DBELL_INF(dmsg));
-                } else {
-                        pr_debug
-                            ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
-                             DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
-                }
-                setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
-                out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
-        }
-      out:
-        return IRQ_HANDLED;
-}
-/**
- * fsl_rio_doorbell_init - MPC85xx doorbell interface init
- * @mport: Master port implementing the inbound doorbell unit
- *
- * Initializes doorbell unit hardware and inbound DMA buffer
- * ring. Called from fsl_rio_setup(). Returns %0 on success
- * or %-ENOMEM on failure.
- */
-static int fsl_rio_doorbell_init(struct rio_mport *mport)
-{
-        struct rio_priv *priv = mport->priv;
-        int rc = 0;
-        /* Map outbound doorbell window immediately after maintenance window */
-        priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
-                            RIO_DBELL_WIN_SIZE);
-        if (!priv->dbell_win) {
-                printk(KERN_ERR
-                       "RIO: unable to map outbound doorbell window\n");
-                rc = -ENOMEM;
-                goto out;
-        }
-        /* Initialize inbound doorbells */
-        priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
-                    DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
-        if (!priv->dbell_ring.virt) {
-                printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
-                rc = -ENOMEM;
-                iounmap(priv->dbell_win);
-                goto out;
-        }
-        /* Point dequeue/enqueue pointers at first entry in ring */
-        out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
-        out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
-        /* Clear interrupt status */
-        out_be32(&priv->msg_regs->dsr, 0x00000091);
-        /* Hook up doorbell handler */
-        rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
-                         "dbell_rx", (void *)mport);
-        if (rc < 0) {
-                iounmap(priv->dbell_win);
-                dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
-                                  priv->dbell_ring.virt, priv->dbell_ring.phys);
-                printk(KERN_ERR
-                       "MPC85xx RIO: unable to request inbound doorbell irq");
-                goto out;
-        }
-        /* Configure doorbells for snooping, 512 entries, and enable */
-        out_be32(&priv->msg_regs->dmr, 0x00108161);
-      out:
-        return rc;
-}
-static void port_error_handler(struct rio_mport *port, int offset)
 {
        /*XXX: Error recovery is not implemented, we just clear errors */
        out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
@@ -1098,263 +279,6 @@ static void port_error_handler(struct rio_mport *port, int offset)
                out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
        }
 }
-static void msg_unit_error_handler(struct rio_mport *port)
-{
-        struct rio_priv *priv = port->priv;
-        /*XXX: Error recovery is not implemented, we just clear errors */
-        out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
-        out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
-        out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
-        out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
-        out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
-        out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
-        out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
-        out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
-}
-/**
- * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
- * @irq: Linux interrupt number
- * @dev_instance: Pointer to interrupt-specific data
- *
- * Handles port write interrupts. Parses a list of registered
- * port write event handlers and executes a matching event handler.
- */
-static irqreturn_t
-fsl_rio_port_write_handler(int irq, void *dev_instance)
-{
-        u32 ipwmr, ipwsr;
-        struct rio_mport *port = (struct rio_mport *)dev_instance;
-        struct rio_priv *priv = port->priv;
-        u32 epwisr, tmp;
-        epwisr = in_be32(priv->regs_win + RIO_EPWISR);
-        if (!(epwisr & RIO_EPWISR_PW))
-                goto pw_done;
-        ipwmr = in_be32(&priv->msg_regs->pwmr);
-        ipwsr = in_be32(&priv->msg_regs->pwsr);
-#ifdef DEBUG_PW
-        pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
-        if (ipwsr & RIO_IPWSR_QF)
-                pr_debug(" QF");
-        if (ipwsr & RIO_IPWSR_TE)
-                pr_debug(" TE");
-        if (ipwsr & RIO_IPWSR_QFI)
-                pr_debug(" QFI");
-        if (ipwsr & RIO_IPWSR_PWD)
-                pr_debug(" PWD");
-        if (ipwsr & RIO_IPWSR_PWB)
-                pr_debug(" PWB");
-        pr_debug(" )\n");
-#endif
-        /* Schedule deferred processing if PW was received */
-        if (ipwsr & RIO_IPWSR_QFI) {
-                /* Save PW message (if there is room in FIFO),
-                 * otherwise discard it.
-                 */
-                if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
-                        priv->port_write_msg.msg_count++;
-                        kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
-                                 RIO_PW_MSG_SIZE);
-                } else {
-                        priv->port_write_msg.discard_count++;
-                        pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
-                                 priv->port_write_msg.discard_count);
-                }
-                /* Clear interrupt and issue Clear Queue command. This allows
-                 * another port-write to be received.
-                 */
-                out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
-                out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
-                schedule_work(&priv->pw_work);
-        }
-        if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
-                priv->port_write_msg.err_count++;
-                pr_debug("RIO: Port-Write Transaction Err (%d)\n",
-                         priv->port_write_msg.err_count);
-                /* Clear Transaction Error: port-write controller should be
-                 * disabled when clearing this error
-                 */
-                out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
-                out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
-                out_be32(&priv->msg_regs->pwmr, ipwmr);
-        }
-        if (ipwsr & RIO_IPWSR_PWD) {
-                priv->port_write_msg.discard_count++;
-                pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
-                         priv->port_write_msg.discard_count);
-                out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
-        }
-pw_done:
-        if (epwisr & RIO_EPWISR_PINT1) {
-                tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
-                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
-                port_error_handler(port, 0);
-        }
-        if (epwisr & RIO_EPWISR_PINT2) {
-                tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
-                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
-                port_error_handler(port, 1);
-        }
-        if (epwisr & RIO_EPWISR_MU) {
-                tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
-                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
-                msg_unit_error_handler(port);
-        }
-        return IRQ_HANDLED;
-}
-static void fsl_pw_dpc(struct work_struct *work)
-{
-        struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
-        unsigned long flags;
-        u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
-        /*
-         * Process port-write messages
-         */
-        spin_lock_irqsave(&priv->pw_fifo_lock, flags);
-        while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
-                         RIO_PW_MSG_SIZE)) {
-                /* Process one message */
-                spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
-#ifdef DEBUG_PW
-                {
-                u32 i;
-                pr_debug("%s : Port-Write Message:", __func__);
-                for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
-                        if ((i%4) == 0)
-                                pr_debug("\n0x%02x: 0x%08x", i*4,
-                                         msg_buffer[i]);
-                        else
-                                pr_debug(" 0x%08x", msg_buffer[i]);
-                }
-                pr_debug("\n");
-                }
-#endif
-                /* Pass the port-write message to RIO core for processing */
-                rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
-                spin_lock_irqsave(&priv->pw_fifo_lock, flags);
-        }
-        spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
-}
-/**
- * fsl_rio_pw_enable - enable/disable port-write interface init
- * @mport: Master port implementing the port write unit
- * @enable:    1=enable; 0=disable port-write message handling
- */
-static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
-{
-        struct rio_priv *priv = mport->priv;
-        u32 rval;
-        rval = in_be32(&priv->msg_regs->pwmr);
-        if (enable)
-                rval |= RIO_IPWMR_PWE;
-        else
-                rval &= ~RIO_IPWMR_PWE;
-        out_be32(&priv->msg_regs->pwmr, rval);
-        return 0;
-}
-/**
- * fsl_rio_port_write_init - MPC85xx port write interface init
- * @mport: Master port implementing the port write unit
- *
- * Initializes port write unit hardware and DMA buffer
- * ring. Called from fsl_rio_setup(). Returns %0 on success
- * or %-ENOMEM on failure.
- */
-static int fsl_rio_port_write_init(struct rio_mport *mport)
-{
-        struct rio_priv *priv = mport->priv;
-        int rc = 0;
-        /* Following configurations require a disabled port write controller */
-        out_be32(&priv->msg_regs->pwmr,
-                 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
-        /* Initialize port write */
-        priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
-                                        RIO_PW_MSG_SIZE,
-                                        &priv->port_write_msg.phys, GFP_KERNEL);
-        if (!priv->port_write_msg.virt) {
-                pr_err("RIO: unable allocate port write queue\n");
-                return -ENOMEM;
-        }
-        priv->port_write_msg.err_count = 0;
-        priv->port_write_msg.discard_count = 0;
-        /* Point dequeue/enqueue pointers at first entry */
-        out_be32(&priv->msg_regs->epwqbar, 0);
-        out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
-        pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
-                 in_be32(&priv->msg_regs->epwqbar),
-                 in_be32(&priv->msg_regs->pwqbar));
-        /* Clear interrupt status IPWSR */
-        out_be32(&priv->msg_regs->pwsr,
-                 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
-        /* Configure port write contoller for snooping enable all reporting,
-           clear queue full */
-        out_be32(&priv->msg_regs->pwmr,
-                 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
-        /* Hook up port-write handler */
-        rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
-                        IRQF_SHARED, "port-write", (void *)mport);
-        if (rc < 0) {
-                pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
-                goto err_out;
-        }
-        /* Enable Error Interrupt */
-        out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
-        INIT_WORK(&priv->pw_work, fsl_pw_dpc);
-        spin_lock_init(&priv->pw_fifo_lock);
-        if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
-                pr_err("FIFO allocation failed\n");
-                rc = -ENOMEM;
-                goto err_out_irq;
-        }
-        pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
-                 in_be32(&priv->msg_regs->pwmr),
-                 in_be32(&priv->msg_regs->pwsr));
-        return rc;
-err_out_irq:
-        free_irq(IRQ_RIO_PW(mport), (void *)mport);
-err_out:
-        dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
-                          priv->port_write_msg.virt,
-                          priv->port_write_msg.phys);
-        return rc;
-}
 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
 {
        const char *str;
@@ -1411,16 +335,21 @@ int fsl_rio_setup(struct platform_device *dev)
        struct rio_mport *port;
        struct rio_priv *priv;
        int rc = 0;
-        const u32 *dt_range, *cell;
+        const u32 *dt_range, *cell, *port_index;
-        struct resource regs;
+        u32 active_ports = 0;
+        struct resource regs, rmu_regs;
+        struct device_node *np, *rmu_node;
        int rlen;
        u32 ccsr;
-        u64 law_start, law_size;
+        u64 range_start, range_size;
        int paw, aw, sw;
+        u32 i;
+        static int tmp;
+        struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
        if (!dev->dev.of_node) {
                dev_err(&dev->dev, "Device OF-Node is NULL");
-                return -EFAULT;
+                return -ENODEV;
        }
        rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
@@ -1429,37 +358,17 @@ int fsl_rio_setup(struct platform_device *dev)
                                dev->dev.of_node->full_name);
                return -EFAULT;
        }
-        dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
+        dev_info(&dev->dev, "Of-device full name %s\n",
+                        dev->dev.of_node->full_name);
        dev_info(&dev->dev, "Regs: %pR\n", &regs);
-        dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
+        rio_regs_win = ioremap(regs.start, resource_size(&regs));
-        if (!dt_range) {
+        if (!rio_regs_win) {
-                dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
+                dev_err(&dev->dev, "Unable to map rio register window\n");
-                                dev->dev.of_node->full_name);
+                rc = -ENOMEM;
-                return -EFAULT;
+                goto err_rio_regs;
        }
-        /* Get node address wide */
-        cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
-        if (cell)
-                aw = *cell;
-        else
-                aw = of_n_addr_cells(dev->dev.of_node);
-        /* Get node size wide */
-        cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
-        if (cell)
-                sw = *cell;
-        else
-                sw = of_n_size_cells(dev->dev.of_node);
-        /* Get parent address wide wide */
-        paw = of_n_addr_cells(dev->dev.of_node);
-        law_start = of_read_number(dt_range + aw, paw);
-        law_size = of_read_number(dt_range + aw + paw, sw);
-        dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
-                        law_start, law_size);
        ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
        if (!ops) {
                rc = -ENOMEM;
@@ -1479,143 +388,257 @@ int fsl_rio_setup(struct platform_device *dev)
        ops->add_inb_buffer = fsl_add_inb_buffer;
        ops->get_inb_message = fsl_get_inb_message;
-        port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+        rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
-        if (!port) {
+        if (!rmu_node)
+                goto err_rmu;
+        rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
+        if (rc) {
+                dev_err(&dev->dev, "Can't get %s property 'reg'\n",
+                                rmu_node->full_name);
+                goto err_rmu;
+        }
+        rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
+        if (!rmu_regs_win) {
+                dev_err(&dev->dev, "Unable to map rmu register window\n");
                rc = -ENOMEM;
-                goto err_port;
+                goto err_rmu;
+        }
+        for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
+                rmu_np[tmp] = np;
+                tmp++;
        }
-        port->index = 0;
-        priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
+        /*set up doobell node*/
-        if (!priv) {
+        np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
-                printk(KERN_ERR "Can't alloc memory for 'priv'\n");
+        if (!np) {
+                rc = -ENODEV;
+                goto err_dbell;
+        }
+        dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
+        if (!(dbell)) {
+                dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
                rc = -ENOMEM;
-                goto err_priv;
+                goto err_dbell;
        }
+        dbell->dev = &dev->dev;
+        dbell->bellirq = irq_of_parse_and_map(np, 1);
+        dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
-        INIT_LIST_HEAD(&port->dbells);
+        aw = of_n_addr_cells(np);
-        port->iores.start = law_start;
+        dt_range = of_get_property(np, "reg", &rlen);
-        port->iores.end = law_start + law_size - 1;
+        if (!dt_range) {
-        port->iores.flags = IORESOURCE_MEM;
+                pr_err("%s: unable to find 'reg' property\n",
-        port->iores.name = "rio_io_win";
+                        np->full_name);
+                rc = -ENOMEM;
-        if (request_resource(&iomem_resource, &port->iores) < 0) {
+                goto err_pw;
-                dev_err(&dev->dev, "RIO: Error requesting master port region"
-                        " 0x%016llx-0x%016llx\n",
-                        (u64)port->iores.start, (u64)port->iores.end);
-                        rc = -ENOMEM;
-                        goto err_res;
        }
+        range_start = of_read_number(dt_range, aw);
+        dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
+                                (u32)range_start);
-        priv->pwirq   = irq_of_parse_and_map(dev->dev.of_node, 0);
+        /*set up port write node*/
-        priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
+        np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
-        priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
+        if (!np) {
-        priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
+                rc = -ENODEV;
-        dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
+                goto err_pw;
-                 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
+        }
+        pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
-        rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
+        if (!(pw)) {
-        rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
+                dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
-        rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
+                rc = -ENOMEM;
-        strcpy(port->name, "RIO0 mport");
+                goto err_pw;
+        }
-        priv->dev = &dev->dev;
+        pw->dev = &dev->dev;
+        pw->pwirq = irq_of_parse_and_map(np, 0);
-        port->ops = ops;
+        dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
-        port->priv = priv;
+        aw = of_n_addr_cells(np);
-        port->phys_efptr = 0x100;
+        dt_range = of_get_property(np, "reg", &rlen);
+        if (!dt_range) {
-        priv->regs_win = ioremap(regs.start, resource_size(&regs));
+                pr_err("%s: unable to find 'reg' property\n",
-        rio_regs_win = priv->regs_win;
+                        np->full_name);
+                rc = -ENOMEM;
-        /* Probe the master port phy type */
+                goto err;
-        ccsr = in_be32(priv->regs_win + RIO_CCSR);
+        }
-        port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
+        range_start = of_read_number(dt_range, aw);
-        dev_info(&dev->dev, "RapidIO PHY type: %s\n",
+        pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
-                        (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
-                        ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
+        /*set up ports node*/
-                         "unknown"));
+        for_each_child_of_node(dev->dev.of_node, np) {
-        /* Checking the port training status */
+                port_index = of_get_property(np, "cell-index", NULL);
-        if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
+                if (!port_index) {
-                dev_err(&dev->dev, "Port is not ready. "
+                        dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
-                                   "Try to restart connection...\n");
+                                        np->full_name);
-                switch (port->phy_type) {
+                        continue;
-                case RIO_PHY_SERIAL:
+                }
+                dt_range = of_get_property(np, "ranges", &rlen);
+                if (!dt_range) {
+                        dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
+                                        np->full_name);
+                        continue;
+                }
+                /* Get node address wide */
+                cell = of_get_property(np, "#address-cells", NULL);
+                if (cell)
+                        aw = *cell;
+                else
+                        aw = of_n_addr_cells(np);
+                /* Get node size wide */
+                cell = of_get_property(np, "#size-cells", NULL);
+                if (cell)
+                        sw = *cell;
+                else
+                        sw = of_n_size_cells(np);
+                /* Get parent address wide wide */
+                paw = of_n_addr_cells(np);
+                range_start = of_read_number(dt_range + aw, paw);
+                range_size = of_read_number(dt_range + aw + paw, sw);
+                dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
+                                np->full_name, range_start, range_size);
+                port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+                if (!port)
+                        continue;
+                i = *port_index - 1;
+                port->index = (unsigned char)i;
+                priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
+                if (!priv) {
+                        dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
+                        kfree(port);
+                        continue;
+                }
+                INIT_LIST_HEAD(&port->dbells);
+                port->iores.start = range_start;
+                port->iores.end = port->iores.start + range_size - 1;
+                port->iores.flags = IORESOURCE_MEM;
+                port->iores.name = "rio_io_win";
+                if (request_resource(&iomem_resource, &port->iores) < 0) {
+                        dev_err(&dev->dev, "RIO: Error requesting master port region"
+                                " 0x%016llx-0x%016llx\n",
+                                (u64)port->iores.start, (u64)port->iores.end);
+                                kfree(priv);
+                                kfree(port);
+                                continue;
+                }
+                sprintf(port->name, "RIO mport %d", i);
+                priv->dev = &dev->dev;
+                port->ops = ops;
+                port->priv = priv;
+                port->phys_efptr = 0x100;
+                priv->regs_win = rio_regs_win;
+                /* Probe the master port phy type */
+                ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
+                port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
+                if (port->phy_type == RIO_PHY_PARALLEL) {
+                        dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
+                        release_resource(&port->iores);
+                        kfree(priv);
+                        kfree(port);
+                        continue;
+                }
+                dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
+                /* Checking the port training status */
+                if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
+                        dev_err(&dev->dev, "Port %d is not ready. "
+                        "Try to restart connection...\n", i);
                        /* Disable ports */
-                        out_be32(priv->regs_win + RIO_CCSR, 0);
+                        out_be32(priv->regs_win
+                                + RIO_CCSR + i*0x20, 0);
                        /* Set 1x lane */
-                        setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
+                        setbits32(priv->regs_win
+                                + RIO_CCSR + i*0x20, 0x02000000);
                        /* Enable ports */
-                        setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
+                        setbits32(priv->regs_win
-                        break;
+                                + RIO_CCSR + i*0x20, 0x00600000);
-                case RIO_PHY_PARALLEL:
+                        msleep(100);
-                        /* Disable ports */
+                        if (in_be32((priv->regs_win
-                        out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
+                                        + RIO_ESCSR + i*0x20)) & 1) {
-                        /* Enable ports */
+                                dev_err(&dev->dev,
-                        out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
+                                        "Port %d restart failed.\n", i);
-                        break;
+                                release_resource(&port->iores);
-                }
+                                kfree(priv);
-                msleep(100);
+                                kfree(port);
-                if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
+                                continue;
-                        dev_err(&dev->dev, "Port restart failed.\n");
+                        }
-                        rc = -ENOLINK;
+                        dev_info(&dev->dev, "Port %d restart success!\n", i);
-                        goto err;
                }
-                dev_info(&dev->dev, "Port restart success!\n");
+                fsl_rio_info(&dev->dev, ccsr);
-        }
-        fsl_rio_info(&dev->dev, ccsr);
-        port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
+                port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
                                        & RIO_PEF_CTLS) >> 4;
-        dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
+                dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
-                        port->sys_size ? 65536 : 256);
+                                port->sys_size ? 65536 : 256);
+                if (rio_register_mport(port)) {
+                        release_resource(&port->iores);
+                        kfree(priv);
+                        kfree(port);
+                        continue;
+                }
+                if (port->host_deviceid >= 0)
+                        out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
+                                RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
+                else
+                        out_be32(priv->regs_win + RIO_GCCSR,
+                                RIO_PORT_GEN_MASTER);
+                priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
+                        + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
+                        RIO_ATMU_REGS_PORT2_OFFSET));
-        if (rio_register_mport(port))
+                priv->maint_atmu_regs = priv->atmu_regs + 1;
+                /* Set to receive any dist ID for serial RapidIO controller. */
+                if (port->phy_type == RIO_PHY_SERIAL)
+                        out_be32((priv->regs_win
+                                + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
+                /* Configure maintenance transaction window */
+                out_be32(&priv->maint_atmu_regs->rowbar,
+                        port->iores.start >> 12);
+                out_be32(&priv->maint_atmu_regs->rowar,
+                         0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
+                priv->maint_win = ioremap(port->iores.start,
+                                RIO_MAINT_WIN_SIZE);
+                rio_law_start = range_start;
+                fsl_rio_setup_rmu(port, rmu_np[i]);
+                dbell->mport[i] = port;
+                active_ports++;
+        }
+        if (!active_ports) {
+                rc = -ENOLINK;
                goto err;
+        }
-        if (port->host_deviceid >= 0)
+        fsl_rio_doorbell_init(dbell);
-                out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
+        fsl_rio_port_write_init(pw);
-                        RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
-        else
-                out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
-        priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
-                                        + RIO_ATMU_REGS_OFFSET);
-        priv->maint_atmu_regs = priv->atmu_regs + 1;
-        priv->dbell_atmu_regs = priv->atmu_regs + 2;
-        priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
-                                ((port->phy_type == RIO_PHY_SERIAL) ?
-                                RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
-        /* Set to receive any dist ID for serial RapidIO controller. */
-        if (port->phy_type == RIO_PHY_SERIAL)
-                out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
-        /* Configure maintenance transaction window */
-        out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
-        out_be32(&priv->maint_atmu_regs->rowar,
-                 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
-        priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
-        /* Configure outbound doorbell window */
-        out_be32(&priv->dbell_atmu_regs->rowbar,
-                        (law_start + RIO_MAINT_WIN_SIZE) >> 12);
-        out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);    /* 4k */
-        fsl_rio_doorbell_init(port);
-        fsl_rio_port_write_init(port);
        return 0;
 err:
-        iounmap(priv->regs_win);
+        kfree(pw);
-        release_resource(&port->iores);
+err_pw:
-err_res:
+        kfree(dbell);
-        kfree(priv);
+err_dbell:
-err_priv:
+        iounmap(rmu_regs_win);
-        kfree(port);
+err_rmu:
-err_port:
        kfree(ops);
 err_ops:
+        iounmap(rio_regs_win);
+err_rio_regs:
        return rc;
 }
@@ -1631,7 +654,7 @@ static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
        {
-                .compatible = "fsl,rapidio-delta",
+                .compatible = "fsl,srio",
        },
        {},
 };
diff --git a/arch/powerpc/sysdev/fsl_rio.h b/arch/powerpc/sysdev/fsl_rio.h
new file mode 100644
index 000000000000..ae8e27405a0d
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rio.h
@@ -0,0 +1,135 @@
+/*
+ * Freescale MPC85xx/MPC86xx RapidIO support
+ *
+ * Copyright 2009 Sysgo AG
+ * Thomas Moll <thomas.moll@sysgo.com>
+ * - fixed maintenance access routines, check for aligned access
+ *
+ * Copyright 2009 Integrated Device Technology, Inc.
+ * Alex Bounine <alexandre.bounine@idt.com>
+ * - Added Port-Write message handling
+ * - Added Machine Check exception handling
+ *
+ * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
+ * Zhang Wei <wei.zhang@freescale.com>
+ * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
+ * Liu Gang <Gang.Liu@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc.
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __FSL_RIO_H
+#define __FSL_RIO_H
+#include <linux/rio.h>
+#include <linux/rio_drv.h>
+#include <linux/kfifo.h>
+#define RIO_REGS_WIN(mport)     (((struct rio_priv *)(mport->priv))->regs_win)
+#define RIO_MAINT_WIN_SIZE      0x400000
+#define RIO_LTLEDCSR            0x0608
+#define DOORBELL_ROWAR_EN       0x80000000
+#define DOORBELL_ROWAR_TFLOWLV  0x08000000 /* highest priority level */
+#define DOORBELL_ROWAR_PCI      0x02000000 /* PCI window */
+#define DOORBELL_ROWAR_NREAD    0x00040000 /* NREAD */
+#define DOORBELL_ROWAR_MAINTRD  0x00070000  /* maintenance read */
+#define DOORBELL_ROWAR_RES      0x00002000 /* wrtpy: reserverd */
+#define DOORBELL_ROWAR_MAINTWD  0x00007000
+#define DOORBELL_ROWAR_SIZE     0x0000000b /* window size is 4k */
+#define RIO_ATMU_REGS_PORT1_OFFSET      0x10c00
+#define RIO_ATMU_REGS_PORT2_OFFSET      0x10e00
+#define RIO_S_DBELL_REGS_OFFSET 0x13400
+#define RIO_S_PW_REGS_OFFSET    0x134e0
+#define RIO_ATMU_REGS_DBELL_OFFSET      0x10C40
+#define MAX_MSG_UNIT_NUM        2
+#define MAX_PORT_NUM            4
+struct rio_atmu_regs {
+         u32 rowtar;
+         u32 rowtear;
+         u32 rowbar;
+         u32 pad1;
+         u32 rowar;
+         u32 pad2[3];
+};
+struct rio_dbell_ring {
+        void *virt;
+        dma_addr_t phys;
+};
+struct rio_port_write_msg {
+         void *virt;
+         dma_addr_t phys;
+         u32 msg_count;
+         u32 err_count;
+         u32 discard_count;
+};
+struct fsl_rio_dbell {
+        struct rio_mport *mport[MAX_PORT_NUM];
+        struct device *dev;
+        struct rio_dbell_regs __iomem *dbell_regs;
+        struct rio_dbell_ring dbell_ring;
+        int bellirq;
+};
+struct fsl_rio_pw {
+        struct device *dev;
+        struct rio_pw_regs __iomem *pw_regs;
+        struct rio_port_write_msg port_write_msg;
+        int pwirq;
+        struct work_struct pw_work;
+        struct kfifo pw_fifo;
+        spinlock_t pw_fifo_lock;
+};
+struct rio_priv {
+        struct device *dev;
+        void __iomem *regs_win;
+        struct rio_atmu_regs __iomem *atmu_regs;
+        struct rio_atmu_regs __iomem *maint_atmu_regs;
+        void __iomem *maint_win;
+        void *rmm_handle; /* RapidIO message manager(unit) Handle */
+};
+extern void __iomem *rio_regs_win;
+extern void __iomem *rmu_regs_win;
+extern resource_size_t rio_law_start;
+extern struct fsl_rio_dbell *dbell;
+extern struct fsl_rio_pw *pw;
+extern int fsl_rio_setup_rmu(struct rio_mport *mport,
+        struct device_node *node);
+extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
+extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
+extern void fsl_rio_port_error_handler(int offset);
+extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
+extern int fsl_rio_doorbell_send(struct rio_mport *mport,
+                                int index, u16 destid, u16 data);
+extern int fsl_add_outb_message(struct rio_mport *mport,
+        struct rio_dev *rdev,
+        int mbox, void *buffer, size_t len);
+extern int fsl_open_outb_mbox(struct rio_mport *mport,
+        void *dev_id, int mbox, int entries);
+extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
+extern int fsl_open_inb_mbox(struct rio_mport *mport,
+        void *dev_id, int mbox, int entries);
+extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
+extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
+extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);
+#endif
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
new file mode 100644
index 000000000000..15485789e9db
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -0,0 +1,1104 @@
+/*
+ * Freescale MPC85xx/MPC86xx RapidIO RMU support
+ *
+ * Copyright 2009 Sysgo AG
+ * Thomas Moll <thomas.moll@sysgo.com>
+ * - fixed maintenance access routines, check for aligned access
+ *
+ * Copyright 2009 Integrated Device Technology, Inc.
+ * Alex Bounine <alexandre.bounine@idt.com>
+ * - Added Port-Write message handling
+ * - Added Machine Check exception handling
+ *
+ * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
+ * Zhang Wei <wei.zhang@freescale.com>
+ * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
+ * Liu Gang <Gang.Liu@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc.
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include "fsl_rio.h"
+#define GET_RMM_HANDLE(mport) \
+                (((struct rio_priv *)(mport->priv))->rmm_handle)
+/* RapidIO definition irq, which read from OF-tree */
+#define IRQ_RIO_PW(m)           (((struct fsl_rio_pw *)(m))->pwirq)
+#define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
+#define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
+#define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
+#define RIO_MIN_TX_RING_SIZE    2
+#define RIO_MAX_TX_RING_SIZE    2048
+#define RIO_MIN_RX_RING_SIZE    2
+#define RIO_MAX_RX_RING_SIZE    2048
+#define RIO_IPWMR_SEN           0x00100000
+#define RIO_IPWMR_QFIE          0x00000100
+#define RIO_IPWMR_EIE           0x00000020
+#define RIO_IPWMR_CQ            0x00000002
+#define RIO_IPWMR_PWE           0x00000001
+#define RIO_IPWSR_QF            0x00100000
+#define RIO_IPWSR_TE            0x00000080
+#define RIO_IPWSR_QFI           0x00000010
+#define RIO_IPWSR_PWD           0x00000008
+#define RIO_IPWSR_PWB           0x00000004
+#define RIO_EPWISR              0x10010
+/* EPWISR Error match value */
+#define RIO_EPWISR_PINT1        0x80000000
+#define RIO_EPWISR_PINT2        0x40000000
+#define RIO_EPWISR_MU           0x00000002
+#define RIO_EPWISR_PW           0x00000001
+#define IPWSR_CLEAR             0x98
+#define OMSR_CLEAR              0x1cb3
+#define IMSR_CLEAR              0x491
+#define IDSR_CLEAR              0x91
+#define ODSR_CLEAR              0x1c00
+#define LTLEECSR_ENABLE_ALL     0xFFC000FC
+#define RIO_LTLEECSR            0x060c
+#define RIO_IM0SR               0x64
+#define RIO_IM1SR               0x164
+#define RIO_OM0SR               0x4
+#define RIO_OM1SR               0x104
+#define RIO_DBELL_WIN_SIZE      0x1000
+#define RIO_MSG_OMR_MUI         0x00000002
+#define RIO_MSG_OSR_TE          0x00000080
+#define RIO_MSG_OSR_QOI         0x00000020
+#define RIO_MSG_OSR_QFI         0x00000010
+#define RIO_MSG_OSR_MUB         0x00000004
+#define RIO_MSG_OSR_EOMI        0x00000002
+#define RIO_MSG_OSR_QEI         0x00000001
+#define RIO_MSG_IMR_MI          0x00000002
+#define RIO_MSG_ISR_TE          0x00000080
+#define RIO_MSG_ISR_QFI         0x00000010
+#define RIO_MSG_ISR_DIQI        0x00000001
+#define RIO_MSG_DESC_SIZE       32
+#define RIO_MSG_BUFFER_SIZE     4096
+#define DOORBELL_DMR_DI         0x00000002
+#define DOORBELL_DSR_TE         0x00000080
+#define DOORBELL_DSR_QFI        0x00000010
+#define DOORBELL_DSR_DIQI       0x00000001
+#define DOORBELL_TID_OFFSET     0x02
+#define DOORBELL_SID_OFFSET     0x04
+#define DOORBELL_INFO_OFFSET    0x06
+#define DOORBELL_MESSAGE_SIZE   0x08
+#define DBELL_SID(x)            (*(u16 *)(x + DOORBELL_SID_OFFSET))
+#define DBELL_TID(x)            (*(u16 *)(x + DOORBELL_TID_OFFSET))
+#define DBELL_INF(x)            (*(u16 *)(x + DOORBELL_INFO_OFFSET))
+struct rio_msg_regs {
+        u32 omr;
+        u32 osr;
+        u32 pad1;
+        u32 odqdpar;
+        u32 pad2;
+        u32 osar;
+        u32 odpr;
+        u32 odatr;
+        u32 odcr;
+        u32 pad3;
+        u32 odqepar;
+        u32 pad4[13];
+        u32 imr;
+        u32 isr;
+        u32 pad5;
+        u32 ifqdpar;
+        u32 pad6;
+        u32 ifqepar;
+};
+struct rio_dbell_regs {
+        u32 odmr;
+        u32 odsr;
+        u32 pad1[4];
+        u32 oddpr;
+        u32 oddatr;
+        u32 pad2[3];
+        u32 odretcr;
+        u32 pad3[12];
+        u32 dmr;
+        u32 dsr;
+        u32 pad4;
+        u32 dqdpar;
+        u32 pad5;
+        u32 dqepar;
+};
+struct rio_pw_regs {
+        u32 pwmr;
+        u32 pwsr;
+        u32 epwqbar;
+        u32 pwqbar;
+};
+struct rio_tx_desc {
+        u32 pad1;
+        u32 saddr;
+        u32 dport;
+        u32 dattr;
+        u32 pad2;
+        u32 pad3;
+        u32 dwcnt;
+        u32 pad4;
+};
+struct rio_msg_tx_ring {
+        void *virt;
+        dma_addr_t phys;
+        void *virt_buffer[RIO_MAX_TX_RING_SIZE];
+        dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
+        int tx_slot;
+        int size;
+        void *dev_id;
+};
+struct rio_msg_rx_ring {
+        void *virt;
+        dma_addr_t phys;
+        void *virt_buffer[RIO_MAX_RX_RING_SIZE];
+        int rx_slot;
+        int size;
+        void *dev_id;
+};
+struct fsl_rmu {
+        struct rio_msg_regs __iomem *msg_regs;
+        struct rio_msg_tx_ring msg_tx_ring;
+        struct rio_msg_rx_ring msg_rx_ring;
+        int txirq;
+        int rxirq;
+};
+/**
+ * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
+ * @irq: Linux interrupt number
+ * @dev_instance: Pointer to interrupt-specific data
+ *
+ * Handles outbound message interrupts. Executes a register outbound
+ * mailbox event handler and acks the interrupt occurrence.
+ */
+static irqreturn_t
+fsl_rio_tx_handler(int irq, void *dev_instance)
+{
+        int osr;
+        struct rio_mport *port = (struct rio_mport *)dev_instance;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
+        osr = in_be32(&rmu->msg_regs->osr);
+        if (osr & RIO_MSG_OSR_TE) {
+                pr_info("RIO: outbound message transmission error\n");
+                out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
+                goto out;
+        }
+        if (osr & RIO_MSG_OSR_QOI) {
+                pr_info("RIO: outbound message queue overflow\n");
+                out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
+                goto out;
+        }
+        if (osr & RIO_MSG_OSR_EOMI) {
+                u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
+                int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
+                if (port->outb_msg[0].mcback != NULL) {
+                        port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id,
+                                        -1,
+                                        slot);
+                }
+                /* Ack the end-of-message interrupt */
+                out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
+        }
+out:
+        return IRQ_HANDLED;
+}
+/**
+ * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
+ * @irq: Linux interrupt number
+ * @dev_instance: Pointer to interrupt-specific data
+ *
+ * Handles inbound message interrupts. Executes a registered inbound
+ * mailbox event handler and acks the interrupt occurrence.
+ */
+static irqreturn_t
+fsl_rio_rx_handler(int irq, void *dev_instance)
+{
+        int isr;
+        struct rio_mport *port = (struct rio_mport *)dev_instance;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
+        isr = in_be32(&rmu->msg_regs->isr);
+        if (isr & RIO_MSG_ISR_TE) {
+                pr_info("RIO: inbound message reception error\n");
+                out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
+                goto out;
+        }
+        /* XXX Need to check/dispatch until queue empty */
+        if (isr & RIO_MSG_ISR_DIQI) {
+                /*
+                * Can receive messages for any mailbox/letter to that
+                * mailbox destination. So, make the callback with an
+                * unknown/invalid mailbox number argument.
+                */
+                if (port->inb_msg[0].mcback != NULL)
+                        port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id,
+                                -1,
+                                -1);
+                /* Ack the queueing interrupt */
+                out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
+        }
+out:
+        return IRQ_HANDLED;
+}
+/**
+ * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
+ * @irq: Linux interrupt number
+ * @dev_instance: Pointer to interrupt-specific data
+ *
+ * Handles doorbell interrupts. Parses a list of registered
+ * doorbell event handlers and executes a matching event handler.
+ */
+static irqreturn_t
+fsl_rio_dbell_handler(int irq, void *dev_instance)
+{
+        int dsr;
+        struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance;
+        int i;
+        dsr = in_be32(&fsl_dbell->dbell_regs->dsr);
+        if (dsr & DOORBELL_DSR_TE) {
+                pr_info("RIO: doorbell reception error\n");
+                out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE);
+                goto out;
+        }
+        if (dsr & DOORBELL_DSR_QFI) {
+                pr_info("RIO: doorbell queue full\n");
+                out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI);
+        }
+        /* XXX Need to check/dispatch until queue empty */
+        if (dsr & DOORBELL_DSR_DIQI) {
+                u32 dmsg =
+                        (u32) fsl_dbell->dbell_ring.virt +
+                        (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
+                struct rio_dbell *dbell;
+                int found = 0;
+                pr_debug
+                        ("RIO: processing doorbell,"
+                        " sid %2.2x tid %2.2x info %4.4x\n",
+                        DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
+                for (i = 0; i < MAX_PORT_NUM; i++) {
+                        if (fsl_dbell->mport[i]) {
+                                list_for_each_entry(dbell,
+                                        &fsl_dbell->mport[i]->dbells, node) {
+                                        if ((dbell->res->start
+                                                <= DBELL_INF(dmsg))
+                                                && (dbell->res->end
+                                                >= DBELL_INF(dmsg))) {
+                                                found = 1;
+                                                break;
+                                        }
+                                }
+                                if (found && dbell->dinb) {
+                                        dbell->dinb(fsl_dbell->mport[i],
+                                                dbell->dev_id, DBELL_SID(dmsg),
+                                                DBELL_TID(dmsg),
+                                                DBELL_INF(dmsg));
+                                        break;
+                                }
+                        }
+                }
+                if (!found) {
+                        pr_debug
+                                ("RIO: spurious doorbell,"
+                                " sid %2.2x tid %2.2x info %4.4x\n",
+                                DBELL_SID(dmsg), DBELL_TID(dmsg),
+                                DBELL_INF(dmsg));
+                }
+                setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
+                out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
+        }
+out:
+        return IRQ_HANDLED;
+}
+void msg_unit_error_handler(void)
+{
+        /*XXX: Error recovery is not implemented, we just clear errors */
+        out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+        out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR);
+        out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR);
+        out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR);
+        out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR);
+        out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR);
+        out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR);
+        out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR);
+}
+/**
+ * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
+ * @irq: Linux interrupt number
+ * @dev_instance: Pointer to interrupt-specific data
+ *
+ * Handles port write interrupts. Parses a list of registered
+ * port write event handlers and executes a matching event handler.
+ */
+static irqreturn_t
+fsl_rio_port_write_handler(int irq, void *dev_instance)
+{
+        u32 ipwmr, ipwsr;
+        struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance;
+        u32 epwisr, tmp;
+        epwisr = in_be32(rio_regs_win + RIO_EPWISR);
+        if (!(epwisr & RIO_EPWISR_PW))
+                goto pw_done;
+        ipwmr = in_be32(&pw->pw_regs->pwmr);
+        ipwsr = in_be32(&pw->pw_regs->pwsr);
+#ifdef DEBUG_PW
+        pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
+        if (ipwsr & RIO_IPWSR_QF)
+                pr_debug(" QF");
+        if (ipwsr & RIO_IPWSR_TE)
+                pr_debug(" TE");
+        if (ipwsr & RIO_IPWSR_QFI)
+                pr_debug(" QFI");
+        if (ipwsr & RIO_IPWSR_PWD)
+                pr_debug(" PWD");
+        if (ipwsr & RIO_IPWSR_PWB)
+                pr_debug(" PWB");
+        pr_debug(" )\n");
+#endif
+        /* Schedule deferred processing if PW was received */
+        if (ipwsr & RIO_IPWSR_QFI) {
+                /* Save PW message (if there is room in FIFO),
+                 * otherwise discard it.
+                 */
+                if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) {
+                        pw->port_write_msg.msg_count++;
+                        kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt,
+                                 RIO_PW_MSG_SIZE);
+                } else {
+                        pw->port_write_msg.discard_count++;
+                        pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
+                                 pw->port_write_msg.discard_count);
+                }
+                /* Clear interrupt and issue Clear Queue command. This allows
+                 * another port-write to be received.
+                 */
+                out_be32(&pw->pw_regs->pwsr,    RIO_IPWSR_QFI);
+                out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
+                schedule_work(&pw->pw_work);
+        }
+        if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
+                pw->port_write_msg.err_count++;
+                pr_debug("RIO: Port-Write Transaction Err (%d)\n",
+                         pw->port_write_msg.err_count);
+                /* Clear Transaction Error: port-write controller should be
+                 * disabled when clearing this error
+                 */
+                out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
+                out_be32(&pw->pw_regs->pwsr,    RIO_IPWSR_TE);
+                out_be32(&pw->pw_regs->pwmr, ipwmr);
+        }
+        if (ipwsr & RIO_IPWSR_PWD) {
+                pw->port_write_msg.discard_count++;
+                pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
+                         pw->port_write_msg.discard_count);
+                out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD);
+        }
+pw_done:
+        if (epwisr & RIO_EPWISR_PINT1) {
+                tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
+                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+                fsl_rio_port_error_handler(0);
+        }
+        if (epwisr & RIO_EPWISR_PINT2) {
+                tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
+                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+                fsl_rio_port_error_handler(1);
+        }
+        if (epwisr & RIO_EPWISR_MU) {
+                tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
+                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+                msg_unit_error_handler();
+        }
+        return IRQ_HANDLED;
+}
+static void fsl_pw_dpc(struct work_struct *work)
+{
+        struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work);
+        u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
+        /*
+         * Process port-write messages
+         */
+        while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)msg_buffer,
+                         RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) {
+                /* Process one message */
+#ifdef DEBUG_PW
+                {
+                u32 i;
+                pr_debug("%s : Port-Write Message:", __func__);
+                for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
+                        if ((i%4) == 0)
+                                pr_debug("\n0x%02x: 0x%08x", i*4,
+                                         msg_buffer[i]);
+                        else
+                                pr_debug(" 0x%08x", msg_buffer[i]);
+                }
+                pr_debug("\n");
+                }
+#endif
+                /* Pass the port-write message to RIO core for processing */
+                rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
+        }
+}
+/**
+ * fsl_rio_pw_enable - enable/disable port-write interface init
+ * @mport: Master port implementing the port write unit
+ * @enable:    1=enable; 0=disable port-write message handling
+ */
+int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
+{
+        u32 rval;
+        rval = in_be32(&pw->pw_regs->pwmr);
+        if (enable)
+                rval |= RIO_IPWMR_PWE;
+        else
+                rval &= ~RIO_IPWMR_PWE;
+        out_be32(&pw->pw_regs->pwmr, rval);
+        return 0;
+}
+/**
+ * fsl_rio_port_write_init - MPC85xx port write interface init
+ * @mport: Master port implementing the port write unit
+ *
+ * Initializes port write unit hardware and DMA buffer
+ * ring. Called from fsl_rio_setup(). Returns %0 on success
+ * or %-ENOMEM on failure.
+ */
+int fsl_rio_port_write_init(struct fsl_rio_pw *pw)
+{
+        int rc = 0;
+        /* Following configurations require a disabled port write controller */
+        out_be32(&pw->pw_regs->pwmr,
+                 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE);
+        /* Initialize port write */
+        pw->port_write_msg.virt = dma_alloc_coherent(pw->dev,
+                                        RIO_PW_MSG_SIZE,
+                                        &pw->port_write_msg.phys, GFP_KERNEL);
+        if (!pw->port_write_msg.virt) {
+                pr_err("RIO: unable allocate port write queue\n");
+                return -ENOMEM;
+        }
+        pw->port_write_msg.err_count = 0;
+        pw->port_write_msg.discard_count = 0;
+        /* Point dequeue/enqueue pointers at first entry */
+        out_be32(&pw->pw_regs->epwqbar, 0);
+        out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys);
+        pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
+                 in_be32(&pw->pw_regs->epwqbar),
+                 in_be32(&pw->pw_regs->pwqbar));
+        /* Clear interrupt status IPWSR */
+        out_be32(&pw->pw_regs->pwsr,
+                 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
+        /* Configure port write contoller for snooping enable all reporting,
+           clear queue full */
+        out_be32(&pw->pw_regs->pwmr,
+                 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
+        /* Hook up port-write handler */
+        rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler,
+                        IRQF_SHARED, "port-write", (void *)pw);
+        if (rc < 0) {
+                pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
+                goto err_out;
+        }
+        /* Enable Error Interrupt */
+        out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
+        INIT_WORK(&pw->pw_work, fsl_pw_dpc);
+        spin_lock_init(&pw->pw_fifo_lock);
+        if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
+                pr_err("FIFO allocation failed\n");
+                rc = -ENOMEM;
+                goto err_out_irq;
+        }
+        pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
+                 in_be32(&pw->pw_regs->pwmr),
+                 in_be32(&pw->pw_regs->pwsr));
+        return rc;
+err_out_irq:
+        free_irq(IRQ_RIO_PW(pw), (void *)pw);
+err_out:
+        dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE,
+                pw->port_write_msg.virt,
+                pw->port_write_msg.phys);
+        return rc;
+}
+/**
+ * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
+ * @mport: RapidIO master port info
+ * @index: ID of RapidIO interface
+ * @destid: Destination ID of target device
+ * @data: 16-bit info field of RapidIO doorbell message
+ *
+ * Sends a MPC85xx doorbell message. Returns %0 on success or
+ * %-EINVAL on failure.
+ */
+int fsl_rio_doorbell_send(struct rio_mport *mport,
+                                int index, u16 destid, u16 data)
+{
+        pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
+                 index, destid, data);
+        /* In the serial version silicons, such as MPC8548, MPC8641,
+         * below operations is must be.
+         */
+        out_be32(&dbell->dbell_regs->odmr, 0x00000000);
+        out_be32(&dbell->dbell_regs->odretcr, 0x00000004);
+        out_be32(&dbell->dbell_regs->oddpr, destid << 16);
+        out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
+        out_be32(&dbell->dbell_regs->odmr, 0x00000001);
+        return 0;
+}
+/**
+ * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
+ * @mport: Master port with outbound message queue
+ * @rdev: Target of outbound message
+ * @mbox: Outbound mailbox
+ * @buffer: Message to add to outbound queue
+ * @len: Length of message
+ *
+ * Adds the @buffer message to the MPC85xx outbound message queue. Returns
+ * %0 on success or %-EINVAL on failure.
+ */
+int
+fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
+                        void *buffer, size_t len)
+{
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        u32 omr;
+        struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
+                                        + rmu->msg_tx_ring.tx_slot;
+        int ret = 0;
+        pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
+                 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
+        if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
+                ret = -EINVAL;
+                goto out;
+        }
+        /* Copy and clear rest of buffer */
+        memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
+                        len);
+        if (len < (RIO_MAX_MSG_SIZE - 4))
+                memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
+                                + len, 0, RIO_MAX_MSG_SIZE - len);
+        /* Set mbox field for message, and set destid */
+        desc->dport = (rdev->destid << 16) | (mbox & 0x3);
+        /* Enable EOMI interrupt and priority */
+        desc->dattr = 0x28000000 | ((mport->index) << 20);
+        /* Set transfer size aligned to next power of 2 (in double words) */
+        desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
+        /* Set snooping and source buffer address */
+        desc->saddr = 0x00000004
+                | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
+        /* Increment enqueue pointer */
+        omr = in_be32(&rmu->msg_regs->omr);
+        out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
+        /* Go to next descriptor */
+        if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
+                rmu->msg_tx_ring.tx_slot = 0;
+out:
+        return ret;
+}
+/**
+ * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
+ * @mport: Master port implementing the outbound message unit
+ * @dev_id: Device specific pointer to pass on event
+ * @mbox: Mailbox to open
+ * @entries: Number of entries in the outbound mailbox ring
+ *
+ * Initializes buffer ring, request the outbound message interrupt,
+ * and enables the outbound message unit. Returns %0 on success and
+ * %-EINVAL or %-ENOMEM on failure.
+ */
+int
+fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
+{
+        int i, j, rc = 0;
+        struct rio_priv *priv = mport->priv;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        if ((entries < RIO_MIN_TX_RING_SIZE) ||
+                (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
+                rc = -EINVAL;
+                goto out;
+        }
+        /* Initialize shadow copy ring */
+        rmu->msg_tx_ring.dev_id = dev_id;
+        rmu->msg_tx_ring.size = entries;
+        for (i = 0; i < rmu->msg_tx_ring.size; i++) {
+                rmu->msg_tx_ring.virt_buffer[i] =
+                        dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
+                                &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
+                if (!rmu->msg_tx_ring.virt_buffer[i]) {
+                        rc = -ENOMEM;
+                        for (j = 0; j < rmu->msg_tx_ring.size; j++)
+                                if (rmu->msg_tx_ring.virt_buffer[j])
+                                        dma_free_coherent(priv->dev,
+                                                        RIO_MSG_BUFFER_SIZE,
+                                                        rmu->msg_tx_ring.
+                                                        virt_buffer[j],
+                                                        rmu->msg_tx_ring.
+                                                        phys_buffer[j]);
+                        goto out;
+                }
+        }
+        /* Initialize outbound message descriptor ring */
+        rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
+                                rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
+                                &rmu->msg_tx_ring.phys, GFP_KERNEL);
+        if (!rmu->msg_tx_ring.virt) {
+                rc = -ENOMEM;
+                goto out_dma;
+        }
+        memset(rmu->msg_tx_ring.virt, 0,
+                        rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
+        rmu->msg_tx_ring.tx_slot = 0;
+        /* Point dequeue/enqueue pointers at first entry in ring */
+        out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
+        out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
+        /* Configure for snooping */
+        out_be32(&rmu->msg_regs->osar, 0x00000004);
+        /* Clear interrupt status */
+        out_be32(&rmu->msg_regs->osr, 0x000000b3);
+        /* Hook up outbound message handler */
+        rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
+                         "msg_tx", (void *)mport);
+        if (rc < 0)
+                goto out_irq;
+        /*
+         * Configure outbound message unit
+         *      Snooping
+         *      Interrupts (all enabled, except QEIE)
+         *      Chaining mode
+         *      Disable
+         */
+        out_be32(&rmu->msg_regs->omr, 0x00100220);
+        /* Set number of entries */
+        out_be32(&rmu->msg_regs->omr,
+                 in_be32(&rmu->msg_regs->omr) |
+                 ((get_bitmask_order(entries) - 2) << 12));
+        /* Now enable the unit */
+        out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
+out:
+        return rc;
+out_irq:
+        dma_free_coherent(priv->dev,
+                rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
+                rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
+out_dma:
+        for (i = 0; i < rmu->msg_tx_ring.size; i++)
+                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
+                rmu->msg_tx_ring.virt_buffer[i],
+                rmu->msg_tx_ring.phys_buffer[i]);
+        return rc;
+}
+/**
+ * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
+ * @mport: Master port implementing the outbound message unit
+ * @mbox: Mailbox to close
+ *
+ * Disables the outbound message unit, free all buffers, and
+ * frees the outbound message interrupt.
+ */
+void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
+{
+        struct rio_priv *priv = mport->priv;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        /* Disable inbound message unit */
+        out_be32(&rmu->msg_regs->omr, 0);
+        /* Free ring */
+        dma_free_coherent(priv->dev,
+        rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
+        rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
+        /* Free interrupt */
+        free_irq(IRQ_RIO_TX(mport), (void *)mport);
+}
+/**
+ * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
+ * @mport: Master port implementing the inbound message unit
+ * @dev_id: Device specific pointer to pass on event
+ * @mbox: Mailbox to open
+ * @entries: Number of entries in the inbound mailbox ring
+ *
+ * Initializes buffer ring, request the inbound message interrupt,
+ * and enables the inbound message unit. Returns %0 on success
+ * and %-EINVAL or %-ENOMEM on failure.
+ */
+int
+fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
+{
+        int i, rc = 0;
+        struct rio_priv *priv = mport->priv;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        if ((entries < RIO_MIN_RX_RING_SIZE) ||
+                (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
+                rc = -EINVAL;
+                goto out;
+        }
+        /* Initialize client buffer ring */
+        rmu->msg_rx_ring.dev_id = dev_id;
+        rmu->msg_rx_ring.size = entries;
+        rmu->msg_rx_ring.rx_slot = 0;
+        for (i = 0; i < rmu->msg_rx_ring.size; i++)
+                rmu->msg_rx_ring.virt_buffer[i] = NULL;
+        /* Initialize inbound message ring */
+        rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
+                                rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
+                                &rmu->msg_rx_ring.phys, GFP_KERNEL);
+        if (!rmu->msg_rx_ring.virt) {
+                rc = -ENOMEM;
+                goto out;
+        }
+        /* Point dequeue/enqueue pointers at first entry in ring */
+        out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
+        out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
+        /* Clear interrupt status */
+        out_be32(&rmu->msg_regs->isr, 0x00000091);
+        /* Hook up inbound message handler */
+        rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
+                         "msg_rx", (void *)mport);
+        if (rc < 0) {
+                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
+                        rmu->msg_tx_ring.virt_buffer[i],
+                        rmu->msg_tx_ring.phys_buffer[i]);
+                goto out;
+        }
+        /*
+         * Configure inbound message unit:
+         *      Snooping
+         *      4KB max message size
+         *      Unmask all interrupt sources
+         *      Disable
+         */
+        out_be32(&rmu->msg_regs->imr, 0x001b0060);
+        /* Set number of queue entries */
+        setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
+        /* Now enable the unit */
+        setbits32(&rmu->msg_regs->imr, 0x1);
+out:
+        return rc;
+}
+/**
+ * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
+ * @mport: Master port implementing the inbound message unit
+ * @mbox: Mailbox to close
+ *
+ * Disables the inbound message unit, free all buffers, and
+ * frees the inbound message interrupt.
+ */
+void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
+{
+        struct rio_priv *priv = mport->priv;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        /* Disable inbound message unit */
+        out_be32(&rmu->msg_regs->imr, 0);
+        /* Free ring */
+        dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
+        rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
+        /* Free interrupt */
+        free_irq(IRQ_RIO_RX(mport), (void *)mport);
+}
+/**
+ * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
+ * @mport: Master port implementing the inbound message unit
+ * @mbox: Inbound mailbox number
+ * @buf: Buffer to add to inbound queue
+ *
+ * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
+ * %0 on success or %-EINVAL on failure.
+ */
+int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
+{
+        int rc = 0;
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
+                 rmu->msg_rx_ring.rx_slot);
+        if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
+                printk(KERN_ERR
+                        "RIO: error adding inbound buffer %d, buffer exists\n",
+                        rmu->msg_rx_ring.rx_slot);
+                rc = -EINVAL;
+                goto out;
+        }
+        rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
+        if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
+                rmu->msg_rx_ring.rx_slot = 0;
+out:
+        return rc;
+}
+/**
+ * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
+ * @mport: Master port implementing the inbound message unit
+ * @mbox: Inbound mailbox number
+ *
+ * Gets the next available inbound message from the inbound message queue.
+ * A pointer to the message is returned on success or NULL on failure.
+ */
+void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
+{
+        struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
+        u32 phys_buf, virt_buf;
+        void *buf = NULL;
+        int buf_idx;
+        phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
+        /* If no more messages, then bail out */
+        if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
+                goto out2;
+        virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf
+                                                - rmu->msg_rx_ring.phys);
+        buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
+        buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
+        if (!buf) {
+                printk(KERN_ERR
+                        "RIO: inbound message copy failed, no buffers\n");
+                goto out1;
+        }
+        /* Copy max message size, caller is expected to allocate that big */
+        memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
+        /* Clear the available buffer */
+        rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
+out1:
+        setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
+out2:
+        return buf;
+}
+/**
+ * fsl_rio_doorbell_init - MPC85xx doorbell interface init
+ * @mport: Master port implementing the inbound doorbell unit
+ *
+ * Initializes doorbell unit hardware and inbound DMA buffer
+ * ring. Called from fsl_rio_setup(). Returns %0 on success
+ * or %-ENOMEM on failure.
+ */
+int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell)
+{
+        int rc = 0;
+        /* Initialize inbound doorbells */
+        dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 *
+                DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL);
+        if (!dbell->dbell_ring.virt) {
+                printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
+                rc = -ENOMEM;
+                goto out;
+        }
+        /* Point dequeue/enqueue pointers at first entry in ring */
+        out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys);
+        out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys);
+        /* Clear interrupt status */
+        out_be32(&dbell->dbell_regs->dsr, 0x00000091);
+        /* Hook up doorbell handler */
+        rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0,
+                         "dbell_rx", (void *)dbell);
+        if (rc < 0) {
+                dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE,
+                         dbell->dbell_ring.virt, dbell->dbell_ring.phys);
+                printk(KERN_ERR
+                        "MPC85xx RIO: unable to request inbound doorbell irq");
+                goto out;
+        }
+        /* Configure doorbells for snooping, 512 entries, and enable */
+        out_be32(&dbell->dbell_regs->dmr, 0x00108161);
+out:
+        return rc;
+}
+int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
+{
+        struct rio_priv *priv;
+        struct fsl_rmu *rmu;
+        u64 msg_start;
+        const u32 *msg_addr;
+        int mlen;
+        int aw;
+        if (!mport || !mport->priv)
+                return -EINVAL;
+        priv = mport->priv;
+        if (!node) {
+                dev_warn(priv->dev, "Can't get %s property 'fsl,rmu'\n",
+                        priv->dev->of_node->full_name);
+                return -EINVAL;
+        }
+        rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
+        if (!rmu)
+                return -ENOMEM;
+        aw = of_n_addr_cells(node);
+        msg_addr = of_get_property(node, "reg", &mlen);
+        if (!msg_addr) {
+                pr_err("%s: unable to find 'reg' property of message-unit\n",
+                        node->full_name);
+                kfree(rmu);
+                return -ENOMEM;
+        }
+        msg_start = of_read_number(msg_addr, aw);
+        rmu->msg_regs = (struct rio_msg_regs *)
+                        (rmu_regs_win + (u32)msg_start);
+        rmu->txirq = irq_of_parse_and_map(node, 0);
+        rmu->rxirq = irq_of_parse_and_map(node, 1);
+        printk(KERN_INFO "%s: txirq: %d, rxirq %d\n",
+                node->full_name, rmu->txirq, rmu->rxirq);
+        priv->rmm_handle = rmu;
+        rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
+        rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
+        rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
+        return 0;
+}
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8c7e8528e7c4..4e9ccb1015de 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -154,7 +154,7 @@ static inline unsigned int mpic_processor_id(struct mpic *mpic)
 {
        unsigned int cpu = 0;
-        if (mpic->flags & MPIC_PRIMARY)
+        if (!(mpic->flags & MPIC_SECONDARY))
                cpu = hard_smp_processor_id();
        return cpu;
@@ -315,29 +315,25 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 }
 #ifdef CONFIG_PPC_DCR
-static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
+static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
-                          struct mpic_reg_bank *rb,
                          unsigned int offset, unsigned int size)
 {
-        const u32 *dbasep;
+        phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
+        rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
-        dbasep = of_get_property(node, "dcr-reg", NULL);
-        rb->dhost = dcr_map(node, *dbasep + offset, size);
        BUG_ON(!DCR_MAP_OK(rb->dhost));
 }
-static inline void mpic_map(struct mpic *mpic, struct device_node *node,
+static inline void mpic_map(struct mpic *mpic,
                            phys_addr_t phys_addr, struct mpic_reg_bank *rb,
                            unsigned int offset, unsigned int size)
 {
        if (mpic->flags & MPIC_USES_DCR)
-                _mpic_map_dcr(mpic, node, rb, offset, size);
+                _mpic_map_dcr(mpic, rb, offset, size);
        else
                _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 }
 #else /* CONFIG_PPC_DCR */
-#define mpic_map(m,n,p,b,o,s)   _mpic_map_mmio(m,p,b,o,s)
+#define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
 #endif /* !CONFIG_PPC_DCR */
@@ -901,7 +897,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
        if (vold != vnew)
                mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
-        return IRQ_SET_MASK_OK_NOCOPY;;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 void mpic_set_vector(unsigned int virq, unsigned int vector)
@@ -990,7 +986,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
 #ifdef CONFIG_SMP
        else if (hw >= mpic->ipi_vecs[0]) {
-                WARN_ON(!(mpic->flags & MPIC_PRIMARY));
+                WARN_ON(mpic->flags & MPIC_SECONDARY);
                DBG("mpic: mapping as IPI\n");
                irq_set_chip_data(virq, mpic);
@@ -1001,7 +997,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
 #endif /* CONFIG_SMP */
        if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
-                WARN_ON(!(mpic->flags & MPIC_PRIMARY));
+                WARN_ON(mpic->flags & MPIC_SECONDARY);
                DBG("mpic: mapping as timer\n");
                irq_set_chip_data(virq, mpic);
@@ -1115,17 +1111,28 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
        return 0;
 }
+/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
+static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct mpic *mpic = irq_desc_get_handler_data(desc);
+        unsigned int virq;
+        BUG_ON(!(mpic->flags & MPIC_SECONDARY));
+        virq = mpic_get_one_irq(mpic);
+        if (virq != NO_IRQ)
+                generic_handle_irq(virq);
+        chip->irq_eoi(&desc->irq_data);
+}
 static struct irq_host_ops mpic_host_ops = {
        .match = mpic_host_match,
        .map = mpic_host_map,
        .xlate = mpic_host_xlate,
 };
-static int mpic_reset_prohibited(struct device_node *node)
-{
-        return node && of_get_property(node, "pic-no-reset", NULL);
-}
 /*
 * Exported functions
 */
@@ -1137,27 +1144,60 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                                unsigned int irq_count,
                                const char *name)
 {
-        struct mpic     *mpic;
+        int i, psize, intvec_top;
-        u32             greg_feature;
+        struct mpic *mpic;
-        const char      *vers;
+        u32 greg_feature;
-        int             i;
+        const char *vers;
-        int             intvec_top;
+        const u32 *psrc;
-        u64             paddr = phys_addr;
+        /* Default MPIC search parameters */
+        static const struct of_device_id __initconst mpic_device_id[] = {
+                { .type       = "open-pic", },
+                { .compatible = "open-pic", },
+                {},
+        };
+        /*
+         * If we were not passed a device-tree node, then perform the default
+         * search for standardized a standardized OpenPIC.
+         */
+        if (node) {
+                node = of_node_get(node);
+        } else {
+                node = of_find_matching_node(NULL, mpic_device_id);
+                if (!node)
+                        return NULL;
+        }
+        /* Pick the physical address from the device tree if unspecified */
+        if (!phys_addr) {
+                /* Check if it is DCR-based */
+                if (of_get_property(node, "dcr-reg", NULL)) {
+                        flags |= MPIC_USES_DCR;
+                } else {
+                        struct resource r;
+                        if (of_address_to_resource(node, 0, &r))
+                                goto err_of_node_put;
+                        phys_addr = r.start;
+                }
+        }
        mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
        if (mpic == NULL)
-                return NULL;
+                goto err_of_node_put;
        mpic->name = name;
+        mpic->node = node;
+        mpic->paddr = phys_addr;
        mpic->hc_irq = mpic_irq_chip;
        mpic->hc_irq.name = name;
-        if (flags & MPIC_PRIMARY)
+        if (!(flags & MPIC_SECONDARY))
                mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
        mpic->hc_ht_irq = mpic_irq_ht_chip;
        mpic->hc_ht_irq.name = name;
-        if (flags & MPIC_PRIMARY)
+        if (!(flags & MPIC_SECONDARY))
                mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
@@ -1194,28 +1234,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
        mpic->spurious_vec  = intvec_top;
        /* Check for "big-endian" in device-tree */
-        if (node && of_get_property(node, "big-endian", NULL) != NULL)
+        if (of_get_property(mpic->node, "big-endian", NULL) != NULL)
                mpic->flags |= MPIC_BIG_ENDIAN;
-        if (node && of_device_is_compatible(node, "fsl,mpic"))
+        if (of_device_is_compatible(mpic->node, "fsl,mpic"))
                mpic->flags |= MPIC_FSL;
        /* Look for protected sources */
-        if (node) {
+        psrc = of_get_property(mpic->node, "protected-sources", &psize);
-                int psize;
+        if (psrc) {
-                unsigned int bits, mapsize;
+                /* Allocate a bitmap with one bit per interrupt */
-                const u32 *psrc =
+                unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
-                        of_get_property(node, "protected-sources", &psize);
+                mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
-                if (psrc) {
+                BUG_ON(mpic->protected == NULL);
-                        psize /= 4;
+                for (i = 0; i < psize/sizeof(u32); i++) {
-                        bits = intvec_top + 1;
+                        if (psrc[i] > intvec_top)
-                        mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
+                                continue;
-                        mpic->protected = kzalloc(mapsize, GFP_KERNEL);
+                        __set_bit(psrc[i], mpic->protected);
-                        BUG_ON(mpic->protected == NULL);
-                        for (i = 0; i < psize; i++) {
-                                if (psrc[i] > intvec_top)
-                                        continue;
-                                __set_bit(psrc[i], mpic->protected);
-                        }
                }
        }
@@ -1224,42 +1258,32 @@ struct mpic * __init mpic_alloc(struct device_node *node,
 #endif
        /* default register type */
-        mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
+        if (flags & MPIC_BIG_ENDIAN)
-                mpic_access_mmio_be : mpic_access_mmio_le;
+                mpic->reg_type = mpic_access_mmio_be;
+        else
-        /* If no physical address is passed in, a device-node is mandatory */
+                mpic->reg_type = mpic_access_mmio_le;
-        BUG_ON(paddr == 0 && node == NULL);
-        /* If no physical address passed in, check if it's dcr based */
+        /*
-        if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
+         * An MPIC with a "dcr-reg" property must be accessed that way, but
+         * only if the kernel includes DCR support.
+         */
 #ifdef CONFIG_PPC_DCR
-                mpic->flags |= MPIC_USES_DCR;
+        if (flags & MPIC_USES_DCR)
                mpic->reg_type = mpic_access_dcr;
 #else
-                BUG();
+        BUG_ON(flags & MPIC_USES_DCR);
-#endif /* CONFIG_PPC_DCR */
+#endif
-        }
-        /* If the MPIC is not DCR based, and no physical address was passed
-         * in, try to obtain one
-         */
-        if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
-                const u32 *reg = of_get_property(node, "reg", NULL);
-                BUG_ON(reg == NULL);
-                paddr = of_translate_address(node, reg);
-                BUG_ON(paddr == OF_BAD_ADDR);
-        }
        /* Map the global registers */
-        mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
+        mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
-        mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
+        mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
        /* Reset */
        /* When using a device-node, reset requests are only honored if the MPIC
         * is allowed to reset.
         */
-        if (mpic_reset_prohibited(node))
+        if (of_get_property(mpic->node, "pic-no-reset", NULL))
                mpic->flags |= MPIC_NO_RESET;
        if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
@@ -1307,7 +1331,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
        for_each_possible_cpu(i) {
                unsigned int cpu = get_hard_smp_processor_id(i);
-                mpic_map(mpic, node, paddr, &mpic->cpuregs[cpu],
+                mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
                         MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
                         0x1000);
        }
@@ -1315,16 +1339,21 @@ struct mpic * __init mpic_alloc(struct device_node *node,
        /* Initialize main ISU if none provided */
        if (mpic->isu_size == 0) {
                mpic->isu_size = mpic->num_sources;
-                mpic_map(mpic, node, paddr, &mpic->isus[0],
+                mpic_map(mpic, mpic->paddr, &mpic->isus[0],
                         MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
        }
        mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
        mpic->isu_mask = (1 << mpic->isu_shift) - 1;
-        mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
+        mpic->irqhost = irq_alloc_host(mpic->node, IRQ_HOST_MAP_LINEAR,
                                       isu_size ? isu_size : mpic->num_sources,
                                       &mpic_host_ops,
                                       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
+        /*
+         * FIXME: The code leaks the MPIC object and mappings here; this
+         * is very unlikely to fail but it ought to be fixed anyways.
+         */
        if (mpic->irqhost == NULL)
                return NULL;
@@ -1347,19 +1376,23 @@ struct mpic * __init mpic_alloc(struct device_node *node,
        }
        printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
               " max %d CPUs\n",
-               name, vers, (unsigned long long)paddr, num_possible_cpus());
+               name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
        printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
               mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
        mpic->next = mpics;
        mpics = mpic;
-        if (flags & MPIC_PRIMARY) {
+        if (!(flags & MPIC_SECONDARY)) {
                mpic_primary = mpic;
                irq_set_default_host(mpic->irqhost);
        }
        return mpic;
+err_of_node_put:
+        of_node_put(node);
+        return NULL;
 }
 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
@@ -1369,7 +1402,7 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
        BUG_ON(isu_num >= MPIC_MAX_ISU);
-        mpic_map(mpic, mpic->irqhost->of_node,
+        mpic_map(mpic,
                 paddr, &mpic->isus[isu_num], 0,
                 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
@@ -1385,8 +1418,7 @@ void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
 void __init mpic_init(struct mpic *mpic)
 {
-        int i;
+        int i, cpu;
-        int cpu;
        BUG_ON(mpic->num_sources == 0);
@@ -1424,7 +1456,7 @@ void __init mpic_init(struct mpic *mpic)
        /* Do the HT PIC fixups on U3 broken mpic */
        DBG("MPIC flags: %x\n", mpic->flags);
-        if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
+        if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
                mpic_scan_ht_pics(mpic);
                mpic_u3msi_init(mpic);
        }
@@ -1471,6 +1503,17 @@ void __init mpic_init(struct mpic *mpic)
                                  GFP_KERNEL);
        BUG_ON(mpic->save_data == NULL);
 #endif
+        /* Check if this MPIC is chained from a parent interrupt controller */
+        if (mpic->flags & MPIC_SECONDARY) {
+                int virq = irq_of_parse_and_map(mpic->node, 0);
+                if (virq != NO_IRQ) {
+                        printk(KERN_INFO "%s: hooking up to IRQ %d\n",
+                                        mpic->node->full_name, virq);
+                        irq_set_handler_data(virq, mpic);
+                        irq_set_chained_handler(virq, &mpic_cascade);
+                }
+        }
 }
 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 862f11b3821e..4f05f7542346 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -185,9 +185,15 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
 out:
        dma_offset_set = 1;
        pci_dram_offset = res->start;
+        hose->dma_window_base_cur = res->start;
+        hose->dma_window_size = resource_size(res);
        printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
               pci_dram_offset);
+        printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
+               (unsigned long long)hose->dma_window_base_cur);
+        printk(KERN_INFO "DMA window size 0x%016llx\n",
+               (unsigned long long)hose->dma_window_size);
        return 0;
 }
@@ -647,6 +653,7 @@ static unsigned int ppc4xx_pciex_port_count;
 struct ppc4xx_pciex_hwops
 {
+        bool want_sdr;
        int (*core_init)(struct device_node *np);
        int (*port_init_hw)(struct ppc4xx_pciex_port *port);
        int (*setup_utl)(struct ppc4xx_pciex_port *port);
@@ -916,6 +923,7 @@ static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
        .core_init      = ppc440spe_pciex_core_init,
        .port_init_hw   = ppc440speA_pciex_init_port_hw,
        .setup_utl      = ppc440speA_pciex_init_utl,
@@ -924,6 +932,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
        .core_init      = ppc440spe_pciex_core_init,
        .port_init_hw   = ppc440speB_pciex_init_port_hw,
        .setup_utl      = ppc440speB_pciex_init_utl,
@@ -1034,6 +1043,7 @@ static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
        .core_init      = ppc460ex_pciex_core_init,
        .port_init_hw   = ppc460ex_pciex_init_port_hw,
        .setup_utl      = ppc460ex_pciex_init_utl,
@@ -1181,6 +1191,7 @@ done:
 }
 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
+        .want_sdr       = true,
        .core_init      = ppc460sx_pciex_core_init,
        .port_init_hw   = ppc460sx_pciex_init_port_hw,
        .setup_utl      = ppc460sx_pciex_init_utl,
@@ -1276,6 +1287,7 @@ static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
        .core_init      = ppc405ex_pciex_core_init,
        .port_init_hw   = ppc405ex_pciex_init_port_hw,
        .setup_utl      = ppc405ex_pciex_init_utl,
@@ -1284,6 +1296,52 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
 #endif /* CONFIG_40x */
+#ifdef CONFIG_476FPE
+static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
+{
+        return 4;
+}
+static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
+{
+        u32 timeout_ms = 20;
+        u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
+        void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
+                                      0x1000);
+        printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
+        if (mbase == NULL) {
+                printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
+                                    port->index);
+                return;
+        }
+                
+        while (timeout_ms--) {
+                val = in_le32(mbase + PECFG_TLDLP);
+                if ((val & mask) == mask)
+                        break;
+                msleep(10);
+        }
+        if (val & PECFG_TLDLP_PRESENT) {
+                printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
+                port->link = 1;
+        } else
+                printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
+        iounmap(mbase);
+        return;
+}
+static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
+{
+        .core_init      = ppc_476fpe_pciex_core_init,
+        .check_link     = ppc_476fpe_pciex_check_link,
+};
+#endif /* CONFIG_476FPE */
 /* Check that the core has been initied and if not, do it */
 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
 {
@@ -1309,6 +1367,10 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
        if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
                ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
 #endif
+#ifdef CONFIG_476FPE
+        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
+                ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
+#endif
        if (ppc4xx_pciex_hwops == NULL) {
                printk(KERN_WARNING "PCIE: unknown host type %s\n",
                       np->full_name);
@@ -1617,6 +1679,10 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port	*port,
                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
                                        | DCRO_PEGPL_OMRxMSKL_VAL);
+                else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
+                                sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
+                                        | DCRO_PEGPL_OMRxMSKL_VAL);
                else
                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                sa | DCRO_PEGPL_OMR1MSKL_UOT
@@ -1739,9 +1805,10 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
                /* Calculate window size */
                sa = (0xffffffffffffffffull << ilog2(size));
                if (res->flags & IORESOURCE_PREFETCH)
-                        sa |= 0x8;
+                        sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
-                if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
+                if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
+                    of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
                        sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
                out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
@@ -1972,13 +2039,15 @@ static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
        }
        port->node = of_node_get(np);
-        pval = of_get_property(np, "sdr-base", NULL);
+        if (ppc4xx_pciex_hwops->want_sdr) {
-        if (pval == NULL) {
+                pval = of_get_property(np, "sdr-base", NULL);
-                printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
+                if (pval == NULL) {
-                       np->full_name);
+                        printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
-                return;
+                               np->full_name);
+                        return;
+                }
+                port->sdr_base = *pval;
        }
-        port->sdr_base = *pval;
        /* Check if device_type property is set to "pci" or "pci-endpoint".
         * Resulting from this setup this PCIe port will be configured
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 32ce763a375a..bb4821938ab1 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -476,6 +476,13 @@
 #define DCRO_PEGPL_OMR1MSKL_UOT  0x00000002
 #define DCRO_PEGPL_OMR3MSKL_IO   0x00000002
+/* 476FPE */
+#define PCCFG_LCPA                      0x270
+#define PECFG_TLDLP                     0x3F8
+#define PECFG_TLDLP_LNKUP               0x00000008
+#define PECFG_TLDLP_PRESENT             0x00000010
+#define DCRO_PEGPL_476FPE_OMR1MSKL_UOT   0x00000004
 /* SDR Bit Mappings */
 #define PESDRx_RCSSET_HLDPLB    0x10000000
 #define PESDRx_RCSSET_RSTGU     0x01000000
diff --git a/arch/powerpc/sysdev/xics/icp-hv.c b/arch/powerpc/sysdev/xics/icp-hv.c
index 9518d367a64f..253dce98c16e 100644
--- a/arch/powerpc/sysdev/xics/icp-hv.c
+++ b/arch/powerpc/sysdev/xics/icp-hv.c
@@ -27,33 +27,50 @@ static inline unsigned int icp_hv_get_xirr(unsigned char cppr)
 {
        unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
        long rc;
+        unsigned int ret = XICS_IRQ_SPURIOUS;
        rc = plpar_hcall(H_XIRR, retbuf, cppr);
-        if (rc != H_SUCCESS)
+        if (rc == H_SUCCESS) {
-                panic(" bad return code xirr - rc = %lx\n", rc);
+                ret = (unsigned int)retbuf[0];
-        return (unsigned int)retbuf[0];
+        } else {
-}
+                pr_err("%s: bad return code xirr cppr=0x%x returned %ld\n",
+                        __func__, cppr, rc);
+                WARN_ON_ONCE(1);
+        }
-static inline void icp_hv_set_xirr(unsigned int value)
+        return ret;
-{
-        long rc = plpar_hcall_norets(H_EOI, value);
-        if (rc != H_SUCCESS)
-                panic("bad return code EOI - rc = %ld, value=%x\n", rc, value);
 }
 static inline void icp_hv_set_cppr(u8 value)
 {
        long rc = plpar_hcall_norets(H_CPPR, value);
-        if (rc != H_SUCCESS)
+        if (rc != H_SUCCESS) {
-                panic("bad return code cppr - rc = %lx\n", rc);
+                pr_err("%s: bad return code cppr cppr=0x%x returned %ld\n",
+                        __func__, value, rc);
+                WARN_ON_ONCE(1);
+        }
+}
+static inline void icp_hv_set_xirr(unsigned int value)
+{
+        long rc = plpar_hcall_norets(H_EOI, value);
+        if (rc != H_SUCCESS) {
+                pr_err("%s: bad return code eoi xirr=0x%x returned %ld\n",
+                        __func__, value, rc);
+                WARN_ON_ONCE(1);
+                icp_hv_set_cppr(value >> 24);
+        }
 }
 static inline void icp_hv_set_qirr(int n_cpu , u8 value)
 {
-        long rc = plpar_hcall_norets(H_IPI, get_hard_smp_processor_id(n_cpu),
+        int hw_cpu = get_hard_smp_processor_id(n_cpu);
-                                     value);
+        long rc = plpar_hcall_norets(H_IPI, hw_cpu, value);
-        if (rc != H_SUCCESS)
+        if (rc != H_SUCCESS) {
-                panic("bad return code qirr - rc = %lx\n", rc);
+                pr_err("%s: bad return code qirr cpu=%d hw_cpu=%d mfrr=0x%x "
+                        "returned %ld\n", __func__, n_cpu, hw_cpu, value, rc);
+                WARN_ON_ONCE(1);
+        }
 }
 static void icp_hv_eoi(struct irq_data *d)
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index 63762c672a03..d72eda6a4c05 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -137,7 +137,7 @@ static void xics_request_ipi(void)
         * IPIs are marked IRQF_PERCPU. The handler was set in map.
         */
        BUG_ON(request_irq(ipi, icp_ops->ipi_action,
-                           IRQF_PERCPU, "IPI", NULL));
+                           IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
 }
 int __init xics_smp_probe(void)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 03a217ae3be0..cb95eea74d3d 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -228,13 +228,11 @@ Commands:\n\
  t     print backtrace\n\
  x     exit monitor and recover\n\
  X     exit monitor and dont recover\n"
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PPC64) && !defined(CONFIG_PPC_BOOK3E)
 "  u    dump segment table or SLB\n"
-#endif
+#elif defined(CONFIG_PPC_STD_MMU_32)
-#ifdef CONFIG_PPC_STD_MMU_32
 "  u    dump segment registers\n"
-#endif
+#elif defined(CONFIG_44x) || defined(CONFIG_PPC_BOOK3E)
-#ifdef CONFIG_44x
 "  u    dump TLB\n"
 #endif
 "  ?    help\n"
@@ -340,7 +338,7 @@ int cpus_are_in_xmon(void)
 static inline int unrecoverable_excp(struct pt_regs *regs)
 {
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
+#if defined(CONFIG_4xx) || defined(CONFIG_PPC_BOOK3E)
        /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
        return 0;
 #else
@@ -885,13 +883,11 @@ cmds(struct pt_regs *excp)
                case 'u':
                        dump_segments();
                        break;
-#endif
+#elif defined(CONFIG_4xx)
-#ifdef CONFIG_4xx
                case 'u':
                        dump_tlb_44x();
                        break;
-#endif
+#elif defined(CONFIG_PPC_BOOK3E)
-#ifdef CONFIG_PPC_BOOK3E
                case 'u':
                        dump_tlb_book3e();
                        break;
author	Linus Torvalds <torvalds@linux-foundation.org>	2012-01-06 20:58:22 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2012-01-06 20:58:22 -0500
commit	e4e88f31bcb5f05f24b9ae518d4ecb44e1a7774d (patch)
tree	9eef6998f5bbd1a2c999011d9e0151f00c6e7297 /arch/powerpc
parent	9753dfe19a85e7e45a34a56f4cb2048bb4f50e27 (diff)
parent	ef88e3911c0e0301e73fa3b3b2567aabdbe17cc4 (diff)