diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
| commit | bbb20089a3275a19e475dbc21320c3742e3ca423 (patch) | |
| tree | 216fdc1cbef450ca688135c5b8969169482d9a48 /arch/powerpc | |
| parent | 3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff) | |
| parent | 657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff) | |
Merge branch 'dmaengine' into async-tx-next
Conflicts:
crypto/async_tx/async_xor.c
drivers/dma/ioat/dma_v2.h
drivers/dma/ioat/pci.c
drivers/md/raid5.c
Diffstat (limited to 'arch/powerpc')
277 files changed, 19561 insertions, 2564 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index cdc9a6ff4be8..bf6cedfa05db 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig | |||
| @@ -42,6 +42,10 @@ config GENERIC_HARDIRQS | |||
| 42 | bool | 42 | bool |
| 43 | default y | 43 | default y |
| 44 | 44 | ||
| 45 | config GENERIC_HARDIRQS_NO__DO_IRQ | ||
| 46 | bool | ||
| 47 | default y | ||
| 48 | |||
| 45 | config HAVE_SETUP_PER_CPU_AREA | 49 | config HAVE_SETUP_PER_CPU_AREA |
| 46 | def_bool PPC64 | 50 | def_bool PPC64 |
| 47 | 51 | ||
| @@ -89,10 +93,6 @@ config GENERIC_HWEIGHT | |||
| 89 | bool | 93 | bool |
| 90 | default y | 94 | default y |
| 91 | 95 | ||
| 92 | config GENERIC_CALIBRATE_DELAY | ||
| 93 | bool | ||
| 94 | default y | ||
| 95 | |||
| 96 | config GENERIC_FIND_NEXT_BIT | 96 | config GENERIC_FIND_NEXT_BIT |
| 97 | bool | 97 | bool |
| 98 | default y | 98 | default y |
| @@ -125,6 +125,8 @@ config PPC | |||
| 125 | select USE_GENERIC_SMP_HELPERS if SMP | 125 | select USE_GENERIC_SMP_HELPERS if SMP |
| 126 | select HAVE_OPROFILE | 126 | select HAVE_OPROFILE |
| 127 | select HAVE_SYSCALL_WRAPPERS if PPC64 | 127 | select HAVE_SYSCALL_WRAPPERS if PPC64 |
| 128 | select GENERIC_ATOMIC64 if PPC32 | ||
| 129 | select HAVE_PERF_COUNTERS | ||
| 128 | 130 | ||
| 129 | config EARLY_PRINTK | 131 | config EARLY_PRINTK |
| 130 | bool | 132 | bool |
| @@ -296,9 +298,19 @@ config IOMMU_VMERGE | |||
| 296 | config IOMMU_HELPER | 298 | config IOMMU_HELPER |
| 297 | def_bool PPC64 | 299 | def_bool PPC64 |
| 298 | 300 | ||
| 301 | config SWIOTLB | ||
| 302 | bool "SWIOTLB support" | ||
| 303 | default n | ||
| 304 | select IOMMU_HELPER | ||
| 305 | ---help--- | ||
| 306 | Support for IO bounce buffering for systems without an IOMMU. | ||
| 307 | This allows us to DMA to the full physical address space on | ||
| 308 | platforms where the size of a physical address is larger | ||
| 309 | than the bus address. Not all platforms support this. | ||
| 310 | |||
| 299 | config PPC_NEED_DMA_SYNC_OPS | 311 | config PPC_NEED_DMA_SYNC_OPS |
| 300 | def_bool y | 312 | def_bool y |
| 301 | depends on NOT_COHERENT_CACHE | 313 | depends on (NOT_COHERENT_CACHE || SWIOTLB) |
| 302 | 314 | ||
| 303 | config HOTPLUG_CPU | 315 | config HOTPLUG_CPU |
| 304 | bool "Support for enabling/disabling CPUs" | 316 | bool "Support for enabling/disabling CPUs" |
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index a1098e23221f..3b1005185390 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug | |||
| @@ -2,6 +2,23 @@ menu "Kernel hacking" | |||
| 2 | 2 | ||
| 3 | source "lib/Kconfig.debug" | 3 | source "lib/Kconfig.debug" |
| 4 | 4 | ||
| 5 | config PPC_DISABLE_WERROR | ||
| 6 | bool "Don't build arch/powerpc code with -Werror" | ||
| 7 | default n | ||
| 8 | help | ||
| 9 | This option tells the compiler NOT to build the code under | ||
| 10 | arch/powerpc with the -Werror flag (which means warnings | ||
| 11 | are treated as errors). | ||
| 12 | |||
| 13 | Only enable this if you are hitting a build failure in the | ||
| 14 | arch/powerpc code caused by a warning, and you don't feel | ||
| 15 | inclined to fix it. | ||
| 16 | |||
| 17 | config PPC_WERROR | ||
| 18 | bool | ||
| 19 | depends on !PPC_DISABLE_WERROR | ||
| 20 | default y | ||
| 21 | |||
| 5 | config PRINT_STACK_DEPTH | 22 | config PRINT_STACK_DEPTH |
| 6 | int "Stack depth to print" if DEBUG_KERNEL | 23 | int "Stack depth to print" if DEBUG_KERNEL |
| 7 | default 64 | 24 | default 64 |
| @@ -41,6 +58,19 @@ config HCALL_STATS | |||
| 41 | This option will add a small amount of overhead to all hypervisor | 58 | This option will add a small amount of overhead to all hypervisor |
| 42 | calls. | 59 | calls. |
| 43 | 60 | ||
| 61 | config PPC_EMULATED_STATS | ||
| 62 | bool "Emulated instructions tracking" | ||
| 63 | depends on DEBUG_FS | ||
| 64 | help | ||
| 65 | Adds code to keep track of the number of instructions that are | ||
| 66 | emulated by the in-kernel emulator. Counters for the various classes | ||
| 67 | of emulated instructions are available under | ||
| 68 | powerpc/emulated_instructions/ in the root of the debugfs file | ||
| 69 | system. Optionally (controlled by | ||
| 70 | powerpc/emulated_instructions/do_warn in debugfs), rate-limited | ||
| 71 | warnings can be printed to the console when instructions are | ||
| 72 | emulated. | ||
| 73 | |||
| 44 | config CODE_PATCHING_SELFTEST | 74 | config CODE_PATCHING_SELFTEST |
| 45 | bool "Run self-tests of the code-patching code." | 75 | bool "Run self-tests of the code-patching code." |
| 46 | depends on DEBUG_KERNEL | 76 | depends on DEBUG_KERNEL |
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 551fc58c05cf..bc35f4e2b81c 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile | |||
| @@ -142,6 +142,7 @@ head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o | |||
| 142 | 142 | ||
| 143 | head-$(CONFIG_PPC64) += arch/powerpc/kernel/entry_64.o | 143 | head-$(CONFIG_PPC64) += arch/powerpc/kernel/entry_64.o |
| 144 | head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o | 144 | head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o |
| 145 | head-$(CONFIG_ALTIVEC) += arch/powerpc/kernel/vector.o | ||
| 145 | 146 | ||
| 146 | core-y += arch/powerpc/kernel/ \ | 147 | core-y += arch/powerpc/kernel/ \ |
| 147 | arch/powerpc/mm/ \ | 148 | arch/powerpc/mm/ \ |
diff --git a/arch/powerpc/boot/cuboot-85xx.c b/arch/powerpc/boot/cuboot-85xx.c index 6776a1a29f13..277ba4a79b5a 100644 --- a/arch/powerpc/boot/cuboot-85xx.c +++ b/arch/powerpc/boot/cuboot-85xx.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include "cuboot.h" | 15 | #include "cuboot.h" |
| 16 | 16 | ||
| 17 | #define TARGET_85xx | 17 | #define TARGET_85xx |
| 18 | #define TARGET_HAS_ETH3 | ||
| 18 | #include "ppcboot.h" | 19 | #include "ppcboot.h" |
| 19 | 20 | ||
| 20 | static bd_t bd; | 21 | static bd_t bd; |
| @@ -27,6 +28,7 @@ static void platform_fixups(void) | |||
| 27 | dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); | 28 | dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); |
| 28 | dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr); | 29 | dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr); |
| 29 | dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr); | 30 | dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr); |
| 31 | dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr); | ||
| 30 | dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq); | 32 | dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq); |
| 31 | 33 | ||
| 32 | /* Unfortunately, the specific model number is encoded in the | 34 | /* Unfortunately, the specific model number is encoded in the |
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts index 7da84fd7be93..261d10c4534b 100644 --- a/arch/powerpc/boot/dts/asp834x-redboot.dts +++ b/arch/powerpc/boot/dts/asp834x-redboot.dts | |||
| @@ -167,7 +167,7 @@ | |||
| 167 | interrupt-parent = <&ipic>; | 167 | interrupt-parent = <&ipic>; |
| 168 | interrupts = <39 0x8>; | 168 | interrupts = <39 0x8>; |
| 169 | phy_type = "ulpi"; | 169 | phy_type = "ulpi"; |
| 170 | port1; | 170 | port0; |
| 171 | }; | 171 | }; |
| 172 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ | 172 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ |
| 173 | usb@23000 { | 173 | usb@23000 { |
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index 53a7a6255909..910944edd886 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts | |||
| @@ -164,9 +164,21 @@ | |||
| 164 | device_type = "soc"; | 164 | device_type = "soc"; |
| 165 | compatible = "fsl,mpc8641-soc", "simple-bus"; | 165 | compatible = "fsl,mpc8641-soc", "simple-bus"; |
| 166 | ranges = <0x0 0xfef00000 0x00100000>; | 166 | ranges = <0x0 0xfef00000 0x00100000>; |
| 167 | reg = <0xfef00000 0x100000>; // CCSRBAR 1M | ||
| 168 | bus-frequency = <33333333>; | 167 | bus-frequency = <33333333>; |
| 169 | 168 | ||
| 169 | mcm-law@0 { | ||
| 170 | compatible = "fsl,mcm-law"; | ||
| 171 | reg = <0x0 0x1000>; | ||
| 172 | fsl,num-laws = <10>; | ||
| 173 | }; | ||
| 174 | |||
| 175 | mcm@1000 { | ||
| 176 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 177 | reg = <0x1000 0x1000>; | ||
| 178 | interrupts = <17 2>; | ||
| 179 | interrupt-parent = <&mpic>; | ||
| 180 | }; | ||
| 181 | |||
| 170 | i2c1: i2c@3000 { | 182 | i2c1: i2c@3000 { |
| 171 | #address-cells = <1>; | 183 | #address-cells = <1>; |
| 172 | #size-cells = <0>; | 184 | #size-cells = <0>; |
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 1569117e5ddc..0f4c9ec2c3a6 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts | |||
| @@ -163,9 +163,21 @@ | |||
| 163 | device_type = "soc"; | 163 | device_type = "soc"; |
| 164 | compatible = "simple-bus"; | 164 | compatible = "simple-bus"; |
| 165 | ranges = <0x0 0xfef00000 0x00100000>; | 165 | ranges = <0x0 0xfef00000 0x00100000>; |
| 166 | reg = <0xfef00000 0x100000>; // CCSRBAR 1M | ||
| 167 | bus-frequency = <33333333>; | 166 | bus-frequency = <33333333>; |
| 168 | 167 | ||
| 168 | mcm-law@0 { | ||
| 169 | compatible = "fsl,mcm-law"; | ||
| 170 | reg = <0x0 0x1000>; | ||
| 171 | fsl,num-laws = <10>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | mcm@1000 { | ||
| 175 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 176 | reg = <0x1000 0x1000>; | ||
| 177 | interrupts = <17 2>; | ||
| 178 | interrupt-parent = <&mpic>; | ||
| 179 | }; | ||
| 180 | |||
| 169 | i2c1: i2c@3000 { | 181 | i2c1: i2c@3000 { |
| 170 | #address-cells = <1>; | 182 | #address-cells = <1>; |
| 171 | #size-cells = <0>; | 183 | #size-cells = <0>; |
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 6582dbd36da7..35a63183eecc 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts | |||
| @@ -128,9 +128,21 @@ | |||
| 128 | device_type = "soc"; | 128 | device_type = "soc"; |
| 129 | compatible = "simple-bus"; | 129 | compatible = "simple-bus"; |
| 130 | ranges = <0x0 0xfef00000 0x00100000>; | 130 | ranges = <0x0 0xfef00000 0x00100000>; |
| 131 | reg = <0xfef00000 0x100000>; // CCSRBAR 1M | ||
| 132 | bus-frequency = <33333333>; | 131 | bus-frequency = <33333333>; |
| 133 | 132 | ||
| 133 | mcm-law@0 { | ||
| 134 | compatible = "fsl,mcm-law"; | ||
| 135 | reg = <0x0 0x1000>; | ||
| 136 | fsl,num-laws = <10>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | mcm@1000 { | ||
| 140 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 141 | reg = <0x1000 0x1000>; | ||
| 142 | interrupts = <17 2>; | ||
| 143 | interrupt-parent = <&mpic>; | ||
| 144 | }; | ||
| 145 | |||
| 134 | i2c1: i2c@3000 { | 146 | i2c1: i2c@3000 { |
| 135 | #address-cells = <1>; | 147 | #address-cells = <1>; |
| 136 | #size-cells = <0>; | 148 | #size-cells = <0>; |
| @@ -140,6 +152,16 @@ | |||
| 140 | interrupt-parent = <&mpic>; | 152 | interrupt-parent = <&mpic>; |
| 141 | dfsrr; | 153 | dfsrr; |
| 142 | 154 | ||
| 155 | hwmon@48 { | ||
| 156 | compatible = "national,lm92"; | ||
| 157 | reg = <0x48>; | ||
| 158 | }; | ||
| 159 | |||
| 160 | hwmon@4c { | ||
| 161 | compatible = "adi,adt7461"; | ||
| 162 | reg = <0x4c>; | ||
| 163 | }; | ||
| 164 | |||
| 143 | rtc@51 { | 165 | rtc@51 { |
| 144 | compatible = "epson,rx8581"; | 166 | compatible = "epson,rx8581"; |
| 145 | reg = <0x00000051>; | 167 | reg = <0x00000051>; |
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts new file mode 100644 index 000000000000..167044f7de1d --- /dev/null +++ b/arch/powerpc/boot/dts/kmeter1.dts | |||
| @@ -0,0 +1,520 @@ | |||
| 1 | /* | ||
| 2 | * Keymile KMETER1 Device Tree Source | ||
| 3 | * | ||
| 4 | * 2008 DENX Software Engineering GmbH | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "KMETER1"; | ||
| 16 | compatible = "keymile,KMETER1"; | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <1>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | ethernet0 = &enet_piggy2; | ||
| 22 | ethernet1 = &enet_estar1; | ||
| 23 | ethernet2 = &enet_estar2; | ||
| 24 | ethernet3 = &enet_eth1; | ||
| 25 | ethernet4 = &enet_eth2; | ||
| 26 | ethernet5 = &enet_eth3; | ||
| 27 | ethernet6 = &enet_eth4; | ||
| 28 | serial0 = &serial0; | ||
| 29 | }; | ||
| 30 | |||
| 31 | cpus { | ||
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | |||
| 35 | PowerPC,8360@0 { | ||
| 36 | device_type = "cpu"; | ||
| 37 | reg = <0x0>; | ||
| 38 | d-cache-line-size = <32>; // 32 bytes | ||
| 39 | i-cache-line-size = <32>; // 32 bytes | ||
| 40 | d-cache-size = <32768>; // L1, 32K | ||
| 41 | i-cache-size = <32768>; // L1, 32K | ||
| 42 | timebase-frequency = <0>; /* Filled in by U-Boot */ | ||
| 43 | bus-frequency = <0>; /* Filled in by U-Boot */ | ||
| 44 | clock-frequency = <0>; /* Filled in by U-Boot */ | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | memory { | ||
| 49 | device_type = "memory"; | ||
| 50 | reg = <0 0>; /* Filled in by U-Boot */ | ||
| 51 | }; | ||
| 52 | |||
| 53 | soc8360@e0000000 { | ||
| 54 | #address-cells = <1>; | ||
| 55 | #size-cells = <1>; | ||
| 56 | device_type = "soc"; | ||
| 57 | compatible = "fsl,mpc8360-immr", "simple-bus"; | ||
| 58 | ranges = <0x0 0xe0000000 0x00200000>; | ||
| 59 | reg = <0xe0000000 0x00000200>; | ||
| 60 | bus-frequency = <0>; /* Filled in by U-Boot */ | ||
| 61 | |||
| 62 | i2c@3000 { | ||
| 63 | #address-cells = <1>; | ||
| 64 | #size-cells = <0>; | ||
| 65 | cell-index = <0>; | ||
| 66 | compatible = "fsl-i2c"; | ||
| 67 | reg = <0x3000 0x100>; | ||
| 68 | interrupts = <14 0x8>; | ||
| 69 | interrupt-parent = <&ipic>; | ||
| 70 | dfsrr; | ||
| 71 | }; | ||
| 72 | |||
| 73 | serial0: serial@4500 { | ||
| 74 | cell-index = <0>; | ||
| 75 | device_type = "serial"; | ||
| 76 | compatible = "ns16550"; | ||
| 77 | reg = <0x4500 0x100>; | ||
| 78 | clock-frequency = <264000000>; | ||
| 79 | interrupts = <9 0x8>; | ||
| 80 | interrupt-parent = <&ipic>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | dma@82a8 { | ||
| 84 | #address-cells = <1>; | ||
| 85 | #size-cells = <1>; | ||
| 86 | compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; | ||
| 87 | reg = <0x82a8 4>; | ||
| 88 | ranges = <0 0x8100 0x1a8>; | ||
| 89 | interrupt-parent = <&ipic>; | ||
| 90 | interrupts = <71 8>; | ||
| 91 | cell-index = <0>; | ||
| 92 | dma-channel@0 { | ||
| 93 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | ||
| 94 | reg = <0 0x80>; | ||
| 95 | interrupt-parent = <&ipic>; | ||
| 96 | interrupts = <71 8>; | ||
| 97 | }; | ||
| 98 | dma-channel@80 { | ||
| 99 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | ||
| 100 | reg = <0x80 0x80>; | ||
| 101 | interrupt-parent = <&ipic>; | ||
| 102 | interrupts = <71 8>; | ||
| 103 | }; | ||
| 104 | dma-channel@100 { | ||
| 105 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | ||
| 106 | reg = <0x100 0x80>; | ||
| 107 | interrupt-parent = <&ipic>; | ||
| 108 | interrupts = <71 8>; | ||
| 109 | }; | ||
| 110 | dma-channel@180 { | ||
| 111 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | ||
| 112 | reg = <0x180 0x28>; | ||
| 113 | interrupt-parent = <&ipic>; | ||
| 114 | interrupts = <71 8>; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | |||
| 118 | ipic: pic@700 { | ||
| 119 | #address-cells = <0>; | ||
| 120 | #interrupt-cells = <2>; | ||
| 121 | compatible = "fsl,pq2pro-pic", "fsl,ipic"; | ||
| 122 | interrupt-controller; | ||
| 123 | reg = <0x700 0x100>; | ||
| 124 | }; | ||
| 125 | |||
| 126 | par_io@1400 { | ||
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | reg = <0x1400 0x100>; | ||
| 130 | compatible = "fsl,mpc8360-par_io"; | ||
| 131 | num-ports = <7>; | ||
| 132 | |||
| 133 | pio_ucc1: ucc_pin@0 { | ||
| 134 | reg = <0>; | ||
| 135 | |||
| 136 | pio-map = < | ||
| 137 | /* port pin dir open_drain assignment has_irq */ | ||
| 138 | 0 1 3 0 2 0 /* MDIO */ | ||
| 139 | 0 2 1 0 1 0 /* MDC */ | ||
| 140 | |||
| 141 | 0 3 1 0 1 0 /* TxD0 */ | ||
| 142 | 0 4 1 0 1 0 /* TxD1 */ | ||
| 143 | 0 5 1 0 1 0 /* TxD2 */ | ||
| 144 | 0 6 1 0 1 0 /* TxD3 */ | ||
| 145 | 0 9 2 0 1 0 /* RxD0 */ | ||
| 146 | 0 10 2 0 1 0 /* RxD1 */ | ||
| 147 | 0 11 2 0 1 0 /* RxD2 */ | ||
| 148 | 0 12 2 0 1 0 /* RxD3 */ | ||
| 149 | 0 7 1 0 1 0 /* TX_EN */ | ||
| 150 | 0 8 1 0 1 0 /* TX_ER */ | ||
| 151 | 0 15 2 0 1 0 /* RX_DV */ | ||
| 152 | 0 16 2 0 1 0 /* RX_ER */ | ||
| 153 | 0 0 2 0 1 0 /* RX_CLK */ | ||
| 154 | 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ | ||
| 155 | 2 8 2 0 1 0 /* GTX125 - CLK9 */ | ||
| 156 | >; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pio_ucc2: ucc_pin@1 { | ||
| 160 | reg = <1>; | ||
| 161 | |||
| 162 | pio-map = < | ||
| 163 | /* port pin dir open_drain assignment has_irq */ | ||
| 164 | 0 1 3 0 2 0 /* MDIO */ | ||
| 165 | 0 2 1 0 1 0 /* MDC */ | ||
| 166 | |||
| 167 | 0 17 1 0 1 0 /* TxD0 */ | ||
| 168 | 0 18 1 0 1 0 /* TxD1 */ | ||
| 169 | 0 19 1 0 1 0 /* TxD2 */ | ||
| 170 | 0 20 1 0 1 0 /* TxD3 */ | ||
| 171 | 0 23 2 0 1 0 /* RxD0 */ | ||
| 172 | 0 24 2 0 1 0 /* RxD1 */ | ||
| 173 | 0 25 2 0 1 0 /* RxD2 */ | ||
| 174 | 0 26 2 0 1 0 /* RxD3 */ | ||
| 175 | 0 21 1 0 1 0 /* TX_EN */ | ||
| 176 | 0 22 1 0 1 0 /* TX_ER */ | ||
| 177 | 0 29 2 0 1 0 /* RX_DV */ | ||
| 178 | 0 30 2 0 1 0 /* RX_ER */ | ||
| 179 | 0 31 2 0 1 0 /* RX_CLK */ | ||
| 180 | 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ | ||
| 181 | 2 3 2 0 1 0 /* GTX125 - CLK4 */ | ||
| 182 | >; | ||
| 183 | }; | ||
| 184 | |||
| 185 | pio_ucc4: ucc_pin@3 { | ||
| 186 | reg = <3>; | ||
| 187 | |||
| 188 | pio-map = < | ||
| 189 | /* port pin dir open_drain assignment has_irq */ | ||
| 190 | 0 1 3 0 2 0 /* MDIO */ | ||
| 191 | 0 2 1 0 1 0 /* MDC */ | ||
| 192 | |||
| 193 | 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ | ||
| 194 | 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ | ||
| 195 | 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ | ||
| 196 | 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ | ||
| 197 | 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ | ||
| 198 | 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ | ||
| 199 | 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ | ||
| 200 | |||
| 201 | 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ | ||
| 202 | >; | ||
| 203 | }; | ||
| 204 | |||
| 205 | pio_ucc5: ucc_pin@4 { | ||
| 206 | reg = <4>; | ||
| 207 | |||
| 208 | pio-map = < | ||
| 209 | /* port pin dir open_drain assignment has_irq */ | ||
| 210 | 0 1 3 0 2 0 /* MDIO */ | ||
| 211 | 0 2 1 0 1 0 /* MDC */ | ||
| 212 | |||
| 213 | 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ | ||
| 214 | 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ | ||
| 215 | 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ | ||
| 216 | 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ | ||
| 217 | 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ | ||
| 218 | 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ | ||
| 219 | 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ | ||
| 220 | >; | ||
| 221 | }; | ||
| 222 | |||
| 223 | pio_ucc6: ucc_pin@5 { | ||
| 224 | reg = <5>; | ||
| 225 | |||
| 226 | pio-map = < | ||
| 227 | /* port pin dir open_drain assignment has_irq */ | ||
| 228 | 0 1 3 0 2 0 /* MDIO */ | ||
| 229 | 0 2 1 0 1 0 /* MDC */ | ||
| 230 | |||
| 231 | 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ | ||
| 232 | 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ | ||
| 233 | 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ | ||
| 234 | 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ | ||
| 235 | 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ | ||
| 236 | 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ | ||
| 237 | 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ | ||
| 238 | >; | ||
| 239 | }; | ||
| 240 | |||
| 241 | pio_ucc7: ucc_pin@6 { | ||
| 242 | reg = <6>; | ||
| 243 | |||
| 244 | pio-map = < | ||
| 245 | /* port pin dir open_drain assignment has_irq */ | ||
| 246 | 0 1 3 0 2 0 /* MDIO */ | ||
| 247 | 0 2 1 0 1 0 /* MDC */ | ||
| 248 | |||
| 249 | 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ | ||
| 250 | 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ | ||
| 251 | 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ | ||
| 252 | 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ | ||
| 253 | 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ | ||
| 254 | 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ | ||
| 255 | 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ | ||
| 256 | >; | ||
| 257 | }; | ||
| 258 | |||
| 259 | pio_ucc8: ucc_pin@7 { | ||
| 260 | reg = <7>; | ||
| 261 | |||
| 262 | pio-map = < | ||
| 263 | /* port pin dir open_drain assignment has_irq */ | ||
| 264 | 0 1 3 0 2 0 /* MDIO */ | ||
| 265 | 0 2 1 0 1 0 /* MDC */ | ||
| 266 | |||
| 267 | 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ | ||
| 268 | 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ | ||
| 269 | 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ | ||
| 270 | 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ | ||
| 271 | 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ | ||
| 272 | 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ | ||
| 273 | 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ | ||
| 274 | |||
| 275 | 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ | ||
| 276 | >; | ||
| 277 | }; | ||
| 278 | |||
| 279 | }; | ||
| 280 | |||
| 281 | qe@100000 { | ||
| 282 | #address-cells = <1>; | ||
| 283 | #size-cells = <1>; | ||
| 284 | compatible = "fsl,qe"; | ||
| 285 | ranges = <0x0 0x100000 0x100000>; | ||
| 286 | reg = <0x100000 0x480>; | ||
| 287 | clock-frequency = <0>; /* Filled in by U-Boot */ | ||
| 288 | brg-frequency = <0>; /* Filled in by U-Boot */ | ||
| 289 | bus-frequency = <0>; /* Filled in by U-Boot */ | ||
| 290 | |||
| 291 | muram@10000 { | ||
| 292 | #address-cells = <1>; | ||
| 293 | #size-cells = <1>; | ||
| 294 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; | ||
| 295 | ranges = <0x0 0x00010000 0x0000c000>; | ||
| 296 | |||
| 297 | data-only@0 { | ||
| 298 | compatible = "fsl,qe-muram-data", | ||
| 299 | "fsl,cpm-muram-data"; | ||
| 300 | reg = <0x0 0xc000>; | ||
| 301 | }; | ||
| 302 | }; | ||
| 303 | |||
| 304 | /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ | ||
| 305 | enet_estar1: ucc@2000 { | ||
| 306 | device_type = "network"; | ||
| 307 | compatible = "ucc_geth"; | ||
| 308 | cell-index = <1>; | ||
| 309 | reg = <0x2000 0x200>; | ||
| 310 | interrupts = <32>; | ||
| 311 | interrupt-parent = <&qeic>; | ||
| 312 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 313 | rx-clock-name = "none"; | ||
| 314 | tx-clock-name = "clk9"; | ||
| 315 | phy-handle = <&phy_estar1>; | ||
| 316 | phy-connection-type = "rgmii-id"; | ||
| 317 | pio-handle = <&pio_ucc1>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ | ||
| 321 | enet_estar2: ucc@3000 { | ||
| 322 | device_type = "network"; | ||
| 323 | compatible = "ucc_geth"; | ||
| 324 | cell-index = <2>; | ||
| 325 | reg = <0x3000 0x200>; | ||
| 326 | interrupts = <33>; | ||
| 327 | interrupt-parent = <&qeic>; | ||
| 328 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 329 | rx-clock-name = "none"; | ||
| 330 | tx-clock-name = "clk4"; | ||
| 331 | phy-handle = <&phy_estar2>; | ||
| 332 | phy-connection-type = "rgmii-id"; | ||
| 333 | pio-handle = <&pio_ucc2>; | ||
| 334 | }; | ||
| 335 | |||
| 336 | /* Piggy2 (UCC4, MDIO 0x00, RMII) */ | ||
| 337 | enet_piggy2: ucc@3200 { | ||
| 338 | device_type = "network"; | ||
| 339 | compatible = "ucc_geth"; | ||
| 340 | cell-index = <4>; | ||
| 341 | reg = <0x3200 0x200>; | ||
| 342 | interrupts = <35>; | ||
| 343 | interrupt-parent = <&qeic>; | ||
| 344 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 345 | rx-clock-name = "none"; | ||
| 346 | tx-clock-name = "clk17"; | ||
| 347 | phy-handle = <&phy_piggy2>; | ||
| 348 | phy-connection-type = "rmii"; | ||
| 349 | pio-handle = <&pio_ucc4>; | ||
| 350 | }; | ||
| 351 | |||
| 352 | /* Eth-1 (UCC5, MDIO 0x08, RMII) */ | ||
| 353 | enet_eth1: ucc@2400 { | ||
| 354 | device_type = "network"; | ||
| 355 | compatible = "ucc_geth"; | ||
| 356 | cell-index = <5>; | ||
| 357 | reg = <0x2400 0x200>; | ||
| 358 | interrupts = <40>; | ||
| 359 | interrupt-parent = <&qeic>; | ||
| 360 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 361 | rx-clock-name = "none"; | ||
| 362 | tx-clock-name = "clk16"; | ||
| 363 | phy-handle = <&phy_eth1>; | ||
| 364 | phy-connection-type = "rmii"; | ||
| 365 | pio-handle = <&pio_ucc5>; | ||
| 366 | }; | ||
| 367 | |||
| 368 | /* Eth-2 (UCC6, MDIO 0x09, RMII) */ | ||
| 369 | enet_eth2: ucc@3400 { | ||
| 370 | device_type = "network"; | ||
| 371 | compatible = "ucc_geth"; | ||
| 372 | cell-index = <6>; | ||
| 373 | reg = <0x3400 0x200>; | ||
| 374 | interrupts = <41>; | ||
| 375 | interrupt-parent = <&qeic>; | ||
| 376 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 377 | rx-clock-name = "none"; | ||
| 378 | tx-clock-name = "clk16"; | ||
| 379 | phy-handle = <&phy_eth2>; | ||
| 380 | phy-connection-type = "rmii"; | ||
| 381 | pio-handle = <&pio_ucc6>; | ||
| 382 | }; | ||
| 383 | |||
| 384 | /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ | ||
| 385 | enet_eth3: ucc@2600 { | ||
| 386 | device_type = "network"; | ||
| 387 | compatible = "ucc_geth"; | ||
| 388 | cell-index = <7>; | ||
| 389 | reg = <0x2600 0x200>; | ||
| 390 | interrupts = <42>; | ||
| 391 | interrupt-parent = <&qeic>; | ||
| 392 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 393 | rx-clock-name = "none"; | ||
| 394 | tx-clock-name = "clk16"; | ||
| 395 | phy-handle = <&phy_eth3>; | ||
| 396 | phy-connection-type = "rmii"; | ||
| 397 | pio-handle = <&pio_ucc7>; | ||
| 398 | }; | ||
| 399 | |||
| 400 | /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ | ||
| 401 | enet_eth4: ucc@3600 { | ||
| 402 | device_type = "network"; | ||
| 403 | compatible = "ucc_geth"; | ||
| 404 | cell-index = <8>; | ||
| 405 | reg = <0x3600 0x200>; | ||
| 406 | interrupts = <43>; | ||
| 407 | interrupt-parent = <&qeic>; | ||
| 408 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 409 | rx-clock-name = "none"; | ||
| 410 | tx-clock-name = "clk16"; | ||
| 411 | phy-handle = <&phy_eth4>; | ||
| 412 | phy-connection-type = "rmii"; | ||
| 413 | pio-handle = <&pio_ucc8>; | ||
| 414 | }; | ||
| 415 | |||
| 416 | mdio@3320 { | ||
| 417 | #address-cells = <1>; | ||
| 418 | #size-cells = <0>; | ||
| 419 | reg = <0x3320 0x18>; | ||
| 420 | compatible = "fsl,ucc-mdio"; | ||
| 421 | |||
| 422 | /* Piggy2 (UCC4, MDIO 0x00, RMII) */ | ||
| 423 | phy_piggy2: ethernet-phy@00 { | ||
| 424 | reg = <0x0>; | ||
| 425 | }; | ||
| 426 | |||
| 427 | /* Eth-1 (UCC5, MDIO 0x08, RMII) */ | ||
| 428 | phy_eth1: ethernet-phy@08 { | ||
| 429 | reg = <0x08>; | ||
| 430 | }; | ||
| 431 | |||
| 432 | /* Eth-2 (UCC6, MDIO 0x09, RMII) */ | ||
| 433 | phy_eth2: ethernet-phy@09 { | ||
| 434 | reg = <0x09>; | ||
| 435 | }; | ||
| 436 | |||
| 437 | /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ | ||
| 438 | phy_eth3: ethernet-phy@0a { | ||
| 439 | reg = <0x0a>; | ||
| 440 | }; | ||
| 441 | |||
| 442 | /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ | ||
| 443 | phy_eth4: ethernet-phy@0b { | ||
| 444 | reg = <0x0b>; | ||
| 445 | }; | ||
| 446 | |||
| 447 | /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ | ||
| 448 | phy_estar1: ethernet-phy@10 { | ||
| 449 | interrupt-parent = <&ipic>; | ||
| 450 | interrupts = <17 0x8>; | ||
| 451 | reg = <0x10>; | ||
| 452 | }; | ||
| 453 | |||
| 454 | /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ | ||
| 455 | phy_estar2: ethernet-phy@11 { | ||
| 456 | interrupt-parent = <&ipic>; | ||
| 457 | interrupts = <18 0x8>; | ||
| 458 | reg = <0x11>; | ||
| 459 | }; | ||
| 460 | }; | ||
| 461 | |||
| 462 | qeic: interrupt-controller@80 { | ||
| 463 | interrupt-controller; | ||
| 464 | compatible = "fsl,qe-ic"; | ||
| 465 | #address-cells = <0>; | ||
| 466 | #interrupt-cells = <1>; | ||
| 467 | reg = <0x80 0x80>; | ||
| 468 | interrupts = <32 8 33 8>; | ||
| 469 | interrupt-parent = <&ipic>; | ||
| 470 | }; | ||
| 471 | }; | ||
| 472 | }; | ||
| 473 | |||
| 474 | localbus@e0005000 { | ||
| 475 | #address-cells = <2>; | ||
| 476 | #size-cells = <1>; | ||
| 477 | compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", | ||
| 478 | "simple-bus"; | ||
| 479 | reg = <0xe0005000 0xd8>; | ||
| 480 | ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ | ||
| 481 | |||
| 482 | flash@f0000000,0 { | ||
| 483 | compatible = "cfi-flash"; | ||
| 484 | /* | ||
| 485 | * The Intel P30 chip has 2 non-identical chips on | ||
| 486 | * one die, so we need to define 2 seperate regions | ||
| 487 | * that are scanned by physmap_of independantly. | ||
| 488 | */ | ||
| 489 | reg = <0 0x00000000 0x02000000 | ||
| 490 | 0 0x02000000 0x02000000>; /* Filled in by U-Boot */ | ||
| 491 | bank-width = <2>; | ||
| 492 | #address-cells = <1>; | ||
| 493 | #size-cells = <1>; | ||
| 494 | partition@0 { | ||
| 495 | label = "u-boot"; | ||
| 496 | reg = <0 0x40000>; | ||
| 497 | }; | ||
| 498 | partition@40000 { | ||
| 499 | label = "env"; | ||
| 500 | reg = <0x40000 0x40000>; | ||
| 501 | }; | ||
| 502 | partition@80000 { | ||
| 503 | label = "dtb"; | ||
| 504 | reg = <0x80000 0x20000>; | ||
| 505 | }; | ||
| 506 | partition@a0000 { | ||
| 507 | label = "kernel"; | ||
| 508 | reg = <0xa0000 0x300000>; | ||
| 509 | }; | ||
| 510 | partition@3a0000 { | ||
| 511 | label = "ramdisk"; | ||
| 512 | reg = <0x3a0000 0x800000>; | ||
| 513 | }; | ||
| 514 | partition@ba0000 { | ||
| 515 | label = "user"; | ||
| 516 | reg = <0xba0000 0x3460000>; | ||
| 517 | }; | ||
| 518 | }; | ||
| 519 | }; | ||
| 520 | }; | ||
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index c9cfd374bffb..bdb7fc0fa332 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts | |||
| @@ -56,6 +56,19 @@ | |||
| 56 | ranges = <0x00000000 0xfdf00000 0x00100000>; | 56 | ranges = <0x00000000 0xfdf00000 0x00100000>; |
| 57 | bus-frequency = <0>; /* Fixed by bootwrapper */ | 57 | bus-frequency = <0>; /* Fixed by bootwrapper */ |
| 58 | 58 | ||
| 59 | ecm-law@0 { | ||
| 60 | compatible = "fsl,ecm-law"; | ||
| 61 | reg = <0x0 0x1000>; | ||
| 62 | fsl,num-laws = <8>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | ecm@1000 { | ||
| 66 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | ||
| 67 | reg = <0x1000 0x1000>; | ||
| 68 | interrupts = <17 2>; | ||
| 69 | interrupt-parent = <&mpic>; | ||
| 70 | }; | ||
| 71 | |||
| 59 | memory-controller@2000 { | 72 | memory-controller@2000 { |
| 60 | compatible = "fsl,mpc8540-memory-controller"; | 73 | compatible = "fsl,mpc8540-memory-controller"; |
| 61 | reg = <0x2000 0x1000>; | 74 | reg = <0x2000 0x1000>; |
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts index 2a1929acaabd..60f332778e41 100644 --- a/arch/powerpc/boot/dts/mpc8272ads.dts +++ b/arch/powerpc/boot/dts/mpc8272ads.dts | |||
| @@ -17,6 +17,13 @@ | |||
| 17 | #address-cells = <1>; | 17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; | 18 | #size-cells = <1>; |
| 19 | 19 | ||
| 20 | aliases { | ||
| 21 | ethernet0 = ð0; | ||
| 22 | ethernet1 = ð1; | ||
| 23 | serial0 = &scc1; | ||
| 24 | serial1 = &scc4; | ||
| 25 | }; | ||
| 26 | |||
| 20 | cpus { | 27 | cpus { |
| 21 | #address-cells = <1>; | 28 | #address-cells = <1>; |
| 22 | #size-cells = <0>; | 29 | #size-cells = <0>; |
| @@ -46,13 +53,13 @@ | |||
| 46 | #size-cells = <1>; | 53 | #size-cells = <1>; |
| 47 | reg = <0xf0010100 0x40>; | 54 | reg = <0xf0010100 0x40>; |
| 48 | 55 | ||
| 49 | ranges = <0x0 0x0 0xfe000000 0x2000000 | 56 | ranges = <0x0 0x0 0xff800000 0x00800000 |
| 50 | 0x1 0x0 0xf4500000 0x8000 | 57 | 0x1 0x0 0xf4500000 0x8000 |
| 51 | 0x3 0x0 0xf8200000 0x8000>; | 58 | 0x3 0x0 0xf8200000 0x8000>; |
| 52 | 59 | ||
| 53 | flash@0,0 { | 60 | flash@0,0 { |
| 54 | compatible = "jedec-flash"; | 61 | compatible = "jedec-flash"; |
| 55 | reg = <0x0 0x0 0x2000000>; | 62 | reg = <0x0 0x0 0x00800000>; |
| 56 | bank-width = <4>; | 63 | bank-width = <4>; |
| 57 | device-width = <1>; | 64 | device-width = <1>; |
| 58 | }; | 65 | }; |
| @@ -144,7 +151,7 @@ | |||
| 144 | reg = <0x119f0 0x10 0x115f0 0x10>; | 151 | reg = <0x119f0 0x10 0x115f0 0x10>; |
| 145 | }; | 152 | }; |
| 146 | 153 | ||
| 147 | serial@11a00 { | 154 | scc1: serial@11a00 { |
| 148 | device_type = "serial"; | 155 | device_type = "serial"; |
| 149 | compatible = "fsl,mpc8272-scc-uart", | 156 | compatible = "fsl,mpc8272-scc-uart", |
| 150 | "fsl,cpm2-scc-uart"; | 157 | "fsl,cpm2-scc-uart"; |
| @@ -155,7 +162,7 @@ | |||
| 155 | fsl,cpm-command = <0x800000>; | 162 | fsl,cpm-command = <0x800000>; |
| 156 | }; | 163 | }; |
| 157 | 164 | ||
| 158 | serial@11a60 { | 165 | scc4: serial@11a60 { |
| 159 | device_type = "serial"; | 166 | device_type = "serial"; |
| 160 | compatible = "fsl,mpc8272-scc-uart", | 167 | compatible = "fsl,mpc8272-scc-uart", |
| 161 | "fsl,cpm2-scc-uart"; | 168 | "fsl,cpm2-scc-uart"; |
| @@ -192,7 +199,7 @@ | |||
| 192 | }; | 199 | }; |
| 193 | }; | 200 | }; |
| 194 | 201 | ||
| 195 | ethernet@11300 { | 202 | eth0: ethernet@11300 { |
| 196 | device_type = "network"; | 203 | device_type = "network"; |
| 197 | compatible = "fsl,mpc8272-fcc-enet", | 204 | compatible = "fsl,mpc8272-fcc-enet", |
| 198 | "fsl,cpm2-fcc-enet"; | 205 | "fsl,cpm2-fcc-enet"; |
| @@ -205,7 +212,7 @@ | |||
| 205 | fsl,cpm-command = <0x12000300>; | 212 | fsl,cpm-command = <0x12000300>; |
| 206 | }; | 213 | }; |
| 207 | 214 | ||
| 208 | ethernet@11320 { | 215 | eth1: ethernet@11320 { |
| 209 | device_type = "network"; | 216 | device_type = "network"; |
| 210 | compatible = "fsl,mpc8272-fcc-enet", | 217 | compatible = "fsl,mpc8272-fcc-enet", |
| 211 | "fsl,cpm2-fcc-enet"; | 218 | "fsl,cpm2-fcc-enet"; |
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index 3f4c5fb988a0..32e10f588c1d 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts | |||
| @@ -322,6 +322,21 @@ | |||
| 322 | reg = <0x700 0x100>; | 322 | reg = <0x700 0x100>; |
| 323 | device_type = "ipic"; | 323 | device_type = "ipic"; |
| 324 | }; | 324 | }; |
| 325 | |||
| 326 | ipic-msi@7c0 { | ||
| 327 | compatible = "fsl,ipic-msi"; | ||
| 328 | reg = <0x7c0 0x40>; | ||
| 329 | msi-available-ranges = <0 0x100>; | ||
| 330 | interrupts = <0x43 0x8 | ||
| 331 | 0x4 0x8 | ||
| 332 | 0x51 0x8 | ||
| 333 | 0x52 0x8 | ||
| 334 | 0x56 0x8 | ||
| 335 | 0x57 0x8 | ||
| 336 | 0x58 0x8 | ||
| 337 | 0x59 0x8>; | ||
| 338 | interrupt-parent = < &ipic >; | ||
| 339 | }; | ||
| 325 | }; | 340 | }; |
| 326 | 341 | ||
| 327 | pci0: pci@e0008500 { | 342 | pci0: pci@e0008500 { |
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 57c595bf1071..436c9c671dd9 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts | |||
| @@ -249,6 +249,8 @@ | |||
| 249 | reg = <0xe0100000 0x480>; | 249 | reg = <0xe0100000 0x480>; |
| 250 | brg-frequency = <0>; | 250 | brg-frequency = <0>; |
| 251 | bus-frequency = <198000000>; | 251 | bus-frequency = <198000000>; |
| 252 | fsl,qe-num-riscs = <1>; | ||
| 253 | fsl,qe-num-snums = <28>; | ||
| 252 | 254 | ||
| 253 | muram@10000 { | 255 | muram@10000 { |
| 254 | #address-cells = <1>; | 256 | #address-cells = <1>; |
| @@ -369,7 +371,6 @@ | |||
| 369 | }; | 371 | }; |
| 370 | 372 | ||
| 371 | pci0: pci@e0008500 { | 373 | pci0: pci@e0008500 { |
| 372 | cell-index = <1>; | ||
| 373 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 374 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 374 | interrupt-map = < | 375 | interrupt-map = < |
| 375 | /* IDSEL 0x11 AD17 */ | 376 | /* IDSEL 0x11 AD17 */ |
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 4319bd70a580..9a0952f74b81 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts | |||
| @@ -221,6 +221,8 @@ | |||
| 221 | reg = <0xe0100000 0x480>; | 221 | reg = <0xe0100000 0x480>; |
| 222 | brg-frequency = <0>; | 222 | brg-frequency = <0>; |
| 223 | bus-frequency = <198000000>; | 223 | bus-frequency = <198000000>; |
| 224 | fsl,qe-num-riscs = <1>; | ||
| 225 | fsl,qe-num-snums = <28>; | ||
| 224 | 226 | ||
| 225 | muram@10000 { | 227 | muram@10000 { |
| 226 | #address-cells = <1>; | 228 | #address-cells = <1>; |
| @@ -327,7 +329,6 @@ | |||
| 327 | }; | 329 | }; |
| 328 | 330 | ||
| 329 | pci0: pci@e0008500 { | 331 | pci0: pci@e0008500 { |
| 330 | cell-index = <1>; | ||
| 331 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 332 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 332 | interrupt-map = < | 333 | interrupt-map = < |
| 333 | /* IDSEL 0x10 AD16 (USB) */ | 334 | /* IDSEL 0x10 AD16 (USB) */ |
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 1ae38f0ddef8..feeeb7f9d609 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts | |||
| @@ -156,7 +156,7 @@ | |||
| 156 | interrupt-parent = <&ipic>; | 156 | interrupt-parent = <&ipic>; |
| 157 | interrupts = <39 0x8>; | 157 | interrupts = <39 0x8>; |
| 158 | phy_type = "ulpi"; | 158 | phy_type = "ulpi"; |
| 159 | port1; | 159 | port0; |
| 160 | }; | 160 | }; |
| 161 | 161 | ||
| 162 | usb@23000 { | 162 | usb@23000 { |
| @@ -278,7 +278,6 @@ | |||
| 278 | }; | 278 | }; |
| 279 | 279 | ||
| 280 | pci0: pci@e0008500 { | 280 | pci0: pci@e0008500 { |
| 281 | cell-index = <1>; | ||
| 282 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 281 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 283 | interrupt-map = < | 282 | interrupt-map = < |
| 284 | /* IDSEL 0x10 - SATA */ | 283 | /* IDSEL 0x10 - SATA */ |
| @@ -301,7 +300,6 @@ | |||
| 301 | }; | 300 | }; |
| 302 | 301 | ||
| 303 | pci1: pci@e0008600 { | 302 | pci1: pci@e0008600 { |
| 304 | cell-index = <2>; | ||
| 305 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 303 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 306 | interrupt-map = < | 304 | interrupt-map = < |
| 307 | /* IDSEL 0x0E - MiniPCI Slot */ | 305 | /* IDSEL 0x0E - MiniPCI Slot */ |
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index 662abe1fb804..eb732115f016 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts | |||
| @@ -227,7 +227,6 @@ | |||
| 227 | }; | 227 | }; |
| 228 | 228 | ||
| 229 | pci0: pci@e0008600 { | 229 | pci0: pci@e0008600 { |
| 230 | cell-index = <2>; | ||
| 231 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 230 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 232 | interrupt-map = < | 231 | interrupt-map = < |
| 233 | /* IDSEL 0x0F - PCI Slot */ | 232 | /* IDSEL 0x0F - PCI Slot */ |
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index d9f0a2325fa4..230febb9b72f 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts | |||
| @@ -153,7 +153,7 @@ | |||
| 153 | interrupt-parent = <&ipic>; | 153 | interrupt-parent = <&ipic>; |
| 154 | interrupts = <39 0x8>; | 154 | interrupts = <39 0x8>; |
| 155 | phy_type = "ulpi"; | 155 | phy_type = "ulpi"; |
| 156 | port1; | 156 | port0; |
| 157 | }; | 157 | }; |
| 158 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ | 158 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ |
| 159 | usb@23000 { | 159 | usb@23000 { |
| @@ -286,7 +286,6 @@ | |||
| 286 | }; | 286 | }; |
| 287 | 287 | ||
| 288 | pci0: pci@e0008500 { | 288 | pci0: pci@e0008500 { |
| 289 | cell-index = <1>; | ||
| 290 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 289 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 291 | interrupt-map = < | 290 | interrupt-map = < |
| 292 | 291 | ||
| @@ -348,7 +347,6 @@ | |||
| 348 | }; | 347 | }; |
| 349 | 348 | ||
| 350 | pci1: pci@e0008600 { | 349 | pci1: pci@e0008600 { |
| 351 | cell-index = <2>; | ||
| 352 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 350 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 353 | interrupt-map = < | 351 | interrupt-map = < |
| 354 | 352 | ||
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 6e34f170fa62..39ff4c829caf 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts | |||
| @@ -289,6 +289,8 @@ | |||
| 289 | reg = <0xe0100000 0x480>; | 289 | reg = <0xe0100000 0x480>; |
| 290 | brg-frequency = <0>; | 290 | brg-frequency = <0>; |
| 291 | bus-frequency = <396000000>; | 291 | bus-frequency = <396000000>; |
| 292 | fsl,qe-num-riscs = <2>; | ||
| 293 | fsl,qe-num-snums = <28>; | ||
| 292 | 294 | ||
| 293 | muram@10000 { | 295 | muram@10000 { |
| 294 | #address-cells = <1>; | 296 | #address-cells = <1>; |
| @@ -410,7 +412,6 @@ | |||
| 410 | }; | 412 | }; |
| 411 | 413 | ||
| 412 | pci0: pci@e0008500 { | 414 | pci0: pci@e0008500 { |
| 413 | cell-index = <1>; | ||
| 414 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 415 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 415 | interrupt-map = < | 416 | interrupt-map = < |
| 416 | 417 | ||
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts index 37b789510d68..6315d6fcc58a 100644 --- a/arch/powerpc/boot/dts/mpc836x_rdk.dts +++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts | |||
| @@ -198,6 +198,8 @@ | |||
| 198 | clock-frequency = <0>; | 198 | clock-frequency = <0>; |
| 199 | bus-frequency = <0>; | 199 | bus-frequency = <0>; |
| 200 | brg-frequency = <0>; | 200 | brg-frequency = <0>; |
| 201 | fsl,qe-num-riscs = <2>; | ||
| 202 | fsl,qe-num-snums = <28>; | ||
| 201 | 203 | ||
| 202 | muram@10000 { | 204 | muram@10000 { |
| 203 | #address-cells = <1>; | 205 | #address-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 963708017e6c..f32c2811c6d9 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts | |||
| @@ -155,7 +155,7 @@ | |||
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | sdhci@2e000 { | 157 | sdhci@2e000 { |
| 158 | compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc"; | 158 | compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; |
| 159 | reg = <0x2e000 0x1000>; | 159 | reg = <0x2e000 0x1000>; |
| 160 | interrupts = <42 0x8>; | 160 | interrupts = <42 0x8>; |
| 161 | interrupt-parent = <&ipic>; | 161 | interrupt-parent = <&ipic>; |
| @@ -383,7 +383,6 @@ | |||
| 383 | }; | 383 | }; |
| 384 | 384 | ||
| 385 | pci0: pci@e0008500 { | 385 | pci0: pci@e0008500 { |
| 386 | cell-index = <0>; | ||
| 387 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 386 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 388 | interrupt-map = < | 387 | interrupt-map = < |
| 389 | 388 | ||
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 053339390c22..224b4f0704b8 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts | |||
| @@ -169,7 +169,7 @@ | |||
| 169 | }; | 169 | }; |
| 170 | 170 | ||
| 171 | sdhci@2e000 { | 171 | sdhci@2e000 { |
| 172 | compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc"; | 172 | compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; |
| 173 | reg = <0x2e000 0x1000>; | 173 | reg = <0x2e000 0x1000>; |
| 174 | interrupts = <42 0x8>; | 174 | interrupts = <42 0x8>; |
| 175 | interrupt-parent = <&ipic>; | 175 | interrupt-parent = <&ipic>; |
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 651ff2f9db2d..f720ab9af30d 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts | |||
| @@ -155,7 +155,7 @@ | |||
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | sdhci@2e000 { | 157 | sdhci@2e000 { |
| 158 | compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; | 158 | compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; |
| 159 | reg = <0x2e000 0x1000>; | 159 | reg = <0x2e000 0x1000>; |
| 160 | interrupts = <42 0x8>; | 160 | interrupts = <42 0x8>; |
| 161 | interrupt-parent = <&ipic>; | 161 | interrupt-parent = <&ipic>; |
| @@ -367,7 +367,6 @@ | |||
| 367 | }; | 367 | }; |
| 368 | 368 | ||
| 369 | pci0: pci@e0008500 { | 369 | pci0: pci@e0008500 { |
| 370 | cell-index = <0>; | ||
| 371 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 370 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 372 | interrupt-map = < | 371 | interrupt-map = < |
| 373 | 372 | ||
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 5d90e85704c3..474ea2fa3f86 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts | |||
| @@ -169,7 +169,7 @@ | |||
| 169 | }; | 169 | }; |
| 170 | 170 | ||
| 171 | sdhci@2e000 { | 171 | sdhci@2e000 { |
| 172 | compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; | 172 | compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; |
| 173 | reg = <0x2e000 0x1000>; | 173 | reg = <0x2e000 0x1000>; |
| 174 | interrupts = <42 0x8>; | 174 | interrupts = <42 0x8>; |
| 175 | interrupt-parent = <&ipic>; | 175 | interrupt-parent = <&ipic>; |
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index d6f208b8297a..4fa221fd9bdc 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts | |||
| @@ -153,7 +153,7 @@ | |||
| 153 | }; | 153 | }; |
| 154 | 154 | ||
| 155 | sdhci@2e000 { | 155 | sdhci@2e000 { |
| 156 | compatible = "fsl,mpc8379-esdhc"; | 156 | compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; |
| 157 | reg = <0x2e000 0x1000>; | 157 | reg = <0x2e000 0x1000>; |
| 158 | interrupts = <42 0x8>; | 158 | interrupts = <42 0x8>; |
| 159 | interrupt-parent = <&ipic>; | 159 | interrupt-parent = <&ipic>; |
| @@ -397,7 +397,6 @@ | |||
| 397 | }; | 397 | }; |
| 398 | 398 | ||
| 399 | pci0: pci@e0008500 { | 399 | pci0: pci@e0008500 { |
| 400 | cell-index = <0>; | ||
| 401 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 400 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 402 | interrupt-map = < | 401 | interrupt-map = < |
| 403 | 402 | ||
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index 98ae95bd18f4..d4838af8d379 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts | |||
| @@ -167,7 +167,7 @@ | |||
| 167 | }; | 167 | }; |
| 168 | 168 | ||
| 169 | sdhci@2e000 { | 169 | sdhci@2e000 { |
| 170 | compatible = "fsl,mpc8379-esdhc"; | 170 | compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; |
| 171 | reg = <0x2e000 0x1000>; | 171 | reg = <0x2e000 0x1000>; |
| 172 | interrupts = <42 0x8>; | 172 | interrupts = <42 0x8>; |
| 173 | interrupt-parent = <&ipic>; | 173 | interrupt-parent = <&ipic>; |
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index b31c5041350b..e781ad2f1f8a 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts | |||
| @@ -51,9 +51,21 @@ | |||
| 51 | device_type = "soc"; | 51 | device_type = "soc"; |
| 52 | compatible = "simple-bus"; | 52 | compatible = "simple-bus"; |
| 53 | ranges = <0x0 0xffe00000 0x100000>; | 53 | ranges = <0x0 0xffe00000 0x100000>; |
| 54 | reg = <0xffe00000 0x1000>; | ||
| 55 | bus-frequency = <0>; // Filled out by uboot. | 54 | bus-frequency = <0>; // Filled out by uboot. |
| 56 | 55 | ||
| 56 | ecm-law@0 { | ||
| 57 | compatible = "fsl,ecm-law"; | ||
| 58 | reg = <0x0 0x1000>; | ||
| 59 | fsl,num-laws = <12>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | ecm@1000 { | ||
| 63 | compatible = "fsl,mpc8536-ecm", "fsl,ecm"; | ||
| 64 | reg = <0x1000 0x1000>; | ||
| 65 | interrupts = <17 2>; | ||
| 66 | interrupt-parent = <&mpic>; | ||
| 67 | }; | ||
| 68 | |||
| 57 | memory-controller@2000 { | 69 | memory-controller@2000 { |
| 58 | compatible = "fsl,mpc8536-memory-controller"; | 70 | compatible = "fsl,mpc8536-memory-controller"; |
| 59 | reg = <0x2000 0x1000>; | 71 | reg = <0x2000 0x1000>; |
| @@ -321,7 +333,6 @@ | |||
| 321 | }; | 333 | }; |
| 322 | 334 | ||
| 323 | pci0: pci@ffe08000 { | 335 | pci0: pci@ffe08000 { |
| 324 | cell-index = <0>; | ||
| 325 | compatible = "fsl,mpc8540-pci"; | 336 | compatible = "fsl,mpc8540-pci"; |
| 326 | device_type = "pci"; | 337 | device_type = "pci"; |
| 327 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 338 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| @@ -346,7 +357,6 @@ | |||
| 346 | }; | 357 | }; |
| 347 | 358 | ||
| 348 | pci1: pcie@ffe09000 { | 359 | pci1: pcie@ffe09000 { |
| 349 | cell-index = <1>; | ||
| 350 | compatible = "fsl,mpc8548-pcie"; | 360 | compatible = "fsl,mpc8548-pcie"; |
| 351 | device_type = "pci"; | 361 | device_type = "pci"; |
| 352 | #interrupt-cells = <1>; | 362 | #interrupt-cells = <1>; |
| @@ -383,7 +393,6 @@ | |||
| 383 | }; | 393 | }; |
| 384 | 394 | ||
| 385 | pci2: pcie@ffe0a000 { | 395 | pci2: pcie@ffe0a000 { |
| 386 | cell-index = <2>; | ||
| 387 | compatible = "fsl,mpc8548-pcie"; | 396 | compatible = "fsl,mpc8548-pcie"; |
| 388 | device_type = "pci"; | 397 | device_type = "pci"; |
| 389 | #interrupt-cells = <1>; | 398 | #interrupt-cells = <1>; |
| @@ -420,7 +429,6 @@ | |||
| 420 | }; | 429 | }; |
| 421 | 430 | ||
| 422 | pci3: pcie@ffe0b000 { | 431 | pci3: pcie@ffe0b000 { |
| 423 | cell-index = <3>; | ||
| 424 | compatible = "fsl,mpc8548-pcie"; | 432 | compatible = "fsl,mpc8548-pcie"; |
| 425 | device_type = "pci"; | 433 | device_type = "pci"; |
| 426 | #interrupt-cells = <1>; | 434 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index ddd67be10b03..9dc292962a9a 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts | |||
| @@ -55,9 +55,21 @@ | |||
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | compatible = "simple-bus"; | 56 | compatible = "simple-bus"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x100000>; // CCSRBAR 1M | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | 59 | ||
| 60 | ecm-law@0 { | ||
| 61 | compatible = "fsl,ecm-law"; | ||
| 62 | reg = <0x0 0x1000>; | ||
| 63 | fsl,num-laws = <8>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | ecm@1000 { | ||
| 67 | compatible = "fsl,mpc8540-ecm", "fsl,ecm"; | ||
| 68 | reg = <0x1000 0x1000>; | ||
| 69 | interrupts = <17 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | memory-controller@2000 { | 73 | memory-controller@2000 { |
| 62 | compatible = "fsl,8540-memory-controller"; | 74 | compatible = "fsl,8540-memory-controller"; |
| 63 | reg = <0x2000 0x1000>; | 75 | reg = <0x2000 0x1000>; |
| @@ -258,7 +270,6 @@ | |||
| 258 | }; | 270 | }; |
| 259 | 271 | ||
| 260 | pci0: pci@e0008000 { | 272 | pci0: pci@e0008000 { |
| 261 | cell-index = <0>; | ||
| 262 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 273 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 263 | interrupt-map = < | 274 | interrupt-map = < |
| 264 | 275 | ||
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index e45097f44fbd..9a3ad311aedf 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts | |||
| @@ -55,9 +55,21 @@ | |||
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | compatible = "simple-bus"; | 56 | compatible = "simple-bus"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x1000>; // CCSRBAR 1M | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | 59 | ||
| 60 | ecm-law@0 { | ||
| 61 | compatible = "fsl,ecm-law"; | ||
| 62 | reg = <0x0 0x1000>; | ||
| 63 | fsl,num-laws = <8>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | ecm@1000 { | ||
| 67 | compatible = "fsl,mpc8541-ecm", "fsl,ecm"; | ||
| 68 | reg = <0x1000 0x1000>; | ||
| 69 | interrupts = <17 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | memory-controller@2000 { | 73 | memory-controller@2000 { |
| 62 | compatible = "fsl,8541-memory-controller"; | 74 | compatible = "fsl,8541-memory-controller"; |
| 63 | reg = <0x2000 0x1000>; | 75 | reg = <0x2000 0x1000>; |
| @@ -272,7 +284,6 @@ | |||
| 272 | }; | 284 | }; |
| 273 | 285 | ||
| 274 | pci0: pci@e0008000 { | 286 | pci0: pci@e0008000 { |
| 275 | cell-index = <0>; | ||
| 276 | interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; | 287 | interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; |
| 277 | interrupt-map = < | 288 | interrupt-map = < |
| 278 | 289 | ||
| @@ -344,7 +355,6 @@ | |||
| 344 | }; | 355 | }; |
| 345 | 356 | ||
| 346 | pci1: pci@e0009000 { | 357 | pci1: pci@e0009000 { |
| 347 | cell-index = <1>; | ||
| 348 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 358 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 349 | interrupt-map = < | 359 | interrupt-map = < |
| 350 | 360 | ||
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 7c6932be0197..98e94b465662 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts | |||
| @@ -57,9 +57,21 @@ | |||
| 57 | compatible = "simple-bus"; | 57 | compatible = "simple-bus"; |
| 58 | 58 | ||
| 59 | ranges = <0x0 0xe0000000 0x100000>; | 59 | ranges = <0x0 0xe0000000 0x100000>; |
| 60 | reg = <0xe0000000 0x1000>; // CCSRBAR 1M | ||
| 61 | bus-frequency = <0>; // Filled out by uboot. | 60 | bus-frequency = <0>; // Filled out by uboot. |
| 62 | 61 | ||
| 62 | ecm-law@0 { | ||
| 63 | compatible = "fsl,ecm-law"; | ||
| 64 | reg = <0x0 0x1000>; | ||
| 65 | fsl,num-laws = <10>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | ecm@1000 { | ||
| 69 | compatible = "fsl,mpc8544-ecm", "fsl,ecm"; | ||
| 70 | reg = <0x1000 0x1000>; | ||
| 71 | interrupts = <17 2>; | ||
| 72 | interrupt-parent = <&mpic>; | ||
| 73 | }; | ||
| 74 | |||
| 63 | memory-controller@2000 { | 75 | memory-controller@2000 { |
| 64 | compatible = "fsl,8544-memory-controller"; | 76 | compatible = "fsl,8544-memory-controller"; |
| 65 | reg = <0x2000 0x1000>; | 77 | reg = <0x2000 0x1000>; |
| @@ -274,7 +286,6 @@ | |||
| 274 | }; | 286 | }; |
| 275 | 287 | ||
| 276 | pci0: pci@e0008000 { | 288 | pci0: pci@e0008000 { |
| 277 | cell-index = <0>; | ||
| 278 | compatible = "fsl,mpc8540-pci"; | 289 | compatible = "fsl,mpc8540-pci"; |
| 279 | device_type = "pci"; | 290 | device_type = "pci"; |
| 280 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 291 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| @@ -306,7 +317,6 @@ | |||
| 306 | }; | 317 | }; |
| 307 | 318 | ||
| 308 | pci1: pcie@e0009000 { | 319 | pci1: pcie@e0009000 { |
| 309 | cell-index = <1>; | ||
| 310 | compatible = "fsl,mpc8548-pcie"; | 320 | compatible = "fsl,mpc8548-pcie"; |
| 311 | device_type = "pci"; | 321 | device_type = "pci"; |
| 312 | #interrupt-cells = <1>; | 322 | #interrupt-cells = <1>; |
| @@ -343,7 +353,6 @@ | |||
| 343 | }; | 353 | }; |
| 344 | 354 | ||
| 345 | pci2: pcie@e000a000 { | 355 | pci2: pcie@e000a000 { |
| 346 | cell-index = <2>; | ||
| 347 | compatible = "fsl,mpc8548-pcie"; | 356 | compatible = "fsl,mpc8548-pcie"; |
| 348 | device_type = "pci"; | 357 | device_type = "pci"; |
| 349 | #interrupt-cells = <1>; | 358 | #interrupt-cells = <1>; |
| @@ -380,7 +389,6 @@ | |||
| 380 | }; | 389 | }; |
| 381 | 390 | ||
| 382 | pci3: pcie@e000b000 { | 391 | pci3: pcie@e000b000 { |
| 383 | cell-index = <3>; | ||
| 384 | compatible = "fsl,mpc8548-pcie"; | 392 | compatible = "fsl,mpc8548-pcie"; |
| 385 | device_type = "pci"; | 393 | device_type = "pci"; |
| 386 | #interrupt-cells = <1>; | 394 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 804e90353293..475be1433fe1 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts | |||
| @@ -60,9 +60,21 @@ | |||
| 60 | device_type = "soc"; | 60 | device_type = "soc"; |
| 61 | compatible = "simple-bus"; | 61 | compatible = "simple-bus"; |
| 62 | ranges = <0x0 0xe0000000 0x100000>; | 62 | ranges = <0x0 0xe0000000 0x100000>; |
| 63 | reg = <0xe0000000 0x1000>; // CCSRBAR | ||
| 64 | bus-frequency = <0>; | 63 | bus-frequency = <0>; |
| 65 | 64 | ||
| 65 | ecm-law@0 { | ||
| 66 | compatible = "fsl,ecm-law"; | ||
| 67 | reg = <0x0 0x1000>; | ||
| 68 | fsl,num-laws = <10>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | ecm@1000 { | ||
| 72 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 73 | reg = <0x1000 0x1000>; | ||
| 74 | interrupts = <17 2>; | ||
| 75 | interrupt-parent = <&mpic>; | ||
| 76 | }; | ||
| 77 | |||
| 66 | memory-controller@2000 { | 78 | memory-controller@2000 { |
| 67 | compatible = "fsl,8548-memory-controller"; | 79 | compatible = "fsl,8548-memory-controller"; |
| 68 | reg = <0x2000 0x1000>; | 80 | reg = <0x2000 0x1000>; |
| @@ -328,7 +340,6 @@ | |||
| 328 | }; | 340 | }; |
| 329 | 341 | ||
| 330 | pci0: pci@e0008000 { | 342 | pci0: pci@e0008000 { |
| 331 | cell-index = <0>; | ||
| 332 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 343 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 333 | interrupt-map = < | 344 | interrupt-map = < |
| 334 | /* IDSEL 0x4 (PCIX Slot 2) */ | 345 | /* IDSEL 0x4 (PCIX Slot 2) */ |
| @@ -478,7 +489,6 @@ | |||
| 478 | }; | 489 | }; |
| 479 | 490 | ||
| 480 | pci1: pci@e0009000 { | 491 | pci1: pci@e0009000 { |
| 481 | cell-index = <1>; | ||
| 482 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 492 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 483 | interrupt-map = < | 493 | interrupt-map = < |
| 484 | 494 | ||
| @@ -503,7 +513,6 @@ | |||
| 503 | }; | 513 | }; |
| 504 | 514 | ||
| 505 | pci2: pcie@e000a000 { | 515 | pci2: pcie@e000a000 { |
| 506 | cell-index = <2>; | ||
| 507 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 516 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 508 | interrupt-map = < | 517 | interrupt-map = < |
| 509 | 518 | ||
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 9484f0729b10..065b2f093de2 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts | |||
| @@ -55,9 +55,21 @@ | |||
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | compatible = "simple-bus"; | 56 | compatible = "simple-bus"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x1000>; // CCSRBAR 1M | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | 59 | ||
| 60 | ecm-law@0 { | ||
| 61 | compatible = "fsl,ecm-law"; | ||
| 62 | reg = <0x0 0x1000>; | ||
| 63 | fsl,num-laws = <8>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | ecm@1000 { | ||
| 67 | compatible = "fsl,mpc8555-ecm", "fsl,ecm"; | ||
| 68 | reg = <0x1000 0x1000>; | ||
| 69 | interrupts = <17 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | memory-controller@2000 { | 73 | memory-controller@2000 { |
| 62 | compatible = "fsl,8555-memory-controller"; | 74 | compatible = "fsl,8555-memory-controller"; |
| 63 | reg = <0x2000 0x1000>; | 75 | reg = <0x2000 0x1000>; |
| @@ -272,7 +284,6 @@ | |||
| 272 | }; | 284 | }; |
| 273 | 285 | ||
| 274 | pci0: pci@e0008000 { | 286 | pci0: pci@e0008000 { |
| 275 | cell-index = <0>; | ||
| 276 | interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; | 287 | interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; |
| 277 | interrupt-map = < | 288 | interrupt-map = < |
| 278 | 289 | ||
| @@ -344,7 +355,6 @@ | |||
| 344 | }; | 355 | }; |
| 345 | 356 | ||
| 346 | pci1: pci@e0009000 { | 357 | pci1: pci@e0009000 { |
| 347 | cell-index = <1>; | ||
| 348 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 358 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 349 | interrupt-map = < | 359 | interrupt-map = < |
| 350 | 360 | ||
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index cc2acf87d02f..a5bb1ec70a5a 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts | |||
| @@ -55,9 +55,21 @@ | |||
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | compatible = "simple-bus"; | 56 | compatible = "simple-bus"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x200>; | ||
| 59 | bus-frequency = <330000000>; | 58 | bus-frequency = <330000000>; |
| 60 | 59 | ||
| 60 | ecm-law@0 { | ||
| 61 | compatible = "fsl,ecm-law"; | ||
| 62 | reg = <0x0 0x1000>; | ||
| 63 | fsl,num-laws = <8>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | ecm@1000 { | ||
| 67 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | ||
| 68 | reg = <0x1000 0x1000>; | ||
| 69 | interrupts = <17 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | memory-controller@2000 { | 73 | memory-controller@2000 { |
| 62 | compatible = "fsl,8540-memory-controller"; | 74 | compatible = "fsl,8540-memory-controller"; |
| 63 | reg = <0x2000 0x1000>; | 75 | reg = <0x2000 0x1000>; |
| @@ -291,7 +303,6 @@ | |||
| 291 | }; | 303 | }; |
| 292 | 304 | ||
| 293 | pci0: pci@e0008000 { | 305 | pci0: pci@e0008000 { |
| 294 | cell-index = <0>; | ||
| 295 | #interrupt-cells = <1>; | 306 | #interrupt-cells = <1>; |
| 296 | #size-cells = <2>; | 307 | #size-cells = <2>; |
| 297 | #address-cells = <3>; | 308 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 9d52e3b25047..00c2bbda7013 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | serial1 = &serial1; | 26 | serial1 = &serial1; |
| 27 | pci0 = &pci0; | 27 | pci0 = &pci0; |
| 28 | pci1 = &pci1; | 28 | pci1 = &pci1; |
| 29 | rapidio0 = &rio0; | ||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | cpus { | 32 | cpus { |
| @@ -62,9 +63,21 @@ | |||
| 62 | device_type = "soc"; | 63 | device_type = "soc"; |
| 63 | compatible = "simple-bus"; | 64 | compatible = "simple-bus"; |
| 64 | ranges = <0x0 0xe0000000 0x100000>; | 65 | ranges = <0x0 0xe0000000 0x100000>; |
| 65 | reg = <0xe0000000 0x1000>; | ||
| 66 | bus-frequency = <0>; | 66 | bus-frequency = <0>; |
| 67 | 67 | ||
| 68 | ecm-law@0 { | ||
| 69 | compatible = "fsl,ecm-law"; | ||
| 70 | reg = <0x0 0x1000>; | ||
| 71 | fsl,num-laws = <10>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | ecm@1000 { | ||
| 75 | compatible = "fsl,mpc8568-ecm", "fsl,ecm"; | ||
| 76 | reg = <0x1000 0x1000>; | ||
| 77 | interrupts = <17 2>; | ||
| 78 | interrupt-parent = <&mpic>; | ||
| 79 | }; | ||
| 80 | |||
| 68 | memory-controller@2000 { | 81 | memory-controller@2000 { |
| 69 | compatible = "fsl,8568-memory-controller"; | 82 | compatible = "fsl,8568-memory-controller"; |
| 70 | reg = <0x2000 0x1000>; | 83 | reg = <0x2000 0x1000>; |
| @@ -275,6 +288,22 @@ | |||
| 275 | device_type = "open-pic"; | 288 | device_type = "open-pic"; |
| 276 | }; | 289 | }; |
| 277 | 290 | ||
| 291 | msi@41600 { | ||
| 292 | compatible = "fsl,mpc8568-msi", "fsl,mpic-msi"; | ||
| 293 | reg = <0x41600 0x80>; | ||
| 294 | msi-available-ranges = <0 0x100>; | ||
| 295 | interrupts = < | ||
| 296 | 0xe0 0 | ||
| 297 | 0xe1 0 | ||
| 298 | 0xe2 0 | ||
| 299 | 0xe3 0 | ||
| 300 | 0xe4 0 | ||
| 301 | 0xe5 0 | ||
| 302 | 0xe6 0 | ||
| 303 | 0xe7 0>; | ||
| 304 | interrupt-parent = <&mpic>; | ||
| 305 | }; | ||
| 306 | |||
| 278 | par_io@e0100 { | 307 | par_io@e0100 { |
| 279 | reg = <0xe0100 0x100>; | 308 | reg = <0xe0100 0x100>; |
| 280 | device_type = "par_io"; | 309 | device_type = "par_io"; |
| @@ -349,6 +378,8 @@ | |||
| 349 | reg = <0xe0080000 0x480>; | 378 | reg = <0xe0080000 0x480>; |
| 350 | brg-frequency = <0>; | 379 | brg-frequency = <0>; |
| 351 | bus-frequency = <396000000>; | 380 | bus-frequency = <396000000>; |
| 381 | fsl,qe-num-riscs = <2>; | ||
| 382 | fsl,qe-num-snums = <28>; | ||
| 352 | 383 | ||
| 353 | muram@10000 { | 384 | muram@10000 { |
| 354 | #address-cells = <1>; | 385 | #address-cells = <1>; |
| @@ -459,7 +490,6 @@ | |||
| 459 | }; | 490 | }; |
| 460 | 491 | ||
| 461 | pci0: pci@e0008000 { | 492 | pci0: pci@e0008000 { |
| 462 | cell-index = <0>; | ||
| 463 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 493 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 464 | interrupt-map = < | 494 | interrupt-map = < |
| 465 | /* IDSEL 0x12 AD18 */ | 495 | /* IDSEL 0x12 AD18 */ |
| @@ -490,7 +520,6 @@ | |||
| 490 | 520 | ||
| 491 | /* PCI Express */ | 521 | /* PCI Express */ |
| 492 | pci1: pcie@e000a000 { | 522 | pci1: pcie@e000a000 { |
| 493 | cell-index = <2>; | ||
| 494 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 523 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 495 | interrupt-map = < | 524 | interrupt-map = < |
| 496 | 525 | ||
| @@ -526,4 +555,20 @@ | |||
| 526 | 0x0 0x800000>; | 555 | 0x0 0x800000>; |
| 527 | }; | 556 | }; |
| 528 | }; | 557 | }; |
| 558 | |||
| 559 | rio0: rapidio@e00c00000 { | ||
| 560 | #address-cells = <2>; | ||
| 561 | #size-cells = <2>; | ||
| 562 | compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; | ||
| 563 | reg = <0xe00c0000 0x20000>; | ||
| 564 | ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; | ||
| 565 | interrupts = <48 2 /* error */ | ||
| 566 | 49 2 /* bell_outb */ | ||
| 567 | 50 2 /* bell_inb */ | ||
| 568 | 53 2 /* msg1_tx */ | ||
| 569 | 54 2 /* msg1_rx */ | ||
| 570 | 55 2 /* msg2_tx */ | ||
| 571 | 56 2 /* msg2_rx */>; | ||
| 572 | interrupt-parent = <&mpic>; | ||
| 573 | }; | ||
| 529 | }; | 574 | }; |
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts new file mode 100644 index 000000000000..a8dcb018c4a5 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8569mds.dts | |||
| @@ -0,0 +1,668 @@ | |||
| 1 | /* | ||
| 2 | * MPC8569E MDS Device Tree Source | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Freescale Semiconductor Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "MPC8569EMDS"; | ||
| 16 | compatible = "fsl,MPC8569EMDS"; | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <1>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | serial0 = &serial0; | ||
| 22 | serial1 = &serial1; | ||
| 23 | ethernet0 = &enet0; | ||
| 24 | ethernet1 = &enet1; | ||
| 25 | ethernet2 = &enet2; | ||
| 26 | ethernet3 = &enet3; | ||
| 27 | ethernet5 = &enet5; | ||
| 28 | ethernet7 = &enet7; | ||
| 29 | pci1 = &pci1; | ||
| 30 | rapidio0 = &rio0; | ||
| 31 | }; | ||
| 32 | |||
| 33 | cpus { | ||
| 34 | #address-cells = <1>; | ||
| 35 | #size-cells = <0>; | ||
| 36 | |||
| 37 | PowerPC,8569@0 { | ||
| 38 | device_type = "cpu"; | ||
| 39 | reg = <0x0>; | ||
| 40 | d-cache-line-size = <32>; // 32 bytes | ||
| 41 | i-cache-line-size = <32>; // 32 bytes | ||
| 42 | d-cache-size = <0x8000>; // L1, 32K | ||
| 43 | i-cache-size = <0x8000>; // L1, 32K | ||
| 44 | timebase-frequency = <0>; | ||
| 45 | bus-frequency = <0>; | ||
| 46 | clock-frequency = <0>; | ||
| 47 | next-level-cache = <&L2>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | memory { | ||
| 52 | device_type = "memory"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | localbus@e0005000 { | ||
| 56 | #address-cells = <2>; | ||
| 57 | #size-cells = <1>; | ||
| 58 | compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; | ||
| 59 | reg = <0xe0005000 0x1000>; | ||
| 60 | interrupts = <19 2>; | ||
| 61 | interrupt-parent = <&mpic>; | ||
| 62 | |||
| 63 | ranges = <0x0 0x0 0xfe000000 0x02000000 | ||
| 64 | 0x1 0x0 0xf8000000 0x00008000 | ||
| 65 | 0x2 0x0 0xf0000000 0x04000000 | ||
| 66 | 0x3 0x0 0xfc000000 0x00008000 | ||
| 67 | 0x4 0x0 0xf8008000 0x00008000 | ||
| 68 | 0x5 0x0 0xf8010000 0x00008000>; | ||
| 69 | |||
| 70 | nor@0,0 { | ||
| 71 | #address-cells = <1>; | ||
| 72 | #size-cells = <1>; | ||
| 73 | compatible = "cfi-flash"; | ||
| 74 | reg = <0x0 0x0 0x02000000>; | ||
| 75 | bank-width = <1>; | ||
| 76 | device-width = <1>; | ||
| 77 | partition@0 { | ||
| 78 | label = "ramdisk"; | ||
| 79 | reg = <0x00000000 0x01c00000>; | ||
| 80 | }; | ||
| 81 | partition@1c00000 { | ||
| 82 | label = "kernel"; | ||
| 83 | reg = <0x01c00000 0x002e0000>; | ||
| 84 | }; | ||
| 85 | partiton@1ee0000 { | ||
| 86 | label = "dtb"; | ||
| 87 | reg = <0x01ee0000 0x00020000>; | ||
| 88 | }; | ||
| 89 | partition@1f00000 { | ||
| 90 | label = "firmware"; | ||
| 91 | reg = <0x01f00000 0x00080000>; | ||
| 92 | read-only; | ||
| 93 | }; | ||
| 94 | partition@1f80000 { | ||
| 95 | label = "u-boot"; | ||
| 96 | reg = <0x01f80000 0x00080000>; | ||
| 97 | read-only; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | |||
| 101 | bcsr@1,0 { | ||
| 102 | compatible = "fsl,mpc8569mds-bcsr"; | ||
| 103 | reg = <1 0 0x8000>; | ||
| 104 | }; | ||
| 105 | |||
| 106 | nand@3,0 { | ||
| 107 | compatible = "fsl,mpc8569-fcm-nand", | ||
| 108 | "fsl,elbc-fcm-nand"; | ||
| 109 | reg = <3 0 0x8000>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | pib@4,0 { | ||
| 113 | compatible = "fsl,mpc8569mds-pib"; | ||
| 114 | reg = <4 0 0x8000>; | ||
| 115 | }; | ||
| 116 | |||
| 117 | pib@5,0 { | ||
| 118 | compatible = "fsl,mpc8569mds-pib"; | ||
| 119 | reg = <5 0 0x8000>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | soc@e0000000 { | ||
| 124 | #address-cells = <1>; | ||
| 125 | #size-cells = <1>; | ||
| 126 | device_type = "soc"; | ||
| 127 | compatible = "fsl,mpc8569-immr", "simple-bus"; | ||
| 128 | ranges = <0x0 0xe0000000 0x100000>; | ||
| 129 | bus-frequency = <0>; | ||
| 130 | |||
| 131 | ecm-law@0 { | ||
| 132 | compatible = "fsl,ecm-law"; | ||
| 133 | reg = <0x0 0x1000>; | ||
| 134 | fsl,num-laws = <10>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | ecm@1000 { | ||
| 138 | compatible = "fsl,mpc8569-ecm", "fsl,ecm"; | ||
| 139 | reg = <0x1000 0x1000>; | ||
| 140 | interrupts = <17 2>; | ||
| 141 | interrupt-parent = <&mpic>; | ||
| 142 | }; | ||
| 143 | |||
| 144 | memory-controller@2000 { | ||
| 145 | compatible = "fsl,mpc8569-memory-controller"; | ||
| 146 | reg = <0x2000 0x1000>; | ||
| 147 | interrupt-parent = <&mpic>; | ||
| 148 | interrupts = <18 2>; | ||
| 149 | }; | ||
| 150 | |||
| 151 | i2c@3000 { | ||
| 152 | #address-cells = <1>; | ||
| 153 | #size-cells = <0>; | ||
| 154 | cell-index = <0>; | ||
| 155 | compatible = "fsl-i2c"; | ||
| 156 | reg = <0x3000 0x100>; | ||
| 157 | interrupts = <43 2>; | ||
| 158 | interrupt-parent = <&mpic>; | ||
| 159 | dfsrr; | ||
| 160 | |||
| 161 | rtc@68 { | ||
| 162 | compatible = "dallas,ds1374"; | ||
| 163 | reg = <0x68>; | ||
| 164 | }; | ||
| 165 | }; | ||
| 166 | |||
| 167 | i2c@3100 { | ||
| 168 | #address-cells = <1>; | ||
| 169 | #size-cells = <0>; | ||
| 170 | cell-index = <1>; | ||
| 171 | compatible = "fsl-i2c"; | ||
| 172 | reg = <0x3100 0x100>; | ||
| 173 | interrupts = <43 2>; | ||
| 174 | interrupt-parent = <&mpic>; | ||
| 175 | dfsrr; | ||
| 176 | }; | ||
| 177 | |||
| 178 | serial0: serial@4500 { | ||
| 179 | cell-index = <0>; | ||
| 180 | device_type = "serial"; | ||
| 181 | compatible = "ns16550"; | ||
| 182 | reg = <0x4500 0x100>; | ||
| 183 | clock-frequency = <0>; | ||
| 184 | interrupts = <42 2>; | ||
| 185 | interrupt-parent = <&mpic>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | serial1: serial@4600 { | ||
| 189 | cell-index = <1>; | ||
| 190 | device_type = "serial"; | ||
| 191 | compatible = "ns16550"; | ||
| 192 | reg = <0x4600 0x100>; | ||
| 193 | clock-frequency = <0>; | ||
| 194 | interrupts = <42 2>; | ||
| 195 | interrupt-parent = <&mpic>; | ||
| 196 | }; | ||
| 197 | |||
| 198 | L2: l2-cache-controller@20000 { | ||
| 199 | compatible = "fsl,mpc8569-l2-cache-controller"; | ||
| 200 | reg = <0x20000 0x1000>; | ||
| 201 | cache-line-size = <32>; // 32 bytes | ||
| 202 | cache-size = <0x80000>; // L2, 512K | ||
| 203 | interrupt-parent = <&mpic>; | ||
| 204 | interrupts = <16 2>; | ||
| 205 | }; | ||
| 206 | |||
| 207 | dma@21300 { | ||
| 208 | #address-cells = <1>; | ||
| 209 | #size-cells = <1>; | ||
| 210 | compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma"; | ||
| 211 | reg = <0x21300 0x4>; | ||
| 212 | ranges = <0x0 0x21100 0x200>; | ||
| 213 | cell-index = <0>; | ||
| 214 | dma-channel@0 { | ||
| 215 | compatible = "fsl,mpc8569-dma-channel", | ||
| 216 | "fsl,eloplus-dma-channel"; | ||
| 217 | reg = <0x0 0x80>; | ||
| 218 | cell-index = <0>; | ||
| 219 | interrupt-parent = <&mpic>; | ||
| 220 | interrupts = <20 2>; | ||
| 221 | }; | ||
| 222 | dma-channel@80 { | ||
| 223 | compatible = "fsl,mpc8569-dma-channel", | ||
| 224 | "fsl,eloplus-dma-channel"; | ||
| 225 | reg = <0x80 0x80>; | ||
| 226 | cell-index = <1>; | ||
| 227 | interrupt-parent = <&mpic>; | ||
| 228 | interrupts = <21 2>; | ||
| 229 | }; | ||
| 230 | dma-channel@100 { | ||
| 231 | compatible = "fsl,mpc8569-dma-channel", | ||
| 232 | "fsl,eloplus-dma-channel"; | ||
| 233 | reg = <0x100 0x80>; | ||
| 234 | cell-index = <2>; | ||
| 235 | interrupt-parent = <&mpic>; | ||
| 236 | interrupts = <22 2>; | ||
| 237 | }; | ||
| 238 | dma-channel@180 { | ||
| 239 | compatible = "fsl,mpc8569-dma-channel", | ||
| 240 | "fsl,eloplus-dma-channel"; | ||
| 241 | reg = <0x180 0x80>; | ||
| 242 | cell-index = <3>; | ||
| 243 | interrupt-parent = <&mpic>; | ||
| 244 | interrupts = <23 2>; | ||
| 245 | }; | ||
| 246 | }; | ||
| 247 | |||
| 248 | sdhci@2e000 { | ||
| 249 | compatible = "fsl,mpc8569-esdhc", "fsl,esdhc"; | ||
| 250 | reg = <0x2e000 0x1000>; | ||
| 251 | interrupts = <72 0x8>; | ||
| 252 | interrupt-parent = <&mpic>; | ||
| 253 | /* Filled in by U-Boot */ | ||
| 254 | clock-frequency = <0>; | ||
| 255 | status = "disabled"; | ||
| 256 | }; | ||
| 257 | |||
| 258 | crypto@30000 { | ||
| 259 | compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", | ||
| 260 | "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; | ||
| 261 | reg = <0x30000 0x10000>; | ||
| 262 | interrupts = <45 2 58 2>; | ||
| 263 | interrupt-parent = <&mpic>; | ||
| 264 | fsl,num-channels = <4>; | ||
| 265 | fsl,channel-fifo-len = <24>; | ||
| 266 | fsl,exec-units-mask = <0xbfe>; | ||
| 267 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 268 | }; | ||
| 269 | |||
| 270 | mpic: pic@40000 { | ||
| 271 | interrupt-controller; | ||
| 272 | #address-cells = <0>; | ||
| 273 | #interrupt-cells = <2>; | ||
| 274 | reg = <0x40000 0x40000>; | ||
| 275 | compatible = "chrp,open-pic"; | ||
| 276 | device_type = "open-pic"; | ||
| 277 | }; | ||
| 278 | |||
| 279 | msi@41600 { | ||
| 280 | compatible = "fsl,mpc8568-msi", "fsl,mpic-msi"; | ||
| 281 | reg = <0x41600 0x80>; | ||
| 282 | msi-available-ranges = <0 0x100>; | ||
| 283 | interrupts = < | ||
| 284 | 0xe0 0 | ||
| 285 | 0xe1 0 | ||
| 286 | 0xe2 0 | ||
| 287 | 0xe3 0 | ||
| 288 | 0xe4 0 | ||
| 289 | 0xe5 0 | ||
| 290 | 0xe6 0 | ||
| 291 | 0xe7 0>; | ||
| 292 | interrupt-parent = <&mpic>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | global-utilities@e0000 { | ||
| 296 | compatible = "fsl,mpc8569-guts"; | ||
| 297 | reg = <0xe0000 0x1000>; | ||
| 298 | fsl,has-rstcr; | ||
| 299 | }; | ||
| 300 | |||
| 301 | par_io@e0100 { | ||
| 302 | #address-cells = <1>; | ||
| 303 | #size-cells = <1>; | ||
| 304 | reg = <0xe0100 0x100>; | ||
| 305 | ranges = <0x0 0xe0100 0x100>; | ||
| 306 | device_type = "par_io"; | ||
| 307 | num-ports = <7>; | ||
| 308 | |||
| 309 | qe_pio_e: gpio-controller@80 { | ||
| 310 | #gpio-cells = <2>; | ||
| 311 | compatible = "fsl,mpc8569-qe-pario-bank", | ||
| 312 | "fsl,mpc8323-qe-pario-bank"; | ||
| 313 | reg = <0x80 0x18>; | ||
| 314 | gpio-controller; | ||
| 315 | }; | ||
| 316 | |||
| 317 | pio1: ucc_pin@01 { | ||
| 318 | pio-map = < | ||
| 319 | /* port pin dir open_drain assignment has_irq */ | ||
| 320 | 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ | ||
| 321 | 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ | ||
| 322 | 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ | ||
| 323 | 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ | ||
| 324 | 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ | ||
| 325 | 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ | ||
| 326 | 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ | ||
| 327 | 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ | ||
| 328 | 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ | ||
| 329 | 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ | ||
| 330 | 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ | ||
| 331 | 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ | ||
| 332 | 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ | ||
| 333 | 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ | ||
| 334 | 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ | ||
| 335 | }; | ||
| 336 | |||
| 337 | pio2: ucc_pin@02 { | ||
| 338 | pio-map = < | ||
| 339 | /* port pin dir open_drain assignment has_irq */ | ||
| 340 | 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ | ||
| 341 | 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ | ||
| 342 | 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ | ||
| 343 | 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ | ||
| 344 | 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ | ||
| 345 | 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ | ||
| 346 | 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ | ||
| 347 | 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ | ||
| 348 | 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ | ||
| 349 | 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ | ||
| 350 | 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ | ||
| 351 | 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ | ||
| 352 | 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ | ||
| 353 | 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ | ||
| 354 | 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ | ||
| 355 | }; | ||
| 356 | |||
| 357 | pio3: ucc_pin@03 { | ||
| 358 | pio-map = < | ||
| 359 | /* port pin dir open_drain assignment has_irq */ | ||
| 360 | 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ | ||
| 361 | 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ | ||
| 362 | 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ | ||
| 363 | 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ | ||
| 364 | 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ | ||
| 365 | 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ | ||
| 366 | 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ | ||
| 367 | 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ | ||
| 368 | 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ | ||
| 369 | 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ | ||
| 370 | 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ | ||
| 371 | 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ | ||
| 372 | 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ | ||
| 373 | 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ | ||
| 374 | 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ | ||
| 375 | }; | ||
| 376 | |||
| 377 | pio4: ucc_pin@04 { | ||
| 378 | pio-map = < | ||
| 379 | /* port pin dir open_drain assignment has_irq */ | ||
| 380 | 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ | ||
| 381 | 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ | ||
| 382 | 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ | ||
| 383 | 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ | ||
| 384 | 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ | ||
| 385 | 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ | ||
| 386 | 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ | ||
| 387 | 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ | ||
| 388 | 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ | ||
| 389 | 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ | ||
| 390 | 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ | ||
| 391 | 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ | ||
| 392 | 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ | ||
| 393 | 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ | ||
| 394 | 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ | ||
| 395 | }; | ||
| 396 | }; | ||
| 397 | }; | ||
| 398 | |||
| 399 | qe@e0080000 { | ||
| 400 | #address-cells = <1>; | ||
| 401 | #size-cells = <1>; | ||
| 402 | device_type = "qe"; | ||
| 403 | compatible = "fsl,qe"; | ||
| 404 | ranges = <0x0 0xe0080000 0x40000>; | ||
| 405 | reg = <0xe0080000 0x480>; | ||
| 406 | brg-frequency = <0>; | ||
| 407 | bus-frequency = <0>; | ||
| 408 | fsl,qe-num-riscs = <4>; | ||
| 409 | fsl,qe-num-snums = <46>; | ||
| 410 | |||
| 411 | qeic: interrupt-controller@80 { | ||
| 412 | interrupt-controller; | ||
| 413 | compatible = "fsl,qe-ic"; | ||
| 414 | #address-cells = <0>; | ||
| 415 | #interrupt-cells = <1>; | ||
| 416 | reg = <0x80 0x80>; | ||
| 417 | interrupts = <46 2 46 2>; //high:30 low:30 | ||
| 418 | interrupt-parent = <&mpic>; | ||
| 419 | }; | ||
| 420 | |||
| 421 | spi@4c0 { | ||
| 422 | #address-cells = <1>; | ||
| 423 | #size-cells = <0>; | ||
| 424 | compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; | ||
| 425 | reg = <0x4c0 0x40>; | ||
| 426 | cell-index = <0>; | ||
| 427 | interrupts = <2>; | ||
| 428 | interrupt-parent = <&qeic>; | ||
| 429 | gpios = <&qe_pio_e 30 0>; | ||
| 430 | mode = "cpu-qe"; | ||
| 431 | |||
| 432 | serial-flash@0 { | ||
| 433 | compatible = "stm,m25p40"; | ||
| 434 | reg = <0>; | ||
| 435 | spi-max-frequency = <25000000>; | ||
| 436 | }; | ||
| 437 | }; | ||
| 438 | |||
| 439 | spi@500 { | ||
| 440 | cell-index = <1>; | ||
| 441 | compatible = "fsl,spi"; | ||
| 442 | reg = <0x500 0x40>; | ||
| 443 | interrupts = <1>; | ||
| 444 | interrupt-parent = <&qeic>; | ||
| 445 | mode = "cpu"; | ||
| 446 | }; | ||
| 447 | |||
| 448 | enet0: ucc@2000 { | ||
| 449 | device_type = "network"; | ||
| 450 | compatible = "ucc_geth"; | ||
| 451 | cell-index = <1>; | ||
| 452 | reg = <0x2000 0x200>; | ||
| 453 | interrupts = <32>; | ||
| 454 | interrupt-parent = <&qeic>; | ||
| 455 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 456 | rx-clock-name = "none"; | ||
| 457 | tx-clock-name = "clk12"; | ||
| 458 | pio-handle = <&pio1>; | ||
| 459 | phy-handle = <&qe_phy0>; | ||
| 460 | phy-connection-type = "rgmii-id"; | ||
| 461 | }; | ||
| 462 | |||
| 463 | mdio@2120 { | ||
| 464 | #address-cells = <1>; | ||
| 465 | #size-cells = <0>; | ||
| 466 | reg = <0x2120 0x18>; | ||
| 467 | compatible = "fsl,ucc-mdio"; | ||
| 468 | |||
| 469 | qe_phy0: ethernet-phy@07 { | ||
| 470 | interrupt-parent = <&mpic>; | ||
| 471 | interrupts = <1 1>; | ||
| 472 | reg = <0x7>; | ||
| 473 | device_type = "ethernet-phy"; | ||
| 474 | }; | ||
| 475 | qe_phy1: ethernet-phy@01 { | ||
| 476 | interrupt-parent = <&mpic>; | ||
| 477 | interrupts = <2 1>; | ||
| 478 | reg = <0x1>; | ||
| 479 | device_type = "ethernet-phy"; | ||
| 480 | }; | ||
| 481 | qe_phy2: ethernet-phy@02 { | ||
| 482 | interrupt-parent = <&mpic>; | ||
| 483 | interrupts = <3 1>; | ||
| 484 | reg = <0x2>; | ||
| 485 | device_type = "ethernet-phy"; | ||
| 486 | }; | ||
| 487 | qe_phy3: ethernet-phy@03 { | ||
| 488 | interrupt-parent = <&mpic>; | ||
| 489 | interrupts = <4 1>; | ||
| 490 | reg = <0x3>; | ||
| 491 | device_type = "ethernet-phy"; | ||
| 492 | }; | ||
| 493 | qe_phy5: ethernet-phy@04 { | ||
| 494 | interrupt-parent = <&mpic>; | ||
| 495 | reg = <0x04>; | ||
| 496 | device_type = "ethernet-phy"; | ||
| 497 | }; | ||
| 498 | qe_phy7: ethernet-phy@06 { | ||
| 499 | interrupt-parent = <&mpic>; | ||
| 500 | reg = <0x6>; | ||
| 501 | device_type = "ethernet-phy"; | ||
| 502 | }; | ||
| 503 | }; | ||
| 504 | mdio@3520 { | ||
| 505 | #address-cells = <1>; | ||
| 506 | #size-cells = <0>; | ||
| 507 | reg = <0x3520 0x18>; | ||
| 508 | compatible = "fsl,ucc-mdio"; | ||
| 509 | |||
| 510 | tbi0: tbi-phy@15 { | ||
| 511 | reg = <0x15>; | ||
| 512 | device_type = "tbi-phy"; | ||
| 513 | }; | ||
| 514 | }; | ||
| 515 | mdio@3720 { | ||
| 516 | #address-cells = <1>; | ||
| 517 | #size-cells = <0>; | ||
| 518 | reg = <0x3720 0x38>; | ||
| 519 | compatible = "fsl,ucc-mdio"; | ||
| 520 | tbi1: tbi-phy@17 { | ||
| 521 | reg = <0x17>; | ||
| 522 | device_type = "tbi-phy"; | ||
| 523 | }; | ||
| 524 | }; | ||
| 525 | |||
| 526 | enet2: ucc@2200 { | ||
| 527 | device_type = "network"; | ||
| 528 | compatible = "ucc_geth"; | ||
| 529 | cell-index = <3>; | ||
| 530 | reg = <0x2200 0x200>; | ||
| 531 | interrupts = <34>; | ||
| 532 | interrupt-parent = <&qeic>; | ||
| 533 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 534 | rx-clock-name = "none"; | ||
| 535 | tx-clock-name = "clk12"; | ||
| 536 | pio-handle = <&pio3>; | ||
| 537 | phy-handle = <&qe_phy2>; | ||
| 538 | phy-connection-type = "rgmii-id"; | ||
| 539 | }; | ||
| 540 | |||
| 541 | enet1: ucc@3000 { | ||
| 542 | device_type = "network"; | ||
| 543 | compatible = "ucc_geth"; | ||
| 544 | cell-index = <2>; | ||
| 545 | reg = <0x3000 0x200>; | ||
| 546 | interrupts = <33>; | ||
| 547 | interrupt-parent = <&qeic>; | ||
| 548 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 549 | rx-clock-name = "none"; | ||
| 550 | tx-clock-name = "clk17"; | ||
| 551 | pio-handle = <&pio2>; | ||
| 552 | phy-handle = <&qe_phy1>; | ||
| 553 | phy-connection-type = "rgmii-id"; | ||
| 554 | }; | ||
| 555 | |||
| 556 | enet3: ucc@3200 { | ||
| 557 | device_type = "network"; | ||
| 558 | compatible = "ucc_geth"; | ||
| 559 | cell-index = <4>; | ||
| 560 | reg = <0x3200 0x200>; | ||
| 561 | interrupts = <35>; | ||
| 562 | interrupt-parent = <&qeic>; | ||
| 563 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 564 | rx-clock-name = "none"; | ||
| 565 | tx-clock-name = "clk17"; | ||
| 566 | pio-handle = <&pio4>; | ||
| 567 | phy-handle = <&qe_phy3>; | ||
| 568 | phy-connection-type = "rgmii-id"; | ||
| 569 | }; | ||
| 570 | |||
| 571 | enet5: ucc@3400 { | ||
| 572 | device_type = "network"; | ||
| 573 | compatible = "ucc_geth"; | ||
| 574 | cell-index = <6>; | ||
| 575 | reg = <0x3400 0x200>; | ||
| 576 | interrupts = <41>; | ||
| 577 | interrupt-parent = <&qeic>; | ||
| 578 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 579 | rx-clock-name = "none"; | ||
| 580 | tx-clock-name = "none"; | ||
| 581 | tbi-handle = <&tbi0>; | ||
| 582 | phy-handle = <&qe_phy5>; | ||
| 583 | phy-connection-type = "sgmii"; | ||
| 584 | }; | ||
| 585 | |||
| 586 | enet7: ucc@3600 { | ||
| 587 | device_type = "network"; | ||
| 588 | compatible = "ucc_geth"; | ||
| 589 | cell-index = <8>; | ||
| 590 | reg = <0x3600 0x200>; | ||
| 591 | interrupts = <43>; | ||
| 592 | interrupt-parent = <&qeic>; | ||
| 593 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 594 | rx-clock-name = "none"; | ||
| 595 | tx-clock-name = "none"; | ||
| 596 | tbi-handle = <&tbi1>; | ||
| 597 | phy-handle = <&qe_phy7>; | ||
| 598 | phy-connection-type = "sgmii"; | ||
| 599 | }; | ||
| 600 | |||
| 601 | muram@10000 { | ||
| 602 | #address-cells = <1>; | ||
| 603 | #size-cells = <1>; | ||
| 604 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; | ||
| 605 | ranges = <0x0 0x10000 0x20000>; | ||
| 606 | |||
| 607 | data-only@0 { | ||
| 608 | compatible = "fsl,qe-muram-data", | ||
| 609 | "fsl,cpm-muram-data"; | ||
| 610 | reg = <0x0 0x20000>; | ||
| 611 | }; | ||
| 612 | }; | ||
| 613 | |||
| 614 | }; | ||
| 615 | |||
| 616 | /* PCI Express */ | ||
| 617 | pci1: pcie@e000a000 { | ||
| 618 | compatible = "fsl,mpc8548-pcie"; | ||
| 619 | device_type = "pci"; | ||
| 620 | #interrupt-cells = <1>; | ||
| 621 | #size-cells = <2>; | ||
| 622 | #address-cells = <3>; | ||
| 623 | reg = <0xe000a000 0x1000>; | ||
| 624 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 625 | interrupt-map = < | ||
| 626 | /* IDSEL 0x0 (PEX) */ | ||
| 627 | 00000 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 628 | 00000 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 629 | 00000 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 630 | 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; | ||
| 631 | |||
| 632 | interrupt-parent = <&mpic>; | ||
| 633 | interrupts = <26 2>; | ||
| 634 | bus-range = <0 255>; | ||
| 635 | ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 | ||
| 636 | 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; | ||
| 637 | clock-frequency = <33333333>; | ||
| 638 | pcie@0 { | ||
| 639 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 640 | #size-cells = <2>; | ||
| 641 | #address-cells = <3>; | ||
| 642 | device_type = "pci"; | ||
| 643 | ranges = <0x2000000 0x0 0xa0000000 | ||
| 644 | 0x2000000 0x0 0xa0000000 | ||
| 645 | 0x0 0x10000000 | ||
| 646 | |||
| 647 | 0x1000000 0x0 0x0 | ||
| 648 | 0x1000000 0x0 0x0 | ||
| 649 | 0x0 0x800000>; | ||
| 650 | }; | ||
| 651 | }; | ||
| 652 | |||
| 653 | rio0: rapidio@e00c00000 { | ||
| 654 | #address-cells = <2>; | ||
| 655 | #size-cells = <2>; | ||
| 656 | compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta"; | ||
| 657 | reg = <0xe00c0000 0x20000>; | ||
| 658 | ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; | ||
| 659 | interrupts = <48 2 /* error */ | ||
| 660 | 49 2 /* bell_outb */ | ||
| 661 | 50 2 /* bell_inb */ | ||
| 662 | 53 2 /* msg1_tx */ | ||
| 663 | 54 2 /* msg1_rx */ | ||
| 664 | 55 2 /* msg2_tx */ | ||
| 665 | 56 2 /* msg2_rx */>; | ||
| 666 | interrupt-parent = <&mpic>; | ||
| 667 | }; | ||
| 668 | }; | ||
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 6e79a4169088..cafc1285c140 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts | |||
| @@ -182,9 +182,21 @@ | |||
| 182 | device_type = "soc"; | 182 | device_type = "soc"; |
| 183 | compatible = "simple-bus"; | 183 | compatible = "simple-bus"; |
| 184 | ranges = <0x0 0 0xffe00000 0x100000>; | 184 | ranges = <0x0 0 0xffe00000 0x100000>; |
| 185 | reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed | ||
| 186 | bus-frequency = <0>; // Filled out by uboot. | 185 | bus-frequency = <0>; // Filled out by uboot. |
| 187 | 186 | ||
| 187 | ecm-law@0 { | ||
| 188 | compatible = "fsl,ecm-law"; | ||
| 189 | reg = <0x0 0x1000>; | ||
| 190 | fsl,num-laws = <12>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | ecm@1000 { | ||
| 194 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 195 | reg = <0x1000 0x1000>; | ||
| 196 | interrupts = <17 2>; | ||
| 197 | interrupt-parent = <&mpic>; | ||
| 198 | }; | ||
| 199 | |||
| 188 | memory-controller@2000 { | 200 | memory-controller@2000 { |
| 189 | compatible = "fsl,mpc8572-memory-controller"; | 201 | compatible = "fsl,mpc8572-memory-controller"; |
| 190 | reg = <0x2000 0x1000>; | 202 | reg = <0x2000 0x1000>; |
| @@ -514,7 +526,6 @@ | |||
| 514 | }; | 526 | }; |
| 515 | 527 | ||
| 516 | pci0: pcie@ffe08000 { | 528 | pci0: pcie@ffe08000 { |
| 517 | cell-index = <0>; | ||
| 518 | compatible = "fsl,mpc8548-pcie"; | 529 | compatible = "fsl,mpc8548-pcie"; |
| 519 | device_type = "pci"; | 530 | device_type = "pci"; |
| 520 | #interrupt-cells = <1>; | 531 | #interrupt-cells = <1>; |
| @@ -724,7 +735,6 @@ | |||
| 724 | }; | 735 | }; |
| 725 | 736 | ||
| 726 | pci1: pcie@ffe09000 { | 737 | pci1: pcie@ffe09000 { |
| 727 | cell-index = <1>; | ||
| 728 | compatible = "fsl,mpc8548-pcie"; | 738 | compatible = "fsl,mpc8548-pcie"; |
| 729 | device_type = "pci"; | 739 | device_type = "pci"; |
| 730 | #interrupt-cells = <1>; | 740 | #interrupt-cells = <1>; |
| @@ -761,7 +771,6 @@ | |||
| 761 | }; | 771 | }; |
| 762 | 772 | ||
| 763 | pci2: pcie@ffe0a000 { | 773 | pci2: pcie@ffe0a000 { |
| 764 | cell-index = <2>; | ||
| 765 | compatible = "fsl,mpc8548-pcie"; | 774 | compatible = "fsl,mpc8548-pcie"; |
| 766 | device_type = "pci"; | 775 | device_type = "pci"; |
| 767 | #interrupt-cells = <1>; | 776 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts index dbd81a764742..f6365db3b97d 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts | |||
| @@ -182,9 +182,21 @@ | |||
| 182 | device_type = "soc"; | 182 | device_type = "soc"; |
| 183 | compatible = "simple-bus"; | 183 | compatible = "simple-bus"; |
| 184 | ranges = <0x0 0xf 0xffe00000 0x100000>; | 184 | ranges = <0x0 0xf 0xffe00000 0x100000>; |
| 185 | reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed | ||
| 186 | bus-frequency = <0>; // Filled out by uboot. | 185 | bus-frequency = <0>; // Filled out by uboot. |
| 187 | 186 | ||
| 187 | ecm-law@0 { | ||
| 188 | compatible = "fsl,ecm-law"; | ||
| 189 | reg = <0x0 0x1000>; | ||
| 190 | fsl,num-laws = <12>; | ||
| 191 | }; | ||
| 192 | |||
| 193 | ecm@1000 { | ||
| 194 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 195 | reg = <0x1000 0x1000>; | ||
| 196 | interrupts = <17 2>; | ||
| 197 | interrupt-parent = <&mpic>; | ||
| 198 | }; | ||
| 199 | |||
| 188 | memory-controller@2000 { | 200 | memory-controller@2000 { |
| 189 | compatible = "fsl,mpc8572-memory-controller"; | 201 | compatible = "fsl,mpc8572-memory-controller"; |
| 190 | reg = <0x2000 0x1000>; | 202 | reg = <0x2000 0x1000>; |
| @@ -514,7 +526,6 @@ | |||
| 514 | }; | 526 | }; |
| 515 | 527 | ||
| 516 | pci0: pcie@fffe08000 { | 528 | pci0: pcie@fffe08000 { |
| 517 | cell-index = <0>; | ||
| 518 | compatible = "fsl,mpc8548-pcie"; | 529 | compatible = "fsl,mpc8548-pcie"; |
| 519 | device_type = "pci"; | 530 | device_type = "pci"; |
| 520 | #interrupt-cells = <1>; | 531 | #interrupt-cells = <1>; |
| @@ -522,7 +533,7 @@ | |||
| 522 | #address-cells = <3>; | 533 | #address-cells = <3>; |
| 523 | reg = <0xf 0xffe08000 0 0x1000>; | 534 | reg = <0xf 0xffe08000 0 0x1000>; |
| 524 | bus-range = <0 255>; | 535 | bus-range = <0 255>; |
| 525 | ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000 | 536 | ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
| 526 | 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; | 537 | 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; |
| 527 | clock-frequency = <33333333>; | 538 | clock-frequency = <33333333>; |
| 528 | interrupt-parent = <&mpic>; | 539 | interrupt-parent = <&mpic>; |
| @@ -649,8 +660,8 @@ | |||
| 649 | #size-cells = <2>; | 660 | #size-cells = <2>; |
| 650 | #address-cells = <3>; | 661 | #address-cells = <3>; |
| 651 | device_type = "pci"; | 662 | device_type = "pci"; |
| 652 | ranges = <0x2000000 0x0 0xc0000000 | 663 | ranges = <0x2000000 0x0 0xe0000000 |
| 653 | 0x2000000 0x0 0xc0000000 | 664 | 0x2000000 0x0 0xe0000000 |
| 654 | 0x0 0x20000000 | 665 | 0x0 0x20000000 |
| 655 | 666 | ||
| 656 | 0x1000000 0x0 0x0 | 667 | 0x1000000 0x0 0x0 |
| @@ -660,8 +671,8 @@ | |||
| 660 | reg = <0x0 0x0 0x0 0x0 0x0>; | 671 | reg = <0x0 0x0 0x0 0x0 0x0>; |
| 661 | #size-cells = <2>; | 672 | #size-cells = <2>; |
| 662 | #address-cells = <3>; | 673 | #address-cells = <3>; |
| 663 | ranges = <0x2000000 0x0 0xc0000000 | 674 | ranges = <0x2000000 0x0 0xe0000000 |
| 664 | 0x2000000 0x0 0xc0000000 | 675 | 0x2000000 0x0 0xe0000000 |
| 665 | 0x0 0x20000000 | 676 | 0x0 0x20000000 |
| 666 | 677 | ||
| 667 | 0x1000000 0x0 0x0 | 678 | 0x1000000 0x0 0x0 |
| @@ -724,7 +735,6 @@ | |||
| 724 | }; | 735 | }; |
| 725 | 736 | ||
| 726 | pci1: pcie@fffe09000 { | 737 | pci1: pcie@fffe09000 { |
| 727 | cell-index = <1>; | ||
| 728 | compatible = "fsl,mpc8548-pcie"; | 738 | compatible = "fsl,mpc8548-pcie"; |
| 729 | device_type = "pci"; | 739 | device_type = "pci"; |
| 730 | #interrupt-cells = <1>; | 740 | #interrupt-cells = <1>; |
| @@ -732,7 +742,7 @@ | |||
| 732 | #address-cells = <3>; | 742 | #address-cells = <3>; |
| 733 | reg = <0xf 0xffe09000 0 0x1000>; | 743 | reg = <0xf 0xffe09000 0 0x1000>; |
| 734 | bus-range = <0 255>; | 744 | bus-range = <0 255>; |
| 735 | ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 | 745 | ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
| 736 | 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; | 746 | 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; |
| 737 | clock-frequency = <33333333>; | 747 | clock-frequency = <33333333>; |
| 738 | interrupt-parent = <&mpic>; | 748 | interrupt-parent = <&mpic>; |
| @@ -750,8 +760,8 @@ | |||
| 750 | #size-cells = <2>; | 760 | #size-cells = <2>; |
| 751 | #address-cells = <3>; | 761 | #address-cells = <3>; |
| 752 | device_type = "pci"; | 762 | device_type = "pci"; |
| 753 | ranges = <0x2000000 0x0 0xc0000000 | 763 | ranges = <0x2000000 0x0 0xe0000000 |
| 754 | 0x2000000 0x0 0xc0000000 | 764 | 0x2000000 0x0 0xe0000000 |
| 755 | 0x0 0x20000000 | 765 | 0x0 0x20000000 |
| 756 | 766 | ||
| 757 | 0x1000000 0x0 0x0 | 767 | 0x1000000 0x0 0x0 |
| @@ -761,7 +771,6 @@ | |||
| 761 | }; | 771 | }; |
| 762 | 772 | ||
| 763 | pci2: pcie@fffe0a000 { | 773 | pci2: pcie@fffe0a000 { |
| 764 | cell-index = <2>; | ||
| 765 | compatible = "fsl,mpc8548-pcie"; | 774 | compatible = "fsl,mpc8548-pcie"; |
| 766 | device_type = "pci"; | 775 | device_type = "pci"; |
| 767 | #interrupt-cells = <1>; | 776 | #interrupt-cells = <1>; |
| @@ -769,7 +778,7 @@ | |||
| 769 | #address-cells = <3>; | 778 | #address-cells = <3>; |
| 770 | reg = <0xf 0xffe0a000 0 0x1000>; | 779 | reg = <0xf 0xffe0a000 0 0x1000>; |
| 771 | bus-range = <0 255>; | 780 | bus-range = <0 255>; |
| 772 | ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 | 781 | ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 |
| 773 | 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; | 782 | 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; |
| 774 | clock-frequency = <33333333>; | 783 | clock-frequency = <33333333>; |
| 775 | interrupt-parent = <&mpic>; | 784 | interrupt-parent = <&mpic>; |
| @@ -787,8 +796,8 @@ | |||
| 787 | #size-cells = <2>; | 796 | #size-cells = <2>; |
| 788 | #address-cells = <3>; | 797 | #address-cells = <3>; |
| 789 | device_type = "pci"; | 798 | device_type = "pci"; |
| 790 | ranges = <0x2000000 0x0 0xc0000000 | 799 | ranges = <0x2000000 0x0 0xe0000000 |
| 791 | 0x2000000 0x0 0xc0000000 | 800 | 0x2000000 0x0 0xe0000000 |
| 792 | 0x0 0x20000000 | 801 | 0x0 0x20000000 |
| 793 | 802 | ||
| 794 | 0x1000000 0x0 0x0 | 803 | 0x1000000 0x0 0x0 |
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts index 2bc0c7189653..5bd1011fde96 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | |||
| @@ -59,9 +59,21 @@ | |||
| 59 | device_type = "soc"; | 59 | device_type = "soc"; |
| 60 | compatible = "simple-bus"; | 60 | compatible = "simple-bus"; |
| 61 | ranges = <0x0 0xffe00000 0x100000>; | 61 | ranges = <0x0 0xffe00000 0x100000>; |
| 62 | reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed | ||
| 63 | bus-frequency = <0>; // Filled out by uboot. | 62 | bus-frequency = <0>; // Filled out by uboot. |
| 64 | 63 | ||
| 64 | ecm-law@0 { | ||
| 65 | compatible = "fsl,ecm-law"; | ||
| 66 | reg = <0x0 0x1000>; | ||
| 67 | fsl,num-laws = <12>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | ecm@1000 { | ||
| 71 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 72 | reg = <0x1000 0x1000>; | ||
| 73 | interrupts = <17 2>; | ||
| 74 | interrupt-parent = <&mpic>; | ||
| 75 | }; | ||
| 76 | |||
| 65 | memory-controller@2000 { | 77 | memory-controller@2000 { |
| 66 | compatible = "fsl,mpc8572-memory-controller"; | 78 | compatible = "fsl,mpc8572-memory-controller"; |
| 67 | reg = <0x2000 0x1000>; | 79 | reg = <0x2000 0x1000>; |
| @@ -238,7 +250,6 @@ | |||
| 238 | }; | 250 | }; |
| 239 | 251 | ||
| 240 | pci0: pcie@ffe08000 { | 252 | pci0: pcie@ffe08000 { |
| 241 | cell-index = <0>; | ||
| 242 | compatible = "fsl,mpc8548-pcie"; | 253 | compatible = "fsl,mpc8548-pcie"; |
| 243 | device_type = "pci"; | 254 | device_type = "pci"; |
| 244 | #interrupt-cells = <1>; | 255 | #interrupt-cells = <1>; |
| @@ -448,7 +459,6 @@ | |||
| 448 | }; | 459 | }; |
| 449 | 460 | ||
| 450 | pci1: pcie@ffe09000 { | 461 | pci1: pcie@ffe09000 { |
| 451 | cell-index = <1>; | ||
| 452 | compatible = "fsl,mpc8548-pcie"; | 462 | compatible = "fsl,mpc8548-pcie"; |
| 453 | device_type = "pci"; | 463 | device_type = "pci"; |
| 454 | #interrupt-cells = <1>; | 464 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts index 159cb3a875f0..0efc3456e297 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts | |||
| @@ -58,7 +58,6 @@ | |||
| 58 | device_type = "soc"; | 58 | device_type = "soc"; |
| 59 | compatible = "simple-bus"; | 59 | compatible = "simple-bus"; |
| 60 | ranges = <0x0 0xffe00000 0x100000>; | 60 | ranges = <0x0 0xffe00000 0x100000>; |
| 61 | reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed | ||
| 62 | bus-frequency = <0>; // Filled out by uboot. | 61 | bus-frequency = <0>; // Filled out by uboot. |
| 63 | 62 | ||
| 64 | L2: l2-cache-controller@20000 { | 63 | L2: l2-cache-controller@20000 { |
| @@ -196,7 +195,6 @@ | |||
| 196 | }; | 195 | }; |
| 197 | 196 | ||
| 198 | pci2: pcie@ffe0a000 { | 197 | pci2: pcie@ffe0a000 { |
| 199 | cell-index = <2>; | ||
| 200 | compatible = "fsl,mpc8548-pcie"; | 198 | compatible = "fsl,mpc8548-pcie"; |
| 201 | device_type = "pci"; | 199 | device_type = "pci"; |
| 202 | #interrupt-cells = <1>; | 200 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 1bd3ebe11437..f468d215f716 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts | |||
| @@ -100,8 +100,18 @@ | |||
| 100 | }; | 100 | }; |
| 101 | 101 | ||
| 102 | board-control@3,0 { | 102 | board-control@3,0 { |
| 103 | #address-cells = <1>; | ||
| 104 | #size-cells = <1>; | ||
| 103 | compatible = "fsl,fpga-pixis"; | 105 | compatible = "fsl,fpga-pixis"; |
| 104 | reg = <3 0 0x20>; | 106 | reg = <3 0 0x20>; |
| 107 | ranges = <0 3 0 0x20>; | ||
| 108 | |||
| 109 | sdcsr_pio: gpio-controller@a { | ||
| 110 | #gpio-cells = <2>; | ||
| 111 | compatible = "fsl,fpga-pixis-gpio-bank"; | ||
| 112 | reg = <0xa 1>; | ||
| 113 | gpio-controller; | ||
| 114 | }; | ||
| 105 | }; | 115 | }; |
| 106 | }; | 116 | }; |
| 107 | 117 | ||
| @@ -112,9 +122,21 @@ | |||
| 112 | device_type = "soc"; | 122 | device_type = "soc"; |
| 113 | compatible = "fsl,mpc8610-immr", "simple-bus"; | 123 | compatible = "fsl,mpc8610-immr", "simple-bus"; |
| 114 | ranges = <0x0 0xe0000000 0x00100000>; | 124 | ranges = <0x0 0xe0000000 0x00100000>; |
| 115 | reg = <0xe0000000 0x1000>; | ||
| 116 | bus-frequency = <0>; | 125 | bus-frequency = <0>; |
| 117 | 126 | ||
| 127 | mcm-law@0 { | ||
| 128 | compatible = "fsl,mcm-law"; | ||
| 129 | reg = <0x0 0x1000>; | ||
| 130 | fsl,num-laws = <10>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | mcm@1000 { | ||
| 134 | compatible = "fsl,mpc8610-mcm", "fsl,mcm"; | ||
| 135 | reg = <0x1000 0x1000>; | ||
| 136 | interrupts = <17 2>; | ||
| 137 | interrupt-parent = <&mpic>; | ||
| 138 | }; | ||
| 139 | |||
| 118 | i2c@3000 { | 140 | i2c@3000 { |
| 119 | #address-cells = <1>; | 141 | #address-cells = <1>; |
| 120 | #size-cells = <0>; | 142 | #size-cells = <0>; |
| @@ -164,6 +186,28 @@ | |||
| 164 | interrupt-parent = <&mpic>; | 186 | interrupt-parent = <&mpic>; |
| 165 | }; | 187 | }; |
| 166 | 188 | ||
| 189 | spi@7000 { | ||
| 190 | #address-cells = <1>; | ||
| 191 | #size-cells = <0>; | ||
| 192 | compatible = "fsl,mpc8610-spi", "fsl,spi"; | ||
| 193 | reg = <0x7000 0x40>; | ||
| 194 | cell-index = <0>; | ||
| 195 | interrupts = <59 2>; | ||
| 196 | interrupt-parent = <&mpic>; | ||
| 197 | mode = "cpu"; | ||
| 198 | gpios = <&sdcsr_pio 7 0>; | ||
| 199 | |||
| 200 | mmc-slot@0 { | ||
| 201 | compatible = "fsl,mpc8610hpcd-mmc-slot", | ||
| 202 | "mmc-spi-slot"; | ||
| 203 | reg = <0>; | ||
| 204 | gpios = <&sdcsr_pio 0 1 /* nCD */ | ||
| 205 | &sdcsr_pio 1 0>; /* WP */ | ||
| 206 | voltage-ranges = <3300 3300>; | ||
| 207 | spi-max-frequency = <50000000>; | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | |||
| 167 | display@2c000 { | 211 | display@2c000 { |
| 168 | compatible = "fsl,diu"; | 212 | compatible = "fsl,diu"; |
| 169 | reg = <0x2c000 100>; | 213 | reg = <0x2c000 100>; |
| @@ -316,7 +360,6 @@ | |||
| 316 | }; | 360 | }; |
| 317 | 361 | ||
| 318 | pci0: pci@e0008000 { | 362 | pci0: pci@e0008000 { |
| 319 | cell-index = <0>; | ||
| 320 | compatible = "fsl,mpc8610-pci"; | 363 | compatible = "fsl,mpc8610-pci"; |
| 321 | device_type = "pci"; | 364 | device_type = "pci"; |
| 322 | #interrupt-cells = <1>; | 365 | #interrupt-cells = <1>; |
| @@ -346,7 +389,6 @@ | |||
| 346 | }; | 389 | }; |
| 347 | 390 | ||
| 348 | pci1: pcie@e000a000 { | 391 | pci1: pcie@e000a000 { |
| 349 | cell-index = <1>; | ||
| 350 | compatible = "fsl,mpc8641-pcie"; | 392 | compatible = "fsl,mpc8641-pcie"; |
| 351 | device_type = "pci"; | 393 | device_type = "pci"; |
| 352 | #interrupt-cells = <1>; | 394 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index d72beb192460..848320e4d3c4 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts | |||
| @@ -114,9 +114,21 @@ | |||
| 114 | device_type = "soc"; | 114 | device_type = "soc"; |
| 115 | compatible = "simple-bus"; | 115 | compatible = "simple-bus"; |
| 116 | ranges = <0x00000000 0xffe00000 0x00100000>; | 116 | ranges = <0x00000000 0xffe00000 0x00100000>; |
| 117 | reg = <0xffe00000 0x00001000>; // CCSRBAR | ||
| 118 | bus-frequency = <0>; | 117 | bus-frequency = <0>; |
| 119 | 118 | ||
| 119 | mcm-law@0 { | ||
| 120 | compatible = "fsl,mcm-law"; | ||
| 121 | reg = <0x0 0x1000>; | ||
| 122 | fsl,num-laws = <10>; | ||
| 123 | }; | ||
| 124 | |||
| 125 | mcm@1000 { | ||
| 126 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 127 | reg = <0x1000 0x1000>; | ||
| 128 | interrupts = <17 2>; | ||
| 129 | interrupt-parent = <&mpic>; | ||
| 130 | }; | ||
| 131 | |||
| 120 | i2c@3000 { | 132 | i2c@3000 { |
| 121 | #address-cells = <1>; | 133 | #address-cells = <1>; |
| 122 | #size-cells = <0>; | 134 | #size-cells = <0>; |
| @@ -357,7 +369,6 @@ | |||
| 357 | }; | 369 | }; |
| 358 | 370 | ||
| 359 | pci0: pcie@ffe08000 { | 371 | pci0: pcie@ffe08000 { |
| 360 | cell-index = <0>; | ||
| 361 | compatible = "fsl,mpc8641-pcie"; | 372 | compatible = "fsl,mpc8641-pcie"; |
| 362 | device_type = "pci"; | 373 | device_type = "pci"; |
| 363 | #interrupt-cells = <1>; | 374 | #interrupt-cells = <1>; |
| @@ -566,7 +577,6 @@ | |||
| 566 | }; | 577 | }; |
| 567 | 578 | ||
| 568 | pci1: pcie@ffe09000 { | 579 | pci1: pcie@ffe09000 { |
| 569 | cell-index = <1>; | ||
| 570 | compatible = "fsl,mpc8641-pcie"; | 580 | compatible = "fsl,mpc8641-pcie"; |
| 571 | device_type = "pci"; | 581 | device_type = "pci"; |
| 572 | #interrupt-cells = <1>; | 582 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts new file mode 100644 index 000000000000..8be8e701e1d3 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts | |||
| @@ -0,0 +1,609 @@ | |||
| 1 | /* | ||
| 2 | * MPC8641 HPCN Device Tree Source | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Freescale Semiconductor Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "MPC8641HPCN"; | ||
| 16 | compatible = "fsl,mpc8641hpcn"; | ||
| 17 | #address-cells = <2>; | ||
| 18 | #size-cells = <2>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | ethernet0 = &enet0; | ||
| 22 | ethernet1 = &enet1; | ||
| 23 | ethernet2 = &enet2; | ||
| 24 | ethernet3 = &enet3; | ||
| 25 | serial0 = &serial0; | ||
| 26 | serial1 = &serial1; | ||
| 27 | pci0 = &pci0; | ||
| 28 | pci1 = &pci1; | ||
| 29 | }; | ||
| 30 | |||
| 31 | cpus { | ||
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | |||
| 35 | PowerPC,8641@0 { | ||
| 36 | device_type = "cpu"; | ||
| 37 | reg = <0>; | ||
| 38 | d-cache-line-size = <32>; // 32 bytes | ||
| 39 | i-cache-line-size = <32>; // 32 bytes | ||
| 40 | d-cache-size = <32768>; // L1, 32K | ||
| 41 | i-cache-size = <32768>; // L1, 32K | ||
| 42 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
| 43 | bus-frequency = <0>; // From uboot | ||
| 44 | clock-frequency = <0>; // From uboot | ||
| 45 | }; | ||
| 46 | PowerPC,8641@1 { | ||
| 47 | device_type = "cpu"; | ||
| 48 | reg = <1>; | ||
| 49 | d-cache-line-size = <32>; // 32 bytes | ||
| 50 | i-cache-line-size = <32>; // 32 bytes | ||
| 51 | d-cache-size = <32768>; // L1, 32K | ||
| 52 | i-cache-size = <32768>; // L1, 32K | ||
| 53 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
| 54 | bus-frequency = <0>; // From uboot | ||
| 55 | clock-frequency = <0>; // From uboot | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | |||
| 59 | memory { | ||
| 60 | device_type = "memory"; | ||
| 61 | reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 | ||
| 62 | }; | ||
| 63 | |||
| 64 | localbus@fffe05000 { | ||
| 65 | #address-cells = <2>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | compatible = "fsl,mpc8641-localbus", "simple-bus"; | ||
| 68 | reg = <0x0f 0xffe05000 0x0 0x1000>; | ||
| 69 | interrupts = <19 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | |||
| 72 | ranges = <0 0 0xf 0xef800000 0x00800000 | ||
| 73 | 2 0 0xf 0xffdf8000 0x00008000 | ||
| 74 | 3 0 0xf 0xffdf0000 0x00008000>; | ||
| 75 | |||
| 76 | flash@0,0 { | ||
| 77 | compatible = "cfi-flash"; | ||
| 78 | reg = <0 0 0x00800000>; | ||
| 79 | bank-width = <2>; | ||
| 80 | device-width = <2>; | ||
| 81 | #address-cells = <1>; | ||
| 82 | #size-cells = <1>; | ||
| 83 | partition@0 { | ||
| 84 | label = "kernel"; | ||
| 85 | reg = <0x00000000 0x00300000>; | ||
| 86 | }; | ||
| 87 | partition@300000 { | ||
| 88 | label = "firmware b"; | ||
| 89 | reg = <0x00300000 0x00100000>; | ||
| 90 | read-only; | ||
| 91 | }; | ||
| 92 | partition@400000 { | ||
| 93 | label = "fs"; | ||
| 94 | reg = <0x00400000 0x00300000>; | ||
| 95 | }; | ||
| 96 | partition@700000 { | ||
| 97 | label = "firmware a"; | ||
| 98 | reg = <0x00700000 0x00100000>; | ||
| 99 | read-only; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | }; | ||
| 103 | |||
| 104 | soc8641@fffe00000 { | ||
| 105 | #address-cells = <1>; | ||
| 106 | #size-cells = <1>; | ||
| 107 | device_type = "soc"; | ||
| 108 | compatible = "simple-bus"; | ||
| 109 | ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; | ||
| 110 | bus-frequency = <0>; | ||
| 111 | |||
| 112 | mcm-law@0 { | ||
| 113 | compatible = "fsl,mcm-law"; | ||
| 114 | reg = <0x0 0x1000>; | ||
| 115 | fsl,num-laws = <10>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | mcm@1000 { | ||
| 119 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 120 | reg = <0x1000 0x1000>; | ||
| 121 | interrupts = <17 2>; | ||
| 122 | interrupt-parent = <&mpic>; | ||
| 123 | }; | ||
| 124 | |||
| 125 | i2c@3000 { | ||
| 126 | #address-cells = <1>; | ||
| 127 | #size-cells = <0>; | ||
| 128 | cell-index = <0>; | ||
| 129 | compatible = "fsl-i2c"; | ||
| 130 | reg = <0x3000 0x100>; | ||
| 131 | interrupts = <43 2>; | ||
| 132 | interrupt-parent = <&mpic>; | ||
| 133 | dfsrr; | ||
| 134 | }; | ||
| 135 | |||
| 136 | i2c@3100 { | ||
| 137 | #address-cells = <1>; | ||
| 138 | #size-cells = <0>; | ||
| 139 | cell-index = <1>; | ||
| 140 | compatible = "fsl-i2c"; | ||
| 141 | reg = <0x3100 0x100>; | ||
| 142 | interrupts = <43 2>; | ||
| 143 | interrupt-parent = <&mpic>; | ||
| 144 | dfsrr; | ||
| 145 | }; | ||
| 146 | |||
| 147 | dma@21300 { | ||
| 148 | #address-cells = <1>; | ||
| 149 | #size-cells = <1>; | ||
| 150 | compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; | ||
| 151 | reg = <0x21300 0x4>; | ||
| 152 | ranges = <0x0 0x21100 0x200>; | ||
| 153 | cell-index = <0>; | ||
| 154 | dma-channel@0 { | ||
| 155 | compatible = "fsl,mpc8641-dma-channel", | ||
| 156 | "fsl,eloplus-dma-channel"; | ||
| 157 | reg = <0x0 0x80>; | ||
| 158 | cell-index = <0>; | ||
| 159 | interrupt-parent = <&mpic>; | ||
| 160 | interrupts = <20 2>; | ||
| 161 | }; | ||
| 162 | dma-channel@80 { | ||
| 163 | compatible = "fsl,mpc8641-dma-channel", | ||
| 164 | "fsl,eloplus-dma-channel"; | ||
| 165 | reg = <0x80 0x80>; | ||
| 166 | cell-index = <1>; | ||
| 167 | interrupt-parent = <&mpic>; | ||
| 168 | interrupts = <21 2>; | ||
| 169 | }; | ||
| 170 | dma-channel@100 { | ||
| 171 | compatible = "fsl,mpc8641-dma-channel", | ||
| 172 | "fsl,eloplus-dma-channel"; | ||
| 173 | reg = <0x100 0x80>; | ||
| 174 | cell-index = <2>; | ||
| 175 | interrupt-parent = <&mpic>; | ||
| 176 | interrupts = <22 2>; | ||
| 177 | }; | ||
| 178 | dma-channel@180 { | ||
| 179 | compatible = "fsl,mpc8641-dma-channel", | ||
| 180 | "fsl,eloplus-dma-channel"; | ||
| 181 | reg = <0x180 0x80>; | ||
| 182 | cell-index = <3>; | ||
| 183 | interrupt-parent = <&mpic>; | ||
| 184 | interrupts = <23 2>; | ||
| 185 | }; | ||
| 186 | }; | ||
| 187 | |||
| 188 | enet0: ethernet@24000 { | ||
| 189 | #address-cells = <1>; | ||
| 190 | #size-cells = <1>; | ||
| 191 | cell-index = <0>; | ||
| 192 | device_type = "network"; | ||
| 193 | model = "TSEC"; | ||
| 194 | compatible = "gianfar"; | ||
| 195 | reg = <0x24000 0x1000>; | ||
| 196 | ranges = <0x0 0x24000 0x1000>; | ||
| 197 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 198 | interrupts = <29 2 30 2 34 2>; | ||
| 199 | interrupt-parent = <&mpic>; | ||
| 200 | tbi-handle = <&tbi0>; | ||
| 201 | phy-handle = <&phy0>; | ||
| 202 | phy-connection-type = "rgmii-id"; | ||
| 203 | |||
| 204 | mdio@520 { | ||
| 205 | #address-cells = <1>; | ||
| 206 | #size-cells = <0>; | ||
| 207 | compatible = "fsl,gianfar-mdio"; | ||
| 208 | reg = <0x520 0x20>; | ||
| 209 | |||
| 210 | phy0: ethernet-phy@0 { | ||
| 211 | interrupt-parent = <&mpic>; | ||
| 212 | interrupts = <10 1>; | ||
| 213 | reg = <0>; | ||
| 214 | device_type = "ethernet-phy"; | ||
| 215 | }; | ||
| 216 | phy1: ethernet-phy@1 { | ||
| 217 | interrupt-parent = <&mpic>; | ||
| 218 | interrupts = <10 1>; | ||
| 219 | reg = <1>; | ||
| 220 | device_type = "ethernet-phy"; | ||
| 221 | }; | ||
| 222 | phy2: ethernet-phy@2 { | ||
| 223 | interrupt-parent = <&mpic>; | ||
| 224 | interrupts = <10 1>; | ||
| 225 | reg = <2>; | ||
| 226 | device_type = "ethernet-phy"; | ||
| 227 | }; | ||
| 228 | phy3: ethernet-phy@3 { | ||
| 229 | interrupt-parent = <&mpic>; | ||
| 230 | interrupts = <10 1>; | ||
| 231 | reg = <3>; | ||
| 232 | device_type = "ethernet-phy"; | ||
| 233 | }; | ||
| 234 | tbi0: tbi-phy@11 { | ||
| 235 | reg = <0x11>; | ||
| 236 | device_type = "tbi-phy"; | ||
| 237 | }; | ||
| 238 | }; | ||
| 239 | }; | ||
| 240 | |||
| 241 | enet1: ethernet@25000 { | ||
| 242 | #address-cells = <1>; | ||
| 243 | #size-cells = <1>; | ||
| 244 | cell-index = <1>; | ||
| 245 | device_type = "network"; | ||
| 246 | model = "TSEC"; | ||
| 247 | compatible = "gianfar"; | ||
| 248 | reg = <0x25000 0x1000>; | ||
| 249 | ranges = <0x0 0x25000 0x1000>; | ||
| 250 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 251 | interrupts = <35 2 36 2 40 2>; | ||
| 252 | interrupt-parent = <&mpic>; | ||
| 253 | tbi-handle = <&tbi1>; | ||
| 254 | phy-handle = <&phy1>; | ||
| 255 | phy-connection-type = "rgmii-id"; | ||
| 256 | |||
| 257 | mdio@520 { | ||
| 258 | #address-cells = <1>; | ||
| 259 | #size-cells = <0>; | ||
| 260 | compatible = "fsl,gianfar-tbi"; | ||
| 261 | reg = <0x520 0x20>; | ||
| 262 | |||
| 263 | tbi1: tbi-phy@11 { | ||
| 264 | reg = <0x11>; | ||
| 265 | device_type = "tbi-phy"; | ||
| 266 | }; | ||
| 267 | }; | ||
| 268 | }; | ||
| 269 | |||
| 270 | enet2: ethernet@26000 { | ||
| 271 | #address-cells = <1>; | ||
| 272 | #size-cells = <1>; | ||
| 273 | cell-index = <2>; | ||
| 274 | device_type = "network"; | ||
| 275 | model = "TSEC"; | ||
| 276 | compatible = "gianfar"; | ||
| 277 | reg = <0x26000 0x1000>; | ||
| 278 | ranges = <0x0 0x26000 0x1000>; | ||
| 279 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 280 | interrupts = <31 2 32 2 33 2>; | ||
| 281 | interrupt-parent = <&mpic>; | ||
| 282 | tbi-handle = <&tbi2>; | ||
| 283 | phy-handle = <&phy2>; | ||
| 284 | phy-connection-type = "rgmii-id"; | ||
| 285 | |||
| 286 | mdio@520 { | ||
| 287 | #address-cells = <1>; | ||
| 288 | #size-cells = <0>; | ||
| 289 | compatible = "fsl,gianfar-tbi"; | ||
| 290 | reg = <0x520 0x20>; | ||
| 291 | |||
| 292 | tbi2: tbi-phy@11 { | ||
| 293 | reg = <0x11>; | ||
| 294 | device_type = "tbi-phy"; | ||
| 295 | }; | ||
| 296 | }; | ||
| 297 | }; | ||
| 298 | |||
| 299 | enet3: ethernet@27000 { | ||
| 300 | #address-cells = <1>; | ||
| 301 | #size-cells = <1>; | ||
| 302 | cell-index = <3>; | ||
| 303 | device_type = "network"; | ||
| 304 | model = "TSEC"; | ||
| 305 | compatible = "gianfar"; | ||
| 306 | reg = <0x27000 0x1000>; | ||
| 307 | ranges = <0x0 0x27000 0x1000>; | ||
| 308 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 309 | interrupts = <37 2 38 2 39 2>; | ||
| 310 | interrupt-parent = <&mpic>; | ||
| 311 | tbi-handle = <&tbi3>; | ||
| 312 | phy-handle = <&phy3>; | ||
| 313 | phy-connection-type = "rgmii-id"; | ||
| 314 | |||
| 315 | mdio@520 { | ||
| 316 | #address-cells = <1>; | ||
| 317 | #size-cells = <0>; | ||
| 318 | compatible = "fsl,gianfar-tbi"; | ||
| 319 | reg = <0x520 0x20>; | ||
| 320 | |||
| 321 | tbi3: tbi-phy@11 { | ||
| 322 | reg = <0x11>; | ||
| 323 | device_type = "tbi-phy"; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | }; | ||
| 327 | |||
| 328 | serial0: serial@4500 { | ||
| 329 | cell-index = <0>; | ||
| 330 | device_type = "serial"; | ||
| 331 | compatible = "ns16550"; | ||
| 332 | reg = <0x4500 0x100>; | ||
| 333 | clock-frequency = <0>; | ||
| 334 | interrupts = <42 2>; | ||
| 335 | interrupt-parent = <&mpic>; | ||
| 336 | }; | ||
| 337 | |||
| 338 | serial1: serial@4600 { | ||
| 339 | cell-index = <1>; | ||
| 340 | device_type = "serial"; | ||
| 341 | compatible = "ns16550"; | ||
| 342 | reg = <0x4600 0x100>; | ||
| 343 | clock-frequency = <0>; | ||
| 344 | interrupts = <28 2>; | ||
| 345 | interrupt-parent = <&mpic>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | mpic: pic@40000 { | ||
| 349 | interrupt-controller; | ||
| 350 | #address-cells = <0>; | ||
| 351 | #interrupt-cells = <2>; | ||
| 352 | reg = <0x40000 0x40000>; | ||
| 353 | compatible = "chrp,open-pic"; | ||
| 354 | device_type = "open-pic"; | ||
| 355 | }; | ||
| 356 | |||
| 357 | global-utilities@e0000 { | ||
| 358 | compatible = "fsl,mpc8641-guts"; | ||
| 359 | reg = <0xe0000 0x1000>; | ||
| 360 | fsl,has-rstcr; | ||
| 361 | }; | ||
| 362 | }; | ||
| 363 | |||
| 364 | pci0: pcie@fffe08000 { | ||
| 365 | cell-index = <0>; | ||
| 366 | compatible = "fsl,mpc8641-pcie"; | ||
| 367 | device_type = "pci"; | ||
| 368 | #interrupt-cells = <1>; | ||
| 369 | #size-cells = <2>; | ||
| 370 | #address-cells = <3>; | ||
| 371 | reg = <0x0f 0xffe08000 0x0 0x1000>; | ||
| 372 | bus-range = <0x0 0xff>; | ||
| 373 | ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 | ||
| 374 | 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; | ||
| 375 | clock-frequency = <33333333>; | ||
| 376 | interrupt-parent = <&mpic>; | ||
| 377 | interrupts = <24 2>; | ||
| 378 | interrupt-map-mask = <0xff00 0 0 7>; | ||
| 379 | interrupt-map = < | ||
| 380 | /* IDSEL 0x11 func 0 - PCI slot 1 */ | ||
| 381 | 0x8800 0 0 1 &mpic 2 1 | ||
| 382 | 0x8800 0 0 2 &mpic 3 1 | ||
| 383 | 0x8800 0 0 3 &mpic 4 1 | ||
| 384 | 0x8800 0 0 4 &mpic 1 1 | ||
| 385 | |||
| 386 | /* IDSEL 0x11 func 1 - PCI slot 1 */ | ||
| 387 | 0x8900 0 0 1 &mpic 2 1 | ||
| 388 | 0x8900 0 0 2 &mpic 3 1 | ||
| 389 | 0x8900 0 0 3 &mpic 4 1 | ||
| 390 | 0x8900 0 0 4 &mpic 1 1 | ||
| 391 | |||
| 392 | /* IDSEL 0x11 func 2 - PCI slot 1 */ | ||
| 393 | 0x8a00 0 0 1 &mpic 2 1 | ||
| 394 | 0x8a00 0 0 2 &mpic 3 1 | ||
| 395 | 0x8a00 0 0 3 &mpic 4 1 | ||
| 396 | 0x8a00 0 0 4 &mpic 1 1 | ||
| 397 | |||
| 398 | /* IDSEL 0x11 func 3 - PCI slot 1 */ | ||
| 399 | 0x8b00 0 0 1 &mpic 2 1 | ||
| 400 | 0x8b00 0 0 2 &mpic 3 1 | ||
| 401 | 0x8b00 0 0 3 &mpic 4 1 | ||
| 402 | 0x8b00 0 0 4 &mpic 1 1 | ||
| 403 | |||
| 404 | /* IDSEL 0x11 func 4 - PCI slot 1 */ | ||
| 405 | 0x8c00 0 0 1 &mpic 2 1 | ||
| 406 | 0x8c00 0 0 2 &mpic 3 1 | ||
| 407 | 0x8c00 0 0 3 &mpic 4 1 | ||
| 408 | 0x8c00 0 0 4 &mpic 1 1 | ||
| 409 | |||
| 410 | /* IDSEL 0x11 func 5 - PCI slot 1 */ | ||
| 411 | 0x8d00 0 0 1 &mpic 2 1 | ||
| 412 | 0x8d00 0 0 2 &mpic 3 1 | ||
| 413 | 0x8d00 0 0 3 &mpic 4 1 | ||
| 414 | 0x8d00 0 0 4 &mpic 1 1 | ||
| 415 | |||
| 416 | /* IDSEL 0x11 func 6 - PCI slot 1 */ | ||
| 417 | 0x8e00 0 0 1 &mpic 2 1 | ||
| 418 | 0x8e00 0 0 2 &mpic 3 1 | ||
| 419 | 0x8e00 0 0 3 &mpic 4 1 | ||
| 420 | 0x8e00 0 0 4 &mpic 1 1 | ||
| 421 | |||
| 422 | /* IDSEL 0x11 func 7 - PCI slot 1 */ | ||
| 423 | 0x8f00 0 0 1 &mpic 2 1 | ||
| 424 | 0x8f00 0 0 2 &mpic 3 1 | ||
| 425 | 0x8f00 0 0 3 &mpic 4 1 | ||
| 426 | 0x8f00 0 0 4 &mpic 1 1 | ||
| 427 | |||
| 428 | /* IDSEL 0x12 func 0 - PCI slot 2 */ | ||
| 429 | 0x9000 0 0 1 &mpic 3 1 | ||
| 430 | 0x9000 0 0 2 &mpic 4 1 | ||
| 431 | 0x9000 0 0 3 &mpic 1 1 | ||
| 432 | 0x9000 0 0 4 &mpic 2 1 | ||
| 433 | |||
| 434 | /* IDSEL 0x12 func 1 - PCI slot 2 */ | ||
| 435 | 0x9100 0 0 1 &mpic 3 1 | ||
| 436 | 0x9100 0 0 2 &mpic 4 1 | ||
| 437 | 0x9100 0 0 3 &mpic 1 1 | ||
| 438 | 0x9100 0 0 4 &mpic 2 1 | ||
| 439 | |||
| 440 | /* IDSEL 0x12 func 2 - PCI slot 2 */ | ||
| 441 | 0x9200 0 0 1 &mpic 3 1 | ||
| 442 | 0x9200 0 0 2 &mpic 4 1 | ||
| 443 | 0x9200 0 0 3 &mpic 1 1 | ||
| 444 | 0x9200 0 0 4 &mpic 2 1 | ||
| 445 | |||
| 446 | /* IDSEL 0x12 func 3 - PCI slot 2 */ | ||
| 447 | 0x9300 0 0 1 &mpic 3 1 | ||
| 448 | 0x9300 0 0 2 &mpic 4 1 | ||
| 449 | 0x9300 0 0 3 &mpic 1 1 | ||
| 450 | 0x9300 0 0 4 &mpic 2 1 | ||
| 451 | |||
| 452 | /* IDSEL 0x12 func 4 - PCI slot 2 */ | ||
| 453 | 0x9400 0 0 1 &mpic 3 1 | ||
| 454 | 0x9400 0 0 2 &mpic 4 1 | ||
| 455 | 0x9400 0 0 3 &mpic 1 1 | ||
| 456 | 0x9400 0 0 4 &mpic 2 1 | ||
| 457 | |||
| 458 | /* IDSEL 0x12 func 5 - PCI slot 2 */ | ||
| 459 | 0x9500 0 0 1 &mpic 3 1 | ||
| 460 | 0x9500 0 0 2 &mpic 4 1 | ||
| 461 | 0x9500 0 0 3 &mpic 1 1 | ||
| 462 | 0x9500 0 0 4 &mpic 2 1 | ||
| 463 | |||
| 464 | /* IDSEL 0x12 func 6 - PCI slot 2 */ | ||
| 465 | 0x9600 0 0 1 &mpic 3 1 | ||
| 466 | 0x9600 0 0 2 &mpic 4 1 | ||
| 467 | 0x9600 0 0 3 &mpic 1 1 | ||
| 468 | 0x9600 0 0 4 &mpic 2 1 | ||
| 469 | |||
| 470 | /* IDSEL 0x12 func 7 - PCI slot 2 */ | ||
| 471 | 0x9700 0 0 1 &mpic 3 1 | ||
| 472 | 0x9700 0 0 2 &mpic 4 1 | ||
| 473 | 0x9700 0 0 3 &mpic 1 1 | ||
| 474 | 0x9700 0 0 4 &mpic 2 1 | ||
| 475 | |||
| 476 | // IDSEL 0x1c USB | ||
| 477 | 0xe000 0 0 1 &i8259 12 2 | ||
| 478 | 0xe100 0 0 2 &i8259 9 2 | ||
| 479 | 0xe200 0 0 3 &i8259 10 2 | ||
| 480 | 0xe300 0 0 4 &i8259 11 2 | ||
| 481 | |||
| 482 | // IDSEL 0x1d Audio | ||
| 483 | 0xe800 0 0 1 &i8259 6 2 | ||
| 484 | |||
| 485 | // IDSEL 0x1e Legacy | ||
| 486 | 0xf000 0 0 1 &i8259 7 2 | ||
| 487 | 0xf100 0 0 1 &i8259 7 2 | ||
| 488 | |||
| 489 | // IDSEL 0x1f IDE/SATA | ||
| 490 | 0xf800 0 0 1 &i8259 14 2 | ||
| 491 | 0xf900 0 0 1 &i8259 5 2 | ||
| 492 | >; | ||
| 493 | |||
| 494 | pcie@0 { | ||
| 495 | reg = <0 0 0 0 0>; | ||
| 496 | #size-cells = <2>; | ||
| 497 | #address-cells = <3>; | ||
| 498 | device_type = "pci"; | ||
| 499 | ranges = <0x02000000 0x0 0xe0000000 | ||
| 500 | 0x02000000 0x0 0xe0000000 | ||
| 501 | 0x0 0x20000000 | ||
| 502 | |||
| 503 | 0x01000000 0x0 0x00000000 | ||
| 504 | 0x01000000 0x0 0x00000000 | ||
| 505 | 0x0 0x00010000>; | ||
| 506 | uli1575@0 { | ||
| 507 | reg = <0 0 0 0 0>; | ||
| 508 | #size-cells = <2>; | ||
| 509 | #address-cells = <3>; | ||
| 510 | ranges = <0x02000000 0x0 0xe0000000 | ||
| 511 | 0x02000000 0x0 0xe0000000 | ||
| 512 | 0x0 0x20000000 | ||
| 513 | 0x01000000 0x0 0x00000000 | ||
| 514 | 0x01000000 0x0 0x00000000 | ||
| 515 | 0x0 0x00010000>; | ||
| 516 | isa@1e { | ||
| 517 | device_type = "isa"; | ||
| 518 | #interrupt-cells = <2>; | ||
| 519 | #size-cells = <1>; | ||
| 520 | #address-cells = <2>; | ||
| 521 | reg = <0xf000 0 0 0 0>; | ||
| 522 | ranges = <1 0 0x01000000 0 0 | ||
| 523 | 0x00001000>; | ||
| 524 | interrupt-parent = <&i8259>; | ||
| 525 | |||
| 526 | i8259: interrupt-controller@20 { | ||
| 527 | reg = <1 0x20 2 | ||
| 528 | 1 0xa0 2 | ||
| 529 | 1 0x4d0 2>; | ||
| 530 | interrupt-controller; | ||
| 531 | device_type = "interrupt-controller"; | ||
| 532 | #address-cells = <0>; | ||
| 533 | #interrupt-cells = <2>; | ||
| 534 | compatible = "chrp,iic"; | ||
| 535 | interrupts = <9 2>; | ||
| 536 | interrupt-parent = <&mpic>; | ||
| 537 | }; | ||
| 538 | |||
| 539 | i8042@60 { | ||
| 540 | #size-cells = <0>; | ||
| 541 | #address-cells = <1>; | ||
| 542 | reg = <1 0x60 1 1 0x64 1>; | ||
| 543 | interrupts = <1 3 12 3>; | ||
| 544 | interrupt-parent = | ||
| 545 | <&i8259>; | ||
| 546 | |||
| 547 | keyboard@0 { | ||
| 548 | reg = <0>; | ||
| 549 | compatible = "pnpPNP,303"; | ||
| 550 | }; | ||
| 551 | |||
| 552 | mouse@1 { | ||
| 553 | reg = <1>; | ||
| 554 | compatible = "pnpPNP,f03"; | ||
| 555 | }; | ||
| 556 | }; | ||
| 557 | |||
| 558 | rtc@70 { | ||
| 559 | compatible = | ||
| 560 | "pnpPNP,b00"; | ||
| 561 | reg = <1 0x70 2>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | gpio@400 { | ||
| 565 | reg = <1 0x400 0x80>; | ||
| 566 | }; | ||
| 567 | }; | ||
| 568 | }; | ||
| 569 | }; | ||
| 570 | |||
| 571 | }; | ||
| 572 | |||
| 573 | pci1: pcie@fffe09000 { | ||
| 574 | cell-index = <1>; | ||
| 575 | compatible = "fsl,mpc8641-pcie"; | ||
| 576 | device_type = "pci"; | ||
| 577 | #interrupt-cells = <1>; | ||
| 578 | #size-cells = <2>; | ||
| 579 | #address-cells = <3>; | ||
| 580 | reg = <0x0f 0xffe09000 0x0 0x1000>; | ||
| 581 | bus-range = <0x0 0xff>; | ||
| 582 | ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 | ||
| 583 | 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; | ||
| 584 | clock-frequency = <33333333>; | ||
| 585 | interrupt-parent = <&mpic>; | ||
| 586 | interrupts = <25 2>; | ||
| 587 | interrupt-map-mask = <0xf800 0 0 7>; | ||
| 588 | interrupt-map = < | ||
| 589 | /* IDSEL 0x0 */ | ||
| 590 | 0x0000 0 0 1 &mpic 4 1 | ||
| 591 | 0x0000 0 0 2 &mpic 5 1 | ||
| 592 | 0x0000 0 0 3 &mpic 6 1 | ||
| 593 | 0x0000 0 0 4 &mpic 7 1 | ||
| 594 | >; | ||
| 595 | pcie@0 { | ||
| 596 | reg = <0 0 0 0 0>; | ||
| 597 | #size-cells = <2>; | ||
| 598 | #address-cells = <3>; | ||
| 599 | device_type = "pci"; | ||
| 600 | ranges = <0x02000000 0x0 0xe0000000 | ||
| 601 | 0x02000000 0x0 0xe0000000 | ||
| 602 | 0x0 0x20000000 | ||
| 603 | |||
| 604 | 0x01000000 0x0 0x00000000 | ||
| 605 | 0x01000000 0x0 0x00000000 | ||
| 606 | 0x0 0x00010000>; | ||
| 607 | }; | ||
| 608 | }; | ||
| 609 | }; | ||
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts new file mode 100644 index 000000000000..11019142813c --- /dev/null +++ b/arch/powerpc/boot/dts/p2020ds.dts | |||
| @@ -0,0 +1,704 @@ | |||
| 1 | /* | ||
| 2 | * P2020 DS Device Tree Source | ||
| 3 | * | ||
| 4 | * Copyright 2009 Freescale Semiconductor Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | model = "fsl,P2020"; | ||
| 15 | compatible = "fsl,P2020DS"; | ||
| 16 | #address-cells = <2>; | ||
| 17 | #size-cells = <2>; | ||
| 18 | |||
| 19 | aliases { | ||
| 20 | ethernet0 = &enet0; | ||
| 21 | ethernet1 = &enet1; | ||
| 22 | ethernet2 = &enet2; | ||
| 23 | serial0 = &serial0; | ||
| 24 | serial1 = &serial1; | ||
| 25 | pci0 = &pci0; | ||
| 26 | pci1 = &pci1; | ||
| 27 | pci2 = &pci2; | ||
| 28 | }; | ||
| 29 | |||
| 30 | cpus { | ||
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <0>; | ||
| 33 | |||
| 34 | PowerPC,P2020@0 { | ||
| 35 | device_type = "cpu"; | ||
| 36 | reg = <0x0>; | ||
| 37 | next-level-cache = <&L2>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | PowerPC,P2020@1 { | ||
| 41 | device_type = "cpu"; | ||
| 42 | reg = <0x1>; | ||
| 43 | next-level-cache = <&L2>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 47 | memory { | ||
| 48 | device_type = "memory"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | localbus@ffe05000 { | ||
| 52 | #address-cells = <2>; | ||
| 53 | #size-cells = <1>; | ||
| 54 | compatible = "fsl,elbc", "simple-bus"; | ||
| 55 | reg = <0 0xffe05000 0 0x1000>; | ||
| 56 | interrupts = <19 2>; | ||
| 57 | interrupt-parent = <&mpic>; | ||
| 58 | |||
| 59 | ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 | ||
| 60 | 0x1 0x0 0x0 0xe0000000 0x08000000 | ||
| 61 | 0x2 0x0 0x0 0xffa00000 0x00040000 | ||
| 62 | 0x3 0x0 0x0 0xffdf0000 0x00008000 | ||
| 63 | 0x4 0x0 0x0 0xffa40000 0x00040000 | ||
| 64 | 0x5 0x0 0x0 0xffa80000 0x00040000 | ||
| 65 | 0x6 0x0 0x0 0xffac0000 0x00040000>; | ||
| 66 | |||
| 67 | nor@0,0 { | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <1>; | ||
| 70 | compatible = "cfi-flash"; | ||
| 71 | reg = <0x0 0x0 0x8000000>; | ||
| 72 | bank-width = <2>; | ||
| 73 | device-width = <1>; | ||
| 74 | |||
| 75 | ramdisk@0 { | ||
| 76 | reg = <0x0 0x03000000>; | ||
| 77 | read-only; | ||
| 78 | }; | ||
| 79 | |||
| 80 | diagnostic@3000000 { | ||
| 81 | reg = <0x03000000 0x00e00000>; | ||
| 82 | read-only; | ||
| 83 | }; | ||
| 84 | |||
| 85 | dink@3e00000 { | ||
| 86 | reg = <0x03e00000 0x00200000>; | ||
| 87 | read-only; | ||
| 88 | }; | ||
| 89 | |||
| 90 | kernel@4000000 { | ||
| 91 | reg = <0x04000000 0x00400000>; | ||
| 92 | read-only; | ||
| 93 | }; | ||
| 94 | |||
| 95 | jffs2@4400000 { | ||
| 96 | reg = <0x04400000 0x03b00000>; | ||
| 97 | }; | ||
| 98 | |||
| 99 | dtb@7f00000 { | ||
| 100 | reg = <0x07f00000 0x00080000>; | ||
| 101 | read-only; | ||
| 102 | }; | ||
| 103 | |||
| 104 | u-boot@7f80000 { | ||
| 105 | reg = <0x07f80000 0x00080000>; | ||
| 106 | read-only; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | |||
| 110 | nand@2,0 { | ||
| 111 | #address-cells = <1>; | ||
| 112 | #size-cells = <1>; | ||
| 113 | compatible = "fsl,elbc-fcm-nand"; | ||
| 114 | reg = <0x2 0x0 0x40000>; | ||
| 115 | |||
| 116 | u-boot@0 { | ||
| 117 | reg = <0x0 0x02000000>; | ||
| 118 | read-only; | ||
| 119 | }; | ||
| 120 | |||
| 121 | jffs2@2000000 { | ||
| 122 | reg = <0x02000000 0x10000000>; | ||
| 123 | }; | ||
| 124 | |||
| 125 | ramdisk@12000000 { | ||
| 126 | reg = <0x12000000 0x08000000>; | ||
| 127 | read-only; | ||
| 128 | }; | ||
| 129 | |||
| 130 | kernel@1a000000 { | ||
| 131 | reg = <0x1a000000 0x04000000>; | ||
| 132 | }; | ||
| 133 | |||
| 134 | dtb@1e000000 { | ||
| 135 | reg = <0x1e000000 0x01000000>; | ||
| 136 | read-only; | ||
| 137 | }; | ||
| 138 | |||
| 139 | empty@1f000000 { | ||
| 140 | reg = <0x1f000000 0x21000000>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | nand@4,0 { | ||
| 145 | compatible = "fsl,elbc-fcm-nand"; | ||
| 146 | reg = <0x4 0x0 0x40000>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | nand@5,0 { | ||
| 150 | compatible = "fsl,elbc-fcm-nand"; | ||
| 151 | reg = <0x5 0x0 0x40000>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | nand@6,0 { | ||
| 155 | compatible = "fsl,elbc-fcm-nand"; | ||
| 156 | reg = <0x6 0x0 0x40000>; | ||
| 157 | }; | ||
| 158 | }; | ||
| 159 | |||
| 160 | soc@ffe00000 { | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <1>; | ||
| 163 | device_type = "soc"; | ||
| 164 | compatible = "fsl,p2020-immr", "simple-bus"; | ||
| 165 | ranges = <0x0 0 0xffe00000 0x100000>; | ||
| 166 | bus-frequency = <0>; // Filled out by uboot. | ||
| 167 | |||
| 168 | ecm-law@0 { | ||
| 169 | compatible = "fsl,ecm-law"; | ||
| 170 | reg = <0x0 0x1000>; | ||
| 171 | fsl,num-laws = <12>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | ecm@1000 { | ||
| 175 | compatible = "fsl,p2020-ecm", "fsl,ecm"; | ||
| 176 | reg = <0x1000 0x1000>; | ||
| 177 | interrupts = <17 2>; | ||
| 178 | interrupt-parent = <&mpic>; | ||
| 179 | }; | ||
| 180 | |||
| 181 | memory-controller@2000 { | ||
| 182 | compatible = "fsl,p2020-memory-controller"; | ||
| 183 | reg = <0x2000 0x1000>; | ||
| 184 | interrupt-parent = <&mpic>; | ||
| 185 | interrupts = <18 2>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | i2c@3000 { | ||
| 189 | #address-cells = <1>; | ||
| 190 | #size-cells = <0>; | ||
| 191 | cell-index = <0>; | ||
| 192 | compatible = "fsl-i2c"; | ||
| 193 | reg = <0x3000 0x100>; | ||
| 194 | interrupts = <43 2>; | ||
| 195 | interrupt-parent = <&mpic>; | ||
| 196 | dfsrr; | ||
| 197 | }; | ||
| 198 | |||
| 199 | i2c@3100 { | ||
| 200 | #address-cells = <1>; | ||
| 201 | #size-cells = <0>; | ||
| 202 | cell-index = <1>; | ||
| 203 | compatible = "fsl-i2c"; | ||
| 204 | reg = <0x3100 0x100>; | ||
| 205 | interrupts = <43 2>; | ||
| 206 | interrupt-parent = <&mpic>; | ||
| 207 | dfsrr; | ||
| 208 | }; | ||
| 209 | |||
| 210 | serial0: serial@4500 { | ||
| 211 | cell-index = <0>; | ||
| 212 | device_type = "serial"; | ||
| 213 | compatible = "ns16550"; | ||
| 214 | reg = <0x4500 0x100>; | ||
| 215 | clock-frequency = <0>; | ||
| 216 | interrupts = <42 2>; | ||
| 217 | interrupt-parent = <&mpic>; | ||
| 218 | }; | ||
| 219 | |||
| 220 | serial1: serial@4600 { | ||
| 221 | cell-index = <1>; | ||
| 222 | device_type = "serial"; | ||
| 223 | compatible = "ns16550"; | ||
| 224 | reg = <0x4600 0x100>; | ||
| 225 | clock-frequency = <0>; | ||
| 226 | interrupts = <42 2>; | ||
| 227 | interrupt-parent = <&mpic>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | spi@7000 { | ||
| 231 | compatible = "fsl,espi"; | ||
| 232 | reg = <0x7000 0x1000>; | ||
| 233 | interrupts = <59 0x2>; | ||
| 234 | interrupt-parent = <&mpic>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | dma@c300 { | ||
| 238 | #address-cells = <1>; | ||
| 239 | #size-cells = <1>; | ||
| 240 | compatible = "fsl,eloplus-dma"; | ||
| 241 | reg = <0xc300 0x4>; | ||
| 242 | ranges = <0x0 0xc100 0x200>; | ||
| 243 | cell-index = <1>; | ||
| 244 | dma-channel@0 { | ||
| 245 | compatible = "fsl,eloplus-dma-channel"; | ||
| 246 | reg = <0x0 0x80>; | ||
| 247 | cell-index = <0>; | ||
| 248 | interrupt-parent = <&mpic>; | ||
| 249 | interrupts = <76 2>; | ||
| 250 | }; | ||
| 251 | dma-channel@80 { | ||
| 252 | compatible = "fsl,eloplus-dma-channel"; | ||
| 253 | reg = <0x80 0x80>; | ||
| 254 | cell-index = <1>; | ||
| 255 | interrupt-parent = <&mpic>; | ||
| 256 | interrupts = <77 2>; | ||
| 257 | }; | ||
| 258 | dma-channel@100 { | ||
| 259 | compatible = "fsl,eloplus-dma-channel"; | ||
| 260 | reg = <0x100 0x80>; | ||
| 261 | cell-index = <2>; | ||
| 262 | interrupt-parent = <&mpic>; | ||
| 263 | interrupts = <78 2>; | ||
| 264 | }; | ||
| 265 | dma-channel@180 { | ||
| 266 | compatible = "fsl,eloplus-dma-channel"; | ||
| 267 | reg = <0x180 0x80>; | ||
| 268 | cell-index = <3>; | ||
| 269 | interrupt-parent = <&mpic>; | ||
| 270 | interrupts = <79 2>; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | |||
| 274 | gpio: gpio-controller@f000 { | ||
| 275 | #gpio-cells = <2>; | ||
| 276 | compatible = "fsl,mpc8572-gpio"; | ||
| 277 | reg = <0xf000 0x100>; | ||
| 278 | interrupts = <47 0x2>; | ||
| 279 | interrupt-parent = <&mpic>; | ||
| 280 | gpio-controller; | ||
| 281 | }; | ||
| 282 | |||
| 283 | L2: l2-cache-controller@20000 { | ||
| 284 | compatible = "fsl,p2020-l2-cache-controller"; | ||
| 285 | reg = <0x20000 0x1000>; | ||
| 286 | cache-line-size = <32>; // 32 bytes | ||
| 287 | cache-size = <0x80000>; // L2, 512k | ||
| 288 | interrupt-parent = <&mpic>; | ||
| 289 | interrupts = <16 2>; | ||
| 290 | }; | ||
| 291 | |||
| 292 | dma@21300 { | ||
| 293 | #address-cells = <1>; | ||
| 294 | #size-cells = <1>; | ||
| 295 | compatible = "fsl,eloplus-dma"; | ||
| 296 | reg = <0x21300 0x4>; | ||
| 297 | ranges = <0x0 0x21100 0x200>; | ||
| 298 | cell-index = <0>; | ||
| 299 | dma-channel@0 { | ||
| 300 | compatible = "fsl,eloplus-dma-channel"; | ||
| 301 | reg = <0x0 0x80>; | ||
| 302 | cell-index = <0>; | ||
| 303 | interrupt-parent = <&mpic>; | ||
| 304 | interrupts = <20 2>; | ||
| 305 | }; | ||
| 306 | dma-channel@80 { | ||
| 307 | compatible = "fsl,eloplus-dma-channel"; | ||
| 308 | reg = <0x80 0x80>; | ||
| 309 | cell-index = <1>; | ||
| 310 | interrupt-parent = <&mpic>; | ||
| 311 | interrupts = <21 2>; | ||
| 312 | }; | ||
| 313 | dma-channel@100 { | ||
| 314 | compatible = "fsl,eloplus-dma-channel"; | ||
| 315 | reg = <0x100 0x80>; | ||
| 316 | cell-index = <2>; | ||
| 317 | interrupt-parent = <&mpic>; | ||
| 318 | interrupts = <22 2>; | ||
| 319 | }; | ||
| 320 | dma-channel@180 { | ||
| 321 | compatible = "fsl,eloplus-dma-channel"; | ||
| 322 | reg = <0x180 0x80>; | ||
| 323 | cell-index = <3>; | ||
| 324 | interrupt-parent = <&mpic>; | ||
| 325 | interrupts = <23 2>; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | |||
| 329 | usb@22000 { | ||
| 330 | #address-cells = <1>; | ||
| 331 | #size-cells = <0>; | ||
| 332 | compatible = "fsl-usb2-dr"; | ||
| 333 | reg = <0x22000 0x1000>; | ||
| 334 | interrupt-parent = <&mpic>; | ||
| 335 | interrupts = <28 0x2>; | ||
| 336 | phy_type = "ulpi"; | ||
| 337 | }; | ||
| 338 | |||
| 339 | enet0: ethernet@24000 { | ||
| 340 | #address-cells = <1>; | ||
| 341 | #size-cells = <1>; | ||
| 342 | cell-index = <0>; | ||
| 343 | device_type = "network"; | ||
| 344 | model = "eTSEC"; | ||
| 345 | compatible = "gianfar"; | ||
| 346 | reg = <0x24000 0x1000>; | ||
| 347 | ranges = <0x0 0x24000 0x1000>; | ||
| 348 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 349 | interrupts = <29 2 30 2 34 2>; | ||
| 350 | interrupt-parent = <&mpic>; | ||
| 351 | tbi-handle = <&tbi0>; | ||
| 352 | phy-handle = <&phy0>; | ||
| 353 | phy-connection-type = "rgmii-id"; | ||
| 354 | |||
| 355 | mdio@520 { | ||
| 356 | #address-cells = <1>; | ||
| 357 | #size-cells = <0>; | ||
| 358 | compatible = "fsl,gianfar-mdio"; | ||
| 359 | reg = <0x520 0x20>; | ||
| 360 | |||
| 361 | phy0: ethernet-phy@0 { | ||
| 362 | interrupt-parent = <&mpic>; | ||
| 363 | interrupts = <3 1>; | ||
| 364 | reg = <0x0>; | ||
| 365 | }; | ||
| 366 | phy1: ethernet-phy@1 { | ||
| 367 | interrupt-parent = <&mpic>; | ||
| 368 | interrupts = <3 1>; | ||
| 369 | reg = <0x1>; | ||
| 370 | }; | ||
| 371 | phy2: ethernet-phy@2 { | ||
| 372 | interrupt-parent = <&mpic>; | ||
| 373 | interrupts = <3 1>; | ||
| 374 | reg = <0x2>; | ||
| 375 | }; | ||
| 376 | tbi0: tbi-phy@11 { | ||
| 377 | reg = <0x11>; | ||
| 378 | device_type = "tbi-phy"; | ||
| 379 | }; | ||
| 380 | }; | ||
| 381 | }; | ||
| 382 | |||
| 383 | enet1: ethernet@25000 { | ||
| 384 | #address-cells = <1>; | ||
| 385 | #size-cells = <1>; | ||
| 386 | cell-index = <1>; | ||
| 387 | device_type = "network"; | ||
| 388 | model = "eTSEC"; | ||
| 389 | compatible = "gianfar"; | ||
| 390 | reg = <0x25000 0x1000>; | ||
| 391 | ranges = <0x0 0x25000 0x1000>; | ||
| 392 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 393 | interrupts = <35 2 36 2 40 2>; | ||
| 394 | interrupt-parent = <&mpic>; | ||
| 395 | tbi-handle = <&tbi1>; | ||
| 396 | phy-handle = <&phy1>; | ||
| 397 | phy-connection-type = "rgmii-id"; | ||
| 398 | |||
| 399 | mdio@520 { | ||
| 400 | #address-cells = <1>; | ||
| 401 | #size-cells = <0>; | ||
| 402 | compatible = "fsl,gianfar-tbi"; | ||
| 403 | reg = <0x520 0x20>; | ||
| 404 | |||
| 405 | tbi1: tbi-phy@11 { | ||
| 406 | reg = <0x11>; | ||
| 407 | device_type = "tbi-phy"; | ||
| 408 | }; | ||
| 409 | }; | ||
| 410 | }; | ||
| 411 | |||
| 412 | enet2: ethernet@26000 { | ||
| 413 | #address-cells = <1>; | ||
| 414 | #size-cells = <1>; | ||
| 415 | cell-index = <2>; | ||
| 416 | device_type = "network"; | ||
| 417 | model = "eTSEC"; | ||
| 418 | compatible = "gianfar"; | ||
| 419 | reg = <0x26000 0x1000>; | ||
| 420 | ranges = <0x0 0x26000 0x1000>; | ||
| 421 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 422 | interrupts = <31 2 32 2 33 2>; | ||
| 423 | interrupt-parent = <&mpic>; | ||
| 424 | tbi-handle = <&tbi2>; | ||
| 425 | phy-handle = <&phy2>; | ||
| 426 | phy-connection-type = "rgmii-id"; | ||
| 427 | |||
| 428 | mdio@520 { | ||
| 429 | #address-cells = <1>; | ||
| 430 | #size-cells = <0>; | ||
| 431 | compatible = "fsl,gianfar-tbi"; | ||
| 432 | reg = <0x520 0x20>; | ||
| 433 | |||
| 434 | tbi2: tbi-phy@11 { | ||
| 435 | reg = <0x11>; | ||
| 436 | device_type = "tbi-phy"; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | }; | ||
| 440 | |||
| 441 | sdhci@2e000 { | ||
| 442 | compatible = "fsl,p2020-esdhc", "fsl,esdhc"; | ||
| 443 | reg = <0x2e000 0x1000>; | ||
| 444 | interrupts = <72 0x2>; | ||
| 445 | interrupt-parent = <&mpic>; | ||
| 446 | /* Filled in by U-Boot */ | ||
| 447 | clock-frequency = <0>; | ||
| 448 | }; | ||
| 449 | |||
| 450 | crypto@30000 { | ||
| 451 | compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", | ||
| 452 | "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; | ||
| 453 | reg = <0x30000 0x10000>; | ||
| 454 | interrupts = <45 2 58 2>; | ||
| 455 | interrupt-parent = <&mpic>; | ||
| 456 | fsl,num-channels = <4>; | ||
| 457 | fsl,channel-fifo-len = <24>; | ||
| 458 | fsl,exec-units-mask = <0xbfe>; | ||
| 459 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | mpic: pic@40000 { | ||
| 463 | interrupt-controller; | ||
| 464 | #address-cells = <0>; | ||
| 465 | #interrupt-cells = <2>; | ||
| 466 | reg = <0x40000 0x40000>; | ||
| 467 | compatible = "chrp,open-pic"; | ||
| 468 | device_type = "open-pic"; | ||
| 469 | }; | ||
| 470 | |||
| 471 | msi@41600 { | ||
| 472 | compatible = "fsl,mpic-msi"; | ||
| 473 | reg = <0x41600 0x80>; | ||
| 474 | msi-available-ranges = <0 0x100>; | ||
| 475 | interrupts = < | ||
| 476 | 0xe0 0 | ||
| 477 | 0xe1 0 | ||
| 478 | 0xe2 0 | ||
| 479 | 0xe3 0 | ||
| 480 | 0xe4 0 | ||
| 481 | 0xe5 0 | ||
| 482 | 0xe6 0 | ||
| 483 | 0xe7 0>; | ||
| 484 | interrupt-parent = <&mpic>; | ||
| 485 | }; | ||
| 486 | |||
| 487 | global-utilities@e0000 { //global utilities block | ||
| 488 | compatible = "fsl,p2020-guts"; | ||
| 489 | reg = <0xe0000 0x1000>; | ||
| 490 | fsl,has-rstcr; | ||
| 491 | }; | ||
| 492 | }; | ||
| 493 | |||
| 494 | pci0: pcie@ffe08000 { | ||
| 495 | compatible = "fsl,mpc8548-pcie"; | ||
| 496 | device_type = "pci"; | ||
| 497 | #interrupt-cells = <1>; | ||
| 498 | #size-cells = <2>; | ||
| 499 | #address-cells = <3>; | ||
| 500 | reg = <0 0xffe08000 0 0x1000>; | ||
| 501 | bus-range = <0 255>; | ||
| 502 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 | ||
| 503 | 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; | ||
| 504 | clock-frequency = <33333333>; | ||
| 505 | interrupt-parent = <&mpic>; | ||
| 506 | interrupts = <24 2>; | ||
| 507 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 508 | interrupt-map = < | ||
| 509 | /* IDSEL 0x0 */ | ||
| 510 | 0000 0x0 0x0 0x1 &mpic 0x8 0x1 | ||
| 511 | 0000 0x0 0x0 0x2 &mpic 0x9 0x1 | ||
| 512 | 0000 0x0 0x0 0x3 &mpic 0xa 0x1 | ||
| 513 | 0000 0x0 0x0 0x4 &mpic 0xb 0x1 | ||
| 514 | >; | ||
| 515 | pcie@0 { | ||
| 516 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 517 | #size-cells = <2>; | ||
| 518 | #address-cells = <3>; | ||
| 519 | device_type = "pci"; | ||
| 520 | ranges = <0x2000000 0x0 0x80000000 | ||
| 521 | 0x2000000 0x0 0x80000000 | ||
| 522 | 0x0 0x20000000 | ||
| 523 | |||
| 524 | 0x1000000 0x0 0x0 | ||
| 525 | 0x1000000 0x0 0x0 | ||
| 526 | 0x0 0x10000>; | ||
| 527 | }; | ||
| 528 | }; | ||
| 529 | |||
| 530 | pci1: pcie@ffe09000 { | ||
| 531 | compatible = "fsl,mpc8548-pcie"; | ||
| 532 | device_type = "pci"; | ||
| 533 | #interrupt-cells = <1>; | ||
| 534 | #size-cells = <2>; | ||
| 535 | #address-cells = <3>; | ||
| 536 | reg = <0 0xffe09000 0 0x1000>; | ||
| 537 | bus-range = <0 255>; | ||
| 538 | ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 | ||
| 539 | 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; | ||
| 540 | clock-frequency = <33333333>; | ||
| 541 | interrupt-parent = <&mpic>; | ||
| 542 | interrupts = <25 2>; | ||
| 543 | interrupt-map-mask = <0xff00 0x0 0x0 0x7>; | ||
| 544 | interrupt-map = < | ||
| 545 | |||
| 546 | // IDSEL 0x11 func 0 - PCI slot 1 | ||
| 547 | 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 548 | 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 549 | |||
| 550 | // IDSEL 0x11 func 1 - PCI slot 1 | ||
| 551 | 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 552 | 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 553 | |||
| 554 | // IDSEL 0x11 func 2 - PCI slot 1 | ||
| 555 | 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 556 | 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 557 | |||
| 558 | // IDSEL 0x11 func 3 - PCI slot 1 | ||
| 559 | 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 560 | 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 561 | |||
| 562 | // IDSEL 0x11 func 4 - PCI slot 1 | ||
| 563 | 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 564 | 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 565 | |||
| 566 | // IDSEL 0x11 func 5 - PCI slot 1 | ||
| 567 | 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 568 | 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 569 | |||
| 570 | // IDSEL 0x11 func 6 - PCI slot 1 | ||
| 571 | 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 572 | 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 573 | |||
| 574 | // IDSEL 0x11 func 7 - PCI slot 1 | ||
| 575 | 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2 | ||
| 576 | 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2 | ||
| 577 | |||
| 578 | // IDSEL 0x1d Audio | ||
| 579 | 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 | ||
| 580 | |||
| 581 | // IDSEL 0x1e Legacy | ||
| 582 | 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 | ||
| 583 | 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 | ||
| 584 | |||
| 585 | // IDSEL 0x1f IDE/SATA | ||
| 586 | 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 | ||
| 587 | 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 | ||
| 588 | >; | ||
| 589 | |||
| 590 | pcie@0 { | ||
| 591 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 592 | #size-cells = <2>; | ||
| 593 | #address-cells = <3>; | ||
| 594 | device_type = "pci"; | ||
| 595 | ranges = <0x2000000 0x0 0xa0000000 | ||
| 596 | 0x2000000 0x0 0xa0000000 | ||
| 597 | 0x0 0x20000000 | ||
| 598 | |||
| 599 | 0x1000000 0x0 0x0 | ||
| 600 | 0x1000000 0x0 0x0 | ||
| 601 | 0x0 0x10000>; | ||
| 602 | uli1575@0 { | ||
| 603 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 604 | #size-cells = <2>; | ||
| 605 | #address-cells = <3>; | ||
| 606 | ranges = <0x2000000 0x0 0xa0000000 | ||
| 607 | 0x2000000 0x0 0xa0000000 | ||
| 608 | 0x0 0x20000000 | ||
| 609 | |||
| 610 | 0x1000000 0x0 0x0 | ||
| 611 | 0x1000000 0x0 0x0 | ||
| 612 | 0x0 0x10000>; | ||
| 613 | isa@1e { | ||
| 614 | device_type = "isa"; | ||
| 615 | #interrupt-cells = <2>; | ||
| 616 | #size-cells = <1>; | ||
| 617 | #address-cells = <2>; | ||
| 618 | reg = <0xf000 0x0 0x0 0x0 0x0>; | ||
| 619 | ranges = <0x1 0x0 0x1000000 0x0 0x0 | ||
| 620 | 0x1000>; | ||
| 621 | interrupt-parent = <&i8259>; | ||
| 622 | |||
| 623 | i8259: interrupt-controller@20 { | ||
| 624 | reg = <0x1 0x20 0x2 | ||
| 625 | 0x1 0xa0 0x2 | ||
| 626 | 0x1 0x4d0 0x2>; | ||
| 627 | interrupt-controller; | ||
| 628 | device_type = "interrupt-controller"; | ||
| 629 | #address-cells = <0>; | ||
| 630 | #interrupt-cells = <2>; | ||
| 631 | compatible = "chrp,iic"; | ||
| 632 | interrupts = <4 1>; | ||
| 633 | interrupt-parent = <&mpic>; | ||
| 634 | }; | ||
| 635 | |||
| 636 | i8042@60 { | ||
| 637 | #size-cells = <0>; | ||
| 638 | #address-cells = <1>; | ||
| 639 | reg = <0x1 0x60 0x1 0x1 0x64 0x1>; | ||
| 640 | interrupts = <1 3 12 3>; | ||
| 641 | interrupt-parent = | ||
| 642 | <&i8259>; | ||
| 643 | |||
| 644 | keyboard@0 { | ||
| 645 | reg = <0x0>; | ||
| 646 | compatible = "pnpPNP,303"; | ||
| 647 | }; | ||
| 648 | |||
| 649 | mouse@1 { | ||
| 650 | reg = <0x1>; | ||
| 651 | compatible = "pnpPNP,f03"; | ||
| 652 | }; | ||
| 653 | }; | ||
| 654 | |||
| 655 | rtc@70 { | ||
| 656 | compatible = "pnpPNP,b00"; | ||
| 657 | reg = <0x1 0x70 0x2>; | ||
| 658 | }; | ||
| 659 | |||
| 660 | gpio@400 { | ||
| 661 | reg = <0x1 0x400 0x80>; | ||
| 662 | }; | ||
| 663 | }; | ||
| 664 | }; | ||
| 665 | }; | ||
| 666 | |||
| 667 | }; | ||
| 668 | |||
| 669 | pci2: pcie@ffe0a000 { | ||
| 670 | compatible = "fsl,mpc8548-pcie"; | ||
| 671 | device_type = "pci"; | ||
| 672 | #interrupt-cells = <1>; | ||
| 673 | #size-cells = <2>; | ||
| 674 | #address-cells = <3>; | ||
| 675 | reg = <0 0xffe0a000 0 0x1000>; | ||
| 676 | bus-range = <0 255>; | ||
| 677 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 | ||
| 678 | 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; | ||
| 679 | clock-frequency = <33333333>; | ||
| 680 | interrupt-parent = <&mpic>; | ||
| 681 | interrupts = <26 2>; | ||
| 682 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 683 | interrupt-map = < | ||
| 684 | /* IDSEL 0x0 */ | ||
| 685 | 0000 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 686 | 0000 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 687 | 0000 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 688 | 0000 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 689 | >; | ||
| 690 | pcie@0 { | ||
| 691 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 692 | #size-cells = <2>; | ||
| 693 | #address-cells = <3>; | ||
| 694 | device_type = "pci"; | ||
| 695 | ranges = <0x2000000 0x0 0xc0000000 | ||
| 696 | 0x2000000 0x0 0xc0000000 | ||
| 697 | 0x0 0x20000000 | ||
| 698 | |||
| 699 | 0x1000000 0x0 0x0 | ||
| 700 | 0x1000000 0x0 0x0 | ||
| 701 | 0x0 0x10000>; | ||
| 702 | }; | ||
| 703 | }; | ||
| 704 | }; | ||
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts index 895834713894..30bfdc04c6df 100644 --- a/arch/powerpc/boot/dts/pcm030.dts +++ b/arch/powerpc/boot/dts/pcm030.dts | |||
| @@ -258,34 +258,16 @@ | |||
| 258 | compatible = "nxp,pcf8563"; | 258 | compatible = "nxp,pcf8563"; |
| 259 | reg = <0x51>; | 259 | reg = <0x51>; |
| 260 | }; | 260 | }; |
| 261 | /* FIXME: EEPROM */ | 261 | eeprom@52 { |
| 262 | compatible = "catalyst,24c32"; | ||
| 263 | reg = <0x52>; | ||
| 264 | }; | ||
| 262 | }; | 265 | }; |
| 263 | 266 | ||
| 264 | sram@8000 { | 267 | sram@8000 { |
| 265 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; | 268 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
| 266 | reg = <0x8000 0x4000>; | 269 | reg = <0x8000 0x4000>; |
| 267 | }; | 270 | }; |
| 268 | |||
| 269 | /* This is only an example device to show the usage of gpios. It maps all available | ||
| 270 | * gpios to the "gpio-provider" device. | ||
| 271 | */ | ||
| 272 | gpio { | ||
| 273 | compatible = "gpio-provider"; | ||
| 274 | |||
| 275 | /* mpc52xx exp.con patchfield */ | ||
| 276 | gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */ | ||
| 277 | &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */ | ||
| 278 | &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */ | ||
| 279 | &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */ | ||
| 280 | &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */ | ||
| 281 | &gpt2 0 0 /* timer2 12d x4-4 */ | ||
| 282 | &gpt3 0 0 /* timer3 13d x6-4 */ | ||
| 283 | &gpt4 0 0 /* timer4 61c x2-16 */ | ||
| 284 | &gpt5 0 0 /* timer5 44c x7-11 */ | ||
| 285 | &gpt6 0 0 /* timer6 60c x8-15 */ | ||
| 286 | &gpt7 0 0 /* timer7 36a x17-9 */ | ||
| 287 | >; | ||
| 288 | }; | ||
| 289 | }; | 271 | }; |
| 290 | 272 | ||
| 291 | pci@f0000d00 { | 273 | pci@f0000d00 { |
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index a36dbbc48694..2d9fa68f641c 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts | |||
| @@ -144,7 +144,7 @@ | |||
| 144 | interrupt-parent = <&ipic>; | 144 | interrupt-parent = <&ipic>; |
| 145 | interrupts = <39 0x8>; | 145 | interrupts = <39 0x8>; |
| 146 | phy_type = "ulpi"; | 146 | phy_type = "ulpi"; |
| 147 | port1; | 147 | port0; |
| 148 | }; | 148 | }; |
| 149 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ | 149 | /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ |
| 150 | usb@23000 { | 150 | usb@23000 { |
| @@ -278,7 +278,6 @@ | |||
| 278 | }; | 278 | }; |
| 279 | 279 | ||
| 280 | pci0: pci@e0008500 { | 280 | pci0: pci@e0008500 { |
| 281 | cell-index = <1>; | ||
| 282 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 281 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 283 | interrupt-map = < | 282 | interrupt-map = < |
| 284 | 283 | ||
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index b1f1416ac998..9eefe00ed253 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts | |||
| @@ -151,10 +151,22 @@ | |||
| 151 | #size-cells = <1>; | 151 | #size-cells = <1>; |
| 152 | device_type = "soc"; | 152 | device_type = "soc"; |
| 153 | ranges = <0x00000000 0xe0000000 0x00100000>; | 153 | ranges = <0x00000000 0xe0000000 0x00100000>; |
| 154 | reg = <0xe0000000 0x00001000>; // CCSRBAR | ||
| 155 | bus-frequency = <0>; | 154 | bus-frequency = <0>; |
| 156 | compatible = "simple-bus"; | 155 | compatible = "simple-bus"; |
| 157 | 156 | ||
| 157 | ecm-law@0 { | ||
| 158 | compatible = "fsl,ecm-law"; | ||
| 159 | reg = <0x0 0x1000>; | ||
| 160 | fsl,num-laws = <10>; | ||
| 161 | }; | ||
| 162 | |||
| 163 | ecm@1000 { | ||
| 164 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 165 | reg = <0x1000 0x1000>; | ||
| 166 | interrupts = <17 2>; | ||
| 167 | interrupt-parent = <&mpic>; | ||
| 168 | }; | ||
| 169 | |||
| 158 | memory-controller@2000 { | 170 | memory-controller@2000 { |
| 159 | compatible = "fsl,mpc8548-memory-controller"; | 171 | compatible = "fsl,mpc8548-memory-controller"; |
| 160 | reg = <0x2000 0x1000>; | 172 | reg = <0x2000 0x1000>; |
| @@ -350,7 +362,6 @@ | |||
| 350 | }; | 362 | }; |
| 351 | 363 | ||
| 352 | pci0: pci@e0008000 { | 364 | pci0: pci@e0008000 { |
| 353 | cell-index = <0>; | ||
| 354 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 365 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 355 | interrupt-map = < | 366 | interrupt-map = < |
| 356 | /* IDSEL 0x01 (PCI-X slot) @66MHz */ | 367 | /* IDSEL 0x01 (PCI-X slot) @66MHz */ |
| @@ -380,7 +391,6 @@ | |||
| 380 | }; | 391 | }; |
| 381 | 392 | ||
| 382 | pci2: pcie@e000a000 { | 393 | pci2: pcie@e000a000 { |
| 383 | cell-index = <2>; | ||
| 384 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 394 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 385 | interrupt-map = < | 395 | interrupt-map = < |
| 386 | 396 | ||
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index c4564b81e473..239d57a55cf4 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts | |||
| @@ -57,9 +57,21 @@ | |||
| 57 | #size-cells = <1>; | 57 | #size-cells = <1>; |
| 58 | device_type = "soc"; | 58 | device_type = "soc"; |
| 59 | ranges = <0x0 0xff700000 0x00100000>; | 59 | ranges = <0x0 0xff700000 0x00100000>; |
| 60 | reg = <0xff700000 0x00100000>; | ||
| 61 | clock-frequency = <0>; | 60 | clock-frequency = <0>; |
| 62 | 61 | ||
| 62 | ecm-law@0 { | ||
| 63 | compatible = "fsl,ecm-law"; | ||
| 64 | reg = <0x0 0x1000>; | ||
| 65 | fsl,num-laws = <8>; | ||
| 66 | }; | ||
| 67 | |||
| 68 | ecm@1000 { | ||
| 69 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | ||
| 70 | reg = <0x1000 0x1000>; | ||
| 71 | interrupts = <17 2>; | ||
| 72 | interrupt-parent = <&mpic>; | ||
| 73 | }; | ||
| 74 | |||
| 63 | memory-controller@2000 { | 75 | memory-controller@2000 { |
| 64 | compatible = "fsl,mpc8560-memory-controller"; | 76 | compatible = "fsl,mpc8560-memory-controller"; |
| 65 | reg = <0x2000 0x1000>; | 77 | reg = <0x2000 0x1000>; |
| @@ -296,7 +308,6 @@ | |||
| 296 | }; | 308 | }; |
| 297 | 309 | ||
| 298 | pci0: pci@ff708000 { | 310 | pci0: pci@ff708000 { |
| 299 | cell-index = <0>; | ||
| 300 | #interrupt-cells = <1>; | 311 | #interrupt-cells = <1>; |
| 301 | #size-cells = <2>; | 312 | #size-cells = <2>; |
| 302 | #address-cells = <3>; | 313 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts index e3e914e78caa..ee5538feb455 100644 --- a/arch/powerpc/boot/dts/sbc8641d.dts +++ b/arch/powerpc/boot/dts/sbc8641d.dts | |||
| @@ -126,9 +126,21 @@ | |||
| 126 | device_type = "soc"; | 126 | device_type = "soc"; |
| 127 | compatible = "simple-bus"; | 127 | compatible = "simple-bus"; |
| 128 | ranges = <0x00000000 0xf8000000 0x00100000>; | 128 | ranges = <0x00000000 0xf8000000 0x00100000>; |
| 129 | reg = <0xf8000000 0x00001000>; // CCSRBAR | ||
| 130 | bus-frequency = <0>; | 129 | bus-frequency = <0>; |
| 131 | 130 | ||
| 131 | mcm-law@0 { | ||
| 132 | compatible = "fsl,mcm-law"; | ||
| 133 | reg = <0x0 0x1000>; | ||
| 134 | fsl,num-laws = <10>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | mcm@1000 { | ||
| 138 | compatible = "fsl,mpc8641-mcm", "fsl,mcm"; | ||
| 139 | reg = <0x1000 0x1000>; | ||
| 140 | interrupts = <17 2>; | ||
| 141 | interrupt-parent = <&mpic>; | ||
| 142 | }; | ||
| 143 | |||
| 132 | i2c@3000 { | 144 | i2c@3000 { |
| 133 | #address-cells = <1>; | 145 | #address-cells = <1>; |
| 134 | #size-cells = <0>; | 146 | #size-cells = <0>; |
| @@ -371,7 +383,6 @@ | |||
| 371 | }; | 383 | }; |
| 372 | 384 | ||
| 373 | pci0: pcie@f8008000 { | 385 | pci0: pcie@f8008000 { |
| 374 | cell-index = <0>; | ||
| 375 | compatible = "fsl,mpc8641-pcie"; | 386 | compatible = "fsl,mpc8641-pcie"; |
| 376 | device_type = "pci"; | 387 | device_type = "pci"; |
| 377 | #interrupt-cells = <1>; | 388 | #interrupt-cells = <1>; |
| @@ -410,7 +421,6 @@ | |||
| 410 | }; | 421 | }; |
| 411 | 422 | ||
| 412 | pci1: pcie@f8009000 { | 423 | pci1: pcie@f8009000 { |
| 413 | cell-index = <1>; | ||
| 414 | compatible = "fsl,mpc8641-pcie"; | 424 | compatible = "fsl,mpc8641-pcie"; |
| 415 | device_type = "pci"; | 425 | device_type = "pci"; |
| 416 | #interrupt-cells = <1>; | 426 | #interrupt-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 43cc68bd3192..739dd0da2416 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts | |||
| @@ -199,6 +199,28 @@ | |||
| 199 | }; | 199 | }; |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | ndfc@3,0 { | ||
| 203 | compatible = "ibm,ndfc"; | ||
| 204 | reg = <0x00000003 0x00000000 0x00002000>; | ||
| 205 | ccr = <0x00001000>; | ||
| 206 | bank-settings = <0x80002222>; | ||
| 207 | #address-cells = <1>; | ||
| 208 | #size-cells = <1>; | ||
| 209 | |||
| 210 | nand { | ||
| 211 | #address-cells = <1>; | ||
| 212 | #size-cells = <1>; | ||
| 213 | |||
| 214 | partition@0 { | ||
| 215 | label = "u-boot"; | ||
| 216 | reg = <0x00000000 0x00084000>; | ||
| 217 | }; | ||
| 218 | partition@84000 { | ||
| 219 | label = "user"; | ||
| 220 | reg = <0x00000000 0x01f7c000>; | ||
| 221 | }; | ||
| 222 | }; | ||
| 223 | }; | ||
| 202 | }; | 224 | }; |
| 203 | 225 | ||
| 204 | UART0: serial@ef600300 { | 226 | UART0: serial@ef600300 { |
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts index 7a6ae75a1e57..feb4ef6bd144 100644 --- a/arch/powerpc/boot/dts/socrates.dts +++ b/arch/powerpc/boot/dts/socrates.dts | |||
| @@ -55,10 +55,22 @@ | |||
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | 56 | ||
| 57 | ranges = <0x00000000 0xe0000000 0x00100000>; | 57 | ranges = <0x00000000 0xe0000000 0x00100000>; |
| 58 | reg = <0xe0000000 0x00001000>; // CCSRBAR 1M | ||
| 59 | bus-frequency = <0>; // Filled in by U-Boot | 58 | bus-frequency = <0>; // Filled in by U-Boot |
| 60 | compatible = "fsl,mpc8544-immr", "simple-bus"; | 59 | compatible = "fsl,mpc8544-immr", "simple-bus"; |
| 61 | 60 | ||
| 61 | ecm-law@0 { | ||
| 62 | compatible = "fsl,ecm-law"; | ||
| 63 | reg = <0x0 0x1000>; | ||
| 64 | fsl,num-laws = <10>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ecm@1000 { | ||
| 68 | compatible = "fsl,mpc8544-ecm", "fsl,ecm"; | ||
| 69 | reg = <0x1000 0x1000>; | ||
| 70 | interrupts = <17 2>; | ||
| 71 | interrupt-parent = <&mpic>; | ||
| 72 | }; | ||
| 73 | |||
| 62 | memory-controller@2000 { | 74 | memory-controller@2000 { |
| 63 | compatible = "fsl,mpc8544-memory-controller"; | 75 | compatible = "fsl,mpc8544-memory-controller"; |
| 64 | reg = <0x2000 0x1000>; | 76 | reg = <0x2000 0x1000>; |
| @@ -314,7 +326,6 @@ | |||
| 314 | }; | 326 | }; |
| 315 | 327 | ||
| 316 | pci0: pci@e0008000 { | 328 | pci0: pci@e0008000 { |
| 317 | cell-index = <0>; | ||
| 318 | #interrupt-cells = <1>; | 329 | #interrupt-cells = <1>; |
| 319 | #size-cells = <2>; | 330 | #size-cells = <2>; |
| 320 | #address-cells = <3>; | 331 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index ea6b15152de3..b670d03fbcd9 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts | |||
| @@ -52,10 +52,22 @@ | |||
| 52 | #size-cells = <1>; | 52 | #size-cells = <1>; |
| 53 | device_type = "soc"; | 53 | device_type = "soc"; |
| 54 | ranges = <0 0xfdf00000 0x100000>; | 54 | ranges = <0 0xfdf00000 0x100000>; |
| 55 | reg = <0xfdf00000 0x1000>; | ||
| 56 | bus-frequency = <0>; | 55 | bus-frequency = <0>; |
| 57 | compatible = "fsl,mpc8560-immr", "simple-bus"; | 56 | compatible = "fsl,mpc8560-immr", "simple-bus"; |
| 58 | 57 | ||
| 58 | ecm-law@0 { | ||
| 59 | compatible = "fsl,ecm-law"; | ||
| 60 | reg = <0x0 0x1000>; | ||
| 61 | fsl,num-laws = <8>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | ecm@1000 { | ||
| 65 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | ||
| 66 | reg = <0x1000 0x1000>; | ||
| 67 | interrupts = <17 2>; | ||
| 68 | interrupt-parent = <&mpic>; | ||
| 69 | }; | ||
| 70 | |||
| 59 | memory-controller@2000 { | 71 | memory-controller@2000 { |
| 60 | compatible = "fsl,mpc8540-memory-controller"; | 72 | compatible = "fsl,mpc8540-memory-controller"; |
| 61 | reg = <0x2000 0x1000>; | 73 | reg = <0x2000 0x1000>; |
| @@ -251,7 +263,6 @@ | |||
| 251 | }; | 263 | }; |
| 252 | 264 | ||
| 253 | pci0: pci@fdf08000 { | 265 | pci0: pci@fdf08000 { |
| 254 | cell-index = <0>; | ||
| 255 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 266 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 256 | interrupt-map = < | 267 | interrupt-map = < |
| 257 | 268 | ||
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index b6f1fc6eb960..71347537b83e 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts | |||
| @@ -54,10 +54,22 @@ | |||
| 54 | #size-cells = <1>; | 54 | #size-cells = <1>; |
| 55 | device_type = "soc"; | 55 | device_type = "soc"; |
| 56 | ranges = <0x0 0xe0000000 0x100000>; | 56 | ranges = <0x0 0xe0000000 0x100000>; |
| 57 | reg = <0xe0000000 0x200>; | ||
| 58 | bus-frequency = <0>; | 57 | bus-frequency = <0>; |
| 59 | compatible = "fsl,mpc8540-immr", "simple-bus"; | 58 | compatible = "fsl,mpc8540-immr", "simple-bus"; |
| 60 | 59 | ||
| 60 | ecm-law@0 { | ||
| 61 | compatible = "fsl,ecm-law"; | ||
| 62 | reg = <0x0 0x1000>; | ||
| 63 | fsl,num-laws = <8>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | ecm@1000 { | ||
| 67 | compatible = "fsl,mpc8540-ecm", "fsl,ecm"; | ||
| 68 | reg = <0x1000 0x1000>; | ||
| 69 | interrupts = <17 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | }; | ||
| 72 | |||
| 61 | memory-controller@2000 { | 73 | memory-controller@2000 { |
| 62 | compatible = "fsl,mpc8540-memory-controller"; | 74 | compatible = "fsl,mpc8540-memory-controller"; |
| 63 | reg = <0x2000 0x1000>; | 75 | reg = <0x2000 0x1000>; |
| @@ -266,7 +278,6 @@ | |||
| 266 | }; | 278 | }; |
| 267 | 279 | ||
| 268 | pci0: pci@e0008000 { | 280 | pci0: pci@e0008000 { |
| 269 | cell-index = <0>; | ||
| 270 | #interrupt-cells = <1>; | 281 | #interrupt-cells = <1>; |
| 271 | #size-cells = <2>; | 282 | #size-cells = <2>; |
| 272 | #address-cells = <3>; | 283 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index fa6a3d54a8a5..b30f63753d41 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts | |||
| @@ -53,10 +53,22 @@ | |||
| 53 | #size-cells = <1>; | 53 | #size-cells = <1>; |
| 54 | device_type = "soc"; | 54 | device_type = "soc"; |
| 55 | ranges = <0x0 0xe0000000 0x100000>; | 55 | ranges = <0x0 0xe0000000 0x100000>; |
| 56 | reg = <0xe0000000 0x200>; | ||
| 57 | bus-frequency = <0>; | 56 | bus-frequency = <0>; |
| 58 | compatible = "fsl,mpc8541-immr", "simple-bus"; | 57 | compatible = "fsl,mpc8541-immr", "simple-bus"; |
| 59 | 58 | ||
| 59 | ecm-law@0 { | ||
| 60 | compatible = "fsl,ecm-law"; | ||
| 61 | reg = <0x0 0x1000>; | ||
| 62 | fsl,num-laws = <8>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | ecm@1000 { | ||
| 66 | compatible = "fsl,mpc8541-ecm", "fsl,ecm"; | ||
| 67 | reg = <0x1000 0x1000>; | ||
| 68 | interrupts = <17 2>; | ||
| 69 | interrupt-parent = <&mpic>; | ||
| 70 | }; | ||
| 71 | |||
| 60 | memory-controller@2000 { | 72 | memory-controller@2000 { |
| 61 | compatible = "fsl,mpc8540-memory-controller"; | 73 | compatible = "fsl,mpc8540-memory-controller"; |
| 62 | reg = <0x2000 0x1000>; | 74 | reg = <0x2000 0x1000>; |
| @@ -288,7 +300,6 @@ | |||
| 288 | }; | 300 | }; |
| 289 | 301 | ||
| 290 | pci0: pci@e0008000 { | 302 | pci0: pci@e0008000 { |
| 291 | cell-index = <0>; | ||
| 292 | #interrupt-cells = <1>; | 303 | #interrupt-cells = <1>; |
| 293 | #size-cells = <2>; | 304 | #size-cells = <2>; |
| 294 | #address-cells = <3>; | 305 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts index 00f7ed7a2455..61f25e15fd66 100644 --- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts | |||
| @@ -55,10 +55,22 @@ | |||
| 55 | #size-cells = <1>; | 55 | #size-cells = <1>; |
| 56 | device_type = "soc"; | 56 | device_type = "soc"; |
| 57 | ranges = <0x0 0xa0000000 0x100000>; | 57 | ranges = <0x0 0xa0000000 0x100000>; |
| 58 | reg = <0xa0000000 0x1000>; // CCSRBAR | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | compatible = "fsl,mpc8548-immr", "simple-bus"; | 59 | compatible = "fsl,mpc8548-immr", "simple-bus"; |
| 61 | 60 | ||
| 61 | ecm-law@0 { | ||
| 62 | compatible = "fsl,ecm-law"; | ||
| 63 | reg = <0x0 0x1000>; | ||
| 64 | fsl,num-laws = <10>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ecm@1000 { | ||
| 68 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 69 | reg = <0x1000 0x1000>; | ||
| 70 | interrupts = <17 2>; | ||
| 71 | interrupt-parent = <&mpic>; | ||
| 72 | }; | ||
| 73 | |||
| 62 | memory-controller@2000 { | 74 | memory-controller@2000 { |
| 63 | compatible = "fsl,mpc8548-memory-controller"; | 75 | compatible = "fsl,mpc8548-memory-controller"; |
| 64 | reg = <0x2000 0x1000>; | 76 | reg = <0x2000 0x1000>; |
| @@ -419,7 +431,6 @@ | |||
| 419 | }; | 431 | }; |
| 420 | 432 | ||
| 421 | pci0: pci@a0008000 { | 433 | pci0: pci@a0008000 { |
| 422 | cell-index = <0>; | ||
| 423 | #interrupt-cells = <1>; | 434 | #interrupt-cells = <1>; |
| 424 | #size-cells = <2>; | 435 | #size-cells = <2>; |
| 425 | #address-cells = <3>; | 436 | #address-cells = <3>; |
| @@ -441,7 +452,6 @@ | |||
| 441 | }; | 452 | }; |
| 442 | 453 | ||
| 443 | pci1: pcie@a000a000 { | 454 | pci1: pcie@a000a000 { |
| 444 | cell-index = <2>; | ||
| 445 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 455 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 446 | interrupt-map = < | 456 | interrupt-map = < |
| 447 | /* IDSEL 0x0 (PEX) */ | 457 | /* IDSEL 0x0 (PEX) */ |
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index 673e4a778ac8..025759c7c955 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts | |||
| @@ -55,10 +55,22 @@ | |||
| 55 | #size-cells = <1>; | 55 | #size-cells = <1>; |
| 56 | device_type = "soc"; | 56 | device_type = "soc"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x1000>; // CCSRBAR | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | compatible = "fsl,mpc8548-immr", "simple-bus"; | 59 | compatible = "fsl,mpc8548-immr", "simple-bus"; |
| 61 | 60 | ||
| 61 | ecm-law@0 { | ||
| 62 | compatible = "fsl,ecm-law"; | ||
| 63 | reg = <0x0 0x1000>; | ||
| 64 | fsl,num-laws = <10>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ecm@1000 { | ||
| 68 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 69 | reg = <0x1000 0x1000>; | ||
| 70 | interrupts = <17 2>; | ||
| 71 | interrupt-parent = <&mpic>; | ||
| 72 | }; | ||
| 73 | |||
| 62 | memory-controller@2000 { | 74 | memory-controller@2000 { |
| 63 | compatible = "fsl,mpc8548-memory-controller"; | 75 | compatible = "fsl,mpc8548-memory-controller"; |
| 64 | reg = <0x2000 0x1000>; | 76 | reg = <0x2000 0x1000>; |
| @@ -419,7 +431,6 @@ | |||
| 419 | }; | 431 | }; |
| 420 | 432 | ||
| 421 | pci0: pci@e0008000 { | 433 | pci0: pci@e0008000 { |
| 422 | cell-index = <0>; | ||
| 423 | #interrupt-cells = <1>; | 434 | #interrupt-cells = <1>; |
| 424 | #size-cells = <2>; | 435 | #size-cells = <2>; |
| 425 | #address-cells = <3>; | 436 | #address-cells = <3>; |
| @@ -441,7 +452,6 @@ | |||
| 441 | }; | 452 | }; |
| 442 | 453 | ||
| 443 | pci1: pcie@e000a000 { | 454 | pci1: pcie@e000a000 { |
| 444 | cell-index = <2>; | ||
| 445 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 455 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 446 | interrupt-map = < | 456 | interrupt-map = < |
| 447 | /* IDSEL 0x0 (PEX) */ | 457 | /* IDSEL 0x0 (PEX) */ |
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 6a99f1eef7ad..95e287381836 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts | |||
| @@ -53,10 +53,22 @@ | |||
| 53 | #size-cells = <1>; | 53 | #size-cells = <1>; |
| 54 | device_type = "soc"; | 54 | device_type = "soc"; |
| 55 | ranges = <0x0 0xe0000000 0x100000>; | 55 | ranges = <0x0 0xe0000000 0x100000>; |
| 56 | reg = <0xe0000000 0x200>; | ||
| 57 | bus-frequency = <0>; | 56 | bus-frequency = <0>; |
| 58 | compatible = "fsl,mpc8555-immr", "simple-bus"; | 57 | compatible = "fsl,mpc8555-immr", "simple-bus"; |
| 59 | 58 | ||
| 59 | ecm-law@0 { | ||
| 60 | compatible = "fsl,ecm-law"; | ||
| 61 | reg = <0x0 0x1000>; | ||
| 62 | fsl,num-laws = <8>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | ecm@1000 { | ||
| 66 | compatible = "fsl,mpc8555-ecm", "fsl,ecm"; | ||
| 67 | reg = <0x1000 0x1000>; | ||
| 68 | interrupts = <17 2>; | ||
| 69 | interrupt-parent = <&mpic>; | ||
| 70 | }; | ||
| 71 | |||
| 60 | memory-controller@2000 { | 72 | memory-controller@2000 { |
| 61 | compatible = "fsl,mpc8540-memory-controller"; | 73 | compatible = "fsl,mpc8540-memory-controller"; |
| 62 | reg = <0x2000 0x1000>; | 74 | reg = <0x2000 0x1000>; |
| @@ -288,7 +300,6 @@ | |||
| 288 | }; | 300 | }; |
| 289 | 301 | ||
| 290 | pci0: pci@e0008000 { | 302 | pci0: pci@e0008000 { |
| 291 | cell-index = <0>; | ||
| 292 | #interrupt-cells = <1>; | 303 | #interrupt-cells = <1>; |
| 293 | #size-cells = <2>; | 304 | #size-cells = <2>; |
| 294 | #address-cells = <3>; | 305 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index b6c2d71defd3..ff70580a8f4c 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts | |||
| @@ -55,10 +55,22 @@ | |||
| 55 | #size-cells = <1>; | 55 | #size-cells = <1>; |
| 56 | device_type = "soc"; | 56 | device_type = "soc"; |
| 57 | ranges = <0x0 0xe0000000 0x100000>; | 57 | ranges = <0x0 0xe0000000 0x100000>; |
| 58 | reg = <0xe0000000 0x200>; | ||
| 59 | bus-frequency = <0>; | 58 | bus-frequency = <0>; |
| 60 | compatible = "fsl,mpc8560-immr", "simple-bus"; | 59 | compatible = "fsl,mpc8560-immr", "simple-bus"; |
| 61 | 60 | ||
| 61 | ecm-law@0 { | ||
| 62 | compatible = "fsl,ecm-law"; | ||
| 63 | reg = <0x0 0x1000>; | ||
| 64 | fsl,num-laws = <8>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | ecm@1000 { | ||
| 68 | compatible = "fsl,mpc8560-ecm", "fsl,ecm"; | ||
| 69 | reg = <0x1000 0x1000>; | ||
| 70 | interrupts = <17 2>; | ||
| 71 | interrupt-parent = <&mpic>; | ||
| 72 | }; | ||
| 73 | |||
| 62 | memory-controller@2000 { | 74 | memory-controller@2000 { |
| 63 | compatible = "fsl,mpc8540-memory-controller"; | 75 | compatible = "fsl,mpc8540-memory-controller"; |
| 64 | reg = <0x2000 0x1000>; | 76 | reg = <0x2000 0x1000>; |
| @@ -359,7 +371,6 @@ | |||
| 359 | }; | 371 | }; |
| 360 | 372 | ||
| 361 | pci0: pci@e0008000 { | 373 | pci0: pci@e0008000 { |
| 362 | cell-index = <0>; | ||
| 363 | #interrupt-cells = <1>; | 374 | #interrupt-cells = <1>; |
| 364 | #size-cells = <2>; | 375 | #size-cells = <2>; |
| 365 | #address-cells = <3>; | 376 | #address-cells = <3>; |
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts new file mode 100644 index 000000000000..81a8dc2c6365 --- /dev/null +++ b/arch/powerpc/boot/dts/virtex440-ml510.dts | |||
| @@ -0,0 +1,465 @@ | |||
| 1 | /* | ||
| 2 | * Xilinx ML510 Reference Design support | ||
| 3 | * | ||
| 4 | * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design. | ||
| 5 | * The reference design contains a bug which prevent PCI DMA from working | ||
| 6 | * properly. A description of the bug is given in the plbv46_pci section. It | ||
| 7 | * needs to be fixed by the user until Xilinx updates their reference design. | ||
| 8 | * | ||
| 9 | * Copyright 2009, Roderick Colenbrander | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | #address-cells = <1>; | ||
| 15 | #size-cells = <1>; | ||
| 16 | compatible = "xlnx,ml510-ref-design", "xlnx,virtex440"; | ||
| 17 | dcr-parent = <&ppc440_0>; | ||
| 18 | DDR2_SDRAM_DIMM0: memory@0 { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = < 0x0 0x20000000 >; | ||
| 21 | } ; | ||
| 22 | alias { | ||
| 23 | ethernet0 = &Hard_Ethernet_MAC; | ||
| 24 | serial0 = &RS232_Uart_1; | ||
| 25 | } ; | ||
| 26 | chosen { | ||
| 27 | bootargs = "console=ttyS0 root=/dev/ram"; | ||
| 28 | linux,stdout-path = "/plb@0/serial@83e00000"; | ||
| 29 | } ; | ||
| 30 | cpus { | ||
| 31 | #address-cells = <1>; | ||
| 32 | #cpus = <0x1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | ppc440_0: cpu@0 { | ||
| 35 | #address-cells = <1>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | clock-frequency = <300000000>; | ||
| 38 | compatible = "PowerPC,440", "ibm,ppc440"; | ||
| 39 | d-cache-line-size = <0x20>; | ||
| 40 | d-cache-size = <0x8000>; | ||
| 41 | dcr-access-method = "native"; | ||
| 42 | dcr-controller ; | ||
| 43 | device_type = "cpu"; | ||
| 44 | i-cache-line-size = <0x20>; | ||
| 45 | i-cache-size = <0x8000>; | ||
| 46 | model = "PowerPC,440"; | ||
| 47 | reg = <0>; | ||
| 48 | timebase-frequency = <300000000>; | ||
| 49 | xlnx,apu-control = <0x2000>; | ||
| 50 | xlnx,apu-udi-0 = <0x0>; | ||
| 51 | xlnx,apu-udi-1 = <0x0>; | ||
| 52 | xlnx,apu-udi-10 = <0x0>; | ||
| 53 | xlnx,apu-udi-11 = <0x0>; | ||
| 54 | xlnx,apu-udi-12 = <0x0>; | ||
| 55 | xlnx,apu-udi-13 = <0x0>; | ||
| 56 | xlnx,apu-udi-14 = <0x0>; | ||
| 57 | xlnx,apu-udi-15 = <0x0>; | ||
| 58 | xlnx,apu-udi-2 = <0x0>; | ||
| 59 | xlnx,apu-udi-3 = <0x0>; | ||
| 60 | xlnx,apu-udi-4 = <0x0>; | ||
| 61 | xlnx,apu-udi-5 = <0x0>; | ||
| 62 | xlnx,apu-udi-6 = <0x0>; | ||
| 63 | xlnx,apu-udi-7 = <0x0>; | ||
| 64 | xlnx,apu-udi-8 = <0x0>; | ||
| 65 | xlnx,apu-udi-9 = <0x0>; | ||
| 66 | xlnx,dcr-autolock-enable = <0x1>; | ||
| 67 | xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; | ||
| 68 | xlnx,dcu-rd-noncache-plb-prio = <0x0>; | ||
| 69 | xlnx,dcu-rd-touch-plb-prio = <0x0>; | ||
| 70 | xlnx,dcu-rd-urgent-plb-prio = <0x0>; | ||
| 71 | xlnx,dcu-wr-flush-plb-prio = <0x0>; | ||
| 72 | xlnx,dcu-wr-store-plb-prio = <0x0>; | ||
| 73 | xlnx,dcu-wr-urgent-plb-prio = <0x0>; | ||
| 74 | xlnx,dma0-control = <0x0>; | ||
| 75 | xlnx,dma0-plb-prio = <0x0>; | ||
| 76 | xlnx,dma0-rxchannelctrl = <0x1010000>; | ||
| 77 | xlnx,dma0-rxirqtimer = <0x3ff>; | ||
| 78 | xlnx,dma0-txchannelctrl = <0x1010000>; | ||
| 79 | xlnx,dma0-txirqtimer = <0x3ff>; | ||
| 80 | xlnx,dma1-control = <0x0>; | ||
| 81 | xlnx,dma1-plb-prio = <0x0>; | ||
| 82 | xlnx,dma1-rxchannelctrl = <0x1010000>; | ||
| 83 | xlnx,dma1-rxirqtimer = <0x3ff>; | ||
| 84 | xlnx,dma1-txchannelctrl = <0x1010000>; | ||
| 85 | xlnx,dma1-txirqtimer = <0x3ff>; | ||
| 86 | xlnx,dma2-control = <0x0>; | ||
| 87 | xlnx,dma2-plb-prio = <0x0>; | ||
| 88 | xlnx,dma2-rxchannelctrl = <0x1010000>; | ||
| 89 | xlnx,dma2-rxirqtimer = <0x3ff>; | ||
| 90 | xlnx,dma2-txchannelctrl = <0x1010000>; | ||
| 91 | xlnx,dma2-txirqtimer = <0x3ff>; | ||
| 92 | xlnx,dma3-control = <0x0>; | ||
| 93 | xlnx,dma3-plb-prio = <0x0>; | ||
| 94 | xlnx,dma3-rxchannelctrl = <0x1010000>; | ||
| 95 | xlnx,dma3-rxirqtimer = <0x3ff>; | ||
| 96 | xlnx,dma3-txchannelctrl = <0x1010000>; | ||
| 97 | xlnx,dma3-txirqtimer = <0x3ff>; | ||
| 98 | xlnx,endian-reset = <0x0>; | ||
| 99 | xlnx,generate-plb-timespecs = <0x1>; | ||
| 100 | xlnx,icu-rd-fetch-plb-prio = <0x0>; | ||
| 101 | xlnx,icu-rd-spec-plb-prio = <0x0>; | ||
| 102 | xlnx,icu-rd-touch-plb-prio = <0x0>; | ||
| 103 | xlnx,interconnect-imask = <0xffffffff>; | ||
| 104 | xlnx,mplb-allow-lock-xfer = <0x1>; | ||
| 105 | xlnx,mplb-arb-mode = <0x0>; | ||
| 106 | xlnx,mplb-awidth = <0x20>; | ||
| 107 | xlnx,mplb-counter = <0x500>; | ||
| 108 | xlnx,mplb-dwidth = <0x80>; | ||
| 109 | xlnx,mplb-max-burst = <0x8>; | ||
| 110 | xlnx,mplb-native-dwidth = <0x80>; | ||
| 111 | xlnx,mplb-p2p = <0x0>; | ||
| 112 | xlnx,mplb-prio-dcur = <0x2>; | ||
| 113 | xlnx,mplb-prio-dcuw = <0x3>; | ||
| 114 | xlnx,mplb-prio-icu = <0x4>; | ||
| 115 | xlnx,mplb-prio-splb0 = <0x1>; | ||
| 116 | xlnx,mplb-prio-splb1 = <0x0>; | ||
| 117 | xlnx,mplb-read-pipe-enable = <0x1>; | ||
| 118 | xlnx,mplb-sync-tattribute = <0x0>; | ||
| 119 | xlnx,mplb-wdog-enable = <0x1>; | ||
| 120 | xlnx,mplb-write-pipe-enable = <0x1>; | ||
| 121 | xlnx,mplb-write-post-enable = <0x1>; | ||
| 122 | xlnx,num-dma = <0x0>; | ||
| 123 | xlnx,pir = <0xf>; | ||
| 124 | xlnx,ppc440mc-addr-base = <0x0>; | ||
| 125 | xlnx,ppc440mc-addr-high = <0x1fffffff>; | ||
| 126 | xlnx,ppc440mc-arb-mode = <0x0>; | ||
| 127 | xlnx,ppc440mc-bank-conflict-mask = <0x1800000>; | ||
| 128 | xlnx,ppc440mc-control = <0xf810008f>; | ||
| 129 | xlnx,ppc440mc-max-burst = <0x8>; | ||
| 130 | xlnx,ppc440mc-prio-dcur = <0x2>; | ||
| 131 | xlnx,ppc440mc-prio-dcuw = <0x3>; | ||
| 132 | xlnx,ppc440mc-prio-icu = <0x4>; | ||
| 133 | xlnx,ppc440mc-prio-splb0 = <0x1>; | ||
| 134 | xlnx,ppc440mc-prio-splb1 = <0x0>; | ||
| 135 | xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>; | ||
| 136 | xlnx,ppcdm-asyncmode = <0x0>; | ||
| 137 | xlnx,ppcds-asyncmode = <0x0>; | ||
| 138 | xlnx,user-reset = <0x0>; | ||
| 139 | } ; | ||
| 140 | } ; | ||
| 141 | plb_v46_0: plb@0 { | ||
| 142 | #address-cells = <1>; | ||
| 143 | #size-cells = <1>; | ||
| 144 | compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; | ||
| 145 | ranges ; | ||
| 146 | FLASH: flash@fc000000 { | ||
| 147 | bank-width = <2>; | ||
| 148 | compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; | ||
| 149 | reg = < 0xfc000000 0x2000000 >; | ||
| 150 | xlnx,family = "virtex5"; | ||
| 151 | xlnx,include-datawidth-matching-0 = <0x1>; | ||
| 152 | xlnx,include-datawidth-matching-1 = <0x0>; | ||
| 153 | xlnx,include-datawidth-matching-2 = <0x0>; | ||
| 154 | xlnx,include-datawidth-matching-3 = <0x0>; | ||
| 155 | xlnx,include-negedge-ioregs = <0x0>; | ||
| 156 | xlnx,include-plb-ipif = <0x1>; | ||
| 157 | xlnx,include-wrbuf = <0x1>; | ||
| 158 | xlnx,max-mem-width = <0x10>; | ||
| 159 | xlnx,mch-native-dwidth = <0x20>; | ||
| 160 | xlnx,mch-plb-clk-period-ps = <0x2710>; | ||
| 161 | xlnx,mch-splb-awidth = <0x20>; | ||
| 162 | xlnx,mch0-accessbuf-depth = <0x10>; | ||
| 163 | xlnx,mch0-protocol = <0x0>; | ||
| 164 | xlnx,mch0-rddatabuf-depth = <0x10>; | ||
| 165 | xlnx,mch1-accessbuf-depth = <0x10>; | ||
| 166 | xlnx,mch1-protocol = <0x0>; | ||
| 167 | xlnx,mch1-rddatabuf-depth = <0x10>; | ||
| 168 | xlnx,mch2-accessbuf-depth = <0x10>; | ||
| 169 | xlnx,mch2-protocol = <0x0>; | ||
| 170 | xlnx,mch2-rddatabuf-depth = <0x10>; | ||
| 171 | xlnx,mch3-accessbuf-depth = <0x10>; | ||
| 172 | xlnx,mch3-protocol = <0x0>; | ||
| 173 | xlnx,mch3-rddatabuf-depth = <0x10>; | ||
| 174 | xlnx,mem0-width = <0x10>; | ||
| 175 | xlnx,mem1-width = <0x20>; | ||
| 176 | xlnx,mem2-width = <0x20>; | ||
| 177 | xlnx,mem3-width = <0x20>; | ||
| 178 | xlnx,num-banks-mem = <0x1>; | ||
| 179 | xlnx,num-channels = <0x2>; | ||
| 180 | xlnx,priority-mode = <0x0>; | ||
| 181 | xlnx,synch-mem-0 = <0x0>; | ||
| 182 | xlnx,synch-mem-1 = <0x0>; | ||
| 183 | xlnx,synch-mem-2 = <0x0>; | ||
| 184 | xlnx,synch-mem-3 = <0x0>; | ||
| 185 | xlnx,synch-pipedelay-0 = <0x2>; | ||
| 186 | xlnx,synch-pipedelay-1 = <0x2>; | ||
| 187 | xlnx,synch-pipedelay-2 = <0x2>; | ||
| 188 | xlnx,synch-pipedelay-3 = <0x2>; | ||
| 189 | xlnx,tavdv-ps-mem-0 = <0x1adb0>; | ||
| 190 | xlnx,tavdv-ps-mem-1 = <0x3a98>; | ||
| 191 | xlnx,tavdv-ps-mem-2 = <0x3a98>; | ||
| 192 | xlnx,tavdv-ps-mem-3 = <0x3a98>; | ||
| 193 | xlnx,tcedv-ps-mem-0 = <0x1adb0>; | ||
| 194 | xlnx,tcedv-ps-mem-1 = <0x3a98>; | ||
| 195 | xlnx,tcedv-ps-mem-2 = <0x3a98>; | ||
| 196 | xlnx,tcedv-ps-mem-3 = <0x3a98>; | ||
| 197 | xlnx,thzce-ps-mem-0 = <0x88b8>; | ||
| 198 | xlnx,thzce-ps-mem-1 = <0x1b58>; | ||
| 199 | xlnx,thzce-ps-mem-2 = <0x1b58>; | ||
| 200 | xlnx,thzce-ps-mem-3 = <0x1b58>; | ||
| 201 | xlnx,thzoe-ps-mem-0 = <0x1b58>; | ||
| 202 | xlnx,thzoe-ps-mem-1 = <0x1b58>; | ||
| 203 | xlnx,thzoe-ps-mem-2 = <0x1b58>; | ||
| 204 | xlnx,thzoe-ps-mem-3 = <0x1b58>; | ||
| 205 | xlnx,tlzwe-ps-mem-0 = <0x88b8>; | ||
| 206 | xlnx,tlzwe-ps-mem-1 = <0x0>; | ||
| 207 | xlnx,tlzwe-ps-mem-2 = <0x0>; | ||
| 208 | xlnx,tlzwe-ps-mem-3 = <0x0>; | ||
| 209 | xlnx,twc-ps-mem-0 = <0x1adb0>; | ||
| 210 | xlnx,twc-ps-mem-1 = <0x3a98>; | ||
| 211 | xlnx,twc-ps-mem-2 = <0x3a98>; | ||
| 212 | xlnx,twc-ps-mem-3 = <0x3a98>; | ||
| 213 | xlnx,twp-ps-mem-0 = <0x11170>; | ||
| 214 | xlnx,twp-ps-mem-1 = <0x2ee0>; | ||
| 215 | xlnx,twp-ps-mem-2 = <0x2ee0>; | ||
| 216 | xlnx,twp-ps-mem-3 = <0x2ee0>; | ||
| 217 | xlnx,xcl0-linesize = <0x4>; | ||
| 218 | xlnx,xcl0-writexfer = <0x1>; | ||
| 219 | xlnx,xcl1-linesize = <0x4>; | ||
| 220 | xlnx,xcl1-writexfer = <0x1>; | ||
| 221 | xlnx,xcl2-linesize = <0x4>; | ||
| 222 | xlnx,xcl2-writexfer = <0x1>; | ||
| 223 | xlnx,xcl3-linesize = <0x4>; | ||
| 224 | xlnx,xcl3-writexfer = <0x1>; | ||
| 225 | } ; | ||
| 226 | Hard_Ethernet_MAC: xps-ll-temac@81c00000 { | ||
| 227 | #address-cells = <1>; | ||
| 228 | #size-cells = <1>; | ||
| 229 | compatible = "xlnx,compound"; | ||
| 230 | ethernet@81c00000 { | ||
| 231 | compatible = "xlnx,xps-ll-temac-1.01.b"; | ||
| 232 | device_type = "network"; | ||
| 233 | interrupt-parent = <&xps_intc_0>; | ||
| 234 | interrupts = < 8 2 >; | ||
| 235 | llink-connected = <&Hard_Ethernet_MAC_fifo>; | ||
| 236 | local-mac-address = [ 02 00 00 00 00 00 ]; | ||
| 237 | reg = < 0x81c00000 0x40 >; | ||
| 238 | xlnx,bus2core-clk-ratio = <0x1>; | ||
| 239 | xlnx,phy-type = <0x3>; | ||
| 240 | xlnx,phyaddr = <0x1>; | ||
| 241 | xlnx,rxcsum = <0x0>; | ||
| 242 | xlnx,rxfifo = <0x8000>; | ||
| 243 | xlnx,temac-type = <0x0>; | ||
| 244 | xlnx,txcsum = <0x0>; | ||
| 245 | xlnx,txfifo = <0x8000>; | ||
| 246 | } ; | ||
| 247 | } ; | ||
| 248 | Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 { | ||
| 249 | compatible = "xlnx,xps-ll-fifo-1.01.a"; | ||
| 250 | interrupt-parent = <&xps_intc_0>; | ||
| 251 | interrupts = < 6 2 >; | ||
| 252 | reg = < 0x81a00000 0x10000 >; | ||
| 253 | xlnx,family = "virtex5"; | ||
| 254 | } ; | ||
| 255 | IIC_EEPROM: i2c@81600000 { | ||
| 256 | compatible = "xlnx,xps-iic-2.00.a"; | ||
| 257 | interrupt-parent = <&xps_intc_0>; | ||
| 258 | interrupts = < 9 2 >; | ||
| 259 | reg = < 0x81600000 0x10000 >; | ||
| 260 | xlnx,clk-freq = <0x5f5e100>; | ||
| 261 | xlnx,family = "virtex5"; | ||
| 262 | xlnx,gpo-width = <0x1>; | ||
| 263 | xlnx,iic-freq = <0x186a0>; | ||
| 264 | xlnx,scl-inertial-delay = <0x5>; | ||
| 265 | xlnx,sda-inertial-delay = <0x5>; | ||
| 266 | xlnx,ten-bit-adr = <0x0>; | ||
| 267 | } ; | ||
| 268 | LCD_OPTIONAL: gpio@81420000 { | ||
| 269 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
| 270 | reg = < 0x81420000 0x10000 >; | ||
| 271 | xlnx,all-inputs = <0x0>; | ||
| 272 | xlnx,all-inputs-2 = <0x0>; | ||
| 273 | xlnx,dout-default = <0x0>; | ||
| 274 | xlnx,dout-default-2 = <0x0>; | ||
| 275 | xlnx,family = "virtex5"; | ||
| 276 | xlnx,gpio-width = <0xb>; | ||
| 277 | xlnx,interrupt-present = <0x0>; | ||
| 278 | xlnx,is-bidir = <0x1>; | ||
| 279 | xlnx,is-bidir-2 = <0x1>; | ||
| 280 | xlnx,is-dual = <0x0>; | ||
| 281 | xlnx,tri-default = <0xffffffff>; | ||
| 282 | xlnx,tri-default-2 = <0xffffffff>; | ||
| 283 | } ; | ||
| 284 | LEDs_4Bit: gpio@81400000 { | ||
| 285 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
| 286 | reg = < 0x81400000 0x10000 >; | ||
| 287 | xlnx,all-inputs = <0x0>; | ||
| 288 | xlnx,all-inputs-2 = <0x0>; | ||
| 289 | xlnx,dout-default = <0x0>; | ||
| 290 | xlnx,dout-default-2 = <0x0>; | ||
| 291 | xlnx,family = "virtex5"; | ||
| 292 | xlnx,gpio-width = <0x4>; | ||
| 293 | xlnx,interrupt-present = <0x0>; | ||
| 294 | xlnx,is-bidir = <0x1>; | ||
| 295 | xlnx,is-bidir-2 = <0x1>; | ||
| 296 | xlnx,is-dual = <0x0>; | ||
| 297 | xlnx,tri-default = <0xffffffff>; | ||
| 298 | xlnx,tri-default-2 = <0xffffffff>; | ||
| 299 | } ; | ||
| 300 | RS232_Uart_1: serial@83e00000 { | ||
| 301 | clock-frequency = <100000000>; | ||
| 302 | compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; | ||
| 303 | current-speed = <9600>; | ||
| 304 | device_type = "serial"; | ||
| 305 | interrupt-parent = <&xps_intc_0>; | ||
| 306 | interrupts = < 11 2 >; | ||
| 307 | reg = < 0x83e00000 0x10000 >; | ||
| 308 | reg-offset = <0x1003>; | ||
| 309 | reg-shift = <2>; | ||
| 310 | xlnx,family = "virtex5"; | ||
| 311 | xlnx,has-external-rclk = <0x0>; | ||
| 312 | xlnx,has-external-xin = <0x0>; | ||
| 313 | xlnx,is-a-16550 = <0x1>; | ||
| 314 | } ; | ||
| 315 | SPI_EEPROM: xps-spi@feff8000 { | ||
| 316 | compatible = "xlnx,xps-spi-2.00.b"; | ||
| 317 | interrupt-parent = <&xps_intc_0>; | ||
| 318 | interrupts = < 10 2 >; | ||
| 319 | reg = < 0xfeff8000 0x80 >; | ||
| 320 | xlnx,family = "virtex5"; | ||
| 321 | xlnx,fifo-exist = <0x1>; | ||
| 322 | xlnx,num-ss-bits = <0x1>; | ||
| 323 | xlnx,num-transfer-bits = <0x8>; | ||
| 324 | xlnx,sck-ratio = <0x80>; | ||
| 325 | } ; | ||
| 326 | SysACE_CompactFlash: sysace@83600000 { | ||
| 327 | compatible = "xlnx,xps-sysace-1.00.a"; | ||
| 328 | interrupt-parent = <&xps_intc_0>; | ||
| 329 | interrupts = < 7 2 >; | ||
| 330 | reg = < 0x83600000 0x10000 >; | ||
| 331 | xlnx,family = "virtex5"; | ||
| 332 | xlnx,mem-width = <0x10>; | ||
| 333 | } ; | ||
| 334 | plbv46_pci_0: plbv46-pci@85e00000 { | ||
| 335 | #size-cells = <2>; | ||
| 336 | #address-cells = <3>; | ||
| 337 | compatible = "xlnx,plbv46-pci-1.03.a"; | ||
| 338 | device_type = "pci"; | ||
| 339 | reg = < 0x85e00000 0x10000 >; | ||
| 340 | |||
| 341 | /* | ||
| 342 | * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to | ||
| 343 | * 0 which means that a read/write to the memory mapped | ||
| 344 | * i/o region (which starts at 0xa0000000) for pci | ||
| 345 | * bar 0 on the plb side translates to 0. | ||
| 346 | * It is important to set this value to 0xa0000000, so | ||
| 347 | * that inbound and outbound pci transactions work | ||
| 348 | * properly including DMA. | ||
| 349 | */ | ||
| 350 | ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 | ||
| 351 | 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>; | ||
| 352 | |||
| 353 | #interrupt-cells = <1>; | ||
| 354 | interrupt-parent = <&xps_intc_0>; | ||
| 355 | interrupt-map-mask = <0xff00 0x0 0x0 0x7>; | ||
| 356 | interrupt-map = < | ||
| 357 | /* IRQ mapping for pci slots and ALI M1533 | ||
| 358 | * periperhals. In total there are 5 interrupt | ||
| 359 | * lines connected to a xps_intc controller. | ||
| 360 | * Four of them are PCI IRQ A, B, C, D and | ||
| 361 | * which correspond to respectively xpx_intc | ||
| 362 | * 5, 4, 3 and 2. The fifth interrupt line is | ||
| 363 | * connected to the south bridge and this one | ||
| 364 | * uses irq 1 and is active high instead of | ||
| 365 | * active low. | ||
| 366 | * | ||
| 367 | * The M1533 contains various peripherals | ||
| 368 | * including AC97 audio, a modem, USB, IDE and | ||
| 369 | * some power management stuff. The modem | ||
| 370 | * isn't connected on the ML510 and the power | ||
| 371 | * management core also isn't used. | ||
| 372 | */ | ||
| 373 | |||
| 374 | /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */ | ||
| 375 | 0x3000 0 0 1 &xps_intc_0 3 2 | ||
| 376 | 0x3000 0 0 2 &xps_intc_0 2 2 | ||
| 377 | 0x3000 0 0 3 &xps_intc_0 5 2 | ||
| 378 | 0x3000 0 0 4 &xps_intc_0 4 2 | ||
| 379 | |||
| 380 | /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */ | ||
| 381 | /* | ||
| 382 | 0x11800 0 0 1 &xps_intc_0 5 0 2 | ||
| 383 | 0x11800 0 0 2 &xps_intc_0 4 0 2 | ||
| 384 | 0x11800 0 0 3 &xps_intc_0 3 0 2 | ||
| 385 | 0x11800 0 0 4 &xps_intc_0 2 0 2 | ||
| 386 | */ | ||
| 387 | |||
| 388 | /* According to the datasheet + schematic | ||
| 389 | * ABCD [FPGA] of slot 5 is mapped to DABC. | ||
| 390 | * Testing showed that at least A maps to B, | ||
| 391 | * the mapping of the other pins is a guess | ||
| 392 | * and for that reason the lines have been | ||
| 393 | * commented out. | ||
| 394 | */ | ||
| 395 | /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */ | ||
| 396 | 0x2800 0 0 1 &xps_intc_0 4 2 | ||
| 397 | /* | ||
| 398 | 0x2800 0 0 2 &xps_intc_0 3 2 | ||
| 399 | 0x2800 0 0 3 &xps_intc_0 2 2 | ||
| 400 | 0x2800 0 0 4 &xps_intc_0 5 2 | ||
| 401 | */ | ||
| 402 | |||
| 403 | /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */ | ||
| 404 | /* | ||
| 405 | 0x11000 0 0 1 &xps_intc_0 4 0 2 | ||
| 406 | 0x11000 0 0 2 &xps_intc_0 3 0 2 | ||
| 407 | 0x11000 0 0 3 &xps_intc_0 2 0 2 | ||
| 408 | 0x11000 0 0 4 &xps_intc_0 5 0 2 | ||
| 409 | */ | ||
| 410 | |||
| 411 | /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */ | ||
| 412 | 0x0800 0 0 1 &i8259 7 2 | ||
| 413 | |||
| 414 | /* IDSEL 0x1b / dev=11, bus=0 / IDE */ | ||
| 415 | 0x5800 0 0 1 &i8259 14 2 | ||
| 416 | |||
| 417 | /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */ | ||
| 418 | 0x7800 0 0 1 &i8259 7 2 | ||
| 419 | >; | ||
| 420 | ali_m1533 { | ||
| 421 | #size-cells = <1>; | ||
| 422 | #address-cells = <2>; | ||
| 423 | i8259: interrupt-controller@20 { | ||
| 424 | reg = <1 0x20 2 | ||
| 425 | 1 0xa0 2 | ||
| 426 | 1 0x4d0 2>; | ||
| 427 | interrupt-controller; | ||
| 428 | device_type = "interrupt-controller"; | ||
| 429 | #address-cells = <0>; | ||
| 430 | #interrupt-cells = <2>; | ||
| 431 | compatible = "chrp,iic"; | ||
| 432 | |||
| 433 | /* south bridge irq is active high */ | ||
| 434 | interrupts = <1 3>; | ||
| 435 | interrupt-parent = <&xps_intc_0>; | ||
| 436 | }; | ||
| 437 | }; | ||
| 438 | } ; | ||
| 439 | xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { | ||
| 440 | compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; | ||
| 441 | reg = < 0xffff0000 0x10000 >; | ||
| 442 | xlnx,family = "virtex5"; | ||
| 443 | } ; | ||
| 444 | xps_intc_0: interrupt-controller@81800000 { | ||
| 445 | #interrupt-cells = <0x2>; | ||
| 446 | compatible = "xlnx,xps-intc-1.00.a"; | ||
| 447 | interrupt-controller ; | ||
| 448 | reg = < 0x81800000 0x10000 >; | ||
| 449 | xlnx,num-intr-inputs = <0xc>; | ||
| 450 | } ; | ||
| 451 | xps_tft_0: tft@86e00000 { | ||
| 452 | compatible = "xlnx,xps-tft-1.00.a"; | ||
| 453 | reg = < 0x86e00000 0x10000 >; | ||
| 454 | xlnx,dcr-splb-slave-if = <0x1>; | ||
| 455 | xlnx,default-tft-base-addr = <0x0>; | ||
| 456 | xlnx,family = "virtex5"; | ||
| 457 | xlnx,i2c-slave-addr = <0x76>; | ||
| 458 | xlnx,mplb-awidth = <0x20>; | ||
| 459 | xlnx,mplb-dwidth = <0x80>; | ||
| 460 | xlnx,mplb-native-dwidth = <0x40>; | ||
| 461 | xlnx,mplb-smallest-slave = <0x20>; | ||
| 462 | xlnx,tft-interface = <0x1>; | ||
| 463 | } ; | ||
| 464 | } ; | ||
| 465 | } ; | ||
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts index 7e183ff9a317..01bfb56bbe80 100644 --- a/arch/powerpc/boot/dts/warp.dts +++ b/arch/powerpc/boot/dts/warp.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Device Tree Source for PIKA Warp | 2 | * Device Tree Source for PIKA Warp |
| 3 | * | 3 | * |
| 4 | * Copyright (c) 2008 PIKA Technologies | 4 | * Copyright (c) 2008-2009 PIKA Technologies |
| 5 | * Sean MacLennan <smaclennan@pikatech.com> | 5 | * Sean MacLennan <smaclennan@pikatech.com> |
| 6 | * | 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public | 7 | * This file is licensed under the terms of the GNU General Public |
| @@ -158,7 +158,7 @@ | |||
| 158 | 158 | ||
| 159 | partition@0 { | 159 | partition@0 { |
| 160 | label = "splash"; | 160 | label = "splash"; |
| 161 | reg = <0x00000000 0x00020000>; | 161 | reg = <0x00000000 0x00010000>; |
| 162 | }; | 162 | }; |
| 163 | partition@300000 { | 163 | partition@300000 { |
| 164 | label = "fpga"; | 164 | label = "fpga"; |
| @@ -244,28 +244,27 @@ | |||
| 244 | }; | 244 | }; |
| 245 | 245 | ||
| 246 | GPIO0: gpio@ef600b00 { | 246 | GPIO0: gpio@ef600b00 { |
| 247 | compatible = "ibm,gpio-440ep"; | 247 | compatible = "ibm,ppc4xx-gpio"; |
| 248 | reg = <0xef600b00 0x00000048>; | 248 | reg = <0xef600b00 0x00000048>; |
| 249 | #gpio-cells = <2>; | 249 | #gpio-cells = <2>; |
| 250 | gpio-controller; | 250 | gpio-controller; |
| 251 | }; | 251 | }; |
| 252 | 252 | ||
| 253 | GPIO1: gpio@ef600c00 { | 253 | GPIO1: gpio@ef600c00 { |
| 254 | compatible = "ibm,gpio-440ep"; | 254 | compatible = "ibm,ppc4xx-gpio"; |
| 255 | reg = <0xef600c00 0x00000048>; | 255 | reg = <0xef600c00 0x00000048>; |
| 256 | #gpio-cells = <2>; | 256 | #gpio-cells = <2>; |
| 257 | gpio-controller; | 257 | gpio-controller; |
| 258 | }; | ||
| 258 | 259 | ||
| 259 | led@31 { | 260 | power-leds { |
| 260 | compatible = "linux,gpio-led"; | 261 | compatible = "gpio-leds"; |
| 261 | linux,name = ":green:"; | 262 | green { |
| 262 | gpios = <&GPIO1 31 0>; | 263 | gpios = <&GPIO1 0 0>; |
| 263 | }; | 264 | default-state = "on"; |
| 264 | 265 | }; | |
| 265 | led@30 { | 266 | red { |
| 266 | compatible = "linux,gpio-led"; | 267 | gpios = <&GPIO1 1 0>; |
| 267 | linux,name = ":red:"; | ||
| 268 | gpios = <&GPIO1 30 0>; | ||
| 269 | }; | 268 | }; |
| 270 | }; | 269 | }; |
| 271 | 270 | ||
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts new file mode 100644 index 000000000000..ac0a617b4299 --- /dev/null +++ b/arch/powerpc/boot/dts/xcalibur1501.dts | |||
| @@ -0,0 +1,696 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E | ||
| 6 | * | ||
| 7 | * This is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | model = "xes,xcalibur1501"; | ||
| 15 | compatible = "xes,xcalibur1501", "xes,MPC8572"; | ||
| 16 | #address-cells = <2>; | ||
| 17 | #size-cells = <2>; | ||
| 18 | |||
| 19 | aliases { | ||
| 20 | ethernet0 = &enet0; | ||
| 21 | ethernet1 = &enet1; | ||
| 22 | ethernet2 = &enet2; | ||
| 23 | ethernet3 = &enet3; | ||
| 24 | serial0 = &serial0; | ||
| 25 | serial1 = &serial1; | ||
| 26 | pci2 = &pci2; | ||
| 27 | }; | ||
| 28 | |||
| 29 | cpus { | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <0>; | ||
| 32 | |||
| 33 | PowerPC,8572@0 { | ||
| 34 | device_type = "cpu"; | ||
| 35 | reg = <0x0>; | ||
| 36 | d-cache-line-size = <32>; // 32 bytes | ||
| 37 | i-cache-line-size = <32>; // 32 bytes | ||
| 38 | d-cache-size = <0x8000>; // L1, 32K | ||
| 39 | i-cache-size = <0x8000>; // L1, 32K | ||
| 40 | timebase-frequency = <0>; | ||
| 41 | bus-frequency = <0>; | ||
| 42 | clock-frequency = <0>; | ||
| 43 | next-level-cache = <&L2>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | PowerPC,8572@1 { | ||
| 47 | device_type = "cpu"; | ||
| 48 | reg = <0x1>; | ||
| 49 | d-cache-line-size = <32>; // 32 bytes | ||
| 50 | i-cache-line-size = <32>; // 32 bytes | ||
| 51 | d-cache-size = <0x8000>; // L1, 32K | ||
| 52 | i-cache-size = <0x8000>; // L1, 32K | ||
| 53 | timebase-frequency = <0>; | ||
| 54 | bus-frequency = <0>; | ||
| 55 | clock-frequency = <0>; | ||
| 56 | next-level-cache = <&L2>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | memory { | ||
| 61 | device_type = "memory"; | ||
| 62 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | ||
| 63 | }; | ||
| 64 | |||
| 65 | localbus@ef005000 { | ||
| 66 | #address-cells = <2>; | ||
| 67 | #size-cells = <1>; | ||
| 68 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | ||
| 69 | reg = <0 0xef005000 0 0x1000>; | ||
| 70 | interrupts = <19 2>; | ||
| 71 | interrupt-parent = <&mpic>; | ||
| 72 | /* Local bus region mappings */ | ||
| 73 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ | ||
| 74 | 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ | ||
| 75 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | ||
| 76 | 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ | ||
| 77 | 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ | ||
| 78 | |||
| 79 | nor-boot@0,0 { | ||
| 80 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 81 | bank-width = <2>; | ||
| 82 | reg = <0 0 0x8000000>; /* 128MB */ | ||
| 83 | #address-cells = <1>; | ||
| 84 | #size-cells = <1>; | ||
| 85 | partition@0 { | ||
| 86 | label = "Primary user space"; | ||
| 87 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 88 | }; | ||
| 89 | partition@6f00000 { | ||
| 90 | label = "Primary kernel"; | ||
| 91 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 92 | }; | ||
| 93 | partition@7f00000 { | ||
| 94 | label = "Primary DTB"; | ||
| 95 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 96 | }; | ||
| 97 | partition@7f40000 { | ||
| 98 | label = "Primary U-Boot environment"; | ||
| 99 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 100 | }; | ||
| 101 | partition@7f80000 { | ||
| 102 | label = "Primary U-Boot"; | ||
| 103 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 104 | read-only; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | nor-alternate@1,0 { | ||
| 109 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 110 | bank-width = <2>; | ||
| 111 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | ||
| 112 | reg = <1 0 0x8000000>; /* 128MB */ | ||
| 113 | #address-cells = <1>; | ||
| 114 | #size-cells = <1>; | ||
| 115 | partition@0 { | ||
| 116 | label = "Secondary user space"; | ||
| 117 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 118 | }; | ||
| 119 | partition@6f00000 { | ||
| 120 | label = "Secondary kernel"; | ||
| 121 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 122 | }; | ||
| 123 | partition@7f00000 { | ||
| 124 | label = "Secondary DTB"; | ||
| 125 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 126 | }; | ||
| 127 | partition@7f40000 { | ||
| 128 | label = "Secondary U-Boot environment"; | ||
| 129 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 130 | }; | ||
| 131 | partition@7f80000 { | ||
| 132 | label = "Secondary U-Boot"; | ||
| 133 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 134 | read-only; | ||
| 135 | }; | ||
| 136 | }; | ||
| 137 | |||
| 138 | nand@2,0 { | ||
| 139 | #address-cells = <1>; | ||
| 140 | #size-cells = <1>; | ||
| 141 | /* | ||
| 142 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | ||
| 143 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | ||
| 144 | * MT29F16G08FAA (2x 1 GB), depending on the build | ||
| 145 | * configuration | ||
| 146 | */ | ||
| 147 | compatible = "fsl,mpc8572-fcm-nand", | ||
| 148 | "fsl,elbc-fcm-nand"; | ||
| 149 | reg = <2 0 0x40000>; | ||
| 150 | /* U-Boot should fix this up if chip size > 1 GB */ | ||
| 151 | partition@0 { | ||
| 152 | label = "NAND Filesystem"; | ||
| 153 | reg = <0 0x40000000>; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | |||
| 157 | usb@4,0 { | ||
| 158 | compatible = "nxp,usb-isp1761"; | ||
| 159 | reg = <4 0 0x100000>; | ||
| 160 | bus-width = <32>; | ||
| 161 | interrupt-parent = <&mpic>; | ||
| 162 | interrupts = <10 1>; | ||
| 163 | }; | ||
| 164 | }; | ||
| 165 | |||
| 166 | soc8572@ef000000 { | ||
| 167 | #address-cells = <1>; | ||
| 168 | #size-cells = <1>; | ||
| 169 | device_type = "soc"; | ||
| 170 | compatible = "fsl,mpc8572-immr", "simple-bus"; | ||
| 171 | ranges = <0x0 0 0xef000000 0x100000>; | ||
| 172 | bus-frequency = <0>; // Filled out by uboot. | ||
| 173 | |||
| 174 | ecm-law@0 { | ||
| 175 | compatible = "fsl,ecm-law"; | ||
| 176 | reg = <0x0 0x1000>; | ||
| 177 | fsl,num-laws = <12>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | ecm@1000 { | ||
| 181 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 182 | reg = <0x1000 0x1000>; | ||
| 183 | interrupts = <17 2>; | ||
| 184 | interrupt-parent = <&mpic>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | memory-controller@2000 { | ||
| 188 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 189 | reg = <0x2000 0x1000>; | ||
| 190 | interrupt-parent = <&mpic>; | ||
| 191 | interrupts = <18 2>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | memory-controller@6000 { | ||
| 195 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 196 | reg = <0x6000 0x1000>; | ||
| 197 | interrupt-parent = <&mpic>; | ||
| 198 | interrupts = <18 2>; | ||
| 199 | }; | ||
| 200 | |||
| 201 | L2: l2-cache-controller@20000 { | ||
| 202 | compatible = "fsl,mpc8572-l2-cache-controller"; | ||
| 203 | reg = <0x20000 0x1000>; | ||
| 204 | cache-line-size = <32>; // 32 bytes | ||
| 205 | cache-size = <0x100000>; // L2, 1M | ||
| 206 | interrupt-parent = <&mpic>; | ||
| 207 | interrupts = <16 2>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | i2c@3000 { | ||
| 211 | #address-cells = <1>; | ||
| 212 | #size-cells = <0>; | ||
| 213 | cell-index = <0>; | ||
| 214 | compatible = "fsl-i2c"; | ||
| 215 | reg = <0x3000 0x100>; | ||
| 216 | interrupts = <43 2>; | ||
| 217 | interrupt-parent = <&mpic>; | ||
| 218 | dfsrr; | ||
| 219 | |||
| 220 | temp-sensor@48 { | ||
| 221 | compatible = "dallas,ds1631", "dallas,ds1621"; | ||
| 222 | reg = <0x48>; | ||
| 223 | }; | ||
| 224 | |||
| 225 | temp-sensor@4c { | ||
| 226 | compatible = "adi,adt7461"; | ||
| 227 | reg = <0x4c>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | cpu-supervisor@51 { | ||
| 231 | compatible = "dallas,ds4510"; | ||
| 232 | reg = <0x51>; | ||
| 233 | }; | ||
| 234 | |||
| 235 | eeprom@54 { | ||
| 236 | compatible = "atmel,at24c128b"; | ||
| 237 | reg = <0x54>; | ||
| 238 | }; | ||
| 239 | |||
| 240 | rtc@68 { | ||
| 241 | compatible = "stm,m41t00", | ||
| 242 | "dallas,ds1338"; | ||
| 243 | reg = <0x68>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | pcie-switch@6a { | ||
| 247 | compatible = "plx,pex8648"; | ||
| 248 | reg = <0x6a>; | ||
| 249 | }; | ||
| 250 | |||
| 251 | /* On-board signals for VID, flash, serial */ | ||
| 252 | gpio1: gpio@18 { | ||
| 253 | compatible = "nxp,pca9557"; | ||
| 254 | reg = <0x18>; | ||
| 255 | #gpio-cells = <2>; | ||
| 256 | gpio-controller; | ||
| 257 | polarity = <0x00>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | /* PMC0/XMC0 signals */ | ||
| 261 | gpio2: gpio@1c { | ||
| 262 | compatible = "nxp,pca9557"; | ||
| 263 | reg = <0x1c>; | ||
| 264 | #gpio-cells = <2>; | ||
| 265 | gpio-controller; | ||
| 266 | polarity = <0x00>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | /* PMC1/XMC1 signals */ | ||
| 270 | gpio3: gpio@1d { | ||
| 271 | compatible = "nxp,pca9557"; | ||
| 272 | reg = <0x1d>; | ||
| 273 | #gpio-cells = <2>; | ||
| 274 | gpio-controller; | ||
| 275 | polarity = <0x00>; | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* CompactPCI signals (sysen, GA[4:0]) */ | ||
| 279 | gpio4: gpio@1e { | ||
| 280 | compatible = "nxp,pca9557"; | ||
| 281 | reg = <0x1e>; | ||
| 282 | #gpio-cells = <2>; | ||
| 283 | gpio-controller; | ||
| 284 | polarity = <0x00>; | ||
| 285 | }; | ||
| 286 | |||
| 287 | /* CompactPCI J5 GPIO and FAL/DEG/PRST */ | ||
| 288 | gpio5: gpio@1f { | ||
| 289 | compatible = "nxp,pca9557"; | ||
| 290 | reg = <0x1f>; | ||
| 291 | #gpio-cells = <2>; | ||
| 292 | gpio-controller; | ||
| 293 | polarity = <0x00>; | ||
| 294 | }; | ||
| 295 | }; | ||
| 296 | |||
| 297 | i2c@3100 { | ||
| 298 | #address-cells = <1>; | ||
| 299 | #size-cells = <0>; | ||
| 300 | cell-index = <1>; | ||
| 301 | compatible = "fsl-i2c"; | ||
| 302 | reg = <0x3100 0x100>; | ||
| 303 | interrupts = <43 2>; | ||
| 304 | interrupt-parent = <&mpic>; | ||
| 305 | dfsrr; | ||
| 306 | }; | ||
| 307 | |||
| 308 | dma@c300 { | ||
| 309 | #address-cells = <1>; | ||
| 310 | #size-cells = <1>; | ||
| 311 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 312 | reg = <0xc300 0x4>; | ||
| 313 | ranges = <0x0 0xc100 0x200>; | ||
| 314 | cell-index = <1>; | ||
| 315 | dma-channel@0 { | ||
| 316 | compatible = "fsl,mpc8572-dma-channel", | ||
| 317 | "fsl,eloplus-dma-channel"; | ||
| 318 | reg = <0x0 0x80>; | ||
| 319 | cell-index = <0>; | ||
| 320 | interrupt-parent = <&mpic>; | ||
| 321 | interrupts = <76 2>; | ||
| 322 | }; | ||
| 323 | dma-channel@80 { | ||
| 324 | compatible = "fsl,mpc8572-dma-channel", | ||
| 325 | "fsl,eloplus-dma-channel"; | ||
| 326 | reg = <0x80 0x80>; | ||
| 327 | cell-index = <1>; | ||
| 328 | interrupt-parent = <&mpic>; | ||
| 329 | interrupts = <77 2>; | ||
| 330 | }; | ||
| 331 | dma-channel@100 { | ||
| 332 | compatible = "fsl,mpc8572-dma-channel", | ||
| 333 | "fsl,eloplus-dma-channel"; | ||
| 334 | reg = <0x100 0x80>; | ||
| 335 | cell-index = <2>; | ||
| 336 | interrupt-parent = <&mpic>; | ||
| 337 | interrupts = <78 2>; | ||
| 338 | }; | ||
| 339 | dma-channel@180 { | ||
| 340 | compatible = "fsl,mpc8572-dma-channel", | ||
| 341 | "fsl,eloplus-dma-channel"; | ||
| 342 | reg = <0x180 0x80>; | ||
| 343 | cell-index = <3>; | ||
| 344 | interrupt-parent = <&mpic>; | ||
| 345 | interrupts = <79 2>; | ||
| 346 | }; | ||
| 347 | }; | ||
| 348 | |||
| 349 | dma@21300 { | ||
| 350 | #address-cells = <1>; | ||
| 351 | #size-cells = <1>; | ||
| 352 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 353 | reg = <0x21300 0x4>; | ||
| 354 | ranges = <0x0 0x21100 0x200>; | ||
| 355 | cell-index = <0>; | ||
| 356 | dma-channel@0 { | ||
| 357 | compatible = "fsl,mpc8572-dma-channel", | ||
| 358 | "fsl,eloplus-dma-channel"; | ||
| 359 | reg = <0x0 0x80>; | ||
| 360 | cell-index = <0>; | ||
| 361 | interrupt-parent = <&mpic>; | ||
| 362 | interrupts = <20 2>; | ||
| 363 | }; | ||
| 364 | dma-channel@80 { | ||
| 365 | compatible = "fsl,mpc8572-dma-channel", | ||
| 366 | "fsl,eloplus-dma-channel"; | ||
| 367 | reg = <0x80 0x80>; | ||
| 368 | cell-index = <1>; | ||
| 369 | interrupt-parent = <&mpic>; | ||
| 370 | interrupts = <21 2>; | ||
| 371 | }; | ||
| 372 | dma-channel@100 { | ||
| 373 | compatible = "fsl,mpc8572-dma-channel", | ||
| 374 | "fsl,eloplus-dma-channel"; | ||
| 375 | reg = <0x100 0x80>; | ||
| 376 | cell-index = <2>; | ||
| 377 | interrupt-parent = <&mpic>; | ||
| 378 | interrupts = <22 2>; | ||
| 379 | }; | ||
| 380 | dma-channel@180 { | ||
| 381 | compatible = "fsl,mpc8572-dma-channel", | ||
| 382 | "fsl,eloplus-dma-channel"; | ||
| 383 | reg = <0x180 0x80>; | ||
| 384 | cell-index = <3>; | ||
| 385 | interrupt-parent = <&mpic>; | ||
| 386 | interrupts = <23 2>; | ||
| 387 | }; | ||
| 388 | }; | ||
| 389 | |||
| 390 | /* eTSEC 1 front panel 0 */ | ||
| 391 | enet0: ethernet@24000 { | ||
| 392 | #address-cells = <1>; | ||
| 393 | #size-cells = <1>; | ||
| 394 | cell-index = <0>; | ||
| 395 | device_type = "network"; | ||
| 396 | model = "eTSEC"; | ||
| 397 | compatible = "gianfar"; | ||
| 398 | reg = <0x24000 0x1000>; | ||
| 399 | ranges = <0x0 0x24000 0x1000>; | ||
| 400 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 401 | interrupts = <29 2 30 2 34 2>; | ||
| 402 | interrupt-parent = <&mpic>; | ||
| 403 | tbi-handle = <&tbi0>; | ||
| 404 | phy-handle = <&phy0>; | ||
| 405 | phy-connection-type = "sgmii"; | ||
| 406 | |||
| 407 | mdio@520 { | ||
| 408 | #address-cells = <1>; | ||
| 409 | #size-cells = <0>; | ||
| 410 | compatible = "fsl,gianfar-mdio"; | ||
| 411 | reg = <0x520 0x20>; | ||
| 412 | |||
| 413 | phy0: ethernet-phy@1 { | ||
| 414 | interrupt-parent = <&mpic>; | ||
| 415 | interrupts = <4 1>; | ||
| 416 | reg = <0x1>; | ||
| 417 | }; | ||
| 418 | phy1: ethernet-phy@2 { | ||
| 419 | interrupt-parent = <&mpic>; | ||
| 420 | interrupts = <4 1>; | ||
| 421 | reg = <0x2>; | ||
| 422 | }; | ||
| 423 | phy2: ethernet-phy@3 { | ||
| 424 | interrupt-parent = <&mpic>; | ||
| 425 | interrupts = <5 1>; | ||
| 426 | reg = <0x3>; | ||
| 427 | }; | ||
| 428 | phy3: ethernet-phy@4 { | ||
| 429 | interrupt-parent = <&mpic>; | ||
| 430 | interrupts = <5 1>; | ||
| 431 | reg = <0x4>; | ||
| 432 | }; | ||
| 433 | tbi0: tbi-phy@11 { | ||
| 434 | reg = <0x11>; | ||
| 435 | device_type = "tbi-phy"; | ||
| 436 | }; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | |||
| 440 | /* eTSEC 2 front panel 1 */ | ||
| 441 | enet1: ethernet@25000 { | ||
| 442 | #address-cells = <1>; | ||
| 443 | #size-cells = <1>; | ||
| 444 | cell-index = <1>; | ||
| 445 | device_type = "network"; | ||
| 446 | model = "eTSEC"; | ||
| 447 | compatible = "gianfar"; | ||
| 448 | reg = <0x25000 0x1000>; | ||
| 449 | ranges = <0x0 0x25000 0x1000>; | ||
| 450 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 451 | interrupts = <35 2 36 2 40 2>; | ||
| 452 | interrupt-parent = <&mpic>; | ||
| 453 | tbi-handle = <&tbi1>; | ||
| 454 | phy-handle = <&phy1>; | ||
| 455 | phy-connection-type = "sgmii"; | ||
| 456 | |||
| 457 | mdio@520 { | ||
| 458 | #address-cells = <1>; | ||
| 459 | #size-cells = <0>; | ||
| 460 | compatible = "fsl,gianfar-tbi"; | ||
| 461 | reg = <0x520 0x20>; | ||
| 462 | |||
| 463 | tbi1: tbi-phy@11 { | ||
| 464 | reg = <0x11>; | ||
| 465 | device_type = "tbi-phy"; | ||
| 466 | }; | ||
| 467 | }; | ||
| 468 | }; | ||
| 469 | |||
| 470 | /* eTSEC 3 PICMG2.16 backplane port 0 */ | ||
| 471 | enet2: ethernet@26000 { | ||
| 472 | #address-cells = <1>; | ||
| 473 | #size-cells = <1>; | ||
| 474 | cell-index = <2>; | ||
| 475 | device_type = "network"; | ||
| 476 | model = "eTSEC"; | ||
| 477 | compatible = "gianfar"; | ||
| 478 | reg = <0x26000 0x1000>; | ||
| 479 | ranges = <0x0 0x26000 0x1000>; | ||
| 480 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 481 | interrupts = <31 2 32 2 33 2>; | ||
| 482 | interrupt-parent = <&mpic>; | ||
| 483 | tbi-handle = <&tbi2>; | ||
| 484 | phy-handle = <&phy2>; | ||
| 485 | phy-connection-type = "sgmii"; | ||
| 486 | |||
| 487 | mdio@520 { | ||
| 488 | #address-cells = <1>; | ||
| 489 | #size-cells = <0>; | ||
| 490 | compatible = "fsl,gianfar-tbi"; | ||
| 491 | reg = <0x520 0x20>; | ||
| 492 | |||
| 493 | tbi2: tbi-phy@11 { | ||
| 494 | reg = <0x11>; | ||
| 495 | device_type = "tbi-phy"; | ||
| 496 | }; | ||
| 497 | }; | ||
| 498 | }; | ||
| 499 | |||
| 500 | /* eTSEC 4 PICMG2.16 backplane port 1 */ | ||
| 501 | enet3: ethernet@27000 { | ||
| 502 | #address-cells = <1>; | ||
| 503 | #size-cells = <1>; | ||
| 504 | cell-index = <3>; | ||
| 505 | device_type = "network"; | ||
| 506 | model = "eTSEC"; | ||
| 507 | compatible = "gianfar"; | ||
| 508 | reg = <0x27000 0x1000>; | ||
| 509 | ranges = <0x0 0x27000 0x1000>; | ||
| 510 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 511 | interrupts = <37 2 38 2 39 2>; | ||
| 512 | interrupt-parent = <&mpic>; | ||
| 513 | tbi-handle = <&tbi3>; | ||
| 514 | phy-handle = <&phy3>; | ||
| 515 | phy-connection-type = "sgmii"; | ||
| 516 | |||
| 517 | mdio@520 { | ||
| 518 | #address-cells = <1>; | ||
| 519 | #size-cells = <0>; | ||
| 520 | compatible = "fsl,gianfar-tbi"; | ||
| 521 | reg = <0x520 0x20>; | ||
| 522 | |||
| 523 | tbi3: tbi-phy@11 { | ||
| 524 | reg = <0x11>; | ||
| 525 | device_type = "tbi-phy"; | ||
| 526 | }; | ||
| 527 | }; | ||
| 528 | }; | ||
| 529 | |||
| 530 | /* UART0 */ | ||
| 531 | serial0: serial@4500 { | ||
| 532 | cell-index = <0>; | ||
| 533 | device_type = "serial"; | ||
| 534 | compatible = "ns16550"; | ||
| 535 | reg = <0x4500 0x100>; | ||
| 536 | clock-frequency = <0>; | ||
| 537 | interrupts = <42 2>; | ||
| 538 | interrupt-parent = <&mpic>; | ||
| 539 | }; | ||
| 540 | |||
| 541 | /* UART1 */ | ||
| 542 | serial1: serial@4600 { | ||
| 543 | cell-index = <1>; | ||
| 544 | device_type = "serial"; | ||
| 545 | compatible = "ns16550"; | ||
| 546 | reg = <0x4600 0x100>; | ||
| 547 | clock-frequency = <0>; | ||
| 548 | interrupts = <42 2>; | ||
| 549 | interrupt-parent = <&mpic>; | ||
| 550 | }; | ||
| 551 | |||
| 552 | global-utilities@e0000 { //global utilities block | ||
| 553 | compatible = "fsl,mpc8572-guts"; | ||
| 554 | reg = <0xe0000 0x1000>; | ||
| 555 | fsl,has-rstcr; | ||
| 556 | }; | ||
| 557 | |||
| 558 | msi@41600 { | ||
| 559 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | ||
| 560 | reg = <0x41600 0x80>; | ||
| 561 | msi-available-ranges = <0 0x100>; | ||
| 562 | interrupts = < | ||
| 563 | 0xe0 0 | ||
| 564 | 0xe1 0 | ||
| 565 | 0xe2 0 | ||
| 566 | 0xe3 0 | ||
| 567 | 0xe4 0 | ||
| 568 | 0xe5 0 | ||
| 569 | 0xe6 0 | ||
| 570 | 0xe7 0>; | ||
| 571 | interrupt-parent = <&mpic>; | ||
| 572 | }; | ||
| 573 | |||
| 574 | crypto@30000 { | ||
| 575 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | ||
| 576 | "fsl,sec2.1", "fsl,sec2.0"; | ||
| 577 | reg = <0x30000 0x10000>; | ||
| 578 | interrupts = <45 2 58 2>; | ||
| 579 | interrupt-parent = <&mpic>; | ||
| 580 | fsl,num-channels = <4>; | ||
| 581 | fsl,channel-fifo-len = <24>; | ||
| 582 | fsl,exec-units-mask = <0x9fe>; | ||
| 583 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 584 | }; | ||
| 585 | |||
| 586 | mpic: pic@40000 { | ||
| 587 | interrupt-controller; | ||
| 588 | #address-cells = <0>; | ||
| 589 | #interrupt-cells = <2>; | ||
| 590 | reg = <0x40000 0x40000>; | ||
| 591 | compatible = "chrp,open-pic"; | ||
| 592 | device_type = "open-pic"; | ||
| 593 | }; | ||
| 594 | |||
| 595 | gpio0: gpio@f000 { | ||
| 596 | compatible = "fsl,mpc8572-gpio"; | ||
| 597 | reg = <0xf000 0x1000>; | ||
| 598 | interrupts = <47 2>; | ||
| 599 | interrupt-parent = <&mpic>; | ||
| 600 | #gpio-cells = <2>; | ||
| 601 | gpio-controller; | ||
| 602 | }; | ||
| 603 | |||
| 604 | gpio-leds { | ||
| 605 | compatible = "gpio-leds"; | ||
| 606 | |||
| 607 | heartbeat { | ||
| 608 | label = "Heartbeat"; | ||
| 609 | gpios = <&gpio0 4 1>; | ||
| 610 | linux,default-trigger = "heartbeat"; | ||
| 611 | }; | ||
| 612 | |||
| 613 | yellow { | ||
| 614 | label = "Yellow"; | ||
| 615 | gpios = <&gpio0 5 1>; | ||
| 616 | }; | ||
| 617 | |||
| 618 | red { | ||
| 619 | label = "Red"; | ||
| 620 | gpios = <&gpio0 6 1>; | ||
| 621 | }; | ||
| 622 | |||
| 623 | green { | ||
| 624 | label = "Green"; | ||
| 625 | gpios = <&gpio0 7 1>; | ||
| 626 | }; | ||
| 627 | }; | ||
| 628 | |||
| 629 | /* PME (pattern-matcher) */ | ||
| 630 | pme@10000 { | ||
| 631 | compatible = "fsl,mpc8572-pme", "pme8572"; | ||
| 632 | reg = <0x10000 0x5000>; | ||
| 633 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | ||
| 634 | interrupt-parent = <&mpic>; | ||
| 635 | }; | ||
| 636 | |||
| 637 | tlu@2f000 { | ||
| 638 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 639 | reg = <0x2f000 0x1000>; | ||
| 640 | interupts = <61 2 >; | ||
| 641 | interrupt-parent = <&mpic>; | ||
| 642 | }; | ||
| 643 | |||
| 644 | tlu@15000 { | ||
| 645 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 646 | reg = <0x15000 0x1000>; | ||
| 647 | interupts = <75 2>; | ||
| 648 | interrupt-parent = <&mpic>; | ||
| 649 | }; | ||
| 650 | }; | ||
| 651 | |||
| 652 | /* | ||
| 653 | * PCI Express controller 3 @ ef008000 is not used. | ||
| 654 | * This would have been pci0 on other mpc85xx platforms. | ||
| 655 | * | ||
| 656 | * PCI Express controller 2 @ ef009000 is not used. | ||
| 657 | * This would have been pci1 on other mpc85xx platforms. | ||
| 658 | */ | ||
| 659 | |||
| 660 | /* PCI Express controller 1, wired to PEX8648 PCIe switch */ | ||
| 661 | pci2: pcie@ef00a000 { | ||
| 662 | compatible = "fsl,mpc8548-pcie"; | ||
| 663 | device_type = "pci"; | ||
| 664 | #interrupt-cells = <1>; | ||
| 665 | #size-cells = <2>; | ||
| 666 | #address-cells = <3>; | ||
| 667 | reg = <0 0xef00a000 0 0x1000>; | ||
| 668 | bus-range = <0 255>; | ||
| 669 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | ||
| 670 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | ||
| 671 | clock-frequency = <33333333>; | ||
| 672 | interrupt-parent = <&mpic>; | ||
| 673 | interrupts = <26 2>; | ||
| 674 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 675 | interrupt-map = < | ||
| 676 | /* IDSEL 0x0 */ | ||
| 677 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 678 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 679 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 680 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 681 | >; | ||
| 682 | pcie@0 { | ||
| 683 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 684 | #size-cells = <2>; | ||
| 685 | #address-cells = <3>; | ||
| 686 | device_type = "pci"; | ||
| 687 | ranges = <0x2000000 0x0 0x80000000 | ||
| 688 | 0x2000000 0x0 0x80000000 | ||
| 689 | 0x0 0x40000000 | ||
| 690 | |||
| 691 | 0x1000000 0x0 0x0 | ||
| 692 | 0x1000000 0x0 0x0 | ||
| 693 | 0x0 0x100000>; | ||
| 694 | }; | ||
| 695 | }; | ||
| 696 | }; | ||
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts new file mode 100644 index 000000000000..a0cf53fbd55c --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5200.dts | |||
| @@ -0,0 +1,466 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on TQM8548 device tree | ||
| 4 | * | ||
| 5 | * XPedite5200 PrPMC/XMC module based on MPC8548E | ||
| 6 | * | ||
| 7 | * This is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "xes,xpedite5200"; | ||
| 16 | compatible = "xes,xpedite5200", "xes,MPC8548"; | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <1>; | ||
| 19 | |||
| 20 | aliases { | ||
| 21 | ethernet0 = &enet0; | ||
| 22 | ethernet1 = &enet1; | ||
| 23 | ethernet2 = &enet2; | ||
| 24 | ethernet3 = &enet3; | ||
| 25 | |||
| 26 | serial0 = &serial0; | ||
| 27 | serial1 = &serial1; | ||
| 28 | pci0 = &pci0; | ||
| 29 | }; | ||
| 30 | |||
| 31 | cpus { | ||
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | |||
| 35 | PowerPC,8548@0 { | ||
| 36 | device_type = "cpu"; | ||
| 37 | reg = <0>; | ||
| 38 | d-cache-line-size = <32>; // 32 bytes | ||
| 39 | i-cache-line-size = <32>; // 32 bytes | ||
| 40 | d-cache-size = <0x8000>; // L1, 32K | ||
| 41 | i-cache-size = <0x8000>; // L1, 32K | ||
| 42 | next-level-cache = <&L2>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | memory { | ||
| 47 | device_type = "memory"; | ||
| 48 | reg = <0x0 0x0>; // Filled in by U-Boot | ||
| 49 | }; | ||
| 50 | |||
| 51 | soc@ef000000 { | ||
| 52 | #address-cells = <1>; | ||
| 53 | #size-cells = <1>; | ||
| 54 | device_type = "soc"; | ||
| 55 | ranges = <0x0 0xef000000 0x100000>; | ||
| 56 | bus-frequency = <0>; | ||
| 57 | compatible = "fsl,mpc8548-immr", "simple-bus"; | ||
| 58 | |||
| 59 | ecm-law@0 { | ||
| 60 | compatible = "fsl,ecm-law"; | ||
| 61 | reg = <0x0 0x1000>; | ||
| 62 | fsl,num-laws = <12>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | ecm@1000 { | ||
| 66 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 67 | reg = <0x1000 0x1000>; | ||
| 68 | interrupts = <17 2>; | ||
| 69 | interrupt-parent = <&mpic>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | memory-controller@2000 { | ||
| 73 | compatible = "fsl,mpc8548-memory-controller"; | ||
| 74 | reg = <0x2000 0x1000>; | ||
| 75 | interrupt-parent = <&mpic>; | ||
| 76 | interrupts = <18 2>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | L2: l2-cache-controller@20000 { | ||
| 80 | compatible = "fsl,mpc8548-l2-cache-controller"; | ||
| 81 | reg = <0x20000 0x1000>; | ||
| 82 | cache-line-size = <32>; // 32 bytes | ||
| 83 | cache-size = <0x80000>; // L2, 512K | ||
| 84 | interrupt-parent = <&mpic>; | ||
| 85 | interrupts = <16 2>; | ||
| 86 | }; | ||
| 87 | |||
| 88 | /* On-card I2C */ | ||
| 89 | i2c@3000 { | ||
| 90 | #address-cells = <1>; | ||
| 91 | #size-cells = <0>; | ||
| 92 | cell-index = <0>; | ||
| 93 | compatible = "fsl-i2c"; | ||
| 94 | reg = <0x3000 0x100>; | ||
| 95 | interrupts = <43 2>; | ||
| 96 | interrupt-parent = <&mpic>; | ||
| 97 | dfsrr; | ||
| 98 | |||
| 99 | /* | ||
| 100 | * Board GPIO: | ||
| 101 | * 0: BRD_CFG0 (1: P14 IO present) | ||
| 102 | * 1: BRD_CFG1 (1: FP ethernet present) | ||
| 103 | * 2: BRD_CFG2 (1: XMC IO present) | ||
| 104 | * 3: XMC root complex indicator | ||
| 105 | * 4: Flash boot device indicator | ||
| 106 | * 5: Flash write protect enable | ||
| 107 | * 6: PMC monarch indicator | ||
| 108 | * 7: PMC EREADY | ||
| 109 | */ | ||
| 110 | gpio1: gpio@18 { | ||
| 111 | compatible = "nxp,pca9556"; | ||
| 112 | reg = <0x18>; | ||
| 113 | #gpio-cells = <2>; | ||
| 114 | gpio-controller; | ||
| 115 | polarity = <0x00>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | /* P14 GPIO */ | ||
| 119 | gpio2: gpio@19 { | ||
| 120 | compatible = "nxp,pca9556"; | ||
| 121 | reg = <0x19>; | ||
| 122 | #gpio-cells = <2>; | ||
| 123 | gpio-controller; | ||
| 124 | polarity = <0x00>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | eeprom@50 { | ||
| 128 | compatible = "atmel,at24c16"; | ||
| 129 | reg = <0x50>; | ||
| 130 | }; | ||
| 131 | |||
| 132 | rtc@68 { | ||
| 133 | compatible = "stm,m41t00", | ||
| 134 | "dallas,ds1338"; | ||
| 135 | reg = <0x68>; | ||
| 136 | }; | ||
| 137 | |||
| 138 | dtt@48 { | ||
| 139 | compatible = "maxim,max1237"; | ||
| 140 | reg = <0x34>; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | /* Off-card I2C */ | ||
| 145 | i2c@3100 { | ||
| 146 | #address-cells = <1>; | ||
| 147 | #size-cells = <0>; | ||
| 148 | cell-index = <1>; | ||
| 149 | compatible = "fsl-i2c"; | ||
| 150 | reg = <0x3100 0x100>; | ||
| 151 | interrupts = <43 2>; | ||
| 152 | interrupt-parent = <&mpic>; | ||
| 153 | dfsrr; | ||
| 154 | }; | ||
| 155 | |||
| 156 | dma@21300 { | ||
| 157 | #address-cells = <1>; | ||
| 158 | #size-cells = <1>; | ||
| 159 | compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; | ||
| 160 | reg = <0x21300 0x4>; | ||
| 161 | ranges = <0x0 0x21100 0x200>; | ||
| 162 | cell-index = <0>; | ||
| 163 | dma-channel@0 { | ||
| 164 | compatible = "fsl,mpc8548-dma-channel", | ||
| 165 | "fsl,eloplus-dma-channel"; | ||
| 166 | reg = <0x0 0x80>; | ||
| 167 | cell-index = <0>; | ||
| 168 | interrupt-parent = <&mpic>; | ||
| 169 | interrupts = <20 2>; | ||
| 170 | }; | ||
| 171 | dma-channel@80 { | ||
| 172 | compatible = "fsl,mpc8548-dma-channel", | ||
| 173 | "fsl,eloplus-dma-channel"; | ||
| 174 | reg = <0x80 0x80>; | ||
| 175 | cell-index = <1>; | ||
| 176 | interrupt-parent = <&mpic>; | ||
| 177 | interrupts = <21 2>; | ||
| 178 | }; | ||
| 179 | dma-channel@100 { | ||
| 180 | compatible = "fsl,mpc8548-dma-channel", | ||
| 181 | "fsl,eloplus-dma-channel"; | ||
| 182 | reg = <0x100 0x80>; | ||
| 183 | cell-index = <2>; | ||
| 184 | interrupt-parent = <&mpic>; | ||
| 185 | interrupts = <22 2>; | ||
| 186 | }; | ||
| 187 | dma-channel@180 { | ||
| 188 | compatible = "fsl,mpc8548-dma-channel", | ||
| 189 | "fsl,eloplus-dma-channel"; | ||
| 190 | reg = <0x180 0x80>; | ||
| 191 | cell-index = <3>; | ||
| 192 | interrupt-parent = <&mpic>; | ||
| 193 | interrupts = <23 2>; | ||
| 194 | }; | ||
| 195 | }; | ||
| 196 | |||
| 197 | /* eTSEC1: Front panel port 0 */ | ||
| 198 | enet0: ethernet@24000 { | ||
| 199 | #address-cells = <1>; | ||
| 200 | #size-cells = <1>; | ||
| 201 | cell-index = <0>; | ||
| 202 | device_type = "network"; | ||
| 203 | model = "eTSEC"; | ||
| 204 | compatible = "gianfar"; | ||
| 205 | reg = <0x24000 0x1000>; | ||
| 206 | ranges = <0x0 0x24000 0x1000>; | ||
| 207 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 208 | interrupts = <29 2 30 2 34 2>; | ||
| 209 | interrupt-parent = <&mpic>; | ||
| 210 | tbi-handle = <&tbi0>; | ||
| 211 | phy-handle = <&phy0>; | ||
| 212 | |||
| 213 | mdio@520 { | ||
| 214 | #address-cells = <1>; | ||
| 215 | #size-cells = <0>; | ||
| 216 | compatible = "fsl,gianfar-mdio"; | ||
| 217 | reg = <0x520 0x20>; | ||
| 218 | |||
| 219 | phy0: ethernet-phy@1 { | ||
| 220 | interrupt-parent = <&mpic>; | ||
| 221 | interrupts = <8 1>; | ||
| 222 | reg = <0x1>; | ||
| 223 | }; | ||
| 224 | phy1: ethernet-phy@2 { | ||
| 225 | interrupt-parent = <&mpic>; | ||
| 226 | interrupts = <8 1>; | ||
| 227 | reg = <0x2>; | ||
| 228 | }; | ||
| 229 | phy2: ethernet-phy@3 { | ||
| 230 | interrupt-parent = <&mpic>; | ||
| 231 | interrupts = <8 1>; | ||
| 232 | reg = <0x3>; | ||
| 233 | }; | ||
| 234 | phy3: ethernet-phy@4 { | ||
| 235 | interrupt-parent = <&mpic>; | ||
| 236 | interrupts = <8 1>; | ||
| 237 | reg = <0x4>; | ||
| 238 | }; | ||
| 239 | tbi0: tbi-phy@11 { | ||
| 240 | reg = <0x11>; | ||
| 241 | device_type = "tbi-phy"; | ||
| 242 | }; | ||
| 243 | }; | ||
| 244 | }; | ||
| 245 | |||
| 246 | /* eTSEC2: Front panel port 1 */ | ||
| 247 | enet1: ethernet@25000 { | ||
| 248 | #address-cells = <1>; | ||
| 249 | #size-cells = <1>; | ||
| 250 | cell-index = <1>; | ||
| 251 | device_type = "network"; | ||
| 252 | model = "eTSEC"; | ||
| 253 | compatible = "gianfar"; | ||
| 254 | reg = <0x25000 0x1000>; | ||
| 255 | ranges = <0x0 0x25000 0x1000>; | ||
| 256 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 257 | interrupts = <35 2 36 2 40 2>; | ||
| 258 | interrupt-parent = <&mpic>; | ||
| 259 | tbi-handle = <&tbi1>; | ||
| 260 | phy-handle = <&phy1>; | ||
| 261 | |||
| 262 | mdio@520 { | ||
| 263 | #address-cells = <1>; | ||
| 264 | #size-cells = <0>; | ||
| 265 | compatible = "fsl,gianfar-tbi"; | ||
| 266 | reg = <0x520 0x20>; | ||
| 267 | |||
| 268 | tbi1: tbi-phy@11 { | ||
| 269 | reg = <0x11>; | ||
| 270 | device_type = "tbi-phy"; | ||
| 271 | }; | ||
| 272 | }; | ||
| 273 | }; | ||
| 274 | |||
| 275 | /* eTSEC3: Rear panel port 2 */ | ||
| 276 | enet2: ethernet@26000 { | ||
| 277 | #address-cells = <1>; | ||
| 278 | #size-cells = <1>; | ||
| 279 | cell-index = <2>; | ||
| 280 | device_type = "network"; | ||
| 281 | model = "eTSEC"; | ||
| 282 | compatible = "gianfar"; | ||
| 283 | reg = <0x26000 0x1000>; | ||
| 284 | ranges = <0x0 0x26000 0x1000>; | ||
| 285 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 286 | interrupts = <31 2 32 2 33 2>; | ||
| 287 | interrupt-parent = <&mpic>; | ||
| 288 | tbi-handle = <&tbi2>; | ||
| 289 | phy-handle = <&phy2>; | ||
| 290 | |||
| 291 | mdio@520 { | ||
| 292 | #address-cells = <1>; | ||
| 293 | #size-cells = <0>; | ||
| 294 | compatible = "fsl,gianfar-tbi"; | ||
| 295 | reg = <0x520 0x20>; | ||
| 296 | |||
| 297 | tbi2: tbi-phy@11 { | ||
| 298 | reg = <0x11>; | ||
| 299 | device_type = "tbi-phy"; | ||
| 300 | }; | ||
| 301 | }; | ||
| 302 | }; | ||
| 303 | |||
| 304 | /* eTSEC4: Rear panel port 3 */ | ||
| 305 | enet3: ethernet@27000 { | ||
| 306 | #address-cells = <1>; | ||
| 307 | #size-cells = <1>; | ||
| 308 | cell-index = <3>; | ||
| 309 | device_type = "network"; | ||
| 310 | model = "eTSEC"; | ||
| 311 | compatible = "gianfar"; | ||
| 312 | reg = <0x27000 0x1000>; | ||
| 313 | ranges = <0x0 0x27000 0x1000>; | ||
| 314 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 315 | interrupts = <37 2 38 2 39 2>; | ||
| 316 | interrupt-parent = <&mpic>; | ||
| 317 | tbi-handle = <&tbi3>; | ||
| 318 | phy-handle = <&phy3>; | ||
| 319 | |||
| 320 | mdio@520 { | ||
| 321 | #address-cells = <1>; | ||
| 322 | #size-cells = <0>; | ||
| 323 | compatible = "fsl,gianfar-tbi"; | ||
| 324 | reg = <0x520 0x20>; | ||
| 325 | |||
| 326 | tbi3: tbi-phy@11 { | ||
| 327 | reg = <0x11>; | ||
| 328 | device_type = "tbi-phy"; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | }; | ||
| 332 | |||
| 333 | serial0: serial@4500 { | ||
| 334 | cell-index = <0>; | ||
| 335 | device_type = "serial"; | ||
| 336 | compatible = "ns16550"; | ||
| 337 | reg = <0x4500 0x100>; | ||
| 338 | clock-frequency = <0>; | ||
| 339 | current-speed = <115200>; | ||
| 340 | interrupts = <42 2>; | ||
| 341 | interrupt-parent = <&mpic>; | ||
| 342 | }; | ||
| 343 | |||
| 344 | serial1: serial@4600 { | ||
| 345 | cell-index = <1>; | ||
| 346 | device_type = "serial"; | ||
| 347 | compatible = "ns16550"; | ||
| 348 | reg = <0x4600 0x100>; | ||
| 349 | clock-frequency = <0>; | ||
| 350 | current-speed = <115200>; | ||
| 351 | interrupts = <42 2>; | ||
| 352 | interrupt-parent = <&mpic>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | global-utilities@e0000 { // global utilities reg | ||
| 356 | compatible = "fsl,mpc8548-guts"; | ||
| 357 | reg = <0xe0000 0x1000>; | ||
| 358 | fsl,has-rstcr; | ||
| 359 | }; | ||
| 360 | |||
| 361 | mpic: pic@40000 { | ||
| 362 | interrupt-controller; | ||
| 363 | #address-cells = <0>; | ||
| 364 | #interrupt-cells = <2>; | ||
| 365 | reg = <0x40000 0x40000>; | ||
| 366 | compatible = "chrp,open-pic"; | ||
| 367 | device_type = "open-pic"; | ||
| 368 | }; | ||
| 369 | }; | ||
| 370 | |||
| 371 | localbus@ef005000 { | ||
| 372 | compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", | ||
| 373 | "simple-bus"; | ||
| 374 | #address-cells = <2>; | ||
| 375 | #size-cells = <1>; | ||
| 376 | reg = <0xef005000 0x100>; // BRx, ORx, etc. | ||
| 377 | |||
| 378 | ranges = < | ||
| 379 | 0 0x0 0xfc000000 0x04000000 // NOR boot flash | ||
| 380 | 1 0x0 0xf8000000 0x04000000 // NOR expansion flash | ||
| 381 | 2 0x0 0xef800000 0x00010000 // NAND CE1 | ||
| 382 | 3 0x0 0xef840000 0x00010000 // NAND CE2 | ||
| 383 | >; | ||
| 384 | |||
| 385 | nor-boot@0,0 { | ||
| 386 | #address-cells = <1>; | ||
| 387 | #size-cells = <1>; | ||
| 388 | compatible = "cfi-flash"; | ||
| 389 | reg = <0 0x0 0x4000000>; | ||
| 390 | bank-width = <2>; | ||
| 391 | |||
| 392 | partition@0 { | ||
| 393 | label = "Primary OS"; | ||
| 394 | reg = <0x00000000 0x180000>; | ||
| 395 | }; | ||
| 396 | partition@180000 { | ||
| 397 | label = "Secondary OS"; | ||
| 398 | reg = <0x00180000 0x180000>; | ||
| 399 | }; | ||
| 400 | partition@300000 { | ||
| 401 | label = "User"; | ||
| 402 | reg = <0x00300000 0x3c80000>; | ||
| 403 | }; | ||
| 404 | partition@3f80000 { | ||
| 405 | label = "Boot firmware"; | ||
| 406 | reg = <0x03f80000 0x80000>; | ||
| 407 | }; | ||
| 408 | }; | ||
| 409 | |||
| 410 | nor-alternate@1,0 { | ||
| 411 | #address-cells = <1>; | ||
| 412 | #size-cells = <1>; | ||
| 413 | compatible = "cfi-flash"; | ||
| 414 | reg = <1 0x0 0x4000000>; | ||
| 415 | bank-width = <2>; | ||
| 416 | |||
| 417 | partition@0 { | ||
| 418 | label = "Filesystem"; | ||
| 419 | reg = <0x00000000 0x3f80000>; | ||
| 420 | }; | ||
| 421 | partition@3f80000 { | ||
| 422 | label = "Alternate boot firmware"; | ||
| 423 | reg = <0x03f80000 0x80000>; | ||
| 424 | }; | ||
| 425 | }; | ||
| 426 | |||
| 427 | nand@2,0 { | ||
| 428 | #address-cells = <1>; | ||
| 429 | #size-cells = <1>; | ||
| 430 | compatible = "xes,address-ctl-nand"; | ||
| 431 | reg = <2 0x0 0x10000>; | ||
| 432 | cle-line = <0x8>; /* CLE tied to A3 */ | ||
| 433 | ale-line = <0x10>; /* ALE tied to A4 */ | ||
| 434 | |||
| 435 | /* U-Boot should fix this up */ | ||
| 436 | partition@0 { | ||
| 437 | label = "NAND Filesystem"; | ||
| 438 | reg = <0 0x40000000>; | ||
| 439 | }; | ||
| 440 | }; | ||
| 441 | }; | ||
| 442 | |||
| 443 | /* PMC interface */ | ||
| 444 | pci0: pci@ef008000 { | ||
| 445 | #interrupt-cells = <1>; | ||
| 446 | #size-cells = <2>; | ||
| 447 | #address-cells = <3>; | ||
| 448 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | ||
| 449 | device_type = "pci"; | ||
| 450 | reg = <0xef008000 0x1000>; | ||
| 451 | clock-frequency = <33333333>; | ||
| 452 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 453 | interrupt-map = < | ||
| 454 | /* IDSEL */ | ||
| 455 | 0xe000 0 0 1 &mpic 2 1 | ||
| 456 | 0xe000 0 0 2 &mpic 3 1>; | ||
| 457 | |||
| 458 | interrupt-parent = <&mpic>; | ||
| 459 | interrupts = <24 2>; | ||
| 460 | bus-range = <0 0>; | ||
| 461 | ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000 | ||
| 462 | 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>; | ||
| 463 | }; | ||
| 464 | |||
| 465 | /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */ | ||
| 466 | }; | ||
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts new file mode 100644 index 000000000000..c5b29752651a --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts | |||
| @@ -0,0 +1,506 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on TQM8548 device tree | ||
| 4 | * | ||
| 5 | * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the | ||
| 6 | * xMon boot loader memory map which differs from U-Boot's. | ||
| 7 | * | ||
| 8 | * This is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "xes,xpedite5200"; | ||
| 17 | compatible = "xes,xpedite5200", "xes,MPC8548"; | ||
| 18 | #address-cells = <1>; | ||
| 19 | #size-cells = <1>; | ||
| 20 | form-factor = "PMC/XMC"; | ||
| 21 | boot-bank = <0x0>; | ||
| 22 | |||
| 23 | aliases { | ||
| 24 | ethernet0 = &enet0; | ||
| 25 | ethernet1 = &enet1; | ||
| 26 | ethernet2 = &enet2; | ||
| 27 | ethernet3 = &enet3; | ||
| 28 | |||
| 29 | serial0 = &serial0; | ||
| 30 | serial1 = &serial1; | ||
| 31 | pci0 = &pci0; | ||
| 32 | pci1 = &pci1; | ||
| 33 | }; | ||
| 34 | |||
| 35 | cpus { | ||
| 36 | #address-cells = <1>; | ||
| 37 | #size-cells = <0>; | ||
| 38 | |||
| 39 | PowerPC,8548@0 { | ||
| 40 | device_type = "cpu"; | ||
| 41 | reg = <0>; | ||
| 42 | d-cache-line-size = <32>; // 32 bytes | ||
| 43 | i-cache-line-size = <32>; // 32 bytes | ||
| 44 | d-cache-size = <0x8000>; // L1, 32K | ||
| 45 | i-cache-size = <0x8000>; // L1, 32K | ||
| 46 | next-level-cache = <&L2>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | |||
| 50 | memory { | ||
| 51 | device_type = "memory"; | ||
| 52 | reg = <0x0 0x0>; // Filled in by boot loader | ||
| 53 | }; | ||
| 54 | |||
| 55 | soc@ef000000 { | ||
| 56 | #address-cells = <1>; | ||
| 57 | #size-cells = <1>; | ||
| 58 | device_type = "soc"; | ||
| 59 | ranges = <0x0 0xef000000 0x100000>; | ||
| 60 | bus-frequency = <0>; | ||
| 61 | compatible = "fsl,mpc8548-immr", "simple-bus"; | ||
| 62 | |||
| 63 | ecm-law@0 { | ||
| 64 | compatible = "fsl,ecm-law"; | ||
| 65 | reg = <0x0 0x1000>; | ||
| 66 | fsl,num-laws = <12>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | ecm@1000 { | ||
| 70 | compatible = "fsl,mpc8548-ecm", "fsl,ecm"; | ||
| 71 | reg = <0x1000 0x1000>; | ||
| 72 | interrupts = <17 2>; | ||
| 73 | interrupt-parent = <&mpic>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | memory-controller@2000 { | ||
| 77 | compatible = "fsl,mpc8548-memory-controller"; | ||
| 78 | reg = <0x2000 0x1000>; | ||
| 79 | interrupt-parent = <&mpic>; | ||
| 80 | interrupts = <18 2>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | L2: l2-cache-controller@20000 { | ||
| 84 | compatible = "fsl,mpc8548-l2-cache-controller"; | ||
| 85 | reg = <0x20000 0x1000>; | ||
| 86 | cache-line-size = <32>; // 32 bytes | ||
| 87 | cache-size = <0x80000>; // L2, 512K | ||
| 88 | interrupt-parent = <&mpic>; | ||
| 89 | interrupts = <16 2>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | /* On-card I2C */ | ||
| 93 | i2c@3000 { | ||
| 94 | #address-cells = <1>; | ||
| 95 | #size-cells = <0>; | ||
| 96 | cell-index = <0>; | ||
| 97 | compatible = "fsl-i2c"; | ||
| 98 | reg = <0x3000 0x100>; | ||
| 99 | interrupts = <43 2>; | ||
| 100 | interrupt-parent = <&mpic>; | ||
| 101 | dfsrr; | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Board GPIO: | ||
| 105 | * 0: BRD_CFG0 (1: P14 IO present) | ||
| 106 | * 1: BRD_CFG1 (1: FP ethernet present) | ||
| 107 | * 2: BRD_CFG2 (1: XMC IO present) | ||
| 108 | * 3: XMC root complex indicator | ||
| 109 | * 4: Flash boot device indicator | ||
| 110 | * 5: Flash write protect enable | ||
| 111 | * 6: PMC monarch indicator | ||
| 112 | * 7: PMC EREADY | ||
| 113 | */ | ||
| 114 | gpio1: gpio@18 { | ||
| 115 | compatible = "nxp,pca9556"; | ||
| 116 | reg = <0x18>; | ||
| 117 | #gpio-cells = <2>; | ||
| 118 | gpio-controller; | ||
| 119 | polarity = <0x00>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | /* P14 GPIO */ | ||
| 123 | gpio2: gpio@19 { | ||
| 124 | compatible = "nxp,pca9556"; | ||
| 125 | reg = <0x19>; | ||
| 126 | #gpio-cells = <2>; | ||
| 127 | gpio-controller; | ||
| 128 | polarity = <0x00>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | eeprom@50 { | ||
| 132 | compatible = "atmel,at24c16"; | ||
| 133 | reg = <0x50>; | ||
| 134 | }; | ||
| 135 | |||
| 136 | rtc@68 { | ||
| 137 | compatible = "stm,m41t00", | ||
| 138 | "dallas,ds1338"; | ||
| 139 | reg = <0x68>; | ||
| 140 | }; | ||
| 141 | |||
| 142 | dtt@48 { | ||
| 143 | compatible = "maxim,max1237"; | ||
| 144 | reg = <0x34>; | ||
| 145 | }; | ||
| 146 | }; | ||
| 147 | |||
| 148 | /* Off-card I2C */ | ||
| 149 | i2c@3100 { | ||
| 150 | #address-cells = <1>; | ||
| 151 | #size-cells = <0>; | ||
| 152 | cell-index = <1>; | ||
| 153 | compatible = "fsl-i2c"; | ||
| 154 | reg = <0x3100 0x100>; | ||
| 155 | interrupts = <43 2>; | ||
| 156 | interrupt-parent = <&mpic>; | ||
| 157 | dfsrr; | ||
| 158 | }; | ||
| 159 | |||
| 160 | dma@21300 { | ||
| 161 | #address-cells = <1>; | ||
| 162 | #size-cells = <1>; | ||
| 163 | compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; | ||
| 164 | reg = <0x21300 0x4>; | ||
| 165 | ranges = <0x0 0x21100 0x200>; | ||
| 166 | cell-index = <0>; | ||
| 167 | dma-channel@0 { | ||
| 168 | compatible = "fsl,mpc8548-dma-channel", | ||
| 169 | "fsl,eloplus-dma-channel"; | ||
| 170 | reg = <0x0 0x80>; | ||
| 171 | cell-index = <0>; | ||
| 172 | interrupt-parent = <&mpic>; | ||
| 173 | interrupts = <20 2>; | ||
| 174 | }; | ||
| 175 | dma-channel@80 { | ||
| 176 | compatible = "fsl,mpc8548-dma-channel", | ||
| 177 | "fsl,eloplus-dma-channel"; | ||
| 178 | reg = <0x80 0x80>; | ||
| 179 | cell-index = <1>; | ||
| 180 | interrupt-parent = <&mpic>; | ||
| 181 | interrupts = <21 2>; | ||
| 182 | }; | ||
| 183 | dma-channel@100 { | ||
| 184 | compatible = "fsl,mpc8548-dma-channel", | ||
| 185 | "fsl,eloplus-dma-channel"; | ||
| 186 | reg = <0x100 0x80>; | ||
| 187 | cell-index = <2>; | ||
| 188 | interrupt-parent = <&mpic>; | ||
| 189 | interrupts = <22 2>; | ||
| 190 | }; | ||
| 191 | dma-channel@180 { | ||
| 192 | compatible = "fsl,mpc8548-dma-channel", | ||
| 193 | "fsl,eloplus-dma-channel"; | ||
| 194 | reg = <0x180 0x80>; | ||
| 195 | cell-index = <3>; | ||
| 196 | interrupt-parent = <&mpic>; | ||
| 197 | interrupts = <23 2>; | ||
| 198 | }; | ||
| 199 | }; | ||
| 200 | |||
| 201 | /* eTSEC1: Front panel port 0 */ | ||
| 202 | enet0: ethernet@24000 { | ||
| 203 | #address-cells = <1>; | ||
| 204 | #size-cells = <1>; | ||
| 205 | cell-index = <0>; | ||
| 206 | device_type = "network"; | ||
| 207 | model = "eTSEC"; | ||
| 208 | compatible = "gianfar"; | ||
| 209 | reg = <0x24000 0x1000>; | ||
| 210 | ranges = <0x0 0x24000 0x1000>; | ||
| 211 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 212 | interrupts = <29 2 30 2 34 2>; | ||
| 213 | interrupt-parent = <&mpic>; | ||
| 214 | tbi-handle = <&tbi0>; | ||
| 215 | phy-handle = <&phy0>; | ||
| 216 | |||
| 217 | mdio@520 { | ||
| 218 | #address-cells = <1>; | ||
| 219 | #size-cells = <0>; | ||
| 220 | compatible = "fsl,gianfar-mdio"; | ||
| 221 | reg = <0x520 0x20>; | ||
| 222 | |||
| 223 | phy0: ethernet-phy@1 { | ||
| 224 | interrupt-parent = <&mpic>; | ||
| 225 | interrupts = <8 1>; | ||
| 226 | reg = <0x1>; | ||
| 227 | }; | ||
| 228 | phy1: ethernet-phy@2 { | ||
| 229 | interrupt-parent = <&mpic>; | ||
| 230 | interrupts = <8 1>; | ||
| 231 | reg = <0x2>; | ||
| 232 | }; | ||
| 233 | phy2: ethernet-phy@3 { | ||
| 234 | interrupt-parent = <&mpic>; | ||
| 235 | interrupts = <8 1>; | ||
| 236 | reg = <0x3>; | ||
| 237 | }; | ||
| 238 | phy3: ethernet-phy@4 { | ||
| 239 | interrupt-parent = <&mpic>; | ||
| 240 | interrupts = <8 1>; | ||
| 241 | reg = <0x4>; | ||
| 242 | }; | ||
| 243 | tbi0: tbi-phy@11 { | ||
| 244 | reg = <0x11>; | ||
| 245 | device_type = "tbi-phy"; | ||
| 246 | }; | ||
| 247 | }; | ||
| 248 | }; | ||
| 249 | |||
| 250 | /* eTSEC2: Front panel port 1 */ | ||
| 251 | enet1: ethernet@25000 { | ||
| 252 | #address-cells = <1>; | ||
| 253 | #size-cells = <1>; | ||
| 254 | cell-index = <1>; | ||
| 255 | device_type = "network"; | ||
| 256 | model = "eTSEC"; | ||
| 257 | compatible = "gianfar"; | ||
| 258 | reg = <0x25000 0x1000>; | ||
| 259 | ranges = <0x0 0x25000 0x1000>; | ||
| 260 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 261 | interrupts = <35 2 36 2 40 2>; | ||
| 262 | interrupt-parent = <&mpic>; | ||
| 263 | tbi-handle = <&tbi1>; | ||
| 264 | phy-handle = <&phy1>; | ||
| 265 | |||
| 266 | mdio@520 { | ||
| 267 | #address-cells = <1>; | ||
| 268 | #size-cells = <0>; | ||
| 269 | compatible = "fsl,gianfar-tbi"; | ||
| 270 | reg = <0x520 0x20>; | ||
| 271 | |||
| 272 | tbi1: tbi-phy@11 { | ||
| 273 | reg = <0x11>; | ||
| 274 | device_type = "tbi-phy"; | ||
| 275 | }; | ||
| 276 | }; | ||
| 277 | }; | ||
| 278 | |||
| 279 | /* eTSEC3: Rear panel port 2 */ | ||
| 280 | enet2: ethernet@26000 { | ||
| 281 | #address-cells = <1>; | ||
| 282 | #size-cells = <1>; | ||
| 283 | cell-index = <2>; | ||
| 284 | device_type = "network"; | ||
| 285 | model = "eTSEC"; | ||
| 286 | compatible = "gianfar"; | ||
| 287 | reg = <0x26000 0x1000>; | ||
| 288 | ranges = <0x0 0x26000 0x1000>; | ||
| 289 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 290 | interrupts = <31 2 32 2 33 2>; | ||
| 291 | interrupt-parent = <&mpic>; | ||
| 292 | tbi-handle = <&tbi2>; | ||
| 293 | phy-handle = <&phy2>; | ||
| 294 | |||
| 295 | mdio@520 { | ||
| 296 | #address-cells = <1>; | ||
| 297 | #size-cells = <0>; | ||
| 298 | compatible = "fsl,gianfar-tbi"; | ||
| 299 | reg = <0x520 0x20>; | ||
| 300 | |||
| 301 | tbi2: tbi-phy@11 { | ||
| 302 | reg = <0x11>; | ||
| 303 | device_type = "tbi-phy"; | ||
| 304 | }; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | |||
| 308 | /* eTSEC4: Rear panel port 3 */ | ||
| 309 | enet3: ethernet@27000 { | ||
| 310 | #address-cells = <1>; | ||
| 311 | #size-cells = <1>; | ||
| 312 | cell-index = <3>; | ||
| 313 | device_type = "network"; | ||
| 314 | model = "eTSEC"; | ||
| 315 | compatible = "gianfar"; | ||
| 316 | reg = <0x27000 0x1000>; | ||
| 317 | ranges = <0x0 0x27000 0x1000>; | ||
| 318 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 319 | interrupts = <37 2 38 2 39 2>; | ||
| 320 | interrupt-parent = <&mpic>; | ||
| 321 | tbi-handle = <&tbi3>; | ||
| 322 | phy-handle = <&phy3>; | ||
| 323 | |||
| 324 | mdio@520 { | ||
| 325 | #address-cells = <1>; | ||
| 326 | #size-cells = <0>; | ||
| 327 | compatible = "fsl,gianfar-tbi"; | ||
| 328 | reg = <0x520 0x20>; | ||
| 329 | |||
| 330 | tbi3: tbi-phy@11 { | ||
| 331 | reg = <0x11>; | ||
| 332 | device_type = "tbi-phy"; | ||
| 333 | }; | ||
| 334 | }; | ||
| 335 | }; | ||
| 336 | |||
| 337 | serial0: serial@4500 { | ||
| 338 | cell-index = <0>; | ||
| 339 | device_type = "serial"; | ||
| 340 | compatible = "ns16550"; | ||
| 341 | reg = <0x4500 0x100>; | ||
| 342 | clock-frequency = <0>; | ||
| 343 | current-speed = <9600>; | ||
| 344 | interrupts = <42 2>; | ||
| 345 | interrupt-parent = <&mpic>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | serial1: serial@4600 { | ||
| 349 | cell-index = <1>; | ||
| 350 | device_type = "serial"; | ||
| 351 | compatible = "ns16550"; | ||
| 352 | reg = <0x4600 0x100>; | ||
| 353 | clock-frequency = <0>; | ||
| 354 | current-speed = <9600>; | ||
| 355 | interrupts = <42 2>; | ||
| 356 | interrupt-parent = <&mpic>; | ||
| 357 | }; | ||
| 358 | |||
| 359 | global-utilities@e0000 { // global utilities reg | ||
| 360 | compatible = "fsl,mpc8548-guts"; | ||
| 361 | reg = <0xe0000 0x1000>; | ||
| 362 | fsl,has-rstcr; | ||
| 363 | }; | ||
| 364 | |||
| 365 | mpic: pic@40000 { | ||
| 366 | interrupt-controller; | ||
| 367 | #address-cells = <0>; | ||
| 368 | #interrupt-cells = <2>; | ||
| 369 | reg = <0x40000 0x40000>; | ||
| 370 | compatible = "chrp,open-pic"; | ||
| 371 | device_type = "open-pic"; | ||
| 372 | }; | ||
| 373 | }; | ||
| 374 | |||
| 375 | localbus@ef005000 { | ||
| 376 | compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", | ||
| 377 | "simple-bus"; | ||
| 378 | #address-cells = <2>; | ||
| 379 | #size-cells = <1>; | ||
| 380 | reg = <0xef005000 0x100>; // BRx, ORx, etc. | ||
| 381 | |||
| 382 | ranges = < | ||
| 383 | 0 0x0 0xf8000000 0x08000000 // NOR boot flash | ||
| 384 | 1 0x0 0xf0000000 0x08000000 // NOR expansion flash | ||
| 385 | 2 0x0 0xe8000000 0x00010000 // NAND CE1 | ||
| 386 | 3 0x0 0xe8010000 0x00010000 // NAND CE2 | ||
| 387 | >; | ||
| 388 | |||
| 389 | nor-boot@0,0 { | ||
| 390 | #address-cells = <1>; | ||
| 391 | #size-cells = <1>; | ||
| 392 | compatible = "cfi-flash"; | ||
| 393 | reg = <0 0x0 0x4000000>; | ||
| 394 | bank-width = <2>; | ||
| 395 | |||
| 396 | partition@0 { | ||
| 397 | label = "Primary OS"; | ||
| 398 | reg = <0x00000000 0x180000>; | ||
| 399 | }; | ||
| 400 | partition@180000 { | ||
| 401 | label = "Secondary OS"; | ||
| 402 | reg = <0x00180000 0x180000>; | ||
| 403 | }; | ||
| 404 | partition@300000 { | ||
| 405 | label = "User"; | ||
| 406 | reg = <0x00300000 0x3c80000>; | ||
| 407 | }; | ||
| 408 | partition@3f80000 { | ||
| 409 | label = "Boot firmware"; | ||
| 410 | reg = <0x03f80000 0x80000>; | ||
| 411 | }; | ||
| 412 | }; | ||
| 413 | |||
| 414 | nor-alternate@1,0 { | ||
| 415 | #address-cells = <1>; | ||
| 416 | #size-cells = <1>; | ||
| 417 | compatible = "cfi-flash"; | ||
| 418 | reg = <1 0x0 0x4000000>; | ||
| 419 | bank-width = <2>; | ||
| 420 | |||
| 421 | partition@0 { | ||
| 422 | label = "Filesystem"; | ||
| 423 | reg = <0x00000000 0x3f80000>; | ||
| 424 | }; | ||
| 425 | partition@3f80000 { | ||
| 426 | label = "Alternate boot firmware"; | ||
| 427 | reg = <0x03f80000 0x80000>; | ||
| 428 | }; | ||
| 429 | }; | ||
| 430 | |||
| 431 | nand@2,0 { | ||
| 432 | #address-cells = <1>; | ||
| 433 | #size-cells = <1>; | ||
| 434 | compatible = "xes,address-ctl-nand"; | ||
| 435 | reg = <2 0x0 0x10000>; | ||
| 436 | cle-line = <0x8>; /* CLE tied to A3 */ | ||
| 437 | ale-line = <0x10>; /* ALE tied to A4 */ | ||
| 438 | |||
| 439 | partition@0 { | ||
| 440 | label = "NAND Filesystem"; | ||
| 441 | reg = <0 0x40000000>; | ||
| 442 | }; | ||
| 443 | }; | ||
| 444 | }; | ||
| 445 | |||
| 446 | /* PMC interface */ | ||
| 447 | pci0: pci@ef008000 { | ||
| 448 | #interrupt-cells = <1>; | ||
| 449 | #size-cells = <2>; | ||
| 450 | #address-cells = <3>; | ||
| 451 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | ||
| 452 | device_type = "pci"; | ||
| 453 | reg = <0xef008000 0x1000>; | ||
| 454 | clock-frequency = <33333333>; | ||
| 455 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 456 | interrupt-map = < | ||
| 457 | /* IDSEL */ | ||
| 458 | 0xe000 0 0 1 &mpic 2 1 | ||
| 459 | 0xe000 0 0 2 &mpic 3 1>; | ||
| 460 | |||
| 461 | interrupt-parent = <&mpic>; | ||
| 462 | interrupts = <24 2>; | ||
| 463 | bus-range = <0 0>; | ||
| 464 | ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 | ||
| 465 | 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; | ||
| 466 | }; | ||
| 467 | |||
| 468 | /* XMC PCIe */ | ||
| 469 | pci1: pcie@ef00a000 { | ||
| 470 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 471 | interrupt-map = < | ||
| 472 | /* IDSEL 0x0 */ | ||
| 473 | 0x00000 0 0 1 &mpic 0 1 | ||
| 474 | 0x00000 0 0 2 &mpic 1 1 | ||
| 475 | 0x00000 0 0 3 &mpic 2 1 | ||
| 476 | 0x00000 0 0 4 &mpic 3 1>; | ||
| 477 | |||
| 478 | interrupt-parent = <&mpic>; | ||
| 479 | interrupts = <26 2>; | ||
| 480 | bus-range = <0 0xff>; | ||
| 481 | ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 | ||
| 482 | 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; | ||
| 483 | clock-frequency = <33333333>; | ||
| 484 | #interrupt-cells = <1>; | ||
| 485 | #size-cells = <2>; | ||
| 486 | #address-cells = <3>; | ||
| 487 | reg = <0xef00a000 0x1000>; | ||
| 488 | compatible = "fsl,mpc8548-pcie"; | ||
| 489 | device_type = "pci"; | ||
| 490 | pcie@0 { | ||
| 491 | reg = <0 0 0 0 0>; | ||
| 492 | #size-cells = <2>; | ||
| 493 | #address-cells = <3>; | ||
| 494 | device_type = "pci"; | ||
| 495 | ranges = <0x02000000 0 0xc0000000 0x02000000 0 | ||
| 496 | 0xc0000000 0 0x20000000 | ||
| 497 | 0x01000000 0 0x00000000 0x01000000 0 | ||
| 498 | 0x00000000 0 0x08000000>; | ||
| 499 | }; | ||
| 500 | }; | ||
| 501 | |||
| 502 | /* Needed for dtbImage boot wrapper compatibility */ | ||
| 503 | chosen { | ||
| 504 | linux,stdout-path = &serial0; | ||
| 505 | }; | ||
| 506 | }; | ||
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts new file mode 100644 index 000000000000..db7faf5ebb39 --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5301.dts | |||
| @@ -0,0 +1,640 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * XPedite5301 PMC/XMC module based on MPC8572E | ||
| 6 | * | ||
| 7 | * This is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | model = "xes,xpedite5301"; | ||
| 15 | compatible = "xes,xpedite5301", "xes,MPC8572"; | ||
| 16 | #address-cells = <2>; | ||
| 17 | #size-cells = <2>; | ||
| 18 | form-factor = "PMC/XMC"; | ||
| 19 | boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ | ||
| 20 | |||
| 21 | aliases { | ||
| 22 | ethernet0 = &enet0; | ||
| 23 | ethernet1 = &enet1; | ||
| 24 | serial0 = &serial0; | ||
| 25 | serial1 = &serial1; | ||
| 26 | pci1 = &pci1; | ||
| 27 | pci2 = &pci2; | ||
| 28 | }; | ||
| 29 | |||
| 30 | cpus { | ||
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <0>; | ||
| 33 | |||
| 34 | PowerPC,8572@0 { | ||
| 35 | device_type = "cpu"; | ||
| 36 | reg = <0x0>; | ||
| 37 | d-cache-line-size = <32>; // 32 bytes | ||
| 38 | i-cache-line-size = <32>; // 32 bytes | ||
| 39 | d-cache-size = <0x8000>; // L1, 32K | ||
| 40 | i-cache-size = <0x8000>; // L1, 32K | ||
| 41 | timebase-frequency = <0>; | ||
| 42 | bus-frequency = <0>; | ||
| 43 | clock-frequency = <0>; | ||
| 44 | next-level-cache = <&L2>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | PowerPC,8572@1 { | ||
| 48 | device_type = "cpu"; | ||
| 49 | reg = <0x1>; | ||
| 50 | d-cache-line-size = <32>; // 32 bytes | ||
| 51 | i-cache-line-size = <32>; // 32 bytes | ||
| 52 | d-cache-size = <0x8000>; // L1, 32K | ||
| 53 | i-cache-size = <0x8000>; // L1, 32K | ||
| 54 | timebase-frequency = <0>; | ||
| 55 | bus-frequency = <0>; | ||
| 56 | clock-frequency = <0>; | ||
| 57 | next-level-cache = <&L2>; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | memory { | ||
| 62 | device_type = "memory"; | ||
| 63 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | ||
| 64 | }; | ||
| 65 | |||
| 66 | localbus@ef005000 { | ||
| 67 | #address-cells = <2>; | ||
| 68 | #size-cells = <1>; | ||
| 69 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | ||
| 70 | reg = <0 0xef005000 0 0x1000>; | ||
| 71 | interrupts = <19 2>; | ||
| 72 | interrupt-parent = <&mpic>; | ||
| 73 | /* Local bus region mappings */ | ||
| 74 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ | ||
| 75 | 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ | ||
| 76 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | ||
| 77 | 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ | ||
| 78 | |||
| 79 | nor-boot@0,0 { | ||
| 80 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 81 | bank-width = <2>; | ||
| 82 | reg = <0 0 0x8000000>; /* 128MB */ | ||
| 83 | #address-cells = <1>; | ||
| 84 | #size-cells = <1>; | ||
| 85 | partition@0 { | ||
| 86 | label = "Primary user space"; | ||
| 87 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 88 | }; | ||
| 89 | partition@6f00000 { | ||
| 90 | label = "Primary kernel"; | ||
| 91 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 92 | }; | ||
| 93 | partition@7f00000 { | ||
| 94 | label = "Primary DTB"; | ||
| 95 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 96 | }; | ||
| 97 | partition@7f40000 { | ||
| 98 | label = "Primary U-Boot environment"; | ||
| 99 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 100 | }; | ||
| 101 | partition@7f80000 { | ||
| 102 | label = "Primary U-Boot"; | ||
| 103 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 104 | read-only; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | |||
| 108 | nor-alternate@1,0 { | ||
| 109 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 110 | bank-width = <2>; | ||
| 111 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | ||
| 112 | reg = <1 0 0x8000000>; /* 128MB */ | ||
| 113 | #address-cells = <1>; | ||
| 114 | #size-cells = <1>; | ||
| 115 | partition@0 { | ||
| 116 | label = "Secondary user space"; | ||
| 117 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 118 | }; | ||
| 119 | partition@6f00000 { | ||
| 120 | label = "Secondary kernel"; | ||
| 121 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 122 | }; | ||
| 123 | partition@7f00000 { | ||
| 124 | label = "Secondary DTB"; | ||
| 125 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 126 | }; | ||
| 127 | partition@7f40000 { | ||
| 128 | label = "Secondary U-Boot environment"; | ||
| 129 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 130 | }; | ||
| 131 | partition@7f80000 { | ||
| 132 | label = "Secondary U-Boot"; | ||
| 133 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 134 | read-only; | ||
| 135 | }; | ||
| 136 | }; | ||
| 137 | |||
| 138 | nand@2,0 { | ||
| 139 | #address-cells = <1>; | ||
| 140 | #size-cells = <1>; | ||
| 141 | /* | ||
| 142 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | ||
| 143 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | ||
| 144 | * MT29F16G08FAA (2x 1 GB), depending on the build | ||
| 145 | * configuration | ||
| 146 | */ | ||
| 147 | compatible = "fsl,mpc8572-fcm-nand", | ||
| 148 | "fsl,elbc-fcm-nand"; | ||
| 149 | reg = <2 0 0x40000>; | ||
| 150 | /* U-Boot should fix this up if chip size > 1 GB */ | ||
| 151 | partition@0 { | ||
| 152 | label = "NAND Filesystem"; | ||
| 153 | reg = <0 0x40000000>; | ||
| 154 | }; | ||
| 155 | }; | ||
| 156 | |||
| 157 | }; | ||
| 158 | |||
| 159 | soc8572@ef000000 { | ||
| 160 | #address-cells = <1>; | ||
| 161 | #size-cells = <1>; | ||
| 162 | device_type = "soc"; | ||
| 163 | compatible = "fsl,mpc8572-immr", "simple-bus"; | ||
| 164 | ranges = <0x0 0 0xef000000 0x100000>; | ||
| 165 | bus-frequency = <0>; // Filled out by uboot. | ||
| 166 | |||
| 167 | ecm-law@0 { | ||
| 168 | compatible = "fsl,ecm-law"; | ||
| 169 | reg = <0x0 0x1000>; | ||
| 170 | fsl,num-laws = <12>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | ecm@1000 { | ||
| 174 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 175 | reg = <0x1000 0x1000>; | ||
| 176 | interrupts = <17 2>; | ||
| 177 | interrupt-parent = <&mpic>; | ||
| 178 | }; | ||
| 179 | |||
| 180 | memory-controller@2000 { | ||
| 181 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 182 | reg = <0x2000 0x1000>; | ||
| 183 | interrupt-parent = <&mpic>; | ||
| 184 | interrupts = <18 2>; | ||
| 185 | }; | ||
| 186 | |||
| 187 | memory-controller@6000 { | ||
| 188 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 189 | reg = <0x6000 0x1000>; | ||
| 190 | interrupt-parent = <&mpic>; | ||
| 191 | interrupts = <18 2>; | ||
| 192 | }; | ||
| 193 | |||
| 194 | L2: l2-cache-controller@20000 { | ||
| 195 | compatible = "fsl,mpc8572-l2-cache-controller"; | ||
| 196 | reg = <0x20000 0x1000>; | ||
| 197 | cache-line-size = <32>; // 32 bytes | ||
| 198 | cache-size = <0x100000>; // L2, 1M | ||
| 199 | interrupt-parent = <&mpic>; | ||
| 200 | interrupts = <16 2>; | ||
| 201 | }; | ||
| 202 | |||
| 203 | i2c@3000 { | ||
| 204 | #address-cells = <1>; | ||
| 205 | #size-cells = <0>; | ||
| 206 | cell-index = <0>; | ||
| 207 | compatible = "fsl-i2c"; | ||
| 208 | reg = <0x3000 0x100>; | ||
| 209 | interrupts = <43 2>; | ||
| 210 | interrupt-parent = <&mpic>; | ||
| 211 | dfsrr; | ||
| 212 | |||
| 213 | temp-sensor@48 { | ||
| 214 | compatible = "dallas,ds1631", "dallas,ds1621"; | ||
| 215 | reg = <0x48>; | ||
| 216 | }; | ||
| 217 | |||
| 218 | temp-sensor@4c { | ||
| 219 | compatible = "adi,adt7461"; | ||
| 220 | reg = <0x4c>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | cpu-supervisor@51 { | ||
| 224 | compatible = "dallas,ds4510"; | ||
| 225 | reg = <0x51>; | ||
| 226 | }; | ||
| 227 | |||
| 228 | eeprom@54 { | ||
| 229 | compatible = "atmel,at24c128b"; | ||
| 230 | reg = <0x54>; | ||
| 231 | }; | ||
| 232 | |||
| 233 | rtc@68 { | ||
| 234 | compatible = "stm,m41t00", | ||
| 235 | "dallas,ds1338"; | ||
| 236 | reg = <0x68>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | pcie-switch@70 { | ||
| 240 | compatible = "plx,pex8518"; | ||
| 241 | reg = <0x70>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | gpio1: gpio@18 { | ||
| 245 | compatible = "nxp,pca9557"; | ||
| 246 | reg = <0x18>; | ||
| 247 | #gpio-cells = <2>; | ||
| 248 | gpio-controller; | ||
| 249 | polarity = <0x00>; | ||
| 250 | }; | ||
| 251 | |||
| 252 | gpio2: gpio@1c { | ||
| 253 | compatible = "nxp,pca9557"; | ||
| 254 | reg = <0x1c>; | ||
| 255 | #gpio-cells = <2>; | ||
| 256 | gpio-controller; | ||
| 257 | polarity = <0x00>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | gpio3: gpio@1e { | ||
| 261 | compatible = "nxp,pca9557"; | ||
| 262 | reg = <0x1e>; | ||
| 263 | #gpio-cells = <2>; | ||
| 264 | gpio-controller; | ||
| 265 | polarity = <0x00>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | gpio4: gpio@1f { | ||
| 269 | compatible = "nxp,pca9557"; | ||
| 270 | reg = <0x1f>; | ||
| 271 | #gpio-cells = <2>; | ||
| 272 | gpio-controller; | ||
| 273 | polarity = <0x00>; | ||
| 274 | }; | ||
| 275 | }; | ||
| 276 | |||
| 277 | i2c@3100 { | ||
| 278 | #address-cells = <1>; | ||
| 279 | #size-cells = <0>; | ||
| 280 | cell-index = <1>; | ||
| 281 | compatible = "fsl-i2c"; | ||
| 282 | reg = <0x3100 0x100>; | ||
| 283 | interrupts = <43 2>; | ||
| 284 | interrupt-parent = <&mpic>; | ||
| 285 | dfsrr; | ||
| 286 | }; | ||
| 287 | |||
| 288 | dma@c300 { | ||
| 289 | #address-cells = <1>; | ||
| 290 | #size-cells = <1>; | ||
| 291 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 292 | reg = <0xc300 0x4>; | ||
| 293 | ranges = <0x0 0xc100 0x200>; | ||
| 294 | cell-index = <1>; | ||
| 295 | dma-channel@0 { | ||
| 296 | compatible = "fsl,mpc8572-dma-channel", | ||
| 297 | "fsl,eloplus-dma-channel"; | ||
| 298 | reg = <0x0 0x80>; | ||
| 299 | cell-index = <0>; | ||
| 300 | interrupt-parent = <&mpic>; | ||
| 301 | interrupts = <76 2>; | ||
| 302 | }; | ||
| 303 | dma-channel@80 { | ||
| 304 | compatible = "fsl,mpc8572-dma-channel", | ||
| 305 | "fsl,eloplus-dma-channel"; | ||
| 306 | reg = <0x80 0x80>; | ||
| 307 | cell-index = <1>; | ||
| 308 | interrupt-parent = <&mpic>; | ||
| 309 | interrupts = <77 2>; | ||
| 310 | }; | ||
| 311 | dma-channel@100 { | ||
| 312 | compatible = "fsl,mpc8572-dma-channel", | ||
| 313 | "fsl,eloplus-dma-channel"; | ||
| 314 | reg = <0x100 0x80>; | ||
| 315 | cell-index = <2>; | ||
| 316 | interrupt-parent = <&mpic>; | ||
| 317 | interrupts = <78 2>; | ||
| 318 | }; | ||
| 319 | dma-channel@180 { | ||
| 320 | compatible = "fsl,mpc8572-dma-channel", | ||
| 321 | "fsl,eloplus-dma-channel"; | ||
| 322 | reg = <0x180 0x80>; | ||
| 323 | cell-index = <3>; | ||
| 324 | interrupt-parent = <&mpic>; | ||
| 325 | interrupts = <79 2>; | ||
| 326 | }; | ||
| 327 | }; | ||
| 328 | |||
| 329 | dma@21300 { | ||
| 330 | #address-cells = <1>; | ||
| 331 | #size-cells = <1>; | ||
| 332 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 333 | reg = <0x21300 0x4>; | ||
| 334 | ranges = <0x0 0x21100 0x200>; | ||
| 335 | cell-index = <0>; | ||
| 336 | dma-channel@0 { | ||
| 337 | compatible = "fsl,mpc8572-dma-channel", | ||
| 338 | "fsl,eloplus-dma-channel"; | ||
| 339 | reg = <0x0 0x80>; | ||
| 340 | cell-index = <0>; | ||
| 341 | interrupt-parent = <&mpic>; | ||
| 342 | interrupts = <20 2>; | ||
| 343 | }; | ||
| 344 | dma-channel@80 { | ||
| 345 | compatible = "fsl,mpc8572-dma-channel", | ||
| 346 | "fsl,eloplus-dma-channel"; | ||
| 347 | reg = <0x80 0x80>; | ||
| 348 | cell-index = <1>; | ||
| 349 | interrupt-parent = <&mpic>; | ||
| 350 | interrupts = <21 2>; | ||
| 351 | }; | ||
| 352 | dma-channel@100 { | ||
| 353 | compatible = "fsl,mpc8572-dma-channel", | ||
| 354 | "fsl,eloplus-dma-channel"; | ||
| 355 | reg = <0x100 0x80>; | ||
| 356 | cell-index = <2>; | ||
| 357 | interrupt-parent = <&mpic>; | ||
| 358 | interrupts = <22 2>; | ||
| 359 | }; | ||
| 360 | dma-channel@180 { | ||
| 361 | compatible = "fsl,mpc8572-dma-channel", | ||
| 362 | "fsl,eloplus-dma-channel"; | ||
| 363 | reg = <0x180 0x80>; | ||
| 364 | cell-index = <3>; | ||
| 365 | interrupt-parent = <&mpic>; | ||
| 366 | interrupts = <23 2>; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 370 | /* eTSEC 1 */ | ||
| 371 | enet0: ethernet@24000 { | ||
| 372 | #address-cells = <1>; | ||
| 373 | #size-cells = <1>; | ||
| 374 | cell-index = <0>; | ||
| 375 | device_type = "network"; | ||
| 376 | model = "eTSEC"; | ||
| 377 | compatible = "gianfar"; | ||
| 378 | reg = <0x24000 0x1000>; | ||
| 379 | ranges = <0x0 0x24000 0x1000>; | ||
| 380 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 381 | interrupts = <29 2 30 2 34 2>; | ||
| 382 | interrupt-parent = <&mpic>; | ||
| 383 | tbi-handle = <&tbi0>; | ||
| 384 | phy-handle = <&phy0>; | ||
| 385 | phy-connection-type = "sgmii"; | ||
| 386 | |||
| 387 | mdio@520 { | ||
| 388 | #address-cells = <1>; | ||
| 389 | #size-cells = <0>; | ||
| 390 | compatible = "fsl,gianfar-mdio"; | ||
| 391 | reg = <0x520 0x20>; | ||
| 392 | |||
| 393 | phy0: ethernet-phy@1 { | ||
| 394 | interrupt-parent = <&mpic>; | ||
| 395 | interrupts = <8 1>; | ||
| 396 | reg = <0x1>; | ||
| 397 | }; | ||
| 398 | phy1: ethernet-phy@2 { | ||
| 399 | interrupt-parent = <&mpic>; | ||
| 400 | interrupts = <8 1>; | ||
| 401 | reg = <0x2>; | ||
| 402 | }; | ||
| 403 | tbi0: tbi-phy@11 { | ||
| 404 | reg = <0x11>; | ||
| 405 | device_type = "tbi-phy"; | ||
| 406 | }; | ||
| 407 | }; | ||
| 408 | }; | ||
| 409 | |||
| 410 | /* eTSEC 2 */ | ||
| 411 | enet1: ethernet@25000 { | ||
| 412 | #address-cells = <1>; | ||
| 413 | #size-cells = <1>; | ||
| 414 | cell-index = <1>; | ||
| 415 | device_type = "network"; | ||
| 416 | model = "eTSEC"; | ||
| 417 | compatible = "gianfar"; | ||
| 418 | reg = <0x25000 0x1000>; | ||
| 419 | ranges = <0x0 0x25000 0x1000>; | ||
| 420 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 421 | interrupts = <35 2 36 2 40 2>; | ||
| 422 | interrupt-parent = <&mpic>; | ||
| 423 | tbi-handle = <&tbi1>; | ||
| 424 | phy-handle = <&phy1>; | ||
| 425 | phy-connection-type = "sgmii"; | ||
| 426 | |||
| 427 | mdio@520 { | ||
| 428 | #address-cells = <1>; | ||
| 429 | #size-cells = <0>; | ||
| 430 | compatible = "fsl,gianfar-tbi"; | ||
| 431 | reg = <0x520 0x20>; | ||
| 432 | |||
| 433 | tbi1: tbi-phy@11 { | ||
| 434 | reg = <0x11>; | ||
| 435 | device_type = "tbi-phy"; | ||
| 436 | }; | ||
| 437 | }; | ||
| 438 | }; | ||
| 439 | |||
| 440 | /* UART0 */ | ||
| 441 | serial0: serial@4500 { | ||
| 442 | cell-index = <0>; | ||
| 443 | device_type = "serial"; | ||
| 444 | compatible = "ns16550"; | ||
| 445 | reg = <0x4500 0x100>; | ||
| 446 | clock-frequency = <0>; | ||
| 447 | interrupts = <42 2>; | ||
| 448 | interrupt-parent = <&mpic>; | ||
| 449 | }; | ||
| 450 | |||
| 451 | /* UART1 */ | ||
| 452 | serial1: serial@4600 { | ||
| 453 | cell-index = <1>; | ||
| 454 | device_type = "serial"; | ||
| 455 | compatible = "ns16550"; | ||
| 456 | reg = <0x4600 0x100>; | ||
| 457 | clock-frequency = <0>; | ||
| 458 | interrupts = <42 2>; | ||
| 459 | interrupt-parent = <&mpic>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | global-utilities@e0000 { //global utilities block | ||
| 463 | compatible = "fsl,mpc8572-guts"; | ||
| 464 | reg = <0xe0000 0x1000>; | ||
| 465 | fsl,has-rstcr; | ||
| 466 | }; | ||
| 467 | |||
| 468 | msi@41600 { | ||
| 469 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | ||
| 470 | reg = <0x41600 0x80>; | ||
| 471 | msi-available-ranges = <0 0x100>; | ||
| 472 | interrupts = < | ||
| 473 | 0xe0 0 | ||
| 474 | 0xe1 0 | ||
| 475 | 0xe2 0 | ||
| 476 | 0xe3 0 | ||
| 477 | 0xe4 0 | ||
| 478 | 0xe5 0 | ||
| 479 | 0xe6 0 | ||
| 480 | 0xe7 0>; | ||
| 481 | interrupt-parent = <&mpic>; | ||
| 482 | }; | ||
| 483 | |||
| 484 | crypto@30000 { | ||
| 485 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | ||
| 486 | "fsl,sec2.1", "fsl,sec2.0"; | ||
| 487 | reg = <0x30000 0x10000>; | ||
| 488 | interrupts = <45 2 58 2>; | ||
| 489 | interrupt-parent = <&mpic>; | ||
| 490 | fsl,num-channels = <4>; | ||
| 491 | fsl,channel-fifo-len = <24>; | ||
| 492 | fsl,exec-units-mask = <0x9fe>; | ||
| 493 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 494 | }; | ||
| 495 | |||
| 496 | mpic: pic@40000 { | ||
| 497 | interrupt-controller; | ||
| 498 | #address-cells = <0>; | ||
| 499 | #interrupt-cells = <2>; | ||
| 500 | reg = <0x40000 0x40000>; | ||
| 501 | compatible = "chrp,open-pic"; | ||
| 502 | device_type = "open-pic"; | ||
| 503 | }; | ||
| 504 | |||
| 505 | gpio0: gpio@f000 { | ||
| 506 | compatible = "fsl,mpc8572-gpio"; | ||
| 507 | reg = <0xf000 0x1000>; | ||
| 508 | interrupts = <47 2>; | ||
| 509 | interrupt-parent = <&mpic>; | ||
| 510 | #gpio-cells = <2>; | ||
| 511 | gpio-controller; | ||
| 512 | }; | ||
| 513 | |||
| 514 | gpio-leds { | ||
| 515 | compatible = "gpio-leds"; | ||
| 516 | |||
| 517 | heartbeat { | ||
| 518 | label = "Heartbeat"; | ||
| 519 | gpios = <&gpio0 4 1>; | ||
| 520 | linux,default-trigger = "heartbeat"; | ||
| 521 | }; | ||
| 522 | |||
| 523 | yellow { | ||
| 524 | label = "Yellow"; | ||
| 525 | gpios = <&gpio0 5 1>; | ||
| 526 | }; | ||
| 527 | |||
| 528 | red { | ||
| 529 | label = "Red"; | ||
| 530 | gpios = <&gpio0 6 1>; | ||
| 531 | }; | ||
| 532 | |||
| 533 | green { | ||
| 534 | label = "Green"; | ||
| 535 | gpios = <&gpio0 7 1>; | ||
| 536 | }; | ||
| 537 | }; | ||
| 538 | |||
| 539 | /* PME (pattern-matcher) */ | ||
| 540 | pme@10000 { | ||
| 541 | compatible = "fsl,mpc8572-pme", "pme8572"; | ||
| 542 | reg = <0x10000 0x5000>; | ||
| 543 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | ||
| 544 | interrupt-parent = <&mpic>; | ||
| 545 | }; | ||
| 546 | |||
| 547 | tlu@2f000 { | ||
| 548 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 549 | reg = <0x2f000 0x1000>; | ||
| 550 | interupts = <61 2 >; | ||
| 551 | interrupt-parent = <&mpic>; | ||
| 552 | }; | ||
| 553 | |||
| 554 | tlu@15000 { | ||
| 555 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 556 | reg = <0x15000 0x1000>; | ||
| 557 | interupts = <75 2>; | ||
| 558 | interrupt-parent = <&mpic>; | ||
| 559 | }; | ||
| 560 | }; | ||
| 561 | |||
| 562 | /* | ||
| 563 | * PCI Express controller 3 @ ef008000 is not used. | ||
| 564 | * This would have been pci0 on other mpc85xx platforms. | ||
| 565 | */ | ||
| 566 | |||
| 567 | /* PCI Express controller 2, wired to XMC P15 connector */ | ||
| 568 | pci1: pcie@ef009000 { | ||
| 569 | compatible = "fsl,mpc8548-pcie"; | ||
| 570 | device_type = "pci"; | ||
| 571 | #interrupt-cells = <1>; | ||
| 572 | #size-cells = <2>; | ||
| 573 | #address-cells = <3>; | ||
| 574 | reg = <0 0xef009000 0 0x1000>; | ||
| 575 | bus-range = <0 255>; | ||
| 576 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 | ||
| 577 | 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; | ||
| 578 | clock-frequency = <33333333>; | ||
| 579 | interrupt-parent = <&mpic>; | ||
| 580 | interrupts = <25 2>; | ||
| 581 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 582 | interrupt-map = < | ||
| 583 | /* IDSEL 0x0 */ | ||
| 584 | 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 | ||
| 585 | 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 | ||
| 586 | 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 | ||
| 587 | 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 | ||
| 588 | >; | ||
| 589 | pcie@0 { | ||
| 590 | reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; | ||
| 591 | #size-cells = <2>; | ||
| 592 | #address-cells = <3>; | ||
| 593 | device_type = "pci"; | ||
| 594 | ranges = <0x2000000 0x0 0xc0000000 | ||
| 595 | 0x2000000 0x0 0xc0000000 | ||
| 596 | 0x0 0x10000000 | ||
| 597 | |||
| 598 | 0x1000000 0x0 0x0 | ||
| 599 | 0x1000000 0x0 0x0 | ||
| 600 | 0x0 0x100000>; | ||
| 601 | }; | ||
| 602 | }; | ||
| 603 | |||
| 604 | /* PCI Express controller 1, wired to PEX8112 for PMC interface */ | ||
| 605 | pci2: pcie@ef00a000 { | ||
| 606 | compatible = "fsl,mpc8548-pcie"; | ||
| 607 | device_type = "pci"; | ||
| 608 | #interrupt-cells = <1>; | ||
| 609 | #size-cells = <2>; | ||
| 610 | #address-cells = <3>; | ||
| 611 | reg = <0 0xef00a000 0 0x1000>; | ||
| 612 | bus-range = <0 255>; | ||
| 613 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | ||
| 614 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | ||
| 615 | clock-frequency = <33333333>; | ||
| 616 | interrupt-parent = <&mpic>; | ||
| 617 | interrupts = <26 2>; | ||
| 618 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 619 | interrupt-map = < | ||
| 620 | /* IDSEL 0x0 */ | ||
| 621 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 622 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 623 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 624 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 625 | >; | ||
| 626 | pcie@0 { | ||
| 627 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 628 | #size-cells = <2>; | ||
| 629 | #address-cells = <3>; | ||
| 630 | device_type = "pci"; | ||
| 631 | ranges = <0x2000000 0x0 0x80000000 | ||
| 632 | 0x2000000 0x0 0x80000000 | ||
| 633 | 0x0 0x40000000 | ||
| 634 | |||
| 635 | 0x1000000 0x0 0x0 | ||
| 636 | 0x1000000 0x0 0x0 | ||
| 637 | 0x0 0x100000>; | ||
| 638 | }; | ||
| 639 | }; | ||
| 640 | }; | ||
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts new file mode 100644 index 000000000000..c364ca6ff7d0 --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5330.dts | |||
| @@ -0,0 +1,707 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * XPedite5330 3U CompactPCI module based on MPC8572E | ||
| 6 | * | ||
| 7 | * This is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | model = "xes,xpedite5330"; | ||
| 15 | compatible = "xes,xpedite5330", "xes,MPC8572"; | ||
| 16 | #address-cells = <2>; | ||
| 17 | #size-cells = <2>; | ||
| 18 | form-factor = "3U CompactPCI"; | ||
| 19 | boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ | ||
| 20 | |||
| 21 | aliases { | ||
| 22 | ethernet0 = &enet0; | ||
| 23 | ethernet1 = &enet1; | ||
| 24 | serial0 = &serial0; | ||
| 25 | serial1 = &serial1; | ||
| 26 | pci0 = &pci0; | ||
| 27 | pci1 = &pci1; | ||
| 28 | pci2 = &pci2; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pmcslots { | ||
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | |||
| 35 | pmcslot@0 { | ||
| 36 | cell-index = <0>; | ||
| 37 | /* | ||
| 38 | * boolean properties (true if defined): | ||
| 39 | * monarch; | ||
| 40 | * module-present; | ||
| 41 | */ | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | xmcslots { | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | |||
| 49 | xmcslot@0 { | ||
| 50 | cell-index = <0>; | ||
| 51 | /* | ||
| 52 | * boolean properties (true if defined): | ||
| 53 | * module-present; | ||
| 54 | */ | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | |||
| 58 | cpci { | ||
| 59 | /* | ||
| 60 | * boolean properties (true if defined): | ||
| 61 | * system-controller; | ||
| 62 | */ | ||
| 63 | system-controller; | ||
| 64 | }; | ||
| 65 | |||
| 66 | cpus { | ||
| 67 | #address-cells = <1>; | ||
| 68 | #size-cells = <0>; | ||
| 69 | |||
| 70 | PowerPC,8572@0 { | ||
| 71 | device_type = "cpu"; | ||
| 72 | reg = <0x0>; | ||
| 73 | d-cache-line-size = <32>; // 32 bytes | ||
| 74 | i-cache-line-size = <32>; // 32 bytes | ||
| 75 | d-cache-size = <0x8000>; // L1, 32K | ||
| 76 | i-cache-size = <0x8000>; // L1, 32K | ||
| 77 | timebase-frequency = <0>; | ||
| 78 | bus-frequency = <0>; | ||
| 79 | clock-frequency = <0>; | ||
| 80 | next-level-cache = <&L2>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | PowerPC,8572@1 { | ||
| 84 | device_type = "cpu"; | ||
| 85 | reg = <0x1>; | ||
| 86 | d-cache-line-size = <32>; // 32 bytes | ||
| 87 | i-cache-line-size = <32>; // 32 bytes | ||
| 88 | d-cache-size = <0x8000>; // L1, 32K | ||
| 89 | i-cache-size = <0x8000>; // L1, 32K | ||
| 90 | timebase-frequency = <0>; | ||
| 91 | bus-frequency = <0>; | ||
| 92 | clock-frequency = <0>; | ||
| 93 | next-level-cache = <&L2>; | ||
| 94 | }; | ||
| 95 | }; | ||
| 96 | |||
| 97 | memory { | ||
| 98 | device_type = "memory"; | ||
| 99 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | ||
| 100 | }; | ||
| 101 | |||
| 102 | localbus@ef005000 { | ||
| 103 | #address-cells = <2>; | ||
| 104 | #size-cells = <1>; | ||
| 105 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | ||
| 106 | reg = <0 0xef005000 0 0x1000>; | ||
| 107 | interrupts = <19 2>; | ||
| 108 | interrupt-parent = <&mpic>; | ||
| 109 | /* Local bus region mappings */ | ||
| 110 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ | ||
| 111 | 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ | ||
| 112 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | ||
| 113 | 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ | ||
| 114 | |||
| 115 | nor-boot@0,0 { | ||
| 116 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 117 | bank-width = <2>; | ||
| 118 | reg = <0 0 0x8000000>; /* 128MB */ | ||
| 119 | #address-cells = <1>; | ||
| 120 | #size-cells = <1>; | ||
| 121 | partition@0 { | ||
| 122 | label = "Primary user space"; | ||
| 123 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 124 | }; | ||
| 125 | partition@6f00000 { | ||
| 126 | label = "Primary kernel"; | ||
| 127 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 128 | }; | ||
| 129 | partition@7f00000 { | ||
| 130 | label = "Primary DTB"; | ||
| 131 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 132 | }; | ||
| 133 | partition@7f40000 { | ||
| 134 | label = "Primary U-Boot environment"; | ||
| 135 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 136 | }; | ||
| 137 | partition@7f80000 { | ||
| 138 | label = "Primary U-Boot"; | ||
| 139 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 140 | read-only; | ||
| 141 | }; | ||
| 142 | }; | ||
| 143 | |||
| 144 | nor-alternate@1,0 { | ||
| 145 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 146 | bank-width = <2>; | ||
| 147 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | ||
| 148 | reg = <1 0 0x8000000>; /* 128MB */ | ||
| 149 | #address-cells = <1>; | ||
| 150 | #size-cells = <1>; | ||
| 151 | partition@0 { | ||
| 152 | label = "Secondary user space"; | ||
| 153 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 154 | }; | ||
| 155 | partition@6f00000 { | ||
| 156 | label = "Secondary kernel"; | ||
| 157 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 158 | }; | ||
| 159 | partition@7f00000 { | ||
| 160 | label = "Secondary DTB"; | ||
| 161 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 162 | }; | ||
| 163 | partition@7f40000 { | ||
| 164 | label = "Secondary U-Boot environment"; | ||
| 165 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 166 | }; | ||
| 167 | partition@7f80000 { | ||
| 168 | label = "Secondary U-Boot"; | ||
| 169 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 170 | read-only; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | |||
| 174 | nand@2,0 { | ||
| 175 | #address-cells = <1>; | ||
| 176 | #size-cells = <1>; | ||
| 177 | /* | ||
| 178 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | ||
| 179 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | ||
| 180 | * MT29F16G08FAA (2x 1 GB), depending on the build | ||
| 181 | * configuration | ||
| 182 | */ | ||
| 183 | compatible = "fsl,mpc8572-fcm-nand", | ||
| 184 | "fsl,elbc-fcm-nand"; | ||
| 185 | reg = <2 0 0x40000>; | ||
| 186 | /* U-Boot should fix this up if chip size > 1 GB */ | ||
| 187 | partition@0 { | ||
| 188 | label = "NAND Filesystem"; | ||
| 189 | reg = <0 0x40000000>; | ||
| 190 | }; | ||
| 191 | }; | ||
| 192 | |||
| 193 | }; | ||
| 194 | |||
| 195 | soc8572@ef000000 { | ||
| 196 | #address-cells = <1>; | ||
| 197 | #size-cells = <1>; | ||
| 198 | device_type = "soc"; | ||
| 199 | compatible = "fsl,mpc8572-immr", "simple-bus"; | ||
| 200 | ranges = <0x0 0 0xef000000 0x100000>; | ||
| 201 | bus-frequency = <0>; // Filled out by uboot. | ||
| 202 | |||
| 203 | ecm-law@0 { | ||
| 204 | compatible = "fsl,ecm-law"; | ||
| 205 | reg = <0x0 0x1000>; | ||
| 206 | fsl,num-laws = <12>; | ||
| 207 | }; | ||
| 208 | |||
| 209 | ecm@1000 { | ||
| 210 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 211 | reg = <0x1000 0x1000>; | ||
| 212 | interrupts = <17 2>; | ||
| 213 | interrupt-parent = <&mpic>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | memory-controller@2000 { | ||
| 217 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 218 | reg = <0x2000 0x1000>; | ||
| 219 | interrupt-parent = <&mpic>; | ||
| 220 | interrupts = <18 2>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | memory-controller@6000 { | ||
| 224 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 225 | reg = <0x6000 0x1000>; | ||
| 226 | interrupt-parent = <&mpic>; | ||
| 227 | interrupts = <18 2>; | ||
| 228 | }; | ||
| 229 | |||
| 230 | L2: l2-cache-controller@20000 { | ||
| 231 | compatible = "fsl,mpc8572-l2-cache-controller"; | ||
| 232 | reg = <0x20000 0x1000>; | ||
| 233 | cache-line-size = <32>; // 32 bytes | ||
| 234 | cache-size = <0x100000>; // L2, 1M | ||
| 235 | interrupt-parent = <&mpic>; | ||
| 236 | interrupts = <16 2>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | i2c@3000 { | ||
| 240 | #address-cells = <1>; | ||
| 241 | #size-cells = <0>; | ||
| 242 | cell-index = <0>; | ||
| 243 | compatible = "fsl-i2c"; | ||
| 244 | reg = <0x3000 0x100>; | ||
| 245 | interrupts = <43 2>; | ||
| 246 | interrupt-parent = <&mpic>; | ||
| 247 | dfsrr; | ||
| 248 | |||
| 249 | temp-sensor@48 { | ||
| 250 | compatible = "dallas,ds1631", "dallas,ds1621"; | ||
| 251 | reg = <0x48>; | ||
| 252 | }; | ||
| 253 | |||
| 254 | temp-sensor@4c { | ||
| 255 | compatible = "adi,adt7461"; | ||
| 256 | reg = <0x4c>; | ||
| 257 | }; | ||
| 258 | |||
| 259 | cpu-supervisor@51 { | ||
| 260 | compatible = "dallas,ds4510"; | ||
| 261 | reg = <0x51>; | ||
| 262 | }; | ||
| 263 | |||
| 264 | eeprom@54 { | ||
| 265 | compatible = "atmel,at24c128b"; | ||
| 266 | reg = <0x54>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | rtc@68 { | ||
| 270 | compatible = "stm,m41t00", | ||
| 271 | "dallas,ds1338"; | ||
| 272 | reg = <0x68>; | ||
| 273 | }; | ||
| 274 | |||
| 275 | pcie-switch@70 { | ||
| 276 | compatible = "plx,pex8518"; | ||
| 277 | reg = <0x70>; | ||
| 278 | }; | ||
| 279 | |||
| 280 | gpio1: gpio@18 { | ||
| 281 | compatible = "nxp,pca9557"; | ||
| 282 | reg = <0x18>; | ||
| 283 | #gpio-cells = <2>; | ||
| 284 | gpio-controller; | ||
| 285 | polarity = <0x00>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | gpio2: gpio@1c { | ||
| 289 | compatible = "nxp,pca9557"; | ||
| 290 | reg = <0x1c>; | ||
| 291 | #gpio-cells = <2>; | ||
| 292 | gpio-controller; | ||
| 293 | polarity = <0x00>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | gpio3: gpio@1e { | ||
| 297 | compatible = "nxp,pca9557"; | ||
| 298 | reg = <0x1e>; | ||
| 299 | #gpio-cells = <2>; | ||
| 300 | gpio-controller; | ||
| 301 | polarity = <0x00>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | gpio4: gpio@1f { | ||
| 305 | compatible = "nxp,pca9557"; | ||
| 306 | reg = <0x1f>; | ||
| 307 | #gpio-cells = <2>; | ||
| 308 | gpio-controller; | ||
| 309 | polarity = <0x00>; | ||
| 310 | }; | ||
| 311 | }; | ||
| 312 | |||
| 313 | i2c@3100 { | ||
| 314 | #address-cells = <1>; | ||
| 315 | #size-cells = <0>; | ||
| 316 | cell-index = <1>; | ||
| 317 | compatible = "fsl-i2c"; | ||
| 318 | reg = <0x3100 0x100>; | ||
| 319 | interrupts = <43 2>; | ||
| 320 | interrupt-parent = <&mpic>; | ||
| 321 | dfsrr; | ||
| 322 | }; | ||
| 323 | |||
| 324 | dma@c300 { | ||
| 325 | #address-cells = <1>; | ||
| 326 | #size-cells = <1>; | ||
| 327 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 328 | reg = <0xc300 0x4>; | ||
| 329 | ranges = <0x0 0xc100 0x200>; | ||
| 330 | cell-index = <1>; | ||
| 331 | dma-channel@0 { | ||
| 332 | compatible = "fsl,mpc8572-dma-channel", | ||
| 333 | "fsl,eloplus-dma-channel"; | ||
| 334 | reg = <0x0 0x80>; | ||
| 335 | cell-index = <0>; | ||
| 336 | interrupt-parent = <&mpic>; | ||
| 337 | interrupts = <76 2>; | ||
| 338 | }; | ||
| 339 | dma-channel@80 { | ||
| 340 | compatible = "fsl,mpc8572-dma-channel", | ||
| 341 | "fsl,eloplus-dma-channel"; | ||
| 342 | reg = <0x80 0x80>; | ||
| 343 | cell-index = <1>; | ||
| 344 | interrupt-parent = <&mpic>; | ||
| 345 | interrupts = <77 2>; | ||
| 346 | }; | ||
| 347 | dma-channel@100 { | ||
| 348 | compatible = "fsl,mpc8572-dma-channel", | ||
| 349 | "fsl,eloplus-dma-channel"; | ||
| 350 | reg = <0x100 0x80>; | ||
| 351 | cell-index = <2>; | ||
| 352 | interrupt-parent = <&mpic>; | ||
| 353 | interrupts = <78 2>; | ||
| 354 | }; | ||
| 355 | dma-channel@180 { | ||
| 356 | compatible = "fsl,mpc8572-dma-channel", | ||
| 357 | "fsl,eloplus-dma-channel"; | ||
| 358 | reg = <0x180 0x80>; | ||
| 359 | cell-index = <3>; | ||
| 360 | interrupt-parent = <&mpic>; | ||
| 361 | interrupts = <79 2>; | ||
| 362 | }; | ||
| 363 | }; | ||
| 364 | |||
| 365 | dma@21300 { | ||
| 366 | #address-cells = <1>; | ||
| 367 | #size-cells = <1>; | ||
| 368 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 369 | reg = <0x21300 0x4>; | ||
| 370 | ranges = <0x0 0x21100 0x200>; | ||
| 371 | cell-index = <0>; | ||
| 372 | dma-channel@0 { | ||
| 373 | compatible = "fsl,mpc8572-dma-channel", | ||
| 374 | "fsl,eloplus-dma-channel"; | ||
| 375 | reg = <0x0 0x80>; | ||
| 376 | cell-index = <0>; | ||
| 377 | interrupt-parent = <&mpic>; | ||
| 378 | interrupts = <20 2>; | ||
| 379 | }; | ||
| 380 | dma-channel@80 { | ||
| 381 | compatible = "fsl,mpc8572-dma-channel", | ||
| 382 | "fsl,eloplus-dma-channel"; | ||
| 383 | reg = <0x80 0x80>; | ||
| 384 | cell-index = <1>; | ||
| 385 | interrupt-parent = <&mpic>; | ||
| 386 | interrupts = <21 2>; | ||
| 387 | }; | ||
| 388 | dma-channel@100 { | ||
| 389 | compatible = "fsl,mpc8572-dma-channel", | ||
| 390 | "fsl,eloplus-dma-channel"; | ||
| 391 | reg = <0x100 0x80>; | ||
| 392 | cell-index = <2>; | ||
| 393 | interrupt-parent = <&mpic>; | ||
| 394 | interrupts = <22 2>; | ||
| 395 | }; | ||
| 396 | dma-channel@180 { | ||
| 397 | compatible = "fsl,mpc8572-dma-channel", | ||
| 398 | "fsl,eloplus-dma-channel"; | ||
| 399 | reg = <0x180 0x80>; | ||
| 400 | cell-index = <3>; | ||
| 401 | interrupt-parent = <&mpic>; | ||
| 402 | interrupts = <23 2>; | ||
| 403 | }; | ||
| 404 | }; | ||
| 405 | |||
| 406 | /* eTSEC 1 */ | ||
| 407 | enet0: ethernet@24000 { | ||
| 408 | #address-cells = <1>; | ||
| 409 | #size-cells = <1>; | ||
| 410 | cell-index = <0>; | ||
| 411 | device_type = "network"; | ||
| 412 | model = "eTSEC"; | ||
| 413 | compatible = "gianfar"; | ||
| 414 | reg = <0x24000 0x1000>; | ||
| 415 | ranges = <0x0 0x24000 0x1000>; | ||
| 416 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 417 | interrupts = <29 2 30 2 34 2>; | ||
| 418 | interrupt-parent = <&mpic>; | ||
| 419 | tbi-handle = <&tbi0>; | ||
| 420 | phy-handle = <&phy0>; | ||
| 421 | phy-connection-type = "sgmii"; | ||
| 422 | |||
| 423 | mdio@520 { | ||
| 424 | #address-cells = <1>; | ||
| 425 | #size-cells = <0>; | ||
| 426 | compatible = "fsl,gianfar-mdio"; | ||
| 427 | reg = <0x520 0x20>; | ||
| 428 | |||
| 429 | phy0: ethernet-phy@1 { | ||
| 430 | interrupt-parent = <&mpic>; | ||
| 431 | interrupts = <8 1>; | ||
| 432 | reg = <0x1>; | ||
| 433 | }; | ||
| 434 | phy1: ethernet-phy@2 { | ||
| 435 | interrupt-parent = <&mpic>; | ||
| 436 | interrupts = <8 1>; | ||
| 437 | reg = <0x2>; | ||
| 438 | }; | ||
| 439 | tbi0: tbi-phy@11 { | ||
| 440 | reg = <0x11>; | ||
| 441 | device_type = "tbi-phy"; | ||
| 442 | }; | ||
| 443 | }; | ||
| 444 | }; | ||
| 445 | |||
| 446 | /* eTSEC 2 */ | ||
| 447 | enet1: ethernet@25000 { | ||
| 448 | #address-cells = <1>; | ||
| 449 | #size-cells = <1>; | ||
| 450 | cell-index = <1>; | ||
| 451 | device_type = "network"; | ||
| 452 | model = "eTSEC"; | ||
| 453 | compatible = "gianfar"; | ||
| 454 | reg = <0x25000 0x1000>; | ||
| 455 | ranges = <0x0 0x25000 0x1000>; | ||
| 456 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 457 | interrupts = <35 2 36 2 40 2>; | ||
| 458 | interrupt-parent = <&mpic>; | ||
| 459 | tbi-handle = <&tbi1>; | ||
| 460 | phy-handle = <&phy1>; | ||
| 461 | phy-connection-type = "sgmii"; | ||
| 462 | |||
| 463 | mdio@520 { | ||
| 464 | #address-cells = <1>; | ||
| 465 | #size-cells = <0>; | ||
| 466 | compatible = "fsl,gianfar-tbi"; | ||
| 467 | reg = <0x520 0x20>; | ||
| 468 | |||
| 469 | tbi1: tbi-phy@11 { | ||
| 470 | reg = <0x11>; | ||
| 471 | device_type = "tbi-phy"; | ||
| 472 | }; | ||
| 473 | }; | ||
| 474 | }; | ||
| 475 | |||
| 476 | /* UART0 */ | ||
| 477 | serial0: serial@4500 { | ||
| 478 | cell-index = <0>; | ||
| 479 | device_type = "serial"; | ||
| 480 | compatible = "ns16550"; | ||
| 481 | reg = <0x4500 0x100>; | ||
| 482 | clock-frequency = <0>; | ||
| 483 | interrupts = <42 2>; | ||
| 484 | interrupt-parent = <&mpic>; | ||
| 485 | }; | ||
| 486 | |||
| 487 | /* UART1 */ | ||
| 488 | serial1: serial@4600 { | ||
| 489 | cell-index = <1>; | ||
| 490 | device_type = "serial"; | ||
| 491 | compatible = "ns16550"; | ||
| 492 | reg = <0x4600 0x100>; | ||
| 493 | clock-frequency = <0>; | ||
| 494 | interrupts = <42 2>; | ||
| 495 | interrupt-parent = <&mpic>; | ||
| 496 | }; | ||
| 497 | |||
| 498 | global-utilities@e0000 { //global utilities block | ||
| 499 | compatible = "fsl,mpc8572-guts"; | ||
| 500 | reg = <0xe0000 0x1000>; | ||
| 501 | fsl,has-rstcr; | ||
| 502 | }; | ||
| 503 | |||
| 504 | msi@41600 { | ||
| 505 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | ||
| 506 | reg = <0x41600 0x80>; | ||
| 507 | msi-available-ranges = <0 0x100>; | ||
| 508 | interrupts = < | ||
| 509 | 0xe0 0 | ||
| 510 | 0xe1 0 | ||
| 511 | 0xe2 0 | ||
| 512 | 0xe3 0 | ||
| 513 | 0xe4 0 | ||
| 514 | 0xe5 0 | ||
| 515 | 0xe6 0 | ||
| 516 | 0xe7 0>; | ||
| 517 | interrupt-parent = <&mpic>; | ||
| 518 | }; | ||
| 519 | |||
| 520 | crypto@30000 { | ||
| 521 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | ||
| 522 | "fsl,sec2.1", "fsl,sec2.0"; | ||
| 523 | reg = <0x30000 0x10000>; | ||
| 524 | interrupts = <45 2 58 2>; | ||
| 525 | interrupt-parent = <&mpic>; | ||
| 526 | fsl,num-channels = <4>; | ||
| 527 | fsl,channel-fifo-len = <24>; | ||
| 528 | fsl,exec-units-mask = <0x9fe>; | ||
| 529 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 530 | }; | ||
| 531 | |||
| 532 | mpic: pic@40000 { | ||
| 533 | interrupt-controller; | ||
| 534 | #address-cells = <0>; | ||
| 535 | #interrupt-cells = <2>; | ||
| 536 | reg = <0x40000 0x40000>; | ||
| 537 | compatible = "chrp,open-pic"; | ||
| 538 | device_type = "open-pic"; | ||
| 539 | }; | ||
| 540 | |||
| 541 | gpio0: gpio@f000 { | ||
| 542 | compatible = "fsl,mpc8572-gpio"; | ||
| 543 | reg = <0xf000 0x1000>; | ||
| 544 | interrupts = <47 2>; | ||
| 545 | interrupt-parent = <&mpic>; | ||
| 546 | #gpio-cells = <2>; | ||
| 547 | gpio-controller; | ||
| 548 | }; | ||
| 549 | |||
| 550 | gpio-leds { | ||
| 551 | compatible = "gpio-leds"; | ||
| 552 | |||
| 553 | heartbeat { | ||
| 554 | label = "Heartbeat"; | ||
| 555 | gpios = <&gpio0 4 1>; | ||
| 556 | linux,default-trigger = "heartbeat"; | ||
| 557 | }; | ||
| 558 | |||
| 559 | yellow { | ||
| 560 | label = "Yellow"; | ||
| 561 | gpios = <&gpio0 5 1>; | ||
| 562 | }; | ||
| 563 | |||
| 564 | red { | ||
| 565 | label = "Red"; | ||
| 566 | gpios = <&gpio0 6 1>; | ||
| 567 | }; | ||
| 568 | |||
| 569 | green { | ||
| 570 | label = "Green"; | ||
| 571 | gpios = <&gpio0 7 1>; | ||
| 572 | }; | ||
| 573 | }; | ||
| 574 | |||
| 575 | /* PME (pattern-matcher) */ | ||
| 576 | pme@10000 { | ||
| 577 | compatible = "fsl,mpc8572-pme", "pme8572"; | ||
| 578 | reg = <0x10000 0x5000>; | ||
| 579 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | ||
| 580 | interrupt-parent = <&mpic>; | ||
| 581 | }; | ||
| 582 | |||
| 583 | tlu@2f000 { | ||
| 584 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 585 | reg = <0x2f000 0x1000>; | ||
| 586 | interupts = <61 2 >; | ||
| 587 | interrupt-parent = <&mpic>; | ||
| 588 | }; | ||
| 589 | |||
| 590 | tlu@15000 { | ||
| 591 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 592 | reg = <0x15000 0x1000>; | ||
| 593 | interupts = <75 2>; | ||
| 594 | interrupt-parent = <&mpic>; | ||
| 595 | }; | ||
| 596 | }; | ||
| 597 | |||
| 598 | /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */ | ||
| 599 | pci0: pcie@ef008000 { | ||
| 600 | compatible = "fsl,mpc8548-pcie"; | ||
| 601 | device_type = "pci"; | ||
| 602 | #interrupt-cells = <1>; | ||
| 603 | #size-cells = <2>; | ||
| 604 | #address-cells = <3>; | ||
| 605 | reg = <0 0xef008000 0 0x1000>; | ||
| 606 | bus-range = <0 255>; | ||
| 607 | ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000 | ||
| 608 | 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>; | ||
| 609 | clock-frequency = <33333333>; | ||
| 610 | interrupt-parent = <&mpic>; | ||
| 611 | interrupts = <24 2>; | ||
| 612 | interrupt-map-mask = <0xff00 0x0 0x0 0x7>; | ||
| 613 | interrupt-map = < | ||
| 614 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 615 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 616 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 617 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 618 | >; | ||
| 619 | pcie@0 { | ||
| 620 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 621 | #size-cells = <2>; | ||
| 622 | #address-cells = <3>; | ||
| 623 | device_type = "pci"; | ||
| 624 | ranges = <0x02000000 0x0 0xe0000000 | ||
| 625 | 0x02000000 0x0 0xe0000000 | ||
| 626 | 0x0 0x10000000 | ||
| 627 | |||
| 628 | 0x01000000 0x0 0x0 | ||
| 629 | 0x01000000 0x0 0x0 | ||
| 630 | 0x0 0x100000>; | ||
| 631 | }; | ||
| 632 | }; | ||
| 633 | |||
| 634 | /* PCI Express controller 2, PMC module via PEX8112 bridge */ | ||
| 635 | pci1: pcie@ef009000 { | ||
| 636 | compatible = "fsl,mpc8548-pcie"; | ||
| 637 | device_type = "pci"; | ||
| 638 | #interrupt-cells = <1>; | ||
| 639 | #size-cells = <2>; | ||
| 640 | #address-cells = <3>; | ||
| 641 | reg = <0 0xef009000 0 0x1000>; | ||
| 642 | bus-range = <0 255>; | ||
| 643 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 | ||
| 644 | 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>; | ||
| 645 | clock-frequency = <33333333>; | ||
| 646 | interrupt-parent = <&mpic>; | ||
| 647 | interrupts = <25 2>; | ||
| 648 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 649 | interrupt-map = < | ||
| 650 | /* IDSEL 0x0 */ | ||
| 651 | 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 | ||
| 652 | 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 | ||
| 653 | 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 | ||
| 654 | 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 | ||
| 655 | >; | ||
| 656 | pcie@0 { | ||
| 657 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 658 | #size-cells = <2>; | ||
| 659 | #address-cells = <3>; | ||
| 660 | device_type = "pci"; | ||
| 661 | ranges = <0x2000000 0x0 0xc0000000 | ||
| 662 | 0x2000000 0x0 0xc0000000 | ||
| 663 | 0x0 0x10000000 | ||
| 664 | |||
| 665 | 0x1000000 0x0 0x0 | ||
| 666 | 0x1000000 0x0 0x0 | ||
| 667 | 0x0 0x100000>; | ||
| 668 | }; | ||
| 669 | }; | ||
| 670 | |||
| 671 | /* PCI Express controller 1, XMC P15 */ | ||
| 672 | pci2: pcie@ef00a000 { | ||
| 673 | compatible = "fsl,mpc8548-pcie"; | ||
| 674 | device_type = "pci"; | ||
| 675 | #interrupt-cells = <1>; | ||
| 676 | #size-cells = <2>; | ||
| 677 | #address-cells = <3>; | ||
| 678 | reg = <0 0xef00a000 0 0x1000>; | ||
| 679 | bus-range = <0 255>; | ||
| 680 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | ||
| 681 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | ||
| 682 | clock-frequency = <33333333>; | ||
| 683 | interrupt-parent = <&mpic>; | ||
| 684 | interrupts = <26 2>; | ||
| 685 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 686 | interrupt-map = < | ||
| 687 | /* IDSEL 0x0 */ | ||
| 688 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 689 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 690 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 691 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 692 | >; | ||
| 693 | pcie@0 { | ||
| 694 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 695 | #size-cells = <2>; | ||
| 696 | #address-cells = <3>; | ||
| 697 | device_type = "pci"; | ||
| 698 | ranges = <0x2000000 0x0 0x80000000 | ||
| 699 | 0x2000000 0x0 0x80000000 | ||
| 700 | 0x0 0x40000000 | ||
| 701 | |||
| 702 | 0x1000000 0x0 0x0 | ||
| 703 | 0x1000000 0x0 0x0 | ||
| 704 | 0x0 0x100000>; | ||
| 705 | }; | ||
| 706 | }; | ||
| 707 | }; | ||
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts new file mode 100644 index 000000000000..7a8a4afd56cf --- /dev/null +++ b/arch/powerpc/boot/dts/xpedite5370.dts | |||
| @@ -0,0 +1,638 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | ||
| 3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * XPedite5370 3U VPX single-board computer based on MPC8572E | ||
| 6 | * | ||
| 7 | * This is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | / { | ||
| 14 | model = "xes,xpedite5370"; | ||
| 15 | compatible = "xes,xpedite5370", "xes,MPC8572"; | ||
| 16 | #address-cells = <2>; | ||
| 17 | #size-cells = <2>; | ||
| 18 | |||
| 19 | aliases { | ||
| 20 | ethernet0 = &enet0; | ||
| 21 | ethernet1 = &enet1; | ||
| 22 | serial0 = &serial0; | ||
| 23 | serial1 = &serial1; | ||
| 24 | pci1 = &pci1; | ||
| 25 | pci2 = &pci2; | ||
| 26 | }; | ||
| 27 | |||
| 28 | cpus { | ||
| 29 | #address-cells = <1>; | ||
| 30 | #size-cells = <0>; | ||
| 31 | |||
| 32 | PowerPC,8572@0 { | ||
| 33 | device_type = "cpu"; | ||
| 34 | reg = <0x0>; | ||
| 35 | d-cache-line-size = <32>; // 32 bytes | ||
| 36 | i-cache-line-size = <32>; // 32 bytes | ||
| 37 | d-cache-size = <0x8000>; // L1, 32K | ||
| 38 | i-cache-size = <0x8000>; // L1, 32K | ||
| 39 | timebase-frequency = <0>; | ||
| 40 | bus-frequency = <0>; | ||
| 41 | clock-frequency = <0>; | ||
| 42 | next-level-cache = <&L2>; | ||
| 43 | }; | ||
| 44 | |||
| 45 | PowerPC,8572@1 { | ||
| 46 | device_type = "cpu"; | ||
| 47 | reg = <0x1>; | ||
| 48 | d-cache-line-size = <32>; // 32 bytes | ||
| 49 | i-cache-line-size = <32>; // 32 bytes | ||
| 50 | d-cache-size = <0x8000>; // L1, 32K | ||
| 51 | i-cache-size = <0x8000>; // L1, 32K | ||
| 52 | timebase-frequency = <0>; | ||
| 53 | bus-frequency = <0>; | ||
| 54 | clock-frequency = <0>; | ||
| 55 | next-level-cache = <&L2>; | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | |||
| 59 | memory { | ||
| 60 | device_type = "memory"; | ||
| 61 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | ||
| 62 | }; | ||
| 63 | |||
| 64 | localbus@ef005000 { | ||
| 65 | #address-cells = <2>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | ||
| 68 | reg = <0 0xef005000 0 0x1000>; | ||
| 69 | interrupts = <19 2>; | ||
| 70 | interrupt-parent = <&mpic>; | ||
| 71 | /* Local bus region mappings */ | ||
| 72 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ | ||
| 73 | 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ | ||
| 74 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | ||
| 75 | 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ | ||
| 76 | |||
| 77 | nor-boot@0,0 { | ||
| 78 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 79 | bank-width = <2>; | ||
| 80 | reg = <0 0 0x8000000>; /* 128MB */ | ||
| 81 | #address-cells = <1>; | ||
| 82 | #size-cells = <1>; | ||
| 83 | partition@0 { | ||
| 84 | label = "Primary user space"; | ||
| 85 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 86 | }; | ||
| 87 | partition@6f00000 { | ||
| 88 | label = "Primary kernel"; | ||
| 89 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 90 | }; | ||
| 91 | partition@7f00000 { | ||
| 92 | label = "Primary DTB"; | ||
| 93 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 94 | }; | ||
| 95 | partition@7f40000 { | ||
| 96 | label = "Primary U-Boot environment"; | ||
| 97 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 98 | }; | ||
| 99 | partition@7f80000 { | ||
| 100 | label = "Primary U-Boot"; | ||
| 101 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 102 | read-only; | ||
| 103 | }; | ||
| 104 | }; | ||
| 105 | |||
| 106 | nor-alternate@1,0 { | ||
| 107 | compatible = "amd,s29gl01gp", "cfi-flash"; | ||
| 108 | bank-width = <2>; | ||
| 109 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | ||
| 110 | reg = <1 0 0x8000000>; /* 128MB */ | ||
| 111 | #address-cells = <1>; | ||
| 112 | #size-cells = <1>; | ||
| 113 | partition@0 { | ||
| 114 | label = "Secondary user space"; | ||
| 115 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | ||
| 116 | }; | ||
| 117 | partition@6f00000 { | ||
| 118 | label = "Secondary kernel"; | ||
| 119 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | ||
| 120 | }; | ||
| 121 | partition@7f00000 { | ||
| 122 | label = "Secondary DTB"; | ||
| 123 | reg = <0x7f00000 0x40000>; /* 256 KB */ | ||
| 124 | }; | ||
| 125 | partition@7f40000 { | ||
| 126 | label = "Secondary U-Boot environment"; | ||
| 127 | reg = <0x7f40000 0x40000>; /* 256 KB */ | ||
| 128 | }; | ||
| 129 | partition@7f80000 { | ||
| 130 | label = "Secondary U-Boot"; | ||
| 131 | reg = <0x7f80000 0x80000>; /* 512 KB */ | ||
| 132 | read-only; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | nand@2,0 { | ||
| 137 | #address-cells = <1>; | ||
| 138 | #size-cells = <1>; | ||
| 139 | /* | ||
| 140 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | ||
| 141 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | ||
| 142 | * MT29F16G08FAA (2x 1 GB), depending on the build | ||
| 143 | * configuration | ||
| 144 | */ | ||
| 145 | compatible = "fsl,mpc8572-fcm-nand", | ||
| 146 | "fsl,elbc-fcm-nand"; | ||
| 147 | reg = <2 0 0x40000>; | ||
| 148 | /* U-Boot should fix this up if chip size > 1 GB */ | ||
| 149 | partition@0 { | ||
| 150 | label = "NAND Filesystem"; | ||
| 151 | reg = <0 0x40000000>; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 155 | }; | ||
| 156 | |||
| 157 | soc8572@ef000000 { | ||
| 158 | #address-cells = <1>; | ||
| 159 | #size-cells = <1>; | ||
| 160 | device_type = "soc"; | ||
| 161 | compatible = "fsl,mpc8572-immr", "simple-bus"; | ||
| 162 | ranges = <0x0 0 0xef000000 0x100000>; | ||
| 163 | bus-frequency = <0>; // Filled out by uboot. | ||
| 164 | |||
| 165 | ecm-law@0 { | ||
| 166 | compatible = "fsl,ecm-law"; | ||
| 167 | reg = <0x0 0x1000>; | ||
| 168 | fsl,num-laws = <12>; | ||
| 169 | }; | ||
| 170 | |||
| 171 | ecm@1000 { | ||
| 172 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | ||
| 173 | reg = <0x1000 0x1000>; | ||
| 174 | interrupts = <17 2>; | ||
| 175 | interrupt-parent = <&mpic>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | memory-controller@2000 { | ||
| 179 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 180 | reg = <0x2000 0x1000>; | ||
| 181 | interrupt-parent = <&mpic>; | ||
| 182 | interrupts = <18 2>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | memory-controller@6000 { | ||
| 186 | compatible = "fsl,mpc8572-memory-controller"; | ||
| 187 | reg = <0x6000 0x1000>; | ||
| 188 | interrupt-parent = <&mpic>; | ||
| 189 | interrupts = <18 2>; | ||
| 190 | }; | ||
| 191 | |||
| 192 | L2: l2-cache-controller@20000 { | ||
| 193 | compatible = "fsl,mpc8572-l2-cache-controller"; | ||
| 194 | reg = <0x20000 0x1000>; | ||
| 195 | cache-line-size = <32>; // 32 bytes | ||
| 196 | cache-size = <0x100000>; // L2, 1M | ||
| 197 | interrupt-parent = <&mpic>; | ||
| 198 | interrupts = <16 2>; | ||
| 199 | }; | ||
| 200 | |||
| 201 | i2c@3000 { | ||
| 202 | #address-cells = <1>; | ||
| 203 | #size-cells = <0>; | ||
| 204 | cell-index = <0>; | ||
| 205 | compatible = "fsl-i2c"; | ||
| 206 | reg = <0x3000 0x100>; | ||
| 207 | interrupts = <43 2>; | ||
| 208 | interrupt-parent = <&mpic>; | ||
| 209 | dfsrr; | ||
| 210 | |||
| 211 | temp-sensor@48 { | ||
| 212 | compatible = "dallas,ds1631", "dallas,ds1621"; | ||
| 213 | reg = <0x48>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | temp-sensor@4c { | ||
| 217 | compatible = "adi,adt7461"; | ||
| 218 | reg = <0x4c>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | cpu-supervisor@51 { | ||
| 222 | compatible = "dallas,ds4510"; | ||
| 223 | reg = <0x51>; | ||
| 224 | }; | ||
| 225 | |||
| 226 | eeprom@54 { | ||
| 227 | compatible = "atmel,at24c128b"; | ||
| 228 | reg = <0x54>; | ||
| 229 | }; | ||
| 230 | |||
| 231 | rtc@68 { | ||
| 232 | compatible = "stm,m41t00", | ||
| 233 | "dallas,ds1338"; | ||
| 234 | reg = <0x68>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | pcie-switch@70 { | ||
| 238 | compatible = "plx,pex8518"; | ||
| 239 | reg = <0x70>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | gpio1: gpio@18 { | ||
| 243 | compatible = "nxp,pca9557"; | ||
| 244 | reg = <0x18>; | ||
| 245 | #gpio-cells = <2>; | ||
| 246 | gpio-controller; | ||
| 247 | polarity = <0x00>; | ||
| 248 | }; | ||
| 249 | |||
| 250 | gpio2: gpio@1c { | ||
| 251 | compatible = "nxp,pca9557"; | ||
| 252 | reg = <0x1c>; | ||
| 253 | #gpio-cells = <2>; | ||
| 254 | gpio-controller; | ||
| 255 | polarity = <0x00>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | gpio3: gpio@1e { | ||
| 259 | compatible = "nxp,pca9557"; | ||
| 260 | reg = <0x1e>; | ||
| 261 | #gpio-cells = <2>; | ||
| 262 | gpio-controller; | ||
| 263 | polarity = <0x00>; | ||
| 264 | }; | ||
| 265 | |||
| 266 | gpio4: gpio@1f { | ||
| 267 | compatible = "nxp,pca9557"; | ||
| 268 | reg = <0x1f>; | ||
| 269 | #gpio-cells = <2>; | ||
| 270 | gpio-controller; | ||
| 271 | polarity = <0x00>; | ||
| 272 | }; | ||
| 273 | }; | ||
| 274 | |||
| 275 | i2c@3100 { | ||
| 276 | #address-cells = <1>; | ||
| 277 | #size-cells = <0>; | ||
| 278 | cell-index = <1>; | ||
| 279 | compatible = "fsl-i2c"; | ||
| 280 | reg = <0x3100 0x100>; | ||
| 281 | interrupts = <43 2>; | ||
| 282 | interrupt-parent = <&mpic>; | ||
| 283 | dfsrr; | ||
| 284 | }; | ||
| 285 | |||
| 286 | dma@c300 { | ||
| 287 | #address-cells = <1>; | ||
| 288 | #size-cells = <1>; | ||
| 289 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 290 | reg = <0xc300 0x4>; | ||
| 291 | ranges = <0x0 0xc100 0x200>; | ||
| 292 | cell-index = <1>; | ||
| 293 | dma-channel@0 { | ||
| 294 | compatible = "fsl,mpc8572-dma-channel", | ||
| 295 | "fsl,eloplus-dma-channel"; | ||
| 296 | reg = <0x0 0x80>; | ||
| 297 | cell-index = <0>; | ||
| 298 | interrupt-parent = <&mpic>; | ||
| 299 | interrupts = <76 2>; | ||
| 300 | }; | ||
| 301 | dma-channel@80 { | ||
| 302 | compatible = "fsl,mpc8572-dma-channel", | ||
| 303 | "fsl,eloplus-dma-channel"; | ||
| 304 | reg = <0x80 0x80>; | ||
| 305 | cell-index = <1>; | ||
| 306 | interrupt-parent = <&mpic>; | ||
| 307 | interrupts = <77 2>; | ||
| 308 | }; | ||
| 309 | dma-channel@100 { | ||
| 310 | compatible = "fsl,mpc8572-dma-channel", | ||
| 311 | "fsl,eloplus-dma-channel"; | ||
| 312 | reg = <0x100 0x80>; | ||
| 313 | cell-index = <2>; | ||
| 314 | interrupt-parent = <&mpic>; | ||
| 315 | interrupts = <78 2>; | ||
| 316 | }; | ||
| 317 | dma-channel@180 { | ||
| 318 | compatible = "fsl,mpc8572-dma-channel", | ||
| 319 | "fsl,eloplus-dma-channel"; | ||
| 320 | reg = <0x180 0x80>; | ||
| 321 | cell-index = <3>; | ||
| 322 | interrupt-parent = <&mpic>; | ||
| 323 | interrupts = <79 2>; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | |||
| 327 | dma@21300 { | ||
| 328 | #address-cells = <1>; | ||
| 329 | #size-cells = <1>; | ||
| 330 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | ||
| 331 | reg = <0x21300 0x4>; | ||
| 332 | ranges = <0x0 0x21100 0x200>; | ||
| 333 | cell-index = <0>; | ||
| 334 | dma-channel@0 { | ||
| 335 | compatible = "fsl,mpc8572-dma-channel", | ||
| 336 | "fsl,eloplus-dma-channel"; | ||
| 337 | reg = <0x0 0x80>; | ||
| 338 | cell-index = <0>; | ||
| 339 | interrupt-parent = <&mpic>; | ||
| 340 | interrupts = <20 2>; | ||
| 341 | }; | ||
| 342 | dma-channel@80 { | ||
| 343 | compatible = "fsl,mpc8572-dma-channel", | ||
| 344 | "fsl,eloplus-dma-channel"; | ||
| 345 | reg = <0x80 0x80>; | ||
| 346 | cell-index = <1>; | ||
| 347 | interrupt-parent = <&mpic>; | ||
| 348 | interrupts = <21 2>; | ||
| 349 | }; | ||
| 350 | dma-channel@100 { | ||
| 351 | compatible = "fsl,mpc8572-dma-channel", | ||
| 352 | "fsl,eloplus-dma-channel"; | ||
| 353 | reg = <0x100 0x80>; | ||
| 354 | cell-index = <2>; | ||
| 355 | interrupt-parent = <&mpic>; | ||
| 356 | interrupts = <22 2>; | ||
| 357 | }; | ||
| 358 | dma-channel@180 { | ||
| 359 | compatible = "fsl,mpc8572-dma-channel", | ||
| 360 | "fsl,eloplus-dma-channel"; | ||
| 361 | reg = <0x180 0x80>; | ||
| 362 | cell-index = <3>; | ||
| 363 | interrupt-parent = <&mpic>; | ||
| 364 | interrupts = <23 2>; | ||
| 365 | }; | ||
| 366 | }; | ||
| 367 | |||
| 368 | /* eTSEC 1 */ | ||
| 369 | enet0: ethernet@24000 { | ||
| 370 | #address-cells = <1>; | ||
| 371 | #size-cells = <1>; | ||
| 372 | cell-index = <0>; | ||
| 373 | device_type = "network"; | ||
| 374 | model = "eTSEC"; | ||
| 375 | compatible = "gianfar"; | ||
| 376 | reg = <0x24000 0x1000>; | ||
| 377 | ranges = <0x0 0x24000 0x1000>; | ||
| 378 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 379 | interrupts = <29 2 30 2 34 2>; | ||
| 380 | interrupt-parent = <&mpic>; | ||
| 381 | tbi-handle = <&tbi0>; | ||
| 382 | phy-handle = <&phy0>; | ||
| 383 | phy-connection-type = "sgmii"; | ||
| 384 | |||
| 385 | mdio@520 { | ||
| 386 | #address-cells = <1>; | ||
| 387 | #size-cells = <0>; | ||
| 388 | compatible = "fsl,gianfar-mdio"; | ||
| 389 | reg = <0x520 0x20>; | ||
| 390 | |||
| 391 | phy0: ethernet-phy@1 { | ||
| 392 | interrupt-parent = <&mpic>; | ||
| 393 | interrupts = <8 1>; | ||
| 394 | reg = <0x1>; | ||
| 395 | }; | ||
| 396 | phy1: ethernet-phy@2 { | ||
| 397 | interrupt-parent = <&mpic>; | ||
| 398 | interrupts = <8 1>; | ||
| 399 | reg = <0x2>; | ||
| 400 | }; | ||
| 401 | tbi0: tbi-phy@11 { | ||
| 402 | reg = <0x11>; | ||
| 403 | device_type = "tbi-phy"; | ||
| 404 | }; | ||
| 405 | }; | ||
| 406 | }; | ||
| 407 | |||
| 408 | /* eTSEC 2 */ | ||
| 409 | enet1: ethernet@25000 { | ||
| 410 | #address-cells = <1>; | ||
| 411 | #size-cells = <1>; | ||
| 412 | cell-index = <1>; | ||
| 413 | device_type = "network"; | ||
| 414 | model = "eTSEC"; | ||
| 415 | compatible = "gianfar"; | ||
| 416 | reg = <0x25000 0x1000>; | ||
| 417 | ranges = <0x0 0x25000 0x1000>; | ||
| 418 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 419 | interrupts = <35 2 36 2 40 2>; | ||
| 420 | interrupt-parent = <&mpic>; | ||
| 421 | tbi-handle = <&tbi1>; | ||
| 422 | phy-handle = <&phy1>; | ||
| 423 | phy-connection-type = "sgmii"; | ||
| 424 | |||
| 425 | mdio@520 { | ||
| 426 | #address-cells = <1>; | ||
| 427 | #size-cells = <0>; | ||
| 428 | compatible = "fsl,gianfar-tbi"; | ||
| 429 | reg = <0x520 0x20>; | ||
| 430 | |||
| 431 | tbi1: tbi-phy@11 { | ||
| 432 | reg = <0x11>; | ||
| 433 | device_type = "tbi-phy"; | ||
| 434 | }; | ||
| 435 | }; | ||
| 436 | }; | ||
| 437 | |||
| 438 | /* UART0 */ | ||
| 439 | serial0: serial@4500 { | ||
| 440 | cell-index = <0>; | ||
| 441 | device_type = "serial"; | ||
| 442 | compatible = "ns16550"; | ||
| 443 | reg = <0x4500 0x100>; | ||
| 444 | clock-frequency = <0>; | ||
| 445 | interrupts = <42 2>; | ||
| 446 | interrupt-parent = <&mpic>; | ||
| 447 | }; | ||
| 448 | |||
| 449 | /* UART1 */ | ||
| 450 | serial1: serial@4600 { | ||
| 451 | cell-index = <1>; | ||
| 452 | device_type = "serial"; | ||
| 453 | compatible = "ns16550"; | ||
| 454 | reg = <0x4600 0x100>; | ||
| 455 | clock-frequency = <0>; | ||
| 456 | interrupts = <42 2>; | ||
| 457 | interrupt-parent = <&mpic>; | ||
| 458 | }; | ||
| 459 | |||
| 460 | global-utilities@e0000 { //global utilities block | ||
| 461 | compatible = "fsl,mpc8572-guts"; | ||
| 462 | reg = <0xe0000 0x1000>; | ||
| 463 | fsl,has-rstcr; | ||
| 464 | }; | ||
| 465 | |||
| 466 | msi@41600 { | ||
| 467 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | ||
| 468 | reg = <0x41600 0x80>; | ||
| 469 | msi-available-ranges = <0 0x100>; | ||
| 470 | interrupts = < | ||
| 471 | 0xe0 0 | ||
| 472 | 0xe1 0 | ||
| 473 | 0xe2 0 | ||
| 474 | 0xe3 0 | ||
| 475 | 0xe4 0 | ||
| 476 | 0xe5 0 | ||
| 477 | 0xe6 0 | ||
| 478 | 0xe7 0>; | ||
| 479 | interrupt-parent = <&mpic>; | ||
| 480 | }; | ||
| 481 | |||
| 482 | crypto@30000 { | ||
| 483 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | ||
| 484 | "fsl,sec2.1", "fsl,sec2.0"; | ||
| 485 | reg = <0x30000 0x10000>; | ||
| 486 | interrupts = <45 2 58 2>; | ||
| 487 | interrupt-parent = <&mpic>; | ||
| 488 | fsl,num-channels = <4>; | ||
| 489 | fsl,channel-fifo-len = <24>; | ||
| 490 | fsl,exec-units-mask = <0x9fe>; | ||
| 491 | fsl,descriptor-types-mask = <0x3ab0ebf>; | ||
| 492 | }; | ||
| 493 | |||
| 494 | mpic: pic@40000 { | ||
| 495 | interrupt-controller; | ||
| 496 | #address-cells = <0>; | ||
| 497 | #interrupt-cells = <2>; | ||
| 498 | reg = <0x40000 0x40000>; | ||
| 499 | compatible = "chrp,open-pic"; | ||
| 500 | device_type = "open-pic"; | ||
| 501 | }; | ||
| 502 | |||
| 503 | gpio0: gpio@f000 { | ||
| 504 | compatible = "fsl,mpc8572-gpio"; | ||
| 505 | reg = <0xf000 0x1000>; | ||
| 506 | interrupts = <47 2>; | ||
| 507 | interrupt-parent = <&mpic>; | ||
| 508 | #gpio-cells = <2>; | ||
| 509 | gpio-controller; | ||
| 510 | }; | ||
| 511 | |||
| 512 | gpio-leds { | ||
| 513 | compatible = "gpio-leds"; | ||
| 514 | |||
| 515 | heartbeat { | ||
| 516 | label = "Heartbeat"; | ||
| 517 | gpios = <&gpio0 4 1>; | ||
| 518 | linux,default-trigger = "heartbeat"; | ||
| 519 | }; | ||
| 520 | |||
| 521 | yellow { | ||
| 522 | label = "Yellow"; | ||
| 523 | gpios = <&gpio0 5 1>; | ||
| 524 | }; | ||
| 525 | |||
| 526 | red { | ||
| 527 | label = "Red"; | ||
| 528 | gpios = <&gpio0 6 1>; | ||
| 529 | }; | ||
| 530 | |||
| 531 | green { | ||
| 532 | label = "Green"; | ||
| 533 | gpios = <&gpio0 7 1>; | ||
| 534 | }; | ||
| 535 | }; | ||
| 536 | |||
| 537 | /* PME (pattern-matcher) */ | ||
| 538 | pme@10000 { | ||
| 539 | compatible = "fsl,mpc8572-pme", "pme8572"; | ||
| 540 | reg = <0x10000 0x5000>; | ||
| 541 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | ||
| 542 | interrupt-parent = <&mpic>; | ||
| 543 | }; | ||
| 544 | |||
| 545 | tlu@2f000 { | ||
| 546 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 547 | reg = <0x2f000 0x1000>; | ||
| 548 | interupts = <61 2 >; | ||
| 549 | interrupt-parent = <&mpic>; | ||
| 550 | }; | ||
| 551 | |||
| 552 | tlu@15000 { | ||
| 553 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | ||
| 554 | reg = <0x15000 0x1000>; | ||
| 555 | interupts = <75 2>; | ||
| 556 | interrupt-parent = <&mpic>; | ||
| 557 | }; | ||
| 558 | }; | ||
| 559 | |||
| 560 | /* | ||
| 561 | * PCI Express controller 3 @ ef008000 is not used. | ||
| 562 | * This would have been pci0 on other mpc85xx platforms. | ||
| 563 | */ | ||
| 564 | |||
| 565 | /* PCI Express controller 2, wired to VPX P1,P2 backplane */ | ||
| 566 | pci1: pcie@ef009000 { | ||
| 567 | compatible = "fsl,mpc8548-pcie"; | ||
| 568 | device_type = "pci"; | ||
| 569 | #interrupt-cells = <1>; | ||
| 570 | #size-cells = <2>; | ||
| 571 | #address-cells = <3>; | ||
| 572 | reg = <0 0xef009000 0 0x1000>; | ||
| 573 | bus-range = <0 255>; | ||
| 574 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 | ||
| 575 | 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; | ||
| 576 | clock-frequency = <33333333>; | ||
| 577 | interrupt-parent = <&mpic>; | ||
| 578 | interrupts = <25 2>; | ||
| 579 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 580 | interrupt-map = < | ||
| 581 | /* IDSEL 0x0 */ | ||
| 582 | 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 | ||
| 583 | 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 | ||
| 584 | 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 | ||
| 585 | 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 | ||
| 586 | >; | ||
| 587 | pcie@0 { | ||
| 588 | reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; | ||
| 589 | #size-cells = <2>; | ||
| 590 | #address-cells = <3>; | ||
| 591 | device_type = "pci"; | ||
| 592 | ranges = <0x2000000 0x0 0xc0000000 | ||
| 593 | 0x2000000 0x0 0xc0000000 | ||
| 594 | 0x0 0x10000000 | ||
| 595 | |||
| 596 | 0x1000000 0x0 0x0 | ||
| 597 | 0x1000000 0x0 0x0 | ||
| 598 | 0x0 0x100000>; | ||
| 599 | }; | ||
| 600 | }; | ||
| 601 | |||
| 602 | /* PCI Express controller 1, wired to PEX8518 PCIe switch */ | ||
| 603 | pci2: pcie@ef00a000 { | ||
| 604 | compatible = "fsl,mpc8548-pcie"; | ||
| 605 | device_type = "pci"; | ||
| 606 | #interrupt-cells = <1>; | ||
| 607 | #size-cells = <2>; | ||
| 608 | #address-cells = <3>; | ||
| 609 | reg = <0 0xef00a000 0 0x1000>; | ||
| 610 | bus-range = <0 255>; | ||
| 611 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | ||
| 612 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | ||
| 613 | clock-frequency = <33333333>; | ||
| 614 | interrupt-parent = <&mpic>; | ||
| 615 | interrupts = <26 2>; | ||
| 616 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 617 | interrupt-map = < | ||
| 618 | /* IDSEL 0x0 */ | ||
| 619 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | ||
| 620 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | ||
| 621 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | ||
| 622 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | ||
| 623 | >; | ||
| 624 | pcie@0 { | ||
| 625 | reg = <0x0 0x0 0x0 0x0 0x0>; | ||
| 626 | #size-cells = <2>; | ||
| 627 | #address-cells = <3>; | ||
| 628 | device_type = "pci"; | ||
| 629 | ranges = <0x2000000 0x0 0x80000000 | ||
| 630 | 0x2000000 0x0 0x80000000 | ||
| 631 | 0x0 0x40000000 | ||
| 632 | |||
| 633 | 0x1000000 0x0 0x0 | ||
| 634 | 0x1000000 0x0 0x0 | ||
| 635 | 0x0 0x100000>; | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | }; | ||
diff --git a/arch/powerpc/boot/install.sh b/arch/powerpc/boot/install.sh index 51b2387bdba0..98312d169c85 100644 --- a/arch/powerpc/boot/install.sh +++ b/arch/powerpc/boot/install.sh | |||
| @@ -18,6 +18,9 @@ | |||
| 18 | # $5 and more - kernel boot files; zImage*, uImage, cuImage.*, etc. | 18 | # $5 and more - kernel boot files; zImage*, uImage, cuImage.*, etc. |
| 19 | # | 19 | # |
| 20 | 20 | ||
| 21 | # Bail with error code if anything goes wrong | ||
| 22 | set -e | ||
| 23 | |||
| 21 | # User may have a custom install script | 24 | # User may have a custom install script |
| 22 | 25 | ||
| 23 | if [ -x ~/bin/${CROSS_COMPILE}installkernel ]; then exec ~/bin/${CROSS_COMPILE}installkernel "$@"; fi | 26 | if [ -x ~/bin/${CROSS_COMPILE}installkernel ]; then exec ~/bin/${CROSS_COMPILE}installkernel "$@"; fi |
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 3ac75aecdb94..4db487d1d2a8 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper | |||
| @@ -225,6 +225,10 @@ asp834x-redboot) | |||
| 225 | platformo="$object/fixed-head.o $object/redboot-83xx.o" | 225 | platformo="$object/fixed-head.o $object/redboot-83xx.o" |
| 226 | binary=y | 226 | binary=y |
| 227 | ;; | 227 | ;; |
| 228 | xpedite52*) | ||
| 229 | link_address='0x1400000' | ||
| 230 | platformo=$object/cuboot-85xx.o | ||
| 231 | ;; | ||
| 228 | esac | 232 | esac |
| 229 | 233 | ||
| 230 | vmz="$tmpdir/`basename \"$kernel\"`.$ext" | 234 | vmz="$tmpdir/`basename \"$kernel\"`.$ext" |
diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig index a32ec8d323a0..173a5bb77ca1 100644 --- a/arch/powerpc/configs/40x/acadia_defconfig +++ b/arch/powerpc/configs/40x/acadia_defconfig | |||
| @@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 252 | # CONFIG_PCIEPORTBUS is not set | 252 | # CONFIG_PCIEPORTBUS is not set |
| 253 | CONFIG_ARCH_SUPPORTS_MSI=y | 253 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 254 | # CONFIG_PCI_MSI is not set | 254 | # CONFIG_PCI_MSI is not set |
| 255 | CONFIG_PCI_LEGACY=y | 255 | # CONFIG_PCI_LEGACY is not set |
| 256 | # CONFIG_PCI_DEBUG is not set | 256 | # CONFIG_PCI_DEBUG is not set |
| 257 | # CONFIG_PCI_STUB is not set | 257 | # CONFIG_PCI_STUB is not set |
| 258 | # CONFIG_PCCARD is not set | 258 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig index 4e9d85f39da0..e9b8495cde0c 100644 --- a/arch/powerpc/configs/40x/ep405_defconfig +++ b/arch/powerpc/configs/40x/ep405_defconfig | |||
| @@ -254,7 +254,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 254 | # CONFIG_PCIEPORTBUS is not set | 254 | # CONFIG_PCIEPORTBUS is not set |
| 255 | CONFIG_ARCH_SUPPORTS_MSI=y | 255 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 256 | # CONFIG_PCI_MSI is not set | 256 | # CONFIG_PCI_MSI is not set |
| 257 | CONFIG_PCI_LEGACY=y | 257 | # CONFIG_PCI_LEGACY is not set |
| 258 | # CONFIG_PCI_DEBUG is not set | 258 | # CONFIG_PCI_DEBUG is not set |
| 259 | # CONFIG_PCI_STUB is not set | 259 | # CONFIG_PCI_STUB is not set |
| 260 | # CONFIG_PCCARD is not set | 260 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig index 9917a09bad3a..865725effe93 100644 --- a/arch/powerpc/configs/40x/kilauea_defconfig +++ b/arch/powerpc/configs/40x/kilauea_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.29-rc2 | 3 | # Linux kernel version: 2.6.30-rc7 |
| 4 | # Tue Jan 20 08:17:52 2009 | 4 | # Wed Jun 3 10:18:16 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_PPC64 is not set | 6 | # CONFIG_PPC64 is not set |
| 7 | 7 | ||
| @@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y | |||
| 27 | CONFIG_GENERIC_TIME_VSYSCALL=y | 27 | CONFIG_GENERIC_TIME_VSYSCALL=y |
| 28 | CONFIG_GENERIC_CLOCKEVENTS=y | 28 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 29 | CONFIG_GENERIC_HARDIRQS=y | 29 | CONFIG_GENERIC_HARDIRQS=y |
| 30 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 30 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set | 31 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set |
| 31 | CONFIG_IRQ_PER_CPU=y | 32 | CONFIG_IRQ_PER_CPU=y |
| 32 | CONFIG_STACKTRACE_SUPPORT=y | 33 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -49,10 +50,12 @@ CONFIG_PPC_UDBG_16550=y | |||
| 49 | # CONFIG_GENERIC_TBSYNC is not set | 50 | # CONFIG_GENERIC_TBSYNC is not set |
| 50 | CONFIG_AUDIT_ARCH=y | 51 | CONFIG_AUDIT_ARCH=y |
| 51 | CONFIG_GENERIC_BUG=y | 52 | CONFIG_GENERIC_BUG=y |
| 53 | CONFIG_DTC=y | ||
| 52 | # CONFIG_DEFAULT_UIMAGE is not set | 54 | # CONFIG_DEFAULT_UIMAGE is not set |
| 53 | CONFIG_PPC_DCR_NATIVE=y | 55 | CONFIG_PPC_DCR_NATIVE=y |
| 54 | # CONFIG_PPC_DCR_MMIO is not set | 56 | # CONFIG_PPC_DCR_MMIO is not set |
| 55 | CONFIG_PPC_DCR=y | 57 | CONFIG_PPC_DCR=y |
| 58 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y | ||
| 56 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 59 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 57 | 60 | ||
| 58 | # | 61 | # |
| @@ -67,9 +70,19 @@ CONFIG_SWAP=y | |||
| 67 | CONFIG_SYSVIPC=y | 70 | CONFIG_SYSVIPC=y |
| 68 | CONFIG_SYSVIPC_SYSCTL=y | 71 | CONFIG_SYSVIPC_SYSCTL=y |
| 69 | CONFIG_POSIX_MQUEUE=y | 72 | CONFIG_POSIX_MQUEUE=y |
| 73 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 70 | # CONFIG_BSD_PROCESS_ACCT is not set | 74 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 71 | # CONFIG_TASKSTATS is not set | 75 | # CONFIG_TASKSTATS is not set |
| 72 | # CONFIG_AUDIT is not set | 76 | # CONFIG_AUDIT is not set |
| 77 | |||
| 78 | # | ||
| 79 | # RCU Subsystem | ||
| 80 | # | ||
| 81 | CONFIG_CLASSIC_RCU=y | ||
| 82 | # CONFIG_TREE_RCU is not set | ||
| 83 | # CONFIG_PREEMPT_RCU is not set | ||
| 84 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 85 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 73 | # CONFIG_IKCONFIG is not set | 86 | # CONFIG_IKCONFIG is not set |
| 74 | CONFIG_LOG_BUF_SHIFT=14 | 87 | CONFIG_LOG_BUF_SHIFT=14 |
| 75 | CONFIG_GROUP_SCHED=y | 88 | CONFIG_GROUP_SCHED=y |
| @@ -84,22 +97,24 @@ CONFIG_SYSFS_DEPRECATED_V2=y | |||
| 84 | # CONFIG_NAMESPACES is not set | 97 | # CONFIG_NAMESPACES is not set |
| 85 | CONFIG_BLK_DEV_INITRD=y | 98 | CONFIG_BLK_DEV_INITRD=y |
| 86 | CONFIG_INITRAMFS_SOURCE="" | 99 | CONFIG_INITRAMFS_SOURCE="" |
| 100 | CONFIG_RD_GZIP=y | ||
| 101 | # CONFIG_RD_BZIP2 is not set | ||
| 102 | # CONFIG_RD_LZMA is not set | ||
| 87 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 103 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 88 | CONFIG_SYSCTL=y | 104 | CONFIG_SYSCTL=y |
| 105 | CONFIG_ANON_INODES=y | ||
| 89 | CONFIG_EMBEDDED=y | 106 | CONFIG_EMBEDDED=y |
| 90 | CONFIG_SYSCTL_SYSCALL=y | 107 | CONFIG_SYSCTL_SYSCALL=y |
| 91 | CONFIG_KALLSYMS=y | 108 | CONFIG_KALLSYMS=y |
| 92 | CONFIG_KALLSYMS_ALL=y | 109 | CONFIG_KALLSYMS_ALL=y |
| 93 | CONFIG_KALLSYMS_STRIP_GENERATED=y | ||
| 94 | CONFIG_KALLSYMS_EXTRA_PASS=y | 110 | CONFIG_KALLSYMS_EXTRA_PASS=y |
| 111 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 95 | CONFIG_HOTPLUG=y | 112 | CONFIG_HOTPLUG=y |
| 96 | CONFIG_PRINTK=y | 113 | CONFIG_PRINTK=y |
| 97 | CONFIG_BUG=y | 114 | CONFIG_BUG=y |
| 98 | CONFIG_ELF_CORE=y | 115 | CONFIG_ELF_CORE=y |
| 99 | CONFIG_COMPAT_BRK=y | ||
| 100 | CONFIG_BASE_FULL=y | 116 | CONFIG_BASE_FULL=y |
| 101 | CONFIG_FUTEX=y | 117 | CONFIG_FUTEX=y |
| 102 | CONFIG_ANON_INODES=y | ||
| 103 | CONFIG_EPOLL=y | 118 | CONFIG_EPOLL=y |
| 104 | CONFIG_SIGNALFD=y | 119 | CONFIG_SIGNALFD=y |
| 105 | CONFIG_TIMERFD=y | 120 | CONFIG_TIMERFD=y |
| @@ -109,10 +124,12 @@ CONFIG_AIO=y | |||
| 109 | CONFIG_VM_EVENT_COUNTERS=y | 124 | CONFIG_VM_EVENT_COUNTERS=y |
| 110 | CONFIG_PCI_QUIRKS=y | 125 | CONFIG_PCI_QUIRKS=y |
| 111 | CONFIG_SLUB_DEBUG=y | 126 | CONFIG_SLUB_DEBUG=y |
| 127 | CONFIG_COMPAT_BRK=y | ||
| 112 | # CONFIG_SLAB is not set | 128 | # CONFIG_SLAB is not set |
| 113 | CONFIG_SLUB=y | 129 | CONFIG_SLUB=y |
| 114 | # CONFIG_SLOB is not set | 130 | # CONFIG_SLOB is not set |
| 115 | # CONFIG_PROFILING is not set | 131 | # CONFIG_PROFILING is not set |
| 132 | # CONFIG_MARKERS is not set | ||
| 116 | CONFIG_HAVE_OPROFILE=y | 133 | CONFIG_HAVE_OPROFILE=y |
| 117 | # CONFIG_KPROBES is not set | 134 | # CONFIG_KPROBES is not set |
| 118 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | 135 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y |
| @@ -120,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y | |||
| 120 | CONFIG_HAVE_KPROBES=y | 137 | CONFIG_HAVE_KPROBES=y |
| 121 | CONFIG_HAVE_KRETPROBES=y | 138 | CONFIG_HAVE_KRETPROBES=y |
| 122 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 139 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 140 | # CONFIG_SLOW_WORK is not set | ||
| 123 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 141 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 124 | CONFIG_SLABINFO=y | 142 | CONFIG_SLABINFO=y |
| 125 | CONFIG_RT_MUTEXES=y | 143 | CONFIG_RT_MUTEXES=y |
| @@ -132,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y | |||
| 132 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 150 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 133 | CONFIG_BLOCK=y | 151 | CONFIG_BLOCK=y |
| 134 | CONFIG_LBD=y | 152 | CONFIG_LBD=y |
| 135 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 136 | # CONFIG_BLK_DEV_BSG is not set | 153 | # CONFIG_BLK_DEV_BSG is not set |
| 137 | # CONFIG_BLK_DEV_INTEGRITY is not set | 154 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 138 | 155 | ||
| @@ -148,11 +165,6 @@ CONFIG_DEFAULT_AS=y | |||
| 148 | # CONFIG_DEFAULT_CFQ is not set | 165 | # CONFIG_DEFAULT_CFQ is not set |
| 149 | # CONFIG_DEFAULT_NOOP is not set | 166 | # CONFIG_DEFAULT_NOOP is not set |
| 150 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 167 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 151 | CONFIG_CLASSIC_RCU=y | ||
| 152 | # CONFIG_TREE_RCU is not set | ||
| 153 | # CONFIG_PREEMPT_RCU is not set | ||
| 154 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 155 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 156 | # CONFIG_FREEZER is not set | 168 | # CONFIG_FREEZER is not set |
| 157 | CONFIG_PPC4xx_PCI_EXPRESS=y | 169 | CONFIG_PPC4xx_PCI_EXPRESS=y |
| 158 | 170 | ||
| @@ -170,7 +182,7 @@ CONFIG_KILAUEA=y | |||
| 170 | # CONFIG_MAKALU is not set | 182 | # CONFIG_MAKALU is not set |
| 171 | # CONFIG_WALNUT is not set | 183 | # CONFIG_WALNUT is not set |
| 172 | # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set | 184 | # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set |
| 173 | # CONFIG_PPC40x_SIMPLE is not set | 185 | CONFIG_PPC40x_SIMPLE=y |
| 174 | CONFIG_405EX=y | 186 | CONFIG_405EX=y |
| 175 | # CONFIG_IPIC is not set | 187 | # CONFIG_IPIC is not set |
| 176 | # CONFIG_MPIC is not set | 188 | # CONFIG_MPIC is not set |
| @@ -228,9 +240,12 @@ CONFIG_ZONE_DMA_FLAG=1 | |||
| 228 | CONFIG_BOUNCE=y | 240 | CONFIG_BOUNCE=y |
| 229 | CONFIG_VIRT_TO_BUS=y | 241 | CONFIG_VIRT_TO_BUS=y |
| 230 | CONFIG_UNEVICTABLE_LRU=y | 242 | CONFIG_UNEVICTABLE_LRU=y |
| 243 | CONFIG_HAVE_MLOCK=y | ||
| 244 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 231 | CONFIG_PPC_4K_PAGES=y | 245 | CONFIG_PPC_4K_PAGES=y |
| 232 | # CONFIG_PPC_16K_PAGES is not set | 246 | # CONFIG_PPC_16K_PAGES is not set |
| 233 | # CONFIG_PPC_64K_PAGES is not set | 247 | # CONFIG_PPC_64K_PAGES is not set |
| 248 | # CONFIG_PPC_256K_PAGES is not set | ||
| 234 | CONFIG_FORCE_MAX_ZONEORDER=11 | 249 | CONFIG_FORCE_MAX_ZONEORDER=11 |
| 235 | CONFIG_PROC_DEVICETREE=y | 250 | CONFIG_PROC_DEVICETREE=y |
| 236 | # CONFIG_CMDLINE_BOOL is not set | 251 | # CONFIG_CMDLINE_BOOL is not set |
| @@ -252,9 +267,10 @@ CONFIG_PCI_SYSCALL=y | |||
| 252 | # CONFIG_PCIEPORTBUS is not set | 267 | # CONFIG_PCIEPORTBUS is not set |
| 253 | CONFIG_ARCH_SUPPORTS_MSI=y | 268 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 254 | # CONFIG_PCI_MSI is not set | 269 | # CONFIG_PCI_MSI is not set |
| 255 | CONFIG_PCI_LEGACY=y | 270 | # CONFIG_PCI_LEGACY is not set |
| 256 | # CONFIG_PCI_DEBUG is not set | 271 | # CONFIG_PCI_DEBUG is not set |
| 257 | # CONFIG_PCI_STUB is not set | 272 | # CONFIG_PCI_STUB is not set |
| 273 | # CONFIG_PCI_IOV is not set | ||
| 258 | # CONFIG_PCCARD is not set | 274 | # CONFIG_PCCARD is not set |
| 259 | # CONFIG_HOTPLUG_PCI is not set | 275 | # CONFIG_HOTPLUG_PCI is not set |
| 260 | # CONFIG_HAS_RAPIDIO is not set | 276 | # CONFIG_HAS_RAPIDIO is not set |
| @@ -272,14 +288,12 @@ CONFIG_PAGE_OFFSET=0xc0000000 | |||
| 272 | CONFIG_KERNEL_START=0xc0000000 | 288 | CONFIG_KERNEL_START=0xc0000000 |
| 273 | CONFIG_PHYSICAL_START=0x00000000 | 289 | CONFIG_PHYSICAL_START=0x00000000 |
| 274 | CONFIG_TASK_SIZE=0xc0000000 | 290 | CONFIG_TASK_SIZE=0xc0000000 |
| 275 | CONFIG_CONSISTENT_START=0xff100000 | ||
| 276 | CONFIG_CONSISTENT_SIZE=0x00200000 | 291 | CONFIG_CONSISTENT_SIZE=0x00200000 |
| 277 | CONFIG_NET=y | 292 | CONFIG_NET=y |
| 278 | 293 | ||
| 279 | # | 294 | # |
| 280 | # Networking options | 295 | # Networking options |
| 281 | # | 296 | # |
| 282 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 283 | CONFIG_PACKET=y | 297 | CONFIG_PACKET=y |
| 284 | # CONFIG_PACKET_MMAP is not set | 298 | # CONFIG_PACKET_MMAP is not set |
| 285 | CONFIG_UNIX=y | 299 | CONFIG_UNIX=y |
| @@ -329,6 +343,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 329 | # CONFIG_LAPB is not set | 343 | # CONFIG_LAPB is not set |
| 330 | # CONFIG_ECONET is not set | 344 | # CONFIG_ECONET is not set |
| 331 | # CONFIG_WAN_ROUTER is not set | 345 | # CONFIG_WAN_ROUTER is not set |
| 346 | # CONFIG_PHONET is not set | ||
| 332 | # CONFIG_NET_SCHED is not set | 347 | # CONFIG_NET_SCHED is not set |
| 333 | # CONFIG_DCB is not set | 348 | # CONFIG_DCB is not set |
| 334 | 349 | ||
| @@ -341,7 +356,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 341 | # CONFIG_IRDA is not set | 356 | # CONFIG_IRDA is not set |
| 342 | # CONFIG_BT is not set | 357 | # CONFIG_BT is not set |
| 343 | # CONFIG_AF_RXRPC is not set | 358 | # CONFIG_AF_RXRPC is not set |
| 344 | # CONFIG_PHONET is not set | ||
| 345 | # CONFIG_WIRELESS is not set | 359 | # CONFIG_WIRELESS is not set |
| 346 | # CONFIG_WIMAX is not set | 360 | # CONFIG_WIMAX is not set |
| 347 | # CONFIG_RFKILL is not set | 361 | # CONFIG_RFKILL is not set |
| @@ -445,7 +459,6 @@ CONFIG_MTD_PHYSMAP_OF=y | |||
| 445 | # LPDDR flash memory drivers | 459 | # LPDDR flash memory drivers |
| 446 | # | 460 | # |
| 447 | # CONFIG_MTD_LPDDR is not set | 461 | # CONFIG_MTD_LPDDR is not set |
| 448 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 449 | 462 | ||
| 450 | # | 463 | # |
| 451 | # UBI - Unsorted block images | 464 | # UBI - Unsorted block images |
| @@ -498,6 +511,7 @@ CONFIG_HAVE_IDE=y | |||
| 498 | # CONFIG_I2O is not set | 511 | # CONFIG_I2O is not set |
| 499 | # CONFIG_MACINTOSH_DRIVERS is not set | 512 | # CONFIG_MACINTOSH_DRIVERS is not set |
| 500 | CONFIG_NETDEVICES=y | 513 | CONFIG_NETDEVICES=y |
| 514 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 501 | # CONFIG_DUMMY is not set | 515 | # CONFIG_DUMMY is not set |
| 502 | # CONFIG_BONDING is not set | 516 | # CONFIG_BONDING is not set |
| 503 | # CONFIG_MACVLAN is not set | 517 | # CONFIG_MACVLAN is not set |
| @@ -512,6 +526,8 @@ CONFIG_NET_ETHERNET=y | |||
| 512 | # CONFIG_SUNGEM is not set | 526 | # CONFIG_SUNGEM is not set |
| 513 | # CONFIG_CASSINI is not set | 527 | # CONFIG_CASSINI is not set |
| 514 | # CONFIG_NET_VENDOR_3COM is not set | 528 | # CONFIG_NET_VENDOR_3COM is not set |
| 529 | # CONFIG_ETHOC is not set | ||
| 530 | # CONFIG_DNET is not set | ||
| 515 | # CONFIG_NET_TULIP is not set | 531 | # CONFIG_NET_TULIP is not set |
| 516 | # CONFIG_HP100 is not set | 532 | # CONFIG_HP100 is not set |
| 517 | CONFIG_IBM_NEW_EMAC=y | 533 | CONFIG_IBM_NEW_EMAC=y |
| @@ -540,7 +556,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y | |||
| 540 | # | 556 | # |
| 541 | # CONFIG_WLAN_PRE80211 is not set | 557 | # CONFIG_WLAN_PRE80211 is not set |
| 542 | # CONFIG_WLAN_80211 is not set | 558 | # CONFIG_WLAN_80211 is not set |
| 543 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 544 | 559 | ||
| 545 | # | 560 | # |
| 546 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 561 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -678,6 +693,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 678 | # CONFIG_EDAC is not set | 693 | # CONFIG_EDAC is not set |
| 679 | # CONFIG_RTC_CLASS is not set | 694 | # CONFIG_RTC_CLASS is not set |
| 680 | # CONFIG_DMADEVICES is not set | 695 | # CONFIG_DMADEVICES is not set |
| 696 | # CONFIG_AUXDISPLAY is not set | ||
| 681 | # CONFIG_UIO is not set | 697 | # CONFIG_UIO is not set |
| 682 | # CONFIG_STAGING is not set | 698 | # CONFIG_STAGING is not set |
| 683 | 699 | ||
| @@ -706,6 +722,11 @@ CONFIG_INOTIFY_USER=y | |||
| 706 | # CONFIG_FUSE_FS is not set | 722 | # CONFIG_FUSE_FS is not set |
| 707 | 723 | ||
| 708 | # | 724 | # |
| 725 | # Caches | ||
| 726 | # | ||
| 727 | # CONFIG_FSCACHE is not set | ||
| 728 | |||
| 729 | # | ||
| 709 | # CD-ROM/DVD Filesystems | 730 | # CD-ROM/DVD Filesystems |
| 710 | # | 731 | # |
| 711 | # CONFIG_ISO9660_FS is not set | 732 | # CONFIG_ISO9660_FS is not set |
| @@ -749,6 +770,7 @@ CONFIG_CRAMFS=y | |||
| 749 | # CONFIG_ROMFS_FS is not set | 770 | # CONFIG_ROMFS_FS is not set |
| 750 | # CONFIG_SYSV_FS is not set | 771 | # CONFIG_SYSV_FS is not set |
| 751 | # CONFIG_UFS_FS is not set | 772 | # CONFIG_UFS_FS is not set |
| 773 | # CONFIG_NILFS2_FS is not set | ||
| 752 | CONFIG_NETWORK_FILESYSTEMS=y | 774 | CONFIG_NETWORK_FILESYSTEMS=y |
| 753 | CONFIG_NFS_FS=y | 775 | CONFIG_NFS_FS=y |
| 754 | CONFIG_NFS_V3=y | 776 | CONFIG_NFS_V3=y |
| @@ -760,7 +782,6 @@ CONFIG_LOCKD=y | |||
| 760 | CONFIG_LOCKD_V4=y | 782 | CONFIG_LOCKD_V4=y |
| 761 | CONFIG_NFS_COMMON=y | 783 | CONFIG_NFS_COMMON=y |
| 762 | CONFIG_SUNRPC=y | 784 | CONFIG_SUNRPC=y |
| 763 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 764 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 785 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 765 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 786 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 766 | # CONFIG_SMB_FS is not set | 787 | # CONFIG_SMB_FS is not set |
| @@ -776,6 +797,7 @@ CONFIG_SUNRPC=y | |||
| 776 | CONFIG_MSDOS_PARTITION=y | 797 | CONFIG_MSDOS_PARTITION=y |
| 777 | # CONFIG_NLS is not set | 798 | # CONFIG_NLS is not set |
| 778 | # CONFIG_DLM is not set | 799 | # CONFIG_DLM is not set |
| 800 | # CONFIG_BINARY_PRINTF is not set | ||
| 779 | 801 | ||
| 780 | # | 802 | # |
| 781 | # Library routines | 803 | # Library routines |
| @@ -790,11 +812,12 @@ CONFIG_CRC32=y | |||
| 790 | # CONFIG_CRC7 is not set | 812 | # CONFIG_CRC7 is not set |
| 791 | # CONFIG_LIBCRC32C is not set | 813 | # CONFIG_LIBCRC32C is not set |
| 792 | CONFIG_ZLIB_INFLATE=y | 814 | CONFIG_ZLIB_INFLATE=y |
| 793 | CONFIG_PLIST=y | 815 | CONFIG_DECOMPRESS_GZIP=y |
| 794 | CONFIG_HAS_IOMEM=y | 816 | CONFIG_HAS_IOMEM=y |
| 795 | CONFIG_HAS_IOPORT=y | 817 | CONFIG_HAS_IOPORT=y |
| 796 | CONFIG_HAS_DMA=y | 818 | CONFIG_HAS_DMA=y |
| 797 | CONFIG_HAVE_LMB=y | 819 | CONFIG_HAVE_LMB=y |
| 820 | CONFIG_NLATTR=y | ||
| 798 | 821 | ||
| 799 | # | 822 | # |
| 800 | # Kernel hacking | 823 | # Kernel hacking |
| @@ -812,6 +835,9 @@ CONFIG_DEBUG_KERNEL=y | |||
| 812 | CONFIG_DETECT_SOFTLOCKUP=y | 835 | CONFIG_DETECT_SOFTLOCKUP=y |
| 813 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 836 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 814 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 837 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| 838 | CONFIG_DETECT_HUNG_TASK=y | ||
| 839 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 840 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 815 | CONFIG_SCHED_DEBUG=y | 841 | CONFIG_SCHED_DEBUG=y |
| 816 | # CONFIG_SCHEDSTATS is not set | 842 | # CONFIG_SCHEDSTATS is not set |
| 817 | # CONFIG_TIMER_STATS is not set | 843 | # CONFIG_TIMER_STATS is not set |
| @@ -841,9 +867,12 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 841 | # CONFIG_FAULT_INJECTION is not set | 867 | # CONFIG_FAULT_INJECTION is not set |
| 842 | # CONFIG_LATENCYTOP is not set | 868 | # CONFIG_LATENCYTOP is not set |
| 843 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 869 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 870 | # CONFIG_DEBUG_PAGEALLOC is not set | ||
| 844 | CONFIG_HAVE_FUNCTION_TRACER=y | 871 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 872 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | ||
| 845 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 873 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 846 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | 874 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 875 | CONFIG_TRACING_SUPPORT=y | ||
| 847 | 876 | ||
| 848 | # | 877 | # |
| 849 | # Tracers | 878 | # Tracers |
| @@ -851,17 +880,21 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |||
| 851 | # CONFIG_FUNCTION_TRACER is not set | 880 | # CONFIG_FUNCTION_TRACER is not set |
| 852 | # CONFIG_SCHED_TRACER is not set | 881 | # CONFIG_SCHED_TRACER is not set |
| 853 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 882 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 883 | # CONFIG_EVENT_TRACER is not set | ||
| 854 | # CONFIG_BOOT_TRACER is not set | 884 | # CONFIG_BOOT_TRACER is not set |
| 855 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 885 | # CONFIG_TRACE_BRANCH_PROFILING is not set |
| 856 | # CONFIG_STACK_TRACER is not set | 886 | # CONFIG_STACK_TRACER is not set |
| 857 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 887 | # CONFIG_KMEMTRACE is not set |
| 888 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 889 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 890 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 858 | # CONFIG_SAMPLES is not set | 891 | # CONFIG_SAMPLES is not set |
| 859 | CONFIG_HAVE_ARCH_KGDB=y | 892 | CONFIG_HAVE_ARCH_KGDB=y |
| 860 | # CONFIG_KGDB is not set | 893 | # CONFIG_KGDB is not set |
| 861 | CONFIG_PRINT_STACK_DEPTH=64 | 894 | CONFIG_PRINT_STACK_DEPTH=64 |
| 862 | # CONFIG_DEBUG_STACKOVERFLOW is not set | 895 | # CONFIG_DEBUG_STACKOVERFLOW is not set |
| 863 | # CONFIG_DEBUG_STACK_USAGE is not set | 896 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 864 | # CONFIG_DEBUG_PAGEALLOC is not set | 897 | # CONFIG_PPC_EMULATED_STATS is not set |
| 865 | # CONFIG_CODE_PATCHING_SELFTEST is not set | 898 | # CONFIG_CODE_PATCHING_SELFTEST is not set |
| 866 | # CONFIG_FTR_FIXUP_SELFTEST is not set | 899 | # CONFIG_FTR_FIXUP_SELFTEST is not set |
| 867 | # CONFIG_MSI_BITMAP_SELFTEST is not set | 900 | # CONFIG_MSI_BITMAP_SELFTEST is not set |
| @@ -892,10 +925,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y | |||
| 892 | CONFIG_CRYPTO_HASH=y | 925 | CONFIG_CRYPTO_HASH=y |
| 893 | CONFIG_CRYPTO_HASH2=y | 926 | CONFIG_CRYPTO_HASH2=y |
| 894 | CONFIG_CRYPTO_RNG2=y | 927 | CONFIG_CRYPTO_RNG2=y |
| 928 | CONFIG_CRYPTO_PCOMP=y | ||
| 895 | CONFIG_CRYPTO_MANAGER=y | 929 | CONFIG_CRYPTO_MANAGER=y |
| 896 | CONFIG_CRYPTO_MANAGER2=y | 930 | CONFIG_CRYPTO_MANAGER2=y |
| 897 | # CONFIG_CRYPTO_GF128MUL is not set | 931 | # CONFIG_CRYPTO_GF128MUL is not set |
| 898 | # CONFIG_CRYPTO_NULL is not set | 932 | # CONFIG_CRYPTO_NULL is not set |
| 933 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 899 | # CONFIG_CRYPTO_CRYPTD is not set | 934 | # CONFIG_CRYPTO_CRYPTD is not set |
| 900 | # CONFIG_CRYPTO_AUTHENC is not set | 935 | # CONFIG_CRYPTO_AUTHENC is not set |
| 901 | # CONFIG_CRYPTO_TEST is not set | 936 | # CONFIG_CRYPTO_TEST is not set |
| @@ -964,6 +999,7 @@ CONFIG_CRYPTO_DES=y | |||
| 964 | # Compression | 999 | # Compression |
| 965 | # | 1000 | # |
| 966 | # CONFIG_CRYPTO_DEFLATE is not set | 1001 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1002 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 967 | # CONFIG_CRYPTO_LZO is not set | 1003 | # CONFIG_CRYPTO_LZO is not set |
| 968 | 1004 | ||
| 969 | # | 1005 | # |
| @@ -972,5 +1008,6 @@ CONFIG_CRYPTO_DES=y | |||
| 972 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 1008 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 973 | CONFIG_CRYPTO_HW=y | 1009 | CONFIG_CRYPTO_HW=y |
| 974 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | 1010 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set |
| 1011 | # CONFIG_CRYPTO_DEV_PPC4XX is not set | ||
| 975 | # CONFIG_PPC_CLOCK is not set | 1012 | # CONFIG_PPC_CLOCK is not set |
| 976 | # CONFIG_VIRTUALIZATION is not set | 1013 | # CONFIG_VIRTUALIZATION is not set |
diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig index 58bf2ac2e0dd..146747547873 100644 --- a/arch/powerpc/configs/40x/makalu_defconfig +++ b/arch/powerpc/configs/40x/makalu_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.29-rc2 | 3 | # Linux kernel version: 2.6.30-rc7 |
| 4 | # Tue Jan 20 08:17:53 2009 | 4 | # Wed Jun 3 09:11:02 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_PPC64 is not set | 6 | # CONFIG_PPC64 is not set |
| 7 | 7 | ||
| @@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y | |||
| 27 | CONFIG_GENERIC_TIME_VSYSCALL=y | 27 | CONFIG_GENERIC_TIME_VSYSCALL=y |
| 28 | CONFIG_GENERIC_CLOCKEVENTS=y | 28 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 29 | CONFIG_GENERIC_HARDIRQS=y | 29 | CONFIG_GENERIC_HARDIRQS=y |
| 30 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 30 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set | 31 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set |
| 31 | CONFIG_IRQ_PER_CPU=y | 32 | CONFIG_IRQ_PER_CPU=y |
| 32 | CONFIG_STACKTRACE_SUPPORT=y | 33 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -49,10 +50,12 @@ CONFIG_PPC_UDBG_16550=y | |||
| 49 | # CONFIG_GENERIC_TBSYNC is not set | 50 | # CONFIG_GENERIC_TBSYNC is not set |
| 50 | CONFIG_AUDIT_ARCH=y | 51 | CONFIG_AUDIT_ARCH=y |
| 51 | CONFIG_GENERIC_BUG=y | 52 | CONFIG_GENERIC_BUG=y |
| 53 | CONFIG_DTC=y | ||
| 52 | # CONFIG_DEFAULT_UIMAGE is not set | 54 | # CONFIG_DEFAULT_UIMAGE is not set |
| 53 | CONFIG_PPC_DCR_NATIVE=y | 55 | CONFIG_PPC_DCR_NATIVE=y |
| 54 | # CONFIG_PPC_DCR_MMIO is not set | 56 | # CONFIG_PPC_DCR_MMIO is not set |
| 55 | CONFIG_PPC_DCR=y | 57 | CONFIG_PPC_DCR=y |
| 58 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y | ||
| 56 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 59 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 57 | 60 | ||
| 58 | # | 61 | # |
| @@ -67,9 +70,19 @@ CONFIG_SWAP=y | |||
| 67 | CONFIG_SYSVIPC=y | 70 | CONFIG_SYSVIPC=y |
| 68 | CONFIG_SYSVIPC_SYSCTL=y | 71 | CONFIG_SYSVIPC_SYSCTL=y |
| 69 | CONFIG_POSIX_MQUEUE=y | 72 | CONFIG_POSIX_MQUEUE=y |
| 73 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 70 | # CONFIG_BSD_PROCESS_ACCT is not set | 74 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 71 | # CONFIG_TASKSTATS is not set | 75 | # CONFIG_TASKSTATS is not set |
| 72 | # CONFIG_AUDIT is not set | 76 | # CONFIG_AUDIT is not set |
| 77 | |||
| 78 | # | ||
| 79 | # RCU Subsystem | ||
| 80 | # | ||
| 81 | CONFIG_CLASSIC_RCU=y | ||
| 82 | # CONFIG_TREE_RCU is not set | ||
| 83 | # CONFIG_PREEMPT_RCU is not set | ||
| 84 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 85 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 73 | # CONFIG_IKCONFIG is not set | 86 | # CONFIG_IKCONFIG is not set |
| 74 | CONFIG_LOG_BUF_SHIFT=14 | 87 | CONFIG_LOG_BUF_SHIFT=14 |
| 75 | CONFIG_GROUP_SCHED=y | 88 | CONFIG_GROUP_SCHED=y |
| @@ -84,22 +97,24 @@ CONFIG_SYSFS_DEPRECATED_V2=y | |||
| 84 | # CONFIG_NAMESPACES is not set | 97 | # CONFIG_NAMESPACES is not set |
| 85 | CONFIG_BLK_DEV_INITRD=y | 98 | CONFIG_BLK_DEV_INITRD=y |
| 86 | CONFIG_INITRAMFS_SOURCE="" | 99 | CONFIG_INITRAMFS_SOURCE="" |
| 100 | CONFIG_RD_GZIP=y | ||
| 101 | # CONFIG_RD_BZIP2 is not set | ||
| 102 | # CONFIG_RD_LZMA is not set | ||
| 87 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 103 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 88 | CONFIG_SYSCTL=y | 104 | CONFIG_SYSCTL=y |
| 105 | CONFIG_ANON_INODES=y | ||
| 89 | CONFIG_EMBEDDED=y | 106 | CONFIG_EMBEDDED=y |
| 90 | CONFIG_SYSCTL_SYSCALL=y | 107 | CONFIG_SYSCTL_SYSCALL=y |
| 91 | CONFIG_KALLSYMS=y | 108 | CONFIG_KALLSYMS=y |
| 92 | CONFIG_KALLSYMS_ALL=y | 109 | CONFIG_KALLSYMS_ALL=y |
| 93 | CONFIG_KALLSYMS_STRIP_GENERATED=y | ||
| 94 | CONFIG_KALLSYMS_EXTRA_PASS=y | 110 | CONFIG_KALLSYMS_EXTRA_PASS=y |
| 111 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 95 | CONFIG_HOTPLUG=y | 112 | CONFIG_HOTPLUG=y |
| 96 | CONFIG_PRINTK=y | 113 | CONFIG_PRINTK=y |
| 97 | CONFIG_BUG=y | 114 | CONFIG_BUG=y |
| 98 | CONFIG_ELF_CORE=y | 115 | CONFIG_ELF_CORE=y |
| 99 | CONFIG_COMPAT_BRK=y | ||
| 100 | CONFIG_BASE_FULL=y | 116 | CONFIG_BASE_FULL=y |
| 101 | CONFIG_FUTEX=y | 117 | CONFIG_FUTEX=y |
| 102 | CONFIG_ANON_INODES=y | ||
| 103 | CONFIG_EPOLL=y | 118 | CONFIG_EPOLL=y |
| 104 | CONFIG_SIGNALFD=y | 119 | CONFIG_SIGNALFD=y |
| 105 | CONFIG_TIMERFD=y | 120 | CONFIG_TIMERFD=y |
| @@ -109,10 +124,12 @@ CONFIG_AIO=y | |||
| 109 | CONFIG_VM_EVENT_COUNTERS=y | 124 | CONFIG_VM_EVENT_COUNTERS=y |
| 110 | CONFIG_PCI_QUIRKS=y | 125 | CONFIG_PCI_QUIRKS=y |
| 111 | CONFIG_SLUB_DEBUG=y | 126 | CONFIG_SLUB_DEBUG=y |
| 127 | CONFIG_COMPAT_BRK=y | ||
| 112 | # CONFIG_SLAB is not set | 128 | # CONFIG_SLAB is not set |
| 113 | CONFIG_SLUB=y | 129 | CONFIG_SLUB=y |
| 114 | # CONFIG_SLOB is not set | 130 | # CONFIG_SLOB is not set |
| 115 | # CONFIG_PROFILING is not set | 131 | # CONFIG_PROFILING is not set |
| 132 | # CONFIG_MARKERS is not set | ||
| 116 | CONFIG_HAVE_OPROFILE=y | 133 | CONFIG_HAVE_OPROFILE=y |
| 117 | # CONFIG_KPROBES is not set | 134 | # CONFIG_KPROBES is not set |
| 118 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | 135 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y |
| @@ -120,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y | |||
| 120 | CONFIG_HAVE_KPROBES=y | 137 | CONFIG_HAVE_KPROBES=y |
| 121 | CONFIG_HAVE_KRETPROBES=y | 138 | CONFIG_HAVE_KRETPROBES=y |
| 122 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 139 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 140 | # CONFIG_SLOW_WORK is not set | ||
| 123 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 141 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 124 | CONFIG_SLABINFO=y | 142 | CONFIG_SLABINFO=y |
| 125 | CONFIG_RT_MUTEXES=y | 143 | CONFIG_RT_MUTEXES=y |
| @@ -132,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y | |||
| 132 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 150 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 133 | CONFIG_BLOCK=y | 151 | CONFIG_BLOCK=y |
| 134 | CONFIG_LBD=y | 152 | CONFIG_LBD=y |
| 135 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 136 | # CONFIG_BLK_DEV_BSG is not set | 153 | # CONFIG_BLK_DEV_BSG is not set |
| 137 | # CONFIG_BLK_DEV_INTEGRITY is not set | 154 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 138 | 155 | ||
| @@ -148,11 +165,6 @@ CONFIG_DEFAULT_AS=y | |||
| 148 | # CONFIG_DEFAULT_CFQ is not set | 165 | # CONFIG_DEFAULT_CFQ is not set |
| 149 | # CONFIG_DEFAULT_NOOP is not set | 166 | # CONFIG_DEFAULT_NOOP is not set |
| 150 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 167 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 151 | CONFIG_CLASSIC_RCU=y | ||
| 152 | # CONFIG_TREE_RCU is not set | ||
| 153 | # CONFIG_PREEMPT_RCU is not set | ||
| 154 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 155 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 156 | # CONFIG_FREEZER is not set | 168 | # CONFIG_FREEZER is not set |
| 157 | CONFIG_PPC4xx_PCI_EXPRESS=y | 169 | CONFIG_PPC4xx_PCI_EXPRESS=y |
| 158 | 170 | ||
| @@ -170,7 +182,7 @@ CONFIG_PPC4xx_PCI_EXPRESS=y | |||
| 170 | CONFIG_MAKALU=y | 182 | CONFIG_MAKALU=y |
| 171 | # CONFIG_WALNUT is not set | 183 | # CONFIG_WALNUT is not set |
| 172 | # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set | 184 | # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set |
| 173 | # CONFIG_PPC40x_SIMPLE is not set | 185 | CONFIG_PPC40x_SIMPLE=y |
| 174 | CONFIG_405EX=y | 186 | CONFIG_405EX=y |
| 175 | # CONFIG_IPIC is not set | 187 | # CONFIG_IPIC is not set |
| 176 | # CONFIG_MPIC is not set | 188 | # CONFIG_MPIC is not set |
| @@ -228,9 +240,12 @@ CONFIG_ZONE_DMA_FLAG=1 | |||
| 228 | CONFIG_BOUNCE=y | 240 | CONFIG_BOUNCE=y |
| 229 | CONFIG_VIRT_TO_BUS=y | 241 | CONFIG_VIRT_TO_BUS=y |
| 230 | CONFIG_UNEVICTABLE_LRU=y | 242 | CONFIG_UNEVICTABLE_LRU=y |
| 243 | CONFIG_HAVE_MLOCK=y | ||
| 244 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 231 | CONFIG_PPC_4K_PAGES=y | 245 | CONFIG_PPC_4K_PAGES=y |
| 232 | # CONFIG_PPC_16K_PAGES is not set | 246 | # CONFIG_PPC_16K_PAGES is not set |
| 233 | # CONFIG_PPC_64K_PAGES is not set | 247 | # CONFIG_PPC_64K_PAGES is not set |
| 248 | # CONFIG_PPC_256K_PAGES is not set | ||
| 234 | CONFIG_FORCE_MAX_ZONEORDER=11 | 249 | CONFIG_FORCE_MAX_ZONEORDER=11 |
| 235 | CONFIG_PROC_DEVICETREE=y | 250 | CONFIG_PROC_DEVICETREE=y |
| 236 | # CONFIG_CMDLINE_BOOL is not set | 251 | # CONFIG_CMDLINE_BOOL is not set |
| @@ -252,9 +267,10 @@ CONFIG_PCI_SYSCALL=y | |||
| 252 | # CONFIG_PCIEPORTBUS is not set | 267 | # CONFIG_PCIEPORTBUS is not set |
| 253 | CONFIG_ARCH_SUPPORTS_MSI=y | 268 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 254 | # CONFIG_PCI_MSI is not set | 269 | # CONFIG_PCI_MSI is not set |
| 255 | CONFIG_PCI_LEGACY=y | 270 | # CONFIG_PCI_LEGACY is not set |
| 256 | # CONFIG_PCI_DEBUG is not set | 271 | # CONFIG_PCI_DEBUG is not set |
| 257 | # CONFIG_PCI_STUB is not set | 272 | # CONFIG_PCI_STUB is not set |
| 273 | # CONFIG_PCI_IOV is not set | ||
| 258 | # CONFIG_PCCARD is not set | 274 | # CONFIG_PCCARD is not set |
| 259 | # CONFIG_HOTPLUG_PCI is not set | 275 | # CONFIG_HOTPLUG_PCI is not set |
| 260 | # CONFIG_HAS_RAPIDIO is not set | 276 | # CONFIG_HAS_RAPIDIO is not set |
| @@ -272,14 +288,12 @@ CONFIG_PAGE_OFFSET=0xc0000000 | |||
| 272 | CONFIG_KERNEL_START=0xc0000000 | 288 | CONFIG_KERNEL_START=0xc0000000 |
| 273 | CONFIG_PHYSICAL_START=0x00000000 | 289 | CONFIG_PHYSICAL_START=0x00000000 |
| 274 | CONFIG_TASK_SIZE=0xc0000000 | 290 | CONFIG_TASK_SIZE=0xc0000000 |
| 275 | CONFIG_CONSISTENT_START=0xff100000 | ||
| 276 | CONFIG_CONSISTENT_SIZE=0x00200000 | 291 | CONFIG_CONSISTENT_SIZE=0x00200000 |
| 277 | CONFIG_NET=y | 292 | CONFIG_NET=y |
| 278 | 293 | ||
| 279 | # | 294 | # |
| 280 | # Networking options | 295 | # Networking options |
| 281 | # | 296 | # |
| 282 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 283 | CONFIG_PACKET=y | 297 | CONFIG_PACKET=y |
| 284 | # CONFIG_PACKET_MMAP is not set | 298 | # CONFIG_PACKET_MMAP is not set |
| 285 | CONFIG_UNIX=y | 299 | CONFIG_UNIX=y |
| @@ -329,6 +343,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 329 | # CONFIG_LAPB is not set | 343 | # CONFIG_LAPB is not set |
| 330 | # CONFIG_ECONET is not set | 344 | # CONFIG_ECONET is not set |
| 331 | # CONFIG_WAN_ROUTER is not set | 345 | # CONFIG_WAN_ROUTER is not set |
| 346 | # CONFIG_PHONET is not set | ||
| 332 | # CONFIG_NET_SCHED is not set | 347 | # CONFIG_NET_SCHED is not set |
| 333 | # CONFIG_DCB is not set | 348 | # CONFIG_DCB is not set |
| 334 | 349 | ||
| @@ -341,7 +356,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 341 | # CONFIG_IRDA is not set | 356 | # CONFIG_IRDA is not set |
| 342 | # CONFIG_BT is not set | 357 | # CONFIG_BT is not set |
| 343 | # CONFIG_AF_RXRPC is not set | 358 | # CONFIG_AF_RXRPC is not set |
| 344 | # CONFIG_PHONET is not set | ||
| 345 | # CONFIG_WIRELESS is not set | 359 | # CONFIG_WIRELESS is not set |
| 346 | # CONFIG_WIMAX is not set | 360 | # CONFIG_WIMAX is not set |
| 347 | # CONFIG_RFKILL is not set | 361 | # CONFIG_RFKILL is not set |
| @@ -445,7 +459,6 @@ CONFIG_MTD_PHYSMAP_OF=y | |||
| 445 | # LPDDR flash memory drivers | 459 | # LPDDR flash memory drivers |
| 446 | # | 460 | # |
| 447 | # CONFIG_MTD_LPDDR is not set | 461 | # CONFIG_MTD_LPDDR is not set |
| 448 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 449 | 462 | ||
| 450 | # | 463 | # |
| 451 | # UBI - Unsorted block images | 464 | # UBI - Unsorted block images |
| @@ -498,6 +511,7 @@ CONFIG_HAVE_IDE=y | |||
| 498 | # CONFIG_I2O is not set | 511 | # CONFIG_I2O is not set |
| 499 | # CONFIG_MACINTOSH_DRIVERS is not set | 512 | # CONFIG_MACINTOSH_DRIVERS is not set |
| 500 | CONFIG_NETDEVICES=y | 513 | CONFIG_NETDEVICES=y |
| 514 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 501 | # CONFIG_DUMMY is not set | 515 | # CONFIG_DUMMY is not set |
| 502 | # CONFIG_BONDING is not set | 516 | # CONFIG_BONDING is not set |
| 503 | # CONFIG_MACVLAN is not set | 517 | # CONFIG_MACVLAN is not set |
| @@ -512,6 +526,8 @@ CONFIG_NET_ETHERNET=y | |||
| 512 | # CONFIG_SUNGEM is not set | 526 | # CONFIG_SUNGEM is not set |
| 513 | # CONFIG_CASSINI is not set | 527 | # CONFIG_CASSINI is not set |
| 514 | # CONFIG_NET_VENDOR_3COM is not set | 528 | # CONFIG_NET_VENDOR_3COM is not set |
| 529 | # CONFIG_ETHOC is not set | ||
| 530 | # CONFIG_DNET is not set | ||
| 515 | # CONFIG_NET_TULIP is not set | 531 | # CONFIG_NET_TULIP is not set |
| 516 | # CONFIG_HP100 is not set | 532 | # CONFIG_HP100 is not set |
| 517 | CONFIG_IBM_NEW_EMAC=y | 533 | CONFIG_IBM_NEW_EMAC=y |
| @@ -540,7 +556,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y | |||
| 540 | # | 556 | # |
| 541 | # CONFIG_WLAN_PRE80211 is not set | 557 | # CONFIG_WLAN_PRE80211 is not set |
| 542 | # CONFIG_WLAN_80211 is not set | 558 | # CONFIG_WLAN_80211 is not set |
| 543 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 544 | 559 | ||
| 545 | # | 560 | # |
| 546 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 561 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -678,6 +693,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 678 | # CONFIG_EDAC is not set | 693 | # CONFIG_EDAC is not set |
| 679 | # CONFIG_RTC_CLASS is not set | 694 | # CONFIG_RTC_CLASS is not set |
| 680 | # CONFIG_DMADEVICES is not set | 695 | # CONFIG_DMADEVICES is not set |
| 696 | # CONFIG_AUXDISPLAY is not set | ||
| 681 | # CONFIG_UIO is not set | 697 | # CONFIG_UIO is not set |
| 682 | # CONFIG_STAGING is not set | 698 | # CONFIG_STAGING is not set |
| 683 | 699 | ||
| @@ -706,6 +722,11 @@ CONFIG_INOTIFY_USER=y | |||
| 706 | # CONFIG_FUSE_FS is not set | 722 | # CONFIG_FUSE_FS is not set |
| 707 | 723 | ||
| 708 | # | 724 | # |
| 725 | # Caches | ||
| 726 | # | ||
| 727 | # CONFIG_FSCACHE is not set | ||
| 728 | |||
| 729 | # | ||
| 709 | # CD-ROM/DVD Filesystems | 730 | # CD-ROM/DVD Filesystems |
| 710 | # | 731 | # |
| 711 | # CONFIG_ISO9660_FS is not set | 732 | # CONFIG_ISO9660_FS is not set |
| @@ -749,6 +770,7 @@ CONFIG_CRAMFS=y | |||
| 749 | # CONFIG_ROMFS_FS is not set | 770 | # CONFIG_ROMFS_FS is not set |
| 750 | # CONFIG_SYSV_FS is not set | 771 | # CONFIG_SYSV_FS is not set |
| 751 | # CONFIG_UFS_FS is not set | 772 | # CONFIG_UFS_FS is not set |
| 773 | # CONFIG_NILFS2_FS is not set | ||
| 752 | CONFIG_NETWORK_FILESYSTEMS=y | 774 | CONFIG_NETWORK_FILESYSTEMS=y |
| 753 | CONFIG_NFS_FS=y | 775 | CONFIG_NFS_FS=y |
| 754 | CONFIG_NFS_V3=y | 776 | CONFIG_NFS_V3=y |
| @@ -760,7 +782,6 @@ CONFIG_LOCKD=y | |||
| 760 | CONFIG_LOCKD_V4=y | 782 | CONFIG_LOCKD_V4=y |
| 761 | CONFIG_NFS_COMMON=y | 783 | CONFIG_NFS_COMMON=y |
| 762 | CONFIG_SUNRPC=y | 784 | CONFIG_SUNRPC=y |
| 763 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 764 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 785 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 765 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 786 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 766 | # CONFIG_SMB_FS is not set | 787 | # CONFIG_SMB_FS is not set |
| @@ -776,6 +797,7 @@ CONFIG_SUNRPC=y | |||
| 776 | CONFIG_MSDOS_PARTITION=y | 797 | CONFIG_MSDOS_PARTITION=y |
| 777 | # CONFIG_NLS is not set | 798 | # CONFIG_NLS is not set |
| 778 | # CONFIG_DLM is not set | 799 | # CONFIG_DLM is not set |
| 800 | # CONFIG_BINARY_PRINTF is not set | ||
| 779 | 801 | ||
| 780 | # | 802 | # |
| 781 | # Library routines | 803 | # Library routines |
| @@ -790,11 +812,12 @@ CONFIG_CRC32=y | |||
| 790 | # CONFIG_CRC7 is not set | 812 | # CONFIG_CRC7 is not set |
| 791 | # CONFIG_LIBCRC32C is not set | 813 | # CONFIG_LIBCRC32C is not set |
| 792 | CONFIG_ZLIB_INFLATE=y | 814 | CONFIG_ZLIB_INFLATE=y |
| 793 | CONFIG_PLIST=y | 815 | CONFIG_DECOMPRESS_GZIP=y |
| 794 | CONFIG_HAS_IOMEM=y | 816 | CONFIG_HAS_IOMEM=y |
| 795 | CONFIG_HAS_IOPORT=y | 817 | CONFIG_HAS_IOPORT=y |
| 796 | CONFIG_HAS_DMA=y | 818 | CONFIG_HAS_DMA=y |
| 797 | CONFIG_HAVE_LMB=y | 819 | CONFIG_HAVE_LMB=y |
| 820 | CONFIG_NLATTR=y | ||
| 798 | 821 | ||
| 799 | # | 822 | # |
| 800 | # Kernel hacking | 823 | # Kernel hacking |
| @@ -812,6 +835,9 @@ CONFIG_DEBUG_KERNEL=y | |||
| 812 | CONFIG_DETECT_SOFTLOCKUP=y | 835 | CONFIG_DETECT_SOFTLOCKUP=y |
| 813 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | 836 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set |
| 814 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | 837 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 |
| 838 | CONFIG_DETECT_HUNG_TASK=y | ||
| 839 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 840 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 815 | CONFIG_SCHED_DEBUG=y | 841 | CONFIG_SCHED_DEBUG=y |
| 816 | # CONFIG_SCHEDSTATS is not set | 842 | # CONFIG_SCHEDSTATS is not set |
| 817 | # CONFIG_TIMER_STATS is not set | 843 | # CONFIG_TIMER_STATS is not set |
| @@ -841,9 +867,12 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 841 | # CONFIG_FAULT_INJECTION is not set | 867 | # CONFIG_FAULT_INJECTION is not set |
| 842 | # CONFIG_LATENCYTOP is not set | 868 | # CONFIG_LATENCYTOP is not set |
| 843 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 869 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 870 | # CONFIG_DEBUG_PAGEALLOC is not set | ||
| 844 | CONFIG_HAVE_FUNCTION_TRACER=y | 871 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 872 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | ||
| 845 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 873 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 846 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | 874 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 875 | CONFIG_TRACING_SUPPORT=y | ||
| 847 | 876 | ||
| 848 | # | 877 | # |
| 849 | # Tracers | 878 | # Tracers |
| @@ -851,17 +880,21 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |||
| 851 | # CONFIG_FUNCTION_TRACER is not set | 880 | # CONFIG_FUNCTION_TRACER is not set |
| 852 | # CONFIG_SCHED_TRACER is not set | 881 | # CONFIG_SCHED_TRACER is not set |
| 853 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 882 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 883 | # CONFIG_EVENT_TRACER is not set | ||
| 854 | # CONFIG_BOOT_TRACER is not set | 884 | # CONFIG_BOOT_TRACER is not set |
| 855 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 885 | # CONFIG_TRACE_BRANCH_PROFILING is not set |
| 856 | # CONFIG_STACK_TRACER is not set | 886 | # CONFIG_STACK_TRACER is not set |
| 857 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 887 | # CONFIG_KMEMTRACE is not set |
| 888 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 889 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 890 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 858 | # CONFIG_SAMPLES is not set | 891 | # CONFIG_SAMPLES is not set |
| 859 | CONFIG_HAVE_ARCH_KGDB=y | 892 | CONFIG_HAVE_ARCH_KGDB=y |
| 860 | # CONFIG_KGDB is not set | 893 | # CONFIG_KGDB is not set |
| 861 | CONFIG_PRINT_STACK_DEPTH=64 | 894 | CONFIG_PRINT_STACK_DEPTH=64 |
| 862 | # CONFIG_DEBUG_STACKOVERFLOW is not set | 895 | # CONFIG_DEBUG_STACKOVERFLOW is not set |
| 863 | # CONFIG_DEBUG_STACK_USAGE is not set | 896 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 864 | # CONFIG_DEBUG_PAGEALLOC is not set | 897 | # CONFIG_PPC_EMULATED_STATS is not set |
| 865 | # CONFIG_CODE_PATCHING_SELFTEST is not set | 898 | # CONFIG_CODE_PATCHING_SELFTEST is not set |
| 866 | # CONFIG_FTR_FIXUP_SELFTEST is not set | 899 | # CONFIG_FTR_FIXUP_SELFTEST is not set |
| 867 | # CONFIG_MSI_BITMAP_SELFTEST is not set | 900 | # CONFIG_MSI_BITMAP_SELFTEST is not set |
| @@ -892,10 +925,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y | |||
| 892 | CONFIG_CRYPTO_HASH=y | 925 | CONFIG_CRYPTO_HASH=y |
| 893 | CONFIG_CRYPTO_HASH2=y | 926 | CONFIG_CRYPTO_HASH2=y |
| 894 | CONFIG_CRYPTO_RNG2=y | 927 | CONFIG_CRYPTO_RNG2=y |
| 928 | CONFIG_CRYPTO_PCOMP=y | ||
| 895 | CONFIG_CRYPTO_MANAGER=y | 929 | CONFIG_CRYPTO_MANAGER=y |
| 896 | CONFIG_CRYPTO_MANAGER2=y | 930 | CONFIG_CRYPTO_MANAGER2=y |
| 897 | # CONFIG_CRYPTO_GF128MUL is not set | 931 | # CONFIG_CRYPTO_GF128MUL is not set |
| 898 | # CONFIG_CRYPTO_NULL is not set | 932 | # CONFIG_CRYPTO_NULL is not set |
| 933 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 899 | # CONFIG_CRYPTO_CRYPTD is not set | 934 | # CONFIG_CRYPTO_CRYPTD is not set |
| 900 | # CONFIG_CRYPTO_AUTHENC is not set | 935 | # CONFIG_CRYPTO_AUTHENC is not set |
| 901 | # CONFIG_CRYPTO_TEST is not set | 936 | # CONFIG_CRYPTO_TEST is not set |
| @@ -964,6 +999,7 @@ CONFIG_CRYPTO_DES=y | |||
| 964 | # Compression | 999 | # Compression |
| 965 | # | 1000 | # |
| 966 | # CONFIG_CRYPTO_DEFLATE is not set | 1001 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1002 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 967 | # CONFIG_CRYPTO_LZO is not set | 1003 | # CONFIG_CRYPTO_LZO is not set |
| 968 | 1004 | ||
| 969 | # | 1005 | # |
| @@ -972,5 +1008,6 @@ CONFIG_CRYPTO_DES=y | |||
| 972 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 1008 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 973 | CONFIG_CRYPTO_HW=y | 1009 | CONFIG_CRYPTO_HW=y |
| 974 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | 1010 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set |
| 1011 | # CONFIG_CRYPTO_DEV_PPC4XX is not set | ||
| 975 | # CONFIG_PPC_CLOCK is not set | 1012 | # CONFIG_PPC_CLOCK is not set |
| 976 | # CONFIG_VIRTUALIZATION is not set | 1013 | # CONFIG_VIRTUALIZATION is not set |
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig index f5698f962e58..416e79ac0711 100644 --- a/arch/powerpc/configs/40x/virtex_defconfig +++ b/arch/powerpc/configs/40x/virtex_defconfig | |||
| @@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 258 | # CONFIG_PCIEPORTBUS is not set | 258 | # CONFIG_PCIEPORTBUS is not set |
| 259 | CONFIG_ARCH_SUPPORTS_MSI=y | 259 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 260 | # CONFIG_PCI_MSI is not set | 260 | # CONFIG_PCI_MSI is not set |
| 261 | CONFIG_PCI_LEGACY=y | 261 | # CONFIG_PCI_LEGACY is not set |
| 262 | # CONFIG_PCI_DEBUG is not set | 262 | # CONFIG_PCI_DEBUG is not set |
| 263 | # CONFIG_PCI_STUB is not set | 263 | # CONFIG_PCI_STUB is not set |
| 264 | # CONFIG_PCCARD is not set | 264 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig index 1d72b0ac3f25..f7fd32c09424 100644 --- a/arch/powerpc/configs/44x/arches_defconfig +++ b/arch/powerpc/configs/44x/arches_defconfig | |||
| @@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 258 | # CONFIG_PCIEPORTBUS is not set | 258 | # CONFIG_PCIEPORTBUS is not set |
| 259 | CONFIG_ARCH_SUPPORTS_MSI=y | 259 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 260 | # CONFIG_PCI_MSI is not set | 260 | # CONFIG_PCI_MSI is not set |
| 261 | CONFIG_PCI_LEGACY=y | 261 | # CONFIG_PCI_LEGACY is not set |
| 262 | # CONFIG_PCI_DEBUG is not set | 262 | # CONFIG_PCI_DEBUG is not set |
| 263 | # CONFIG_PCI_STUB is not set | 263 | # CONFIG_PCI_STUB is not set |
| 264 | # CONFIG_PCCARD is not set | 264 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig index 959bdc43a491..e57f1e4c1795 100644 --- a/arch/powerpc/configs/44x/bamboo_defconfig +++ b/arch/powerpc/configs/44x/bamboo_defconfig | |||
| @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 262 | # CONFIG_PCIEPORTBUS is not set | 262 | # CONFIG_PCIEPORTBUS is not set |
| 263 | CONFIG_ARCH_SUPPORTS_MSI=y | 263 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 264 | # CONFIG_PCI_MSI is not set | 264 | # CONFIG_PCI_MSI is not set |
| 265 | CONFIG_PCI_LEGACY=y | 265 | # CONFIG_PCI_LEGACY is not set |
| 266 | # CONFIG_PCI_DEBUG is not set | 266 | # CONFIG_PCI_DEBUG is not set |
| 267 | # CONFIG_PCI_STUB is not set | 267 | # CONFIG_PCI_STUB is not set |
| 268 | # CONFIG_PCCARD is not set | 268 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig index f9a08ee49b96..5e85412eb9fa 100644 --- a/arch/powerpc/configs/44x/canyonlands_defconfig +++ b/arch/powerpc/configs/44x/canyonlands_defconfig | |||
| @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 262 | # CONFIG_PCIEPORTBUS is not set | 262 | # CONFIG_PCIEPORTBUS is not set |
| 263 | CONFIG_ARCH_SUPPORTS_MSI=y | 263 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 264 | # CONFIG_PCI_MSI is not set | 264 | # CONFIG_PCI_MSI is not set |
| 265 | CONFIG_PCI_LEGACY=y | 265 | # CONFIG_PCI_LEGACY is not set |
| 266 | # CONFIG_PCI_DEBUG is not set | 266 | # CONFIG_PCI_DEBUG is not set |
| 267 | # CONFIG_PCI_STUB is not set | 267 | # CONFIG_PCI_STUB is not set |
| 268 | # CONFIG_PCCARD is not set | 268 | # CONFIG_PCCARD is not set |
| @@ -716,7 +716,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 716 | # | 716 | # |
| 717 | # Multimedia drivers | 717 | # Multimedia drivers |
| 718 | # | 718 | # |
| 719 | CONFIG_DAB=y | 719 | # CONFIG_DAB is not set |
| 720 | # CONFIG_USB_DABUSB is not set | 720 | # CONFIG_USB_DABUSB is not set |
| 721 | 721 | ||
| 722 | # | 722 | # |
| @@ -725,7 +725,7 @@ CONFIG_DAB=y | |||
| 725 | # CONFIG_AGP is not set | 725 | # CONFIG_AGP is not set |
| 726 | # CONFIG_DRM is not set | 726 | # CONFIG_DRM is not set |
| 727 | # CONFIG_VGASTATE is not set | 727 | # CONFIG_VGASTATE is not set |
| 728 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 728 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set |
| 729 | # CONFIG_FB is not set | 729 | # CONFIG_FB is not set |
| 730 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 730 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 731 | 731 | ||
diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig index be64aa644d15..b652f7dcab5a 100644 --- a/arch/powerpc/configs/44x/ebony_defconfig +++ b/arch/powerpc/configs/44x/ebony_defconfig | |||
| @@ -261,7 +261,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 261 | # CONFIG_PCIEPORTBUS is not set | 261 | # CONFIG_PCIEPORTBUS is not set |
| 262 | CONFIG_ARCH_SUPPORTS_MSI=y | 262 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 263 | # CONFIG_PCI_MSI is not set | 263 | # CONFIG_PCI_MSI is not set |
| 264 | CONFIG_PCI_LEGACY=y | 264 | # CONFIG_PCI_LEGACY is not set |
| 265 | # CONFIG_PCI_DEBUG is not set | 265 | # CONFIG_PCI_DEBUG is not set |
| 266 | # CONFIG_PCI_STUB is not set | 266 | # CONFIG_PCI_STUB is not set |
| 267 | # CONFIG_PCCARD is not set | 267 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig index f67250b24ec5..c23a4ef13e45 100644 --- a/arch/powerpc/configs/44x/katmai_defconfig +++ b/arch/powerpc/configs/44x/katmai_defconfig | |||
| @@ -256,7 +256,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 256 | # CONFIG_PCIEPORTBUS is not set | 256 | # CONFIG_PCIEPORTBUS is not set |
| 257 | CONFIG_ARCH_SUPPORTS_MSI=y | 257 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 258 | # CONFIG_PCI_MSI is not set | 258 | # CONFIG_PCI_MSI is not set |
| 259 | CONFIG_PCI_LEGACY=y | 259 | # CONFIG_PCI_LEGACY is not set |
| 260 | # CONFIG_PCI_DEBUG is not set | 260 | # CONFIG_PCI_DEBUG is not set |
| 261 | # CONFIG_PCI_STUB is not set | 261 | # CONFIG_PCI_STUB is not set |
| 262 | # CONFIG_PCCARD is not set | 262 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig index 9348c12bd7a6..b25fad1343dc 100644 --- a/arch/powerpc/configs/44x/rainier_defconfig +++ b/arch/powerpc/configs/44x/rainier_defconfig | |||
| @@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 260 | # CONFIG_PCIEPORTBUS is not set | 260 | # CONFIG_PCIEPORTBUS is not set |
| 261 | CONFIG_ARCH_SUPPORTS_MSI=y | 261 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 262 | # CONFIG_PCI_MSI is not set | 262 | # CONFIG_PCI_MSI is not set |
| 263 | CONFIG_PCI_LEGACY=y | 263 | # CONFIG_PCI_LEGACY is not set |
| 264 | # CONFIG_PCI_DEBUG is not set | 264 | # CONFIG_PCI_DEBUG is not set |
| 265 | # CONFIG_PCI_STUB is not set | 265 | # CONFIG_PCI_STUB is not set |
| 266 | # CONFIG_PCCARD is not set | 266 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/redwood_defconfig b/arch/powerpc/configs/44x/redwood_defconfig index e665433762ba..ed31d4f17b5a 100644 --- a/arch/powerpc/configs/44x/redwood_defconfig +++ b/arch/powerpc/configs/44x/redwood_defconfig | |||
| @@ -265,7 +265,7 @@ CONFIG_PCIEAER=y | |||
| 265 | # CONFIG_PCIEASPM is not set | 265 | # CONFIG_PCIEASPM is not set |
| 266 | CONFIG_ARCH_SUPPORTS_MSI=y | 266 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 267 | # CONFIG_PCI_MSI is not set | 267 | # CONFIG_PCI_MSI is not set |
| 268 | CONFIG_PCI_LEGACY=y | 268 | # CONFIG_PCI_LEGACY is not set |
| 269 | # CONFIG_PCI_DEBUG is not set | 269 | # CONFIG_PCI_DEBUG is not set |
| 270 | # CONFIG_PCI_STUB is not set | 270 | # CONFIG_PCI_STUB is not set |
| 271 | # CONFIG_PCCARD is not set | 271 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/sam440ep_defconfig b/arch/powerpc/configs/44x/sam440ep_defconfig index 70d5c3fa3283..e14e89a5e06b 100644 --- a/arch/powerpc/configs/44x/sam440ep_defconfig +++ b/arch/powerpc/configs/44x/sam440ep_defconfig | |||
| @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 262 | # CONFIG_PCIEPORTBUS is not set | 262 | # CONFIG_PCIEPORTBUS is not set |
| 263 | CONFIG_ARCH_SUPPORTS_MSI=y | 263 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 264 | # CONFIG_PCI_MSI is not set | 264 | # CONFIG_PCI_MSI is not set |
| 265 | CONFIG_PCI_LEGACY=y | 265 | # CONFIG_PCI_LEGACY is not set |
| 266 | # CONFIG_PCI_STUB is not set | 266 | # CONFIG_PCI_STUB is not set |
| 267 | # CONFIG_PCCARD is not set | 267 | # CONFIG_PCCARD is not set |
| 268 | # CONFIG_HOTPLUG_PCI is not set | 268 | # CONFIG_HOTPLUG_PCI is not set |
diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig index a921fe3c3711..6400aae04dda 100644 --- a/arch/powerpc/configs/44x/sequoia_defconfig +++ b/arch/powerpc/configs/44x/sequoia_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.29-rc2 | 3 | # Linux kernel version: 2.6.29 |
| 4 | # Tue Jan 20 08:22:45 2009 | 4 | # Tue Apr 7 17:04:52 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_PPC64 is not set | 6 | # CONFIG_PPC64 is not set |
| 7 | 7 | ||
| @@ -57,6 +57,7 @@ CONFIG_GENERIC_BUG=y | |||
| 57 | CONFIG_PPC_DCR_NATIVE=y | 57 | CONFIG_PPC_DCR_NATIVE=y |
| 58 | # CONFIG_PPC_DCR_MMIO is not set | 58 | # CONFIG_PPC_DCR_MMIO is not set |
| 59 | CONFIG_PPC_DCR=y | 59 | CONFIG_PPC_DCR=y |
| 60 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y | ||
| 60 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 61 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 61 | 62 | ||
| 62 | # | 63 | # |
| @@ -74,6 +75,15 @@ CONFIG_POSIX_MQUEUE=y | |||
| 74 | # CONFIG_BSD_PROCESS_ACCT is not set | 75 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 75 | # CONFIG_TASKSTATS is not set | 76 | # CONFIG_TASKSTATS is not set |
| 76 | # CONFIG_AUDIT is not set | 77 | # CONFIG_AUDIT is not set |
| 78 | |||
| 79 | # | ||
| 80 | # RCU Subsystem | ||
| 81 | # | ||
| 82 | CONFIG_CLASSIC_RCU=y | ||
| 83 | # CONFIG_TREE_RCU is not set | ||
| 84 | # CONFIG_PREEMPT_RCU is not set | ||
| 85 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 86 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 77 | # CONFIG_IKCONFIG is not set | 87 | # CONFIG_IKCONFIG is not set |
| 78 | CONFIG_LOG_BUF_SHIFT=14 | 88 | CONFIG_LOG_BUF_SHIFT=14 |
| 79 | CONFIG_GROUP_SCHED=y | 89 | CONFIG_GROUP_SCHED=y |
| @@ -88,8 +98,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y | |||
| 88 | # CONFIG_NAMESPACES is not set | 98 | # CONFIG_NAMESPACES is not set |
| 89 | CONFIG_BLK_DEV_INITRD=y | 99 | CONFIG_BLK_DEV_INITRD=y |
| 90 | CONFIG_INITRAMFS_SOURCE="" | 100 | CONFIG_INITRAMFS_SOURCE="" |
| 101 | CONFIG_RD_GZIP=y | ||
| 102 | # CONFIG_RD_BZIP2 is not set | ||
| 103 | # CONFIG_RD_LZMA is not set | ||
| 91 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 104 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 92 | CONFIG_SYSCTL=y | 105 | CONFIG_SYSCTL=y |
| 106 | CONFIG_ANON_INODES=y | ||
| 93 | CONFIG_EMBEDDED=y | 107 | CONFIG_EMBEDDED=y |
| 94 | CONFIG_SYSCTL_SYSCALL=y | 108 | CONFIG_SYSCTL_SYSCALL=y |
| 95 | CONFIG_KALLSYMS=y | 109 | CONFIG_KALLSYMS=y |
| @@ -99,10 +113,8 @@ CONFIG_HOTPLUG=y | |||
| 99 | CONFIG_PRINTK=y | 113 | CONFIG_PRINTK=y |
| 100 | CONFIG_BUG=y | 114 | CONFIG_BUG=y |
| 101 | CONFIG_ELF_CORE=y | 115 | CONFIG_ELF_CORE=y |
| 102 | CONFIG_COMPAT_BRK=y | ||
| 103 | CONFIG_BASE_FULL=y | 116 | CONFIG_BASE_FULL=y |
| 104 | CONFIG_FUTEX=y | 117 | CONFIG_FUTEX=y |
| 105 | CONFIG_ANON_INODES=y | ||
| 106 | CONFIG_EPOLL=y | 118 | CONFIG_EPOLL=y |
| 107 | CONFIG_SIGNALFD=y | 119 | CONFIG_SIGNALFD=y |
| 108 | CONFIG_TIMERFD=y | 120 | CONFIG_TIMERFD=y |
| @@ -112,10 +124,12 @@ CONFIG_AIO=y | |||
| 112 | CONFIG_VM_EVENT_COUNTERS=y | 124 | CONFIG_VM_EVENT_COUNTERS=y |
| 113 | CONFIG_PCI_QUIRKS=y | 125 | CONFIG_PCI_QUIRKS=y |
| 114 | CONFIG_SLUB_DEBUG=y | 126 | CONFIG_SLUB_DEBUG=y |
| 127 | CONFIG_COMPAT_BRK=y | ||
| 115 | # CONFIG_SLAB is not set | 128 | # CONFIG_SLAB is not set |
| 116 | CONFIG_SLUB=y | 129 | CONFIG_SLUB=y |
| 117 | # CONFIG_SLOB is not set | 130 | # CONFIG_SLOB is not set |
| 118 | # CONFIG_PROFILING is not set | 131 | # CONFIG_PROFILING is not set |
| 132 | # CONFIG_MARKERS is not set | ||
| 119 | CONFIG_HAVE_OPROFILE=y | 133 | CONFIG_HAVE_OPROFILE=y |
| 120 | # CONFIG_KPROBES is not set | 134 | # CONFIG_KPROBES is not set |
| 121 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | 135 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y |
| @@ -123,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y | |||
| 123 | CONFIG_HAVE_KPROBES=y | 137 | CONFIG_HAVE_KPROBES=y |
| 124 | CONFIG_HAVE_KRETPROBES=y | 138 | CONFIG_HAVE_KRETPROBES=y |
| 125 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 139 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 140 | # CONFIG_SLOW_WORK is not set | ||
| 126 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 141 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 127 | CONFIG_SLABINFO=y | 142 | CONFIG_SLABINFO=y |
| 128 | CONFIG_RT_MUTEXES=y | 143 | CONFIG_RT_MUTEXES=y |
| @@ -135,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y | |||
| 135 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 150 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 136 | CONFIG_BLOCK=y | 151 | CONFIG_BLOCK=y |
| 137 | CONFIG_LBD=y | 152 | CONFIG_LBD=y |
| 138 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 139 | # CONFIG_BLK_DEV_BSG is not set | 153 | # CONFIG_BLK_DEV_BSG is not set |
| 140 | # CONFIG_BLK_DEV_INTEGRITY is not set | 154 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 141 | 155 | ||
| @@ -151,11 +165,6 @@ CONFIG_DEFAULT_AS=y | |||
| 151 | # CONFIG_DEFAULT_CFQ is not set | 165 | # CONFIG_DEFAULT_CFQ is not set |
| 152 | # CONFIG_DEFAULT_NOOP is not set | 166 | # CONFIG_DEFAULT_NOOP is not set |
| 153 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 167 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 154 | CONFIG_CLASSIC_RCU=y | ||
| 155 | # CONFIG_TREE_RCU is not set | ||
| 156 | # CONFIG_PREEMPT_RCU is not set | ||
| 157 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 158 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 159 | # CONFIG_FREEZER is not set | 168 | # CONFIG_FREEZER is not set |
| 160 | # CONFIG_PPC4xx_PCI_EXPRESS is not set | 169 | # CONFIG_PPC4xx_PCI_EXPRESS is not set |
| 161 | 170 | ||
| @@ -176,6 +185,7 @@ CONFIG_SEQUOIA=y | |||
| 176 | # CONFIG_ARCHES is not set | 185 | # CONFIG_ARCHES is not set |
| 177 | # CONFIG_CANYONLANDS is not set | 186 | # CONFIG_CANYONLANDS is not set |
| 178 | # CONFIG_GLACIER is not set | 187 | # CONFIG_GLACIER is not set |
| 188 | # CONFIG_REDWOOD is not set | ||
| 179 | # CONFIG_YOSEMITE is not set | 189 | # CONFIG_YOSEMITE is not set |
| 180 | # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set | 190 | # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set |
| 181 | CONFIG_PPC44x_SIMPLE=y | 191 | CONFIG_PPC44x_SIMPLE=y |
| @@ -238,9 +248,13 @@ CONFIG_ZONE_DMA_FLAG=1 | |||
| 238 | CONFIG_BOUNCE=y | 248 | CONFIG_BOUNCE=y |
| 239 | CONFIG_VIRT_TO_BUS=y | 249 | CONFIG_VIRT_TO_BUS=y |
| 240 | CONFIG_UNEVICTABLE_LRU=y | 250 | CONFIG_UNEVICTABLE_LRU=y |
| 251 | CONFIG_HAVE_MLOCK=y | ||
| 252 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 253 | CONFIG_STDBINUTILS=y | ||
| 241 | CONFIG_PPC_4K_PAGES=y | 254 | CONFIG_PPC_4K_PAGES=y |
| 242 | # CONFIG_PPC_16K_PAGES is not set | 255 | # CONFIG_PPC_16K_PAGES is not set |
| 243 | # CONFIG_PPC_64K_PAGES is not set | 256 | # CONFIG_PPC_64K_PAGES is not set |
| 257 | # CONFIG_PPC_256K_PAGES is not set | ||
| 244 | CONFIG_FORCE_MAX_ZONEORDER=11 | 258 | CONFIG_FORCE_MAX_ZONEORDER=11 |
| 245 | CONFIG_PROC_DEVICETREE=y | 259 | CONFIG_PROC_DEVICETREE=y |
| 246 | CONFIG_CMDLINE_BOOL=y | 260 | CONFIG_CMDLINE_BOOL=y |
| @@ -262,9 +276,10 @@ CONFIG_PCI_SYSCALL=y | |||
| 262 | # CONFIG_PCIEPORTBUS is not set | 276 | # CONFIG_PCIEPORTBUS is not set |
| 263 | CONFIG_ARCH_SUPPORTS_MSI=y | 277 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 264 | # CONFIG_PCI_MSI is not set | 278 | # CONFIG_PCI_MSI is not set |
| 265 | CONFIG_PCI_LEGACY=y | 279 | # CONFIG_PCI_LEGACY is not set |
| 266 | # CONFIG_PCI_DEBUG is not set | 280 | # CONFIG_PCI_DEBUG is not set |
| 267 | # CONFIG_PCI_STUB is not set | 281 | # CONFIG_PCI_STUB is not set |
| 282 | # CONFIG_PCI_IOV is not set | ||
| 268 | # CONFIG_PCCARD is not set | 283 | # CONFIG_PCCARD is not set |
| 269 | # CONFIG_HOTPLUG_PCI is not set | 284 | # CONFIG_HOTPLUG_PCI is not set |
| 270 | # CONFIG_HAS_RAPIDIO is not set | 285 | # CONFIG_HAS_RAPIDIO is not set |
| @@ -278,18 +293,16 @@ CONFIG_PCI_LEGACY=y | |||
| 278 | # Default settings for advanced configuration options are used | 293 | # Default settings for advanced configuration options are used |
| 279 | # | 294 | # |
| 280 | CONFIG_LOWMEM_SIZE=0x30000000 | 295 | CONFIG_LOWMEM_SIZE=0x30000000 |
| 296 | CONFIG_LOWMEM_CAM_NUM=3 | ||
| 281 | CONFIG_PAGE_OFFSET=0xc0000000 | 297 | CONFIG_PAGE_OFFSET=0xc0000000 |
| 282 | CONFIG_KERNEL_START=0xc0000000 | 298 | CONFIG_KERNEL_START=0xc0000000 |
| 283 | CONFIG_PHYSICAL_START=0x00000000 | 299 | CONFIG_PHYSICAL_START=0x00000000 |
| 284 | CONFIG_TASK_SIZE=0xc0000000 | 300 | CONFIG_TASK_SIZE=0xc0000000 |
| 285 | CONFIG_CONSISTENT_START=0xff100000 | ||
| 286 | CONFIG_CONSISTENT_SIZE=0x00200000 | ||
| 287 | CONFIG_NET=y | 301 | CONFIG_NET=y |
| 288 | 302 | ||
| 289 | # | 303 | # |
| 290 | # Networking options | 304 | # Networking options |
| 291 | # | 305 | # |
| 292 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 293 | CONFIG_PACKET=y | 306 | CONFIG_PACKET=y |
| 294 | # CONFIG_PACKET_MMAP is not set | 307 | # CONFIG_PACKET_MMAP is not set |
| 295 | CONFIG_UNIX=y | 308 | CONFIG_UNIX=y |
| @@ -339,6 +352,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 339 | # CONFIG_LAPB is not set | 352 | # CONFIG_LAPB is not set |
| 340 | # CONFIG_ECONET is not set | 353 | # CONFIG_ECONET is not set |
| 341 | # CONFIG_WAN_ROUTER is not set | 354 | # CONFIG_WAN_ROUTER is not set |
| 355 | # CONFIG_PHONET is not set | ||
| 342 | # CONFIG_NET_SCHED is not set | 356 | # CONFIG_NET_SCHED is not set |
| 343 | # CONFIG_DCB is not set | 357 | # CONFIG_DCB is not set |
| 344 | 358 | ||
| @@ -351,7 +365,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 351 | # CONFIG_IRDA is not set | 365 | # CONFIG_IRDA is not set |
| 352 | # CONFIG_BT is not set | 366 | # CONFIG_BT is not set |
| 353 | # CONFIG_AF_RXRPC is not set | 367 | # CONFIG_AF_RXRPC is not set |
| 354 | # CONFIG_PHONET is not set | ||
| 355 | # CONFIG_WIRELESS is not set | 368 | # CONFIG_WIRELESS is not set |
| 356 | # CONFIG_WIMAX is not set | 369 | # CONFIG_WIMAX is not set |
| 357 | # CONFIG_RFKILL is not set | 370 | # CONFIG_RFKILL is not set |
| @@ -448,14 +461,23 @@ CONFIG_MTD_PHYSMAP_OF=y | |||
| 448 | # CONFIG_MTD_DOC2000 is not set | 461 | # CONFIG_MTD_DOC2000 is not set |
| 449 | # CONFIG_MTD_DOC2001 is not set | 462 | # CONFIG_MTD_DOC2001 is not set |
| 450 | # CONFIG_MTD_DOC2001PLUS is not set | 463 | # CONFIG_MTD_DOC2001PLUS is not set |
| 451 | # CONFIG_MTD_NAND is not set | 464 | CONFIG_MTD_NAND=y |
| 465 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 466 | CONFIG_MTD_NAND_ECC_SMC=y | ||
| 467 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 468 | CONFIG_MTD_NAND_IDS=y | ||
| 469 | CONFIG_MTD_NAND_NDFC=y | ||
| 470 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 471 | # CONFIG_MTD_NAND_CAFE is not set | ||
| 472 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 473 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 474 | # CONFIG_MTD_NAND_FSL_ELBC is not set | ||
| 452 | # CONFIG_MTD_ONENAND is not set | 475 | # CONFIG_MTD_ONENAND is not set |
| 453 | 476 | ||
| 454 | # | 477 | # |
| 455 | # LPDDR flash memory drivers | 478 | # LPDDR flash memory drivers |
| 456 | # | 479 | # |
| 457 | # CONFIG_MTD_LPDDR is not set | 480 | # CONFIG_MTD_LPDDR is not set |
| 458 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 459 | 481 | ||
| 460 | # | 482 | # |
| 461 | # UBI - Unsorted block images | 483 | # UBI - Unsorted block images |
| @@ -483,12 +505,16 @@ CONFIG_BLK_DEV_RAM_SIZE=35000 | |||
| 483 | # CONFIG_BLK_DEV_HD is not set | 505 | # CONFIG_BLK_DEV_HD is not set |
| 484 | CONFIG_MISC_DEVICES=y | 506 | CONFIG_MISC_DEVICES=y |
| 485 | # CONFIG_PHANTOM is not set | 507 | # CONFIG_PHANTOM is not set |
| 486 | # CONFIG_EEPROM_93CX6 is not set | ||
| 487 | # CONFIG_SGI_IOC4 is not set | 508 | # CONFIG_SGI_IOC4 is not set |
| 488 | # CONFIG_TIFM_CORE is not set | 509 | # CONFIG_TIFM_CORE is not set |
| 489 | # CONFIG_ENCLOSURE_SERVICES is not set | 510 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 490 | # CONFIG_HP_ILO is not set | 511 | # CONFIG_HP_ILO is not set |
| 491 | # CONFIG_C2PORT is not set | 512 | # CONFIG_C2PORT is not set |
| 513 | |||
| 514 | # | ||
| 515 | # EEPROM support | ||
| 516 | # | ||
| 517 | # CONFIG_EEPROM_93CX6 is not set | ||
| 492 | CONFIG_HAVE_IDE=y | 518 | CONFIG_HAVE_IDE=y |
| 493 | # CONFIG_IDE is not set | 519 | # CONFIG_IDE is not set |
| 494 | 520 | ||
| @@ -515,6 +541,7 @@ CONFIG_HAVE_IDE=y | |||
| 515 | # CONFIG_I2O is not set | 541 | # CONFIG_I2O is not set |
| 516 | # CONFIG_MACINTOSH_DRIVERS is not set | 542 | # CONFIG_MACINTOSH_DRIVERS is not set |
| 517 | CONFIG_NETDEVICES=y | 543 | CONFIG_NETDEVICES=y |
| 544 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 518 | # CONFIG_DUMMY is not set | 545 | # CONFIG_DUMMY is not set |
| 519 | # CONFIG_BONDING is not set | 546 | # CONFIG_BONDING is not set |
| 520 | # CONFIG_MACVLAN is not set | 547 | # CONFIG_MACVLAN is not set |
| @@ -529,6 +556,8 @@ CONFIG_NET_ETHERNET=y | |||
| 529 | # CONFIG_SUNGEM is not set | 556 | # CONFIG_SUNGEM is not set |
| 530 | # CONFIG_CASSINI is not set | 557 | # CONFIG_CASSINI is not set |
| 531 | # CONFIG_NET_VENDOR_3COM is not set | 558 | # CONFIG_NET_VENDOR_3COM is not set |
| 559 | # CONFIG_ETHOC is not set | ||
| 560 | # CONFIG_DNET is not set | ||
| 532 | # CONFIG_NET_TULIP is not set | 561 | # CONFIG_NET_TULIP is not set |
| 533 | # CONFIG_HP100 is not set | 562 | # CONFIG_HP100 is not set |
| 534 | CONFIG_IBM_NEW_EMAC=y | 563 | CONFIG_IBM_NEW_EMAC=y |
| @@ -568,6 +597,7 @@ CONFIG_NETDEV_1000=y | |||
| 568 | # CONFIG_QLA3XXX is not set | 597 | # CONFIG_QLA3XXX is not set |
| 569 | # CONFIG_ATL1 is not set | 598 | # CONFIG_ATL1 is not set |
| 570 | # CONFIG_ATL1E is not set | 599 | # CONFIG_ATL1E is not set |
| 600 | # CONFIG_ATL1C is not set | ||
| 571 | # CONFIG_JME is not set | 601 | # CONFIG_JME is not set |
| 572 | CONFIG_NETDEV_10000=y | 602 | CONFIG_NETDEV_10000=y |
| 573 | # CONFIG_CHELSIO_T1 is not set | 603 | # CONFIG_CHELSIO_T1 is not set |
| @@ -577,6 +607,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y | |||
| 577 | # CONFIG_IXGBE is not set | 607 | # CONFIG_IXGBE is not set |
| 578 | # CONFIG_IXGB is not set | 608 | # CONFIG_IXGB is not set |
| 579 | # CONFIG_S2IO is not set | 609 | # CONFIG_S2IO is not set |
| 610 | # CONFIG_VXGE is not set | ||
| 580 | # CONFIG_MYRI10GE is not set | 611 | # CONFIG_MYRI10GE is not set |
| 581 | # CONFIG_NETXEN_NIC is not set | 612 | # CONFIG_NETXEN_NIC is not set |
| 582 | # CONFIG_NIU is not set | 613 | # CONFIG_NIU is not set |
| @@ -586,6 +617,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y | |||
| 586 | # CONFIG_BNX2X is not set | 617 | # CONFIG_BNX2X is not set |
| 587 | # CONFIG_QLGE is not set | 618 | # CONFIG_QLGE is not set |
| 588 | # CONFIG_SFC is not set | 619 | # CONFIG_SFC is not set |
| 620 | # CONFIG_BE2NET is not set | ||
| 589 | # CONFIG_TR is not set | 621 | # CONFIG_TR is not set |
| 590 | 622 | ||
| 591 | # | 623 | # |
| @@ -593,7 +625,6 @@ CONFIG_CHELSIO_T3_DEPENDS=y | |||
| 593 | # | 625 | # |
| 594 | # CONFIG_WLAN_PRE80211 is not set | 626 | # CONFIG_WLAN_PRE80211 is not set |
| 595 | # CONFIG_WLAN_80211 is not set | 627 | # CONFIG_WLAN_80211 is not set |
| 596 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 597 | 628 | ||
| 598 | # | 629 | # |
| 599 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 630 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -734,7 +765,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y | |||
| 734 | # | 765 | # |
| 735 | 766 | ||
| 736 | # | 767 | # |
| 737 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | 768 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may |
| 738 | # | 769 | # |
| 739 | # CONFIG_USB_GADGET is not set | 770 | # CONFIG_USB_GADGET is not set |
| 740 | 771 | ||
| @@ -750,6 +781,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y | |||
| 750 | # CONFIG_EDAC is not set | 781 | # CONFIG_EDAC is not set |
| 751 | # CONFIG_RTC_CLASS is not set | 782 | # CONFIG_RTC_CLASS is not set |
| 752 | # CONFIG_DMADEVICES is not set | 783 | # CONFIG_DMADEVICES is not set |
| 784 | # CONFIG_AUXDISPLAY is not set | ||
| 753 | # CONFIG_UIO is not set | 785 | # CONFIG_UIO is not set |
| 754 | # CONFIG_STAGING is not set | 786 | # CONFIG_STAGING is not set |
| 755 | 787 | ||
| @@ -778,6 +810,11 @@ CONFIG_INOTIFY_USER=y | |||
| 778 | # CONFIG_FUSE_FS is not set | 810 | # CONFIG_FUSE_FS is not set |
| 779 | 811 | ||
| 780 | # | 812 | # |
| 813 | # Caches | ||
| 814 | # | ||
| 815 | # CONFIG_FSCACHE is not set | ||
| 816 | |||
| 817 | # | ||
| 781 | # CD-ROM/DVD Filesystems | 818 | # CD-ROM/DVD Filesystems |
| 782 | # | 819 | # |
| 783 | # CONFIG_ISO9660_FS is not set | 820 | # CONFIG_ISO9660_FS is not set |
| @@ -842,7 +879,6 @@ CONFIG_LOCKD=y | |||
| 842 | CONFIG_LOCKD_V4=y | 879 | CONFIG_LOCKD_V4=y |
| 843 | CONFIG_NFS_COMMON=y | 880 | CONFIG_NFS_COMMON=y |
| 844 | CONFIG_SUNRPC=y | 881 | CONFIG_SUNRPC=y |
| 845 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 846 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 882 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 847 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 883 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 848 | # CONFIG_SMB_FS is not set | 884 | # CONFIG_SMB_FS is not set |
| @@ -858,6 +894,7 @@ CONFIG_SUNRPC=y | |||
| 858 | CONFIG_MSDOS_PARTITION=y | 894 | CONFIG_MSDOS_PARTITION=y |
| 859 | # CONFIG_NLS is not set | 895 | # CONFIG_NLS is not set |
| 860 | # CONFIG_DLM is not set | 896 | # CONFIG_DLM is not set |
| 897 | # CONFIG_BINARY_PRINTF is not set | ||
| 861 | 898 | ||
| 862 | # | 899 | # |
| 863 | # Library routines | 900 | # Library routines |
| @@ -873,11 +910,12 @@ CONFIG_CRC32=y | |||
| 873 | # CONFIG_LIBCRC32C is not set | 910 | # CONFIG_LIBCRC32C is not set |
| 874 | CONFIG_ZLIB_INFLATE=y | 911 | CONFIG_ZLIB_INFLATE=y |
| 875 | CONFIG_ZLIB_DEFLATE=y | 912 | CONFIG_ZLIB_DEFLATE=y |
| 876 | CONFIG_PLIST=y | 913 | CONFIG_DECOMPRESS_GZIP=y |
| 877 | CONFIG_HAS_IOMEM=y | 914 | CONFIG_HAS_IOMEM=y |
| 878 | CONFIG_HAS_IOPORT=y | 915 | CONFIG_HAS_IOPORT=y |
| 879 | CONFIG_HAS_DMA=y | 916 | CONFIG_HAS_DMA=y |
| 880 | CONFIG_HAVE_LMB=y | 917 | CONFIG_HAVE_LMB=y |
| 918 | CONFIG_NLATTR=y | ||
| 881 | 919 | ||
| 882 | # | 920 | # |
| 883 | # Kernel hacking | 921 | # Kernel hacking |
| @@ -924,9 +962,12 @@ CONFIG_SCHED_DEBUG=y | |||
| 924 | # CONFIG_FAULT_INJECTION is not set | 962 | # CONFIG_FAULT_INJECTION is not set |
| 925 | # CONFIG_LATENCYTOP is not set | 963 | # CONFIG_LATENCYTOP is not set |
| 926 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 964 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 965 | # CONFIG_DEBUG_PAGEALLOC is not set | ||
| 927 | CONFIG_HAVE_FUNCTION_TRACER=y | 966 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 967 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | ||
| 928 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 968 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 929 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | 969 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 970 | CONFIG_TRACING_SUPPORT=y | ||
| 930 | 971 | ||
| 931 | # | 972 | # |
| 932 | # Tracers | 973 | # Tracers |
| @@ -934,17 +975,20 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | |||
| 934 | # CONFIG_FUNCTION_TRACER is not set | 975 | # CONFIG_FUNCTION_TRACER is not set |
| 935 | # CONFIG_SCHED_TRACER is not set | 976 | # CONFIG_SCHED_TRACER is not set |
| 936 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 977 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 978 | # CONFIG_EVENT_TRACER is not set | ||
| 937 | # CONFIG_BOOT_TRACER is not set | 979 | # CONFIG_BOOT_TRACER is not set |
| 938 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 980 | # CONFIG_TRACE_BRANCH_PROFILING is not set |
| 939 | # CONFIG_STACK_TRACER is not set | 981 | # CONFIG_STACK_TRACER is not set |
| 940 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 982 | # CONFIG_KMEMTRACE is not set |
| 983 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 984 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 985 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 941 | # CONFIG_SAMPLES is not set | 986 | # CONFIG_SAMPLES is not set |
| 942 | CONFIG_HAVE_ARCH_KGDB=y | 987 | CONFIG_HAVE_ARCH_KGDB=y |
| 943 | # CONFIG_KGDB is not set | 988 | # CONFIG_KGDB is not set |
| 944 | CONFIG_PRINT_STACK_DEPTH=64 | 989 | CONFIG_PRINT_STACK_DEPTH=64 |
| 945 | # CONFIG_DEBUG_STACKOVERFLOW is not set | 990 | # CONFIG_DEBUG_STACKOVERFLOW is not set |
| 946 | # CONFIG_DEBUG_STACK_USAGE is not set | 991 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 947 | # CONFIG_DEBUG_PAGEALLOC is not set | ||
| 948 | # CONFIG_CODE_PATCHING_SELFTEST is not set | 992 | # CONFIG_CODE_PATCHING_SELFTEST is not set |
| 949 | # CONFIG_FTR_FIXUP_SELFTEST is not set | 993 | # CONFIG_FTR_FIXUP_SELFTEST is not set |
| 950 | # CONFIG_MSI_BITMAP_SELFTEST is not set | 994 | # CONFIG_MSI_BITMAP_SELFTEST is not set |
| @@ -952,20 +996,7 @@ CONFIG_PRINT_STACK_DEPTH=64 | |||
| 952 | # CONFIG_IRQSTACKS is not set | 996 | # CONFIG_IRQSTACKS is not set |
| 953 | # CONFIG_VIRQ_DEBUG is not set | 997 | # CONFIG_VIRQ_DEBUG is not set |
| 954 | # CONFIG_BDI_SWITCH is not set | 998 | # CONFIG_BDI_SWITCH is not set |
| 955 | CONFIG_PPC_EARLY_DEBUG=y | 999 | # CONFIG_PPC_EARLY_DEBUG is not set |
| 956 | # CONFIG_PPC_EARLY_DEBUG_LPAR is not set | ||
| 957 | # CONFIG_PPC_EARLY_DEBUG_G5 is not set | ||
| 958 | # CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set | ||
| 959 | # CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set | ||
| 960 | # CONFIG_PPC_EARLY_DEBUG_MAPLE is not set | ||
| 961 | # CONFIG_PPC_EARLY_DEBUG_ISERIES is not set | ||
| 962 | # CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set | ||
| 963 | # CONFIG_PPC_EARLY_DEBUG_BEAT is not set | ||
| 964 | CONFIG_PPC_EARLY_DEBUG_44x=y | ||
| 965 | # CONFIG_PPC_EARLY_DEBUG_40x is not set | ||
| 966 | # CONFIG_PPC_EARLY_DEBUG_CPM is not set | ||
| 967 | CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300 | ||
| 968 | CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x1 | ||
| 969 | 1000 | ||
| 970 | # | 1001 | # |
| 971 | # Security options | 1002 | # Security options |
| @@ -988,10 +1019,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y | |||
| 988 | CONFIG_CRYPTO_HASH=y | 1019 | CONFIG_CRYPTO_HASH=y |
| 989 | CONFIG_CRYPTO_HASH2=y | 1020 | CONFIG_CRYPTO_HASH2=y |
| 990 | CONFIG_CRYPTO_RNG2=y | 1021 | CONFIG_CRYPTO_RNG2=y |
| 1022 | CONFIG_CRYPTO_PCOMP=y | ||
| 991 | CONFIG_CRYPTO_MANAGER=y | 1023 | CONFIG_CRYPTO_MANAGER=y |
| 992 | CONFIG_CRYPTO_MANAGER2=y | 1024 | CONFIG_CRYPTO_MANAGER2=y |
| 993 | # CONFIG_CRYPTO_GF128MUL is not set | 1025 | # CONFIG_CRYPTO_GF128MUL is not set |
| 994 | # CONFIG_CRYPTO_NULL is not set | 1026 | # CONFIG_CRYPTO_NULL is not set |
| 1027 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 995 | # CONFIG_CRYPTO_CRYPTD is not set | 1028 | # CONFIG_CRYPTO_CRYPTD is not set |
| 996 | # CONFIG_CRYPTO_AUTHENC is not set | 1029 | # CONFIG_CRYPTO_AUTHENC is not set |
| 997 | # CONFIG_CRYPTO_TEST is not set | 1030 | # CONFIG_CRYPTO_TEST is not set |
| @@ -1060,6 +1093,7 @@ CONFIG_CRYPTO_DES=y | |||
| 1060 | # Compression | 1093 | # Compression |
| 1061 | # | 1094 | # |
| 1062 | # CONFIG_CRYPTO_DEFLATE is not set | 1095 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1096 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1063 | # CONFIG_CRYPTO_LZO is not set | 1097 | # CONFIG_CRYPTO_LZO is not set |
| 1064 | 1098 | ||
| 1065 | # | 1099 | # |
| @@ -1068,5 +1102,6 @@ CONFIG_CRYPTO_DES=y | |||
| 1068 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 1102 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 1069 | CONFIG_CRYPTO_HW=y | 1103 | CONFIG_CRYPTO_HW=y |
| 1070 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | 1104 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set |
| 1105 | # CONFIG_CRYPTO_DEV_PPC4XX is not set | ||
| 1071 | # CONFIG_PPC_CLOCK is not set | 1106 | # CONFIG_PPC_CLOCK is not set |
| 1072 | # CONFIG_VIRTUALIZATION is not set | 1107 | # CONFIG_VIRTUALIZATION is not set |
diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig index 826700872d26..ef32cc4f82eb 100644 --- a/arch/powerpc/configs/44x/taishan_defconfig +++ b/arch/powerpc/configs/44x/taishan_defconfig | |||
| @@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 260 | # CONFIG_PCIEPORTBUS is not set | 260 | # CONFIG_PCIEPORTBUS is not set |
| 261 | CONFIG_ARCH_SUPPORTS_MSI=y | 261 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 262 | # CONFIG_PCI_MSI is not set | 262 | # CONFIG_PCI_MSI is not set |
| 263 | CONFIG_PCI_LEGACY=y | 263 | # CONFIG_PCI_LEGACY is not set |
| 264 | # CONFIG_PCI_DEBUG is not set | 264 | # CONFIG_PCI_DEBUG is not set |
| 265 | # CONFIG_PCI_STUB is not set | 265 | # CONFIG_PCI_STUB is not set |
| 266 | # CONFIG_PCCARD is not set | 266 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig index 1bf0a63614b1..2518b8568c70 100644 --- a/arch/powerpc/configs/44x/virtex5_defconfig +++ b/arch/powerpc/configs/44x/virtex5_defconfig | |||
| @@ -263,7 +263,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 263 | # CONFIG_PCIEPORTBUS is not set | 263 | # CONFIG_PCIEPORTBUS is not set |
| 264 | CONFIG_ARCH_SUPPORTS_MSI=y | 264 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 265 | # CONFIG_PCI_MSI is not set | 265 | # CONFIG_PCI_MSI is not set |
| 266 | CONFIG_PCI_LEGACY=y | 266 | # CONFIG_PCI_LEGACY is not set |
| 267 | # CONFIG_PCI_DEBUG is not set | 267 | # CONFIG_PCI_DEBUG is not set |
| 268 | # CONFIG_PCI_STUB is not set | 268 | # CONFIG_PCI_STUB is not set |
| 269 | # CONFIG_PCCARD is not set | 269 | # CONFIG_PCCARD is not set |
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig new file mode 100644 index 000000000000..bf0853f29f31 --- /dev/null +++ b/arch/powerpc/configs/83xx/kmeter1_defconfig | |||
| @@ -0,0 +1,908 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.28 | ||
| 4 | # Fri Apr 3 10:34:33 2009 | ||
| 5 | # | ||
| 6 | # CONFIG_PPC64 is not set | ||
| 7 | |||
| 8 | # | ||
| 9 | # Processor support | ||
| 10 | # | ||
| 11 | CONFIG_6xx=y | ||
| 12 | # CONFIG_PPC_85xx is not set | ||
| 13 | # CONFIG_PPC_8xx is not set | ||
| 14 | # CONFIG_40x is not set | ||
| 15 | # CONFIG_44x is not set | ||
| 16 | # CONFIG_E200 is not set | ||
| 17 | CONFIG_PPC_FPU=y | ||
| 18 | # CONFIG_FSL_EMB_PERFMON is not set | ||
| 19 | # CONFIG_ALTIVEC is not set | ||
| 20 | CONFIG_PPC_STD_MMU=y | ||
| 21 | CONFIG_PPC_STD_MMU_32=y | ||
| 22 | # CONFIG_PPC_MM_SLICES is not set | ||
| 23 | # CONFIG_SMP is not set | ||
| 24 | CONFIG_PPC32=y | ||
| 25 | CONFIG_WORD_SIZE=32 | ||
| 26 | # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set | ||
| 27 | CONFIG_MMU=y | ||
| 28 | CONFIG_GENERIC_CMOS_UPDATE=y | ||
| 29 | CONFIG_GENERIC_TIME=y | ||
| 30 | CONFIG_GENERIC_TIME_VSYSCALL=y | ||
| 31 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 32 | CONFIG_GENERIC_HARDIRQS=y | ||
| 33 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set | ||
| 34 | CONFIG_IRQ_PER_CPU=y | ||
| 35 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 36 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 37 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 38 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y | ||
| 39 | CONFIG_ARCH_HAS_ILOG2_U32=y | ||
| 40 | CONFIG_GENERIC_HWEIGHT=y | ||
| 41 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 42 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 43 | # CONFIG_ARCH_NO_VIRT_TO_BUS is not set | ||
| 44 | CONFIG_PPC=y | ||
| 45 | CONFIG_EARLY_PRINTK=y | ||
| 46 | CONFIG_GENERIC_NVRAM=y | ||
| 47 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
| 48 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y | ||
| 49 | CONFIG_PPC_OF=y | ||
| 50 | CONFIG_OF=y | ||
| 51 | CONFIG_PPC_UDBG_16550=y | ||
| 52 | # CONFIG_GENERIC_TBSYNC is not set | ||
| 53 | CONFIG_AUDIT_ARCH=y | ||
| 54 | CONFIG_GENERIC_BUG=y | ||
| 55 | CONFIG_DEFAULT_UIMAGE=y | ||
| 56 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 57 | # CONFIG_PPC_DCR_NATIVE is not set | ||
| 58 | # CONFIG_PPC_DCR_MMIO is not set | ||
| 59 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 60 | |||
| 61 | # | ||
| 62 | # General setup | ||
| 63 | # | ||
| 64 | CONFIG_EXPERIMENTAL=y | ||
| 65 | CONFIG_BROKEN_ON_SMP=y | ||
| 66 | CONFIG_LOCK_KERNEL=y | ||
| 67 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 68 | CONFIG_LOCALVERSION="" | ||
| 69 | CONFIG_LOCALVERSION_AUTO=y | ||
| 70 | # CONFIG_SWAP is not set | ||
| 71 | CONFIG_SYSVIPC=y | ||
| 72 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 73 | CONFIG_POSIX_MQUEUE=y | ||
| 74 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 75 | # CONFIG_TASKSTATS is not set | ||
| 76 | # CONFIG_AUDIT is not set | ||
| 77 | # CONFIG_IKCONFIG is not set | ||
| 78 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 79 | # CONFIG_CGROUPS is not set | ||
| 80 | # CONFIG_GROUP_SCHED is not set | ||
| 81 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 82 | # CONFIG_RELAY is not set | ||
| 83 | # CONFIG_NAMESPACES is not set | ||
| 84 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 85 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 86 | CONFIG_SYSCTL=y | ||
| 87 | CONFIG_EMBEDDED=y | ||
| 88 | CONFIG_SYSCTL_SYSCALL=y | ||
| 89 | CONFIG_KALLSYMS=y | ||
| 90 | CONFIG_KALLSYMS_ALL=y | ||
| 91 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 92 | # CONFIG_HOTPLUG is not set | ||
| 93 | CONFIG_PRINTK=y | ||
| 94 | CONFIG_BUG=y | ||
| 95 | CONFIG_ELF_CORE=y | ||
| 96 | CONFIG_COMPAT_BRK=y | ||
| 97 | CONFIG_BASE_FULL=y | ||
| 98 | CONFIG_FUTEX=y | ||
| 99 | CONFIG_ANON_INODES=y | ||
| 100 | CONFIG_EPOLL=y | ||
| 101 | CONFIG_SIGNALFD=y | ||
| 102 | CONFIG_TIMERFD=y | ||
| 103 | CONFIG_EVENTFD=y | ||
| 104 | CONFIG_SHMEM=y | ||
| 105 | CONFIG_AIO=y | ||
| 106 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 107 | CONFIG_SLAB=y | ||
| 108 | # CONFIG_SLUB is not set | ||
| 109 | # CONFIG_SLOB is not set | ||
| 110 | # CONFIG_PROFILING is not set | ||
| 111 | # CONFIG_MARKERS is not set | ||
| 112 | CONFIG_HAVE_OPROFILE=y | ||
| 113 | # CONFIG_KPROBES is not set | ||
| 114 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | ||
| 115 | CONFIG_HAVE_IOREMAP_PROT=y | ||
| 116 | CONFIG_HAVE_KPROBES=y | ||
| 117 | CONFIG_HAVE_KRETPROBES=y | ||
| 118 | CONFIG_HAVE_ARCH_TRACEHOOK=y | ||
| 119 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 120 | CONFIG_SLABINFO=y | ||
| 121 | CONFIG_RT_MUTEXES=y | ||
| 122 | # CONFIG_TINY_SHMEM is not set | ||
| 123 | CONFIG_BASE_SMALL=0 | ||
| 124 | CONFIG_MODULES=y | ||
| 125 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 126 | CONFIG_MODULE_UNLOAD=y | ||
| 127 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 128 | # CONFIG_MODVERSIONS is not set | ||
| 129 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 130 | CONFIG_KMOD=y | ||
| 131 | CONFIG_BLOCK=y | ||
| 132 | # CONFIG_LBD is not set | ||
| 133 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 134 | # CONFIG_LSF is not set | ||
| 135 | # CONFIG_BLK_DEV_BSG is not set | ||
| 136 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 137 | |||
| 138 | # | ||
| 139 | # IO Schedulers | ||
| 140 | # | ||
| 141 | CONFIG_IOSCHED_NOOP=y | ||
| 142 | # CONFIG_IOSCHED_AS is not set | ||
| 143 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 144 | # CONFIG_IOSCHED_CFQ is not set | ||
| 145 | # CONFIG_DEFAULT_AS is not set | ||
| 146 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 147 | # CONFIG_DEFAULT_CFQ is not set | ||
| 148 | CONFIG_DEFAULT_NOOP=y | ||
| 149 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 150 | CONFIG_CLASSIC_RCU=y | ||
| 151 | # CONFIG_FREEZER is not set | ||
| 152 | |||
| 153 | # | ||
| 154 | # Platform support | ||
| 155 | # | ||
| 156 | CONFIG_PPC_MULTIPLATFORM=y | ||
| 157 | CONFIG_CLASSIC32=y | ||
| 158 | # CONFIG_PPC_CHRP is not set | ||
| 159 | # CONFIG_MPC5121_ADS is not set | ||
| 160 | # CONFIG_MPC5121_GENERIC is not set | ||
| 161 | # CONFIG_PPC_MPC52xx is not set | ||
| 162 | # CONFIG_PPC_PMAC is not set | ||
| 163 | # CONFIG_PPC_CELL is not set | ||
| 164 | # CONFIG_PPC_CELL_NATIVE is not set | ||
| 165 | # CONFIG_PPC_82xx is not set | ||
| 166 | # CONFIG_PQ2ADS is not set | ||
| 167 | CONFIG_PPC_83xx=y | ||
| 168 | # CONFIG_MPC831x_RDB is not set | ||
| 169 | # CONFIG_MPC832x_MDS is not set | ||
| 170 | # CONFIG_MPC832x_RDB is not set | ||
| 171 | # CONFIG_MPC834x_MDS is not set | ||
| 172 | # CONFIG_MPC834x_ITX is not set | ||
| 173 | # CONFIG_MPC836x_MDS is not set | ||
| 174 | # CONFIG_MPC836x_RDK is not set | ||
| 175 | # CONFIG_MPC837x_MDS is not set | ||
| 176 | # CONFIG_MPC837x_RDB is not set | ||
| 177 | # CONFIG_SBC834x is not set | ||
| 178 | # CONFIG_ASP834x is not set | ||
| 179 | CONFIG_KMETER1=y | ||
| 180 | # CONFIG_PPC_86xx is not set | ||
| 181 | # CONFIG_EMBEDDED6xx is not set | ||
| 182 | CONFIG_IPIC=y | ||
| 183 | # CONFIG_MPIC is not set | ||
| 184 | # CONFIG_MPIC_WEIRD is not set | ||
| 185 | # CONFIG_PPC_I8259 is not set | ||
| 186 | # CONFIG_PPC_RTAS is not set | ||
| 187 | # CONFIG_MMIO_NVRAM is not set | ||
| 188 | # CONFIG_PPC_MPC106 is not set | ||
| 189 | # CONFIG_PPC_970_NAP is not set | ||
| 190 | # CONFIG_PPC_INDIRECT_IO is not set | ||
| 191 | # CONFIG_GENERIC_IOMAP is not set | ||
| 192 | # CONFIG_CPU_FREQ is not set | ||
| 193 | # CONFIG_TAU is not set | ||
| 194 | CONFIG_QUICC_ENGINE=y | ||
| 195 | # CONFIG_QE_GPIO is not set | ||
| 196 | # CONFIG_FSL_ULI1575 is not set | ||
| 197 | |||
| 198 | # | ||
| 199 | # Kernel options | ||
| 200 | # | ||
| 201 | # CONFIG_HIGHMEM is not set | ||
| 202 | CONFIG_TICK_ONESHOT=y | ||
| 203 | CONFIG_NO_HZ=y | ||
| 204 | CONFIG_HIGH_RES_TIMERS=y | ||
| 205 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 206 | # CONFIG_HZ_100 is not set | ||
| 207 | CONFIG_HZ_250=y | ||
| 208 | # CONFIG_HZ_300 is not set | ||
| 209 | # CONFIG_HZ_1000 is not set | ||
| 210 | CONFIG_HZ=250 | ||
| 211 | CONFIG_SCHED_HRTICK=y | ||
| 212 | # CONFIG_PREEMPT_NONE is not set | ||
| 213 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 214 | CONFIG_PREEMPT=y | ||
| 215 | # CONFIG_PREEMPT_RCU is not set | ||
| 216 | CONFIG_BINFMT_ELF=y | ||
| 217 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 218 | # CONFIG_HAVE_AOUT is not set | ||
| 219 | # CONFIG_BINFMT_MISC is not set | ||
| 220 | # CONFIG_IOMMU_HELPER is not set | ||
| 221 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y | ||
| 222 | CONFIG_ARCH_HAS_WALK_MEMORY=y | ||
| 223 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y | ||
| 224 | # CONFIG_KEXEC is not set | ||
| 225 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
| 226 | CONFIG_ARCH_POPULATES_NODE_MAP=y | ||
| 227 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 228 | CONFIG_FLATMEM_MANUAL=y | ||
| 229 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 230 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 231 | CONFIG_FLATMEM=y | ||
| 232 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 233 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 234 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 235 | CONFIG_MIGRATION=y | ||
| 236 | # CONFIG_RESOURCES_64BIT is not set | ||
| 237 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 238 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 239 | CONFIG_BOUNCE=y | ||
| 240 | CONFIG_VIRT_TO_BUS=y | ||
| 241 | CONFIG_UNEVICTABLE_LRU=y | ||
| 242 | CONFIG_FORCE_MAX_ZONEORDER=11 | ||
| 243 | CONFIG_PROC_DEVICETREE=y | ||
| 244 | # CONFIG_CMDLINE_BOOL is not set | ||
| 245 | CONFIG_EXTRA_TARGETS="" | ||
| 246 | # CONFIG_PM is not set | ||
| 247 | # CONFIG_SECCOMP is not set | ||
| 248 | CONFIG_ISA_DMA_API=y | ||
| 249 | |||
| 250 | # | ||
| 251 | # Bus options | ||
| 252 | # | ||
| 253 | CONFIG_ZONE_DMA=y | ||
| 254 | CONFIG_GENERIC_ISA_DMA=y | ||
| 255 | CONFIG_FSL_SOC=y | ||
| 256 | CONFIG_PPC_PCI_CHOICE=y | ||
| 257 | # CONFIG_PCI is not set | ||
| 258 | # CONFIG_PCI_DOMAINS is not set | ||
| 259 | # CONFIG_PCI_SYSCALL is not set | ||
| 260 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 261 | # CONFIG_HAS_RAPIDIO is not set | ||
| 262 | |||
| 263 | # | ||
| 264 | # Advanced setup | ||
| 265 | # | ||
| 266 | # CONFIG_ADVANCED_OPTIONS is not set | ||
| 267 | |||
| 268 | # | ||
| 269 | # Default settings for advanced configuration options are used | ||
| 270 | # | ||
| 271 | CONFIG_LOWMEM_SIZE=0x30000000 | ||
| 272 | CONFIG_PAGE_OFFSET=0xc0000000 | ||
| 273 | CONFIG_KERNEL_START=0xc0000000 | ||
| 274 | CONFIG_PHYSICAL_START=0x00000000 | ||
| 275 | CONFIG_TASK_SIZE=0xc0000000 | ||
| 276 | CONFIG_NET=y | ||
| 277 | |||
| 278 | # | ||
| 279 | # Networking options | ||
| 280 | # | ||
| 281 | CONFIG_PACKET=y | ||
| 282 | # CONFIG_PACKET_MMAP is not set | ||
| 283 | CONFIG_UNIX=y | ||
| 284 | # CONFIG_NET_KEY is not set | ||
| 285 | CONFIG_INET=y | ||
| 286 | CONFIG_IP_MULTICAST=y | ||
| 287 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 288 | CONFIG_IP_FIB_HASH=y | ||
| 289 | CONFIG_IP_PNP=y | ||
| 290 | # CONFIG_IP_PNP_DHCP is not set | ||
| 291 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 292 | # CONFIG_IP_PNP_RARP is not set | ||
| 293 | # CONFIG_NET_IPIP is not set | ||
| 294 | # CONFIG_NET_IPGRE is not set | ||
| 295 | # CONFIG_IP_MROUTE is not set | ||
| 296 | # CONFIG_ARPD is not set | ||
| 297 | # CONFIG_SYN_COOKIES is not set | ||
| 298 | # CONFIG_INET_AH is not set | ||
| 299 | # CONFIG_INET_ESP is not set | ||
| 300 | # CONFIG_INET_IPCOMP is not set | ||
| 301 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 302 | # CONFIG_INET_TUNNEL is not set | ||
| 303 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 304 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 305 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 306 | # CONFIG_INET_LRO is not set | ||
| 307 | CONFIG_INET_DIAG=y | ||
| 308 | CONFIG_INET_TCP_DIAG=y | ||
| 309 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 310 | CONFIG_TCP_CONG_CUBIC=y | ||
| 311 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 312 | # CONFIG_TCP_MD5SIG is not set | ||
| 313 | # CONFIG_IPV6 is not set | ||
| 314 | # CONFIG_NETWORK_SECMARK is not set | ||
| 315 | # CONFIG_NETFILTER is not set | ||
| 316 | # CONFIG_IP_DCCP is not set | ||
| 317 | # CONFIG_IP_SCTP is not set | ||
| 318 | # CONFIG_TIPC is not set | ||
| 319 | # CONFIG_ATM is not set | ||
| 320 | CONFIG_STP=m | ||
| 321 | CONFIG_BRIDGE=m | ||
| 322 | # CONFIG_NET_DSA is not set | ||
| 323 | CONFIG_VLAN_8021Q=y | ||
| 324 | # CONFIG_VLAN_8021Q_GVRP is not set | ||
| 325 | # CONFIG_DECNET is not set | ||
| 326 | CONFIG_LLC=m | ||
| 327 | # CONFIG_LLC2 is not set | ||
| 328 | # CONFIG_IPX is not set | ||
| 329 | # CONFIG_ATALK is not set | ||
| 330 | # CONFIG_X25 is not set | ||
| 331 | # CONFIG_LAPB is not set | ||
| 332 | # CONFIG_ECONET is not set | ||
| 333 | # CONFIG_WAN_ROUTER is not set | ||
| 334 | # CONFIG_NET_SCHED is not set | ||
| 335 | |||
| 336 | # | ||
| 337 | # Network testing | ||
| 338 | # | ||
| 339 | # CONFIG_NET_PKTGEN is not set | ||
| 340 | # CONFIG_HAMRADIO is not set | ||
| 341 | # CONFIG_CAN is not set | ||
| 342 | # CONFIG_IRDA is not set | ||
| 343 | # CONFIG_BT is not set | ||
| 344 | # CONFIG_AF_RXRPC is not set | ||
| 345 | # CONFIG_PHONET is not set | ||
| 346 | # CONFIG_WIRELESS is not set | ||
| 347 | # CONFIG_RFKILL is not set | ||
| 348 | # CONFIG_NET_9P is not set | ||
| 349 | |||
| 350 | # | ||
| 351 | # Device Drivers | ||
| 352 | # | ||
| 353 | |||
| 354 | # | ||
| 355 | # Generic Driver Options | ||
| 356 | # | ||
| 357 | CONFIG_STANDALONE=y | ||
| 358 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 359 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 360 | # CONFIG_CONNECTOR is not set | ||
| 361 | CONFIG_MTD=y | ||
| 362 | # CONFIG_MTD_DEBUG is not set | ||
| 363 | CONFIG_MTD_CONCAT=y | ||
| 364 | CONFIG_MTD_PARTITIONS=y | ||
| 365 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 366 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 367 | CONFIG_MTD_OF_PARTS=y | ||
| 368 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # User Modules And Translation Layers | ||
| 372 | # | ||
| 373 | CONFIG_MTD_CHAR=y | ||
| 374 | CONFIG_MTD_BLKDEVS=y | ||
| 375 | CONFIG_MTD_BLOCK=y | ||
| 376 | # CONFIG_FTL is not set | ||
| 377 | # CONFIG_NFTL is not set | ||
| 378 | # CONFIG_INFTL is not set | ||
| 379 | # CONFIG_RFD_FTL is not set | ||
| 380 | # CONFIG_SSFDC is not set | ||
| 381 | # CONFIG_MTD_OOPS is not set | ||
| 382 | |||
| 383 | # | ||
| 384 | # RAM/ROM/Flash chip drivers | ||
| 385 | # | ||
| 386 | CONFIG_MTD_CFI=y | ||
| 387 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 388 | CONFIG_MTD_GEN_PROBE=y | ||
| 389 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 390 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 391 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 392 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 393 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 394 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 395 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 396 | CONFIG_MTD_CFI_I1=y | ||
| 397 | CONFIG_MTD_CFI_I2=y | ||
| 398 | # CONFIG_MTD_CFI_I4 is not set | ||
| 399 | # CONFIG_MTD_CFI_I8 is not set | ||
| 400 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 401 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 402 | # CONFIG_MTD_CFI_STAA is not set | ||
| 403 | CONFIG_MTD_CFI_UTIL=y | ||
| 404 | # CONFIG_MTD_RAM is not set | ||
| 405 | # CONFIG_MTD_ROM is not set | ||
| 406 | # CONFIG_MTD_ABSENT is not set | ||
| 407 | |||
| 408 | # | ||
| 409 | # Mapping drivers for chip access | ||
| 410 | # | ||
| 411 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 412 | # CONFIG_MTD_PHYSMAP is not set | ||
| 413 | CONFIG_MTD_PHYSMAP_OF=y | ||
| 414 | # CONFIG_MTD_PLATRAM is not set | ||
| 415 | |||
| 416 | # | ||
| 417 | # Self-contained MTD device drivers | ||
| 418 | # | ||
| 419 | # CONFIG_MTD_SLRAM is not set | ||
| 420 | CONFIG_MTD_PHRAM=y | ||
| 421 | # CONFIG_MTD_MTDRAM is not set | ||
| 422 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # Disk-On-Chip Device Drivers | ||
| 426 | # | ||
| 427 | # CONFIG_MTD_DOC2000 is not set | ||
| 428 | # CONFIG_MTD_DOC2001 is not set | ||
| 429 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 430 | # CONFIG_MTD_NAND is not set | ||
| 431 | # CONFIG_MTD_ONENAND is not set | ||
| 432 | |||
| 433 | # | ||
| 434 | # UBI - Unsorted block images | ||
| 435 | # | ||
| 436 | CONFIG_MTD_UBI=y | ||
| 437 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 438 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 439 | CONFIG_MTD_UBI_GLUEBI=y | ||
| 440 | |||
| 441 | # | ||
| 442 | # UBI debugging options | ||
| 443 | # | ||
| 444 | CONFIG_MTD_UBI_DEBUG=y | ||
| 445 | # CONFIG_MTD_UBI_DEBUG_MSG is not set | ||
| 446 | # CONFIG_MTD_UBI_DEBUG_PARANOID is not set | ||
| 447 | # CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set | ||
| 448 | # CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set | ||
| 449 | # CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set | ||
| 450 | # CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set | ||
| 451 | # CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set | ||
| 452 | |||
| 453 | # | ||
| 454 | # Additional UBI debugging messages | ||
| 455 | # | ||
| 456 | # CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set | ||
| 457 | # CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set | ||
| 458 | # CONFIG_MTD_UBI_DEBUG_MSG_WL is not set | ||
| 459 | # CONFIG_MTD_UBI_DEBUG_MSG_IO is not set | ||
| 460 | CONFIG_OF_DEVICE=y | ||
| 461 | CONFIG_OF_I2C=y | ||
| 462 | # CONFIG_PARPORT is not set | ||
| 463 | CONFIG_BLK_DEV=y | ||
| 464 | # CONFIG_BLK_DEV_FD is not set | ||
| 465 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 466 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 467 | # CONFIG_BLK_DEV_NBD is not set | ||
| 468 | # CONFIG_BLK_DEV_RAM is not set | ||
| 469 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 470 | # CONFIG_ATA_OVER_ETH is not set | ||
| 471 | # CONFIG_BLK_DEV_HD is not set | ||
| 472 | # CONFIG_MISC_DEVICES is not set | ||
| 473 | CONFIG_HAVE_IDE=y | ||
| 474 | # CONFIG_IDE is not set | ||
| 475 | |||
| 476 | # | ||
| 477 | # SCSI device support | ||
| 478 | # | ||
| 479 | # CONFIG_RAID_ATTRS is not set | ||
| 480 | # CONFIG_SCSI is not set | ||
| 481 | # CONFIG_SCSI_DMA is not set | ||
| 482 | # CONFIG_SCSI_NETLINK is not set | ||
| 483 | # CONFIG_ATA is not set | ||
| 484 | # CONFIG_MD is not set | ||
| 485 | # CONFIG_MACINTOSH_DRIVERS is not set | ||
| 486 | CONFIG_NETDEVICES=y | ||
| 487 | CONFIG_DUMMY=y | ||
| 488 | # CONFIG_BONDING is not set | ||
| 489 | # CONFIG_MACVLAN is not set | ||
| 490 | # CONFIG_EQUALIZER is not set | ||
| 491 | CONFIG_TUN=y | ||
| 492 | # CONFIG_VETH is not set | ||
| 493 | CONFIG_PHYLIB=y | ||
| 494 | |||
| 495 | # | ||
| 496 | # MII PHY device drivers | ||
| 497 | # | ||
| 498 | CONFIG_MARVELL_PHY=y | ||
| 499 | # CONFIG_DAVICOM_PHY is not set | ||
| 500 | # CONFIG_QSEMI_PHY is not set | ||
| 501 | # CONFIG_LXT_PHY is not set | ||
| 502 | # CONFIG_CICADA_PHY is not set | ||
| 503 | # CONFIG_VITESSE_PHY is not set | ||
| 504 | # CONFIG_SMSC_PHY is not set | ||
| 505 | # CONFIG_BROADCOM_PHY is not set | ||
| 506 | # CONFIG_ICPLUS_PHY is not set | ||
| 507 | # CONFIG_REALTEK_PHY is not set | ||
| 508 | # CONFIG_FIXED_PHY is not set | ||
| 509 | # CONFIG_MDIO_BITBANG is not set | ||
| 510 | CONFIG_NET_ETHERNET=y | ||
| 511 | CONFIG_MII=y | ||
| 512 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 513 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 514 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 515 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 516 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 517 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 518 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 519 | # CONFIG_B44 is not set | ||
| 520 | CONFIG_NETDEV_1000=y | ||
| 521 | # CONFIG_GIANFAR is not set | ||
| 522 | CONFIG_UCC_GETH=y | ||
| 523 | # CONFIG_UGETH_MAGIC_PACKET is not set | ||
| 524 | # CONFIG_UGETH_FILTERING is not set | ||
| 525 | # CONFIG_UGETH_TX_ON_DEMAND is not set | ||
| 526 | # CONFIG_MV643XX_ETH is not set | ||
| 527 | # CONFIG_NETDEV_10000 is not set | ||
| 528 | |||
| 529 | # | ||
| 530 | # Wireless LAN | ||
| 531 | # | ||
| 532 | # CONFIG_WLAN_PRE80211 is not set | ||
| 533 | # CONFIG_WLAN_80211 is not set | ||
| 534 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 535 | CONFIG_WAN=y | ||
| 536 | CONFIG_HDLC=y | ||
| 537 | # CONFIG_HDLC_RAW is not set | ||
| 538 | # CONFIG_HDLC_RAW_ETH is not set | ||
| 539 | # CONFIG_HDLC_CISCO is not set | ||
| 540 | # CONFIG_HDLC_FR is not set | ||
| 541 | # CONFIG_HDLC_PPP is not set | ||
| 542 | |||
| 543 | # | ||
| 544 | # X.25/LAPB support is disabled | ||
| 545 | # | ||
| 546 | CONFIG_HDLC_KM=y | ||
| 547 | CONFIG_FS_UCC_HDLC=y | ||
| 548 | # CONFIG_DLCI is not set | ||
| 549 | CONFIG_PPP=y | ||
| 550 | CONFIG_PPP_MULTILINK=y | ||
| 551 | # CONFIG_PPP_FILTER is not set | ||
| 552 | # CONFIG_PPP_ASYNC is not set | ||
| 553 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 554 | # CONFIG_PPP_DEFLATE is not set | ||
| 555 | # CONFIG_PPP_BSDCOMP is not set | ||
| 556 | # CONFIG_PPP_MPPE is not set | ||
| 557 | CONFIG_PPPOE=y | ||
| 558 | # CONFIG_PPPOL2TP is not set | ||
| 559 | # CONFIG_SLIP is not set | ||
| 560 | CONFIG_SLHC=y | ||
| 561 | # CONFIG_NETCONSOLE is not set | ||
| 562 | # CONFIG_NETPOLL is not set | ||
| 563 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 564 | # CONFIG_ISDN is not set | ||
| 565 | # CONFIG_PHONE is not set | ||
| 566 | |||
| 567 | # | ||
| 568 | # Input device support | ||
| 569 | # | ||
| 570 | # CONFIG_INPUT is not set | ||
| 571 | |||
| 572 | # | ||
| 573 | # Hardware I/O ports | ||
| 574 | # | ||
| 575 | # CONFIG_SERIO is not set | ||
| 576 | # CONFIG_GAMEPORT is not set | ||
| 577 | |||
| 578 | # | ||
| 579 | # Character devices | ||
| 580 | # | ||
| 581 | # CONFIG_VT is not set | ||
| 582 | # CONFIG_DEVKMEM is not set | ||
| 583 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 584 | |||
| 585 | # | ||
| 586 | # Serial drivers | ||
| 587 | # | ||
| 588 | CONFIG_SERIAL_8250=y | ||
| 589 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 590 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 591 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 592 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # Non-8250 serial port support | ||
| 596 | # | ||
| 597 | # CONFIG_SERIAL_UARTLITE is not set | ||
| 598 | CONFIG_SERIAL_CORE=y | ||
| 599 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 600 | # CONFIG_SERIAL_OF_PLATFORM is not set | ||
| 601 | # CONFIG_SERIAL_QE is not set | ||
| 602 | CONFIG_UNIX98_PTYS=y | ||
| 603 | CONFIG_LEGACY_PTYS=y | ||
| 604 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 605 | # CONFIG_IPMI_HANDLER is not set | ||
| 606 | CONFIG_HW_RANDOM=y | ||
| 607 | # CONFIG_NVRAM is not set | ||
| 608 | # CONFIG_GEN_RTC is not set | ||
| 609 | # CONFIG_R3964 is not set | ||
| 610 | # CONFIG_RAW_DRIVER is not set | ||
| 611 | # CONFIG_TCG_TPM is not set | ||
| 612 | CONFIG_BOOTCOUNT=y | ||
| 613 | CONFIG_I2C=y | ||
| 614 | CONFIG_I2C_BOARDINFO=y | ||
| 615 | CONFIG_I2C_CHARDEV=y | ||
| 616 | CONFIG_I2C_HELPER_AUTO=y | ||
| 617 | |||
| 618 | # | ||
| 619 | # I2C Hardware Bus support | ||
| 620 | # | ||
| 621 | |||
| 622 | # | ||
| 623 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 624 | # | ||
| 625 | CONFIG_I2C_MPC=y | ||
| 626 | # CONFIG_I2C_OCORES is not set | ||
| 627 | # CONFIG_I2C_SIMTEC is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # External I2C/SMBus adapter drivers | ||
| 631 | # | ||
| 632 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 633 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 634 | |||
| 635 | # | ||
| 636 | # Other I2C/SMBus bus drivers | ||
| 637 | # | ||
| 638 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 639 | # CONFIG_I2C_STUB is not set | ||
| 640 | |||
| 641 | # | ||
| 642 | # Miscellaneous I2C Chip support | ||
| 643 | # | ||
| 644 | # CONFIG_DS1682 is not set | ||
| 645 | # CONFIG_AT24 is not set | ||
| 646 | # CONFIG_SENSORS_EEPROM is not set | ||
| 647 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 648 | # CONFIG_PCF8575 is not set | ||
| 649 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 650 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 651 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 652 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 653 | # CONFIG_MCU_MPC8349EMITX is not set | ||
| 654 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 655 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 656 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 657 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 658 | # CONFIG_SPI is not set | ||
| 659 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 660 | # CONFIG_GPIOLIB is not set | ||
| 661 | # CONFIG_W1 is not set | ||
| 662 | # CONFIG_POWER_SUPPLY is not set | ||
| 663 | # CONFIG_HWMON is not set | ||
| 664 | # CONFIG_THERMAL is not set | ||
| 665 | # CONFIG_THERMAL_HWMON is not set | ||
| 666 | # CONFIG_WATCHDOG is not set | ||
| 667 | CONFIG_SSB_POSSIBLE=y | ||
| 668 | |||
| 669 | # | ||
| 670 | # Sonics Silicon Backplane | ||
| 671 | # | ||
| 672 | # CONFIG_SSB is not set | ||
| 673 | |||
| 674 | # | ||
| 675 | # Multifunction device drivers | ||
| 676 | # | ||
| 677 | # CONFIG_MFD_CORE is not set | ||
| 678 | # CONFIG_MFD_SM501 is not set | ||
| 679 | # CONFIG_HTC_PASIC3 is not set | ||
| 680 | # CONFIG_MFD_TMIO is not set | ||
| 681 | # CONFIG_PMIC_DA903X is not set | ||
| 682 | # CONFIG_MFD_WM8400 is not set | ||
| 683 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 684 | # CONFIG_REGULATOR is not set | ||
| 685 | |||
| 686 | # | ||
| 687 | # Multimedia devices | ||
| 688 | # | ||
| 689 | |||
| 690 | # | ||
| 691 | # Multimedia core support | ||
| 692 | # | ||
| 693 | # CONFIG_VIDEO_DEV is not set | ||
| 694 | # CONFIG_DVB_CORE is not set | ||
| 695 | # CONFIG_VIDEO_MEDIA is not set | ||
| 696 | |||
| 697 | # | ||
| 698 | # Multimedia drivers | ||
| 699 | # | ||
| 700 | # CONFIG_DAB is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Graphics support | ||
| 704 | # | ||
| 705 | # CONFIG_VGASTATE is not set | ||
| 706 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 707 | # CONFIG_FB is not set | ||
| 708 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 709 | |||
| 710 | # | ||
| 711 | # Display device support | ||
| 712 | # | ||
| 713 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 714 | # CONFIG_SOUND is not set | ||
| 715 | # CONFIG_USB_SUPPORT is not set | ||
| 716 | # CONFIG_MMC is not set | ||
| 717 | # CONFIG_MEMSTICK is not set | ||
| 718 | # CONFIG_NEW_LEDS is not set | ||
| 719 | # CONFIG_ACCESSIBILITY is not set | ||
| 720 | # CONFIG_EDAC is not set | ||
| 721 | # CONFIG_RTC_CLASS is not set | ||
| 722 | # CONFIG_DMADEVICES is not set | ||
| 723 | CONFIG_UIO=y | ||
| 724 | # CONFIG_UIO_PDRV is not set | ||
| 725 | # CONFIG_UIO_PDRV_GENIRQ is not set | ||
| 726 | # CONFIG_UIO_SMX is not set | ||
| 727 | # CONFIG_UIO_SERCOS3 is not set | ||
| 728 | # CONFIG_STAGING is not set | ||
| 729 | |||
| 730 | # | ||
| 731 | # File systems | ||
| 732 | # | ||
| 733 | # CONFIG_EXT2_FS is not set | ||
| 734 | # CONFIG_EXT3_FS is not set | ||
| 735 | # CONFIG_EXT4_FS is not set | ||
| 736 | # CONFIG_REISERFS_FS is not set | ||
| 737 | # CONFIG_JFS_FS is not set | ||
| 738 | # CONFIG_FS_POSIX_ACL is not set | ||
| 739 | CONFIG_FILE_LOCKING=y | ||
| 740 | # CONFIG_XFS_FS is not set | ||
| 741 | # CONFIG_OCFS2_FS is not set | ||
| 742 | # CONFIG_DNOTIFY is not set | ||
| 743 | CONFIG_INOTIFY=y | ||
| 744 | CONFIG_INOTIFY_USER=y | ||
| 745 | # CONFIG_QUOTA is not set | ||
| 746 | # CONFIG_AUTOFS_FS is not set | ||
| 747 | # CONFIG_AUTOFS4_FS is not set | ||
| 748 | # CONFIG_FUSE_FS is not set | ||
| 749 | |||
| 750 | # | ||
| 751 | # CD-ROM/DVD Filesystems | ||
| 752 | # | ||
| 753 | # CONFIG_ISO9660_FS is not set | ||
| 754 | # CONFIG_UDF_FS is not set | ||
| 755 | |||
| 756 | # | ||
| 757 | # DOS/FAT/NT Filesystems | ||
| 758 | # | ||
| 759 | # CONFIG_MSDOS_FS is not set | ||
| 760 | # CONFIG_VFAT_FS is not set | ||
| 761 | # CONFIG_NTFS_FS is not set | ||
| 762 | |||
| 763 | # | ||
| 764 | # Pseudo filesystems | ||
| 765 | # | ||
| 766 | CONFIG_PROC_FS=y | ||
| 767 | # CONFIG_PROC_KCORE is not set | ||
| 768 | CONFIG_PROC_SYSCTL=y | ||
| 769 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 770 | CONFIG_SYSFS=y | ||
| 771 | CONFIG_TMPFS=y | ||
| 772 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 773 | # CONFIG_HUGETLB_PAGE is not set | ||
| 774 | # CONFIG_CONFIGFS_FS is not set | ||
| 775 | |||
| 776 | # | ||
| 777 | # Miscellaneous filesystems | ||
| 778 | # | ||
| 779 | # CONFIG_ADFS_FS is not set | ||
| 780 | # CONFIG_AFFS_FS is not set | ||
| 781 | # CONFIG_HFS_FS is not set | ||
| 782 | # CONFIG_HFSPLUS_FS is not set | ||
| 783 | # CONFIG_BEFS_FS is not set | ||
| 784 | # CONFIG_BFS_FS is not set | ||
| 785 | # CONFIG_EFS_FS is not set | ||
| 786 | CONFIG_JFFS2_FS=y | ||
| 787 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 788 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 789 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 790 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 791 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 792 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 793 | CONFIG_JFFS2_ZLIB=y | ||
| 794 | # CONFIG_JFFS2_LZO is not set | ||
| 795 | CONFIG_JFFS2_RTIME=y | ||
| 796 | # CONFIG_JFFS2_RUBIN is not set | ||
| 797 | # CONFIG_UBIFS_FS is not set | ||
| 798 | # CONFIG_CRAMFS is not set | ||
| 799 | # CONFIG_VXFS_FS is not set | ||
| 800 | # CONFIG_MINIX_FS is not set | ||
| 801 | # CONFIG_OMFS_FS is not set | ||
| 802 | # CONFIG_HPFS_FS is not set | ||
| 803 | # CONFIG_QNX4FS_FS is not set | ||
| 804 | # CONFIG_ROMFS_FS is not set | ||
| 805 | # CONFIG_SYSV_FS is not set | ||
| 806 | # CONFIG_UFS_FS is not set | ||
| 807 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 808 | CONFIG_NFS_FS=y | ||
| 809 | CONFIG_NFS_V3=y | ||
| 810 | # CONFIG_NFS_V3_ACL is not set | ||
| 811 | # CONFIG_NFS_V4 is not set | ||
| 812 | CONFIG_ROOT_NFS=y | ||
| 813 | # CONFIG_NFSD is not set | ||
| 814 | CONFIG_LOCKD=y | ||
| 815 | CONFIG_LOCKD_V4=y | ||
| 816 | CONFIG_NFS_COMMON=y | ||
| 817 | CONFIG_SUNRPC=y | ||
| 818 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 819 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 820 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 821 | # CONFIG_SMB_FS is not set | ||
| 822 | # CONFIG_CIFS is not set | ||
| 823 | # CONFIG_NCP_FS is not set | ||
| 824 | # CONFIG_CODA_FS is not set | ||
| 825 | # CONFIG_AFS_FS is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # Partition Types | ||
| 829 | # | ||
| 830 | CONFIG_PARTITION_ADVANCED=y | ||
| 831 | # CONFIG_ACORN_PARTITION is not set | ||
| 832 | # CONFIG_OSF_PARTITION is not set | ||
| 833 | # CONFIG_AMIGA_PARTITION is not set | ||
| 834 | # CONFIG_ATARI_PARTITION is not set | ||
| 835 | # CONFIG_MAC_PARTITION is not set | ||
| 836 | # CONFIG_MSDOS_PARTITION is not set | ||
| 837 | # CONFIG_LDM_PARTITION is not set | ||
| 838 | # CONFIG_SGI_PARTITION is not set | ||
| 839 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 840 | # CONFIG_SUN_PARTITION is not set | ||
| 841 | # CONFIG_KARMA_PARTITION is not set | ||
| 842 | # CONFIG_EFI_PARTITION is not set | ||
| 843 | # CONFIG_SYSV68_PARTITION is not set | ||
| 844 | # CONFIG_NLS is not set | ||
| 845 | # CONFIG_DLM is not set | ||
| 846 | CONFIG_UCC_FAST=y | ||
| 847 | CONFIG_UCC=y | ||
| 848 | |||
| 849 | # | ||
| 850 | # Library routines | ||
| 851 | # | ||
| 852 | CONFIG_BITREVERSE=y | ||
| 853 | # CONFIG_CRC_CCITT is not set | ||
| 854 | # CONFIG_CRC16 is not set | ||
| 855 | # CONFIG_CRC_T10DIF is not set | ||
| 856 | # CONFIG_CRC_ITU_T is not set | ||
| 857 | CONFIG_CRC32=y | ||
| 858 | # CONFIG_CRC7 is not set | ||
| 859 | # CONFIG_LIBCRC32C is not set | ||
| 860 | CONFIG_ZLIB_INFLATE=y | ||
| 861 | CONFIG_ZLIB_DEFLATE=y | ||
| 862 | CONFIG_PLIST=y | ||
| 863 | CONFIG_HAS_IOMEM=y | ||
| 864 | CONFIG_HAS_IOPORT=y | ||
| 865 | CONFIG_HAS_DMA=y | ||
| 866 | CONFIG_HAVE_LMB=y | ||
| 867 | |||
| 868 | # | ||
| 869 | # Kernel hacking | ||
| 870 | # | ||
| 871 | # CONFIG_PRINTK_TIME is not set | ||
| 872 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 873 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 874 | CONFIG_FRAME_WARN=1024 | ||
| 875 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 876 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 877 | CONFIG_DEBUG_FS=y | ||
| 878 | # CONFIG_HEADERS_CHECK is not set | ||
| 879 | # CONFIG_DEBUG_KERNEL is not set | ||
| 880 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 881 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 882 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 883 | # CONFIG_LATENCYTOP is not set | ||
| 884 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 885 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 886 | |||
| 887 | # | ||
| 888 | # Tracers | ||
| 889 | # | ||
| 890 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 891 | # CONFIG_SAMPLES is not set | ||
| 892 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 893 | # CONFIG_IRQSTACKS is not set | ||
| 894 | # CONFIG_VIRQ_DEBUG is not set | ||
| 895 | # CONFIG_BOOTX_TEXT is not set | ||
| 896 | # CONFIG_PPC_EARLY_DEBUG is not set | ||
| 897 | |||
| 898 | # | ||
| 899 | # Security options | ||
| 900 | # | ||
| 901 | # CONFIG_KEYS is not set | ||
| 902 | # CONFIG_SECURITY is not set | ||
| 903 | # CONFIG_SECURITYFS is not set | ||
| 904 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 905 | # CONFIG_CRYPTO is not set | ||
| 906 | # CONFIG_PPC_CLOCK is not set | ||
| 907 | CONFIG_PPC_LIB_RHEAP=y | ||
| 908 | # CONFIG_VIRTUALIZATION is not set | ||
diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig new file mode 100644 index 000000000000..2552cbefba6b --- /dev/null +++ b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig | |||
| @@ -0,0 +1,1821 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.30-rc6 | ||
| 4 | # Thu Jun 11 11:25:17 2009 | ||
| 5 | # | ||
| 6 | # CONFIG_PPC64 is not set | ||
| 7 | |||
| 8 | # | ||
| 9 | # Processor support | ||
| 10 | # | ||
| 11 | # CONFIG_6xx is not set | ||
| 12 | CONFIG_PPC_85xx=y | ||
| 13 | # CONFIG_PPC_8xx is not set | ||
| 14 | # CONFIG_40x is not set | ||
| 15 | # CONFIG_44x is not set | ||
| 16 | # CONFIG_E200 is not set | ||
| 17 | CONFIG_E500=y | ||
| 18 | # CONFIG_PPC_E500MC is not set | ||
| 19 | CONFIG_BOOKE=y | ||
| 20 | CONFIG_FSL_BOOKE=y | ||
| 21 | CONFIG_FSL_EMB_PERFMON=y | ||
| 22 | # CONFIG_PHYS_64BIT is not set | ||
| 23 | CONFIG_SPE=y | ||
| 24 | CONFIG_PPC_MMU_NOHASH=y | ||
| 25 | CONFIG_PPC_BOOK3E_MMU=y | ||
| 26 | # CONFIG_PPC_MM_SLICES is not set | ||
| 27 | CONFIG_SMP=y | ||
| 28 | CONFIG_NR_CPUS=2 | ||
| 29 | CONFIG_PPC32=y | ||
| 30 | CONFIG_WORD_SIZE=32 | ||
| 31 | # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set | ||
| 32 | CONFIG_MMU=y | ||
| 33 | CONFIG_GENERIC_CMOS_UPDATE=y | ||
| 34 | CONFIG_GENERIC_TIME=y | ||
| 35 | CONFIG_GENERIC_TIME_VSYSCALL=y | ||
| 36 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 37 | CONFIG_GENERIC_HARDIRQS=y | ||
| 38 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set | ||
| 39 | CONFIG_IRQ_PER_CPU=y | ||
| 40 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 41 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 42 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 43 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y | ||
| 44 | CONFIG_ARCH_HAS_ILOG2_U32=y | ||
| 45 | CONFIG_GENERIC_HWEIGHT=y | ||
| 46 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 47 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 48 | CONFIG_GENERIC_GPIO=y | ||
| 49 | # CONFIG_ARCH_NO_VIRT_TO_BUS is not set | ||
| 50 | CONFIG_PPC=y | ||
| 51 | CONFIG_EARLY_PRINTK=y | ||
| 52 | CONFIG_GENERIC_NVRAM=y | ||
| 53 | CONFIG_SCHED_OMIT_FRAME_POINTER=y | ||
| 54 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y | ||
| 55 | CONFIG_PPC_OF=y | ||
| 56 | CONFIG_OF=y | ||
| 57 | CONFIG_PPC_UDBG_16550=y | ||
| 58 | CONFIG_GENERIC_TBSYNC=y | ||
| 59 | CONFIG_AUDIT_ARCH=y | ||
| 60 | CONFIG_GENERIC_BUG=y | ||
| 61 | CONFIG_DTC=y | ||
| 62 | CONFIG_DEFAULT_UIMAGE=y | ||
| 63 | # CONFIG_PPC_DCR_NATIVE is not set | ||
| 64 | # CONFIG_PPC_DCR_MMIO is not set | ||
| 65 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y | ||
| 66 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 67 | |||
| 68 | # | ||
| 69 | # General setup | ||
| 70 | # | ||
| 71 | CONFIG_EXPERIMENTAL=y | ||
| 72 | CONFIG_LOCK_KERNEL=y | ||
| 73 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 74 | CONFIG_LOCALVERSION="" | ||
| 75 | CONFIG_LOCALVERSION_AUTO=y | ||
| 76 | CONFIG_SWAP=y | ||
| 77 | CONFIG_SYSVIPC=y | ||
| 78 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 79 | CONFIG_POSIX_MQUEUE=y | ||
| 80 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 81 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 82 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 83 | # CONFIG_TASKSTATS is not set | ||
| 84 | CONFIG_AUDIT=y | ||
| 85 | # CONFIG_AUDITSYSCALL is not set | ||
| 86 | |||
| 87 | # | ||
| 88 | # RCU Subsystem | ||
| 89 | # | ||
| 90 | CONFIG_CLASSIC_RCU=y | ||
| 91 | # CONFIG_TREE_RCU is not set | ||
| 92 | # CONFIG_PREEMPT_RCU is not set | ||
| 93 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 94 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 95 | CONFIG_IKCONFIG=y | ||
| 96 | CONFIG_IKCONFIG_PROC=y | ||
| 97 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 98 | # CONFIG_GROUP_SCHED is not set | ||
| 99 | # CONFIG_CGROUPS is not set | ||
| 100 | CONFIG_SYSFS_DEPRECATED=y | ||
| 101 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 102 | # CONFIG_RELAY is not set | ||
| 103 | # CONFIG_NAMESPACES is not set | ||
| 104 | CONFIG_BLK_DEV_INITRD=y | ||
| 105 | CONFIG_INITRAMFS_SOURCE="" | ||
| 106 | CONFIG_RD_GZIP=y | ||
| 107 | # CONFIG_RD_BZIP2 is not set | ||
| 108 | # CONFIG_RD_LZMA is not set | ||
| 109 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 110 | CONFIG_SYSCTL=y | ||
| 111 | CONFIG_ANON_INODES=y | ||
| 112 | CONFIG_EMBEDDED=y | ||
| 113 | CONFIG_SYSCTL_SYSCALL=y | ||
| 114 | CONFIG_KALLSYMS=y | ||
| 115 | CONFIG_KALLSYMS_ALL=y | ||
| 116 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 117 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 118 | CONFIG_HOTPLUG=y | ||
| 119 | CONFIG_PRINTK=y | ||
| 120 | CONFIG_BUG=y | ||
| 121 | CONFIG_ELF_CORE=y | ||
| 122 | CONFIG_BASE_FULL=y | ||
| 123 | CONFIG_FUTEX=y | ||
| 124 | CONFIG_EPOLL=y | ||
| 125 | CONFIG_SIGNALFD=y | ||
| 126 | CONFIG_TIMERFD=y | ||
| 127 | CONFIG_EVENTFD=y | ||
| 128 | CONFIG_SHMEM=y | ||
| 129 | CONFIG_AIO=y | ||
| 130 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 131 | CONFIG_PCI_QUIRKS=y | ||
| 132 | CONFIG_SLUB_DEBUG=y | ||
| 133 | CONFIG_COMPAT_BRK=y | ||
| 134 | # CONFIG_SLAB is not set | ||
| 135 | CONFIG_SLUB=y | ||
| 136 | # CONFIG_SLOB is not set | ||
| 137 | # CONFIG_PROFILING is not set | ||
| 138 | # CONFIG_MARKERS is not set | ||
| 139 | CONFIG_HAVE_OPROFILE=y | ||
| 140 | # CONFIG_KPROBES is not set | ||
| 141 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | ||
| 142 | CONFIG_HAVE_IOREMAP_PROT=y | ||
| 143 | CONFIG_HAVE_KPROBES=y | ||
| 144 | CONFIG_HAVE_KRETPROBES=y | ||
| 145 | CONFIG_HAVE_ARCH_TRACEHOOK=y | ||
| 146 | CONFIG_USE_GENERIC_SMP_HELPERS=y | ||
| 147 | # CONFIG_SLOW_WORK is not set | ||
| 148 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 149 | CONFIG_SLABINFO=y | ||
| 150 | CONFIG_RT_MUTEXES=y | ||
| 151 | CONFIG_BASE_SMALL=0 | ||
| 152 | CONFIG_MODULES=y | ||
| 153 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 154 | CONFIG_MODULE_UNLOAD=y | ||
| 155 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 156 | CONFIG_MODVERSIONS=y | ||
| 157 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 158 | CONFIG_STOP_MACHINE=y | ||
| 159 | CONFIG_BLOCK=y | ||
| 160 | CONFIG_LBD=y | ||
| 161 | # CONFIG_BLK_DEV_BSG is not set | ||
| 162 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 163 | |||
| 164 | # | ||
| 165 | # IO Schedulers | ||
| 166 | # | ||
| 167 | CONFIG_IOSCHED_NOOP=y | ||
| 168 | CONFIG_IOSCHED_AS=y | ||
| 169 | CONFIG_IOSCHED_DEADLINE=y | ||
| 170 | CONFIG_IOSCHED_CFQ=y | ||
| 171 | # CONFIG_DEFAULT_AS is not set | ||
| 172 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 173 | CONFIG_DEFAULT_CFQ=y | ||
| 174 | # CONFIG_DEFAULT_NOOP is not set | ||
| 175 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 176 | # CONFIG_FREEZER is not set | ||
| 177 | CONFIG_PPC_MSI_BITMAP=y | ||
| 178 | |||
| 179 | # | ||
| 180 | # Platform support | ||
| 181 | # | ||
| 182 | # CONFIG_PPC_CELL is not set | ||
| 183 | # CONFIG_PPC_CELL_NATIVE is not set | ||
| 184 | # CONFIG_PQ2ADS is not set | ||
| 185 | CONFIG_MPC85xx=y | ||
| 186 | # CONFIG_MPC8540_ADS is not set | ||
| 187 | # CONFIG_MPC8560_ADS is not set | ||
| 188 | # CONFIG_MPC85xx_CDS is not set | ||
| 189 | # CONFIG_MPC85xx_MDS is not set | ||
| 190 | # CONFIG_MPC8536_DS is not set | ||
| 191 | # CONFIG_MPC85xx_DS is not set | ||
| 192 | # CONFIG_SOCRATES is not set | ||
| 193 | # CONFIG_KSI8560 is not set | ||
| 194 | CONFIG_XES_MPC85xx=y | ||
| 195 | # CONFIG_STX_GP3 is not set | ||
| 196 | # CONFIG_TQM8540 is not set | ||
| 197 | # CONFIG_TQM8541 is not set | ||
| 198 | # CONFIG_TQM8548 is not set | ||
| 199 | # CONFIG_TQM8555 is not set | ||
| 200 | # CONFIG_TQM8560 is not set | ||
| 201 | # CONFIG_SBC8548 is not set | ||
| 202 | # CONFIG_SBC8560 is not set | ||
| 203 | # CONFIG_IPIC is not set | ||
| 204 | CONFIG_MPIC=y | ||
| 205 | # CONFIG_MPIC_WEIRD is not set | ||
| 206 | # CONFIG_PPC_I8259 is not set | ||
| 207 | # CONFIG_PPC_RTAS is not set | ||
| 208 | # CONFIG_MMIO_NVRAM is not set | ||
| 209 | # CONFIG_PPC_MPC106 is not set | ||
| 210 | # CONFIG_PPC_970_NAP is not set | ||
| 211 | # CONFIG_PPC_INDIRECT_IO is not set | ||
| 212 | # CONFIG_GENERIC_IOMAP is not set | ||
| 213 | # CONFIG_CPU_FREQ is not set | ||
| 214 | # CONFIG_QUICC_ENGINE is not set | ||
| 215 | # CONFIG_CPM2 is not set | ||
| 216 | # CONFIG_FSL_ULI1575 is not set | ||
| 217 | CONFIG_MPC8xxx_GPIO=y | ||
| 218 | # CONFIG_SIMPLE_GPIO is not set | ||
| 219 | |||
| 220 | # | ||
| 221 | # Kernel options | ||
| 222 | # | ||
| 223 | CONFIG_HIGHMEM=y | ||
| 224 | # CONFIG_NO_HZ is not set | ||
| 225 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 226 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 227 | # CONFIG_HZ_100 is not set | ||
| 228 | CONFIG_HZ_250=y | ||
| 229 | # CONFIG_HZ_300 is not set | ||
| 230 | # CONFIG_HZ_1000 is not set | ||
| 231 | CONFIG_HZ=250 | ||
| 232 | # CONFIG_SCHED_HRTICK is not set | ||
| 233 | CONFIG_PREEMPT_NONE=y | ||
| 234 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 235 | # CONFIG_PREEMPT is not set | ||
| 236 | CONFIG_BINFMT_ELF=y | ||
| 237 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 238 | # CONFIG_HAVE_AOUT is not set | ||
| 239 | # CONFIG_BINFMT_MISC is not set | ||
| 240 | CONFIG_MATH_EMULATION=y | ||
| 241 | # CONFIG_IOMMU_HELPER is not set | ||
| 242 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y | ||
| 243 | CONFIG_ARCH_HAS_WALK_MEMORY=y | ||
| 244 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y | ||
| 245 | # CONFIG_IRQ_ALL_CPUS is not set | ||
| 246 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
| 247 | CONFIG_ARCH_POPULATES_NODE_MAP=y | ||
| 248 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 249 | CONFIG_FLATMEM_MANUAL=y | ||
| 250 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 251 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 252 | CONFIG_FLATMEM=y | ||
| 253 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 254 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 255 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 256 | CONFIG_MIGRATION=y | ||
| 257 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 258 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 259 | CONFIG_BOUNCE=y | ||
| 260 | CONFIG_VIRT_TO_BUS=y | ||
| 261 | CONFIG_UNEVICTABLE_LRU=y | ||
| 262 | CONFIG_HAVE_MLOCK=y | ||
| 263 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 264 | CONFIG_PPC_4K_PAGES=y | ||
| 265 | # CONFIG_PPC_16K_PAGES is not set | ||
| 266 | # CONFIG_PPC_64K_PAGES is not set | ||
| 267 | # CONFIG_PPC_256K_PAGES is not set | ||
| 268 | CONFIG_FORCE_MAX_ZONEORDER=11 | ||
| 269 | CONFIG_PROC_DEVICETREE=y | ||
| 270 | # CONFIG_CMDLINE_BOOL is not set | ||
| 271 | CONFIG_EXTRA_TARGETS="" | ||
| 272 | # CONFIG_PM is not set | ||
| 273 | CONFIG_SECCOMP=y | ||
| 274 | CONFIG_ISA_DMA_API=y | ||
| 275 | |||
| 276 | # | ||
| 277 | # Bus options | ||
| 278 | # | ||
| 279 | CONFIG_ZONE_DMA=y | ||
| 280 | CONFIG_PPC_INDIRECT_PCI=y | ||
| 281 | CONFIG_FSL_SOC=y | ||
| 282 | CONFIG_FSL_PCI=y | ||
| 283 | CONFIG_FSL_LBC=y | ||
| 284 | CONFIG_PPC_PCI_CHOICE=y | ||
| 285 | CONFIG_PCI=y | ||
| 286 | CONFIG_PCI_DOMAINS=y | ||
| 287 | CONFIG_PCI_SYSCALL=y | ||
| 288 | CONFIG_PCIEPORTBUS=y | ||
| 289 | CONFIG_PCIEAER=y | ||
| 290 | # CONFIG_PCIEASPM is not set | ||
| 291 | CONFIG_ARCH_SUPPORTS_MSI=y | ||
| 292 | CONFIG_PCI_MSI=y | ||
| 293 | CONFIG_PCI_LEGACY=y | ||
| 294 | # CONFIG_PCI_DEBUG is not set | ||
| 295 | # CONFIG_PCI_STUB is not set | ||
| 296 | # CONFIG_PCI_IOV is not set | ||
| 297 | # CONFIG_PCCARD is not set | ||
| 298 | # CONFIG_HOTPLUG_PCI is not set | ||
| 299 | # CONFIG_HAS_RAPIDIO is not set | ||
| 300 | |||
| 301 | # | ||
| 302 | # Advanced setup | ||
| 303 | # | ||
| 304 | CONFIG_ADVANCED_OPTIONS=y | ||
| 305 | CONFIG_LOWMEM_SIZE_BOOL=y | ||
| 306 | CONFIG_LOWMEM_SIZE=0x40000000 | ||
| 307 | # CONFIG_LOWMEM_CAM_NUM_BOOL is not set | ||
| 308 | CONFIG_LOWMEM_CAM_NUM=3 | ||
| 309 | # CONFIG_RELOCATABLE is not set | ||
| 310 | CONFIG_PAGE_OFFSET_BOOL=y | ||
| 311 | CONFIG_PAGE_OFFSET=0x80000000 | ||
| 312 | CONFIG_KERNEL_START_BOOL=y | ||
| 313 | CONFIG_KERNEL_START=0x80000000 | ||
| 314 | # CONFIG_PHYSICAL_START_BOOL is not set | ||
| 315 | CONFIG_PHYSICAL_START=0x00000000 | ||
| 316 | CONFIG_PHYSICAL_ALIGN=0x04000000 | ||
| 317 | CONFIG_TASK_SIZE_BOOL=y | ||
| 318 | CONFIG_TASK_SIZE=0x80000000 | ||
| 319 | CONFIG_NET=y | ||
| 320 | |||
| 321 | # | ||
| 322 | # Networking options | ||
| 323 | # | ||
| 324 | CONFIG_PACKET=y | ||
| 325 | # CONFIG_PACKET_MMAP is not set | ||
| 326 | CONFIG_UNIX=y | ||
| 327 | CONFIG_XFRM=y | ||
| 328 | CONFIG_XFRM_USER=y | ||
| 329 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 330 | # CONFIG_XFRM_MIGRATE is not set | ||
| 331 | # CONFIG_XFRM_STATISTICS is not set | ||
| 332 | CONFIG_NET_KEY=y | ||
| 333 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 334 | CONFIG_INET=y | ||
| 335 | CONFIG_IP_MULTICAST=y | ||
| 336 | CONFIG_IP_ADVANCED_ROUTER=y | ||
| 337 | CONFIG_ASK_IP_FIB_HASH=y | ||
| 338 | # CONFIG_IP_FIB_TRIE is not set | ||
| 339 | CONFIG_IP_FIB_HASH=y | ||
| 340 | CONFIG_IP_MULTIPLE_TABLES=y | ||
| 341 | CONFIG_IP_ROUTE_MULTIPATH=y | ||
| 342 | CONFIG_IP_ROUTE_VERBOSE=y | ||
| 343 | CONFIG_IP_PNP=y | ||
| 344 | CONFIG_IP_PNP_DHCP=y | ||
| 345 | CONFIG_IP_PNP_BOOTP=y | ||
| 346 | CONFIG_IP_PNP_RARP=y | ||
| 347 | CONFIG_NET_IPIP=y | ||
| 348 | CONFIG_NET_IPGRE=y | ||
| 349 | CONFIG_NET_IPGRE_BROADCAST=y | ||
| 350 | CONFIG_IP_MROUTE=y | ||
| 351 | CONFIG_IP_PIMSM_V1=y | ||
| 352 | CONFIG_IP_PIMSM_V2=y | ||
| 353 | CONFIG_ARPD=y | ||
| 354 | # CONFIG_SYN_COOKIES is not set | ||
| 355 | # CONFIG_INET_AH is not set | ||
| 356 | # CONFIG_INET_ESP is not set | ||
| 357 | # CONFIG_INET_IPCOMP is not set | ||
| 358 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 359 | CONFIG_INET_TUNNEL=y | ||
| 360 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 361 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 362 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 363 | # CONFIG_INET_LRO is not set | ||
| 364 | CONFIG_INET_DIAG=y | ||
| 365 | CONFIG_INET_TCP_DIAG=y | ||
| 366 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 367 | CONFIG_TCP_CONG_CUBIC=y | ||
| 368 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 369 | # CONFIG_TCP_MD5SIG is not set | ||
| 370 | CONFIG_IPV6=y | ||
| 371 | # CONFIG_IPV6_PRIVACY is not set | ||
| 372 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 373 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 374 | # CONFIG_INET6_AH is not set | ||
| 375 | # CONFIG_INET6_ESP is not set | ||
| 376 | # CONFIG_INET6_IPCOMP is not set | ||
| 377 | # CONFIG_IPV6_MIP6 is not set | ||
| 378 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 379 | # CONFIG_INET6_TUNNEL is not set | ||
| 380 | CONFIG_INET6_XFRM_MODE_TRANSPORT=y | ||
| 381 | CONFIG_INET6_XFRM_MODE_TUNNEL=y | ||
| 382 | CONFIG_INET6_XFRM_MODE_BEET=y | ||
| 383 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 384 | CONFIG_IPV6_SIT=y | ||
| 385 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 386 | # CONFIG_IPV6_TUNNEL is not set | ||
| 387 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 388 | # CONFIG_IPV6_MROUTE is not set | ||
| 389 | # CONFIG_NETWORK_SECMARK is not set | ||
| 390 | # CONFIG_NETFILTER is not set | ||
| 391 | # CONFIG_IP_DCCP is not set | ||
| 392 | # CONFIG_IP_SCTP is not set | ||
| 393 | # CONFIG_TIPC is not set | ||
| 394 | # CONFIG_ATM is not set | ||
| 395 | # CONFIG_BRIDGE is not set | ||
| 396 | # CONFIG_NET_DSA is not set | ||
| 397 | # CONFIG_VLAN_8021Q is not set | ||
| 398 | # CONFIG_DECNET is not set | ||
| 399 | # CONFIG_LLC2 is not set | ||
| 400 | # CONFIG_IPX is not set | ||
| 401 | # CONFIG_ATALK is not set | ||
| 402 | # CONFIG_X25 is not set | ||
| 403 | # CONFIG_LAPB is not set | ||
| 404 | # CONFIG_ECONET is not set | ||
| 405 | # CONFIG_WAN_ROUTER is not set | ||
| 406 | # CONFIG_PHONET is not set | ||
| 407 | # CONFIG_NET_SCHED is not set | ||
| 408 | # CONFIG_DCB is not set | ||
| 409 | |||
| 410 | # | ||
| 411 | # Network testing | ||
| 412 | # | ||
| 413 | # CONFIG_NET_PKTGEN is not set | ||
| 414 | # CONFIG_HAMRADIO is not set | ||
| 415 | # CONFIG_CAN is not set | ||
| 416 | # CONFIG_IRDA is not set | ||
| 417 | # CONFIG_BT is not set | ||
| 418 | # CONFIG_AF_RXRPC is not set | ||
| 419 | CONFIG_FIB_RULES=y | ||
| 420 | # CONFIG_WIRELESS is not set | ||
| 421 | # CONFIG_WIMAX is not set | ||
| 422 | # CONFIG_RFKILL is not set | ||
| 423 | # CONFIG_NET_9P is not set | ||
| 424 | |||
| 425 | # | ||
| 426 | # Device Drivers | ||
| 427 | # | ||
| 428 | |||
| 429 | # | ||
| 430 | # Generic Driver Options | ||
| 431 | # | ||
| 432 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 433 | CONFIG_STANDALONE=y | ||
| 434 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 435 | CONFIG_FW_LOADER=y | ||
| 436 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 437 | CONFIG_EXTRA_FIRMWARE="" | ||
| 438 | # CONFIG_DEBUG_DRIVER is not set | ||
| 439 | # CONFIG_DEBUG_DEVRES is not set | ||
| 440 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 441 | # CONFIG_CONNECTOR is not set | ||
| 442 | CONFIG_MTD=y | ||
| 443 | # CONFIG_MTD_DEBUG is not set | ||
| 444 | # CONFIG_MTD_CONCAT is not set | ||
| 445 | CONFIG_MTD_PARTITIONS=y | ||
| 446 | # CONFIG_MTD_TESTS is not set | ||
| 447 | CONFIG_MTD_REDBOOT_PARTS=y | ||
| 448 | CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 | ||
| 449 | # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set | ||
| 450 | # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set | ||
| 451 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 452 | CONFIG_MTD_OF_PARTS=y | ||
| 453 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 454 | |||
| 455 | # | ||
| 456 | # User Modules And Translation Layers | ||
| 457 | # | ||
| 458 | CONFIG_MTD_CHAR=y | ||
| 459 | CONFIG_MTD_BLKDEVS=y | ||
| 460 | CONFIG_MTD_BLOCK=y | ||
| 461 | # CONFIG_FTL is not set | ||
| 462 | # CONFIG_NFTL is not set | ||
| 463 | # CONFIG_INFTL is not set | ||
| 464 | # CONFIG_RFD_FTL is not set | ||
| 465 | # CONFIG_SSFDC is not set | ||
| 466 | # CONFIG_MTD_OOPS is not set | ||
| 467 | |||
| 468 | # | ||
| 469 | # RAM/ROM/Flash chip drivers | ||
| 470 | # | ||
| 471 | CONFIG_MTD_CFI=y | ||
| 472 | CONFIG_MTD_JEDECPROBE=y | ||
| 473 | CONFIG_MTD_GEN_PROBE=y | ||
| 474 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 475 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 476 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 478 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 479 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 480 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 481 | CONFIG_MTD_CFI_I1=y | ||
| 482 | CONFIG_MTD_CFI_I2=y | ||
| 483 | # CONFIG_MTD_CFI_I4 is not set | ||
| 484 | # CONFIG_MTD_CFI_I8 is not set | ||
| 485 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 486 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 487 | CONFIG_MTD_CFI_STAA=y | ||
| 488 | CONFIG_MTD_CFI_UTIL=y | ||
| 489 | # CONFIG_MTD_RAM is not set | ||
| 490 | # CONFIG_MTD_ROM is not set | ||
| 491 | # CONFIG_MTD_ABSENT is not set | ||
| 492 | |||
| 493 | # | ||
| 494 | # Mapping drivers for chip access | ||
| 495 | # | ||
| 496 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 497 | # CONFIG_MTD_PHYSMAP is not set | ||
| 498 | CONFIG_MTD_PHYSMAP_OF=y | ||
| 499 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 500 | # CONFIG_MTD_PLATRAM is not set | ||
| 501 | |||
| 502 | # | ||
| 503 | # Self-contained MTD device drivers | ||
| 504 | # | ||
| 505 | # CONFIG_MTD_PMC551 is not set | ||
| 506 | # CONFIG_MTD_SLRAM is not set | ||
| 507 | # CONFIG_MTD_PHRAM is not set | ||
| 508 | # CONFIG_MTD_MTDRAM is not set | ||
| 509 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 510 | |||
| 511 | # | ||
| 512 | # Disk-On-Chip Device Drivers | ||
| 513 | # | ||
| 514 | # CONFIG_MTD_DOC2000 is not set | ||
| 515 | # CONFIG_MTD_DOC2001 is not set | ||
| 516 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 517 | CONFIG_MTD_NAND=y | ||
| 518 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 519 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 520 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 521 | CONFIG_MTD_NAND_IDS=y | ||
| 522 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 523 | # CONFIG_MTD_NAND_CAFE is not set | ||
| 524 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 525 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 526 | # CONFIG_MTD_ALAUDA is not set | ||
| 527 | CONFIG_MTD_NAND_FSL_ELBC=y | ||
| 528 | CONFIG_MTD_NAND_FSL_UPM=y | ||
| 529 | # CONFIG_MTD_ONENAND is not set | ||
| 530 | |||
| 531 | # | ||
| 532 | # LPDDR flash memory drivers | ||
| 533 | # | ||
| 534 | # CONFIG_MTD_LPDDR is not set | ||
| 535 | |||
| 536 | # | ||
| 537 | # UBI - Unsorted block images | ||
| 538 | # | ||
| 539 | # CONFIG_MTD_UBI is not set | ||
| 540 | CONFIG_OF_DEVICE=y | ||
| 541 | CONFIG_OF_GPIO=y | ||
| 542 | CONFIG_OF_I2C=y | ||
| 543 | # CONFIG_PARPORT is not set | ||
| 544 | CONFIG_BLK_DEV=y | ||
| 545 | # CONFIG_BLK_DEV_FD is not set | ||
| 546 | # CONFIG_BLK_CPQ_DA is not set | ||
| 547 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
| 548 | # CONFIG_BLK_DEV_DAC960 is not set | ||
| 549 | # CONFIG_BLK_DEV_UMEM is not set | ||
| 550 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 551 | CONFIG_BLK_DEV_LOOP=y | ||
| 552 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 553 | CONFIG_BLK_DEV_NBD=y | ||
| 554 | # CONFIG_BLK_DEV_SX8 is not set | ||
| 555 | # CONFIG_BLK_DEV_UB is not set | ||
| 556 | CONFIG_BLK_DEV_RAM=y | ||
| 557 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 558 | CONFIG_BLK_DEV_RAM_SIZE=131072 | ||
| 559 | # CONFIG_BLK_DEV_XIP is not set | ||
| 560 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 561 | # CONFIG_ATA_OVER_ETH is not set | ||
| 562 | # CONFIG_BLK_DEV_HD is not set | ||
| 563 | CONFIG_MISC_DEVICES=y | ||
| 564 | # CONFIG_PHANTOM is not set | ||
| 565 | # CONFIG_SGI_IOC4 is not set | ||
| 566 | # CONFIG_TIFM_CORE is not set | ||
| 567 | # CONFIG_ICS932S401 is not set | ||
| 568 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 569 | # CONFIG_HP_ILO is not set | ||
| 570 | # CONFIG_ISL29003 is not set | ||
| 571 | # CONFIG_C2PORT is not set | ||
| 572 | |||
| 573 | # | ||
| 574 | # EEPROM support | ||
| 575 | # | ||
| 576 | # CONFIG_EEPROM_AT24 is not set | ||
| 577 | # CONFIG_EEPROM_LEGACY is not set | ||
| 578 | # CONFIG_EEPROM_93CX6 is not set | ||
| 579 | CONFIG_HAVE_IDE=y | ||
| 580 | # CONFIG_IDE is not set | ||
| 581 | |||
| 582 | # | ||
| 583 | # SCSI device support | ||
| 584 | # | ||
| 585 | # CONFIG_RAID_ATTRS is not set | ||
| 586 | CONFIG_SCSI=y | ||
| 587 | CONFIG_SCSI_DMA=y | ||
| 588 | # CONFIG_SCSI_TGT is not set | ||
| 589 | # CONFIG_SCSI_NETLINK is not set | ||
| 590 | CONFIG_SCSI_PROC_FS=y | ||
| 591 | |||
| 592 | # | ||
| 593 | # SCSI support type (disk, tape, CD-ROM) | ||
| 594 | # | ||
| 595 | CONFIG_BLK_DEV_SD=y | ||
| 596 | CONFIG_CHR_DEV_ST=y | ||
| 597 | # CONFIG_CHR_DEV_OSST is not set | ||
| 598 | CONFIG_BLK_DEV_SR=y | ||
| 599 | # CONFIG_BLK_DEV_SR_VENDOR is not set | ||
| 600 | CONFIG_CHR_DEV_SG=y | ||
| 601 | # CONFIG_CHR_DEV_SCH is not set | ||
| 602 | |||
| 603 | # | ||
| 604 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 605 | # | ||
| 606 | CONFIG_SCSI_MULTI_LUN=y | ||
| 607 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 608 | CONFIG_SCSI_LOGGING=y | ||
| 609 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 610 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 611 | |||
| 612 | # | ||
| 613 | # SCSI Transports | ||
| 614 | # | ||
| 615 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 616 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 617 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 618 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 619 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 620 | CONFIG_SCSI_LOWLEVEL=y | ||
| 621 | # CONFIG_ISCSI_TCP is not set | ||
| 622 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | ||
| 623 | # CONFIG_SCSI_3W_9XXX is not set | ||
| 624 | # CONFIG_SCSI_ACARD is not set | ||
| 625 | # CONFIG_SCSI_AACRAID is not set | ||
| 626 | # CONFIG_SCSI_AIC7XXX is not set | ||
| 627 | # CONFIG_SCSI_AIC7XXX_OLD is not set | ||
| 628 | # CONFIG_SCSI_AIC79XX is not set | ||
| 629 | # CONFIG_SCSI_AIC94XX is not set | ||
| 630 | # CONFIG_SCSI_DPT_I2O is not set | ||
| 631 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 632 | # CONFIG_SCSI_ARCMSR is not set | ||
| 633 | # CONFIG_MEGARAID_NEWGEN is not set | ||
| 634 | # CONFIG_MEGARAID_LEGACY is not set | ||
| 635 | # CONFIG_MEGARAID_SAS is not set | ||
| 636 | # CONFIG_SCSI_MPT2SAS is not set | ||
| 637 | # CONFIG_SCSI_HPTIOP is not set | ||
| 638 | # CONFIG_SCSI_BUSLOGIC is not set | ||
| 639 | # CONFIG_LIBFC is not set | ||
| 640 | # CONFIG_LIBFCOE is not set | ||
| 641 | # CONFIG_FCOE is not set | ||
| 642 | # CONFIG_SCSI_DMX3191D is not set | ||
| 643 | # CONFIG_SCSI_EATA is not set | ||
| 644 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | ||
| 645 | # CONFIG_SCSI_GDTH is not set | ||
| 646 | # CONFIG_SCSI_IPS is not set | ||
| 647 | # CONFIG_SCSI_INITIO is not set | ||
| 648 | # CONFIG_SCSI_INIA100 is not set | ||
| 649 | # CONFIG_SCSI_MVSAS is not set | ||
| 650 | # CONFIG_SCSI_STEX is not set | ||
| 651 | # CONFIG_SCSI_SYM53C8XX_2 is not set | ||
| 652 | # CONFIG_SCSI_IPR is not set | ||
| 653 | # CONFIG_SCSI_QLOGIC_1280 is not set | ||
| 654 | # CONFIG_SCSI_QLA_FC is not set | ||
| 655 | # CONFIG_SCSI_QLA_ISCSI is not set | ||
| 656 | # CONFIG_SCSI_LPFC is not set | ||
| 657 | # CONFIG_SCSI_DC395x is not set | ||
| 658 | # CONFIG_SCSI_DC390T is not set | ||
| 659 | # CONFIG_SCSI_NSP32 is not set | ||
| 660 | # CONFIG_SCSI_DEBUG is not set | ||
| 661 | # CONFIG_SCSI_SRP is not set | ||
| 662 | # CONFIG_SCSI_DH is not set | ||
| 663 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 664 | CONFIG_ATA=y | ||
| 665 | # CONFIG_ATA_NONSTANDARD is not set | ||
| 666 | CONFIG_SATA_PMP=y | ||
| 667 | CONFIG_SATA_AHCI=y | ||
| 668 | # CONFIG_SATA_SIL24 is not set | ||
| 669 | # CONFIG_SATA_FSL is not set | ||
| 670 | CONFIG_ATA_SFF=y | ||
| 671 | # CONFIG_SATA_SVW is not set | ||
| 672 | # CONFIG_ATA_PIIX is not set | ||
| 673 | # CONFIG_SATA_MV is not set | ||
| 674 | # CONFIG_SATA_NV is not set | ||
| 675 | # CONFIG_PDC_ADMA is not set | ||
| 676 | # CONFIG_SATA_QSTOR is not set | ||
| 677 | # CONFIG_SATA_PROMISE is not set | ||
| 678 | # CONFIG_SATA_SX4 is not set | ||
| 679 | # CONFIG_SATA_SIL is not set | ||
| 680 | # CONFIG_SATA_SIS is not set | ||
| 681 | # CONFIG_SATA_ULI is not set | ||
| 682 | # CONFIG_SATA_VIA is not set | ||
| 683 | # CONFIG_SATA_VITESSE is not set | ||
| 684 | # CONFIG_SATA_INIC162X is not set | ||
| 685 | CONFIG_PATA_ALI=y | ||
| 686 | # CONFIG_PATA_AMD is not set | ||
| 687 | # CONFIG_PATA_ARTOP is not set | ||
| 688 | # CONFIG_PATA_ATIIXP is not set | ||
| 689 | # CONFIG_PATA_CMD640_PCI is not set | ||
| 690 | # CONFIG_PATA_CMD64X is not set | ||
| 691 | # CONFIG_PATA_CS5520 is not set | ||
| 692 | # CONFIG_PATA_CS5530 is not set | ||
| 693 | # CONFIG_PATA_CYPRESS is not set | ||
| 694 | # CONFIG_PATA_EFAR is not set | ||
| 695 | # CONFIG_ATA_GENERIC is not set | ||
| 696 | # CONFIG_PATA_HPT366 is not set | ||
| 697 | # CONFIG_PATA_HPT37X is not set | ||
| 698 | # CONFIG_PATA_HPT3X2N is not set | ||
| 699 | # CONFIG_PATA_HPT3X3 is not set | ||
| 700 | # CONFIG_PATA_IT821X is not set | ||
| 701 | # CONFIG_PATA_IT8213 is not set | ||
| 702 | # CONFIG_PATA_JMICRON is not set | ||
| 703 | # CONFIG_PATA_TRIFLEX is not set | ||
| 704 | # CONFIG_PATA_MARVELL is not set | ||
| 705 | # CONFIG_PATA_MPIIX is not set | ||
| 706 | # CONFIG_PATA_OLDPIIX is not set | ||
| 707 | # CONFIG_PATA_NETCELL is not set | ||
| 708 | # CONFIG_PATA_NINJA32 is not set | ||
| 709 | # CONFIG_PATA_NS87410 is not set | ||
| 710 | # CONFIG_PATA_NS87415 is not set | ||
| 711 | # CONFIG_PATA_OPTI is not set | ||
| 712 | # CONFIG_PATA_OPTIDMA is not set | ||
| 713 | # CONFIG_PATA_PDC_OLD is not set | ||
| 714 | # CONFIG_PATA_RADISYS is not set | ||
| 715 | # CONFIG_PATA_RZ1000 is not set | ||
| 716 | # CONFIG_PATA_SC1200 is not set | ||
| 717 | # CONFIG_PATA_SERVERWORKS is not set | ||
| 718 | # CONFIG_PATA_PDC2027X is not set | ||
| 719 | # CONFIG_PATA_SIL680 is not set | ||
| 720 | # CONFIG_PATA_SIS is not set | ||
| 721 | # CONFIG_PATA_VIA is not set | ||
| 722 | # CONFIG_PATA_WINBOND is not set | ||
| 723 | # CONFIG_PATA_PLATFORM is not set | ||
| 724 | # CONFIG_PATA_SCH is not set | ||
| 725 | # CONFIG_MD is not set | ||
| 726 | # CONFIG_FUSION is not set | ||
| 727 | |||
| 728 | # | ||
| 729 | # IEEE 1394 (FireWire) support | ||
| 730 | # | ||
| 731 | |||
| 732 | # | ||
| 733 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 734 | # | ||
| 735 | # CONFIG_FIREWIRE is not set | ||
| 736 | # CONFIG_IEEE1394 is not set | ||
| 737 | # CONFIG_I2O is not set | ||
| 738 | # CONFIG_MACINTOSH_DRIVERS is not set | ||
| 739 | CONFIG_NETDEVICES=y | ||
| 740 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 741 | CONFIG_DUMMY=y | ||
| 742 | # CONFIG_BONDING is not set | ||
| 743 | # CONFIG_MACVLAN is not set | ||
| 744 | # CONFIG_EQUALIZER is not set | ||
| 745 | # CONFIG_TUN is not set | ||
| 746 | # CONFIG_VETH is not set | ||
| 747 | # CONFIG_ARCNET is not set | ||
| 748 | CONFIG_PHYLIB=y | ||
| 749 | |||
| 750 | # | ||
| 751 | # MII PHY device drivers | ||
| 752 | # | ||
| 753 | # CONFIG_MARVELL_PHY is not set | ||
| 754 | # CONFIG_DAVICOM_PHY is not set | ||
| 755 | # CONFIG_QSEMI_PHY is not set | ||
| 756 | # CONFIG_LXT_PHY is not set | ||
| 757 | # CONFIG_CICADA_PHY is not set | ||
| 758 | # CONFIG_VITESSE_PHY is not set | ||
| 759 | # CONFIG_SMSC_PHY is not set | ||
| 760 | CONFIG_BROADCOM_PHY=y | ||
| 761 | # CONFIG_ICPLUS_PHY is not set | ||
| 762 | # CONFIG_REALTEK_PHY is not set | ||
| 763 | # CONFIG_NATIONAL_PHY is not set | ||
| 764 | # CONFIG_STE10XP is not set | ||
| 765 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 766 | # CONFIG_FIXED_PHY is not set | ||
| 767 | # CONFIG_MDIO_BITBANG is not set | ||
| 768 | CONFIG_NET_ETHERNET=y | ||
| 769 | CONFIG_MII=y | ||
| 770 | # CONFIG_HAPPYMEAL is not set | ||
| 771 | # CONFIG_SUNGEM is not set | ||
| 772 | # CONFIG_CASSINI is not set | ||
| 773 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 774 | # CONFIG_ETHOC is not set | ||
| 775 | # CONFIG_DNET is not set | ||
| 776 | # CONFIG_NET_TULIP is not set | ||
| 777 | # CONFIG_HP100 is not set | ||
| 778 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 779 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 780 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 781 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 782 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 783 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 784 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 785 | # CONFIG_NET_PCI is not set | ||
| 786 | # CONFIG_B44 is not set | ||
| 787 | # CONFIG_ATL2 is not set | ||
| 788 | CONFIG_NETDEV_1000=y | ||
| 789 | # CONFIG_ACENIC is not set | ||
| 790 | # CONFIG_DL2K is not set | ||
| 791 | CONFIG_E1000=y | ||
| 792 | # CONFIG_E1000E is not set | ||
| 793 | # CONFIG_IP1000 is not set | ||
| 794 | # CONFIG_IGB is not set | ||
| 795 | # CONFIG_IGBVF is not set | ||
| 796 | # CONFIG_NS83820 is not set | ||
| 797 | # CONFIG_HAMACHI is not set | ||
| 798 | # CONFIG_YELLOWFIN is not set | ||
| 799 | # CONFIG_R8169 is not set | ||
| 800 | # CONFIG_SIS190 is not set | ||
| 801 | # CONFIG_SKGE is not set | ||
| 802 | # CONFIG_SKY2 is not set | ||
| 803 | # CONFIG_VIA_VELOCITY is not set | ||
| 804 | # CONFIG_TIGON3 is not set | ||
| 805 | # CONFIG_BNX2 is not set | ||
| 806 | CONFIG_FSL_PQ_MDIO=y | ||
| 807 | CONFIG_GIANFAR=y | ||
| 808 | # CONFIG_QLA3XXX is not set | ||
| 809 | # CONFIG_ATL1 is not set | ||
| 810 | # CONFIG_ATL1E is not set | ||
| 811 | # CONFIG_ATL1C is not set | ||
| 812 | # CONFIG_JME is not set | ||
| 813 | # CONFIG_NETDEV_10000 is not set | ||
| 814 | # CONFIG_TR is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # Wireless LAN | ||
| 818 | # | ||
| 819 | # CONFIG_WLAN_PRE80211 is not set | ||
| 820 | # CONFIG_WLAN_80211 is not set | ||
| 821 | |||
| 822 | # | ||
| 823 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 824 | # | ||
| 825 | |||
| 826 | # | ||
| 827 | # USB Network Adapters | ||
| 828 | # | ||
| 829 | # CONFIG_USB_CATC is not set | ||
| 830 | # CONFIG_USB_KAWETH is not set | ||
| 831 | # CONFIG_USB_PEGASUS is not set | ||
| 832 | # CONFIG_USB_RTL8150 is not set | ||
| 833 | # CONFIG_USB_USBNET is not set | ||
| 834 | # CONFIG_WAN is not set | ||
| 835 | # CONFIG_FDDI is not set | ||
| 836 | # CONFIG_HIPPI is not set | ||
| 837 | # CONFIG_PPP is not set | ||
| 838 | # CONFIG_SLIP is not set | ||
| 839 | # CONFIG_NET_FC is not set | ||
| 840 | # CONFIG_NETCONSOLE is not set | ||
| 841 | # CONFIG_NETPOLL is not set | ||
| 842 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 843 | # CONFIG_ISDN is not set | ||
| 844 | # CONFIG_PHONE is not set | ||
| 845 | |||
| 846 | # | ||
| 847 | # Input device support | ||
| 848 | # | ||
| 849 | CONFIG_INPUT=y | ||
| 850 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 851 | # CONFIG_INPUT_POLLDEV is not set | ||
| 852 | |||
| 853 | # | ||
| 854 | # Userland interfaces | ||
| 855 | # | ||
| 856 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 857 | # CONFIG_INPUT_JOYDEV is not set | ||
| 858 | # CONFIG_INPUT_EVDEV is not set | ||
| 859 | # CONFIG_INPUT_EVBUG is not set | ||
| 860 | |||
| 861 | # | ||
| 862 | # Input Device Drivers | ||
| 863 | # | ||
| 864 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 865 | # CONFIG_INPUT_MOUSE is not set | ||
| 866 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 867 | # CONFIG_INPUT_TABLET is not set | ||
| 868 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 869 | # CONFIG_INPUT_MISC is not set | ||
| 870 | |||
| 871 | # | ||
| 872 | # Hardware I/O ports | ||
| 873 | # | ||
| 874 | CONFIG_SERIO=y | ||
| 875 | CONFIG_SERIO_I8042=y | ||
| 876 | CONFIG_SERIO_SERPORT=y | ||
| 877 | # CONFIG_SERIO_PCIPS2 is not set | ||
| 878 | CONFIG_SERIO_LIBPS2=y | ||
| 879 | # CONFIG_SERIO_RAW is not set | ||
| 880 | # CONFIG_SERIO_XILINX_XPS_PS2 is not set | ||
| 881 | # CONFIG_GAMEPORT is not set | ||
| 882 | |||
| 883 | # | ||
| 884 | # Character devices | ||
| 885 | # | ||
| 886 | CONFIG_VT=y | ||
| 887 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 888 | CONFIG_VT_CONSOLE=y | ||
| 889 | CONFIG_HW_CONSOLE=y | ||
| 890 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 891 | CONFIG_DEVKMEM=y | ||
| 892 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 893 | # CONFIG_NOZOMI is not set | ||
| 894 | |||
| 895 | # | ||
| 896 | # Serial drivers | ||
| 897 | # | ||
| 898 | CONFIG_SERIAL_8250=y | ||
| 899 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 900 | CONFIG_SERIAL_8250_PCI=y | ||
| 901 | CONFIG_SERIAL_8250_NR_UARTS=2 | ||
| 902 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | ||
| 903 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 904 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 905 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 906 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 907 | CONFIG_SERIAL_8250_RSA=y | ||
| 908 | |||
| 909 | # | ||
| 910 | # Non-8250 serial port support | ||
| 911 | # | ||
| 912 | # CONFIG_SERIAL_UARTLITE is not set | ||
| 913 | CONFIG_SERIAL_CORE=y | ||
| 914 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 915 | # CONFIG_SERIAL_JSM is not set | ||
| 916 | # CONFIG_SERIAL_OF_PLATFORM is not set | ||
| 917 | CONFIG_UNIX98_PTYS=y | ||
| 918 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 919 | CONFIG_LEGACY_PTYS=y | ||
| 920 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 921 | # CONFIG_HVC_UDBG is not set | ||
| 922 | # CONFIG_IPMI_HANDLER is not set | ||
| 923 | # CONFIG_HW_RANDOM is not set | ||
| 924 | CONFIG_NVRAM=y | ||
| 925 | # CONFIG_R3964 is not set | ||
| 926 | # CONFIG_APPLICOM is not set | ||
| 927 | # CONFIG_RAW_DRIVER is not set | ||
| 928 | # CONFIG_TCG_TPM is not set | ||
| 929 | CONFIG_DEVPORT=y | ||
| 930 | CONFIG_I2C=y | ||
| 931 | CONFIG_I2C_BOARDINFO=y | ||
| 932 | CONFIG_I2C_CHARDEV=y | ||
| 933 | CONFIG_I2C_HELPER_AUTO=y | ||
| 934 | |||
| 935 | # | ||
| 936 | # I2C Hardware Bus support | ||
| 937 | # | ||
| 938 | |||
| 939 | # | ||
| 940 | # PC SMBus host controller drivers | ||
| 941 | # | ||
| 942 | # CONFIG_I2C_ALI1535 is not set | ||
| 943 | # CONFIG_I2C_ALI1563 is not set | ||
| 944 | # CONFIG_I2C_ALI15X3 is not set | ||
| 945 | # CONFIG_I2C_AMD756 is not set | ||
| 946 | # CONFIG_I2C_AMD8111 is not set | ||
| 947 | # CONFIG_I2C_I801 is not set | ||
| 948 | # CONFIG_I2C_ISCH is not set | ||
| 949 | # CONFIG_I2C_PIIX4 is not set | ||
| 950 | # CONFIG_I2C_NFORCE2 is not set | ||
| 951 | # CONFIG_I2C_SIS5595 is not set | ||
| 952 | # CONFIG_I2C_SIS630 is not set | ||
| 953 | # CONFIG_I2C_SIS96X is not set | ||
| 954 | # CONFIG_I2C_VIA is not set | ||
| 955 | # CONFIG_I2C_VIAPRO is not set | ||
| 956 | |||
| 957 | # | ||
| 958 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 959 | # | ||
| 960 | # CONFIG_I2C_GPIO is not set | ||
| 961 | CONFIG_I2C_MPC=y | ||
| 962 | # CONFIG_I2C_OCORES is not set | ||
| 963 | # CONFIG_I2C_SIMTEC is not set | ||
| 964 | |||
| 965 | # | ||
| 966 | # External I2C/SMBus adapter drivers | ||
| 967 | # | ||
| 968 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 969 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 970 | # CONFIG_I2C_TINY_USB is not set | ||
| 971 | |||
| 972 | # | ||
| 973 | # Graphics adapter I2C/DDC channel drivers | ||
| 974 | # | ||
| 975 | # CONFIG_I2C_VOODOO3 is not set | ||
| 976 | |||
| 977 | # | ||
| 978 | # Other I2C/SMBus bus drivers | ||
| 979 | # | ||
| 980 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 981 | # CONFIG_I2C_STUB is not set | ||
| 982 | |||
| 983 | # | ||
| 984 | # Miscellaneous I2C Chip support | ||
| 985 | # | ||
| 986 | # CONFIG_DS1682 is not set | ||
| 987 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 988 | # CONFIG_PCF8575 is not set | ||
| 989 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 990 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 991 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 992 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 993 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 994 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 995 | # CONFIG_SPI is not set | ||
| 996 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 997 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 998 | CONFIG_GPIOLIB=y | ||
| 999 | # CONFIG_DEBUG_GPIO is not set | ||
| 1000 | CONFIG_GPIO_SYSFS=y | ||
| 1001 | |||
| 1002 | # | ||
| 1003 | # Memory mapped GPIO expanders: | ||
| 1004 | # | ||
| 1005 | # CONFIG_GPIO_XILINX is not set | ||
| 1006 | |||
| 1007 | # | ||
| 1008 | # I2C GPIO expanders: | ||
| 1009 | # | ||
| 1010 | # CONFIG_GPIO_MAX732X is not set | ||
| 1011 | CONFIG_GPIO_PCA953X=y | ||
| 1012 | # CONFIG_GPIO_PCF857X is not set | ||
| 1013 | |||
| 1014 | # | ||
| 1015 | # PCI GPIO expanders: | ||
| 1016 | # | ||
| 1017 | # CONFIG_GPIO_BT8XX is not set | ||
| 1018 | |||
| 1019 | # | ||
| 1020 | # SPI GPIO expanders: | ||
| 1021 | # | ||
| 1022 | # CONFIG_W1 is not set | ||
| 1023 | # CONFIG_POWER_SUPPLY is not set | ||
| 1024 | CONFIG_HWMON=y | ||
| 1025 | # CONFIG_HWMON_VID is not set | ||
| 1026 | # CONFIG_SENSORS_AD7414 is not set | ||
| 1027 | # CONFIG_SENSORS_AD7418 is not set | ||
| 1028 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 1029 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 1030 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 1031 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 1032 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 1033 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 1034 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 1035 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 1036 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 1037 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 1038 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 1039 | CONFIG_SENSORS_DS1621=y | ||
| 1040 | # CONFIG_SENSORS_I5K_AMB is not set | ||
| 1041 | # CONFIG_SENSORS_F71805F is not set | ||
| 1042 | # CONFIG_SENSORS_F71882FG is not set | ||
| 1043 | # CONFIG_SENSORS_F75375S is not set | ||
| 1044 | # CONFIG_SENSORS_G760A is not set | ||
| 1045 | # CONFIG_SENSORS_GL518SM is not set | ||
| 1046 | # CONFIG_SENSORS_GL520SM is not set | ||
| 1047 | # CONFIG_SENSORS_IT87 is not set | ||
| 1048 | # CONFIG_SENSORS_LM63 is not set | ||
| 1049 | # CONFIG_SENSORS_LM75 is not set | ||
| 1050 | # CONFIG_SENSORS_LM77 is not set | ||
| 1051 | # CONFIG_SENSORS_LM78 is not set | ||
| 1052 | # CONFIG_SENSORS_LM80 is not set | ||
| 1053 | # CONFIG_SENSORS_LM83 is not set | ||
| 1054 | # CONFIG_SENSORS_LM85 is not set | ||
| 1055 | # CONFIG_SENSORS_LM87 is not set | ||
| 1056 | CONFIG_SENSORS_LM90=y | ||
| 1057 | # CONFIG_SENSORS_LM92 is not set | ||
| 1058 | # CONFIG_SENSORS_LM93 is not set | ||
| 1059 | # CONFIG_SENSORS_LTC4215 is not set | ||
| 1060 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 1061 | # CONFIG_SENSORS_LM95241 is not set | ||
| 1062 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 1063 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 1064 | # CONFIG_SENSORS_PC87360 is not set | ||
| 1065 | # CONFIG_SENSORS_PC87427 is not set | ||
| 1066 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 1067 | # CONFIG_SENSORS_SHT15 is not set | ||
| 1068 | # CONFIG_SENSORS_SIS5595 is not set | ||
| 1069 | # CONFIG_SENSORS_DME1737 is not set | ||
| 1070 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 1071 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 1072 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 1073 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 1074 | # CONFIG_SENSORS_THMC50 is not set | ||
| 1075 | # CONFIG_SENSORS_VIA686A is not set | ||
| 1076 | # CONFIG_SENSORS_VT1211 is not set | ||
| 1077 | # CONFIG_SENSORS_VT8231 is not set | ||
| 1078 | # CONFIG_SENSORS_W83781D is not set | ||
| 1079 | # CONFIG_SENSORS_W83791D is not set | ||
| 1080 | # CONFIG_SENSORS_W83792D is not set | ||
| 1081 | # CONFIG_SENSORS_W83793 is not set | ||
| 1082 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 1083 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 1084 | # CONFIG_SENSORS_W83627HF is not set | ||
| 1085 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 1086 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1087 | # CONFIG_THERMAL is not set | ||
| 1088 | # CONFIG_THERMAL_HWMON is not set | ||
| 1089 | CONFIG_WATCHDOG=y | ||
| 1090 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 1091 | |||
| 1092 | # | ||
| 1093 | # Watchdog Device Drivers | ||
| 1094 | # | ||
| 1095 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1096 | # CONFIG_ALIM7101_WDT is not set | ||
| 1097 | # CONFIG_BOOKE_WDT is not set | ||
| 1098 | |||
| 1099 | # | ||
| 1100 | # PCI-based Watchdog Cards | ||
| 1101 | # | ||
| 1102 | # CONFIG_PCIPCWATCHDOG is not set | ||
| 1103 | # CONFIG_WDTPCI is not set | ||
| 1104 | |||
| 1105 | # | ||
| 1106 | # USB-based Watchdog Cards | ||
| 1107 | # | ||
| 1108 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1109 | CONFIG_SSB_POSSIBLE=y | ||
| 1110 | |||
| 1111 | # | ||
| 1112 | # Sonics Silicon Backplane | ||
| 1113 | # | ||
| 1114 | # CONFIG_SSB is not set | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Multifunction device drivers | ||
| 1118 | # | ||
| 1119 | # CONFIG_MFD_CORE is not set | ||
| 1120 | # CONFIG_MFD_SM501 is not set | ||
| 1121 | # CONFIG_HTC_PASIC3 is not set | ||
| 1122 | # CONFIG_TPS65010 is not set | ||
| 1123 | # CONFIG_TWL4030_CORE is not set | ||
| 1124 | # CONFIG_MFD_TMIO is not set | ||
| 1125 | # CONFIG_PMIC_DA903X is not set | ||
| 1126 | # CONFIG_MFD_WM8400 is not set | ||
| 1127 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1128 | # CONFIG_MFD_PCF50633 is not set | ||
| 1129 | # CONFIG_REGULATOR is not set | ||
| 1130 | |||
| 1131 | # | ||
| 1132 | # Multimedia devices | ||
| 1133 | # | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Multimedia core support | ||
| 1137 | # | ||
| 1138 | # CONFIG_VIDEO_DEV is not set | ||
| 1139 | # CONFIG_DVB_CORE is not set | ||
| 1140 | # CONFIG_VIDEO_MEDIA is not set | ||
| 1141 | |||
| 1142 | # | ||
| 1143 | # Multimedia drivers | ||
| 1144 | # | ||
| 1145 | # CONFIG_DAB is not set | ||
| 1146 | |||
| 1147 | # | ||
| 1148 | # Graphics support | ||
| 1149 | # | ||
| 1150 | # CONFIG_AGP is not set | ||
| 1151 | # CONFIG_DRM is not set | ||
| 1152 | # CONFIG_VGASTATE is not set | ||
| 1153 | CONFIG_VIDEO_OUTPUT_CONTROL=y | ||
| 1154 | # CONFIG_FB is not set | ||
| 1155 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1156 | |||
| 1157 | # | ||
| 1158 | # Display device support | ||
| 1159 | # | ||
| 1160 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 1161 | |||
| 1162 | # | ||
| 1163 | # Console display driver support | ||
| 1164 | # | ||
| 1165 | CONFIG_VGA_CONSOLE=y | ||
| 1166 | # CONFIG_VGACON_SOFT_SCROLLBACK is not set | ||
| 1167 | CONFIG_DUMMY_CONSOLE=y | ||
| 1168 | # CONFIG_SOUND is not set | ||
| 1169 | CONFIG_HID_SUPPORT=y | ||
| 1170 | CONFIG_HID=y | ||
| 1171 | # CONFIG_HID_DEBUG is not set | ||
| 1172 | # CONFIG_HIDRAW is not set | ||
| 1173 | |||
| 1174 | # | ||
| 1175 | # USB Input Devices | ||
| 1176 | # | ||
| 1177 | CONFIG_USB_HID=y | ||
| 1178 | # CONFIG_HID_PID is not set | ||
| 1179 | # CONFIG_USB_HIDDEV is not set | ||
| 1180 | |||
| 1181 | # | ||
| 1182 | # Special HID drivers | ||
| 1183 | # | ||
| 1184 | # CONFIG_HID_A4TECH is not set | ||
| 1185 | # CONFIG_HID_APPLE is not set | ||
| 1186 | # CONFIG_HID_BELKIN is not set | ||
| 1187 | # CONFIG_HID_CHERRY is not set | ||
| 1188 | # CONFIG_HID_CHICONY is not set | ||
| 1189 | # CONFIG_HID_CYPRESS is not set | ||
| 1190 | # CONFIG_DRAGONRISE_FF is not set | ||
| 1191 | # CONFIG_HID_EZKEY is not set | ||
| 1192 | # CONFIG_HID_KYE is not set | ||
| 1193 | # CONFIG_HID_GYRATION is not set | ||
| 1194 | # CONFIG_HID_KENSINGTON is not set | ||
| 1195 | # CONFIG_HID_LOGITECH is not set | ||
| 1196 | # CONFIG_HID_MICROSOFT is not set | ||
| 1197 | # CONFIG_HID_MONTEREY is not set | ||
| 1198 | # CONFIG_HID_NTRIG is not set | ||
| 1199 | # CONFIG_HID_PANTHERLORD is not set | ||
| 1200 | # CONFIG_HID_PETALYNX is not set | ||
| 1201 | # CONFIG_HID_SAMSUNG is not set | ||
| 1202 | # CONFIG_HID_SONY is not set | ||
| 1203 | # CONFIG_HID_SUNPLUS is not set | ||
| 1204 | # CONFIG_GREENASIA_FF is not set | ||
| 1205 | # CONFIG_HID_TOPSEED is not set | ||
| 1206 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1207 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1208 | CONFIG_USB_SUPPORT=y | ||
| 1209 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1210 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1211 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 1212 | CONFIG_USB=y | ||
| 1213 | # CONFIG_USB_DEBUG is not set | ||
| 1214 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1215 | |||
| 1216 | # | ||
| 1217 | # Miscellaneous USB options | ||
| 1218 | # | ||
| 1219 | CONFIG_USB_DEVICEFS=y | ||
| 1220 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 1221 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1222 | # CONFIG_USB_OTG is not set | ||
| 1223 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1224 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1225 | CONFIG_USB_MON=y | ||
| 1226 | # CONFIG_USB_WUSB is not set | ||
| 1227 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1228 | |||
| 1229 | # | ||
| 1230 | # USB Host Controller Drivers | ||
| 1231 | # | ||
| 1232 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1233 | # CONFIG_USB_EHCI_HCD is not set | ||
| 1234 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1235 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1236 | CONFIG_USB_ISP1760_HCD=y | ||
| 1237 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1238 | # CONFIG_USB_UHCI_HCD is not set | ||
| 1239 | # CONFIG_USB_SL811_HCD is not set | ||
| 1240 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1241 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1242 | # CONFIG_USB_HWA_HCD is not set | ||
| 1243 | |||
| 1244 | # | ||
| 1245 | # USB Device Class drivers | ||
| 1246 | # | ||
| 1247 | # CONFIG_USB_ACM is not set | ||
| 1248 | # CONFIG_USB_PRINTER is not set | ||
| 1249 | # CONFIG_USB_WDM is not set | ||
| 1250 | # CONFIG_USB_TMC is not set | ||
| 1251 | |||
| 1252 | # | ||
| 1253 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 1254 | # | ||
| 1255 | |||
| 1256 | # | ||
| 1257 | # also be needed; see USB_STORAGE Help for more info | ||
| 1258 | # | ||
| 1259 | CONFIG_USB_STORAGE=y | ||
| 1260 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1261 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1262 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1263 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1264 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1265 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1266 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1267 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1268 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1269 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1270 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1271 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1272 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1273 | |||
| 1274 | # | ||
| 1275 | # USB Imaging devices | ||
| 1276 | # | ||
| 1277 | # CONFIG_USB_MDC800 is not set | ||
| 1278 | # CONFIG_USB_MICROTEK is not set | ||
| 1279 | |||
| 1280 | # | ||
| 1281 | # USB port drivers | ||
| 1282 | # | ||
| 1283 | # CONFIG_USB_SERIAL is not set | ||
| 1284 | |||
| 1285 | # | ||
| 1286 | # USB Miscellaneous drivers | ||
| 1287 | # | ||
| 1288 | # CONFIG_USB_EMI62 is not set | ||
| 1289 | # CONFIG_USB_EMI26 is not set | ||
| 1290 | # CONFIG_USB_ADUTUX is not set | ||
| 1291 | # CONFIG_USB_SEVSEG is not set | ||
| 1292 | # CONFIG_USB_RIO500 is not set | ||
| 1293 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1294 | # CONFIG_USB_LCD is not set | ||
| 1295 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1296 | # CONFIG_USB_LED is not set | ||
| 1297 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1298 | # CONFIG_USB_CYTHERM is not set | ||
| 1299 | # CONFIG_USB_IDMOUSE is not set | ||
| 1300 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1301 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1302 | # CONFIG_USB_LD is not set | ||
| 1303 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1304 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1305 | # CONFIG_USB_TEST is not set | ||
| 1306 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1307 | # CONFIG_USB_VST is not set | ||
| 1308 | # CONFIG_USB_GADGET is not set | ||
| 1309 | |||
| 1310 | # | ||
| 1311 | # OTG and related infrastructure | ||
| 1312 | # | ||
| 1313 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1314 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1315 | # CONFIG_UWB is not set | ||
| 1316 | # CONFIG_MMC is not set | ||
| 1317 | # CONFIG_MEMSTICK is not set | ||
| 1318 | CONFIG_NEW_LEDS=y | ||
| 1319 | CONFIG_LEDS_CLASS=y | ||
| 1320 | |||
| 1321 | # | ||
| 1322 | # LED drivers | ||
| 1323 | # | ||
| 1324 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1325 | CONFIG_LEDS_GPIO=y | ||
| 1326 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1327 | CONFIG_LEDS_GPIO_OF=y | ||
| 1328 | # CONFIG_LEDS_LP5521 is not set | ||
| 1329 | CONFIG_LEDS_PCA955X=y | ||
| 1330 | # CONFIG_LEDS_BD2802 is not set | ||
| 1331 | |||
| 1332 | # | ||
| 1333 | # LED Triggers | ||
| 1334 | # | ||
| 1335 | CONFIG_LEDS_TRIGGERS=y | ||
| 1336 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1337 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1338 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1339 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1340 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1341 | |||
| 1342 | # | ||
| 1343 | # iptables trigger is under Netfilter config (LED target) | ||
| 1344 | # | ||
| 1345 | # CONFIG_ACCESSIBILITY is not set | ||
| 1346 | # CONFIG_INFINIBAND is not set | ||
| 1347 | CONFIG_EDAC=y | ||
| 1348 | |||
| 1349 | # | ||
| 1350 | # Reporting subsystems | ||
| 1351 | # | ||
| 1352 | # CONFIG_EDAC_DEBUG is not set | ||
| 1353 | CONFIG_EDAC_MM_EDAC=y | ||
| 1354 | CONFIG_EDAC_MPC85XX=y | ||
| 1355 | # CONFIG_EDAC_AMD8131 is not set | ||
| 1356 | # CONFIG_EDAC_AMD8111 is not set | ||
| 1357 | CONFIG_RTC_LIB=y | ||
| 1358 | CONFIG_RTC_CLASS=y | ||
| 1359 | CONFIG_RTC_HCTOSYS=y | ||
| 1360 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1361 | # CONFIG_RTC_DEBUG is not set | ||
| 1362 | |||
| 1363 | # | ||
| 1364 | # RTC interfaces | ||
| 1365 | # | ||
| 1366 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1367 | CONFIG_RTC_INTF_PROC=y | ||
| 1368 | CONFIG_RTC_INTF_DEV=y | ||
| 1369 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1370 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1371 | |||
| 1372 | # | ||
| 1373 | # I2C RTC drivers | ||
| 1374 | # | ||
| 1375 | CONFIG_RTC_DRV_DS1307=y | ||
| 1376 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1377 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1378 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1379 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1380 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1381 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1382 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1383 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1384 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1385 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1386 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1387 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1388 | |||
| 1389 | # | ||
| 1390 | # SPI RTC drivers | ||
| 1391 | # | ||
| 1392 | |||
| 1393 | # | ||
| 1394 | # Platform RTC drivers | ||
| 1395 | # | ||
| 1396 | CONFIG_RTC_DRV_CMOS=y | ||
| 1397 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1398 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1399 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1400 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1401 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1402 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1403 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1404 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1405 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1406 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1407 | |||
| 1408 | # | ||
| 1409 | # on-CPU RTC drivers | ||
| 1410 | # | ||
| 1411 | # CONFIG_RTC_DRV_GENERIC is not set | ||
| 1412 | CONFIG_DMADEVICES=y | ||
| 1413 | |||
| 1414 | # | ||
| 1415 | # DMA Devices | ||
| 1416 | # | ||
| 1417 | CONFIG_FSL_DMA=y | ||
| 1418 | CONFIG_DMA_ENGINE=y | ||
| 1419 | |||
| 1420 | # | ||
| 1421 | # DMA Clients | ||
| 1422 | # | ||
| 1423 | CONFIG_NET_DMA=y | ||
| 1424 | # CONFIG_ASYNC_TX_DMA is not set | ||
| 1425 | # CONFIG_DMATEST is not set | ||
| 1426 | # CONFIG_AUXDISPLAY is not set | ||
| 1427 | # CONFIG_UIO is not set | ||
| 1428 | # CONFIG_STAGING is not set | ||
| 1429 | |||
| 1430 | # | ||
| 1431 | # File systems | ||
| 1432 | # | ||
| 1433 | CONFIG_EXT2_FS=y | ||
| 1434 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1435 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1436 | CONFIG_EXT3_FS=y | ||
| 1437 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1438 | CONFIG_EXT3_FS_XATTR=y | ||
| 1439 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1440 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1441 | # CONFIG_EXT4_FS is not set | ||
| 1442 | CONFIG_JBD=y | ||
| 1443 | CONFIG_FS_MBCACHE=y | ||
| 1444 | # CONFIG_REISERFS_FS is not set | ||
| 1445 | # CONFIG_JFS_FS is not set | ||
| 1446 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1447 | CONFIG_FILE_LOCKING=y | ||
| 1448 | # CONFIG_XFS_FS is not set | ||
| 1449 | # CONFIG_GFS2_FS is not set | ||
| 1450 | # CONFIG_OCFS2_FS is not set | ||
| 1451 | # CONFIG_BTRFS_FS is not set | ||
| 1452 | CONFIG_DNOTIFY=y | ||
| 1453 | CONFIG_INOTIFY=y | ||
| 1454 | CONFIG_INOTIFY_USER=y | ||
| 1455 | # CONFIG_QUOTA is not set | ||
| 1456 | # CONFIG_AUTOFS_FS is not set | ||
| 1457 | # CONFIG_AUTOFS4_FS is not set | ||
| 1458 | # CONFIG_FUSE_FS is not set | ||
| 1459 | |||
| 1460 | # | ||
| 1461 | # Caches | ||
| 1462 | # | ||
| 1463 | # CONFIG_FSCACHE is not set | ||
| 1464 | |||
| 1465 | # | ||
| 1466 | # CD-ROM/DVD Filesystems | ||
| 1467 | # | ||
| 1468 | CONFIG_ISO9660_FS=y | ||
| 1469 | CONFIG_JOLIET=y | ||
| 1470 | CONFIG_ZISOFS=y | ||
| 1471 | CONFIG_UDF_FS=y | ||
| 1472 | CONFIG_UDF_NLS=y | ||
| 1473 | |||
| 1474 | # | ||
| 1475 | # DOS/FAT/NT Filesystems | ||
| 1476 | # | ||
| 1477 | CONFIG_FAT_FS=y | ||
| 1478 | CONFIG_MSDOS_FS=y | ||
| 1479 | CONFIG_VFAT_FS=y | ||
| 1480 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1481 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1482 | # CONFIG_NTFS_FS is not set | ||
| 1483 | |||
| 1484 | # | ||
| 1485 | # Pseudo filesystems | ||
| 1486 | # | ||
| 1487 | CONFIG_PROC_FS=y | ||
| 1488 | CONFIG_PROC_KCORE=y | ||
| 1489 | CONFIG_PROC_SYSCTL=y | ||
| 1490 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1491 | CONFIG_SYSFS=y | ||
| 1492 | CONFIG_TMPFS=y | ||
| 1493 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1494 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1495 | # CONFIG_CONFIGFS_FS is not set | ||
| 1496 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1497 | # CONFIG_ADFS_FS is not set | ||
| 1498 | # CONFIG_AFFS_FS is not set | ||
| 1499 | # CONFIG_HFS_FS is not set | ||
| 1500 | # CONFIG_HFSPLUS_FS is not set | ||
| 1501 | # CONFIG_BEFS_FS is not set | ||
| 1502 | # CONFIG_BFS_FS is not set | ||
| 1503 | # CONFIG_EFS_FS is not set | ||
| 1504 | CONFIG_JFFS2_FS=y | ||
| 1505 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1506 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1507 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1508 | CONFIG_JFFS2_SUMMARY=y | ||
| 1509 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1510 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1511 | CONFIG_JFFS2_ZLIB=y | ||
| 1512 | # CONFIG_JFFS2_LZO is not set | ||
| 1513 | CONFIG_JFFS2_RTIME=y | ||
| 1514 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1515 | # CONFIG_CRAMFS is not set | ||
| 1516 | # CONFIG_SQUASHFS is not set | ||
| 1517 | # CONFIG_VXFS_FS is not set | ||
| 1518 | # CONFIG_MINIX_FS is not set | ||
| 1519 | # CONFIG_OMFS_FS is not set | ||
| 1520 | # CONFIG_HPFS_FS is not set | ||
| 1521 | # CONFIG_QNX4FS_FS is not set | ||
| 1522 | # CONFIG_ROMFS_FS is not set | ||
| 1523 | # CONFIG_SYSV_FS is not set | ||
| 1524 | # CONFIG_UFS_FS is not set | ||
| 1525 | # CONFIG_NILFS2_FS is not set | ||
| 1526 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1527 | CONFIG_NFS_FS=y | ||
| 1528 | CONFIG_NFS_V3=y | ||
| 1529 | # CONFIG_NFS_V3_ACL is not set | ||
| 1530 | # CONFIG_NFS_V4 is not set | ||
| 1531 | CONFIG_ROOT_NFS=y | ||
| 1532 | CONFIG_NFSD=y | ||
| 1533 | # CONFIG_NFSD_V3 is not set | ||
| 1534 | # CONFIG_NFSD_V4 is not set | ||
| 1535 | CONFIG_LOCKD=y | ||
| 1536 | CONFIG_LOCKD_V4=y | ||
| 1537 | CONFIG_EXPORTFS=y | ||
| 1538 | CONFIG_NFS_COMMON=y | ||
| 1539 | CONFIG_SUNRPC=y | ||
| 1540 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1541 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1542 | # CONFIG_SMB_FS is not set | ||
| 1543 | # CONFIG_CIFS is not set | ||
| 1544 | # CONFIG_NCP_FS is not set | ||
| 1545 | # CONFIG_CODA_FS is not set | ||
| 1546 | # CONFIG_AFS_FS is not set | ||
| 1547 | |||
| 1548 | # | ||
| 1549 | # Partition Types | ||
| 1550 | # | ||
| 1551 | CONFIG_PARTITION_ADVANCED=y | ||
| 1552 | # CONFIG_ACORN_PARTITION is not set | ||
| 1553 | # CONFIG_OSF_PARTITION is not set | ||
| 1554 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1555 | # CONFIG_ATARI_PARTITION is not set | ||
| 1556 | # CONFIG_MAC_PARTITION is not set | ||
| 1557 | CONFIG_MSDOS_PARTITION=y | ||
| 1558 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1559 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1560 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1561 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1562 | # CONFIG_LDM_PARTITION is not set | ||
| 1563 | # CONFIG_SGI_PARTITION is not set | ||
| 1564 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1565 | # CONFIG_SUN_PARTITION is not set | ||
| 1566 | # CONFIG_KARMA_PARTITION is not set | ||
| 1567 | # CONFIG_EFI_PARTITION is not set | ||
| 1568 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1569 | CONFIG_NLS=y | ||
| 1570 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1571 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1572 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1573 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1574 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1575 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1576 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1577 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1578 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1579 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1580 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1581 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1582 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1583 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1584 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1585 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1586 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1587 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1588 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1589 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1590 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1591 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1592 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1593 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1594 | # CONFIG_NLS_ASCII is not set | ||
| 1595 | CONFIG_NLS_ISO8859_1=y | ||
| 1596 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1597 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1598 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1599 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1600 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1601 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1602 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1603 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1604 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1605 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1606 | # CONFIG_NLS_KOI8_R is not set | ||
| 1607 | # CONFIG_NLS_KOI8_U is not set | ||
| 1608 | # CONFIG_NLS_UTF8 is not set | ||
| 1609 | # CONFIG_DLM is not set | ||
| 1610 | # CONFIG_BINARY_PRINTF is not set | ||
| 1611 | |||
| 1612 | # | ||
| 1613 | # Library routines | ||
| 1614 | # | ||
| 1615 | CONFIG_BITREVERSE=y | ||
| 1616 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1617 | # CONFIG_CRC_CCITT is not set | ||
| 1618 | # CONFIG_CRC16 is not set | ||
| 1619 | CONFIG_CRC_T10DIF=y | ||
| 1620 | CONFIG_CRC_ITU_T=y | ||
| 1621 | CONFIG_CRC32=y | ||
| 1622 | # CONFIG_CRC7 is not set | ||
| 1623 | # CONFIG_LIBCRC32C is not set | ||
| 1624 | CONFIG_ZLIB_INFLATE=y | ||
| 1625 | CONFIG_ZLIB_DEFLATE=y | ||
| 1626 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1627 | CONFIG_HAS_IOMEM=y | ||
| 1628 | CONFIG_HAS_IOPORT=y | ||
| 1629 | CONFIG_HAS_DMA=y | ||
| 1630 | CONFIG_HAVE_LMB=y | ||
| 1631 | CONFIG_NLATTR=y | ||
| 1632 | |||
| 1633 | # | ||
| 1634 | # Kernel hacking | ||
| 1635 | # | ||
| 1636 | # CONFIG_PRINTK_TIME is not set | ||
| 1637 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1638 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1639 | CONFIG_FRAME_WARN=1024 | ||
| 1640 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1641 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1642 | # CONFIG_DEBUG_FS is not set | ||
| 1643 | # CONFIG_HEADERS_CHECK is not set | ||
| 1644 | CONFIG_DEBUG_KERNEL=y | ||
| 1645 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1646 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1647 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1648 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1649 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1650 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1651 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1652 | CONFIG_SCHED_DEBUG=y | ||
| 1653 | # CONFIG_SCHEDSTATS is not set | ||
| 1654 | # CONFIG_TIMER_STATS is not set | ||
| 1655 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1656 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1657 | # CONFIG_SLUB_STATS is not set | ||
| 1658 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1659 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1660 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1661 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1662 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1663 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1664 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1665 | # CONFIG_DEBUG_HIGHMEM is not set | ||
| 1666 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1667 | # CONFIG_DEBUG_INFO is not set | ||
| 1668 | # CONFIG_DEBUG_VM is not set | ||
| 1669 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1670 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1671 | # CONFIG_DEBUG_LIST is not set | ||
| 1672 | # CONFIG_DEBUG_SG is not set | ||
| 1673 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1674 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1675 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1676 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1677 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1678 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1679 | # CONFIG_FAULT_INJECTION is not set | ||
| 1680 | # CONFIG_LATENCYTOP is not set | ||
| 1681 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1682 | # CONFIG_DEBUG_PAGEALLOC is not set | ||
| 1683 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1684 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | ||
| 1685 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 1686 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | ||
| 1687 | CONFIG_TRACING_SUPPORT=y | ||
| 1688 | |||
| 1689 | # | ||
| 1690 | # Tracers | ||
| 1691 | # | ||
| 1692 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1693 | # CONFIG_SCHED_TRACER is not set | ||
| 1694 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1695 | # CONFIG_EVENT_TRACER is not set | ||
| 1696 | # CONFIG_BOOT_TRACER is not set | ||
| 1697 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1698 | # CONFIG_STACK_TRACER is not set | ||
| 1699 | # CONFIG_KMEMTRACE is not set | ||
| 1700 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1701 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1702 | # CONFIG_SAMPLES is not set | ||
| 1703 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1704 | # CONFIG_KGDB is not set | ||
| 1705 | CONFIG_PRINT_STACK_DEPTH=64 | ||
| 1706 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1707 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1708 | # CONFIG_CODE_PATCHING_SELFTEST is not set | ||
| 1709 | # CONFIG_FTR_FIXUP_SELFTEST is not set | ||
| 1710 | # CONFIG_MSI_BITMAP_SELFTEST is not set | ||
| 1711 | # CONFIG_XMON is not set | ||
| 1712 | # CONFIG_IRQSTACKS is not set | ||
| 1713 | # CONFIG_BDI_SWITCH is not set | ||
| 1714 | # CONFIG_PPC_EARLY_DEBUG is not set | ||
| 1715 | |||
| 1716 | # | ||
| 1717 | # Security options | ||
| 1718 | # | ||
| 1719 | # CONFIG_KEYS is not set | ||
| 1720 | # CONFIG_SECURITY is not set | ||
| 1721 | # CONFIG_SECURITYFS is not set | ||
| 1722 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1723 | CONFIG_CRYPTO=y | ||
| 1724 | |||
| 1725 | # | ||
| 1726 | # Crypto core or helper | ||
| 1727 | # | ||
| 1728 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1729 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1730 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1731 | CONFIG_CRYPTO_AEAD2=y | ||
| 1732 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1733 | CONFIG_CRYPTO_HASH=y | ||
| 1734 | CONFIG_CRYPTO_HASH2=y | ||
| 1735 | CONFIG_CRYPTO_RNG2=y | ||
| 1736 | CONFIG_CRYPTO_PCOMP=y | ||
| 1737 | CONFIG_CRYPTO_MANAGER=y | ||
| 1738 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1739 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1740 | # CONFIG_CRYPTO_NULL is not set | ||
| 1741 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 1742 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1743 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1744 | # CONFIG_CRYPTO_TEST is not set | ||
| 1745 | |||
| 1746 | # | ||
| 1747 | # Authenticated Encryption with Associated Data | ||
| 1748 | # | ||
| 1749 | # CONFIG_CRYPTO_CCM is not set | ||
| 1750 | # CONFIG_CRYPTO_GCM is not set | ||
| 1751 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1752 | |||
| 1753 | # | ||
| 1754 | # Block modes | ||
| 1755 | # | ||
| 1756 | # CONFIG_CRYPTO_CBC is not set | ||
| 1757 | # CONFIG_CRYPTO_CTR is not set | ||
| 1758 | # CONFIG_CRYPTO_CTS is not set | ||
| 1759 | # CONFIG_CRYPTO_ECB is not set | ||
| 1760 | # CONFIG_CRYPTO_LRW is not set | ||
| 1761 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1762 | # CONFIG_CRYPTO_XTS is not set | ||
| 1763 | |||
| 1764 | # | ||
| 1765 | # Hash modes | ||
| 1766 | # | ||
| 1767 | CONFIG_CRYPTO_HMAC=y | ||
| 1768 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1769 | |||
| 1770 | # | ||
| 1771 | # Digest | ||
| 1772 | # | ||
| 1773 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1774 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1775 | CONFIG_CRYPTO_MD5=y | ||
| 1776 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1777 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1778 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1779 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1780 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1781 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1782 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1783 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1784 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1785 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1786 | |||
| 1787 | # | ||
| 1788 | # Ciphers | ||
| 1789 | # | ||
| 1790 | # CONFIG_CRYPTO_AES is not set | ||
| 1791 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1792 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1793 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1794 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1795 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1796 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1797 | # CONFIG_CRYPTO_DES is not set | ||
| 1798 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1799 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1800 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1801 | # CONFIG_CRYPTO_SEED is not set | ||
| 1802 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1803 | # CONFIG_CRYPTO_TEA is not set | ||
| 1804 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1805 | |||
| 1806 | # | ||
| 1807 | # Compression | ||
| 1808 | # | ||
| 1809 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1810 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1811 | # CONFIG_CRYPTO_LZO is not set | ||
| 1812 | |||
| 1813 | # | ||
| 1814 | # Random Number Generation | ||
| 1815 | # | ||
| 1816 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1817 | CONFIG_CRYPTO_HW=y | ||
| 1818 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
| 1819 | # CONFIG_CRYPTO_DEV_TALITOS is not set | ||
| 1820 | # CONFIG_PPC_CLOCK is not set | ||
| 1821 | # CONFIG_VIRTUALIZATION is not set | ||
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 7d044dfd9236..12dc7c409616 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig | |||
| @@ -1808,7 +1808,7 @@ CONFIG_PCF8575=m | |||
| 1808 | CONFIG_SENSORS_PCA9539=m | 1808 | CONFIG_SENSORS_PCA9539=m |
| 1809 | CONFIG_SENSORS_PCF8591=m | 1809 | CONFIG_SENSORS_PCF8591=m |
| 1810 | # CONFIG_TPS65010 is not set | 1810 | # CONFIG_TPS65010 is not set |
| 1811 | CONFIG_SENSORS_MAX6875=m | 1811 | CONFIG_EEPROM_MAX6875=m |
| 1812 | CONFIG_SENSORS_TSL2550=m | 1812 | CONFIG_SENSORS_TSL2550=m |
| 1813 | CONFIG_MCU_MPC8349EMITX=m | 1813 | CONFIG_MCU_MPC8349EMITX=m |
| 1814 | # CONFIG_I2C_DEBUG_CORE is not set | 1814 | # CONFIG_I2C_DEBUG_CORE is not set |
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h index b70d6e53b303..a71c9c1455a7 100644 --- a/arch/powerpc/include/asm/8253pit.h +++ b/arch/powerpc/include/asm/8253pit.h | |||
| @@ -1,10 +1,3 @@ | |||
| 1 | #ifndef _ASM_POWERPC_8253PIT_H | ||
| 2 | #define _ASM_POWERPC_8253PIT_H | ||
| 3 | |||
| 4 | /* | 1 | /* |
| 5 | * 8253/8254 Programmable Interval Timer | 2 | * 8253/8254 Programmable Interval Timer |
| 6 | */ | 3 | */ |
| 7 | |||
| 8 | #define PIT_TICK_RATE 1193182UL | ||
| 9 | |||
| 10 | #endif /* _ASM_POWERPC_8253PIT_H */ | ||
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index b401950f5259..4012483b1899 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h | |||
| @@ -470,8 +470,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) | |||
| 470 | 470 | ||
| 471 | #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) | 471 | #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) |
| 472 | 472 | ||
| 473 | #else /* __powerpc64__ */ | ||
| 474 | #include <asm-generic/atomic64.h> | ||
| 475 | |||
| 473 | #endif /* __powerpc64__ */ | 476 | #endif /* __powerpc64__ */ |
| 474 | 477 | ||
| 475 | #include <asm-generic/atomic.h> | 478 | #include <asm-generic/atomic-long.h> |
| 476 | #endif /* __KERNEL__ */ | 479 | #endif /* __KERNEL__ */ |
| 477 | #endif /* _ASM_POWERPC_ATOMIC_H_ */ | 480 | #endif /* _ASM_POWERPC_ATOMIC_H_ */ |
diff --git a/arch/powerpc/include/asm/bitsperlong.h b/arch/powerpc/include/asm/bitsperlong.h new file mode 100644 index 000000000000..5f1659032c40 --- /dev/null +++ b/arch/powerpc/include/asm/bitsperlong.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef __ASM_POWERPC_BITSPERLONG_H | ||
| 2 | #define __ASM_POWERPC_BITSPERLONG_H | ||
| 3 | |||
| 4 | #if defined(__powerpc64__) | ||
| 5 | # define __BITS_PER_LONG 64 | ||
| 6 | #else | ||
| 7 | # define __BITS_PER_LONG 32 | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #include <asm-generic/bitsperlong.h> | ||
| 11 | |||
| 12 | #endif /* __ASM_POWERPC_BITSPERLONG_H */ | ||
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h index 0f5e8ff59a85..990ff191da8b 100644 --- a/arch/powerpc/include/asm/cpm2.h +++ b/arch/powerpc/include/asm/cpm2.h | |||
| @@ -14,10 +14,6 @@ | |||
| 14 | #include <asm/cpm.h> | 14 | #include <asm/cpm.h> |
| 15 | #include <sysdev/fsl_soc.h> | 15 | #include <sysdev/fsl_soc.h> |
| 16 | 16 | ||
| 17 | #ifdef CONFIG_PPC_85xx | ||
| 18 | #define CPM_MAP_ADDR (get_immrbase() + 0x80000) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | /* CPM Command register. | 17 | /* CPM Command register. |
| 22 | */ | 18 | */ |
| 23 | #define CPM_CR_RST ((uint)0x80000000) | 19 | #define CPM_CR_RST ((uint)0x80000000) |
diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/delay.h index f9200a65c632..1e2eb41fa057 100644 --- a/arch/powerpc/include/asm/delay.h +++ b/arch/powerpc/include/asm/delay.h | |||
| @@ -2,8 +2,11 @@ | |||
| 2 | #define _ASM_POWERPC_DELAY_H | 2 | #define _ASM_POWERPC_DELAY_H |
| 3 | #ifdef __KERNEL__ | 3 | #ifdef __KERNEL__ |
| 4 | 4 | ||
| 5 | #include <asm/time.h> | ||
| 6 | |||
| 5 | /* | 7 | /* |
| 6 | * Copyright 1996, Paul Mackerras. | 8 | * Copyright 1996, Paul Mackerras. |
| 9 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | ||
| 7 | * | 10 | * |
| 8 | * This program is free software; you can redistribute it and/or | 11 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License | 12 | * modify it under the terms of the GNU General Public License |
| @@ -30,5 +33,38 @@ extern void udelay(unsigned long usecs); | |||
| 30 | #define mdelay(n) udelay((n) * 1000) | 33 | #define mdelay(n) udelay((n) * 1000) |
| 31 | #endif | 34 | #endif |
| 32 | 35 | ||
| 36 | /** | ||
| 37 | * spin_event_timeout - spin until a condition gets true or a timeout elapses | ||
| 38 | * @condition: a C expression to evalate | ||
| 39 | * @timeout: timeout, in microseconds | ||
| 40 | * @delay: the number of microseconds to delay between each evaluation of | ||
| 41 | * @condition | ||
| 42 | * | ||
| 43 | * The process spins until the condition evaluates to true (non-zero) or the | ||
| 44 | * timeout elapses. The return value of this macro is the value of | ||
| 45 | * @condition when the loop terminates. This allows you to determine the cause | ||
| 46 | * of the loop terminates. If the return value is zero, then you know a | ||
| 47 | * timeout has occurred. | ||
| 48 | * | ||
| 49 | * This primary purpose of this macro is to poll on a hardware register | ||
| 50 | * until a status bit changes. The timeout ensures that the loop still | ||
| 51 | * terminates even if the bit never changes. The delay is for devices that | ||
| 52 | * need a delay in between successive reads. | ||
| 53 | * | ||
| 54 | * gcc will optimize out the if-statement if @delay is a constant. | ||
| 55 | */ | ||
| 56 | #define spin_event_timeout(condition, timeout, delay) \ | ||
| 57 | ({ \ | ||
| 58 | typeof(condition) __ret; \ | ||
| 59 | unsigned long __loops = tb_ticks_per_usec * timeout; \ | ||
| 60 | unsigned long __start = get_tbl(); \ | ||
| 61 | while (!(__ret = (condition)) && (tb_ticks_since(__start) <= __loops)) \ | ||
| 62 | if (delay) \ | ||
| 63 | udelay(delay); \ | ||
| 64 | else \ | ||
| 65 | cpu_relax(); \ | ||
| 66 | __ret; \ | ||
| 67 | }) | ||
| 68 | |||
| 33 | #endif /* __KERNEL__ */ | 69 | #endif /* __KERNEL__ */ |
| 34 | #endif /* _ASM_POWERPC_DELAY_H */ | 70 | #endif /* _ASM_POWERPC_DELAY_H */ |
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index cb448d68452c..3d9e887c3c0c 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h | |||
| @@ -15,9 +15,18 @@ | |||
| 15 | #include <linux/scatterlist.h> | 15 | #include <linux/scatterlist.h> |
| 16 | #include <linux/dma-attrs.h> | 16 | #include <linux/dma-attrs.h> |
| 17 | #include <asm/io.h> | 17 | #include <asm/io.h> |
| 18 | #include <asm/swiotlb.h> | ||
| 18 | 19 | ||
| 19 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | 20 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) |
| 20 | 21 | ||
| 22 | /* Some dma direct funcs must be visible for use in other dma_ops */ | ||
| 23 | extern void *dma_direct_alloc_coherent(struct device *dev, size_t size, | ||
| 24 | dma_addr_t *dma_handle, gfp_t flag); | ||
| 25 | extern void dma_direct_free_coherent(struct device *dev, size_t size, | ||
| 26 | void *vaddr, dma_addr_t dma_handle); | ||
| 27 | |||
| 28 | extern unsigned long get_dma_direct_offset(struct device *dev); | ||
| 29 | |||
| 21 | #ifdef CONFIG_NOT_COHERENT_CACHE | 30 | #ifdef CONFIG_NOT_COHERENT_CACHE |
| 22 | /* | 31 | /* |
| 23 | * DMA-consistent mapping functions for PowerPCs that don't support | 32 | * DMA-consistent mapping functions for PowerPCs that don't support |
| @@ -78,6 +87,8 @@ struct dma_mapping_ops { | |||
| 78 | dma_addr_t dma_address, size_t size, | 87 | dma_addr_t dma_address, size_t size, |
| 79 | enum dma_data_direction direction, | 88 | enum dma_data_direction direction, |
| 80 | struct dma_attrs *attrs); | 89 | struct dma_attrs *attrs); |
| 90 | int (*addr_needs_map)(struct device *dev, dma_addr_t addr, | ||
| 91 | size_t size); | ||
| 81 | #ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS | 92 | #ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS |
| 82 | void (*sync_single_range_for_cpu)(struct device *hwdev, | 93 | void (*sync_single_range_for_cpu)(struct device *hwdev, |
| 83 | dma_addr_t dma_handle, unsigned long offset, | 94 | dma_addr_t dma_handle, unsigned long offset, |
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h index d6b4a12cdeff..014a624f4c8e 100644 --- a/arch/powerpc/include/asm/elf.h +++ b/arch/powerpc/include/asm/elf.h | |||
| @@ -256,11 +256,11 @@ do { \ | |||
| 256 | * even if we have an executable stack. | 256 | * even if we have an executable stack. |
| 257 | */ | 257 | */ |
| 258 | # define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ | 258 | # define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ |
| 259 | (exec_stk != EXSTACK_DISABLE_X) : 0) | 259 | (exec_stk == EXSTACK_DEFAULT) : 0) |
| 260 | #else | 260 | #else |
| 261 | # define SET_PERSONALITY(ex) \ | 261 | # define SET_PERSONALITY(ex) \ |
| 262 | set_personality(PER_LINUX | (current->personality & (~PER_MASK))) | 262 | set_personality(PER_LINUX | (current->personality & (~PER_MASK))) |
| 263 | # define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) | 263 | # define elf_read_implies_exec(ex, exec_stk) (exec_stk == EXSTACK_DEFAULT) |
| 264 | #endif /* __powerpc64__ */ | 264 | #endif /* __powerpc64__ */ |
| 265 | 265 | ||
| 266 | extern int dcache_bsize; | 266 | extern int dcache_bsize; |
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h new file mode 100644 index 000000000000..9154e8526732 --- /dev/null +++ b/arch/powerpc/include/asm/emulated_ops.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Sony Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; version 2 of the License. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. | ||
| 15 | * If not, see <http://www.gnu.org/licenses/>. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _ASM_POWERPC_EMULATED_OPS_H | ||
| 19 | #define _ASM_POWERPC_EMULATED_OPS_H | ||
| 20 | |||
| 21 | #include <asm/atomic.h> | ||
| 22 | |||
| 23 | |||
| 24 | #ifdef CONFIG_PPC_EMULATED_STATS | ||
| 25 | |||
| 26 | struct ppc_emulated_entry { | ||
| 27 | const char *name; | ||
| 28 | atomic_t val; | ||
| 29 | }; | ||
| 30 | |||
| 31 | extern struct ppc_emulated { | ||
| 32 | #ifdef CONFIG_ALTIVEC | ||
| 33 | struct ppc_emulated_entry altivec; | ||
| 34 | #endif | ||
| 35 | struct ppc_emulated_entry dcba; | ||
| 36 | struct ppc_emulated_entry dcbz; | ||
| 37 | struct ppc_emulated_entry fp_pair; | ||
| 38 | struct ppc_emulated_entry isel; | ||
| 39 | struct ppc_emulated_entry mcrxr; | ||
| 40 | struct ppc_emulated_entry mfpvr; | ||
| 41 | struct ppc_emulated_entry multiple; | ||
| 42 | struct ppc_emulated_entry popcntb; | ||
| 43 | struct ppc_emulated_entry spe; | ||
| 44 | struct ppc_emulated_entry string; | ||
| 45 | struct ppc_emulated_entry unaligned; | ||
| 46 | #ifdef CONFIG_MATH_EMULATION | ||
| 47 | struct ppc_emulated_entry math; | ||
| 48 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | ||
| 49 | struct ppc_emulated_entry 8xx; | ||
| 50 | #endif | ||
| 51 | #ifdef CONFIG_VSX | ||
| 52 | struct ppc_emulated_entry vsx; | ||
| 53 | #endif | ||
| 54 | } ppc_emulated; | ||
| 55 | |||
| 56 | extern u32 ppc_warn_emulated; | ||
| 57 | |||
| 58 | extern void ppc_warn_emulated_print(const char *type); | ||
| 59 | |||
| 60 | #define PPC_WARN_EMULATED(type) \ | ||
| 61 | do { \ | ||
| 62 | atomic_inc(&ppc_emulated.type.val); \ | ||
| 63 | if (ppc_warn_emulated) \ | ||
| 64 | ppc_warn_emulated_print(ppc_emulated.type.name); \ | ||
| 65 | } while (0) | ||
| 66 | |||
| 67 | #else /* !CONFIG_PPC_EMULATED_STATS */ | ||
| 68 | |||
| 69 | #define PPC_WARN_EMULATED(type) do { } while (0) | ||
| 70 | |||
| 71 | #endif /* !CONFIG_PPC_EMULATED_STATS */ | ||
| 72 | |||
| 73 | #endif /* _ASM_POWERPC_EMULATED_OPS_H */ | ||
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h index e4094a5cb05b..cbd4dfa4bce2 100644 --- a/arch/powerpc/include/asm/feature-fixups.h +++ b/arch/powerpc/include/asm/feature-fixups.h | |||
| @@ -8,8 +8,6 @@ | |||
| 8 | * 2 of the License, or (at your option) any later version. | 8 | * 2 of the License, or (at your option) any later version. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #ifdef __ASSEMBLY__ | ||
| 12 | |||
| 13 | /* | 11 | /* |
| 14 | * Feature section common macros | 12 | * Feature section common macros |
| 15 | * | 13 | * |
| @@ -23,10 +21,12 @@ | |||
| 23 | /* 64 bits kernel, 32 bits code (ie. vdso32) */ | 21 | /* 64 bits kernel, 32 bits code (ie. vdso32) */ |
| 24 | #define FTR_ENTRY_LONG .llong | 22 | #define FTR_ENTRY_LONG .llong |
| 25 | #define FTR_ENTRY_OFFSET .long 0xffffffff; .long | 23 | #define FTR_ENTRY_OFFSET .long 0xffffffff; .long |
| 24 | #elif defined(CONFIG_PPC64) | ||
| 25 | #define FTR_ENTRY_LONG .llong | ||
| 26 | #define FTR_ENTRY_OFFSET .llong | ||
| 26 | #else | 27 | #else |
| 27 | /* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */ | 28 | #define FTR_ENTRY_LONG .long |
| 28 | #define FTR_ENTRY_LONG PPC_LONG | 29 | #define FTR_ENTRY_OFFSET .long |
| 29 | #define FTR_ENTRY_OFFSET PPC_LONG | ||
| 30 | #endif | 30 | #endif |
| 31 | 31 | ||
| 32 | #define START_FTR_SECTION(label) label##1: | 32 | #define START_FTR_SECTION(label) label##1: |
| @@ -141,6 +141,21 @@ label##5: \ | |||
| 141 | #define ALT_FW_FTR_SECTION_END_IFCLR(msk) \ | 141 | #define ALT_FW_FTR_SECTION_END_IFCLR(msk) \ |
| 142 | ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97) | 142 | ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97) |
| 143 | 143 | ||
| 144 | #ifndef __ASSEMBLY__ | ||
| 145 | |||
| 146 | #define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \ | ||
| 147 | stringify_in_c(BEGIN_MMU_FTR_SECTION) \ | ||
| 148 | section_if "; " \ | ||
| 149 | stringify_in_c(MMU_FTR_SECTION_ELSE) \ | ||
| 150 | section_else "; " \ | ||
| 151 | stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val))) | ||
| 152 | |||
| 153 | #define ASM_MMU_FTR_IFSET(section_if, section_else, msk) \ | ||
| 154 | ASM_MMU_FTR_IF(section_if, section_else, (msk), (msk)) | ||
| 155 | |||
| 156 | #define ASM_MMU_FTR_IFCLR(section_if, section_else, msk) \ | ||
| 157 | ASM_MMU_FTR_IF(section_if, section_else, (msk), 0) | ||
| 158 | |||
| 144 | #endif /* __ASSEMBLY__ */ | 159 | #endif /* __ASSEMBLY__ */ |
| 145 | 160 | ||
| 146 | /* LWSYNC feature sections */ | 161 | /* LWSYNC feature sections */ |
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 63a4f779f531..1b5a21041f9b 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h | |||
| @@ -95,8 +95,8 @@ struct fsl_lbc_bank { | |||
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | struct fsl_lbc_regs { | 97 | struct fsl_lbc_regs { |
| 98 | struct fsl_lbc_bank bank[8]; | 98 | struct fsl_lbc_bank bank[12]; |
| 99 | u8 res0[0x28]; | 99 | u8 res0[0x8]; |
| 100 | __be32 mar; /**< UPM Address Register */ | 100 | __be32 mar; /**< UPM Address Register */ |
| 101 | u8 res1[0x4]; | 101 | u8 res1[0x4]; |
| 102 | __be32 mamr; /**< UPMA Mode Register */ | 102 | __be32 mamr; /**< UPMA Mode Register */ |
diff --git a/arch/powerpc/include/asm/fsldma.h b/arch/powerpc/include/asm/fsldma.h new file mode 100644 index 000000000000..a67aeed17d40 --- /dev/null +++ b/arch/powerpc/include/asm/fsldma.h | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* | ||
| 2 | * Freescale MPC83XX / MPC85XX DMA Controller | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Ira W. Snyder <iws@ovro.caltech.edu> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ARCH_POWERPC_ASM_FSLDMA_H__ | ||
| 12 | #define __ARCH_POWERPC_ASM_FSLDMA_H__ | ||
| 13 | |||
| 14 | #include <linux/dmaengine.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Definitions for the Freescale DMA controller's DMA_SLAVE implemention | ||
| 18 | * | ||
| 19 | * The Freescale DMA_SLAVE implementation was designed to handle many-to-many | ||
| 20 | * transfers. An example usage would be an accelerated copy between two | ||
| 21 | * scatterlists. Another example use would be an accelerated copy from | ||
| 22 | * multiple non-contiguous device buffers into a single scatterlist. | ||
| 23 | * | ||
| 24 | * A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This | ||
| 25 | * structure contains a list of hardware addresses that should be copied | ||
| 26 | * to/from the scatterlist passed into device_prep_slave_sg(). The structure | ||
| 27 | * also has some fields to enable hardware-specific features. | ||
| 28 | */ | ||
| 29 | |||
| 30 | /** | ||
| 31 | * struct fsl_dma_hw_addr | ||
| 32 | * @entry: linked list entry | ||
| 33 | * @address: the hardware address | ||
| 34 | * @length: length to transfer | ||
| 35 | * | ||
| 36 | * Holds a single physical hardware address / length pair for use | ||
| 37 | * with the DMAEngine DMA_SLAVE API. | ||
| 38 | */ | ||
| 39 | struct fsl_dma_hw_addr { | ||
| 40 | struct list_head entry; | ||
| 41 | |||
| 42 | dma_addr_t address; | ||
| 43 | size_t length; | ||
| 44 | }; | ||
| 45 | |||
| 46 | /** | ||
| 47 | * struct fsl_dma_slave | ||
| 48 | * @addresses: a linked list of struct fsl_dma_hw_addr structures | ||
| 49 | * @request_count: value for DMA request count | ||
| 50 | * @src_loop_size: setup and enable constant source-address DMA transfers | ||
| 51 | * @dst_loop_size: setup and enable constant destination address DMA transfers | ||
| 52 | * @external_start: enable externally started DMA transfers | ||
| 53 | * @external_pause: enable externally paused DMA transfers | ||
| 54 | * | ||
| 55 | * Holds a list of address / length pairs for use with the DMAEngine | ||
| 56 | * DMA_SLAVE API implementation for the Freescale DMA controller. | ||
| 57 | */ | ||
| 58 | struct fsl_dma_slave { | ||
| 59 | |||
| 60 | /* List of hardware address/length pairs */ | ||
| 61 | struct list_head addresses; | ||
| 62 | |||
| 63 | /* Support for extra controller features */ | ||
| 64 | unsigned int request_count; | ||
| 65 | unsigned int src_loop_size; | ||
| 66 | unsigned int dst_loop_size; | ||
| 67 | bool external_start; | ||
| 68 | bool external_pause; | ||
| 69 | }; | ||
| 70 | |||
| 71 | /** | ||
| 72 | * fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave | ||
| 73 | * @slave: the &struct fsl_dma_slave to add to | ||
| 74 | * @address: the hardware address to add | ||
| 75 | * @length: the length of bytes to transfer from @address | ||
| 76 | * | ||
| 77 | * Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on | ||
| 78 | * success, -ERRNO otherwise. | ||
| 79 | */ | ||
| 80 | static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave, | ||
| 81 | dma_addr_t address, size_t length) | ||
| 82 | { | ||
| 83 | struct fsl_dma_hw_addr *addr; | ||
| 84 | |||
| 85 | addr = kzalloc(sizeof(*addr), GFP_ATOMIC); | ||
| 86 | if (!addr) | ||
| 87 | return -ENOMEM; | ||
| 88 | |||
| 89 | INIT_LIST_HEAD(&addr->entry); | ||
| 90 | addr->address = address; | ||
| 91 | addr->length = length; | ||
| 92 | |||
| 93 | list_add_tail(&addr->entry, &slave->addresses); | ||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | /** | ||
| 98 | * fsl_dma_slave_free - free a struct fsl_dma_slave | ||
| 99 | * @slave: the struct fsl_dma_slave to free | ||
| 100 | * | ||
| 101 | * Free a struct fsl_dma_slave and all associated address/length pairs | ||
| 102 | */ | ||
| 103 | static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave) | ||
| 104 | { | ||
| 105 | struct fsl_dma_hw_addr *addr, *tmp; | ||
| 106 | |||
| 107 | if (slave) { | ||
| 108 | list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) { | ||
| 109 | list_del(&addr->entry); | ||
| 110 | kfree(addr); | ||
| 111 | } | ||
| 112 | |||
| 113 | kfree(slave); | ||
| 114 | } | ||
| 115 | } | ||
| 116 | |||
| 117 | /** | ||
| 118 | * fsl_dma_slave_alloc - allocate a struct fsl_dma_slave | ||
| 119 | * @gfp: the flags to pass to kmalloc when allocating this structure | ||
| 120 | * | ||
| 121 | * Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new | ||
| 122 | * struct fsl_dma_slave on success, or NULL on failure. | ||
| 123 | */ | ||
| 124 | static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp) | ||
| 125 | { | ||
| 126 | struct fsl_dma_slave *slave; | ||
| 127 | |||
| 128 | slave = kzalloc(sizeof(*slave), gfp); | ||
| 129 | if (!slave) | ||
| 130 | return NULL; | ||
| 131 | |||
| 132 | INIT_LIST_HEAD(&slave->addresses); | ||
| 133 | return slave; | ||
| 134 | } | ||
| 135 | |||
| 136 | #endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */ | ||
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index b7e034b0a6dd..867ab8ed69b3 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h | |||
| @@ -80,7 +80,7 @@ static inline void local_irq_disable(void) | |||
| 80 | __asm__ __volatile__("wrteei 0": : :"memory"); | 80 | __asm__ __volatile__("wrteei 0": : :"memory"); |
| 81 | #else | 81 | #else |
| 82 | unsigned long msr; | 82 | unsigned long msr; |
| 83 | __asm__ __volatile__("": : :"memory"); | 83 | |
| 84 | msr = mfmsr(); | 84 | msr = mfmsr(); |
| 85 | SET_MSR_EE(msr & ~MSR_EE); | 85 | SET_MSR_EE(msr & ~MSR_EE); |
| 86 | #endif | 86 | #endif |
| @@ -92,7 +92,7 @@ static inline void local_irq_enable(void) | |||
| 92 | __asm__ __volatile__("wrteei 1": : :"memory"); | 92 | __asm__ __volatile__("wrteei 1": : :"memory"); |
| 93 | #else | 93 | #else |
| 94 | unsigned long msr; | 94 | unsigned long msr; |
| 95 | __asm__ __volatile__("": : :"memory"); | 95 | |
| 96 | msr = mfmsr(); | 96 | msr = mfmsr(); |
| 97 | SET_MSR_EE(msr | MSR_EE); | 97 | SET_MSR_EE(msr | MSR_EE); |
| 98 | #endif | 98 | #endif |
| @@ -108,7 +108,6 @@ static inline void local_irq_save_ptr(unsigned long *flags) | |||
| 108 | #else | 108 | #else |
| 109 | SET_MSR_EE(msr & ~MSR_EE); | 109 | SET_MSR_EE(msr & ~MSR_EE); |
| 110 | #endif | 110 | #endif |
| 111 | __asm__ __volatile__("": : :"memory"); | ||
| 112 | } | 111 | } |
| 113 | 112 | ||
| 114 | #define local_save_flags(flags) ((flags) = mfmsr()) | 113 | #define local_save_flags(flags) ((flags) = mfmsr()) |
| @@ -131,5 +130,43 @@ static inline int irqs_disabled_flags(unsigned long flags) | |||
| 131 | */ | 130 | */ |
| 132 | struct irq_chip; | 131 | struct irq_chip; |
| 133 | 132 | ||
| 133 | #ifdef CONFIG_PERF_COUNTERS | ||
| 134 | |||
| 135 | #ifdef CONFIG_PPC64 | ||
| 136 | static inline unsigned long test_perf_counter_pending(void) | ||
| 137 | { | ||
| 138 | unsigned long x; | ||
| 139 | |||
| 140 | asm volatile("lbz %0,%1(13)" | ||
| 141 | : "=r" (x) | ||
| 142 | : "i" (offsetof(struct paca_struct, perf_counter_pending))); | ||
| 143 | return x; | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline void set_perf_counter_pending(void) | ||
| 147 | { | ||
| 148 | asm volatile("stb %0,%1(13)" : : | ||
| 149 | "r" (1), | ||
| 150 | "i" (offsetof(struct paca_struct, perf_counter_pending))); | ||
| 151 | } | ||
| 152 | |||
| 153 | static inline void clear_perf_counter_pending(void) | ||
| 154 | { | ||
| 155 | asm volatile("stb %0,%1(13)" : : | ||
| 156 | "r" (0), | ||
| 157 | "i" (offsetof(struct paca_struct, perf_counter_pending))); | ||
| 158 | } | ||
| 159 | #endif /* CONFIG_PPC64 */ | ||
| 160 | |||
| 161 | #else /* CONFIG_PERF_COUNTERS */ | ||
| 162 | |||
| 163 | static inline unsigned long test_perf_counter_pending(void) | ||
| 164 | { | ||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | |||
| 168 | static inline void clear_perf_counter_pending(void) {} | ||
| 169 | #endif /* CONFIG_PERF_COUNTERS */ | ||
| 170 | |||
| 134 | #endif /* __KERNEL__ */ | 171 | #endif /* __KERNEL__ */ |
| 135 | #endif /* _ASM_POWERPC_HW_IRQ_H */ | 172 | #endif /* _ASM_POWERPC_HW_IRQ_H */ |
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index 7464c0daddd1..7ead7c16fb7c 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h | |||
| @@ -35,6 +35,16 @@ | |||
| 35 | #define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1)) | 35 | #define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1)) |
| 36 | #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE) | 36 | #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE) |
| 37 | 37 | ||
| 38 | /* Cell page table entries */ | ||
| 39 | #define CBE_IOPTE_PP_W 0x8000000000000000ul /* protection: write */ | ||
| 40 | #define CBE_IOPTE_PP_R 0x4000000000000000ul /* protection: read */ | ||
| 41 | #define CBE_IOPTE_M 0x2000000000000000ul /* coherency required */ | ||
| 42 | #define CBE_IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ | ||
| 43 | #define CBE_IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ | ||
| 44 | #define CBE_IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ | ||
| 45 | #define CBE_IOPTE_H 0x0000000000000800ul /* cache hint */ | ||
| 46 | #define CBE_IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ | ||
| 47 | |||
| 38 | /* Boot time flags */ | 48 | /* Boot time flags */ |
| 39 | extern int iommu_is_off; | 49 | extern int iommu_is_off; |
| 40 | extern int iommu_force_on; | 50 | extern int iommu_force_on; |
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h index d2a65e8ca6ae..f78f65c38f05 100644 --- a/arch/powerpc/include/asm/lppaca.h +++ b/arch/powerpc/include/asm/lppaca.h | |||
| @@ -20,6 +20,11 @@ | |||
| 20 | #define _ASM_POWERPC_LPPACA_H | 20 | #define _ASM_POWERPC_LPPACA_H |
| 21 | #ifdef __KERNEL__ | 21 | #ifdef __KERNEL__ |
| 22 | 22 | ||
| 23 | /* These definitions relate to hypervisors that only exist when using | ||
| 24 | * a server type processor | ||
| 25 | */ | ||
| 26 | #ifdef CONFIG_PPC_BOOK3S | ||
| 27 | |||
| 23 | //============================================================================= | 28 | //============================================================================= |
| 24 | // | 29 | // |
| 25 | // This control block contains the data that is shared between the | 30 | // This control block contains the data that is shared between the |
| @@ -158,5 +163,6 @@ struct slb_shadow { | |||
| 158 | 163 | ||
| 159 | extern struct slb_shadow slb_shadow[]; | 164 | extern struct slb_shadow slb_shadow[]; |
| 160 | 165 | ||
| 166 | #endif /* CONFIG_PPC_BOOK3S */ | ||
| 161 | #endif /* __KERNEL__ */ | 167 | #endif /* __KERNEL__ */ |
| 162 | #endif /* _ASM_POWERPC_LPPACA_H */ | 168 | #endif /* _ASM_POWERPC_LPPACA_H */ |
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index 0efdb1dfdc5f..11d1fc3a8962 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h | |||
| @@ -110,6 +110,10 @@ struct machdep_calls { | |||
| 110 | void (*show_percpuinfo)(struct seq_file *m, int i); | 110 | void (*show_percpuinfo)(struct seq_file *m, int i); |
| 111 | 111 | ||
| 112 | void (*init_IRQ)(void); | 112 | void (*init_IRQ)(void); |
| 113 | |||
| 114 | /* Return an irq, or NO_IRQ to indicate there are none pending. | ||
| 115 | * If for some reason there is no irq, but the interrupt | ||
| 116 | * shouldn't be counted as spurious, return NO_IRQ_IGNORE. */ | ||
| 113 | unsigned int (*get_irq)(void); | 117 | unsigned int (*get_irq)(void); |
| 114 | #ifdef CONFIG_KEXEC | 118 | #ifdef CONFIG_KEXEC |
| 115 | void (*kexec_cpu_down)(int crash_shutdown, int secondary); | 119 | void (*kexec_cpu_down)(int crash_shutdown, int secondary); |
diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h index e7b99bac9f48..7b1c49811a24 100644 --- a/arch/powerpc/include/asm/mman.h +++ b/arch/powerpc/include/asm/mman.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | #ifndef _ASM_POWERPC_MMAN_H | 1 | #ifndef _ASM_POWERPC_MMAN_H |
| 2 | #define _ASM_POWERPC_MMAN_H | 2 | #define _ASM_POWERPC_MMAN_H |
| 3 | 3 | ||
| 4 | #include <asm-generic/mman.h> | 4 | #include <asm-generic/mman-common.h> |
| 5 | 5 | ||
| 6 | /* | 6 | /* |
| 7 | * This program is free software; you can redistribute it and/or | 7 | * This program is free software; you can redistribute it and/or |
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index cbf154387091..fb57ded592f9 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h | |||
| @@ -52,6 +52,11 @@ | |||
| 52 | */ | 52 | */ |
| 53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) | 53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) |
| 54 | 54 | ||
| 55 | /* This indicates that the processor uses the ISA 2.06 server tlbie | ||
| 56 | * mnemonics | ||
| 57 | */ | ||
| 58 | #define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000) | ||
| 59 | |||
| 55 | #ifndef __ASSEMBLY__ | 60 | #ifndef __ASSEMBLY__ |
| 56 | #include <asm/cputable.h> | 61 | #include <asm/cputable.h> |
| 57 | 62 | ||
| @@ -69,10 +74,10 @@ extern void early_init_mmu_secondary(void); | |||
| 69 | #endif /* !__ASSEMBLY__ */ | 74 | #endif /* !__ASSEMBLY__ */ |
| 70 | 75 | ||
| 71 | 76 | ||
| 72 | #ifdef CONFIG_PPC64 | 77 | #if defined(CONFIG_PPC_STD_MMU_64) |
| 73 | /* 64-bit classic hash table MMU */ | 78 | /* 64-bit classic hash table MMU */ |
| 74 | # include <asm/mmu-hash64.h> | 79 | # include <asm/mmu-hash64.h> |
| 75 | #elif defined(CONFIG_PPC_STD_MMU) | 80 | #elif defined(CONFIG_PPC_STD_MMU_32) |
| 76 | /* 32-bit classic hash table MMU */ | 81 | /* 32-bit classic hash table MMU */ |
| 77 | # include <asm/mmu-hash32.h> | 82 | # include <asm/mmu-hash32.h> |
| 78 | #elif defined(CONFIG_40x) | 83 | #elif defined(CONFIG_40x) |
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h index 52e049cd9e68..1b4f697abbdd 100644 --- a/arch/powerpc/include/asm/mpc52xx.h +++ b/arch/powerpc/include/asm/mpc52xx.h | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #ifndef __ASSEMBLY__ | 16 | #ifndef __ASSEMBLY__ |
| 17 | #include <asm/types.h> | 17 | #include <asm/types.h> |
| 18 | #include <asm/prom.h> | 18 | #include <asm/prom.h> |
| 19 | #include <asm/mpc5xxx.h> | ||
| 19 | #endif /* __ASSEMBLY__ */ | 20 | #endif /* __ASSEMBLY__ */ |
| 20 | 21 | ||
| 21 | #include <linux/suspend.h> | 22 | #include <linux/suspend.h> |
| @@ -268,7 +269,6 @@ struct mpc52xx_intr { | |||
| 268 | #ifndef __ASSEMBLY__ | 269 | #ifndef __ASSEMBLY__ |
| 269 | 270 | ||
| 270 | /* mpc52xx_common.c */ | 271 | /* mpc52xx_common.c */ |
| 271 | extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node); | ||
| 272 | extern void mpc5200_setup_xlb_arbiter(void); | 272 | extern void mpc5200_setup_xlb_arbiter(void); |
| 273 | extern void mpc52xx_declare_of_platform_devices(void); | 273 | extern void mpc52xx_declare_of_platform_devices(void); |
| 274 | extern void mpc52xx_map_common_devices(void); | 274 | extern void mpc52xx_map_common_devices(void); |
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h index a218da6bec7c..fb8412057450 100644 --- a/arch/powerpc/include/asm/mpc52xx_psc.h +++ b/arch/powerpc/include/asm/mpc52xx_psc.h | |||
| @@ -28,6 +28,10 @@ | |||
| 28 | #define MPC52xx_PSC_MAXNUM 6 | 28 | #define MPC52xx_PSC_MAXNUM 6 |
| 29 | 29 | ||
| 30 | /* Programmable Serial Controller (PSC) status register bits */ | 30 | /* Programmable Serial Controller (PSC) status register bits */ |
| 31 | #define MPC52xx_PSC_SR_UNEX_RX 0x0001 | ||
| 32 | #define MPC52xx_PSC_SR_DATA_VAL 0x0002 | ||
| 33 | #define MPC52xx_PSC_SR_DATA_OVR 0x0004 | ||
| 34 | #define MPC52xx_PSC_SR_CMDSEND 0x0008 | ||
| 31 | #define MPC52xx_PSC_SR_CDE 0x0080 | 35 | #define MPC52xx_PSC_SR_CDE 0x0080 |
| 32 | #define MPC52xx_PSC_SR_RXRDY 0x0100 | 36 | #define MPC52xx_PSC_SR_RXRDY 0x0100 |
| 33 | #define MPC52xx_PSC_SR_RXFULL 0x0200 | 37 | #define MPC52xx_PSC_SR_RXFULL 0x0200 |
| @@ -61,6 +65,12 @@ | |||
| 61 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 | 65 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 |
| 62 | 66 | ||
| 63 | /* PSC interrupt status/mask bits */ | 67 | /* PSC interrupt status/mask bits */ |
| 68 | #define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001 | ||
| 69 | #define MPC52xx_PSC_IMR_DATA_VALID 0x0002 | ||
| 70 | #define MPC52xx_PSC_IMR_DATA_OVR 0x0004 | ||
| 71 | #define MPC52xx_PSC_IMR_CMD_SEND 0x0008 | ||
| 72 | #define MPC52xx_PSC_IMR_ERROR 0x0040 | ||
| 73 | #define MPC52xx_PSC_IMR_DEOF 0x0080 | ||
| 64 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 | 74 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 |
| 65 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 | 75 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 |
| 66 | #define MPC52xx_PSC_IMR_DB 0x0400 | 76 | #define MPC52xx_PSC_IMR_DB 0x0400 |
| @@ -117,6 +127,7 @@ | |||
| 117 | #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) | 127 | #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) |
| 118 | #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) | 128 | #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) |
| 119 | #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) | 129 | #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) |
| 130 | #define MPC52xx_PSC_SICR_AWR (1 << 30) | ||
| 120 | #define MPC52xx_PSC_SICR_GENCLK (1 << 23) | 131 | #define MPC52xx_PSC_SICR_GENCLK (1 << 23) |
| 121 | #define MPC52xx_PSC_SICR_I2S (1 << 22) | 132 | #define MPC52xx_PSC_SICR_I2S (1 << 22) |
| 122 | #define MPC52xx_PSC_SICR_CLKPOL (1 << 21) | 133 | #define MPC52xx_PSC_SICR_CLKPOL (1 << 21) |
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc5xxx.h index c48a1658eeac..5ce9c5fa434a 100644 --- a/arch/powerpc/include/asm/mpc512x.h +++ b/arch/powerpc/include/asm/mpc5xxx.h | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007 | 4 | * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007 |
| 5 | * | 5 | * |
| 6 | * Description: | 6 | * Description: |
| 7 | * MPC5121 Prototypes and definitions | 7 | * MPC5xxx Prototypes and definitions |
| 8 | * | 8 | * |
| 9 | * This is free software; you can redistribute it and/or modify it | 9 | * This is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by | 10 | * under the terms of the GNU General Public License as published by |
| @@ -13,10 +13,10 @@ | |||
| 13 | * | 13 | * |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef __ASM_POWERPC_MPC512x_H__ | 16 | #ifndef __ASM_POWERPC_MPC5xxx_H__ |
| 17 | #define __ASM_POWERPC_MPC512x_H__ | 17 | #define __ASM_POWERPC_MPC5xxx_H__ |
| 18 | 18 | ||
| 19 | extern unsigned long mpc512x_find_ips_freq(struct device_node *node); | 19 | extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node); |
| 20 | 20 | ||
| 21 | #endif /* __ASM_POWERPC_MPC512x_H__ */ | 21 | #endif /* __ASM_POWERPC_MPC5xxx_H__ */ |
| 22 | 22 | ||
diff --git a/arch/powerpc/include/asm/mpc86xx.h b/arch/powerpc/include/asm/mpc86xx.h deleted file mode 100644 index 15f650f987e7..000000000000 --- a/arch/powerpc/include/asm/mpc86xx.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MPC86xx definitions | ||
| 3 | * | ||
| 4 | * Author: Jeff Brown | ||
| 5 | * | ||
| 6 | * Copyright 2004 Freescale Semiconductor, Inc | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifdef __KERNEL__ | ||
| 15 | #ifndef __ASM_POWERPC_MPC86xx_H__ | ||
| 16 | #define __ASM_POWERPC_MPC86xx_H__ | ||
| 17 | |||
| 18 | #include <asm/mmu.h> | ||
| 19 | |||
| 20 | #ifdef CONFIG_PPC_86xx | ||
| 21 | |||
| 22 | #define CPU0_BOOT_RELEASE 0x01000000 | ||
| 23 | #define CPU1_BOOT_RELEASE 0x02000000 | ||
| 24 | #define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE) | ||
| 25 | #define MCM_PORT_CONFIG_OFFSET 0x1010 | ||
| 26 | |||
| 27 | /* Offset from CCSRBAR */ | ||
| 28 | #define MPC86xx_MCM_OFFSET (0x00000) | ||
| 29 | #define MPC86xx_MCM_SIZE (0x02000) | ||
| 30 | |||
| 31 | #endif /* CONFIG_PPC_86xx */ | ||
| 32 | #endif /* __ASM_POWERPC_MPC86xx_H__ */ | ||
| 33 | #endif /* __KERNEL__ */ | ||
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index 082b3aedf145..c8a3cbfe02ff 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h | |||
| @@ -43,6 +43,7 @@ struct task_struct; | |||
| 43 | * processor. | 43 | * processor. |
| 44 | */ | 44 | */ |
| 45 | struct paca_struct { | 45 | struct paca_struct { |
| 46 | #ifdef CONFIG_PPC_BOOK3S | ||
| 46 | /* | 47 | /* |
| 47 | * Because hw_cpu_id, unlike other paca fields, is accessed | 48 | * Because hw_cpu_id, unlike other paca fields, is accessed |
| 48 | * routinely from other CPUs (from the IRQ code), we stick to | 49 | * routinely from other CPUs (from the IRQ code), we stick to |
| @@ -51,7 +52,7 @@ struct paca_struct { | |||
| 51 | */ | 52 | */ |
| 52 | 53 | ||
| 53 | struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ | 54 | struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ |
| 54 | 55 | #endif /* CONFIG_PPC_BOOK3S */ | |
| 55 | /* | 56 | /* |
| 56 | * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c | 57 | * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c |
| 57 | * load lock_token and paca_index with a single lwz | 58 | * load lock_token and paca_index with a single lwz |
| @@ -64,13 +65,16 @@ struct paca_struct { | |||
| 64 | u64 kernel_toc; /* Kernel TOC address */ | 65 | u64 kernel_toc; /* Kernel TOC address */ |
| 65 | u64 kernelbase; /* Base address of kernel */ | 66 | u64 kernelbase; /* Base address of kernel */ |
| 66 | u64 kernel_msr; /* MSR while running in kernel */ | 67 | u64 kernel_msr; /* MSR while running in kernel */ |
| 68 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 67 | u64 stab_real; /* Absolute address of segment table */ | 69 | u64 stab_real; /* Absolute address of segment table */ |
| 68 | u64 stab_addr; /* Virtual address of segment table */ | 70 | u64 stab_addr; /* Virtual address of segment table */ |
| 71 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 69 | void *emergency_sp; /* pointer to emergency stack */ | 72 | void *emergency_sp; /* pointer to emergency stack */ |
| 70 | u64 data_offset; /* per cpu data offset */ | 73 | u64 data_offset; /* per cpu data offset */ |
| 71 | s16 hw_cpu_id; /* Physical processor number */ | 74 | s16 hw_cpu_id; /* Physical processor number */ |
| 72 | u8 cpu_start; /* At startup, processor spins until */ | 75 | u8 cpu_start; /* At startup, processor spins until */ |
| 73 | /* this becomes non-zero. */ | 76 | /* this becomes non-zero. */ |
| 77 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 74 | struct slb_shadow *slb_shadow_ptr; | 78 | struct slb_shadow *slb_shadow_ptr; |
| 75 | 79 | ||
| 76 | /* | 80 | /* |
| @@ -81,11 +85,13 @@ struct paca_struct { | |||
| 81 | u64 exmc[10]; /* used for machine checks */ | 85 | u64 exmc[10]; /* used for machine checks */ |
| 82 | u64 exslb[10]; /* used for SLB/segment table misses | 86 | u64 exslb[10]; /* used for SLB/segment table misses |
| 83 | * on the linear mapping */ | 87 | * on the linear mapping */ |
| 84 | 88 | /* SLB related definitions */ | |
| 85 | mm_context_t context; | ||
| 86 | u16 vmalloc_sllp; | 89 | u16 vmalloc_sllp; |
| 87 | u16 slb_cache_ptr; | 90 | u16 slb_cache_ptr; |
| 88 | u16 slb_cache[SLB_CACHE_ENTRIES]; | 91 | u16 slb_cache[SLB_CACHE_ENTRIES]; |
| 92 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 93 | |||
| 94 | mm_context_t context; | ||
| 89 | 95 | ||
| 90 | /* | 96 | /* |
| 91 | * then miscellaneous read-write fields | 97 | * then miscellaneous read-write fields |
| @@ -99,6 +105,7 @@ struct paca_struct { | |||
| 99 | u8 soft_enabled; /* irq soft-enable flag */ | 105 | u8 soft_enabled; /* irq soft-enable flag */ |
| 100 | u8 hard_enabled; /* set if irqs are enabled in MSR */ | 106 | u8 hard_enabled; /* set if irqs are enabled in MSR */ |
| 101 | u8 io_sync; /* writel() needs spin_unlock sync */ | 107 | u8 io_sync; /* writel() needs spin_unlock sync */ |
| 108 | u8 perf_counter_pending; /* PM interrupt while soft-disabled */ | ||
| 102 | 109 | ||
| 103 | /* Stuff for accurate time accounting */ | 110 | /* Stuff for accurate time accounting */ |
| 104 | u64 user_time; /* accumulated usermode TB ticks */ | 111 | u64 user_time; /* accumulated usermode TB ticks */ |
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index 32cbf16f10ea..4940662ee87e 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h | |||
| @@ -231,6 +231,11 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr, | |||
| 231 | struct page *p); | 231 | struct page *p); |
| 232 | extern int page_is_ram(unsigned long pfn); | 232 | extern int page_is_ram(unsigned long pfn); |
| 233 | 233 | ||
| 234 | #ifdef CONFIG_PPC_SMLPAR | ||
| 235 | void arch_free_page(struct page *page, int order); | ||
| 236 | #define HAVE_ARCH_FREE_PAGE | ||
| 237 | #endif | ||
| 238 | |||
| 234 | struct vm_area_struct; | 239 | struct vm_area_struct; |
| 235 | 240 | ||
| 236 | typedef struct page *pgtable_t; | 241 | typedef struct page *pgtable_t; |
diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h index a0e3f6e6b4ee..bd0849dbcaaa 100644 --- a/arch/powerpc/include/asm/page_32.h +++ b/arch/powerpc/include/asm/page_32.h | |||
| @@ -41,7 +41,7 @@ extern void clear_pages(void *page, int order); | |||
| 41 | static inline void clear_page(void *page) { clear_pages(page, 0); } | 41 | static inline void clear_page(void *page) { clear_pages(page, 0); } |
| 42 | extern void copy_page(void *to, void *from); | 42 | extern void copy_page(void *to, void *from); |
| 43 | 43 | ||
| 44 | #include <asm-generic/page.h> | 44 | #include <asm-generic/getorder.h> |
| 45 | 45 | ||
| 46 | #define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) | 46 | #define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) |
| 47 | #define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) | 47 | #define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) |
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h index 043bfdfe4f73..5817a3b747e5 100644 --- a/arch/powerpc/include/asm/page_64.h +++ b/arch/powerpc/include/asm/page_64.h | |||
| @@ -180,6 +180,6 @@ do { \ | |||
| 180 | (test_thread_flag(TIF_32BIT) ? \ | 180 | (test_thread_flag(TIF_32BIT) ? \ |
| 181 | VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) | 181 | VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) |
| 182 | 182 | ||
| 183 | #include <asm-generic/page.h> | 183 | #include <asm-generic/getorder.h> |
| 184 | 184 | ||
| 185 | #endif /* _ASM_POWERPC_PAGE_64_H */ | 185 | #endif /* _ASM_POWERPC_PAGE_64_H */ |
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 84007afabdb5..4c61fa0b8d75 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h | |||
| @@ -86,17 +86,12 @@ struct pci_controller { | |||
| 86 | void *io_base_alloc; | 86 | void *io_base_alloc; |
| 87 | #endif | 87 | #endif |
| 88 | resource_size_t io_base_phys; | 88 | resource_size_t io_base_phys; |
| 89 | #ifndef CONFIG_PPC64 | ||
| 90 | resource_size_t pci_io_size; | 89 | resource_size_t pci_io_size; |
| 91 | #endif | ||
| 92 | 90 | ||
| 93 | /* Some machines (PReP) have a non 1:1 mapping of | 91 | /* Some machines (PReP) have a non 1:1 mapping of |
| 94 | * the PCI memory space in the CPU bus space | 92 | * the PCI memory space in the CPU bus space |
| 95 | */ | 93 | */ |
| 96 | resource_size_t pci_mem_offset; | 94 | resource_size_t pci_mem_offset; |
| 97 | #ifdef CONFIG_PPC64 | ||
| 98 | unsigned long pci_io_size; | ||
| 99 | #endif | ||
| 100 | 95 | ||
| 101 | /* Some machines have a special region to forward the ISA | 96 | /* Some machines have a special region to forward the ISA |
| 102 | * "memory" cycles such as VGA memory regions. Left to 0 | 97 | * "memory" cycles such as VGA memory regions. Left to 0 |
| @@ -140,10 +135,12 @@ struct pci_controller { | |||
| 140 | struct resource io_resource; | 135 | struct resource io_resource; |
| 141 | struct resource mem_resources[3]; | 136 | struct resource mem_resources[3]; |
| 142 | int global_number; /* PCI domain number */ | 137 | int global_number; /* PCI domain number */ |
| 138 | |||
| 139 | resource_size_t dma_window_base_cur; | ||
| 140 | resource_size_t dma_window_size; | ||
| 141 | |||
| 143 | #ifdef CONFIG_PPC64 | 142 | #ifdef CONFIG_PPC64 |
| 144 | unsigned long buid; | 143 | unsigned long buid; |
| 145 | unsigned long dma_window_base_cur; | ||
| 146 | unsigned long dma_window_size; | ||
| 147 | 144 | ||
| 148 | void *private_data; | 145 | void *private_data; |
| 149 | #endif /* CONFIG_PPC64 */ | 146 | #endif /* CONFIG_PPC64 */ |
| @@ -185,7 +182,6 @@ extern int early_find_capability(struct pci_controller *hose, int bus, | |||
| 185 | extern void setup_indirect_pci(struct pci_controller* hose, | 182 | extern void setup_indirect_pci(struct pci_controller* hose, |
| 186 | resource_size_t cfg_addr, | 183 | resource_size_t cfg_addr, |
| 187 | resource_size_t cfg_data, u32 flags); | 184 | resource_size_t cfg_data, u32 flags); |
| 188 | extern void setup_grackle(struct pci_controller *hose); | ||
| 189 | #else /* CONFIG_PPC64 */ | 185 | #else /* CONFIG_PPC64 */ |
| 190 | 186 | ||
| 191 | /* | 187 | /* |
| @@ -221,6 +217,7 @@ struct pci_dn { | |||
| 221 | #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) | 217 | #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) |
| 222 | 218 | ||
| 223 | extern struct device_node *fetch_dev_dn(struct pci_dev *dev); | 219 | extern struct device_node *fetch_dev_dn(struct pci_dev *dev); |
| 220 | extern void * update_dn_pci_info(struct device_node *dn, void *data); | ||
| 224 | 221 | ||
| 225 | /* Get a device_node from a pci_dev. This code must be fast except | 222 | /* Get a device_node from a pci_dev. This code must be fast except |
| 226 | * in the case where the sysdata is incorrect and needs to be fixed | 223 | * in the case where the sysdata is incorrect and needs to be fixed |
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index ba17d5d90a49..d9483c504d2d 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h | |||
| @@ -195,19 +195,6 @@ extern void pcibios_bus_to_resource(struct pci_dev *dev, | |||
| 195 | struct resource *res, | 195 | struct resource *res, |
| 196 | struct pci_bus_region *region); | 196 | struct pci_bus_region *region); |
| 197 | 197 | ||
| 198 | static inline struct resource *pcibios_select_root(struct pci_dev *pdev, | ||
| 199 | struct resource *res) | ||
| 200 | { | ||
| 201 | struct resource *root = NULL; | ||
| 202 | |||
| 203 | if (res->flags & IORESOURCE_IO) | ||
| 204 | root = &ioport_resource; | ||
| 205 | if (res->flags & IORESOURCE_MEM) | ||
| 206 | root = &iomem_resource; | ||
| 207 | |||
| 208 | return root; | ||
| 209 | } | ||
| 210 | |||
| 211 | extern void pcibios_claim_one_bus(struct pci_bus *b); | 198 | extern void pcibios_claim_one_bus(struct pci_bus *b); |
| 212 | 199 | ||
| 213 | extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); | 200 | extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); |
diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h new file mode 100644 index 000000000000..8ccd4e155768 --- /dev/null +++ b/arch/powerpc/include/asm/perf_counter.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support - PowerPC-specific definitions. | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/types.h> | ||
| 12 | |||
| 13 | #include <asm/hw_irq.h> | ||
| 14 | |||
| 15 | #define MAX_HWCOUNTERS 8 | ||
| 16 | #define MAX_EVENT_ALTERNATIVES 8 | ||
| 17 | #define MAX_LIMITED_HWCOUNTERS 2 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * This struct provides the constants and functions needed to | ||
| 21 | * describe the PMU on a particular POWER-family CPU. | ||
| 22 | */ | ||
| 23 | struct power_pmu { | ||
| 24 | const char *name; | ||
| 25 | int n_counter; | ||
| 26 | int max_alternatives; | ||
| 27 | unsigned long add_fields; | ||
| 28 | unsigned long test_adder; | ||
| 29 | int (*compute_mmcr)(u64 events[], int n_ev, | ||
| 30 | unsigned int hwc[], unsigned long mmcr[]); | ||
| 31 | int (*get_constraint)(u64 event, unsigned long *mskp, | ||
| 32 | unsigned long *valp); | ||
| 33 | int (*get_alternatives)(u64 event, unsigned int flags, | ||
| 34 | u64 alt[]); | ||
| 35 | void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]); | ||
| 36 | int (*limited_pmc_event)(u64 event); | ||
| 37 | u32 flags; | ||
| 38 | int n_generic; | ||
| 39 | int *generic_events; | ||
| 40 | int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] | ||
| 41 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 42 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | ||
| 43 | }; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Values for power_pmu.flags | ||
| 47 | */ | ||
| 48 | #define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */ | ||
| 49 | #define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Values for flags to get_alternatives() | ||
| 53 | */ | ||
| 54 | #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */ | ||
| 55 | #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */ | ||
| 56 | #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */ | ||
| 57 | |||
| 58 | extern int register_power_pmu(struct power_pmu *); | ||
| 59 | |||
| 60 | struct pt_regs; | ||
| 61 | extern unsigned long perf_misc_flags(struct pt_regs *regs); | ||
| 62 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Only override the default definitions in include/linux/perf_counter.h | ||
| 66 | * if we have hardware PMU support. | ||
| 67 | */ | ||
| 68 | #ifdef CONFIG_PPC_PERF_CTRS | ||
| 69 | #define perf_misc_flags(regs) perf_misc_flags(regs) | ||
| 70 | #endif | ||
| 71 | |||
| 72 | /* | ||
| 73 | * The power_pmu.get_constraint function returns a 32/64-bit value and | ||
| 74 | * a 32/64-bit mask that express the constraints between this event and | ||
| 75 | * other events. | ||
| 76 | * | ||
| 77 | * The value and mask are divided up into (non-overlapping) bitfields | ||
| 78 | * of three different types: | ||
| 79 | * | ||
| 80 | * Select field: this expresses the constraint that some set of bits | ||
| 81 | * in MMCR* needs to be set to a specific value for this event. For a | ||
| 82 | * select field, the mask contains 1s in every bit of the field, and | ||
| 83 | * the value contains a unique value for each possible setting of the | ||
| 84 | * MMCR* bits. The constraint checking code will ensure that two events | ||
| 85 | * that set the same field in their masks have the same value in their | ||
| 86 | * value dwords. | ||
| 87 | * | ||
| 88 | * Add field: this expresses the constraint that there can be at most | ||
| 89 | * N events in a particular class. A field of k bits can be used for | ||
| 90 | * N <= 2^(k-1) - 1. The mask has the most significant bit of the field | ||
| 91 | * set (and the other bits 0), and the value has only the least significant | ||
| 92 | * bit of the field set. In addition, the 'add_fields' and 'test_adder' | ||
| 93 | * in the struct power_pmu for this processor come into play. The | ||
| 94 | * add_fields value contains 1 in the LSB of the field, and the | ||
| 95 | * test_adder contains 2^(k-1) - 1 - N in the field. | ||
| 96 | * | ||
| 97 | * NAND field: this expresses the constraint that you may not have events | ||
| 98 | * in all of a set of classes. (For example, on PPC970, you can't select | ||
| 99 | * events from the FPU, ISU and IDU simultaneously, although any two are | ||
| 100 | * possible.) For N classes, the field is N+1 bits wide, and each class | ||
| 101 | * is assigned one bit from the least-significant N bits. The mask has | ||
| 102 | * only the most-significant bit set, and the value has only the bit | ||
| 103 | * for the event's class set. The test_adder has the least significant | ||
| 104 | * bit set in the field. | ||
| 105 | * | ||
| 106 | * If an event is not subject to the constraint expressed by a particular | ||
| 107 | * field, then it will have 0 in both the mask and value for that field. | ||
| 108 | */ | ||
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index c40db05f21e0..8cd083c61503 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h | |||
| @@ -31,9 +31,11 @@ | |||
| 31 | #error TASK_SIZE_USER64 exceeds pagetable range | 31 | #error TASK_SIZE_USER64 exceeds pagetable range |
| 32 | #endif | 32 | #endif |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 34 | #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT)) | 35 | #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT)) |
| 35 | #error TASK_SIZE_USER64 exceeds user VSID range | 36 | #error TASK_SIZE_USER64 exceeds user VSID range |
| 36 | #endif | 37 | #endif |
| 38 | #endif | ||
| 37 | 39 | ||
| 38 | /* | 40 | /* |
| 39 | * Define the address range of the vmalloc VM area. | 41 | * Define the address range of the vmalloc VM area. |
| @@ -199,8 +201,11 @@ static inline unsigned long pte_update(struct mm_struct *mm, | |||
| 199 | if (!huge) | 201 | if (!huge) |
| 200 | assert_pte_locked(mm, addr); | 202 | assert_pte_locked(mm, addr); |
| 201 | 203 | ||
| 204 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 202 | if (old & _PAGE_HASHPTE) | 205 | if (old & _PAGE_HASHPTE) |
| 203 | hpte_need_flush(mm, addr, ptep, old, huge); | 206 | hpte_need_flush(mm, addr, ptep, old, huge); |
| 207 | #endif | ||
| 208 | |||
| 204 | return old; | 209 | return old; |
| 205 | } | 210 | } |
| 206 | 211 | ||
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 640ccbbc0977..b74f16d45cb4 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #define PPC_INST_LSWI 0x7c0004aa | 25 | #define PPC_INST_LSWI 0x7c0004aa |
| 26 | #define PPC_INST_LSWX 0x7c00042a | 26 | #define PPC_INST_LSWX 0x7c00042a |
| 27 | #define PPC_INST_LWSYNC 0x7c2004ac | 27 | #define PPC_INST_LWSYNC 0x7c2004ac |
| 28 | #define PPC_INST_LXVD2X 0x7c000698 | ||
| 28 | #define PPC_INST_MCRXR 0x7c000400 | 29 | #define PPC_INST_MCRXR 0x7c000400 |
| 29 | #define PPC_INST_MCRXR_MASK 0xfc0007fe | 30 | #define PPC_INST_MCRXR_MASK 0xfc0007fe |
| 30 | #define PPC_INST_MFSPR_PVR 0x7c1f42a6 | 31 | #define PPC_INST_MFSPR_PVR 0x7c1f42a6 |
| @@ -43,14 +44,18 @@ | |||
| 43 | 44 | ||
| 44 | #define PPC_INST_STSWI 0x7c0005aa | 45 | #define PPC_INST_STSWI 0x7c0005aa |
| 45 | #define PPC_INST_STSWX 0x7c00052a | 46 | #define PPC_INST_STSWX 0x7c00052a |
| 47 | #define PPC_INST_STXVD2X 0x7c000798 | ||
| 48 | #define PPC_INST_TLBIE 0x7c000264 | ||
| 46 | #define PPC_INST_TLBILX 0x7c000024 | 49 | #define PPC_INST_TLBILX 0x7c000024 |
| 47 | #define PPC_INST_WAIT 0x7c00007c | 50 | #define PPC_INST_WAIT 0x7c00007c |
| 48 | 51 | ||
| 49 | /* macros to insert fields into opcodes */ | 52 | /* macros to insert fields into opcodes */ |
| 50 | #define __PPC_RA(a) ((a & 0x1f) << 16) | 53 | #define __PPC_RA(a) (((a) & 0x1f) << 16) |
| 51 | #define __PPC_RB(b) ((b & 0x1f) << 11) | 54 | #define __PPC_RB(b) (((b) & 0x1f) << 11) |
| 52 | #define __PPC_T_TLB(t) ((t & 0x3) << 21) | 55 | #define __PPC_RS(s) (((s) & 0x1f) << 21) |
| 53 | #define __PPC_WC(w) ((w & 0x3) << 21) | 56 | #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) |
| 57 | #define __PPC_T_TLB(t) (((t) & 0x3) << 21) | ||
| 58 | #define __PPC_WC(w) (((w) & 0x3) << 21) | ||
| 54 | 59 | ||
| 55 | /* Deal with instructions that older assemblers aren't aware of */ | 60 | /* Deal with instructions that older assemblers aren't aware of */ |
| 56 | #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ | 61 | #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ |
| @@ -69,5 +74,17 @@ | |||
| 69 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) | 74 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) |
| 70 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ | 75 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ |
| 71 | __PPC_WC(w)) | 76 | __PPC_WC(w)) |
| 77 | #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ | ||
| 78 | __PPC_RB(a) | __PPC_RS(lp)) | ||
| 79 | |||
| 80 | /* | ||
| 81 | * Define what the VSX XX1 form instructions will look like, then add | ||
| 82 | * the 128 bit load store instructions based on that. | ||
| 83 | */ | ||
| 84 | #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) | ||
| 85 | #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ | ||
| 86 | VSX_XX1((s), (a), (b))) | ||
| 87 | #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ | ||
| 88 | VSX_XX1((s), (a), (b))) | ||
| 72 | 89 | ||
| 73 | #endif /* _ASM_POWERPC_PPC_OPCODE_H */ | 90 | #endif /* _ASM_POWERPC_PPC_OPCODE_H */ |
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 384d90c9c272..f9729529c20d 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h | |||
| @@ -76,16 +76,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ | |||
| 76 | REST_10GPRS(22, base) | 76 | REST_10GPRS(22, base) |
| 77 | #endif | 77 | #endif |
| 78 | 78 | ||
| 79 | /* | ||
| 80 | * Define what the VSX XX1 form instructions will look like, then add | ||
| 81 | * the 128 bit load store instructions based on that. | ||
| 82 | */ | ||
| 83 | #define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \ | ||
| 84 | ((rb) << 11) | (((xs) >> 5))) | ||
| 85 | |||
| 86 | #define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb))) | ||
| 87 | #define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb))) | ||
| 88 | |||
| 89 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) | 79 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) |
| 90 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) | 80 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) |
| 91 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) | 81 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) |
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h index cdb6fd814de8..7f065e178ec4 100644 --- a/arch/powerpc/include/asm/ps3.h +++ b/arch/powerpc/include/asm/ps3.h | |||
| @@ -53,6 +53,13 @@ enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void); | |||
| 53 | extern u64 ps3_os_area_get_rtc_diff(void); | 53 | extern u64 ps3_os_area_get_rtc_diff(void); |
| 54 | extern void ps3_os_area_set_rtc_diff(u64 rtc_diff); | 54 | extern void ps3_os_area_set_rtc_diff(u64 rtc_diff); |
| 55 | 55 | ||
| 56 | struct ps3_os_area_flash_ops { | ||
| 57 | ssize_t (*read)(void *buf, size_t count, loff_t pos); | ||
| 58 | ssize_t (*write)(const void *buf, size_t count, loff_t pos); | ||
| 59 | }; | ||
| 60 | |||
| 61 | extern void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops); | ||
| 62 | |||
| 56 | /* dma routines */ | 63 | /* dma routines */ |
| 57 | 64 | ||
| 58 | enum ps3_dma_page_size { | 65 | enum ps3_dma_page_size { |
| @@ -418,15 +425,15 @@ static inline struct ps3_system_bus_driver * | |||
| 418 | * @data: Data to set | 425 | * @data: Data to set |
| 419 | */ | 426 | */ |
| 420 | 427 | ||
| 421 | static inline void ps3_system_bus_set_driver_data( | 428 | static inline void ps3_system_bus_set_drvdata( |
| 422 | struct ps3_system_bus_device *dev, void *data) | 429 | struct ps3_system_bus_device *dev, void *data) |
| 423 | { | 430 | { |
| 424 | dev->core.driver_data = data; | 431 | dev_set_drvdata(&dev->core, data); |
| 425 | } | 432 | } |
| 426 | static inline void *ps3_system_bus_get_driver_data( | 433 | static inline void *ps3_system_bus_get_drvdata( |
| 427 | struct ps3_system_bus_device *dev) | 434 | struct ps3_system_bus_device *dev) |
| 428 | { | 435 | { |
| 429 | return dev->core.driver_data; | 436 | return dev_get_drvdata(&dev->core); |
| 430 | } | 437 | } |
| 431 | 438 | ||
| 432 | /* These two need global scope for get_dma_ops(). */ | 439 | /* These two need global scope for get_dma_ops(). */ |
| @@ -520,7 +527,4 @@ void ps3_sync_irq(int node); | |||
| 520 | u32 ps3_get_hw_thread_id(int cpu); | 527 | u32 ps3_get_hw_thread_id(int cpu); |
| 521 | u64 ps3_get_spe_id(void *arg); | 528 | u64 ps3_get_spe_id(void *arg); |
| 522 | 529 | ||
| 523 | /* mutex synchronizing GPU accesses and video mode changes */ | ||
| 524 | extern struct mutex ps3_gpu_mutex; | ||
| 525 | |||
| 526 | #endif | 530 | #endif |
diff --git a/arch/powerpc/include/asm/ps3gpu.h b/arch/powerpc/include/asm/ps3gpu.h new file mode 100644 index 000000000000..b2b89591907c --- /dev/null +++ b/arch/powerpc/include/asm/ps3gpu.h | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* | ||
| 2 | * PS3 GPU declarations. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Sony Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; version 2 of the License. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program. | ||
| 17 | * If not, see <http://www.gnu.org/licenses/>. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _ASM_POWERPC_PS3GPU_H | ||
| 21 | #define _ASM_POWERPC_PS3GPU_H | ||
| 22 | |||
| 23 | #include <linux/mutex.h> | ||
| 24 | |||
| 25 | #include <asm/lv1call.h> | ||
| 26 | |||
| 27 | |||
| 28 | #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101 | ||
| 29 | #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102 | ||
| 30 | |||
| 31 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600 | ||
| 32 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601 | ||
| 33 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602 | ||
| 34 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603 | ||
| 35 | |||
| 36 | #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION (1ULL << 32) | ||
| 37 | |||
| 38 | #define L1GPU_DISPLAY_SYNC_HSYNC 1 | ||
| 39 | #define L1GPU_DISPLAY_SYNC_VSYNC 2 | ||
| 40 | |||
| 41 | |||
| 42 | /* mutex synchronizing GPU accesses and video mode changes */ | ||
| 43 | extern struct mutex ps3_gpu_mutex; | ||
| 44 | |||
| 45 | |||
| 46 | static inline int lv1_gpu_display_sync(u64 context_handle, u64 head, | ||
| 47 | u64 ddr_offset) | ||
| 48 | { | ||
| 49 | return lv1_gpu_context_attribute(context_handle, | ||
| 50 | L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC, | ||
| 51 | head, ddr_offset, 0, 0); | ||
| 52 | } | ||
| 53 | |||
| 54 | static inline int lv1_gpu_display_flip(u64 context_handle, u64 head, | ||
| 55 | u64 ddr_offset) | ||
| 56 | { | ||
| 57 | return lv1_gpu_context_attribute(context_handle, | ||
| 58 | L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP, | ||
| 59 | head, ddr_offset, 0, 0); | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar, | ||
| 63 | u64 xdr_size, u64 ioif_offset) | ||
| 64 | { | ||
| 65 | return lv1_gpu_context_attribute(context_handle, | ||
| 66 | L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP, | ||
| 67 | xdr_lpar, xdr_size, ioif_offset, 0); | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset, | ||
| 71 | u64 ioif_offset, u64 sync_width, u64 pitch) | ||
| 72 | { | ||
| 73 | return lv1_gpu_context_attribute(context_handle, | ||
| 74 | L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, | ||
| 75 | ddr_offset, ioif_offset, sync_width, | ||
| 76 | pitch); | ||
| 77 | } | ||
| 78 | |||
| 79 | static inline int lv1_gpu_fb_close(u64 context_handle) | ||
| 80 | { | ||
| 81 | return lv1_gpu_context_attribute(context_handle, | ||
| 82 | L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, | ||
| 83 | 0, 0, 0); | ||
| 84 | } | ||
| 85 | |||
| 86 | #endif /* _ASM_POWERPC_PS3GPU_H */ | ||
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h index c9c678fb2538..8c341490cfc5 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h | |||
| @@ -135,7 +135,9 @@ do { \ | |||
| 135 | * These are defined as per linux/ptrace.h, which see. | 135 | * These are defined as per linux/ptrace.h, which see. |
| 136 | */ | 136 | */ |
| 137 | #define arch_has_single_step() (1) | 137 | #define arch_has_single_step() (1) |
| 138 | #define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) | ||
| 138 | extern void user_enable_single_step(struct task_struct *); | 139 | extern void user_enable_single_step(struct task_struct *); |
| 140 | extern void user_enable_block_step(struct task_struct *); | ||
| 139 | extern void user_disable_single_step(struct task_struct *); | 141 | extern void user_disable_single_step(struct task_struct *); |
| 140 | 142 | ||
| 141 | #endif /* __ASSEMBLY__ */ | 143 | #endif /* __ASSEMBLY__ */ |
| @@ -288,4 +290,6 @@ extern void user_disable_single_step(struct task_struct *); | |||
| 288 | #define PPC_PTRACE_PEEKUSR_3264 0x91 | 290 | #define PPC_PTRACE_PEEKUSR_3264 0x91 |
| 289 | #define PPC_PTRACE_POKEUSR_3264 0x90 | 291 | #define PPC_PTRACE_POKEUSR_3264 0x90 |
| 290 | 292 | ||
| 293 | #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ | ||
| 294 | |||
| 291 | #endif /* _ASM_POWERPC_PTRACE_H */ | 295 | #endif /* _ASM_POWERPC_PTRACE_H */ |
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 2701753d9937..157c5ca581c8 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | #include <asm/cpm.h> | 22 | #include <asm/cpm.h> |
| 23 | #include <asm/immap_qe.h> | 23 | #include <asm/immap_qe.h> |
| 24 | 24 | ||
| 25 | #define QE_NUM_OF_SNUM 28 | 25 | #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ |
| 26 | #define QE_NUM_OF_BRGS 16 | 26 | #define QE_NUM_OF_BRGS 16 |
| 27 | #define QE_NUM_OF_PORTS 1024 | 27 | #define QE_NUM_OF_PORTS 1024 |
| 28 | 28 | ||
| @@ -152,6 +152,9 @@ unsigned int qe_get_brg_clk(void); | |||
| 152 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); | 152 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); |
| 153 | int qe_get_snum(void); | 153 | int qe_get_snum(void); |
| 154 | void qe_put_snum(u8 snum); | 154 | void qe_put_snum(u8 snum); |
| 155 | unsigned int qe_get_num_of_risc(void); | ||
| 156 | unsigned int qe_get_num_of_snums(void); | ||
| 157 | |||
| 155 | /* we actually use cpm_muram implementation, define this for convenience */ | 158 | /* we actually use cpm_muram implementation, define this for convenience */ |
| 156 | #define qe_muram_init cpm_muram_init | 159 | #define qe_muram_init cpm_muram_init |
| 157 | #define qe_muram_alloc cpm_muram_alloc | 160 | #define qe_muram_alloc cpm_muram_alloc |
| @@ -231,12 +234,16 @@ struct qe_bd { | |||
| 231 | #define QE_ALIGNMENT_OF_PRAM 64 | 234 | #define QE_ALIGNMENT_OF_PRAM 64 |
| 232 | 235 | ||
| 233 | /* RISC allocation */ | 236 | /* RISC allocation */ |
| 234 | enum qe_risc_allocation { | 237 | #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ |
| 235 | QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ | 238 | #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ |
| 236 | QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ | 239 | #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ |
| 237 | QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose | 240 | #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ |
| 238 | RISC 1 or RISC 2 */ | 241 | #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ |
| 239 | }; | 242 | QE_RISC_ALLOCATION_RISC2) |
| 243 | #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ | ||
| 244 | QE_RISC_ALLOCATION_RISC2 | \ | ||
| 245 | QE_RISC_ALLOCATION_RISC3 | \ | ||
| 246 | QE_RISC_ALLOCATION_RISC4) | ||
| 240 | 247 | ||
| 241 | /* QE extended filtering Table Lookup Key Size */ | 248 | /* QE extended filtering Table Lookup Key Size */ |
| 242 | enum qe_fltr_tbl_lookup_key_size { | 249 | enum qe_fltr_tbl_lookup_key_size { |
| @@ -668,6 +675,8 @@ struct ucc_slow_pram { | |||
| 668 | #define UCC_GETH_UPSMR_RMM 0x00001000 | 675 | #define UCC_GETH_UPSMR_RMM 0x00001000 |
| 669 | #define UCC_GETH_UPSMR_CAM 0x00000400 | 676 | #define UCC_GETH_UPSMR_CAM 0x00000400 |
| 670 | #define UCC_GETH_UPSMR_BRO 0x00000200 | 677 | #define UCC_GETH_UPSMR_BRO 0x00000200 |
| 678 | #define UCC_GETH_UPSMR_SMM 0x00000080 | ||
| 679 | #define UCC_GETH_UPSMR_SGMM 0x00000020 | ||
| 671 | 680 | ||
| 672 | /* UCC Transmit On Demand Register (UTODR) */ | 681 | /* UCC Transmit On Demand Register (UTODR) */ |
| 673 | #define UCC_SLOW_TOD 0x8000 | 682 | #define UCC_SLOW_TOD 0x8000 |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index e8018d540e87..1170267736d3 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
| @@ -492,11 +492,13 @@ | |||
| 492 | #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ | 492 | #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ |
| 493 | #define SPRN_MMCR1 798 | 493 | #define SPRN_MMCR1 798 |
| 494 | #define SPRN_MMCRA 0x312 | 494 | #define SPRN_MMCRA 0x312 |
| 495 | #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ | ||
| 495 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ | 496 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ |
| 496 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ | 497 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ |
| 497 | #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ | 498 | #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ |
| 498 | #define MMCRA_SLOT_SHIFT 24 | 499 | #define MMCRA_SLOT_SHIFT 24 |
| 499 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ | 500 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ |
| 501 | #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ | ||
| 500 | #define POWER6_MMCRA_SIHV 0x0000040000000000ULL | 502 | #define POWER6_MMCRA_SIHV 0x0000040000000000ULL |
| 501 | #define POWER6_MMCRA_SIPR 0x0000020000000000ULL | 503 | #define POWER6_MMCRA_SIPR 0x0000020000000000ULL |
| 502 | #define POWER6_MMCRA_THRM 0x00000020UL | 504 | #define POWER6_MMCRA_THRM 0x00000020UL |
| @@ -743,17 +745,18 @@ | |||
| 743 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) | 745 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) |
| 744 | #ifdef CONFIG_PPC64 | 746 | #ifdef CONFIG_PPC64 |
| 745 | #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ | 747 | #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ |
| 746 | : : "r" (v)) | 748 | : : "r" (v) : "memory") |
| 747 | #define mtmsrd(v) __mtmsrd((v), 0) | 749 | #define mtmsrd(v) __mtmsrd((v), 0) |
| 748 | #define mtmsr(v) mtmsrd(v) | 750 | #define mtmsr(v) mtmsrd(v) |
| 749 | #else | 751 | #else |
| 750 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) | 752 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v) : "memory") |
| 751 | #endif | 753 | #endif |
| 752 | 754 | ||
| 753 | #define mfspr(rn) ({unsigned long rval; \ | 755 | #define mfspr(rn) ({unsigned long rval; \ |
| 754 | asm volatile("mfspr %0," __stringify(rn) \ | 756 | asm volatile("mfspr %0," __stringify(rn) \ |
| 755 | : "=r" (rval)); rval;}) | 757 | : "=r" (rval)); rval;}) |
| 756 | #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) | 758 | #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\ |
| 759 | : "memory") | ||
| 757 | 760 | ||
| 758 | #ifdef __powerpc64__ | 761 | #ifdef __powerpc64__ |
| 759 | #ifdef CONFIG_PPC_CELL | 762 | #ifdef CONFIG_PPC_CELL |
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 601ddbc46002..6bcf364cbb2f 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
| @@ -389,12 +389,14 @@ | |||
| 389 | #define ICCR_CACHE 1 /* Cacheable */ | 389 | #define ICCR_CACHE 1 /* Cacheable */ |
| 390 | 390 | ||
| 391 | /* Bit definitions for L1CSR0. */ | 391 | /* Bit definitions for L1CSR0. */ |
| 392 | #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ | ||
| 392 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | 393 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ |
| 393 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | 394 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
| 394 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | 395 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ |
| 395 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | 396 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
| 396 | 397 | ||
| 397 | /* Bit definitions for L1CSR1. */ | 398 | /* Bit definitions for L1CSR1. */ |
| 399 | #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ | ||
| 398 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | 400 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ |
| 399 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | 401 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ |
| 400 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | 402 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ |
diff --git a/arch/powerpc/include/asm/scatterlist.h b/arch/powerpc/include/asm/scatterlist.h index fcf7d55afe45..912bf597870f 100644 --- a/arch/powerpc/include/asm/scatterlist.h +++ b/arch/powerpc/include/asm/scatterlist.h | |||
| @@ -21,7 +21,7 @@ struct scatterlist { | |||
| 21 | unsigned int offset; | 21 | unsigned int offset; |
| 22 | unsigned int length; | 22 | unsigned int length; |
| 23 | 23 | ||
| 24 | /* For TCE support */ | 24 | /* For TCE or SWIOTLB support */ |
| 25 | dma_addr_t dma_address; | 25 | dma_addr_t dma_address; |
| 26 | u32 dma_length; | 26 | u32 dma_length; |
| 27 | }; | 27 | }; |
| @@ -34,11 +34,7 @@ struct scatterlist { | |||
| 34 | * is 0. | 34 | * is 0. |
| 35 | */ | 35 | */ |
| 36 | #define sg_dma_address(sg) ((sg)->dma_address) | 36 | #define sg_dma_address(sg) ((sg)->dma_address) |
| 37 | #ifdef __powerpc64__ | ||
| 38 | #define sg_dma_len(sg) ((sg)->dma_length) | 37 | #define sg_dma_len(sg) ((sg)->dma_length) |
| 39 | #else | ||
| 40 | #define sg_dma_len(sg) ((sg)->length) | ||
| 41 | #endif | ||
| 42 | 38 | ||
| 43 | #ifdef __powerpc64__ | 39 | #ifdef __powerpc64__ |
| 44 | #define ISA_DMA_THRESHOLD (~0UL) | 40 | #define ISA_DMA_THRESHOLD (~0UL) |
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h index 69f709d8e8e7..3eb13be11d8f 100644 --- a/arch/powerpc/include/asm/signal.h +++ b/arch/powerpc/include/asm/signal.h | |||
| @@ -94,7 +94,7 @@ typedef struct { | |||
| 94 | #define MINSIGSTKSZ 2048 | 94 | #define MINSIGSTKSZ 2048 |
| 95 | #define SIGSTKSZ 8192 | 95 | #define SIGSTKSZ 8192 |
| 96 | 96 | ||
| 97 | #include <asm-generic/signal.h> | 97 | #include <asm-generic/signal-defs.h> |
| 98 | 98 | ||
| 99 | struct old_sigaction { | 99 | struct old_sigaction { |
| 100 | __sighandler_t sa_handler; | 100 | __sighandler_t sa_handler; |
diff --git a/arch/powerpc/include/asm/swiotlb.h b/arch/powerpc/include/asm/swiotlb.h new file mode 100644 index 000000000000..30891d6e2bc1 --- /dev/null +++ b/arch/powerpc/include/asm/swiotlb.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the | ||
| 6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 7 | * option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_SWIOTLB_H | ||
| 12 | #define __ASM_SWIOTLB_H | ||
| 13 | |||
| 14 | #include <linux/swiotlb.h> | ||
| 15 | |||
| 16 | extern struct dma_mapping_ops swiotlb_dma_ops; | ||
| 17 | extern struct dma_mapping_ops swiotlb_pci_dma_ops; | ||
| 18 | |||
| 19 | int swiotlb_arch_address_needs_mapping(struct device *, dma_addr_t, | ||
| 20 | size_t size); | ||
| 21 | |||
| 22 | static inline void dma_mark_clean(void *addr, size_t size) {} | ||
| 23 | |||
| 24 | extern unsigned int ppc_swiotlb_enable; | ||
| 25 | int __init swiotlb_setup_bus_notifier(void); | ||
| 26 | |||
| 27 | #endif /* __ASM_SWIOTLB_H */ | ||
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index d98a30dfd41c..370600ca2765 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h | |||
| @@ -322,6 +322,7 @@ SYSCALL_SPU(epoll_create1) | |||
| 322 | SYSCALL_SPU(dup3) | 322 | SYSCALL_SPU(dup3) |
| 323 | SYSCALL_SPU(pipe2) | 323 | SYSCALL_SPU(pipe2) |
| 324 | SYSCALL(inotify_init1) | 324 | SYSCALL(inotify_init1) |
| 325 | SYSCALL(ni_syscall) | 325 | SYSCALL_SPU(perf_counter_open) |
| 326 | COMPAT_SYS_SPU(preadv) | 326 | COMPAT_SYS_SPU(preadv) |
| 327 | COMPAT_SYS_SPU(pwritev) | 327 | COMPAT_SYS_SPU(pwritev) |
| 328 | COMPAT_SYS(rt_tgsigqueueinfo) | ||
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h index 2b2420a49884..bb8e006a47c6 100644 --- a/arch/powerpc/include/asm/system.h +++ b/arch/powerpc/include/asm/system.h | |||
| @@ -211,7 +211,7 @@ extern struct task_struct *_switch(struct thread_struct *prev, | |||
| 211 | 211 | ||
| 212 | extern unsigned int rtas_data; | 212 | extern unsigned int rtas_data; |
| 213 | extern int mem_init_done; /* set on boot once kmalloc can be called */ | 213 | extern int mem_init_done; /* set on boot once kmalloc can be called */ |
| 214 | extern int init_bootmem_done; /* set on !NUMA once bootmem is available */ | 214 | extern int init_bootmem_done; /* set once bootmem is available */ |
| 215 | extern phys_addr_t memory_limit; | 215 | extern phys_addr_t memory_limit; |
| 216 | extern unsigned long klimit; | 216 | extern unsigned long klimit; |
| 217 | 217 | ||
diff --git a/arch/powerpc/include/asm/termios.h b/arch/powerpc/include/asm/termios.h index 2c14fea07c8a..a24f48704a34 100644 --- a/arch/powerpc/include/asm/termios.h +++ b/arch/powerpc/include/asm/termios.h | |||
| @@ -78,7 +78,7 @@ struct termio { | |||
| 78 | 78 | ||
| 79 | #ifdef __KERNEL__ | 79 | #ifdef __KERNEL__ |
| 80 | 80 | ||
| 81 | #include <asm-generic/termios.h> | 81 | #include <asm-generic/termios-base.h> |
| 82 | 82 | ||
| 83 | #endif /* __KERNEL__ */ | 83 | #endif /* __KERNEL__ */ |
| 84 | 84 | ||
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index 7ce27a52bb34..a5aea0ca34e9 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h | |||
| @@ -40,15 +40,6 @@ typedef struct { | |||
| 40 | #endif /* __ASSEMBLY__ */ | 40 | #endif /* __ASSEMBLY__ */ |
| 41 | 41 | ||
| 42 | #ifdef __KERNEL__ | 42 | #ifdef __KERNEL__ |
| 43 | /* | ||
| 44 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 45 | */ | ||
| 46 | #ifdef __powerpc64__ | ||
| 47 | #define BITS_PER_LONG 64 | ||
| 48 | #else | ||
| 49 | #define BITS_PER_LONG 32 | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #ifndef __ASSEMBLY__ | 43 | #ifndef __ASSEMBLY__ |
| 53 | 44 | ||
| 54 | typedef __vector128 vector128; | 45 | typedef __vector128 vector128; |
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 3f06f8ec81c5..cef080bfc607 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h | |||
| @@ -341,12 +341,14 @@ | |||
| 341 | #define __NR_dup3 316 | 341 | #define __NR_dup3 316 |
| 342 | #define __NR_pipe2 317 | 342 | #define __NR_pipe2 317 |
| 343 | #define __NR_inotify_init1 318 | 343 | #define __NR_inotify_init1 318 |
| 344 | #define __NR_perf_counter_open 319 | ||
| 344 | #define __NR_preadv 320 | 345 | #define __NR_preadv 320 |
| 345 | #define __NR_pwritev 321 | 346 | #define __NR_pwritev 321 |
| 347 | #define __NR_rt_tgsigqueueinfo 322 | ||
| 346 | 348 | ||
| 347 | #ifdef __KERNEL__ | 349 | #ifdef __KERNEL__ |
| 348 | 350 | ||
| 349 | #define __NR_syscalls 322 | 351 | #define __NR_syscalls 323 |
| 350 | 352 | ||
| 351 | #define __NR__exit __NR_exit | 353 | #define __NR__exit __NR_exit |
| 352 | #define NR_syscalls __NR_syscalls | 354 | #define NR_syscalls __NR_syscalls |
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h new file mode 100644 index 000000000000..7a8275caf6af --- /dev/null +++ b/arch/powerpc/include/asm/xilinx_pci.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Xilinx pci external definitions | ||
| 3 | * | ||
| 4 | * Copyright 2009 Roderick Colenbrander | ||
| 5 | * Copyright 2009 Secret Lab Technologies Ltd. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef INCLUDE_XILINX_PCI | ||
| 13 | #define INCLUDE_XILINX_PCI | ||
| 14 | |||
| 15 | #ifdef CONFIG_XILINX_PCI | ||
| 16 | extern void __init xilinx_pci_init(void); | ||
| 17 | #else | ||
| 18 | static inline void __init xilinx_pci_init(void) { return; } | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* INCLUDE_XILINX_PCI */ | ||
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 71901fbda4a5..b73396b93905 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile | |||
| @@ -4,6 +4,8 @@ | |||
| 4 | 4 | ||
| 5 | CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' | 5 | CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' |
| 6 | 6 | ||
| 7 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 8 | |||
| 7 | ifeq ($(CONFIG_PPC64),y) | 9 | ifeq ($(CONFIG_PPC64),y) |
| 8 | CFLAGS_prom_init.o += -mno-minimal-toc | 10 | CFLAGS_prom_init.o += -mno-minimal-toc |
| 9 | endif | 11 | endif |
| @@ -36,7 +38,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \ | |||
| 36 | firmware.o nvram_64.o | 38 | firmware.o nvram_64.o |
| 37 | obj64-$(CONFIG_RELOCATABLE) += reloc_64.o | 39 | obj64-$(CONFIG_RELOCATABLE) += reloc_64.o |
| 38 | obj-$(CONFIG_PPC64) += vdso64/ | 40 | obj-$(CONFIG_PPC64) += vdso64/ |
| 39 | obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o | 41 | obj-$(CONFIG_ALTIVEC) += vecemu.o |
| 40 | obj-$(CONFIG_PPC_970_NAP) += idle_power4.o | 42 | obj-$(CONFIG_PPC_970_NAP) += idle_power4.o |
| 41 | obj-$(CONFIG_PPC_OF) += of_device.o of_platform.o prom_parse.o | 43 | obj-$(CONFIG_PPC_OF) += of_device.o of_platform.o prom_parse.o |
| 42 | obj-$(CONFIG_PPC_CLOCK) += clock.o | 44 | obj-$(CONFIG_PPC_CLOCK) += clock.o |
| @@ -82,6 +84,7 @@ obj-$(CONFIG_SMP) += smp.o | |||
| 82 | obj-$(CONFIG_KPROBES) += kprobes.o | 84 | obj-$(CONFIG_KPROBES) += kprobes.o |
| 83 | obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o | 85 | obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o |
| 84 | obj-$(CONFIG_STACKTRACE) += stacktrace.o | 86 | obj-$(CONFIG_STACKTRACE) += stacktrace.o |
| 87 | obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o | ||
| 85 | 88 | ||
| 86 | pci64-$(CONFIG_PPC64) += pci_dn.o isa-bridge.o | 89 | pci64-$(CONFIG_PPC64) += pci_dn.o isa-bridge.o |
| 87 | obj-$(CONFIG_PCI) += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \ | 90 | obj-$(CONFIG_PCI) += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \ |
| @@ -94,6 +97,10 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o | |||
| 94 | 97 | ||
| 95 | obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o | 98 | obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o |
| 96 | obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o | 99 | obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o |
| 100 | obj-$(CONFIG_PPC_PERF_CTRS) += perf_counter.o | ||
| 101 | obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ | ||
| 102 | power5+-pmu.o power6-pmu.o power7-pmu.o | ||
| 103 | obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o | ||
| 97 | 104 | ||
| 98 | obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o | 105 | obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o |
| 99 | 106 | ||
| @@ -102,12 +109,14 @@ obj-y += iomap.o | |||
| 102 | endif | 109 | endif |
| 103 | 110 | ||
| 104 | obj-$(CONFIG_PPC64) += $(obj64-y) | 111 | obj-$(CONFIG_PPC64) += $(obj64-y) |
| 112 | obj-$(CONFIG_PPC32) += $(obj32-y) | ||
| 105 | 113 | ||
| 106 | ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),) | 114 | ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),) |
| 107 | obj-y += ppc_save_regs.o | 115 | obj-y += ppc_save_regs.o |
| 108 | endif | 116 | endif |
| 109 | 117 | ||
| 110 | extra-$(CONFIG_PPC_FPU) += fpu.o | 118 | extra-$(CONFIG_PPC_FPU) += fpu.o |
| 119 | extra-$(CONFIG_ALTIVEC) += vector.o | ||
| 111 | extra-$(CONFIG_PPC64) += entry_64.o | 120 | extra-$(CONFIG_PPC64) += entry_64.o |
| 112 | 121 | ||
| 113 | extra-y += systbl_chk.i | 122 | extra-y += systbl_chk.i |
| @@ -120,6 +129,7 @@ PHONY += systbl_chk | |||
| 120 | systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i | 129 | systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i |
| 121 | $(call cmd,systbl_chk) | 130 | $(call cmd,systbl_chk) |
| 122 | 131 | ||
| 132 | ifeq ($(CONFIG_PPC_OF_BOOT_TRAMPOLINE),y) | ||
| 123 | $(obj)/built-in.o: prom_init_check | 133 | $(obj)/built-in.o: prom_init_check |
| 124 | 134 | ||
| 125 | quiet_cmd_prom_init_check = CALL $< | 135 | quiet_cmd_prom_init_check = CALL $< |
| @@ -128,5 +138,6 @@ quiet_cmd_prom_init_check = CALL $< | |||
| 128 | PHONY += prom_init_check | 138 | PHONY += prom_init_check |
| 129 | prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o | 139 | prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o |
| 130 | $(call cmd,prom_init_check) | 140 | $(call cmd,prom_init_check) |
| 141 | endif | ||
| 131 | 142 | ||
| 132 | clean-files := vmlinux.lds | 143 | clean-files := vmlinux.lds |
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c index 5ffcfaa77d6a..a5b632e52fae 100644 --- a/arch/powerpc/kernel/align.c +++ b/arch/powerpc/kernel/align.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <asm/system.h> | 24 | #include <asm/system.h> |
| 25 | #include <asm/cache.h> | 25 | #include <asm/cache.h> |
| 26 | #include <asm/cputable.h> | 26 | #include <asm/cputable.h> |
| 27 | #include <asm/emulated_ops.h> | ||
| 27 | 28 | ||
| 28 | struct aligninfo { | 29 | struct aligninfo { |
| 29 | unsigned char len; | 30 | unsigned char len; |
| @@ -730,8 +731,10 @@ int fix_alignment(struct pt_regs *regs) | |||
| 730 | areg = dsisr & 0x1f; /* register to update */ | 731 | areg = dsisr & 0x1f; /* register to update */ |
| 731 | 732 | ||
| 732 | #ifdef CONFIG_SPE | 733 | #ifdef CONFIG_SPE |
| 733 | if ((instr >> 26) == 0x4) | 734 | if ((instr >> 26) == 0x4) { |
| 735 | PPC_WARN_EMULATED(spe); | ||
| 734 | return emulate_spe(regs, reg, instr); | 736 | return emulate_spe(regs, reg, instr); |
| 737 | } | ||
| 735 | #endif | 738 | #endif |
| 736 | 739 | ||
| 737 | instr = (dsisr >> 10) & 0x7f; | 740 | instr = (dsisr >> 10) & 0x7f; |
| @@ -783,23 +786,28 @@ int fix_alignment(struct pt_regs *regs) | |||
| 783 | flags |= SPLT; | 786 | flags |= SPLT; |
| 784 | nb = 8; | 787 | nb = 8; |
| 785 | } | 788 | } |
| 789 | PPC_WARN_EMULATED(vsx); | ||
| 786 | return emulate_vsx(addr, reg, areg, regs, flags, nb); | 790 | return emulate_vsx(addr, reg, areg, regs, flags, nb); |
| 787 | } | 791 | } |
| 788 | #endif | 792 | #endif |
| 789 | /* A size of 0 indicates an instruction we don't support, with | 793 | /* A size of 0 indicates an instruction we don't support, with |
| 790 | * the exception of DCBZ which is handled as a special case here | 794 | * the exception of DCBZ which is handled as a special case here |
| 791 | */ | 795 | */ |
| 792 | if (instr == DCBZ) | 796 | if (instr == DCBZ) { |
| 797 | PPC_WARN_EMULATED(dcbz); | ||
| 793 | return emulate_dcbz(regs, addr); | 798 | return emulate_dcbz(regs, addr); |
| 799 | } | ||
| 794 | if (unlikely(nb == 0)) | 800 | if (unlikely(nb == 0)) |
| 795 | return 0; | 801 | return 0; |
| 796 | 802 | ||
| 797 | /* Load/Store Multiple instructions are handled in their own | 803 | /* Load/Store Multiple instructions are handled in their own |
| 798 | * function | 804 | * function |
| 799 | */ | 805 | */ |
| 800 | if (flags & M) | 806 | if (flags & M) { |
| 807 | PPC_WARN_EMULATED(multiple); | ||
| 801 | return emulate_multiple(regs, addr, reg, nb, | 808 | return emulate_multiple(regs, addr, reg, nb, |
| 802 | flags, instr, swiz); | 809 | flags, instr, swiz); |
| 810 | } | ||
| 803 | 811 | ||
| 804 | /* Verify the address of the operand */ | 812 | /* Verify the address of the operand */ |
| 805 | if (unlikely(user_mode(regs) && | 813 | if (unlikely(user_mode(regs) && |
| @@ -816,8 +824,12 @@ int fix_alignment(struct pt_regs *regs) | |||
| 816 | } | 824 | } |
| 817 | 825 | ||
| 818 | /* Special case for 16-byte FP loads and stores */ | 826 | /* Special case for 16-byte FP loads and stores */ |
| 819 | if (nb == 16) | 827 | if (nb == 16) { |
| 828 | PPC_WARN_EMULATED(fp_pair); | ||
| 820 | return emulate_fp_pair(addr, reg, flags); | 829 | return emulate_fp_pair(addr, reg, flags); |
| 830 | } | ||
| 831 | |||
| 832 | PPC_WARN_EMULATED(unaligned); | ||
| 821 | 833 | ||
| 822 | /* If we are loading, get the data from user space, else | 834 | /* If we are loading, get the data from user space, else |
| 823 | * get it from register values | 835 | * get it from register values |
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 1e40bc053946..561b64652311 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c | |||
| @@ -122,8 +122,6 @@ int main(void) | |||
| 122 | DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack)); | 122 | DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack)); |
| 123 | DEFINE(PACACURRENT, offsetof(struct paca_struct, __current)); | 123 | DEFINE(PACACURRENT, offsetof(struct paca_struct, __current)); |
| 124 | DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr)); | 124 | DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr)); |
| 125 | DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real)); | ||
| 126 | DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr)); | ||
| 127 | DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr)); | 125 | DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr)); |
| 128 | DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1)); | 126 | DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1)); |
| 129 | DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc)); | 127 | DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc)); |
| @@ -131,35 +129,31 @@ int main(void) | |||
| 131 | DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); | 129 | DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); |
| 132 | DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); | 130 | DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); |
| 133 | DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled)); | 131 | DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled)); |
| 134 | DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); | 132 | DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_counter_pending)); |
| 135 | DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); | ||
| 136 | DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); | 133 | DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); |
| 137 | DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp)); | ||
| 138 | #ifdef CONFIG_PPC_MM_SLICES | 134 | #ifdef CONFIG_PPC_MM_SLICES |
| 139 | DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, | 135 | DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, |
| 140 | context.low_slices_psize)); | 136 | context.low_slices_psize)); |
| 141 | DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct, | 137 | DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct, |
| 142 | context.high_slices_psize)); | 138 | context.high_slices_psize)); |
| 143 | DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); | 139 | DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); |
| 140 | #endif /* CONFIG_PPC_MM_SLICES */ | ||
| 141 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 142 | DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real)); | ||
| 143 | DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr)); | ||
| 144 | DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); | ||
| 145 | DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); | ||
| 146 | DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp)); | ||
| 147 | #ifdef CONFIG_PPC_MM_SLICES | ||
| 144 | DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp)); | 148 | DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp)); |
| 145 | #else | 149 | #else |
| 146 | DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp)); | 150 | DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp)); |
| 147 | |||
| 148 | #endif /* CONFIG_PPC_MM_SLICES */ | 151 | #endif /* CONFIG_PPC_MM_SLICES */ |
| 149 | DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); | 152 | DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); |
| 150 | DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); | 153 | DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); |
| 151 | DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb)); | 154 | DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb)); |
| 152 | DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); | ||
| 153 | DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr)); | 155 | DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr)); |
| 154 | DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); | ||
| 155 | DEFINE(PACA_STARTPURR, offsetof(struct paca_struct, startpurr)); | ||
| 156 | DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr)); | ||
| 157 | DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time)); | ||
| 158 | DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); | ||
| 159 | DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr)); | 156 | DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr)); |
| 160 | DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset)); | ||
| 161 | DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); | ||
| 162 | |||
| 163 | DEFINE(SLBSHADOW_STACKVSID, | 157 | DEFINE(SLBSHADOW_STACKVSID, |
| 164 | offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid)); | 158 | offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid)); |
| 165 | DEFINE(SLBSHADOW_STACKESID, | 159 | DEFINE(SLBSHADOW_STACKESID, |
| @@ -169,6 +163,15 @@ int main(void) | |||
| 169 | DEFINE(LPPACAANYINT, offsetof(struct lppaca, int_dword.any_int)); | 163 | DEFINE(LPPACAANYINT, offsetof(struct lppaca, int_dword.any_int)); |
| 170 | DEFINE(LPPACADECRINT, offsetof(struct lppaca, int_dword.fields.decr_int)); | 164 | DEFINE(LPPACADECRINT, offsetof(struct lppaca, int_dword.fields.decr_int)); |
| 171 | DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area)); | 165 | DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area)); |
| 166 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 167 | DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); | ||
| 168 | DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); | ||
| 169 | DEFINE(PACA_STARTPURR, offsetof(struct paca_struct, startpurr)); | ||
| 170 | DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr)); | ||
| 171 | DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time)); | ||
| 172 | DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); | ||
| 173 | DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset)); | ||
| 174 | DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); | ||
| 172 | #endif /* CONFIG_PPC64 */ | 175 | #endif /* CONFIG_PPC64 */ |
| 173 | 176 | ||
| 174 | /* RTAS */ | 177 | /* RTAS */ |
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S index 54f767e31a1a..1e9949e68856 100644 --- a/arch/powerpc/kernel/cpu_setup_6xx.S +++ b/arch/powerpc/kernel/cpu_setup_6xx.S | |||
| @@ -239,6 +239,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR) | |||
| 239 | ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | 239 | ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE |
| 240 | ori r11,r11,HID0_LRSTK | HID0_BTIC | 240 | ori r11,r11,HID0_LRSTK | HID0_BTIC |
| 241 | oris r11,r11,HID0_DPM@h | 241 | oris r11,r11,HID0_DPM@h |
| 242 | BEGIN_MMU_FTR_SECTION | ||
| 243 | oris r11,r11,HID0_HIGH_BAT@h | ||
| 244 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) | ||
| 242 | BEGIN_FTR_SECTION | 245 | BEGIN_FTR_SECTION |
| 243 | xori r11,r11,HID0_BTIC | 246 | xori r11,r11,HID0_BTIC |
| 244 | END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) | 247 | END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) |
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index eb4b9adcedb4..0adb50ad8031 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S | |||
| @@ -17,6 +17,40 @@ | |||
| 17 | #include <asm/cputable.h> | 17 | #include <asm/cputable.h> |
| 18 | #include <asm/ppc_asm.h> | 18 | #include <asm/ppc_asm.h> |
| 19 | 19 | ||
| 20 | _GLOBAL(__e500_icache_setup) | ||
| 21 | mfspr r0, SPRN_L1CSR1 | ||
| 22 | andi. r3, r0, L1CSR1_ICE | ||
| 23 | bnelr /* Already enabled */ | ||
| 24 | oris r0, r0, L1CSR1_CPE@h | ||
| 25 | ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE) | ||
| 26 | mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */ | ||
| 27 | isync | ||
| 28 | blr | ||
| 29 | |||
| 30 | _GLOBAL(__e500_dcache_setup) | ||
| 31 | mfspr r0, SPRN_L1CSR0 | ||
| 32 | andi. r3, r0, L1CSR0_DCE | ||
| 33 | bnelr /* Already enabled */ | ||
| 34 | msync | ||
| 35 | isync | ||
| 36 | li r0, 0 | ||
| 37 | mtspr SPRN_L1CSR0, r0 /* Disable */ | ||
| 38 | msync | ||
| 39 | isync | ||
| 40 | li r0, (L1CSR0_DCFI | L1CSR0_CLFC) | ||
| 41 | mtspr SPRN_L1CSR0, r0 /* Invalidate */ | ||
| 42 | isync | ||
| 43 | 1: mfspr r0, SPRN_L1CSR0 | ||
| 44 | andi. r3, r0, L1CSR0_CLFC | ||
| 45 | bne+ 1b /* Wait for lock bits reset */ | ||
| 46 | oris r0, r0, L1CSR0_CPE@h | ||
| 47 | ori r0, r0, L1CSR0_DCE | ||
| 48 | msync | ||
| 49 | isync | ||
| 50 | mtspr SPRN_L1CSR0, r0 /* Enable */ | ||
| 51 | isync | ||
| 52 | blr | ||
| 53 | |||
| 20 | _GLOBAL(__setup_cpu_e200) | 54 | _GLOBAL(__setup_cpu_e200) |
| 21 | /* enable dedicated debug exception handling resources (Debug APU) */ | 55 | /* enable dedicated debug exception handling resources (Debug APU) */ |
| 22 | mfspr r3,SPRN_HID0 | 56 | mfspr r3,SPRN_HID0 |
| @@ -25,7 +59,16 @@ _GLOBAL(__setup_cpu_e200) | |||
| 25 | b __setup_e200_ivors | 59 | b __setup_e200_ivors |
| 26 | _GLOBAL(__setup_cpu_e500v1) | 60 | _GLOBAL(__setup_cpu_e500v1) |
| 27 | _GLOBAL(__setup_cpu_e500v2) | 61 | _GLOBAL(__setup_cpu_e500v2) |
| 28 | b __setup_e500_ivors | 62 | mflr r4 |
| 63 | bl __e500_icache_setup | ||
| 64 | bl __e500_dcache_setup | ||
| 65 | bl __setup_e500_ivors | ||
| 66 | mtlr r4 | ||
| 67 | blr | ||
| 29 | _GLOBAL(__setup_cpu_e500mc) | 68 | _GLOBAL(__setup_cpu_e500mc) |
| 30 | b __setup_e500mc_ivors | 69 | mflr r4 |
| 31 | 70 | bl __e500_icache_setup | |
| 71 | bl __e500_dcache_setup | ||
| 72 | bl __setup_e500mc_ivors | ||
| 73 | mtlr r4 | ||
| 74 | blr | ||
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 3e33fb933d99..4a24a2fc4574 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
| @@ -427,7 +427,8 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
| 427 | .cpu_name = "POWER7 (architected)", | 427 | .cpu_name = "POWER7 (architected)", |
| 428 | .cpu_features = CPU_FTRS_POWER7, | 428 | .cpu_features = CPU_FTRS_POWER7, |
| 429 | .cpu_user_features = COMMON_USER_POWER7, | 429 | .cpu_user_features = COMMON_USER_POWER7, |
| 430 | .mmu_features = MMU_FTR_HPTE_TABLE, | 430 | .mmu_features = MMU_FTR_HPTE_TABLE | |
| 431 | MMU_FTR_TLBIE_206, | ||
| 431 | .icache_bsize = 128, | 432 | .icache_bsize = 128, |
| 432 | .dcache_bsize = 128, | 433 | .dcache_bsize = 128, |
| 433 | .machine_check = machine_check_generic, | 434 | .machine_check = machine_check_generic, |
| @@ -441,7 +442,8 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
| 441 | .cpu_name = "POWER7 (raw)", | 442 | .cpu_name = "POWER7 (raw)", |
| 442 | .cpu_features = CPU_FTRS_POWER7, | 443 | .cpu_features = CPU_FTRS_POWER7, |
| 443 | .cpu_user_features = COMMON_USER_POWER7, | 444 | .cpu_user_features = COMMON_USER_POWER7, |
| 444 | .mmu_features = MMU_FTR_HPTE_TABLE, | 445 | .mmu_features = MMU_FTR_HPTE_TABLE | |
| 446 | MMU_FTR_TLBIE_206, | ||
| 445 | .icache_bsize = 128, | 447 | .icache_bsize = 128, |
| 446 | .dcache_bsize = 128, | 448 | .dcache_bsize = 128, |
| 447 | .num_pmcs = 6, | 449 | .num_pmcs = 6, |
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c new file mode 100644 index 000000000000..68ccf11e4f19 --- /dev/null +++ b/arch/powerpc/kernel/dma-swiotlb.c | |||
| @@ -0,0 +1,163 @@ | |||
| 1 | /* | ||
| 2 | * Contains routines needed to support swiotlb for ppc. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/dma-mapping.h> | ||
| 14 | #include <linux/pfn.h> | ||
| 15 | #include <linux/of_platform.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/pci.h> | ||
| 18 | |||
| 19 | #include <asm/machdep.h> | ||
| 20 | #include <asm/swiotlb.h> | ||
| 21 | #include <asm/dma.h> | ||
| 22 | #include <asm/abs_addr.h> | ||
| 23 | |||
| 24 | int swiotlb __read_mostly; | ||
| 25 | unsigned int ppc_swiotlb_enable; | ||
| 26 | |||
| 27 | void *swiotlb_bus_to_virt(struct device *hwdev, dma_addr_t addr) | ||
| 28 | { | ||
| 29 | unsigned long pfn = PFN_DOWN(swiotlb_bus_to_phys(hwdev, addr)); | ||
| 30 | void *pageaddr = page_address(pfn_to_page(pfn)); | ||
| 31 | |||
| 32 | if (pageaddr != NULL) | ||
| 33 | return pageaddr + (addr % PAGE_SIZE); | ||
| 34 | return NULL; | ||
| 35 | } | ||
| 36 | |||
| 37 | dma_addr_t swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr) | ||
| 38 | { | ||
| 39 | return paddr + get_dma_direct_offset(hwdev); | ||
| 40 | } | ||
| 41 | |||
| 42 | phys_addr_t swiotlb_bus_to_phys(struct device *hwdev, dma_addr_t baddr) | ||
| 43 | |||
| 44 | { | ||
| 45 | return baddr - get_dma_direct_offset(hwdev); | ||
| 46 | } | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Determine if an address needs bounce buffering via swiotlb. | ||
| 50 | * Going forward I expect the swiotlb code to generalize on using | ||
| 51 | * a dma_ops->addr_needs_map, and this function will move from here to the | ||
| 52 | * generic swiotlb code. | ||
| 53 | */ | ||
| 54 | int | ||
| 55 | swiotlb_arch_address_needs_mapping(struct device *hwdev, dma_addr_t addr, | ||
| 56 | size_t size) | ||
| 57 | { | ||
| 58 | struct dma_mapping_ops *dma_ops = get_dma_ops(hwdev); | ||
| 59 | |||
| 60 | BUG_ON(!dma_ops); | ||
| 61 | return dma_ops->addr_needs_map(hwdev, addr, size); | ||
| 62 | } | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Determine if an address is reachable by a pci device, or if we must bounce. | ||
| 66 | */ | ||
| 67 | static int | ||
| 68 | swiotlb_pci_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size) | ||
| 69 | { | ||
| 70 | u64 mask = dma_get_mask(hwdev); | ||
| 71 | dma_addr_t max; | ||
| 72 | struct pci_controller *hose; | ||
| 73 | struct pci_dev *pdev = to_pci_dev(hwdev); | ||
| 74 | |||
| 75 | hose = pci_bus_to_host(pdev->bus); | ||
| 76 | max = hose->dma_window_base_cur + hose->dma_window_size; | ||
| 77 | |||
| 78 | /* check that we're within mapped pci window space */ | ||
| 79 | if ((addr + size > max) | (addr < hose->dma_window_base_cur)) | ||
| 80 | return 1; | ||
| 81 | |||
| 82 | return !is_buffer_dma_capable(mask, addr, size); | ||
| 83 | } | ||
| 84 | |||
| 85 | static int | ||
| 86 | swiotlb_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size) | ||
| 87 | { | ||
| 88 | return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size); | ||
| 89 | } | ||
| 90 | |||
| 91 | |||
| 92 | /* | ||
| 93 | * At the moment, all platforms that use this code only require | ||
| 94 | * swiotlb to be used if we're operating on HIGHMEM. Since | ||
| 95 | * we don't ever call anything other than map_sg, unmap_sg, | ||
| 96 | * map_page, and unmap_page on highmem, use normal dma_ops | ||
| 97 | * for everything else. | ||
| 98 | */ | ||
| 99 | struct dma_mapping_ops swiotlb_dma_ops = { | ||
| 100 | .alloc_coherent = dma_direct_alloc_coherent, | ||
| 101 | .free_coherent = dma_direct_free_coherent, | ||
| 102 | .map_sg = swiotlb_map_sg_attrs, | ||
| 103 | .unmap_sg = swiotlb_unmap_sg_attrs, | ||
| 104 | .dma_supported = swiotlb_dma_supported, | ||
| 105 | .map_page = swiotlb_map_page, | ||
| 106 | .unmap_page = swiotlb_unmap_page, | ||
| 107 | .addr_needs_map = swiotlb_addr_needs_map, | ||
| 108 | .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu, | ||
| 109 | .sync_single_range_for_device = swiotlb_sync_single_range_for_device, | ||
| 110 | .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, | ||
| 111 | .sync_sg_for_device = swiotlb_sync_sg_for_device | ||
| 112 | }; | ||
| 113 | |||
| 114 | struct dma_mapping_ops swiotlb_pci_dma_ops = { | ||
| 115 | .alloc_coherent = dma_direct_alloc_coherent, | ||
| 116 | .free_coherent = dma_direct_free_coherent, | ||
| 117 | .map_sg = swiotlb_map_sg_attrs, | ||
| 118 | .unmap_sg = swiotlb_unmap_sg_attrs, | ||
| 119 | .dma_supported = swiotlb_dma_supported, | ||
| 120 | .map_page = swiotlb_map_page, | ||
| 121 | .unmap_page = swiotlb_unmap_page, | ||
| 122 | .addr_needs_map = swiotlb_pci_addr_needs_map, | ||
| 123 | .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu, | ||
| 124 | .sync_single_range_for_device = swiotlb_sync_single_range_for_device, | ||
| 125 | .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, | ||
| 126 | .sync_sg_for_device = swiotlb_sync_sg_for_device | ||
| 127 | }; | ||
| 128 | |||
| 129 | static int ppc_swiotlb_bus_notify(struct notifier_block *nb, | ||
| 130 | unsigned long action, void *data) | ||
| 131 | { | ||
| 132 | struct device *dev = data; | ||
| 133 | |||
| 134 | /* We are only intereted in device addition */ | ||
| 135 | if (action != BUS_NOTIFY_ADD_DEVICE) | ||
| 136 | return 0; | ||
| 137 | |||
| 138 | /* May need to bounce if the device can't address all of DRAM */ | ||
| 139 | if (dma_get_mask(dev) < lmb_end_of_DRAM()) | ||
| 140 | set_dma_ops(dev, &swiotlb_dma_ops); | ||
| 141 | |||
| 142 | return NOTIFY_DONE; | ||
| 143 | } | ||
| 144 | |||
| 145 | static struct notifier_block ppc_swiotlb_plat_bus_notifier = { | ||
| 146 | .notifier_call = ppc_swiotlb_bus_notify, | ||
| 147 | .priority = 0, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct notifier_block ppc_swiotlb_of_bus_notifier = { | ||
| 151 | .notifier_call = ppc_swiotlb_bus_notify, | ||
| 152 | .priority = 0, | ||
| 153 | }; | ||
| 154 | |||
| 155 | int __init swiotlb_setup_bus_notifier(void) | ||
| 156 | { | ||
| 157 | bus_register_notifier(&platform_bus_type, | ||
| 158 | &ppc_swiotlb_plat_bus_notifier); | ||
| 159 | bus_register_notifier(&of_platform_bus_type, | ||
| 160 | &ppc_swiotlb_of_bus_notifier); | ||
| 161 | |||
| 162 | return 0; | ||
| 163 | } | ||
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index 6b02793dc75b..20a60d661ba8 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | * default the offset is PCI_DRAM_OFFSET. | 19 | * default the offset is PCI_DRAM_OFFSET. |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | static unsigned long get_dma_direct_offset(struct device *dev) | 22 | unsigned long get_dma_direct_offset(struct device *dev) |
| 23 | { | 23 | { |
| 24 | if (dev) | 24 | if (dev) |
| 25 | return (unsigned long)dev->archdata.dma_data; | 25 | return (unsigned long)dev->archdata.dma_data; |
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index abfc32330479..43e073477c34 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S | |||
| @@ -526,6 +526,15 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES) | |||
| 526 | 2: | 526 | 2: |
| 527 | TRACE_AND_RESTORE_IRQ(r5); | 527 | TRACE_AND_RESTORE_IRQ(r5); |
| 528 | 528 | ||
| 529 | #ifdef CONFIG_PERF_COUNTERS | ||
| 530 | /* check paca->perf_counter_pending if we're enabling ints */ | ||
| 531 | lbz r3,PACAPERFPEND(r13) | ||
| 532 | and. r3,r3,r5 | ||
| 533 | beq 27f | ||
| 534 | bl .perf_counter_do_pending | ||
| 535 | 27: | ||
| 536 | #endif /* CONFIG_PERF_COUNTERS */ | ||
| 537 | |||
| 529 | /* extract EE bit and use it to restore paca->hard_enabled */ | 538 | /* extract EE bit and use it to restore paca->hard_enabled */ |
| 530 | ld r3,_MSR(r1) | 539 | ld r3,_MSR(r1) |
| 531 | rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ | 540 | rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ |
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S new file mode 100644 index 000000000000..eb898112e577 --- /dev/null +++ b/arch/powerpc/kernel/exceptions-64s.S | |||
| @@ -0,0 +1,978 @@ | |||
| 1 | /* | ||
| 2 | * This file contains the 64-bit "server" PowerPC variant | ||
| 3 | * of the low level exception handling including exception | ||
| 4 | * vectors, exception return, part of the slb and stab | ||
| 5 | * handling and other fixed offset specific things. | ||
| 6 | * | ||
| 7 | * This file is meant to be #included from head_64.S due to | ||
| 8 | * position dependant assembly. | ||
| 9 | * | ||
| 10 | * Most of this originates from head_64.S and thus has the same | ||
| 11 | * copyright history. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * We layout physical memory as follows: | ||
| 17 | * 0x0000 - 0x00ff : Secondary processor spin code | ||
| 18 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | ||
| 19 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | ||
| 20 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | ||
| 21 | * 0x7000 - 0x7fff : FWNMI data area | ||
| 22 | * 0x8000 - : Early init and support code | ||
| 23 | */ | ||
| 24 | |||
| 25 | |||
| 26 | /* | ||
| 27 | * SPRG Usage | ||
| 28 | * | ||
| 29 | * Register Definition | ||
| 30 | * | ||
| 31 | * SPRG0 reserved for hypervisor | ||
| 32 | * SPRG1 temp - used to save gpr | ||
| 33 | * SPRG2 temp - used to save gpr | ||
| 34 | * SPRG3 virt addr of paca | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* | ||
| 38 | * This is the start of the interrupt handlers for pSeries | ||
| 39 | * This code runs with relocation off. | ||
| 40 | * Code from here to __end_interrupts gets copied down to real | ||
| 41 | * address 0x100 when we are running a relocatable kernel. | ||
| 42 | * Therefore any relative branches in this section must only | ||
| 43 | * branch to labels in this section. | ||
| 44 | */ | ||
| 45 | . = 0x100 | ||
| 46 | .globl __start_interrupts | ||
| 47 | __start_interrupts: | ||
| 48 | |||
| 49 | STD_EXCEPTION_PSERIES(0x100, system_reset) | ||
| 50 | |||
| 51 | . = 0x200 | ||
| 52 | _machine_check_pSeries: | ||
| 53 | HMT_MEDIUM | ||
| 54 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 55 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | ||
| 56 | |||
| 57 | . = 0x300 | ||
| 58 | .globl data_access_pSeries | ||
| 59 | data_access_pSeries: | ||
| 60 | HMT_MEDIUM | ||
| 61 | mtspr SPRN_SPRG1,r13 | ||
| 62 | BEGIN_FTR_SECTION | ||
| 63 | mtspr SPRN_SPRG2,r12 | ||
| 64 | mfspr r13,SPRN_DAR | ||
| 65 | mfspr r12,SPRN_DSISR | ||
| 66 | srdi r13,r13,60 | ||
| 67 | rlwimi r13,r12,16,0x20 | ||
| 68 | mfcr r12 | ||
| 69 | cmpwi r13,0x2c | ||
| 70 | beq do_stab_bolted_pSeries | ||
| 71 | mtcrf 0x80,r12 | ||
| 72 | mfspr r12,SPRN_SPRG2 | ||
| 73 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | ||
| 74 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | ||
| 75 | |||
| 76 | . = 0x380 | ||
| 77 | .globl data_access_slb_pSeries | ||
| 78 | data_access_slb_pSeries: | ||
| 79 | HMT_MEDIUM | ||
| 80 | mtspr SPRN_SPRG1,r13 | ||
| 81 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ | ||
| 82 | std r3,PACA_EXSLB+EX_R3(r13) | ||
| 83 | mfspr r3,SPRN_DAR | ||
| 84 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | ||
| 85 | mfcr r9 | ||
| 86 | #ifdef __DISABLED__ | ||
| 87 | /* Keep that around for when we re-implement dynamic VSIDs */ | ||
| 88 | cmpdi r3,0 | ||
| 89 | bge slb_miss_user_pseries | ||
| 90 | #endif /* __DISABLED__ */ | ||
| 91 | std r10,PACA_EXSLB+EX_R10(r13) | ||
| 92 | std r11,PACA_EXSLB+EX_R11(r13) | ||
| 93 | std r12,PACA_EXSLB+EX_R12(r13) | ||
| 94 | mfspr r10,SPRN_SPRG1 | ||
| 95 | std r10,PACA_EXSLB+EX_R13(r13) | ||
| 96 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | ||
| 97 | #ifndef CONFIG_RELOCATABLE | ||
| 98 | b .slb_miss_realmode | ||
| 99 | #else | ||
| 100 | /* | ||
| 101 | * We can't just use a direct branch to .slb_miss_realmode | ||
| 102 | * because the distance from here to there depends on where | ||
| 103 | * the kernel ends up being put. | ||
| 104 | */ | ||
| 105 | mfctr r11 | ||
| 106 | ld r10,PACAKBASE(r13) | ||
| 107 | LOAD_HANDLER(r10, .slb_miss_realmode) | ||
| 108 | mtctr r10 | ||
| 109 | bctr | ||
| 110 | #endif | ||
| 111 | |||
| 112 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | ||
| 113 | |||
| 114 | . = 0x480 | ||
| 115 | .globl instruction_access_slb_pSeries | ||
| 116 | instruction_access_slb_pSeries: | ||
| 117 | HMT_MEDIUM | ||
| 118 | mtspr SPRN_SPRG1,r13 | ||
| 119 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ | ||
| 120 | std r3,PACA_EXSLB+EX_R3(r13) | ||
| 121 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | ||
| 122 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | ||
| 123 | mfcr r9 | ||
| 124 | #ifdef __DISABLED__ | ||
| 125 | /* Keep that around for when we re-implement dynamic VSIDs */ | ||
| 126 | cmpdi r3,0 | ||
| 127 | bge slb_miss_user_pseries | ||
| 128 | #endif /* __DISABLED__ */ | ||
| 129 | std r10,PACA_EXSLB+EX_R10(r13) | ||
| 130 | std r11,PACA_EXSLB+EX_R11(r13) | ||
| 131 | std r12,PACA_EXSLB+EX_R12(r13) | ||
| 132 | mfspr r10,SPRN_SPRG1 | ||
| 133 | std r10,PACA_EXSLB+EX_R13(r13) | ||
| 134 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | ||
| 135 | #ifndef CONFIG_RELOCATABLE | ||
| 136 | b .slb_miss_realmode | ||
| 137 | #else | ||
| 138 | mfctr r11 | ||
| 139 | ld r10,PACAKBASE(r13) | ||
| 140 | LOAD_HANDLER(r10, .slb_miss_realmode) | ||
| 141 | mtctr r10 | ||
| 142 | bctr | ||
| 143 | #endif | ||
| 144 | |||
| 145 | MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) | ||
| 146 | STD_EXCEPTION_PSERIES(0x600, alignment) | ||
| 147 | STD_EXCEPTION_PSERIES(0x700, program_check) | ||
| 148 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | ||
| 149 | MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) | ||
| 150 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) | ||
| 151 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | ||
| 152 | |||
| 153 | . = 0xc00 | ||
| 154 | .globl system_call_pSeries | ||
| 155 | system_call_pSeries: | ||
| 156 | HMT_MEDIUM | ||
| 157 | BEGIN_FTR_SECTION | ||
| 158 | cmpdi r0,0x1ebe | ||
| 159 | beq- 1f | ||
| 160 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | ||
| 161 | mr r9,r13 | ||
| 162 | mfspr r13,SPRN_SPRG3 | ||
| 163 | mfspr r11,SPRN_SRR0 | ||
| 164 | ld r12,PACAKBASE(r13) | ||
| 165 | ld r10,PACAKMSR(r13) | ||
| 166 | LOAD_HANDLER(r12, system_call_entry) | ||
| 167 | mtspr SPRN_SRR0,r12 | ||
| 168 | mfspr r12,SPRN_SRR1 | ||
| 169 | mtspr SPRN_SRR1,r10 | ||
| 170 | rfid | ||
| 171 | b . /* prevent speculative execution */ | ||
| 172 | |||
| 173 | /* Fast LE/BE switch system call */ | ||
| 174 | 1: mfspr r12,SPRN_SRR1 | ||
| 175 | xori r12,r12,MSR_LE | ||
| 176 | mtspr SPRN_SRR1,r12 | ||
| 177 | rfid /* return to userspace */ | ||
| 178 | b . | ||
| 179 | |||
| 180 | STD_EXCEPTION_PSERIES(0xd00, single_step) | ||
| 181 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | ||
| 182 | |||
| 183 | /* We need to deal with the Altivec unavailable exception | ||
| 184 | * here which is at 0xf20, thus in the middle of the | ||
| 185 | * prolog code of the PerformanceMonitor one. A little | ||
| 186 | * trickery is thus necessary | ||
| 187 | */ | ||
| 188 | . = 0xf00 | ||
| 189 | b performance_monitor_pSeries | ||
| 190 | |||
| 191 | . = 0xf20 | ||
| 192 | b altivec_unavailable_pSeries | ||
| 193 | |||
| 194 | . = 0xf40 | ||
| 195 | b vsx_unavailable_pSeries | ||
| 196 | |||
| 197 | #ifdef CONFIG_CBE_RAS | ||
| 198 | HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) | ||
| 199 | #endif /* CONFIG_CBE_RAS */ | ||
| 200 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | ||
| 201 | #ifdef CONFIG_CBE_RAS | ||
| 202 | HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) | ||
| 203 | #endif /* CONFIG_CBE_RAS */ | ||
| 204 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | ||
| 205 | #ifdef CONFIG_CBE_RAS | ||
| 206 | HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) | ||
| 207 | #endif /* CONFIG_CBE_RAS */ | ||
| 208 | |||
| 209 | . = 0x3000 | ||
| 210 | |||
| 211 | /*** pSeries interrupt support ***/ | ||
| 212 | |||
| 213 | /* moved from 0xf00 */ | ||
| 214 | STD_EXCEPTION_PSERIES(., performance_monitor) | ||
| 215 | STD_EXCEPTION_PSERIES(., altivec_unavailable) | ||
| 216 | STD_EXCEPTION_PSERIES(., vsx_unavailable) | ||
| 217 | |||
| 218 | /* | ||
| 219 | * An interrupt came in while soft-disabled; clear EE in SRR1, | ||
| 220 | * clear paca->hard_enabled and return. | ||
| 221 | */ | ||
| 222 | masked_interrupt: | ||
| 223 | stb r10,PACAHARDIRQEN(r13) | ||
| 224 | mtcrf 0x80,r9 | ||
| 225 | ld r9,PACA_EXGEN+EX_R9(r13) | ||
| 226 | mfspr r10,SPRN_SRR1 | ||
| 227 | rldicl r10,r10,48,1 /* clear MSR_EE */ | ||
| 228 | rotldi r10,r10,16 | ||
| 229 | mtspr SPRN_SRR1,r10 | ||
| 230 | ld r10,PACA_EXGEN+EX_R10(r13) | ||
| 231 | mfspr r13,SPRN_SPRG1 | ||
| 232 | rfid | ||
| 233 | b . | ||
| 234 | |||
| 235 | .align 7 | ||
| 236 | do_stab_bolted_pSeries: | ||
| 237 | mtcrf 0x80,r12 | ||
| 238 | mfspr r12,SPRN_SPRG2 | ||
| 239 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) | ||
| 240 | |||
| 241 | #ifdef CONFIG_PPC_PSERIES | ||
| 242 | /* | ||
| 243 | * Vectors for the FWNMI option. Share common code. | ||
| 244 | */ | ||
| 245 | .globl system_reset_fwnmi | ||
| 246 | .align 7 | ||
| 247 | system_reset_fwnmi: | ||
| 248 | HMT_MEDIUM | ||
| 249 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 250 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) | ||
| 251 | |||
| 252 | .globl machine_check_fwnmi | ||
| 253 | .align 7 | ||
| 254 | machine_check_fwnmi: | ||
| 255 | HMT_MEDIUM | ||
| 256 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 257 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | ||
| 258 | |||
| 259 | #endif /* CONFIG_PPC_PSERIES */ | ||
| 260 | |||
| 261 | #ifdef __DISABLED__ | ||
| 262 | /* | ||
| 263 | * This is used for when the SLB miss handler has to go virtual, | ||
| 264 | * which doesn't happen for now anymore but will once we re-implement | ||
| 265 | * dynamic VSIDs for shared page tables | ||
| 266 | */ | ||
| 267 | slb_miss_user_pseries: | ||
| 268 | std r10,PACA_EXGEN+EX_R10(r13) | ||
| 269 | std r11,PACA_EXGEN+EX_R11(r13) | ||
| 270 | std r12,PACA_EXGEN+EX_R12(r13) | ||
| 271 | mfspr r10,SPRG1 | ||
| 272 | ld r11,PACA_EXSLB+EX_R9(r13) | ||
| 273 | ld r12,PACA_EXSLB+EX_R3(r13) | ||
| 274 | std r10,PACA_EXGEN+EX_R13(r13) | ||
| 275 | std r11,PACA_EXGEN+EX_R9(r13) | ||
| 276 | std r12,PACA_EXGEN+EX_R3(r13) | ||
| 277 | clrrdi r12,r13,32 | ||
| 278 | mfmsr r10 | ||
| 279 | mfspr r11,SRR0 /* save SRR0 */ | ||
| 280 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | ||
| 281 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | ||
| 282 | mtspr SRR0,r12 | ||
| 283 | mfspr r12,SRR1 /* and SRR1 */ | ||
| 284 | mtspr SRR1,r10 | ||
| 285 | rfid | ||
| 286 | b . /* prevent spec. execution */ | ||
| 287 | #endif /* __DISABLED__ */ | ||
| 288 | |||
| 289 | .align 7 | ||
| 290 | .globl __end_interrupts | ||
| 291 | __end_interrupts: | ||
| 292 | |||
| 293 | /* | ||
| 294 | * Code from here down to __end_handlers is invoked from the | ||
| 295 | * exception prologs above. Because the prologs assemble the | ||
| 296 | * addresses of these handlers using the LOAD_HANDLER macro, | ||
| 297 | * which uses an addi instruction, these handlers must be in | ||
| 298 | * the first 32k of the kernel image. | ||
| 299 | */ | ||
| 300 | |||
| 301 | /*** Common interrupt handlers ***/ | ||
| 302 | |||
| 303 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | ||
| 304 | |||
| 305 | /* | ||
| 306 | * Machine check is different because we use a different | ||
| 307 | * save area: PACA_EXMC instead of PACA_EXGEN. | ||
| 308 | */ | ||
| 309 | .align 7 | ||
| 310 | .globl machine_check_common | ||
| 311 | machine_check_common: | ||
| 312 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | ||
| 313 | FINISH_NAP | ||
| 314 | DISABLE_INTS | ||
| 315 | bl .save_nvgprs | ||
| 316 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 317 | bl .machine_check_exception | ||
| 318 | b .ret_from_except | ||
| 319 | |||
| 320 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | ||
| 321 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | ||
| 322 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | ||
| 323 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | ||
| 324 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | ||
| 325 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) | ||
| 326 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | ||
| 327 | #ifdef CONFIG_ALTIVEC | ||
| 328 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | ||
| 329 | #else | ||
| 330 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | ||
| 331 | #endif | ||
| 332 | #ifdef CONFIG_CBE_RAS | ||
| 333 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | ||
| 334 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | ||
| 335 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | ||
| 336 | #endif /* CONFIG_CBE_RAS */ | ||
| 337 | |||
| 338 | .align 7 | ||
| 339 | system_call_entry: | ||
| 340 | b system_call_common | ||
| 341 | |||
| 342 | /* | ||
| 343 | * Here we have detected that the kernel stack pointer is bad. | ||
| 344 | * R9 contains the saved CR, r13 points to the paca, | ||
| 345 | * r10 contains the (bad) kernel stack pointer, | ||
| 346 | * r11 and r12 contain the saved SRR0 and SRR1. | ||
| 347 | * We switch to using an emergency stack, save the registers there, | ||
| 348 | * and call kernel_bad_stack(), which panics. | ||
| 349 | */ | ||
| 350 | bad_stack: | ||
| 351 | ld r1,PACAEMERGSP(r13) | ||
| 352 | subi r1,r1,64+INT_FRAME_SIZE | ||
| 353 | std r9,_CCR(r1) | ||
| 354 | std r10,GPR1(r1) | ||
| 355 | std r11,_NIP(r1) | ||
| 356 | std r12,_MSR(r1) | ||
| 357 | mfspr r11,SPRN_DAR | ||
| 358 | mfspr r12,SPRN_DSISR | ||
| 359 | std r11,_DAR(r1) | ||
| 360 | std r12,_DSISR(r1) | ||
| 361 | mflr r10 | ||
| 362 | mfctr r11 | ||
| 363 | mfxer r12 | ||
| 364 | std r10,_LINK(r1) | ||
| 365 | std r11,_CTR(r1) | ||
| 366 | std r12,_XER(r1) | ||
| 367 | SAVE_GPR(0,r1) | ||
| 368 | SAVE_GPR(2,r1) | ||
| 369 | SAVE_4GPRS(3,r1) | ||
| 370 | SAVE_2GPRS(7,r1) | ||
| 371 | SAVE_10GPRS(12,r1) | ||
| 372 | SAVE_10GPRS(22,r1) | ||
| 373 | lhz r12,PACA_TRAP_SAVE(r13) | ||
| 374 | std r12,_TRAP(r1) | ||
| 375 | addi r11,r1,INT_FRAME_SIZE | ||
| 376 | std r11,0(r1) | ||
| 377 | li r12,0 | ||
| 378 | std r12,0(r11) | ||
| 379 | ld r2,PACATOC(r13) | ||
| 380 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 381 | bl .kernel_bad_stack | ||
| 382 | b 1b | ||
| 383 | |||
| 384 | /* | ||
| 385 | * Here r13 points to the paca, r9 contains the saved CR, | ||
| 386 | * SRR0 and SRR1 are saved in r11 and r12, | ||
| 387 | * r9 - r13 are saved in paca->exgen. | ||
| 388 | */ | ||
| 389 | .align 7 | ||
| 390 | .globl data_access_common | ||
| 391 | data_access_common: | ||
| 392 | mfspr r10,SPRN_DAR | ||
| 393 | std r10,PACA_EXGEN+EX_DAR(r13) | ||
| 394 | mfspr r10,SPRN_DSISR | ||
| 395 | stw r10,PACA_EXGEN+EX_DSISR(r13) | ||
| 396 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | ||
| 397 | ld r3,PACA_EXGEN+EX_DAR(r13) | ||
| 398 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | ||
| 399 | li r5,0x300 | ||
| 400 | b .do_hash_page /* Try to handle as hpte fault */ | ||
| 401 | |||
| 402 | .align 7 | ||
| 403 | .globl instruction_access_common | ||
| 404 | instruction_access_common: | ||
| 405 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | ||
| 406 | ld r3,_NIP(r1) | ||
| 407 | andis. r4,r12,0x5820 | ||
| 408 | li r5,0x400 | ||
| 409 | b .do_hash_page /* Try to handle as hpte fault */ | ||
| 410 | |||
| 411 | /* | ||
| 412 | * Here is the common SLB miss user that is used when going to virtual | ||
| 413 | * mode for SLB misses, that is currently not used | ||
| 414 | */ | ||
| 415 | #ifdef __DISABLED__ | ||
| 416 | .align 7 | ||
| 417 | .globl slb_miss_user_common | ||
| 418 | slb_miss_user_common: | ||
| 419 | mflr r10 | ||
| 420 | std r3,PACA_EXGEN+EX_DAR(r13) | ||
| 421 | stw r9,PACA_EXGEN+EX_CCR(r13) | ||
| 422 | std r10,PACA_EXGEN+EX_LR(r13) | ||
| 423 | std r11,PACA_EXGEN+EX_SRR0(r13) | ||
| 424 | bl .slb_allocate_user | ||
| 425 | |||
| 426 | ld r10,PACA_EXGEN+EX_LR(r13) | ||
| 427 | ld r3,PACA_EXGEN+EX_R3(r13) | ||
| 428 | lwz r9,PACA_EXGEN+EX_CCR(r13) | ||
| 429 | ld r11,PACA_EXGEN+EX_SRR0(r13) | ||
| 430 | mtlr r10 | ||
| 431 | beq- slb_miss_fault | ||
| 432 | |||
| 433 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | ||
| 434 | beq- unrecov_user_slb | ||
| 435 | mfmsr r10 | ||
| 436 | |||
| 437 | .machine push | ||
| 438 | .machine "power4" | ||
| 439 | mtcrf 0x80,r9 | ||
| 440 | .machine pop | ||
| 441 | |||
| 442 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | ||
| 443 | mtmsrd r10,1 | ||
| 444 | |||
| 445 | mtspr SRR0,r11 | ||
| 446 | mtspr SRR1,r12 | ||
| 447 | |||
| 448 | ld r9,PACA_EXGEN+EX_R9(r13) | ||
| 449 | ld r10,PACA_EXGEN+EX_R10(r13) | ||
| 450 | ld r11,PACA_EXGEN+EX_R11(r13) | ||
| 451 | ld r12,PACA_EXGEN+EX_R12(r13) | ||
| 452 | ld r13,PACA_EXGEN+EX_R13(r13) | ||
| 453 | rfid | ||
| 454 | b . | ||
| 455 | |||
| 456 | slb_miss_fault: | ||
| 457 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | ||
| 458 | ld r4,PACA_EXGEN+EX_DAR(r13) | ||
| 459 | li r5,0 | ||
| 460 | std r4,_DAR(r1) | ||
| 461 | std r5,_DSISR(r1) | ||
| 462 | b handle_page_fault | ||
| 463 | |||
| 464 | unrecov_user_slb: | ||
| 465 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | ||
| 466 | DISABLE_INTS | ||
| 467 | bl .save_nvgprs | ||
| 468 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 469 | bl .unrecoverable_exception | ||
| 470 | b 1b | ||
| 471 | |||
| 472 | #endif /* __DISABLED__ */ | ||
| 473 | |||
| 474 | |||
| 475 | /* | ||
| 476 | * r13 points to the PACA, r9 contains the saved CR, | ||
| 477 | * r12 contain the saved SRR1, SRR0 is still ready for return | ||
| 478 | * r3 has the faulting address | ||
| 479 | * r9 - r13 are saved in paca->exslb. | ||
| 480 | * r3 is saved in paca->slb_r3 | ||
| 481 | * We assume we aren't going to take any exceptions during this procedure. | ||
| 482 | */ | ||
| 483 | _GLOBAL(slb_miss_realmode) | ||
| 484 | mflr r10 | ||
| 485 | #ifdef CONFIG_RELOCATABLE | ||
| 486 | mtctr r11 | ||
| 487 | #endif | ||
| 488 | |||
| 489 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | ||
| 490 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | ||
| 491 | |||
| 492 | bl .slb_allocate_realmode | ||
| 493 | |||
| 494 | /* All done -- return from exception. */ | ||
| 495 | |||
| 496 | ld r10,PACA_EXSLB+EX_LR(r13) | ||
| 497 | ld r3,PACA_EXSLB+EX_R3(r13) | ||
| 498 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | ||
| 499 | #ifdef CONFIG_PPC_ISERIES | ||
| 500 | BEGIN_FW_FTR_SECTION | ||
| 501 | ld r11,PACALPPACAPTR(r13) | ||
| 502 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | ||
| 503 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 504 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 505 | |||
| 506 | mtlr r10 | ||
| 507 | |||
| 508 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | ||
| 509 | beq- 2f | ||
| 510 | |||
| 511 | .machine push | ||
| 512 | .machine "power4" | ||
| 513 | mtcrf 0x80,r9 | ||
| 514 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | ||
| 515 | .machine pop | ||
| 516 | |||
| 517 | #ifdef CONFIG_PPC_ISERIES | ||
| 518 | BEGIN_FW_FTR_SECTION | ||
| 519 | mtspr SPRN_SRR0,r11 | ||
| 520 | mtspr SPRN_SRR1,r12 | ||
| 521 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 522 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 523 | ld r9,PACA_EXSLB+EX_R9(r13) | ||
| 524 | ld r10,PACA_EXSLB+EX_R10(r13) | ||
| 525 | ld r11,PACA_EXSLB+EX_R11(r13) | ||
| 526 | ld r12,PACA_EXSLB+EX_R12(r13) | ||
| 527 | ld r13,PACA_EXSLB+EX_R13(r13) | ||
| 528 | rfid | ||
| 529 | b . /* prevent speculative execution */ | ||
| 530 | |||
| 531 | 2: | ||
| 532 | #ifdef CONFIG_PPC_ISERIES | ||
| 533 | BEGIN_FW_FTR_SECTION | ||
| 534 | b unrecov_slb | ||
| 535 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 536 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 537 | mfspr r11,SPRN_SRR0 | ||
| 538 | ld r10,PACAKBASE(r13) | ||
| 539 | LOAD_HANDLER(r10,unrecov_slb) | ||
| 540 | mtspr SPRN_SRR0,r10 | ||
| 541 | ld r10,PACAKMSR(r13) | ||
| 542 | mtspr SPRN_SRR1,r10 | ||
| 543 | rfid | ||
| 544 | b . | ||
| 545 | |||
| 546 | unrecov_slb: | ||
| 547 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | ||
| 548 | DISABLE_INTS | ||
| 549 | bl .save_nvgprs | ||
| 550 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 551 | bl .unrecoverable_exception | ||
| 552 | b 1b | ||
| 553 | |||
| 554 | .align 7 | ||
| 555 | .globl hardware_interrupt_common | ||
| 556 | .globl hardware_interrupt_entry | ||
| 557 | hardware_interrupt_common: | ||
| 558 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | ||
| 559 | FINISH_NAP | ||
| 560 | hardware_interrupt_entry: | ||
| 561 | DISABLE_INTS | ||
| 562 | BEGIN_FTR_SECTION | ||
| 563 | bl .ppc64_runlatch_on | ||
| 564 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | ||
| 565 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 566 | bl .do_IRQ | ||
| 567 | b .ret_from_except_lite | ||
| 568 | |||
| 569 | #ifdef CONFIG_PPC_970_NAP | ||
| 570 | power4_fixup_nap: | ||
| 571 | andc r9,r9,r10 | ||
| 572 | std r9,TI_LOCAL_FLAGS(r11) | ||
| 573 | ld r10,_LINK(r1) /* make idle task do the */ | ||
| 574 | std r10,_NIP(r1) /* equivalent of a blr */ | ||
| 575 | blr | ||
| 576 | #endif | ||
| 577 | |||
| 578 | .align 7 | ||
| 579 | .globl alignment_common | ||
| 580 | alignment_common: | ||
| 581 | mfspr r10,SPRN_DAR | ||
| 582 | std r10,PACA_EXGEN+EX_DAR(r13) | ||
| 583 | mfspr r10,SPRN_DSISR | ||
| 584 | stw r10,PACA_EXGEN+EX_DSISR(r13) | ||
| 585 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | ||
| 586 | ld r3,PACA_EXGEN+EX_DAR(r13) | ||
| 587 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | ||
| 588 | std r3,_DAR(r1) | ||
| 589 | std r4,_DSISR(r1) | ||
| 590 | bl .save_nvgprs | ||
| 591 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 592 | ENABLE_INTS | ||
| 593 | bl .alignment_exception | ||
| 594 | b .ret_from_except | ||
| 595 | |||
| 596 | .align 7 | ||
| 597 | .globl program_check_common | ||
| 598 | program_check_common: | ||
| 599 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | ||
| 600 | bl .save_nvgprs | ||
| 601 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 602 | ENABLE_INTS | ||
| 603 | bl .program_check_exception | ||
| 604 | b .ret_from_except | ||
| 605 | |||
| 606 | .align 7 | ||
| 607 | .globl fp_unavailable_common | ||
| 608 | fp_unavailable_common: | ||
| 609 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | ||
| 610 | bne 1f /* if from user, just load it up */ | ||
| 611 | bl .save_nvgprs | ||
| 612 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 613 | ENABLE_INTS | ||
| 614 | bl .kernel_fp_unavailable_exception | ||
| 615 | BUG_OPCODE | ||
| 616 | 1: bl .load_up_fpu | ||
| 617 | b fast_exception_return | ||
| 618 | |||
| 619 | .align 7 | ||
| 620 | .globl altivec_unavailable_common | ||
| 621 | altivec_unavailable_common: | ||
| 622 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | ||
| 623 | #ifdef CONFIG_ALTIVEC | ||
| 624 | BEGIN_FTR_SECTION | ||
| 625 | beq 1f | ||
| 626 | bl .load_up_altivec | ||
| 627 | b fast_exception_return | ||
| 628 | 1: | ||
| 629 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | ||
| 630 | #endif | ||
| 631 | bl .save_nvgprs | ||
| 632 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 633 | ENABLE_INTS | ||
| 634 | bl .altivec_unavailable_exception | ||
| 635 | b .ret_from_except | ||
| 636 | |||
| 637 | .align 7 | ||
| 638 | .globl vsx_unavailable_common | ||
| 639 | vsx_unavailable_common: | ||
| 640 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | ||
| 641 | #ifdef CONFIG_VSX | ||
| 642 | BEGIN_FTR_SECTION | ||
| 643 | bne .load_up_vsx | ||
| 644 | 1: | ||
| 645 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | ||
| 646 | #endif | ||
| 647 | bl .save_nvgprs | ||
| 648 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 649 | ENABLE_INTS | ||
| 650 | bl .vsx_unavailable_exception | ||
| 651 | b .ret_from_except | ||
| 652 | |||
| 653 | .align 7 | ||
| 654 | .globl __end_handlers | ||
| 655 | __end_handlers: | ||
| 656 | |||
| 657 | /* | ||
| 658 | * Return from an exception with minimal checks. | ||
| 659 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | ||
| 660 | * If interrupts have been enabled, or anything has been | ||
| 661 | * done that might have changed the scheduling status of | ||
| 662 | * any task or sent any task a signal, you should use | ||
| 663 | * ret_from_except or ret_from_except_lite instead of this. | ||
| 664 | */ | ||
| 665 | fast_exc_return_irq: /* restores irq state too */ | ||
| 666 | ld r3,SOFTE(r1) | ||
| 667 | TRACE_AND_RESTORE_IRQ(r3); | ||
| 668 | ld r12,_MSR(r1) | ||
| 669 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | ||
| 670 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | ||
| 671 | b 1f | ||
| 672 | |||
| 673 | .globl fast_exception_return | ||
| 674 | fast_exception_return: | ||
| 675 | ld r12,_MSR(r1) | ||
| 676 | 1: ld r11,_NIP(r1) | ||
| 677 | andi. r3,r12,MSR_RI /* check if RI is set */ | ||
| 678 | beq- unrecov_fer | ||
| 679 | |||
| 680 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | ||
| 681 | andi. r3,r12,MSR_PR | ||
| 682 | beq 2f | ||
| 683 | ACCOUNT_CPU_USER_EXIT(r3, r4) | ||
| 684 | 2: | ||
| 685 | #endif | ||
| 686 | |||
| 687 | ld r3,_CCR(r1) | ||
| 688 | ld r4,_LINK(r1) | ||
| 689 | ld r5,_CTR(r1) | ||
| 690 | ld r6,_XER(r1) | ||
| 691 | mtcr r3 | ||
| 692 | mtlr r4 | ||
| 693 | mtctr r5 | ||
| 694 | mtxer r6 | ||
| 695 | REST_GPR(0, r1) | ||
| 696 | REST_8GPRS(2, r1) | ||
| 697 | |||
| 698 | mfmsr r10 | ||
| 699 | rldicl r10,r10,48,1 /* clear EE */ | ||
| 700 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | ||
| 701 | mtmsrd r10,1 | ||
| 702 | |||
| 703 | mtspr SPRN_SRR1,r12 | ||
| 704 | mtspr SPRN_SRR0,r11 | ||
| 705 | REST_4GPRS(10, r1) | ||
| 706 | ld r1,GPR1(r1) | ||
| 707 | rfid | ||
| 708 | b . /* prevent speculative execution */ | ||
| 709 | |||
| 710 | unrecov_fer: | ||
| 711 | bl .save_nvgprs | ||
| 712 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 713 | bl .unrecoverable_exception | ||
| 714 | b 1b | ||
| 715 | |||
| 716 | |||
| 717 | /* | ||
| 718 | * Hash table stuff | ||
| 719 | */ | ||
| 720 | .align 7 | ||
| 721 | _STATIC(do_hash_page) | ||
| 722 | std r3,_DAR(r1) | ||
| 723 | std r4,_DSISR(r1) | ||
| 724 | |||
| 725 | andis. r0,r4,0xa450 /* weird error? */ | ||
| 726 | bne- handle_page_fault /* if not, try to insert a HPTE */ | ||
| 727 | BEGIN_FTR_SECTION | ||
| 728 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | ||
| 729 | bne- do_ste_alloc /* If so handle it */ | ||
| 730 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | ||
| 731 | |||
| 732 | /* | ||
| 733 | * On iSeries, we soft-disable interrupts here, then | ||
| 734 | * hard-enable interrupts so that the hash_page code can spin on | ||
| 735 | * the hash_table_lock without problems on a shared processor. | ||
| 736 | */ | ||
| 737 | DISABLE_INTS | ||
| 738 | |||
| 739 | /* | ||
| 740 | * Currently, trace_hardirqs_off() will be called by DISABLE_INTS | ||
| 741 | * and will clobber volatile registers when irq tracing is enabled | ||
| 742 | * so we need to reload them. It may be possible to be smarter here | ||
| 743 | * and move the irq tracing elsewhere but let's keep it simple for | ||
| 744 | * now | ||
| 745 | */ | ||
| 746 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 747 | ld r3,_DAR(r1) | ||
| 748 | ld r4,_DSISR(r1) | ||
| 749 | ld r5,_TRAP(r1) | ||
| 750 | ld r12,_MSR(r1) | ||
| 751 | clrrdi r5,r5,4 | ||
| 752 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 753 | /* | ||
| 754 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | ||
| 755 | * accessing a userspace segment (even from the kernel). We assume | ||
| 756 | * kernel addresses always have the high bit set. | ||
| 757 | */ | ||
| 758 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | ||
| 759 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | ||
| 760 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | ||
| 761 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | ||
| 762 | ori r4,r4,1 /* add _PAGE_PRESENT */ | ||
| 763 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | ||
| 764 | |||
| 765 | /* | ||
| 766 | * r3 contains the faulting address | ||
| 767 | * r4 contains the required access permissions | ||
| 768 | * r5 contains the trap number | ||
| 769 | * | ||
| 770 | * at return r3 = 0 for success | ||
| 771 | */ | ||
| 772 | bl .hash_page /* build HPTE if possible */ | ||
| 773 | cmpdi r3,0 /* see if hash_page succeeded */ | ||
| 774 | |||
| 775 | BEGIN_FW_FTR_SECTION | ||
| 776 | /* | ||
| 777 | * If we had interrupts soft-enabled at the point where the | ||
| 778 | * DSI/ISI occurred, and an interrupt came in during hash_page, | ||
| 779 | * handle it now. | ||
| 780 | * We jump to ret_from_except_lite rather than fast_exception_return | ||
| 781 | * because ret_from_except_lite will check for and handle pending | ||
| 782 | * interrupts if necessary. | ||
| 783 | */ | ||
| 784 | beq 13f | ||
| 785 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 786 | |||
| 787 | BEGIN_FW_FTR_SECTION | ||
| 788 | /* | ||
| 789 | * Here we have interrupts hard-disabled, so it is sufficient | ||
| 790 | * to restore paca->{soft,hard}_enable and get out. | ||
| 791 | */ | ||
| 792 | beq fast_exc_return_irq /* Return from exception on success */ | ||
| 793 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | ||
| 794 | |||
| 795 | /* For a hash failure, we don't bother re-enabling interrupts */ | ||
| 796 | ble- 12f | ||
| 797 | |||
| 798 | /* | ||
| 799 | * hash_page couldn't handle it, set soft interrupt enable back | ||
| 800 | * to what it was before the trap. Note that .raw_local_irq_restore | ||
| 801 | * handles any interrupts pending at this point. | ||
| 802 | */ | ||
| 803 | ld r3,SOFTE(r1) | ||
| 804 | TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) | ||
| 805 | bl .raw_local_irq_restore | ||
| 806 | b 11f | ||
| 807 | |||
| 808 | /* Here we have a page fault that hash_page can't handle. */ | ||
| 809 | handle_page_fault: | ||
| 810 | ENABLE_INTS | ||
| 811 | 11: ld r4,_DAR(r1) | ||
| 812 | ld r5,_DSISR(r1) | ||
| 813 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 814 | bl .do_page_fault | ||
| 815 | cmpdi r3,0 | ||
| 816 | beq+ 13f | ||
| 817 | bl .save_nvgprs | ||
| 818 | mr r5,r3 | ||
| 819 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 820 | lwz r4,_DAR(r1) | ||
| 821 | bl .bad_page_fault | ||
| 822 | b .ret_from_except | ||
| 823 | |||
| 824 | 13: b .ret_from_except_lite | ||
| 825 | |||
| 826 | /* We have a page fault that hash_page could handle but HV refused | ||
| 827 | * the PTE insertion | ||
| 828 | */ | ||
| 829 | 12: bl .save_nvgprs | ||
| 830 | mr r5,r3 | ||
| 831 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 832 | ld r4,_DAR(r1) | ||
| 833 | bl .low_hash_fault | ||
| 834 | b .ret_from_except | ||
| 835 | |||
| 836 | /* here we have a segment miss */ | ||
| 837 | do_ste_alloc: | ||
| 838 | bl .ste_allocate /* try to insert stab entry */ | ||
| 839 | cmpdi r3,0 | ||
| 840 | bne- handle_page_fault | ||
| 841 | b fast_exception_return | ||
| 842 | |||
| 843 | /* | ||
| 844 | * r13 points to the PACA, r9 contains the saved CR, | ||
| 845 | * r11 and r12 contain the saved SRR0 and SRR1. | ||
| 846 | * r9 - r13 are saved in paca->exslb. | ||
| 847 | * We assume we aren't going to take any exceptions during this procedure. | ||
| 848 | * We assume (DAR >> 60) == 0xc. | ||
| 849 | */ | ||
| 850 | .align 7 | ||
| 851 | _GLOBAL(do_stab_bolted) | ||
| 852 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | ||
| 853 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | ||
| 854 | |||
| 855 | /* Hash to the primary group */ | ||
| 856 | ld r10,PACASTABVIRT(r13) | ||
| 857 | mfspr r11,SPRN_DAR | ||
| 858 | srdi r11,r11,28 | ||
| 859 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | ||
| 860 | |||
| 861 | /* Calculate VSID */ | ||
| 862 | /* This is a kernel address, so protovsid = ESID */ | ||
| 863 | ASM_VSID_SCRAMBLE(r11, r9, 256M) | ||
| 864 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | ||
| 865 | |||
| 866 | /* Search the primary group for a free entry */ | ||
| 867 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | ||
| 868 | andi. r11,r11,0x80 | ||
| 869 | beq 2f | ||
| 870 | addi r10,r10,16 | ||
| 871 | andi. r11,r10,0x70 | ||
| 872 | bne 1b | ||
| 873 | |||
| 874 | /* Stick for only searching the primary group for now. */ | ||
| 875 | /* At least for now, we use a very simple random castout scheme */ | ||
| 876 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | ||
| 877 | mftb r11 | ||
| 878 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | ||
| 879 | ori r11,r11,0x10 | ||
| 880 | |||
| 881 | /* r10 currently points to an ste one past the group of interest */ | ||
| 882 | /* make it point to the randomly selected entry */ | ||
| 883 | subi r10,r10,128 | ||
| 884 | or r10,r10,r11 /* r10 is the entry to invalidate */ | ||
| 885 | |||
| 886 | isync /* mark the entry invalid */ | ||
| 887 | ld r11,0(r10) | ||
| 888 | rldicl r11,r11,56,1 /* clear the valid bit */ | ||
| 889 | rotldi r11,r11,8 | ||
| 890 | std r11,0(r10) | ||
| 891 | sync | ||
| 892 | |||
| 893 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | ||
| 894 | slbie r11 | ||
| 895 | |||
| 896 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | ||
| 897 | eieio | ||
| 898 | |||
| 899 | mfspr r11,SPRN_DAR /* Get the new esid */ | ||
| 900 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | ||
| 901 | ori r11,r11,0x90 /* Turn on valid and kp */ | ||
| 902 | std r11,0(r10) /* Put new entry back into the stab */ | ||
| 903 | |||
| 904 | sync | ||
| 905 | |||
| 906 | /* All done -- return from exception. */ | ||
| 907 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | ||
| 908 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | ||
| 909 | |||
| 910 | andi. r10,r12,MSR_RI | ||
| 911 | beq- unrecov_slb | ||
| 912 | |||
| 913 | mtcrf 0x80,r9 /* restore CR */ | ||
| 914 | |||
| 915 | mfmsr r10 | ||
| 916 | clrrdi r10,r10,2 | ||
| 917 | mtmsrd r10,1 | ||
| 918 | |||
| 919 | mtspr SPRN_SRR0,r11 | ||
| 920 | mtspr SPRN_SRR1,r12 | ||
| 921 | ld r9,PACA_EXSLB+EX_R9(r13) | ||
| 922 | ld r10,PACA_EXSLB+EX_R10(r13) | ||
| 923 | ld r11,PACA_EXSLB+EX_R11(r13) | ||
| 924 | ld r12,PACA_EXSLB+EX_R12(r13) | ||
| 925 | ld r13,PACA_EXSLB+EX_R13(r13) | ||
| 926 | rfid | ||
| 927 | b . /* prevent speculative execution */ | ||
| 928 | |||
| 929 | /* | ||
| 930 | * Space for CPU0's segment table. | ||
| 931 | * | ||
| 932 | * On iSeries, the hypervisor must fill in at least one entry before | ||
| 933 | * we get control (with relocate on). The address is given to the hv | ||
| 934 | * as a page number (see xLparMap below), so this must be at a | ||
| 935 | * fixed address (the linker can't compute (u64)&initial_stab >> | ||
| 936 | * PAGE_SHIFT). | ||
| 937 | */ | ||
| 938 | . = STAB0_OFFSET /* 0x6000 */ | ||
| 939 | .globl initial_stab | ||
| 940 | initial_stab: | ||
| 941 | .space 4096 | ||
| 942 | |||
| 943 | #ifdef CONFIG_PPC_PSERIES | ||
| 944 | /* | ||
| 945 | * Data area reserved for FWNMI option. | ||
| 946 | * This address (0x7000) is fixed by the RPA. | ||
| 947 | */ | ||
| 948 | .= 0x7000 | ||
| 949 | .globl fwnmi_data_area | ||
| 950 | fwnmi_data_area: | ||
| 951 | #endif /* CONFIG_PPC_PSERIES */ | ||
| 952 | |||
| 953 | /* iSeries does not use the FWNMI stuff, so it is safe to put | ||
| 954 | * this here, even if we later allow kernels that will boot on | ||
| 955 | * both pSeries and iSeries */ | ||
| 956 | #ifdef CONFIG_PPC_ISERIES | ||
| 957 | . = LPARMAP_PHYS | ||
| 958 | .globl xLparMap | ||
| 959 | xLparMap: | ||
| 960 | .quad HvEsidsToMap /* xNumberEsids */ | ||
| 961 | .quad HvRangesToMap /* xNumberRanges */ | ||
| 962 | .quad STAB0_PAGE /* xSegmentTableOffs */ | ||
| 963 | .zero 40 /* xRsvd */ | ||
| 964 | /* xEsids (HvEsidsToMap entries of 2 quads) */ | ||
| 965 | .quad PAGE_OFFSET_ESID /* xKernelEsid */ | ||
| 966 | .quad PAGE_OFFSET_VSID /* xKernelVsid */ | ||
| 967 | .quad VMALLOC_START_ESID /* xKernelEsid */ | ||
| 968 | .quad VMALLOC_START_VSID /* xKernelVsid */ | ||
| 969 | /* xRanges (HvRangesToMap entries of 3 quads) */ | ||
| 970 | .quad HvPagesToMap /* xPages */ | ||
| 971 | .quad 0 /* xOffset */ | ||
| 972 | .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ | ||
| 973 | |||
| 974 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 975 | |||
| 976 | #ifdef CONFIG_PPC_PSERIES | ||
| 977 | . = 0x8000 | ||
| 978 | #endif /* CONFIG_PPC_PSERIES */ | ||
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c index 2d182f119d1d..ce1f3e44c24f 100644 --- a/arch/powerpc/kernel/ftrace.c +++ b/arch/powerpc/kernel/ftrace.c | |||
| @@ -23,25 +23,14 @@ | |||
| 23 | #include <asm/code-patching.h> | 23 | #include <asm/code-patching.h> |
| 24 | #include <asm/ftrace.h> | 24 | #include <asm/ftrace.h> |
| 25 | 25 | ||
| 26 | #ifdef CONFIG_PPC32 | ||
| 27 | # define GET_ADDR(addr) addr | ||
| 28 | #else | ||
| 29 | /* PowerPC64's functions are data that points to the functions */ | ||
| 30 | # define GET_ADDR(addr) (*(unsigned long *)addr) | ||
| 31 | #endif | ||
| 32 | 26 | ||
| 33 | #ifdef CONFIG_DYNAMIC_FTRACE | 27 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 34 | static unsigned int ftrace_nop_replace(void) | ||
| 35 | { | ||
| 36 | return PPC_INST_NOP; | ||
| 37 | } | ||
| 38 | |||
| 39 | static unsigned int | 28 | static unsigned int |
| 40 | ftrace_call_replace(unsigned long ip, unsigned long addr, int link) | 29 | ftrace_call_replace(unsigned long ip, unsigned long addr, int link) |
| 41 | { | 30 | { |
| 42 | unsigned int op; | 31 | unsigned int op; |
| 43 | 32 | ||
| 44 | addr = GET_ADDR(addr); | 33 | addr = ppc_function_entry((void *)addr); |
| 45 | 34 | ||
| 46 | /* if (link) set op to 'bl' else 'b' */ | 35 | /* if (link) set op to 'bl' else 'b' */ |
| 47 | op = create_branch((unsigned int *)ip, addr, link ? 1 : 0); | 36 | op = create_branch((unsigned int *)ip, addr, link ? 1 : 0); |
| @@ -49,14 +38,6 @@ ftrace_call_replace(unsigned long ip, unsigned long addr, int link) | |||
| 49 | return op; | 38 | return op; |
| 50 | } | 39 | } |
| 51 | 40 | ||
| 52 | #ifdef CONFIG_PPC64 | ||
| 53 | # define _ASM_ALIGN " .align 3 " | ||
| 54 | # define _ASM_PTR " .llong " | ||
| 55 | #else | ||
| 56 | # define _ASM_ALIGN " .align 2 " | ||
| 57 | # define _ASM_PTR " .long " | ||
| 58 | #endif | ||
| 59 | |||
| 60 | static int | 41 | static int |
| 61 | ftrace_modify_code(unsigned long ip, unsigned int old, unsigned int new) | 42 | ftrace_modify_code(unsigned long ip, unsigned int old, unsigned int new) |
| 62 | { | 43 | { |
| @@ -197,7 +178,7 @@ __ftrace_make_nop(struct module *mod, | |||
| 197 | ptr = ((unsigned long)jmp[0] << 32) + jmp[1]; | 178 | ptr = ((unsigned long)jmp[0] << 32) + jmp[1]; |
| 198 | 179 | ||
| 199 | /* This should match what was called */ | 180 | /* This should match what was called */ |
| 200 | if (ptr != GET_ADDR(addr)) { | 181 | if (ptr != ppc_function_entry((void *)addr)) { |
| 201 | printk(KERN_ERR "addr does not match %lx\n", ptr); | 182 | printk(KERN_ERR "addr does not match %lx\n", ptr); |
| 202 | return -EINVAL; | 183 | return -EINVAL; |
| 203 | } | 184 | } |
| @@ -328,7 +309,7 @@ int ftrace_make_nop(struct module *mod, | |||
| 328 | if (test_24bit_addr(ip, addr)) { | 309 | if (test_24bit_addr(ip, addr)) { |
| 329 | /* within range */ | 310 | /* within range */ |
| 330 | old = ftrace_call_replace(ip, addr, 1); | 311 | old = ftrace_call_replace(ip, addr, 1); |
| 331 | new = ftrace_nop_replace(); | 312 | new = PPC_INST_NOP; |
| 332 | return ftrace_modify_code(ip, old, new); | 313 | return ftrace_modify_code(ip, old, new); |
| 333 | } | 314 | } |
| 334 | 315 | ||
| @@ -466,7 +447,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) | |||
| 466 | */ | 447 | */ |
| 467 | if (test_24bit_addr(ip, addr)) { | 448 | if (test_24bit_addr(ip, addr)) { |
| 468 | /* within range */ | 449 | /* within range */ |
| 469 | old = ftrace_nop_replace(); | 450 | old = PPC_INST_NOP; |
| 470 | new = ftrace_call_replace(ip, addr, 1); | 451 | new = ftrace_call_replace(ip, addr, 1); |
| 471 | return ftrace_modify_code(ip, old, new); | 452 | return ftrace_modify_code(ip, old, new); |
| 472 | } | 453 | } |
| @@ -570,7 +551,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) | |||
| 570 | return_hooker = (unsigned long)&mod_return_to_handler; | 551 | return_hooker = (unsigned long)&mod_return_to_handler; |
| 571 | #endif | 552 | #endif |
| 572 | 553 | ||
| 573 | return_hooker = GET_ADDR(return_hooker); | 554 | return_hooker = ppc_function_entry((void *)return_hooker); |
| 574 | 555 | ||
| 575 | /* | 556 | /* |
| 576 | * Protect against fault, even if it shouldn't | 557 | * Protect against fault, even if it shouldn't |
| @@ -605,7 +586,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr) | |||
| 605 | return; | 586 | return; |
| 606 | } | 587 | } |
| 607 | 588 | ||
| 608 | if (ftrace_push_return_trace(old, self_addr, &trace.depth) == -EBUSY) { | 589 | if (ftrace_push_return_trace(old, self_addr, &trace.depth, 0) == -EBUSY) { |
| 609 | *parent = old; | 590 | *parent = old; |
| 610 | return; | 591 | return; |
| 611 | } | 592 | } |
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index c01467f952d3..48469463f89e 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
| @@ -733,9 +733,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) | |||
| 733 | AltiVecUnavailable: | 733 | AltiVecUnavailable: |
| 734 | EXCEPTION_PROLOG | 734 | EXCEPTION_PROLOG |
| 735 | #ifdef CONFIG_ALTIVEC | 735 | #ifdef CONFIG_ALTIVEC |
| 736 | bne load_up_altivec /* if from user, just load it up */ | 736 | beq 1f |
| 737 | bl load_up_altivec /* if from user, just load it up */ | ||
| 738 | b fast_exception_return | ||
| 737 | #endif /* CONFIG_ALTIVEC */ | 739 | #endif /* CONFIG_ALTIVEC */ |
| 738 | addi r3,r1,STACK_FRAME_OVERHEAD | 740 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 739 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) | 741 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) |
| 740 | 742 | ||
| 741 | PerformanceMonitor: | 743 | PerformanceMonitor: |
| @@ -743,101 +745,6 @@ PerformanceMonitor: | |||
| 743 | addi r3,r1,STACK_FRAME_OVERHEAD | 745 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 744 | EXC_XFER_STD(0xf00, performance_monitor_exception) | 746 | EXC_XFER_STD(0xf00, performance_monitor_exception) |
| 745 | 747 | ||
| 746 | #ifdef CONFIG_ALTIVEC | ||
| 747 | /* Note that the AltiVec support is closely modeled after the FP | ||
| 748 | * support. Changes to one are likely to be applicable to the | ||
| 749 | * other! */ | ||
| 750 | load_up_altivec: | ||
| 751 | /* | ||
| 752 | * Disable AltiVec for the task which had AltiVec previously, | ||
| 753 | * and save its AltiVec registers in its thread_struct. | ||
| 754 | * Enables AltiVec for use in the kernel on return. | ||
| 755 | * On SMP we know the AltiVec units are free, since we give it up every | ||
| 756 | * switch. -- Kumar | ||
| 757 | */ | ||
| 758 | mfmsr r5 | ||
| 759 | oris r5,r5,MSR_VEC@h | ||
| 760 | MTMSRD(r5) /* enable use of AltiVec now */ | ||
| 761 | isync | ||
| 762 | /* | ||
| 763 | * For SMP, we don't do lazy AltiVec switching because it just gets too | ||
| 764 | * horrendously complex, especially when a task switches from one CPU | ||
| 765 | * to another. Instead we call giveup_altivec in switch_to. | ||
| 766 | */ | ||
| 767 | #ifndef CONFIG_SMP | ||
| 768 | tophys(r6,0) | ||
| 769 | addis r3,r6,last_task_used_altivec@ha | ||
| 770 | lwz r4,last_task_used_altivec@l(r3) | ||
| 771 | cmpwi 0,r4,0 | ||
| 772 | beq 1f | ||
| 773 | add r4,r4,r6 | ||
| 774 | addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ | ||
| 775 | SAVE_32VRS(0,r10,r4) | ||
| 776 | mfvscr vr0 | ||
| 777 | li r10,THREAD_VSCR | ||
| 778 | stvx vr0,r10,r4 | ||
| 779 | lwz r5,PT_REGS(r4) | ||
| 780 | add r5,r5,r6 | ||
| 781 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 782 | lis r10,MSR_VEC@h | ||
| 783 | andc r4,r4,r10 /* disable altivec for previous task */ | ||
| 784 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 785 | 1: | ||
| 786 | #endif /* CONFIG_SMP */ | ||
| 787 | /* enable use of AltiVec after return */ | ||
| 788 | oris r9,r9,MSR_VEC@h | ||
| 789 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | ||
| 790 | li r4,1 | ||
| 791 | li r10,THREAD_VSCR | ||
| 792 | stw r4,THREAD_USED_VR(r5) | ||
| 793 | lvx vr0,r10,r5 | ||
| 794 | mtvscr vr0 | ||
| 795 | REST_32VRS(0,r10,r5) | ||
| 796 | #ifndef CONFIG_SMP | ||
| 797 | subi r4,r5,THREAD | ||
| 798 | sub r4,r4,r6 | ||
| 799 | stw r4,last_task_used_altivec@l(r3) | ||
| 800 | #endif /* CONFIG_SMP */ | ||
| 801 | /* restore registers and return */ | ||
| 802 | /* we haven't used ctr or xer or lr */ | ||
| 803 | b fast_exception_return | ||
| 804 | |||
| 805 | /* | ||
| 806 | * giveup_altivec(tsk) | ||
| 807 | * Disable AltiVec for the task given as the argument, | ||
| 808 | * and save the AltiVec registers in its thread_struct. | ||
| 809 | * Enables AltiVec for use in the kernel on return. | ||
| 810 | */ | ||
| 811 | |||
| 812 | .globl giveup_altivec | ||
| 813 | giveup_altivec: | ||
| 814 | mfmsr r5 | ||
| 815 | oris r5,r5,MSR_VEC@h | ||
| 816 | SYNC | ||
| 817 | MTMSRD(r5) /* enable use of AltiVec now */ | ||
| 818 | isync | ||
| 819 | cmpwi 0,r3,0 | ||
| 820 | beqlr- /* if no previous owner, done */ | ||
| 821 | addi r3,r3,THREAD /* want THREAD of task */ | ||
| 822 | lwz r5,PT_REGS(r3) | ||
| 823 | cmpwi 0,r5,0 | ||
| 824 | SAVE_32VRS(0, r4, r3) | ||
| 825 | mfvscr vr0 | ||
| 826 | li r4,THREAD_VSCR | ||
| 827 | stvx vr0,r4,r3 | ||
| 828 | beq 1f | ||
| 829 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 830 | lis r3,MSR_VEC@h | ||
| 831 | andc r4,r4,r3 /* disable AltiVec for previous task */ | ||
| 832 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 833 | 1: | ||
| 834 | #ifndef CONFIG_SMP | ||
| 835 | li r5,0 | ||
| 836 | lis r4,last_task_used_altivec@ha | ||
| 837 | stw r5,last_task_used_altivec@l(r4) | ||
| 838 | #endif /* CONFIG_SMP */ | ||
| 839 | blr | ||
| 840 | #endif /* CONFIG_ALTIVEC */ | ||
| 841 | 748 | ||
| 842 | /* | 749 | /* |
| 843 | * This code is jumped to from the startup code to copy | 750 | * This code is jumped to from the startup code to copy |
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 50ef505b8fb6..012505ebd9f9 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S | |||
| @@ -12,8 +12,9 @@ | |||
| 12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | 12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and |
| 13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | 13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com |
| 14 | * | 14 | * |
| 15 | * This file contains the low-level support and setup for the | 15 | * This file contains the entry point for the 64-bit kernel along |
| 16 | * PowerPC-64 platform, including trap and interrupt dispatch. | 16 | * with some early initialization code common to all 64-bit powerpc |
| 17 | * variants. | ||
| 17 | * | 18 | * |
| 18 | * This program is free software; you can redistribute it and/or | 19 | * This program is free software; you can redistribute it and/or |
| 19 | * modify it under the terms of the GNU General Public License | 20 | * modify it under the terms of the GNU General Public License |
| @@ -38,36 +39,25 @@ | |||
| 38 | #include <asm/exception.h> | 39 | #include <asm/exception.h> |
| 39 | #include <asm/irqflags.h> | 40 | #include <asm/irqflags.h> |
| 40 | 41 | ||
| 41 | /* | 42 | /* The physical memory is layed out such that the secondary processor |
| 42 | * We layout physical memory as follows: | 43 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
| 43 | * 0x0000 - 0x00ff : Secondary processor spin code | 44 | * using the layout described in exceptions-64s.S |
| 44 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | ||
| 45 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | ||
| 46 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | ||
| 47 | * 0x7000 - 0x7fff : FWNMI data area | ||
| 48 | * 0x8000 - : Early init and support code | ||
| 49 | */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * SPRG Usage | ||
| 53 | * | ||
| 54 | * Register Definition | ||
| 55 | * | ||
| 56 | * SPRG0 reserved for hypervisor | ||
| 57 | * SPRG1 temp - used to save gpr | ||
| 58 | * SPRG2 temp - used to save gpr | ||
| 59 | * SPRG3 virt addr of paca | ||
| 60 | */ | 45 | */ |
| 61 | 46 | ||
| 62 | /* | 47 | /* |
| 63 | * Entering into this code we make the following assumptions: | 48 | * Entering into this code we make the following assumptions: |
| 64 | * For pSeries: | 49 | * |
| 50 | * For pSeries or server processors: | ||
| 65 | * 1. The MMU is off & open firmware is running in real mode. | 51 | * 1. The MMU is off & open firmware is running in real mode. |
| 66 | * 2. The kernel is entered at __start | 52 | * 2. The kernel is entered at __start |
| 67 | * | 53 | * |
| 68 | * For iSeries: | 54 | * For iSeries: |
| 69 | * 1. The MMU is on (as it always is for iSeries) | 55 | * 1. The MMU is on (as it always is for iSeries) |
| 70 | * 2. The kernel is entered at system_reset_iSeries | 56 | * 2. The kernel is entered at system_reset_iSeries |
| 57 | * | ||
| 58 | * For Book3E processors: | ||
| 59 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | ||
| 60 | * 2. The kernel is entered at __start | ||
| 71 | */ | 61 | */ |
| 72 | 62 | ||
| 73 | .text | 63 | .text |
| @@ -166,1065 +156,14 @@ exception_marker: | |||
| 166 | .text | 156 | .text |
| 167 | 157 | ||
| 168 | /* | 158 | /* |
| 169 | * This is the start of the interrupt handlers for pSeries | 159 | * On server, we include the exception vectors code here as it |
| 170 | * This code runs with relocation off. | 160 | * relies on absolute addressing which is only possible within |
| 171 | * Code from here to __end_interrupts gets copied down to real | 161 | * this compilation unit |
| 172 | * address 0x100 when we are running a relocatable kernel. | ||
| 173 | * Therefore any relative branches in this section must only | ||
| 174 | * branch to labels in this section. | ||
| 175 | */ | ||
| 176 | . = 0x100 | ||
| 177 | .globl __start_interrupts | ||
| 178 | __start_interrupts: | ||
| 179 | |||
| 180 | STD_EXCEPTION_PSERIES(0x100, system_reset) | ||
| 181 | |||
| 182 | . = 0x200 | ||
| 183 | _machine_check_pSeries: | ||
| 184 | HMT_MEDIUM | ||
| 185 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 186 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | ||
| 187 | |||
| 188 | . = 0x300 | ||
| 189 | .globl data_access_pSeries | ||
| 190 | data_access_pSeries: | ||
| 191 | HMT_MEDIUM | ||
| 192 | mtspr SPRN_SPRG1,r13 | ||
| 193 | BEGIN_FTR_SECTION | ||
| 194 | mtspr SPRN_SPRG2,r12 | ||
| 195 | mfspr r13,SPRN_DAR | ||
| 196 | mfspr r12,SPRN_DSISR | ||
| 197 | srdi r13,r13,60 | ||
| 198 | rlwimi r13,r12,16,0x20 | ||
| 199 | mfcr r12 | ||
| 200 | cmpwi r13,0x2c | ||
| 201 | beq do_stab_bolted_pSeries | ||
| 202 | mtcrf 0x80,r12 | ||
| 203 | mfspr r12,SPRN_SPRG2 | ||
| 204 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | ||
| 205 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | ||
| 206 | |||
| 207 | . = 0x380 | ||
| 208 | .globl data_access_slb_pSeries | ||
| 209 | data_access_slb_pSeries: | ||
| 210 | HMT_MEDIUM | ||
| 211 | mtspr SPRN_SPRG1,r13 | ||
| 212 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ | ||
| 213 | std r3,PACA_EXSLB+EX_R3(r13) | ||
| 214 | mfspr r3,SPRN_DAR | ||
| 215 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | ||
| 216 | mfcr r9 | ||
| 217 | #ifdef __DISABLED__ | ||
| 218 | /* Keep that around for when we re-implement dynamic VSIDs */ | ||
| 219 | cmpdi r3,0 | ||
| 220 | bge slb_miss_user_pseries | ||
| 221 | #endif /* __DISABLED__ */ | ||
| 222 | std r10,PACA_EXSLB+EX_R10(r13) | ||
| 223 | std r11,PACA_EXSLB+EX_R11(r13) | ||
| 224 | std r12,PACA_EXSLB+EX_R12(r13) | ||
| 225 | mfspr r10,SPRN_SPRG1 | ||
| 226 | std r10,PACA_EXSLB+EX_R13(r13) | ||
| 227 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | ||
| 228 | #ifndef CONFIG_RELOCATABLE | ||
| 229 | b .slb_miss_realmode | ||
| 230 | #else | ||
| 231 | /* | ||
| 232 | * We can't just use a direct branch to .slb_miss_realmode | ||
| 233 | * because the distance from here to there depends on where | ||
| 234 | * the kernel ends up being put. | ||
| 235 | */ | ||
| 236 | mfctr r11 | ||
| 237 | ld r10,PACAKBASE(r13) | ||
| 238 | LOAD_HANDLER(r10, .slb_miss_realmode) | ||
| 239 | mtctr r10 | ||
| 240 | bctr | ||
| 241 | #endif | ||
| 242 | |||
| 243 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | ||
| 244 | |||
| 245 | . = 0x480 | ||
| 246 | .globl instruction_access_slb_pSeries | ||
| 247 | instruction_access_slb_pSeries: | ||
| 248 | HMT_MEDIUM | ||
| 249 | mtspr SPRN_SPRG1,r13 | ||
| 250 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ | ||
| 251 | std r3,PACA_EXSLB+EX_R3(r13) | ||
| 252 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | ||
| 253 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | ||
| 254 | mfcr r9 | ||
| 255 | #ifdef __DISABLED__ | ||
| 256 | /* Keep that around for when we re-implement dynamic VSIDs */ | ||
| 257 | cmpdi r3,0 | ||
| 258 | bge slb_miss_user_pseries | ||
| 259 | #endif /* __DISABLED__ */ | ||
| 260 | std r10,PACA_EXSLB+EX_R10(r13) | ||
| 261 | std r11,PACA_EXSLB+EX_R11(r13) | ||
| 262 | std r12,PACA_EXSLB+EX_R12(r13) | ||
| 263 | mfspr r10,SPRN_SPRG1 | ||
| 264 | std r10,PACA_EXSLB+EX_R13(r13) | ||
| 265 | mfspr r12,SPRN_SRR1 /* and SRR1 */ | ||
| 266 | #ifndef CONFIG_RELOCATABLE | ||
| 267 | b .slb_miss_realmode | ||
| 268 | #else | ||
| 269 | mfctr r11 | ||
| 270 | ld r10,PACAKBASE(r13) | ||
| 271 | LOAD_HANDLER(r10, .slb_miss_realmode) | ||
| 272 | mtctr r10 | ||
| 273 | bctr | ||
| 274 | #endif | ||
| 275 | |||
| 276 | MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) | ||
| 277 | STD_EXCEPTION_PSERIES(0x600, alignment) | ||
| 278 | STD_EXCEPTION_PSERIES(0x700, program_check) | ||
| 279 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | ||
| 280 | MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) | ||
| 281 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) | ||
| 282 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | ||
| 283 | |||
| 284 | . = 0xc00 | ||
| 285 | .globl system_call_pSeries | ||
| 286 | system_call_pSeries: | ||
| 287 | HMT_MEDIUM | ||
| 288 | BEGIN_FTR_SECTION | ||
| 289 | cmpdi r0,0x1ebe | ||
| 290 | beq- 1f | ||
| 291 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) | ||
| 292 | mr r9,r13 | ||
| 293 | mfspr r13,SPRN_SPRG3 | ||
| 294 | mfspr r11,SPRN_SRR0 | ||
| 295 | ld r12,PACAKBASE(r13) | ||
| 296 | ld r10,PACAKMSR(r13) | ||
| 297 | LOAD_HANDLER(r12, system_call_entry) | ||
| 298 | mtspr SPRN_SRR0,r12 | ||
| 299 | mfspr r12,SPRN_SRR1 | ||
| 300 | mtspr SPRN_SRR1,r10 | ||
| 301 | rfid | ||
| 302 | b . /* prevent speculative execution */ | ||
| 303 | |||
| 304 | /* Fast LE/BE switch system call */ | ||
| 305 | 1: mfspr r12,SPRN_SRR1 | ||
| 306 | xori r12,r12,MSR_LE | ||
| 307 | mtspr SPRN_SRR1,r12 | ||
| 308 | rfid /* return to userspace */ | ||
| 309 | b . | ||
| 310 | |||
| 311 | STD_EXCEPTION_PSERIES(0xd00, single_step) | ||
| 312 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | ||
| 313 | |||
| 314 | /* We need to deal with the Altivec unavailable exception | ||
| 315 | * here which is at 0xf20, thus in the middle of the | ||
| 316 | * prolog code of the PerformanceMonitor one. A little | ||
| 317 | * trickery is thus necessary | ||
| 318 | */ | ||
| 319 | . = 0xf00 | ||
| 320 | b performance_monitor_pSeries | ||
| 321 | |||
| 322 | . = 0xf20 | ||
| 323 | b altivec_unavailable_pSeries | ||
| 324 | |||
| 325 | . = 0xf40 | ||
| 326 | b vsx_unavailable_pSeries | ||
| 327 | |||
| 328 | #ifdef CONFIG_CBE_RAS | ||
| 329 | HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) | ||
| 330 | #endif /* CONFIG_CBE_RAS */ | ||
| 331 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | ||
| 332 | #ifdef CONFIG_CBE_RAS | ||
| 333 | HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) | ||
| 334 | #endif /* CONFIG_CBE_RAS */ | ||
| 335 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | ||
| 336 | #ifdef CONFIG_CBE_RAS | ||
| 337 | HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) | ||
| 338 | #endif /* CONFIG_CBE_RAS */ | ||
| 339 | |||
| 340 | . = 0x3000 | ||
| 341 | |||
| 342 | /*** pSeries interrupt support ***/ | ||
| 343 | |||
| 344 | /* moved from 0xf00 */ | ||
| 345 | STD_EXCEPTION_PSERIES(., performance_monitor) | ||
| 346 | STD_EXCEPTION_PSERIES(., altivec_unavailable) | ||
| 347 | STD_EXCEPTION_PSERIES(., vsx_unavailable) | ||
| 348 | |||
| 349 | /* | ||
| 350 | * An interrupt came in while soft-disabled; clear EE in SRR1, | ||
| 351 | * clear paca->hard_enabled and return. | ||
| 352 | */ | ||
| 353 | masked_interrupt: | ||
| 354 | stb r10,PACAHARDIRQEN(r13) | ||
| 355 | mtcrf 0x80,r9 | ||
| 356 | ld r9,PACA_EXGEN+EX_R9(r13) | ||
| 357 | mfspr r10,SPRN_SRR1 | ||
| 358 | rldicl r10,r10,48,1 /* clear MSR_EE */ | ||
| 359 | rotldi r10,r10,16 | ||
| 360 | mtspr SPRN_SRR1,r10 | ||
| 361 | ld r10,PACA_EXGEN+EX_R10(r13) | ||
| 362 | mfspr r13,SPRN_SPRG1 | ||
| 363 | rfid | ||
| 364 | b . | ||
| 365 | |||
| 366 | .align 7 | ||
| 367 | do_stab_bolted_pSeries: | ||
| 368 | mtcrf 0x80,r12 | ||
| 369 | mfspr r12,SPRN_SPRG2 | ||
| 370 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) | ||
| 371 | |||
| 372 | #ifdef CONFIG_PPC_PSERIES | ||
| 373 | /* | ||
| 374 | * Vectors for the FWNMI option. Share common code. | ||
| 375 | */ | ||
| 376 | .globl system_reset_fwnmi | ||
| 377 | .align 7 | ||
| 378 | system_reset_fwnmi: | ||
| 379 | HMT_MEDIUM | ||
| 380 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 381 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) | ||
| 382 | |||
| 383 | .globl machine_check_fwnmi | ||
| 384 | .align 7 | ||
| 385 | machine_check_fwnmi: | ||
| 386 | HMT_MEDIUM | ||
| 387 | mtspr SPRN_SPRG1,r13 /* save r13 */ | ||
| 388 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | ||
| 389 | |||
| 390 | #endif /* CONFIG_PPC_PSERIES */ | ||
| 391 | |||
| 392 | #ifdef __DISABLED__ | ||
| 393 | /* | ||
| 394 | * This is used for when the SLB miss handler has to go virtual, | ||
| 395 | * which doesn't happen for now anymore but will once we re-implement | ||
| 396 | * dynamic VSIDs for shared page tables | ||
| 397 | */ | ||
| 398 | slb_miss_user_pseries: | ||
| 399 | std r10,PACA_EXGEN+EX_R10(r13) | ||
| 400 | std r11,PACA_EXGEN+EX_R11(r13) | ||
| 401 | std r12,PACA_EXGEN+EX_R12(r13) | ||
| 402 | mfspr r10,SPRG1 | ||
| 403 | ld r11,PACA_EXSLB+EX_R9(r13) | ||
| 404 | ld r12,PACA_EXSLB+EX_R3(r13) | ||
| 405 | std r10,PACA_EXGEN+EX_R13(r13) | ||
| 406 | std r11,PACA_EXGEN+EX_R9(r13) | ||
| 407 | std r12,PACA_EXGEN+EX_R3(r13) | ||
| 408 | clrrdi r12,r13,32 | ||
| 409 | mfmsr r10 | ||
| 410 | mfspr r11,SRR0 /* save SRR0 */ | ||
| 411 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | ||
| 412 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | ||
| 413 | mtspr SRR0,r12 | ||
| 414 | mfspr r12,SRR1 /* and SRR1 */ | ||
| 415 | mtspr SRR1,r10 | ||
| 416 | rfid | ||
| 417 | b . /* prevent spec. execution */ | ||
| 418 | #endif /* __DISABLED__ */ | ||
| 419 | |||
| 420 | .align 7 | ||
| 421 | .globl __end_interrupts | ||
| 422 | __end_interrupts: | ||
| 423 | |||
| 424 | /* | ||
| 425 | * Code from here down to __end_handlers is invoked from the | ||
| 426 | * exception prologs above. Because the prologs assemble the | ||
| 427 | * addresses of these handlers using the LOAD_HANDLER macro, | ||
| 428 | * which uses an addi instruction, these handlers must be in | ||
| 429 | * the first 32k of the kernel image. | ||
| 430 | */ | ||
| 431 | |||
| 432 | /*** Common interrupt handlers ***/ | ||
| 433 | |||
| 434 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | ||
| 435 | |||
| 436 | /* | ||
| 437 | * Machine check is different because we use a different | ||
| 438 | * save area: PACA_EXMC instead of PACA_EXGEN. | ||
| 439 | */ | ||
| 440 | .align 7 | ||
| 441 | .globl machine_check_common | ||
| 442 | machine_check_common: | ||
| 443 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | ||
| 444 | FINISH_NAP | ||
| 445 | DISABLE_INTS | ||
| 446 | bl .save_nvgprs | ||
| 447 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 448 | bl .machine_check_exception | ||
| 449 | b .ret_from_except | ||
| 450 | |||
| 451 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | ||
| 452 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | ||
| 453 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | ||
| 454 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | ||
| 455 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | ||
| 456 | STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) | ||
| 457 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | ||
| 458 | #ifdef CONFIG_ALTIVEC | ||
| 459 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | ||
| 460 | #else | ||
| 461 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | ||
| 462 | #endif | ||
| 463 | #ifdef CONFIG_CBE_RAS | ||
| 464 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | ||
| 465 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | ||
| 466 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | ||
| 467 | #endif /* CONFIG_CBE_RAS */ | ||
| 468 | |||
| 469 | .align 7 | ||
| 470 | system_call_entry: | ||
| 471 | b system_call_common | ||
| 472 | |||
| 473 | /* | ||
| 474 | * Here we have detected that the kernel stack pointer is bad. | ||
| 475 | * R9 contains the saved CR, r13 points to the paca, | ||
| 476 | * r10 contains the (bad) kernel stack pointer, | ||
| 477 | * r11 and r12 contain the saved SRR0 and SRR1. | ||
| 478 | * We switch to using an emergency stack, save the registers there, | ||
| 479 | * and call kernel_bad_stack(), which panics. | ||
| 480 | */ | ||
| 481 | bad_stack: | ||
| 482 | ld r1,PACAEMERGSP(r13) | ||
| 483 | subi r1,r1,64+INT_FRAME_SIZE | ||
| 484 | std r9,_CCR(r1) | ||
| 485 | std r10,GPR1(r1) | ||
| 486 | std r11,_NIP(r1) | ||
| 487 | std r12,_MSR(r1) | ||
| 488 | mfspr r11,SPRN_DAR | ||
| 489 | mfspr r12,SPRN_DSISR | ||
| 490 | std r11,_DAR(r1) | ||
| 491 | std r12,_DSISR(r1) | ||
| 492 | mflr r10 | ||
| 493 | mfctr r11 | ||
| 494 | mfxer r12 | ||
| 495 | std r10,_LINK(r1) | ||
| 496 | std r11,_CTR(r1) | ||
| 497 | std r12,_XER(r1) | ||
| 498 | SAVE_GPR(0,r1) | ||
| 499 | SAVE_GPR(2,r1) | ||
| 500 | SAVE_4GPRS(3,r1) | ||
| 501 | SAVE_2GPRS(7,r1) | ||
| 502 | SAVE_10GPRS(12,r1) | ||
| 503 | SAVE_10GPRS(22,r1) | ||
| 504 | lhz r12,PACA_TRAP_SAVE(r13) | ||
| 505 | std r12,_TRAP(r1) | ||
| 506 | addi r11,r1,INT_FRAME_SIZE | ||
| 507 | std r11,0(r1) | ||
| 508 | li r12,0 | ||
| 509 | std r12,0(r11) | ||
| 510 | ld r2,PACATOC(r13) | ||
| 511 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 512 | bl .kernel_bad_stack | ||
| 513 | b 1b | ||
| 514 | |||
| 515 | /* | ||
| 516 | * Here r13 points to the paca, r9 contains the saved CR, | ||
| 517 | * SRR0 and SRR1 are saved in r11 and r12, | ||
| 518 | * r9 - r13 are saved in paca->exgen. | ||
| 519 | */ | ||
| 520 | .align 7 | ||
| 521 | .globl data_access_common | ||
| 522 | data_access_common: | ||
| 523 | mfspr r10,SPRN_DAR | ||
| 524 | std r10,PACA_EXGEN+EX_DAR(r13) | ||
| 525 | mfspr r10,SPRN_DSISR | ||
| 526 | stw r10,PACA_EXGEN+EX_DSISR(r13) | ||
| 527 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | ||
| 528 | ld r3,PACA_EXGEN+EX_DAR(r13) | ||
| 529 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | ||
| 530 | li r5,0x300 | ||
| 531 | b .do_hash_page /* Try to handle as hpte fault */ | ||
| 532 | |||
| 533 | .align 7 | ||
| 534 | .globl instruction_access_common | ||
| 535 | instruction_access_common: | ||
| 536 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | ||
| 537 | ld r3,_NIP(r1) | ||
| 538 | andis. r4,r12,0x5820 | ||
| 539 | li r5,0x400 | ||
| 540 | b .do_hash_page /* Try to handle as hpte fault */ | ||
| 541 | |||
| 542 | /* | ||
| 543 | * Here is the common SLB miss user that is used when going to virtual | ||
| 544 | * mode for SLB misses, that is currently not used | ||
| 545 | */ | ||
| 546 | #ifdef __DISABLED__ | ||
| 547 | .align 7 | ||
| 548 | .globl slb_miss_user_common | ||
| 549 | slb_miss_user_common: | ||
| 550 | mflr r10 | ||
| 551 | std r3,PACA_EXGEN+EX_DAR(r13) | ||
| 552 | stw r9,PACA_EXGEN+EX_CCR(r13) | ||
| 553 | std r10,PACA_EXGEN+EX_LR(r13) | ||
| 554 | std r11,PACA_EXGEN+EX_SRR0(r13) | ||
| 555 | bl .slb_allocate_user | ||
| 556 | |||
| 557 | ld r10,PACA_EXGEN+EX_LR(r13) | ||
| 558 | ld r3,PACA_EXGEN+EX_R3(r13) | ||
| 559 | lwz r9,PACA_EXGEN+EX_CCR(r13) | ||
| 560 | ld r11,PACA_EXGEN+EX_SRR0(r13) | ||
| 561 | mtlr r10 | ||
| 562 | beq- slb_miss_fault | ||
| 563 | |||
| 564 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | ||
| 565 | beq- unrecov_user_slb | ||
| 566 | mfmsr r10 | ||
| 567 | |||
| 568 | .machine push | ||
| 569 | .machine "power4" | ||
| 570 | mtcrf 0x80,r9 | ||
| 571 | .machine pop | ||
| 572 | |||
| 573 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | ||
| 574 | mtmsrd r10,1 | ||
| 575 | |||
| 576 | mtspr SRR0,r11 | ||
| 577 | mtspr SRR1,r12 | ||
| 578 | |||
| 579 | ld r9,PACA_EXGEN+EX_R9(r13) | ||
| 580 | ld r10,PACA_EXGEN+EX_R10(r13) | ||
| 581 | ld r11,PACA_EXGEN+EX_R11(r13) | ||
| 582 | ld r12,PACA_EXGEN+EX_R12(r13) | ||
| 583 | ld r13,PACA_EXGEN+EX_R13(r13) | ||
| 584 | rfid | ||
| 585 | b . | ||
| 586 | |||
| 587 | slb_miss_fault: | ||
| 588 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | ||
| 589 | ld r4,PACA_EXGEN+EX_DAR(r13) | ||
| 590 | li r5,0 | ||
| 591 | std r4,_DAR(r1) | ||
| 592 | std r5,_DSISR(r1) | ||
| 593 | b handle_page_fault | ||
| 594 | |||
| 595 | unrecov_user_slb: | ||
| 596 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | ||
| 597 | DISABLE_INTS | ||
| 598 | bl .save_nvgprs | ||
| 599 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 600 | bl .unrecoverable_exception | ||
| 601 | b 1b | ||
| 602 | |||
| 603 | #endif /* __DISABLED__ */ | ||
| 604 | |||
| 605 | |||
| 606 | /* | ||
| 607 | * r13 points to the PACA, r9 contains the saved CR, | ||
| 608 | * r12 contain the saved SRR1, SRR0 is still ready for return | ||
| 609 | * r3 has the faulting address | ||
| 610 | * r9 - r13 are saved in paca->exslb. | ||
| 611 | * r3 is saved in paca->slb_r3 | ||
| 612 | * We assume we aren't going to take any exceptions during this procedure. | ||
| 613 | */ | ||
| 614 | _GLOBAL(slb_miss_realmode) | ||
| 615 | mflr r10 | ||
| 616 | #ifdef CONFIG_RELOCATABLE | ||
| 617 | mtctr r11 | ||
| 618 | #endif | ||
| 619 | |||
| 620 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | ||
| 621 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | ||
| 622 | |||
| 623 | bl .slb_allocate_realmode | ||
| 624 | |||
| 625 | /* All done -- return from exception. */ | ||
| 626 | |||
| 627 | ld r10,PACA_EXSLB+EX_LR(r13) | ||
| 628 | ld r3,PACA_EXSLB+EX_R3(r13) | ||
| 629 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | ||
| 630 | #ifdef CONFIG_PPC_ISERIES | ||
| 631 | BEGIN_FW_FTR_SECTION | ||
| 632 | ld r11,PACALPPACAPTR(r13) | ||
| 633 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | ||
| 634 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 635 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 636 | |||
| 637 | mtlr r10 | ||
| 638 | |||
| 639 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | ||
| 640 | beq- 2f | ||
| 641 | |||
| 642 | .machine push | ||
| 643 | .machine "power4" | ||
| 644 | mtcrf 0x80,r9 | ||
| 645 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | ||
| 646 | .machine pop | ||
| 647 | |||
| 648 | #ifdef CONFIG_PPC_ISERIES | ||
| 649 | BEGIN_FW_FTR_SECTION | ||
| 650 | mtspr SPRN_SRR0,r11 | ||
| 651 | mtspr SPRN_SRR1,r12 | ||
| 652 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 653 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 654 | ld r9,PACA_EXSLB+EX_R9(r13) | ||
| 655 | ld r10,PACA_EXSLB+EX_R10(r13) | ||
| 656 | ld r11,PACA_EXSLB+EX_R11(r13) | ||
| 657 | ld r12,PACA_EXSLB+EX_R12(r13) | ||
| 658 | ld r13,PACA_EXSLB+EX_R13(r13) | ||
| 659 | rfid | ||
| 660 | b . /* prevent speculative execution */ | ||
| 661 | |||
| 662 | 2: | ||
| 663 | #ifdef CONFIG_PPC_ISERIES | ||
| 664 | BEGIN_FW_FTR_SECTION | ||
| 665 | b unrecov_slb | ||
| 666 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 667 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 668 | mfspr r11,SPRN_SRR0 | ||
| 669 | ld r10,PACAKBASE(r13) | ||
| 670 | LOAD_HANDLER(r10,unrecov_slb) | ||
| 671 | mtspr SPRN_SRR0,r10 | ||
| 672 | ld r10,PACAKMSR(r13) | ||
| 673 | mtspr SPRN_SRR1,r10 | ||
| 674 | rfid | ||
| 675 | b . | ||
| 676 | |||
| 677 | unrecov_slb: | ||
| 678 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | ||
| 679 | DISABLE_INTS | ||
| 680 | bl .save_nvgprs | ||
| 681 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 682 | bl .unrecoverable_exception | ||
| 683 | b 1b | ||
| 684 | |||
| 685 | .align 7 | ||
| 686 | .globl hardware_interrupt_common | ||
| 687 | .globl hardware_interrupt_entry | ||
| 688 | hardware_interrupt_common: | ||
| 689 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | ||
| 690 | FINISH_NAP | ||
| 691 | hardware_interrupt_entry: | ||
| 692 | DISABLE_INTS | ||
| 693 | BEGIN_FTR_SECTION | ||
| 694 | bl .ppc64_runlatch_on | ||
| 695 | END_FTR_SECTION_IFSET(CPU_FTR_CTRL) | ||
| 696 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 697 | bl .do_IRQ | ||
| 698 | b .ret_from_except_lite | ||
| 699 | |||
| 700 | #ifdef CONFIG_PPC_970_NAP | ||
| 701 | power4_fixup_nap: | ||
| 702 | andc r9,r9,r10 | ||
| 703 | std r9,TI_LOCAL_FLAGS(r11) | ||
| 704 | ld r10,_LINK(r1) /* make idle task do the */ | ||
| 705 | std r10,_NIP(r1) /* equivalent of a blr */ | ||
| 706 | blr | ||
| 707 | #endif | ||
| 708 | |||
| 709 | .align 7 | ||
| 710 | .globl alignment_common | ||
| 711 | alignment_common: | ||
| 712 | mfspr r10,SPRN_DAR | ||
| 713 | std r10,PACA_EXGEN+EX_DAR(r13) | ||
| 714 | mfspr r10,SPRN_DSISR | ||
| 715 | stw r10,PACA_EXGEN+EX_DSISR(r13) | ||
| 716 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | ||
| 717 | ld r3,PACA_EXGEN+EX_DAR(r13) | ||
| 718 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | ||
| 719 | std r3,_DAR(r1) | ||
| 720 | std r4,_DSISR(r1) | ||
| 721 | bl .save_nvgprs | ||
| 722 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 723 | ENABLE_INTS | ||
| 724 | bl .alignment_exception | ||
| 725 | b .ret_from_except | ||
| 726 | |||
| 727 | .align 7 | ||
| 728 | .globl program_check_common | ||
| 729 | program_check_common: | ||
| 730 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | ||
| 731 | bl .save_nvgprs | ||
| 732 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 733 | ENABLE_INTS | ||
| 734 | bl .program_check_exception | ||
| 735 | b .ret_from_except | ||
| 736 | |||
| 737 | .align 7 | ||
| 738 | .globl fp_unavailable_common | ||
| 739 | fp_unavailable_common: | ||
| 740 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | ||
| 741 | bne 1f /* if from user, just load it up */ | ||
| 742 | bl .save_nvgprs | ||
| 743 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 744 | ENABLE_INTS | ||
| 745 | bl .kernel_fp_unavailable_exception | ||
| 746 | BUG_OPCODE | ||
| 747 | 1: bl .load_up_fpu | ||
| 748 | b fast_exception_return | ||
| 749 | |||
| 750 | .align 7 | ||
| 751 | .globl altivec_unavailable_common | ||
| 752 | altivec_unavailable_common: | ||
| 753 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | ||
| 754 | #ifdef CONFIG_ALTIVEC | ||
| 755 | BEGIN_FTR_SECTION | ||
| 756 | beq 1f | ||
| 757 | bl .load_up_altivec | ||
| 758 | b fast_exception_return | ||
| 759 | 1: | ||
| 760 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | ||
| 761 | #endif | ||
| 762 | bl .save_nvgprs | ||
| 763 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 764 | ENABLE_INTS | ||
| 765 | bl .altivec_unavailable_exception | ||
| 766 | b .ret_from_except | ||
| 767 | |||
| 768 | .align 7 | ||
| 769 | .globl vsx_unavailable_common | ||
| 770 | vsx_unavailable_common: | ||
| 771 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | ||
| 772 | #ifdef CONFIG_VSX | ||
| 773 | BEGIN_FTR_SECTION | ||
| 774 | bne .load_up_vsx | ||
| 775 | 1: | ||
| 776 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | ||
| 777 | #endif | ||
| 778 | bl .save_nvgprs | ||
| 779 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 780 | ENABLE_INTS | ||
| 781 | bl .vsx_unavailable_exception | ||
| 782 | b .ret_from_except | ||
| 783 | |||
| 784 | .align 7 | ||
| 785 | .globl __end_handlers | ||
| 786 | __end_handlers: | ||
| 787 | |||
| 788 | /* | ||
| 789 | * Return from an exception with minimal checks. | ||
| 790 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | ||
| 791 | * If interrupts have been enabled, or anything has been | ||
| 792 | * done that might have changed the scheduling status of | ||
| 793 | * any task or sent any task a signal, you should use | ||
| 794 | * ret_from_except or ret_from_except_lite instead of this. | ||
| 795 | */ | 162 | */ |
| 796 | fast_exc_return_irq: /* restores irq state too */ | 163 | #ifdef CONFIG_PPC_BOOK3S |
| 797 | ld r3,SOFTE(r1) | 164 | #include "exceptions-64s.S" |
| 798 | TRACE_AND_RESTORE_IRQ(r3); | ||
| 799 | ld r12,_MSR(r1) | ||
| 800 | rldicl r4,r12,49,63 /* get MSR_EE to LSB */ | ||
| 801 | stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */ | ||
| 802 | b 1f | ||
| 803 | |||
| 804 | .globl fast_exception_return | ||
| 805 | fast_exception_return: | ||
| 806 | ld r12,_MSR(r1) | ||
| 807 | 1: ld r11,_NIP(r1) | ||
| 808 | andi. r3,r12,MSR_RI /* check if RI is set */ | ||
| 809 | beq- unrecov_fer | ||
| 810 | |||
| 811 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | ||
| 812 | andi. r3,r12,MSR_PR | ||
| 813 | beq 2f | ||
| 814 | ACCOUNT_CPU_USER_EXIT(r3, r4) | ||
| 815 | 2: | ||
| 816 | #endif | 165 | #endif |
| 817 | 166 | ||
| 818 | ld r3,_CCR(r1) | ||
| 819 | ld r4,_LINK(r1) | ||
| 820 | ld r5,_CTR(r1) | ||
| 821 | ld r6,_XER(r1) | ||
| 822 | mtcr r3 | ||
| 823 | mtlr r4 | ||
| 824 | mtctr r5 | ||
| 825 | mtxer r6 | ||
| 826 | REST_GPR(0, r1) | ||
| 827 | REST_8GPRS(2, r1) | ||
| 828 | |||
| 829 | mfmsr r10 | ||
| 830 | rldicl r10,r10,48,1 /* clear EE */ | ||
| 831 | rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ | ||
| 832 | mtmsrd r10,1 | ||
| 833 | |||
| 834 | mtspr SPRN_SRR1,r12 | ||
| 835 | mtspr SPRN_SRR0,r11 | ||
| 836 | REST_4GPRS(10, r1) | ||
| 837 | ld r1,GPR1(r1) | ||
| 838 | rfid | ||
| 839 | b . /* prevent speculative execution */ | ||
| 840 | |||
| 841 | unrecov_fer: | ||
| 842 | bl .save_nvgprs | ||
| 843 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 844 | bl .unrecoverable_exception | ||
| 845 | b 1b | ||
| 846 | |||
| 847 | #ifdef CONFIG_ALTIVEC | ||
| 848 | /* | ||
| 849 | * load_up_altivec(unused, unused, tsk) | ||
| 850 | * Disable VMX for the task which had it previously, | ||
| 851 | * and save its vector registers in its thread_struct. | ||
| 852 | * Enables the VMX for use in the kernel on return. | ||
| 853 | * On SMP we know the VMX is free, since we give it up every | ||
| 854 | * switch (ie, no lazy save of the vector registers). | ||
| 855 | * On entry: r13 == 'current' && last_task_used_altivec != 'current' | ||
| 856 | */ | ||
| 857 | _STATIC(load_up_altivec) | ||
| 858 | mfmsr r5 /* grab the current MSR */ | ||
| 859 | oris r5,r5,MSR_VEC@h | ||
| 860 | mtmsrd r5 /* enable use of VMX now */ | ||
| 861 | isync | ||
| 862 | |||
| 863 | /* | ||
| 864 | * For SMP, we don't do lazy VMX switching because it just gets too | ||
| 865 | * horrendously complex, especially when a task switches from one CPU | ||
| 866 | * to another. Instead we call giveup_altvec in switch_to. | ||
| 867 | * VRSAVE isn't dealt with here, that is done in the normal context | ||
| 868 | * switch code. Note that we could rely on vrsave value to eventually | ||
| 869 | * avoid saving all of the VREGs here... | ||
| 870 | */ | ||
| 871 | #ifndef CONFIG_SMP | ||
| 872 | ld r3,last_task_used_altivec@got(r2) | ||
| 873 | ld r4,0(r3) | ||
| 874 | cmpdi 0,r4,0 | ||
| 875 | beq 1f | ||
| 876 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | ||
| 877 | addi r4,r4,THREAD | ||
| 878 | SAVE_32VRS(0,r5,r4) | ||
| 879 | mfvscr vr0 | ||
| 880 | li r10,THREAD_VSCR | ||
| 881 | stvx vr0,r10,r4 | ||
| 882 | /* Disable VMX for last_task_used_altivec */ | ||
| 883 | ld r5,PT_REGS(r4) | ||
| 884 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 885 | lis r6,MSR_VEC@h | ||
| 886 | andc r4,r4,r6 | ||
| 887 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 888 | 1: | ||
| 889 | #endif /* CONFIG_SMP */ | ||
| 890 | /* Hack: if we get an altivec unavailable trap with VRSAVE | ||
| 891 | * set to all zeros, we assume this is a broken application | ||
| 892 | * that fails to set it properly, and thus we switch it to | ||
| 893 | * all 1's | ||
| 894 | */ | ||
| 895 | mfspr r4,SPRN_VRSAVE | ||
| 896 | cmpdi 0,r4,0 | ||
| 897 | bne+ 1f | ||
| 898 | li r4,-1 | ||
| 899 | mtspr SPRN_VRSAVE,r4 | ||
| 900 | 1: | ||
| 901 | /* enable use of VMX after return */ | ||
| 902 | ld r4,PACACURRENT(r13) | ||
| 903 | addi r5,r4,THREAD /* Get THREAD */ | ||
| 904 | oris r12,r12,MSR_VEC@h | ||
| 905 | std r12,_MSR(r1) | ||
| 906 | li r4,1 | ||
| 907 | li r10,THREAD_VSCR | ||
| 908 | stw r4,THREAD_USED_VR(r5) | ||
| 909 | lvx vr0,r10,r5 | ||
| 910 | mtvscr vr0 | ||
| 911 | REST_32VRS(0,r4,r5) | ||
| 912 | #ifndef CONFIG_SMP | ||
| 913 | /* Update last_task_used_math to 'current' */ | ||
| 914 | subi r4,r5,THREAD /* Back to 'current' */ | ||
| 915 | std r4,0(r3) | ||
| 916 | #endif /* CONFIG_SMP */ | ||
| 917 | /* restore registers and return */ | ||
| 918 | blr | ||
| 919 | #endif /* CONFIG_ALTIVEC */ | ||
| 920 | |||
| 921 | #ifdef CONFIG_VSX | ||
| 922 | /* | ||
| 923 | * load_up_vsx(unused, unused, tsk) | ||
| 924 | * Disable VSX for the task which had it previously, | ||
| 925 | * and save its vector registers in its thread_struct. | ||
| 926 | * Reuse the fp and vsx saves, but first check to see if they have | ||
| 927 | * been saved already. | ||
| 928 | * On entry: r13 == 'current' && last_task_used_vsx != 'current' | ||
| 929 | */ | ||
| 930 | _STATIC(load_up_vsx) | ||
| 931 | /* Load FP and VSX registers if they haven't been done yet */ | ||
| 932 | andi. r5,r12,MSR_FP | ||
| 933 | beql+ load_up_fpu /* skip if already loaded */ | ||
| 934 | andis. r5,r12,MSR_VEC@h | ||
| 935 | beql+ load_up_altivec /* skip if already loaded */ | ||
| 936 | |||
| 937 | #ifndef CONFIG_SMP | ||
| 938 | ld r3,last_task_used_vsx@got(r2) | ||
| 939 | ld r4,0(r3) | ||
| 940 | cmpdi 0,r4,0 | ||
| 941 | beq 1f | ||
| 942 | /* Disable VSX for last_task_used_vsx */ | ||
| 943 | addi r4,r4,THREAD | ||
| 944 | ld r5,PT_REGS(r4) | ||
| 945 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 946 | lis r6,MSR_VSX@h | ||
| 947 | andc r6,r4,r6 | ||
| 948 | std r6,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 949 | 1: | ||
| 950 | #endif /* CONFIG_SMP */ | ||
| 951 | ld r4,PACACURRENT(r13) | ||
| 952 | addi r4,r4,THREAD /* Get THREAD */ | ||
| 953 | li r6,1 | ||
| 954 | stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */ | ||
| 955 | /* enable use of VSX after return */ | ||
| 956 | oris r12,r12,MSR_VSX@h | ||
| 957 | std r12,_MSR(r1) | ||
| 958 | #ifndef CONFIG_SMP | ||
| 959 | /* Update last_task_used_math to 'current' */ | ||
| 960 | ld r4,PACACURRENT(r13) | ||
| 961 | std r4,0(r3) | ||
| 962 | #endif /* CONFIG_SMP */ | ||
| 963 | b fast_exception_return | ||
| 964 | #endif /* CONFIG_VSX */ | ||
| 965 | |||
| 966 | /* | ||
| 967 | * Hash table stuff | ||
| 968 | */ | ||
| 969 | .align 7 | ||
| 970 | _STATIC(do_hash_page) | ||
| 971 | std r3,_DAR(r1) | ||
| 972 | std r4,_DSISR(r1) | ||
| 973 | |||
| 974 | andis. r0,r4,0xa450 /* weird error? */ | ||
| 975 | bne- handle_page_fault /* if not, try to insert a HPTE */ | ||
| 976 | BEGIN_FTR_SECTION | ||
| 977 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | ||
| 978 | bne- do_ste_alloc /* If so handle it */ | ||
| 979 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | ||
| 980 | |||
| 981 | /* | ||
| 982 | * On iSeries, we soft-disable interrupts here, then | ||
| 983 | * hard-enable interrupts so that the hash_page code can spin on | ||
| 984 | * the hash_table_lock without problems on a shared processor. | ||
| 985 | */ | ||
| 986 | DISABLE_INTS | ||
| 987 | |||
| 988 | /* | ||
| 989 | * Currently, trace_hardirqs_off() will be called by DISABLE_INTS | ||
| 990 | * and will clobber volatile registers when irq tracing is enabled | ||
| 991 | * so we need to reload them. It may be possible to be smarter here | ||
| 992 | * and move the irq tracing elsewhere but let's keep it simple for | ||
| 993 | * now | ||
| 994 | */ | ||
| 995 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 996 | ld r3,_DAR(r1) | ||
| 997 | ld r4,_DSISR(r1) | ||
| 998 | ld r5,_TRAP(r1) | ||
| 999 | ld r12,_MSR(r1) | ||
| 1000 | clrrdi r5,r5,4 | ||
| 1001 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 1002 | /* | ||
| 1003 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | ||
| 1004 | * accessing a userspace segment (even from the kernel). We assume | ||
| 1005 | * kernel addresses always have the high bit set. | ||
| 1006 | */ | ||
| 1007 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | ||
| 1008 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | ||
| 1009 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | ||
| 1010 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | ||
| 1011 | ori r4,r4,1 /* add _PAGE_PRESENT */ | ||
| 1012 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | ||
| 1013 | |||
| 1014 | /* | ||
| 1015 | * r3 contains the faulting address | ||
| 1016 | * r4 contains the required access permissions | ||
| 1017 | * r5 contains the trap number | ||
| 1018 | * | ||
| 1019 | * at return r3 = 0 for success | ||
| 1020 | */ | ||
| 1021 | bl .hash_page /* build HPTE if possible */ | ||
| 1022 | cmpdi r3,0 /* see if hash_page succeeded */ | ||
| 1023 | |||
| 1024 | BEGIN_FW_FTR_SECTION | ||
| 1025 | /* | ||
| 1026 | * If we had interrupts soft-enabled at the point where the | ||
| 1027 | * DSI/ISI occurred, and an interrupt came in during hash_page, | ||
| 1028 | * handle it now. | ||
| 1029 | * We jump to ret_from_except_lite rather than fast_exception_return | ||
| 1030 | * because ret_from_except_lite will check for and handle pending | ||
| 1031 | * interrupts if necessary. | ||
| 1032 | */ | ||
| 1033 | beq 13f | ||
| 1034 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) | ||
| 1035 | |||
| 1036 | BEGIN_FW_FTR_SECTION | ||
| 1037 | /* | ||
| 1038 | * Here we have interrupts hard-disabled, so it is sufficient | ||
| 1039 | * to restore paca->{soft,hard}_enable and get out. | ||
| 1040 | */ | ||
| 1041 | beq fast_exc_return_irq /* Return from exception on success */ | ||
| 1042 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | ||
| 1043 | |||
| 1044 | /* For a hash failure, we don't bother re-enabling interrupts */ | ||
| 1045 | ble- 12f | ||
| 1046 | |||
| 1047 | /* | ||
| 1048 | * hash_page couldn't handle it, set soft interrupt enable back | ||
| 1049 | * to what it was before the trap. Note that .raw_local_irq_restore | ||
| 1050 | * handles any interrupts pending at this point. | ||
| 1051 | */ | ||
| 1052 | ld r3,SOFTE(r1) | ||
| 1053 | TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) | ||
| 1054 | bl .raw_local_irq_restore | ||
| 1055 | b 11f | ||
| 1056 | |||
| 1057 | /* Here we have a page fault that hash_page can't handle. */ | ||
| 1058 | handle_page_fault: | ||
| 1059 | ENABLE_INTS | ||
| 1060 | 11: ld r4,_DAR(r1) | ||
| 1061 | ld r5,_DSISR(r1) | ||
| 1062 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 1063 | bl .do_page_fault | ||
| 1064 | cmpdi r3,0 | ||
| 1065 | beq+ 13f | ||
| 1066 | bl .save_nvgprs | ||
| 1067 | mr r5,r3 | ||
| 1068 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 1069 | lwz r4,_DAR(r1) | ||
| 1070 | bl .bad_page_fault | ||
| 1071 | b .ret_from_except | ||
| 1072 | |||
| 1073 | 13: b .ret_from_except_lite | ||
| 1074 | |||
| 1075 | /* We have a page fault that hash_page could handle but HV refused | ||
| 1076 | * the PTE insertion | ||
| 1077 | */ | ||
| 1078 | 12: bl .save_nvgprs | ||
| 1079 | mr r5,r3 | ||
| 1080 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
| 1081 | ld r4,_DAR(r1) | ||
| 1082 | bl .low_hash_fault | ||
| 1083 | b .ret_from_except | ||
| 1084 | |||
| 1085 | /* here we have a segment miss */ | ||
| 1086 | do_ste_alloc: | ||
| 1087 | bl .ste_allocate /* try to insert stab entry */ | ||
| 1088 | cmpdi r3,0 | ||
| 1089 | bne- handle_page_fault | ||
| 1090 | b fast_exception_return | ||
| 1091 | |||
| 1092 | /* | ||
| 1093 | * r13 points to the PACA, r9 contains the saved CR, | ||
| 1094 | * r11 and r12 contain the saved SRR0 and SRR1. | ||
| 1095 | * r9 - r13 are saved in paca->exslb. | ||
| 1096 | * We assume we aren't going to take any exceptions during this procedure. | ||
| 1097 | * We assume (DAR >> 60) == 0xc. | ||
| 1098 | */ | ||
| 1099 | .align 7 | ||
| 1100 | _GLOBAL(do_stab_bolted) | ||
| 1101 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | ||
| 1102 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | ||
| 1103 | |||
| 1104 | /* Hash to the primary group */ | ||
| 1105 | ld r10,PACASTABVIRT(r13) | ||
| 1106 | mfspr r11,SPRN_DAR | ||
| 1107 | srdi r11,r11,28 | ||
| 1108 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | ||
| 1109 | |||
| 1110 | /* Calculate VSID */ | ||
| 1111 | /* This is a kernel address, so protovsid = ESID */ | ||
| 1112 | ASM_VSID_SCRAMBLE(r11, r9, 256M) | ||
| 1113 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | ||
| 1114 | |||
| 1115 | /* Search the primary group for a free entry */ | ||
| 1116 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | ||
| 1117 | andi. r11,r11,0x80 | ||
| 1118 | beq 2f | ||
| 1119 | addi r10,r10,16 | ||
| 1120 | andi. r11,r10,0x70 | ||
| 1121 | bne 1b | ||
| 1122 | |||
| 1123 | /* Stick for only searching the primary group for now. */ | ||
| 1124 | /* At least for now, we use a very simple random castout scheme */ | ||
| 1125 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | ||
| 1126 | mftb r11 | ||
| 1127 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | ||
| 1128 | ori r11,r11,0x10 | ||
| 1129 | |||
| 1130 | /* r10 currently points to an ste one past the group of interest */ | ||
| 1131 | /* make it point to the randomly selected entry */ | ||
| 1132 | subi r10,r10,128 | ||
| 1133 | or r10,r10,r11 /* r10 is the entry to invalidate */ | ||
| 1134 | |||
| 1135 | isync /* mark the entry invalid */ | ||
| 1136 | ld r11,0(r10) | ||
| 1137 | rldicl r11,r11,56,1 /* clear the valid bit */ | ||
| 1138 | rotldi r11,r11,8 | ||
| 1139 | std r11,0(r10) | ||
| 1140 | sync | ||
| 1141 | |||
| 1142 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | ||
| 1143 | slbie r11 | ||
| 1144 | |||
| 1145 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | ||
| 1146 | eieio | ||
| 1147 | |||
| 1148 | mfspr r11,SPRN_DAR /* Get the new esid */ | ||
| 1149 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | ||
| 1150 | ori r11,r11,0x90 /* Turn on valid and kp */ | ||
| 1151 | std r11,0(r10) /* Put new entry back into the stab */ | ||
| 1152 | |||
| 1153 | sync | ||
| 1154 | |||
| 1155 | /* All done -- return from exception. */ | ||
| 1156 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | ||
| 1157 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | ||
| 1158 | |||
| 1159 | andi. r10,r12,MSR_RI | ||
| 1160 | beq- unrecov_slb | ||
| 1161 | |||
| 1162 | mtcrf 0x80,r9 /* restore CR */ | ||
| 1163 | |||
| 1164 | mfmsr r10 | ||
| 1165 | clrrdi r10,r10,2 | ||
| 1166 | mtmsrd r10,1 | ||
| 1167 | |||
| 1168 | mtspr SPRN_SRR0,r11 | ||
| 1169 | mtspr SPRN_SRR1,r12 | ||
| 1170 | ld r9,PACA_EXSLB+EX_R9(r13) | ||
| 1171 | ld r10,PACA_EXSLB+EX_R10(r13) | ||
| 1172 | ld r11,PACA_EXSLB+EX_R11(r13) | ||
| 1173 | ld r12,PACA_EXSLB+EX_R12(r13) | ||
| 1174 | ld r13,PACA_EXSLB+EX_R13(r13) | ||
| 1175 | rfid | ||
| 1176 | b . /* prevent speculative execution */ | ||
| 1177 | |||
| 1178 | /* | ||
| 1179 | * Space for CPU0's segment table. | ||
| 1180 | * | ||
| 1181 | * On iSeries, the hypervisor must fill in at least one entry before | ||
| 1182 | * we get control (with relocate on). The address is given to the hv | ||
| 1183 | * as a page number (see xLparMap below), so this must be at a | ||
| 1184 | * fixed address (the linker can't compute (u64)&initial_stab >> | ||
| 1185 | * PAGE_SHIFT). | ||
| 1186 | */ | ||
| 1187 | . = STAB0_OFFSET /* 0x6000 */ | ||
| 1188 | .globl initial_stab | ||
| 1189 | initial_stab: | ||
| 1190 | .space 4096 | ||
| 1191 | |||
| 1192 | #ifdef CONFIG_PPC_PSERIES | ||
| 1193 | /* | ||
| 1194 | * Data area reserved for FWNMI option. | ||
| 1195 | * This address (0x7000) is fixed by the RPA. | ||
| 1196 | */ | ||
| 1197 | .= 0x7000 | ||
| 1198 | .globl fwnmi_data_area | ||
| 1199 | fwnmi_data_area: | ||
| 1200 | #endif /* CONFIG_PPC_PSERIES */ | ||
| 1201 | |||
| 1202 | /* iSeries does not use the FWNMI stuff, so it is safe to put | ||
| 1203 | * this here, even if we later allow kernels that will boot on | ||
| 1204 | * both pSeries and iSeries */ | ||
| 1205 | #ifdef CONFIG_PPC_ISERIES | ||
| 1206 | . = LPARMAP_PHYS | ||
| 1207 | .globl xLparMap | ||
| 1208 | xLparMap: | ||
| 1209 | .quad HvEsidsToMap /* xNumberEsids */ | ||
| 1210 | .quad HvRangesToMap /* xNumberRanges */ | ||
| 1211 | .quad STAB0_PAGE /* xSegmentTableOffs */ | ||
| 1212 | .zero 40 /* xRsvd */ | ||
| 1213 | /* xEsids (HvEsidsToMap entries of 2 quads) */ | ||
| 1214 | .quad PAGE_OFFSET_ESID /* xKernelEsid */ | ||
| 1215 | .quad PAGE_OFFSET_VSID /* xKernelVsid */ | ||
| 1216 | .quad VMALLOC_START_ESID /* xKernelEsid */ | ||
| 1217 | .quad VMALLOC_START_VSID /* xKernelVsid */ | ||
| 1218 | /* xRanges (HvRangesToMap entries of 3 quads) */ | ||
| 1219 | .quad HvPagesToMap /* xPages */ | ||
| 1220 | .quad 0 /* xOffset */ | ||
| 1221 | .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */ | ||
| 1222 | |||
| 1223 | #endif /* CONFIG_PPC_ISERIES */ | ||
| 1224 | |||
| 1225 | #ifdef CONFIG_PPC_PSERIES | ||
| 1226 | . = 0x8000 | ||
| 1227 | #endif /* CONFIG_PPC_PSERIES */ | ||
| 1228 | 167 | ||
| 1229 | /* | 168 | /* |
| 1230 | * On pSeries and most other platforms, secondary processors spin | 169 | * On pSeries and most other platforms, secondary processors spin |
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 95f39f1e68d4..5f9febc8d143 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h | |||
| @@ -256,7 +256,7 @@ label: | |||
| 256 | * off DE in the DSRR1 value and clearing the debug status. \ | 256 | * off DE in the DSRR1 value and clearing the debug status. \ |
| 257 | */ \ | 257 | */ \ |
| 258 | mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ | 258 | mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ |
| 259 | andis. r10,r10,DBSR_IC@h; \ | 259 | andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ |
| 260 | beq+ 2f; \ | 260 | beq+ 2f; \ |
| 261 | \ | 261 | \ |
| 262 | lis r10,KERNELBASE@h; /* check if exception in vectors */ \ | 262 | lis r10,KERNELBASE@h; /* check if exception in vectors */ \ |
| @@ -271,7 +271,7 @@ label: | |||
| 271 | \ | 271 | \ |
| 272 | /* here it looks like we got an inappropriate debug exception. */ \ | 272 | /* here it looks like we got an inappropriate debug exception. */ \ |
| 273 | 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ | 273 | 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ |
| 274 | lis r10,DBSR_IC@h; /* clear the IC event */ \ | 274 | lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ |
| 275 | mtspr SPRN_DBSR,r10; \ | 275 | mtspr SPRN_DBSR,r10; \ |
| 276 | /* restore state and get out */ \ | 276 | /* restore state and get out */ \ |
| 277 | lwz r10,_CCR(r11); \ | 277 | lwz r10,_CCR(r11); \ |
| @@ -309,7 +309,7 @@ label: | |||
| 309 | * off DE in the CSRR1 value and clearing the debug status. \ | 309 | * off DE in the CSRR1 value and clearing the debug status. \ |
| 310 | */ \ | 310 | */ \ |
| 311 | mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ | 311 | mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ |
| 312 | andis. r10,r10,DBSR_IC@h; \ | 312 | andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ |
| 313 | beq+ 2f; \ | 313 | beq+ 2f; \ |
| 314 | \ | 314 | \ |
| 315 | lis r10,KERNELBASE@h; /* check if exception in vectors */ \ | 315 | lis r10,KERNELBASE@h; /* check if exception in vectors */ \ |
| @@ -317,14 +317,14 @@ label: | |||
| 317 | cmplw r12,r10; \ | 317 | cmplw r12,r10; \ |
| 318 | blt+ 2f; /* addr below exception vectors */ \ | 318 | blt+ 2f; /* addr below exception vectors */ \ |
| 319 | \ | 319 | \ |
| 320 | lis r10,DebugCrit@h; \ | 320 | lis r10,DebugCrit@h; \ |
| 321 | ori r10,r10,DebugCrit@l; \ | 321 | ori r10,r10,DebugCrit@l; \ |
| 322 | cmplw r12,r10; \ | 322 | cmplw r12,r10; \ |
| 323 | bgt+ 2f; /* addr above exception vectors */ \ | 323 | bgt+ 2f; /* addr above exception vectors */ \ |
| 324 | \ | 324 | \ |
| 325 | /* here it looks like we got an inappropriate debug exception. */ \ | 325 | /* here it looks like we got an inappropriate debug exception. */ \ |
| 326 | 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ | 326 | 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ |
| 327 | lis r10,DBSR_IC@h; /* clear the IC event */ \ | 327 | lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ |
| 328 | mtspr SPRN_DBSR,r10; \ | 328 | mtspr SPRN_DBSR,r10; \ |
| 329 | /* restore state and get out */ \ | 329 | /* restore state and get out */ \ |
| 330 | lwz r10,_CCR(r11); \ | 330 | lwz r10,_CCR(r11); \ |
diff --git a/arch/powerpc/kernel/init_task.c b/arch/powerpc/kernel/init_task.c index 688b329800bd..ffc4253fef55 100644 --- a/arch/powerpc/kernel/init_task.c +++ b/arch/powerpc/kernel/init_task.c | |||
| @@ -9,10 +9,6 @@ | |||
| 9 | 9 | ||
| 10 | static struct signal_struct init_signals = INIT_SIGNALS(init_signals); | 10 | static struct signal_struct init_signals = INIT_SIGNALS(init_signals); |
| 11 | static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); | 11 | static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); |
| 12 | struct mm_struct init_mm = INIT_MM(init_mm); | ||
| 13 | |||
| 14 | EXPORT_SYMBOL(init_mm); | ||
| 15 | |||
| 16 | /* | 12 | /* |
| 17 | * Initial thread structure. | 13 | * Initial thread structure. |
| 18 | * | 14 | * |
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 8c1a4966867e..f7f376ea7b17 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
| @@ -53,6 +53,7 @@ | |||
| 53 | #include <linux/bootmem.h> | 53 | #include <linux/bootmem.h> |
| 54 | #include <linux/pci.h> | 54 | #include <linux/pci.h> |
| 55 | #include <linux/debugfs.h> | 55 | #include <linux/debugfs.h> |
| 56 | #include <linux/perf_counter.h> | ||
| 56 | 57 | ||
| 57 | #include <asm/uaccess.h> | 58 | #include <asm/uaccess.h> |
| 58 | #include <asm/system.h> | 59 | #include <asm/system.h> |
| @@ -117,6 +118,7 @@ notrace void raw_local_irq_restore(unsigned long en) | |||
| 117 | if (!en) | 118 | if (!en) |
| 118 | return; | 119 | return; |
| 119 | 120 | ||
| 121 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 120 | if (firmware_has_feature(FW_FEATURE_ISERIES)) { | 122 | if (firmware_has_feature(FW_FEATURE_ISERIES)) { |
| 121 | /* | 123 | /* |
| 122 | * Do we need to disable preemption here? Not really: in the | 124 | * Do we need to disable preemption here? Not really: in the |
| @@ -134,6 +136,12 @@ notrace void raw_local_irq_restore(unsigned long en) | |||
| 134 | if (local_paca->lppaca_ptr->int_dword.any_int) | 136 | if (local_paca->lppaca_ptr->int_dword.any_int) |
| 135 | iseries_handle_interrupts(); | 137 | iseries_handle_interrupts(); |
| 136 | } | 138 | } |
| 139 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 140 | |||
| 141 | if (test_perf_counter_pending()) { | ||
| 142 | clear_perf_counter_pending(); | ||
| 143 | perf_counter_do_pending(); | ||
| 144 | } | ||
| 137 | 145 | ||
| 138 | /* | 146 | /* |
| 139 | * if (get_paca()->hard_enabled) return; | 147 | * if (get_paca()->hard_enabled) return; |
| @@ -248,77 +256,84 @@ void fixup_irqs(cpumask_t map) | |||
| 248 | } | 256 | } |
| 249 | #endif | 257 | #endif |
| 250 | 258 | ||
| 251 | void do_IRQ(struct pt_regs *regs) | ||
| 252 | { | ||
| 253 | struct pt_regs *old_regs = set_irq_regs(regs); | ||
| 254 | unsigned int irq; | ||
| 255 | #ifdef CONFIG_IRQSTACKS | 259 | #ifdef CONFIG_IRQSTACKS |
| 260 | static inline void handle_one_irq(unsigned int irq) | ||
| 261 | { | ||
| 256 | struct thread_info *curtp, *irqtp; | 262 | struct thread_info *curtp, *irqtp; |
| 257 | #endif | 263 | unsigned long saved_sp_limit; |
| 264 | struct irq_desc *desc; | ||
| 258 | 265 | ||
| 259 | irq_enter(); | 266 | /* Switch to the irq stack to handle this */ |
| 267 | curtp = current_thread_info(); | ||
| 268 | irqtp = hardirq_ctx[smp_processor_id()]; | ||
| 269 | |||
| 270 | if (curtp == irqtp) { | ||
| 271 | /* We're already on the irq stack, just handle it */ | ||
| 272 | generic_handle_irq(irq); | ||
| 273 | return; | ||
| 274 | } | ||
| 275 | |||
| 276 | desc = irq_desc + irq; | ||
| 277 | saved_sp_limit = current->thread.ksp_limit; | ||
| 278 | |||
| 279 | irqtp->task = curtp->task; | ||
| 280 | irqtp->flags = 0; | ||
| 281 | |||
| 282 | /* Copy the softirq bits in preempt_count so that the | ||
| 283 | * softirq checks work in the hardirq context. */ | ||
| 284 | irqtp->preempt_count = (irqtp->preempt_count & ~SOFTIRQ_MASK) | | ||
| 285 | (curtp->preempt_count & SOFTIRQ_MASK); | ||
| 286 | |||
| 287 | current->thread.ksp_limit = (unsigned long)irqtp + | ||
| 288 | _ALIGN_UP(sizeof(struct thread_info), 16); | ||
| 289 | |||
| 290 | call_handle_irq(irq, desc, irqtp, desc->handle_irq); | ||
| 291 | current->thread.ksp_limit = saved_sp_limit; | ||
| 292 | irqtp->task = NULL; | ||
| 260 | 293 | ||
| 294 | /* Set any flag that may have been set on the | ||
| 295 | * alternate stack | ||
| 296 | */ | ||
| 297 | if (irqtp->flags) | ||
| 298 | set_bits(irqtp->flags, &curtp->flags); | ||
| 299 | } | ||
| 300 | #else | ||
| 301 | static inline void handle_one_irq(unsigned int irq) | ||
| 302 | { | ||
| 303 | generic_handle_irq(irq); | ||
| 304 | } | ||
| 305 | #endif | ||
| 306 | |||
| 307 | static inline void check_stack_overflow(void) | ||
| 308 | { | ||
| 261 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | 309 | #ifdef CONFIG_DEBUG_STACKOVERFLOW |
| 262 | /* Debugging check for stack overflow: is there less than 2KB free? */ | 310 | long sp; |
| 263 | { | ||
| 264 | long sp; | ||
| 265 | 311 | ||
| 266 | sp = __get_SP() & (THREAD_SIZE-1); | 312 | sp = __get_SP() & (THREAD_SIZE-1); |
| 267 | 313 | ||
| 268 | if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { | 314 | /* check for stack overflow: is there less than 2KB free? */ |
| 269 | printk("do_IRQ: stack overflow: %ld\n", | 315 | if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { |
| 270 | sp - sizeof(struct thread_info)); | 316 | printk("do_IRQ: stack overflow: %ld\n", |
| 271 | dump_stack(); | 317 | sp - sizeof(struct thread_info)); |
| 272 | } | 318 | dump_stack(); |
| 273 | } | 319 | } |
| 274 | #endif | 320 | #endif |
| 321 | } | ||
| 275 | 322 | ||
| 276 | /* | 323 | void do_IRQ(struct pt_regs *regs) |
| 277 | * Every platform is required to implement ppc_md.get_irq. | 324 | { |
| 278 | * This function will either return an irq number or NO_IRQ to | 325 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 279 | * indicate there are no more pending. | 326 | unsigned int irq; |
| 280 | * The value NO_IRQ_IGNORE is for buggy hardware and means that this | ||
| 281 | * IRQ has already been handled. -- Tom | ||
| 282 | */ | ||
| 283 | irq = ppc_md.get_irq(); | ||
| 284 | 327 | ||
| 285 | if (irq != NO_IRQ && irq != NO_IRQ_IGNORE) { | 328 | irq_enter(); |
| 286 | #ifdef CONFIG_IRQSTACKS | ||
| 287 | /* Switch to the irq stack to handle this */ | ||
| 288 | curtp = current_thread_info(); | ||
| 289 | irqtp = hardirq_ctx[smp_processor_id()]; | ||
| 290 | if (curtp != irqtp) { | ||
| 291 | struct irq_desc *desc = irq_desc + irq; | ||
| 292 | void *handler = desc->handle_irq; | ||
| 293 | unsigned long saved_sp_limit = current->thread.ksp_limit; | ||
| 294 | if (handler == NULL) | ||
| 295 | handler = &__do_IRQ; | ||
| 296 | irqtp->task = curtp->task; | ||
| 297 | irqtp->flags = 0; | ||
| 298 | |||
| 299 | /* Copy the softirq bits in preempt_count so that the | ||
| 300 | * softirq checks work in the hardirq context. | ||
| 301 | */ | ||
| 302 | irqtp->preempt_count = | ||
| 303 | (irqtp->preempt_count & ~SOFTIRQ_MASK) | | ||
| 304 | (curtp->preempt_count & SOFTIRQ_MASK); | ||
| 305 | 329 | ||
| 306 | current->thread.ksp_limit = (unsigned long)irqtp + | 330 | check_stack_overflow(); |
| 307 | _ALIGN_UP(sizeof(struct thread_info), 16); | ||
| 308 | call_handle_irq(irq, desc, irqtp, handler); | ||
| 309 | current->thread.ksp_limit = saved_sp_limit; | ||
| 310 | irqtp->task = NULL; | ||
| 311 | 331 | ||
| 332 | irq = ppc_md.get_irq(); | ||
| 312 | 333 | ||
| 313 | /* Set any flag that may have been set on the | 334 | if (irq != NO_IRQ && irq != NO_IRQ_IGNORE) |
| 314 | * alternate stack | 335 | handle_one_irq(irq); |
| 315 | */ | 336 | else if (irq != NO_IRQ_IGNORE) |
| 316 | if (irqtp->flags) | ||
| 317 | set_bits(irqtp->flags, &curtp->flags); | ||
| 318 | } else | ||
| 319 | #endif | ||
| 320 | generic_handle_irq(irq); | ||
| 321 | } else if (irq != NO_IRQ_IGNORE) | ||
| 322 | /* That's not SMP safe ... but who cares ? */ | 337 | /* That's not SMP safe ... but who cares ? */ |
| 323 | ppc_spurious_interrupts++; | 338 | ppc_spurious_interrupts++; |
| 324 | 339 | ||
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c index 78b3f7840ade..2419cc706ff1 100644 --- a/arch/powerpc/kernel/lparcfg.c +++ b/arch/powerpc/kernel/lparcfg.c | |||
| @@ -169,6 +169,9 @@ struct hvcall_ppp_data { | |||
| 169 | u8 unallocated_weight; | 169 | u8 unallocated_weight; |
| 170 | u16 active_procs_in_pool; | 170 | u16 active_procs_in_pool; |
| 171 | u16 active_system_procs; | 171 | u16 active_system_procs; |
| 172 | u16 phys_platform_procs; | ||
| 173 | u32 max_proc_cap_avail; | ||
| 174 | u32 entitled_proc_cap_avail; | ||
| 172 | }; | 175 | }; |
| 173 | 176 | ||
| 174 | /* | 177 | /* |
| @@ -190,13 +193,18 @@ struct hvcall_ppp_data { | |||
| 190 | * XX - Unallocated Variable Processor Capacity Weight. | 193 | * XX - Unallocated Variable Processor Capacity Weight. |
| 191 | * XXXX - Active processors in Physical Processor Pool. | 194 | * XXXX - Active processors in Physical Processor Pool. |
| 192 | * XXXX - Processors active on platform. | 195 | * XXXX - Processors active on platform. |
| 196 | * R8 (QQQQRRRRRRSSSSSS). if ibm,partition-performance-parameters-level >= 1 | ||
| 197 | * XXXX - Physical platform procs allocated to virtualization. | ||
| 198 | * XXXXXX - Max procs capacity % available to the partitions pool. | ||
| 199 | * XXXXXX - Entitled procs capacity % available to the | ||
| 200 | * partitions pool. | ||
| 193 | */ | 201 | */ |
| 194 | static unsigned int h_get_ppp(struct hvcall_ppp_data *ppp_data) | 202 | static unsigned int h_get_ppp(struct hvcall_ppp_data *ppp_data) |
| 195 | { | 203 | { |
| 196 | unsigned long rc; | 204 | unsigned long rc; |
| 197 | unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; | 205 | unsigned long retbuf[PLPAR_HCALL9_BUFSIZE]; |
| 198 | 206 | ||
| 199 | rc = plpar_hcall(H_GET_PPP, retbuf); | 207 | rc = plpar_hcall9(H_GET_PPP, retbuf); |
| 200 | 208 | ||
| 201 | ppp_data->entitlement = retbuf[0]; | 209 | ppp_data->entitlement = retbuf[0]; |
| 202 | ppp_data->unallocated_entitlement = retbuf[1]; | 210 | ppp_data->unallocated_entitlement = retbuf[1]; |
| @@ -210,6 +218,10 @@ static unsigned int h_get_ppp(struct hvcall_ppp_data *ppp_data) | |||
| 210 | ppp_data->active_procs_in_pool = (retbuf[3] >> 2 * 8) & 0xffff; | 218 | ppp_data->active_procs_in_pool = (retbuf[3] >> 2 * 8) & 0xffff; |
| 211 | ppp_data->active_system_procs = retbuf[3] & 0xffff; | 219 | ppp_data->active_system_procs = retbuf[3] & 0xffff; |
| 212 | 220 | ||
| 221 | ppp_data->phys_platform_procs = retbuf[4] >> 6 * 8; | ||
| 222 | ppp_data->max_proc_cap_avail = (retbuf[4] >> 3 * 8) & 0xffffff; | ||
| 223 | ppp_data->entitled_proc_cap_avail = retbuf[4] & 0xffffff; | ||
| 224 | |||
| 213 | return rc; | 225 | return rc; |
| 214 | } | 226 | } |
| 215 | 227 | ||
| @@ -234,6 +246,8 @@ static unsigned h_pic(unsigned long *pool_idle_time, | |||
| 234 | static void parse_ppp_data(struct seq_file *m) | 246 | static void parse_ppp_data(struct seq_file *m) |
| 235 | { | 247 | { |
| 236 | struct hvcall_ppp_data ppp_data; | 248 | struct hvcall_ppp_data ppp_data; |
| 249 | struct device_node *root; | ||
| 250 | const int *perf_level; | ||
| 237 | int rc; | 251 | int rc; |
| 238 | 252 | ||
| 239 | rc = h_get_ppp(&ppp_data); | 253 | rc = h_get_ppp(&ppp_data); |
| @@ -267,6 +281,28 @@ static void parse_ppp_data(struct seq_file *m) | |||
| 267 | seq_printf(m, "capped=%d\n", ppp_data.capped); | 281 | seq_printf(m, "capped=%d\n", ppp_data.capped); |
| 268 | seq_printf(m, "unallocated_capacity=%lld\n", | 282 | seq_printf(m, "unallocated_capacity=%lld\n", |
| 269 | ppp_data.unallocated_entitlement); | 283 | ppp_data.unallocated_entitlement); |
| 284 | |||
| 285 | /* The last bits of information returned from h_get_ppp are only | ||
| 286 | * valid if the ibm,partition-performance-parameters-level | ||
| 287 | * property is >= 1. | ||
| 288 | */ | ||
| 289 | root = of_find_node_by_path("/"); | ||
| 290 | if (root) { | ||
| 291 | perf_level = of_get_property(root, | ||
| 292 | "ibm,partition-performance-parameters-level", | ||
| 293 | NULL); | ||
| 294 | if (perf_level && (*perf_level >= 1)) { | ||
| 295 | seq_printf(m, | ||
| 296 | "physical_procs_allocated_to_virtualization=%d\n", | ||
| 297 | ppp_data.phys_platform_procs); | ||
| 298 | seq_printf(m, "max_proc_capacity_available=%d\n", | ||
| 299 | ppp_data.max_proc_cap_avail); | ||
| 300 | seq_printf(m, "entitled_proc_capacity_available=%d\n", | ||
| 301 | ppp_data.entitled_proc_cap_avail); | ||
| 302 | } | ||
| 303 | |||
| 304 | of_node_put(root); | ||
| 305 | } | ||
| 270 | } | 306 | } |
| 271 | 307 | ||
| 272 | /** | 308 | /** |
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index b9530b2395a2..a5cf9c1356a6 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S | |||
| @@ -457,98 +457,6 @@ _GLOBAL(disable_kernel_fp) | |||
| 457 | isync | 457 | isync |
| 458 | blr | 458 | blr |
| 459 | 459 | ||
| 460 | #ifdef CONFIG_ALTIVEC | ||
| 461 | |||
| 462 | #if 0 /* this has no callers for now */ | ||
| 463 | /* | ||
| 464 | * disable_kernel_altivec() | ||
| 465 | * Disable the VMX. | ||
| 466 | */ | ||
| 467 | _GLOBAL(disable_kernel_altivec) | ||
| 468 | mfmsr r3 | ||
| 469 | rldicl r0,r3,(63-MSR_VEC_LG),1 | ||
| 470 | rldicl r3,r0,(MSR_VEC_LG+1),0 | ||
| 471 | mtmsrd r3 /* disable use of VMX now */ | ||
| 472 | isync | ||
| 473 | blr | ||
| 474 | #endif /* 0 */ | ||
| 475 | |||
| 476 | /* | ||
| 477 | * giveup_altivec(tsk) | ||
| 478 | * Disable VMX for the task given as the argument, | ||
| 479 | * and save the vector registers in its thread_struct. | ||
| 480 | * Enables the VMX for use in the kernel on return. | ||
| 481 | */ | ||
| 482 | _GLOBAL(giveup_altivec) | ||
| 483 | mfmsr r5 | ||
| 484 | oris r5,r5,MSR_VEC@h | ||
| 485 | mtmsrd r5 /* enable use of VMX now */ | ||
| 486 | isync | ||
| 487 | cmpdi 0,r3,0 | ||
| 488 | beqlr- /* if no previous owner, done */ | ||
| 489 | addi r3,r3,THREAD /* want THREAD of task */ | ||
| 490 | ld r5,PT_REGS(r3) | ||
| 491 | cmpdi 0,r5,0 | ||
| 492 | SAVE_32VRS(0,r4,r3) | ||
| 493 | mfvscr vr0 | ||
| 494 | li r4,THREAD_VSCR | ||
| 495 | stvx vr0,r4,r3 | ||
| 496 | beq 1f | ||
| 497 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 498 | #ifdef CONFIG_VSX | ||
| 499 | BEGIN_FTR_SECTION | ||
| 500 | lis r3,(MSR_VEC|MSR_VSX)@h | ||
| 501 | FTR_SECTION_ELSE | ||
| 502 | lis r3,MSR_VEC@h | ||
| 503 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | ||
| 504 | #else | ||
| 505 | lis r3,MSR_VEC@h | ||
| 506 | #endif | ||
| 507 | andc r4,r4,r3 /* disable FP for previous task */ | ||
| 508 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 509 | 1: | ||
| 510 | #ifndef CONFIG_SMP | ||
| 511 | li r5,0 | ||
| 512 | ld r4,last_task_used_altivec@got(r2) | ||
| 513 | std r5,0(r4) | ||
| 514 | #endif /* CONFIG_SMP */ | ||
| 515 | blr | ||
| 516 | |||
| 517 | #endif /* CONFIG_ALTIVEC */ | ||
| 518 | |||
| 519 | #ifdef CONFIG_VSX | ||
| 520 | /* | ||
| 521 | * __giveup_vsx(tsk) | ||
| 522 | * Disable VSX for the task given as the argument. | ||
| 523 | * Does NOT save vsx registers. | ||
| 524 | * Enables the VSX for use in the kernel on return. | ||
| 525 | */ | ||
| 526 | _GLOBAL(__giveup_vsx) | ||
| 527 | mfmsr r5 | ||
| 528 | oris r5,r5,MSR_VSX@h | ||
| 529 | mtmsrd r5 /* enable use of VSX now */ | ||
| 530 | isync | ||
| 531 | |||
| 532 | cmpdi 0,r3,0 | ||
| 533 | beqlr- /* if no previous owner, done */ | ||
| 534 | addi r3,r3,THREAD /* want THREAD of task */ | ||
| 535 | ld r5,PT_REGS(r3) | ||
| 536 | cmpdi 0,r5,0 | ||
| 537 | beq 1f | ||
| 538 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 539 | lis r3,MSR_VSX@h | ||
| 540 | andc r4,r4,r3 /* disable VSX for previous task */ | ||
| 541 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 542 | 1: | ||
| 543 | #ifndef CONFIG_SMP | ||
| 544 | li r5,0 | ||
| 545 | ld r4,last_task_used_vsx@got(r2) | ||
| 546 | std r5,0(r4) | ||
| 547 | #endif /* CONFIG_SMP */ | ||
| 548 | blr | ||
| 549 | |||
| 550 | #endif /* CONFIG_VSX */ | ||
| 551 | |||
| 552 | /* kexec_wait(phys_cpu) | 460 | /* kexec_wait(phys_cpu) |
| 553 | * | 461 | * |
| 554 | * wait for the flag to change, indicating this kernel is going away but | 462 | * wait for the flag to change, indicating this kernel is going away but |
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c index 43e7e3a7f130..477c663e0140 100644 --- a/arch/powerpc/kernel/module.c +++ b/arch/powerpc/kernel/module.c | |||
| @@ -43,8 +43,6 @@ void *module_alloc(unsigned long size) | |||
| 43 | void module_free(struct module *mod, void *module_region) | 43 | void module_free(struct module *mod, void *module_region) |
| 44 | { | 44 | { |
| 45 | vfree(module_region); | 45 | vfree(module_region); |
| 46 | /* FIXME: If module_region == mod->init_region, trim exception | ||
| 47 | table entries. */ | ||
| 48 | } | 46 | } |
| 49 | 47 | ||
| 50 | static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, | 48 | static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, |
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c new file mode 100644 index 000000000000..75ff47fed7bf --- /dev/null +++ b/arch/powerpc/kernel/mpc7450-pmu.c | |||
| @@ -0,0 +1,417 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for MPC7450-family processors. | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/string.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | #define N_COUNTER 6 /* Number of hardware counters */ | ||
| 18 | #define MAX_ALT 3 /* Maximum number of event alternative codes */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Bits in event code for MPC7450 family | ||
| 22 | */ | ||
| 23 | #define PM_THRMULT_MSKS 0x40000 | ||
| 24 | #define PM_THRESH_SH 12 | ||
| 25 | #define PM_THRESH_MSK 0x3f | ||
| 26 | #define PM_PMC_SH 8 | ||
| 27 | #define PM_PMC_MSK 7 | ||
| 28 | #define PM_PMCSEL_MSK 0x7f | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Classify events according to how specific their PMC requirements are. | ||
| 32 | * Result is: | ||
| 33 | * 0: can go on any PMC | ||
| 34 | * 1: can go on PMCs 1-4 | ||
| 35 | * 2: can go on PMCs 1,2,4 | ||
| 36 | * 3: can go on PMCs 1 or 2 | ||
| 37 | * 4: can only go on one PMC | ||
| 38 | * -1: event code is invalid | ||
| 39 | */ | ||
| 40 | #define N_CLASSES 5 | ||
| 41 | |||
| 42 | static int mpc7450_classify_event(u32 event) | ||
| 43 | { | ||
| 44 | int pmc; | ||
| 45 | |||
| 46 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 47 | if (pmc) { | ||
| 48 | if (pmc > N_COUNTER) | ||
| 49 | return -1; | ||
| 50 | return 4; | ||
| 51 | } | ||
| 52 | event &= PM_PMCSEL_MSK; | ||
| 53 | if (event <= 1) | ||
| 54 | return 0; | ||
| 55 | if (event <= 7) | ||
| 56 | return 1; | ||
| 57 | if (event <= 13) | ||
| 58 | return 2; | ||
| 59 | if (event <= 22) | ||
| 60 | return 3; | ||
| 61 | return -1; | ||
| 62 | } | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Events using threshold and possible threshold scale: | ||
| 66 | * code scale? name | ||
| 67 | * 11e N PM_INSTQ_EXCEED_CYC | ||
| 68 | * 11f N PM_ALTV_IQ_EXCEED_CYC | ||
| 69 | * 128 Y PM_DTLB_SEARCH_EXCEED_CYC | ||
| 70 | * 12b Y PM_LD_MISS_EXCEED_L1_CYC | ||
| 71 | * 220 N PM_CQ_EXCEED_CYC | ||
| 72 | * 30c N PM_GPR_RB_EXCEED_CYC | ||
| 73 | * 30d ? PM_FPR_IQ_EXCEED_CYC ? | ||
| 74 | * 311 Y PM_ITLB_SEARCH_EXCEED | ||
| 75 | * 410 N PM_GPR_IQ_EXCEED_CYC | ||
| 76 | */ | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Return use of threshold and threshold scale bits: | ||
| 80 | * 0 = uses neither, 1 = uses threshold, 2 = uses both | ||
| 81 | */ | ||
| 82 | static int mpc7450_threshold_use(u32 event) | ||
| 83 | { | ||
| 84 | int pmc, sel; | ||
| 85 | |||
| 86 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 87 | sel = event & PM_PMCSEL_MSK; | ||
| 88 | switch (pmc) { | ||
| 89 | case 1: | ||
| 90 | if (sel == 0x1e || sel == 0x1f) | ||
| 91 | return 1; | ||
| 92 | if (sel == 0x28 || sel == 0x2b) | ||
| 93 | return 2; | ||
| 94 | break; | ||
| 95 | case 2: | ||
| 96 | if (sel == 0x20) | ||
| 97 | return 1; | ||
| 98 | break; | ||
| 99 | case 3: | ||
| 100 | if (sel == 0xc || sel == 0xd) | ||
| 101 | return 1; | ||
| 102 | if (sel == 0x11) | ||
| 103 | return 2; | ||
| 104 | break; | ||
| 105 | case 4: | ||
| 106 | if (sel == 0x10) | ||
| 107 | return 1; | ||
| 108 | break; | ||
| 109 | } | ||
| 110 | return 0; | ||
| 111 | } | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Layout of constraint bits: | ||
| 115 | * 33222222222211111111110000000000 | ||
| 116 | * 10987654321098765432109876543210 | ||
| 117 | * |< >< > < > < ><><><><><><> | ||
| 118 | * TS TV G4 G3 G2P6P5P4P3P2P1 | ||
| 119 | * | ||
| 120 | * P1 - P6 | ||
| 121 | * 0 - 11: Count of events needing PMC1 .. PMC6 | ||
| 122 | * | ||
| 123 | * G2 | ||
| 124 | * 12 - 14: Count of events needing PMC1 or PMC2 | ||
| 125 | * | ||
| 126 | * G3 | ||
| 127 | * 16 - 18: Count of events needing PMC1, PMC2 or PMC4 | ||
| 128 | * | ||
| 129 | * G4 | ||
| 130 | * 20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4 | ||
| 131 | * | ||
| 132 | * TV | ||
| 133 | * 24 - 29: Threshold value requested | ||
| 134 | * | ||
| 135 | * TS | ||
| 136 | * 30: Threshold scale value requested | ||
| 137 | */ | ||
| 138 | |||
| 139 | static u32 pmcbits[N_COUNTER][2] = { | ||
| 140 | { 0x00844002, 0x00111001 }, /* PMC1 mask, value: P1,G2,G3,G4 */ | ||
| 141 | { 0x00844008, 0x00111004 }, /* PMC2: P2,G2,G3,G4 */ | ||
| 142 | { 0x00800020, 0x00100010 }, /* PMC3: P3,G4 */ | ||
| 143 | { 0x00840080, 0x00110040 }, /* PMC4: P4,G3,G4 */ | ||
| 144 | { 0x00000200, 0x00000100 }, /* PMC5: P5 */ | ||
| 145 | { 0x00000800, 0x00000400 } /* PMC6: P6 */ | ||
| 146 | }; | ||
| 147 | |||
| 148 | static u32 classbits[N_CLASSES - 1][2] = { | ||
| 149 | { 0x00000000, 0x00000000 }, /* class 0: no constraint */ | ||
| 150 | { 0x00800000, 0x00100000 }, /* class 1: G4 */ | ||
| 151 | { 0x00040000, 0x00010000 }, /* class 2: G3 */ | ||
| 152 | { 0x00004000, 0x00001000 }, /* class 3: G2 */ | ||
| 153 | }; | ||
| 154 | |||
| 155 | static int mpc7450_get_constraint(u64 event, unsigned long *maskp, | ||
| 156 | unsigned long *valp) | ||
| 157 | { | ||
| 158 | int pmc, class; | ||
| 159 | u32 mask, value; | ||
| 160 | int thresh, tuse; | ||
| 161 | |||
| 162 | class = mpc7450_classify_event(event); | ||
| 163 | if (class < 0) | ||
| 164 | return -1; | ||
| 165 | if (class == 4) { | ||
| 166 | pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 167 | mask = pmcbits[pmc - 1][0]; | ||
| 168 | value = pmcbits[pmc - 1][1]; | ||
| 169 | } else { | ||
| 170 | mask = classbits[class][0]; | ||
| 171 | value = classbits[class][1]; | ||
| 172 | } | ||
| 173 | |||
| 174 | tuse = mpc7450_threshold_use(event); | ||
| 175 | if (tuse) { | ||
| 176 | thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK; | ||
| 177 | mask |= 0x3f << 24; | ||
| 178 | value |= thresh << 24; | ||
| 179 | if (tuse == 2) { | ||
| 180 | mask |= 0x40000000; | ||
| 181 | if ((unsigned int)event & PM_THRMULT_MSKS) | ||
| 182 | value |= 0x40000000; | ||
| 183 | } | ||
| 184 | } | ||
| 185 | |||
| 186 | *maskp = mask; | ||
| 187 | *valp = value; | ||
| 188 | return 0; | ||
| 189 | } | ||
| 190 | |||
| 191 | static const unsigned int event_alternatives[][MAX_ALT] = { | ||
| 192 | { 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */ | ||
| 193 | { 0x418, 0x50f, 0x60f }, /* PM_SNOOP_RETRY */ | ||
| 194 | { 0x502, 0x602 }, /* PM_L2_HIT */ | ||
| 195 | { 0x503, 0x603 }, /* PM_L3_HIT */ | ||
| 196 | { 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */ | ||
| 197 | { 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */ | ||
| 198 | { 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */ | ||
| 199 | { 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */ | ||
| 200 | { 0x50a, 0x623 }, /* PM_LD_HIT_L3 */ | ||
| 201 | { 0x50b, 0x624 }, /* PM_ST_HIT_L3 */ | ||
| 202 | { 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */ | ||
| 203 | { 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */ | ||
| 204 | { 0x512, 0x612 }, /* PM_INT_LOCAL */ | ||
| 205 | { 0x513, 0x61d }, /* PM_L2_MISS */ | ||
| 206 | { 0x514, 0x61e }, /* PM_L3_MISS */ | ||
| 207 | }; | ||
| 208 | |||
| 209 | /* | ||
| 210 | * Scan the alternatives table for a match and return the | ||
| 211 | * index into the alternatives table if found, else -1. | ||
| 212 | */ | ||
| 213 | static int find_alternative(u32 event) | ||
| 214 | { | ||
| 215 | int i, j; | ||
| 216 | |||
| 217 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | ||
| 218 | if (event < event_alternatives[i][0]) | ||
| 219 | break; | ||
| 220 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | ||
| 221 | if (event == event_alternatives[i][j]) | ||
| 222 | return i; | ||
| 223 | } | ||
| 224 | return -1; | ||
| 225 | } | ||
| 226 | |||
| 227 | static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 228 | { | ||
| 229 | int i, j, nalt = 1; | ||
| 230 | u32 ae; | ||
| 231 | |||
| 232 | alt[0] = event; | ||
| 233 | nalt = 1; | ||
| 234 | i = find_alternative((u32)event); | ||
| 235 | if (i >= 0) { | ||
| 236 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 237 | ae = event_alternatives[i][j]; | ||
| 238 | if (ae && ae != (u32)event) | ||
| 239 | alt[nalt++] = ae; | ||
| 240 | } | ||
| 241 | } | ||
| 242 | return nalt; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* | ||
| 246 | * Bitmaps of which PMCs each class can use for classes 0 - 3. | ||
| 247 | * Bit i is set if PMC i+1 is usable. | ||
| 248 | */ | ||
| 249 | static const u8 classmap[N_CLASSES] = { | ||
| 250 | 0x3f, 0x0f, 0x0b, 0x03, 0 | ||
| 251 | }; | ||
| 252 | |||
| 253 | /* Bit position and width of each PMCSEL field */ | ||
| 254 | static const int pmcsel_shift[N_COUNTER] = { | ||
| 255 | 6, 0, 27, 22, 17, 11 | ||
| 256 | }; | ||
| 257 | static const u32 pmcsel_mask[N_COUNTER] = { | ||
| 258 | 0x7f, 0x3f, 0x1f, 0x1f, 0x1f, 0x3f | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* | ||
| 262 | * Compute MMCR0/1/2 values for a set of events. | ||
| 263 | */ | ||
| 264 | static int mpc7450_compute_mmcr(u64 event[], int n_ev, | ||
| 265 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 266 | { | ||
| 267 | u8 event_index[N_CLASSES][N_COUNTER]; | ||
| 268 | int n_classevent[N_CLASSES]; | ||
| 269 | int i, j, class, tuse; | ||
| 270 | u32 pmc_inuse = 0, pmc_avail; | ||
| 271 | u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0; | ||
| 272 | u32 ev, pmc, thresh; | ||
| 273 | |||
| 274 | if (n_ev > N_COUNTER) | ||
| 275 | return -1; | ||
| 276 | |||
| 277 | /* First pass: count usage in each class */ | ||
| 278 | for (i = 0; i < N_CLASSES; ++i) | ||
| 279 | n_classevent[i] = 0; | ||
| 280 | for (i = 0; i < n_ev; ++i) { | ||
| 281 | class = mpc7450_classify_event(event[i]); | ||
| 282 | if (class < 0) | ||
| 283 | return -1; | ||
| 284 | j = n_classevent[class]++; | ||
| 285 | event_index[class][j] = i; | ||
| 286 | } | ||
| 287 | |||
| 288 | /* Second pass: allocate PMCs from most specific event to least */ | ||
| 289 | for (class = N_CLASSES - 1; class >= 0; --class) { | ||
| 290 | for (i = 0; i < n_classevent[class]; ++i) { | ||
| 291 | ev = event[event_index[class][i]]; | ||
| 292 | if (class == 4) { | ||
| 293 | pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 294 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 295 | return -1; | ||
| 296 | } else { | ||
| 297 | /* Find a suitable PMC */ | ||
| 298 | pmc_avail = classmap[class] & ~pmc_inuse; | ||
| 299 | if (!pmc_avail) | ||
| 300 | return -1; | ||
| 301 | pmc = ffs(pmc_avail); | ||
| 302 | } | ||
| 303 | pmc_inuse |= 1 << (pmc - 1); | ||
| 304 | |||
| 305 | tuse = mpc7450_threshold_use(ev); | ||
| 306 | if (tuse) { | ||
| 307 | thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK; | ||
| 308 | mmcr0 |= thresh << 16; | ||
| 309 | if (tuse == 2 && (ev & PM_THRMULT_MSKS)) | ||
| 310 | mmcr2 = 0x80000000; | ||
| 311 | } | ||
| 312 | ev &= pmcsel_mask[pmc - 1]; | ||
| 313 | ev <<= pmcsel_shift[pmc - 1]; | ||
| 314 | if (pmc <= 2) | ||
| 315 | mmcr0 |= ev; | ||
| 316 | else | ||
| 317 | mmcr1 |= ev; | ||
| 318 | hwc[event_index[class][i]] = pmc - 1; | ||
| 319 | } | ||
| 320 | } | ||
| 321 | |||
| 322 | if (pmc_inuse & 1) | ||
| 323 | mmcr0 |= MMCR0_PMC1CE; | ||
| 324 | if (pmc_inuse & 0x3e) | ||
| 325 | mmcr0 |= MMCR0_PMCnCE; | ||
| 326 | |||
| 327 | /* Return MMCRx values */ | ||
| 328 | mmcr[0] = mmcr0; | ||
| 329 | mmcr[1] = mmcr1; | ||
| 330 | mmcr[2] = mmcr2; | ||
| 331 | return 0; | ||
| 332 | } | ||
| 333 | |||
| 334 | /* | ||
| 335 | * Disable counting by a PMC. | ||
| 336 | * Note that the pmc argument is 0-based here, not 1-based. | ||
| 337 | */ | ||
| 338 | static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 339 | { | ||
| 340 | if (pmc <= 1) | ||
| 341 | mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]); | ||
| 342 | else | ||
| 343 | mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]); | ||
| 344 | } | ||
| 345 | |||
| 346 | static int mpc7450_generic_events[] = { | ||
| 347 | [PERF_COUNT_HW_CPU_CYCLES] = 1, | ||
| 348 | [PERF_COUNT_HW_INSTRUCTIONS] = 2, | ||
| 349 | [PERF_COUNT_HW_CACHE_MISSES] = 0x217, /* PM_L1_DCACHE_MISS */ | ||
| 350 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x122, /* PM_BR_CMPL */ | ||
| 351 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x41c, /* PM_BR_MPRED */ | ||
| 352 | }; | ||
| 353 | |||
| 354 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 355 | |||
| 356 | /* | ||
| 357 | * Table of generalized cache-related events. | ||
| 358 | * 0 means not supported, -1 means nonsensical, other values | ||
| 359 | * are event codes. | ||
| 360 | */ | ||
| 361 | static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 362 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 363 | [C(OP_READ)] = { 0, 0x225 }, | ||
| 364 | [C(OP_WRITE)] = { 0, 0x227 }, | ||
| 365 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 366 | }, | ||
| 367 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 368 | [C(OP_READ)] = { 0x129, 0x115 }, | ||
| 369 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 370 | [C(OP_PREFETCH)] = { 0x634, 0 }, | ||
| 371 | }, | ||
| 372 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 373 | [C(OP_READ)] = { 0, 0 }, | ||
| 374 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 375 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 376 | }, | ||
| 377 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 378 | [C(OP_READ)] = { 0, 0x312 }, | ||
| 379 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 380 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 381 | }, | ||
| 382 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 383 | [C(OP_READ)] = { 0, 0x223 }, | ||
| 384 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 385 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 386 | }, | ||
| 387 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 388 | [C(OP_READ)] = { 0x122, 0x41c }, | ||
| 389 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 390 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 391 | }, | ||
| 392 | }; | ||
| 393 | |||
| 394 | struct power_pmu mpc7450_pmu = { | ||
| 395 | .name = "MPC7450 family", | ||
| 396 | .n_counter = N_COUNTER, | ||
| 397 | .max_alternatives = MAX_ALT, | ||
| 398 | .add_fields = 0x00111555ul, | ||
| 399 | .test_adder = 0x00301000ul, | ||
| 400 | .compute_mmcr = mpc7450_compute_mmcr, | ||
| 401 | .get_constraint = mpc7450_get_constraint, | ||
| 402 | .get_alternatives = mpc7450_get_alternatives, | ||
| 403 | .disable_pmc = mpc7450_disable_pmc, | ||
| 404 | .n_generic = ARRAY_SIZE(mpc7450_generic_events), | ||
| 405 | .generic_events = mpc7450_generic_events, | ||
| 406 | .cache_events = &mpc7450_cache_events, | ||
| 407 | }; | ||
| 408 | |||
| 409 | static int init_mpc7450_pmu(void) | ||
| 410 | { | ||
| 411 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450")) | ||
| 412 | return -ENODEV; | ||
| 413 | |||
| 414 | return register_power_pmu(&mpc7450_pmu); | ||
| 415 | } | ||
| 416 | |||
| 417 | arch_initcall(init_mpc7450_pmu); | ||
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c index c744b327bcab..e9962c7f8a09 100644 --- a/arch/powerpc/kernel/paca.c +++ b/arch/powerpc/kernel/paca.c | |||
| @@ -18,6 +18,8 @@ | |||
| 18 | * field correctly */ | 18 | * field correctly */ |
| 19 | extern unsigned long __toc_start; | 19 | extern unsigned long __toc_start; |
| 20 | 20 | ||
| 21 | #ifdef CONFIG_PPC_BOOK3S | ||
| 22 | |||
| 21 | /* | 23 | /* |
| 22 | * The structure which the hypervisor knows about - this structure | 24 | * The structure which the hypervisor knows about - this structure |
| 23 | * should not cross a page boundary. The vpa_init/register_vpa call | 25 | * should not cross a page boundary. The vpa_init/register_vpa call |
| @@ -41,6 +43,10 @@ struct lppaca lppaca[] = { | |||
| 41 | }, | 43 | }, |
| 42 | }; | 44 | }; |
| 43 | 45 | ||
| 46 | #endif /* CONFIG_PPC_BOOK3S */ | ||
| 47 | |||
| 48 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 49 | |||
| 44 | /* | 50 | /* |
| 45 | * 3 persistent SLBs are registered here. The buffer will be zero | 51 | * 3 persistent SLBs are registered here. The buffer will be zero |
| 46 | * initially, hence will all be invaild until we actually write them. | 52 | * initially, hence will all be invaild until we actually write them. |
| @@ -52,6 +58,8 @@ struct slb_shadow slb_shadow[] __cacheline_aligned = { | |||
| 52 | }, | 58 | }, |
| 53 | }; | 59 | }; |
| 54 | 60 | ||
| 61 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 62 | |||
| 55 | /* The Paca is an array with one entry per processor. Each contains an | 63 | /* The Paca is an array with one entry per processor. Each contains an |
| 56 | * lppaca, which contains the information shared between the | 64 | * lppaca, which contains the information shared between the |
| 57 | * hypervisor and Linux. | 65 | * hypervisor and Linux. |
| @@ -77,15 +85,19 @@ void __init initialise_pacas(void) | |||
| 77 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | 85 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
| 78 | struct paca_struct *new_paca = &paca[cpu]; | 86 | struct paca_struct *new_paca = &paca[cpu]; |
| 79 | 87 | ||
| 88 | #ifdef CONFIG_PPC_BOOK3S | ||
| 80 | new_paca->lppaca_ptr = &lppaca[cpu]; | 89 | new_paca->lppaca_ptr = &lppaca[cpu]; |
| 90 | #endif | ||
| 81 | new_paca->lock_token = 0x8000; | 91 | new_paca->lock_token = 0x8000; |
| 82 | new_paca->paca_index = cpu; | 92 | new_paca->paca_index = cpu; |
| 83 | new_paca->kernel_toc = kernel_toc; | 93 | new_paca->kernel_toc = kernel_toc; |
| 84 | new_paca->kernelbase = (unsigned long) _stext; | 94 | new_paca->kernelbase = (unsigned long) _stext; |
| 85 | new_paca->kernel_msr = MSR_KERNEL; | 95 | new_paca->kernel_msr = MSR_KERNEL; |
| 86 | new_paca->hw_cpu_id = 0xffff; | 96 | new_paca->hw_cpu_id = 0xffff; |
| 87 | new_paca->slb_shadow_ptr = &slb_shadow[cpu]; | ||
| 88 | new_paca->__current = &init_task; | 97 | new_paca->__current = &init_task; |
| 98 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 99 | new_paca->slb_shadow_ptr = &slb_shadow[cpu]; | ||
| 100 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 89 | 101 | ||
| 90 | } | 102 | } |
| 91 | } | 103 | } |
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 4fee63cb53ff..5a56e97c5ac0 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c | |||
| @@ -1505,7 +1505,7 @@ void __init pcibios_resource_survey(void) | |||
| 1505 | * rest of the code later, for now, keep it as-is as our main | 1505 | * rest of the code later, for now, keep it as-is as our main |
| 1506 | * resource allocation function doesn't deal with sub-trees yet. | 1506 | * resource allocation function doesn't deal with sub-trees yet. |
| 1507 | */ | 1507 | */ |
| 1508 | void __devinit pcibios_claim_one_bus(struct pci_bus *bus) | 1508 | void pcibios_claim_one_bus(struct pci_bus *bus) |
| 1509 | { | 1509 | { |
| 1510 | struct pci_dev *dev; | 1510 | struct pci_dev *dev; |
| 1511 | struct pci_bus *child_bus; | 1511 | struct pci_bus *child_bus; |
| @@ -1533,7 +1533,6 @@ void __devinit pcibios_claim_one_bus(struct pci_bus *bus) | |||
| 1533 | list_for_each_entry(child_bus, &bus->children, node) | 1533 | list_for_each_entry(child_bus, &bus->children, node) |
| 1534 | pcibios_claim_one_bus(child_bus); | 1534 | pcibios_claim_one_bus(child_bus); |
| 1535 | } | 1535 | } |
| 1536 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | ||
| 1537 | 1536 | ||
| 1538 | 1537 | ||
| 1539 | /* pcibios_finish_adding_to_bus | 1538 | /* pcibios_finish_adding_to_bus |
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c index d473634e39e3..3ae1c666ff92 100644 --- a/arch/powerpc/kernel/pci_32.c +++ b/arch/powerpc/kernel/pci_32.c | |||
| @@ -33,7 +33,6 @@ int pcibios_assign_bus_offset = 1; | |||
| 33 | 33 | ||
| 34 | void pcibios_make_OF_bus_map(void); | 34 | void pcibios_make_OF_bus_map(void); |
| 35 | 35 | ||
| 36 | static void fixup_broken_pcnet32(struct pci_dev* dev); | ||
| 37 | static void fixup_cpc710_pci64(struct pci_dev* dev); | 36 | static void fixup_cpc710_pci64(struct pci_dev* dev); |
| 38 | #ifdef CONFIG_PPC_OF | 37 | #ifdef CONFIG_PPC_OF |
| 39 | static u8* pci_to_OF_bus_map; | 38 | static u8* pci_to_OF_bus_map; |
| @@ -72,16 +71,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_res | |||
| 72 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | 71 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); |
| 73 | 72 | ||
| 74 | static void | 73 | static void |
| 75 | fixup_broken_pcnet32(struct pci_dev* dev) | ||
| 76 | { | ||
| 77 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | ||
| 78 | dev->vendor = PCI_VENDOR_ID_AMD; | ||
| 79 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | ||
| 80 | } | ||
| 81 | } | ||
| 82 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | ||
| 83 | |||
| 84 | static void | ||
| 85 | fixup_cpc710_pci64(struct pci_dev* dev) | 74 | fixup_cpc710_pci64(struct pci_dev* dev) |
| 86 | { | 75 | { |
| 87 | /* Hide the PCI64 BARs from the kernel as their content doesn't | 76 | /* Hide the PCI64 BARs from the kernel as their content doesn't |
| @@ -447,14 +436,6 @@ static int __init pcibios_init(void) | |||
| 447 | 436 | ||
| 448 | subsys_initcall(pcibios_init); | 437 | subsys_initcall(pcibios_init); |
| 449 | 438 | ||
| 450 | /* the next one is stolen from the alpha port... */ | ||
| 451 | void __init | ||
| 452 | pcibios_update_irq(struct pci_dev *dev, int irq) | ||
| 453 | { | ||
| 454 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | ||
| 455 | /* XXX FIXME - update OF device tree node interrupt property */ | ||
| 456 | } | ||
| 457 | |||
| 458 | static struct pci_controller* | 439 | static struct pci_controller* |
| 459 | pci_bus_to_hose(int bus) | 440 | pci_bus_to_hose(int bus) |
| 460 | { | 441 | { |
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index 96edb6f8babb..9e8902fa14c7 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c | |||
| @@ -43,16 +43,6 @@ unsigned long pci_probe_only = 1; | |||
| 43 | unsigned long pci_io_base = ISA_IO_BASE; | 43 | unsigned long pci_io_base = ISA_IO_BASE; |
| 44 | EXPORT_SYMBOL(pci_io_base); | 44 | EXPORT_SYMBOL(pci_io_base); |
| 45 | 45 | ||
| 46 | static void fixup_broken_pcnet32(struct pci_dev* dev) | ||
| 47 | { | ||
| 48 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | ||
| 49 | dev->vendor = PCI_VENDOR_ID_AMD; | ||
| 50 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | ||
| 51 | } | ||
| 52 | } | ||
| 53 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | ||
| 54 | |||
| 55 | |||
| 56 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) | 46 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) |
| 57 | { | 47 | { |
| 58 | const u32 *prop; | 48 | const u32 *prop; |
| @@ -430,6 +420,9 @@ int pcibios_unmap_io_space(struct pci_bus *bus) | |||
| 430 | * so flushing the hash table is the only sane way to make sure | 420 | * so flushing the hash table is the only sane way to make sure |
| 431 | * that no hash entries are covering that removed bridge area | 421 | * that no hash entries are covering that removed bridge area |
| 432 | * while still allowing other busses overlapping those pages | 422 | * while still allowing other busses overlapping those pages |
| 423 | * | ||
| 424 | * Note: If we ever support P2P hotplug on Book3E, we'll have | ||
| 425 | * to do an appropriate TLB flush here too | ||
| 433 | */ | 426 | */ |
| 434 | if (bus->self) { | 427 | if (bus->self) { |
| 435 | struct resource *res = bus->resource[0]; | 428 | struct resource *res = bus->resource[0]; |
| @@ -437,8 +430,10 @@ int pcibios_unmap_io_space(struct pci_bus *bus) | |||
| 437 | pr_debug("IO unmapping for PCI-PCI bridge %s\n", | 430 | pr_debug("IO unmapping for PCI-PCI bridge %s\n", |
| 438 | pci_name(bus->self)); | 431 | pci_name(bus->self)); |
| 439 | 432 | ||
| 433 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 440 | __flush_hash_table_range(&init_mm, res->start + _IO_BASE, | 434 | __flush_hash_table_range(&init_mm, res->start + _IO_BASE, |
| 441 | res->end + _IO_BASE + 1); | 435 | res->end + _IO_BASE + 1); |
| 436 | #endif | ||
| 442 | return 0; | 437 | return 0; |
| 443 | } | 438 | } |
| 444 | 439 | ||
| @@ -511,7 +506,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus) | |||
| 511 | pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); | 506 | pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); |
| 512 | pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", | 507 | pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", |
| 513 | hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); | 508 | hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); |
| 514 | pr_debug(" size=0x%016lx (alloc=0x%016lx)\n", | 509 | pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", |
| 515 | hose->pci_io_size, size_page); | 510 | hose->pci_io_size, size_page); |
| 516 | 511 | ||
| 517 | /* Establish the mapping */ | 512 | /* Establish the mapping */ |
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c index 1c67de52e3ce..d5e36e5dc7c2 100644 --- a/arch/powerpc/kernel/pci_dn.c +++ b/arch/powerpc/kernel/pci_dn.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <asm/io.h> | 27 | #include <asm/io.h> |
| 28 | #include <asm/prom.h> | 28 | #include <asm/prom.h> |
| 29 | #include <asm/pci-bridge.h> | 29 | #include <asm/pci-bridge.h> |
| 30 | #include <asm/pSeries_reconfig.h> | ||
| 31 | #include <asm/ppc-pci.h> | 30 | #include <asm/ppc-pci.h> |
| 32 | #include <asm/firmware.h> | 31 | #include <asm/firmware.h> |
| 33 | 32 | ||
| @@ -35,7 +34,7 @@ | |||
| 35 | * Traverse_func that inits the PCI fields of the device node. | 34 | * Traverse_func that inits the PCI fields of the device node. |
| 36 | * NOTE: this *must* be done before read/write config to the device. | 35 | * NOTE: this *must* be done before read/write config to the device. |
| 37 | */ | 36 | */ |
| 38 | static void * __devinit update_dn_pci_info(struct device_node *dn, void *data) | 37 | void * __devinit update_dn_pci_info(struct device_node *dn, void *data) |
| 39 | { | 38 | { |
| 40 | struct pci_controller *phb = data; | 39 | struct pci_controller *phb = data; |
| 41 | const int *type = | 40 | const int *type = |
| @@ -184,29 +183,6 @@ struct device_node *fetch_dev_dn(struct pci_dev *dev) | |||
| 184 | } | 183 | } |
| 185 | EXPORT_SYMBOL(fetch_dev_dn); | 184 | EXPORT_SYMBOL(fetch_dev_dn); |
| 186 | 185 | ||
| 187 | static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | ||
| 188 | { | ||
| 189 | struct device_node *np = node; | ||
| 190 | struct pci_dn *pci = NULL; | ||
| 191 | int err = NOTIFY_OK; | ||
| 192 | |||
| 193 | switch (action) { | ||
| 194 | case PSERIES_RECONFIG_ADD: | ||
| 195 | pci = np->parent->data; | ||
| 196 | if (pci) | ||
| 197 | update_dn_pci_info(np, pci->phb); | ||
| 198 | break; | ||
| 199 | default: | ||
| 200 | err = NOTIFY_DONE; | ||
| 201 | break; | ||
| 202 | } | ||
| 203 | return err; | ||
| 204 | } | ||
| 205 | |||
| 206 | static struct notifier_block pci_dn_reconfig_nb = { | ||
| 207 | .notifier_call = pci_dn_reconfig_notifier, | ||
| 208 | }; | ||
| 209 | |||
| 210 | /** | 186 | /** |
| 211 | * pci_devs_phb_init - Initialize phbs and pci devs under them. | 187 | * pci_devs_phb_init - Initialize phbs and pci devs under them. |
| 212 | * | 188 | * |
| @@ -223,6 +199,4 @@ void __init pci_devs_phb_init(void) | |||
| 223 | /* This must be done first so the device nodes have valid pci info! */ | 199 | /* This must be done first so the device nodes have valid pci info! */ |
| 224 | list_for_each_entry_safe(phb, tmp, &hose_list, list_node) | 200 | list_for_each_entry_safe(phb, tmp, &hose_list, list_node) |
| 225 | pci_devs_phb_init_dynamic(phb); | 201 | pci_devs_phb_init_dynamic(phb); |
| 226 | |||
| 227 | pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb); | ||
| 228 | } | 202 | } |
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c new file mode 100644 index 000000000000..809fdf94b95f --- /dev/null +++ b/arch/powerpc/kernel/perf_counter.c | |||
| @@ -0,0 +1,1306 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support - powerpc architecture code | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <linux/perf_counter.h> | ||
| 14 | #include <linux/percpu.h> | ||
| 15 | #include <linux/hardirq.h> | ||
| 16 | #include <asm/reg.h> | ||
| 17 | #include <asm/pmc.h> | ||
| 18 | #include <asm/machdep.h> | ||
| 19 | #include <asm/firmware.h> | ||
| 20 | #include <asm/ptrace.h> | ||
| 21 | |||
| 22 | struct cpu_hw_counters { | ||
| 23 | int n_counters; | ||
| 24 | int n_percpu; | ||
| 25 | int disabled; | ||
| 26 | int n_added; | ||
| 27 | int n_limited; | ||
| 28 | u8 pmcs_enabled; | ||
| 29 | struct perf_counter *counter[MAX_HWCOUNTERS]; | ||
| 30 | u64 events[MAX_HWCOUNTERS]; | ||
| 31 | unsigned int flags[MAX_HWCOUNTERS]; | ||
| 32 | unsigned long mmcr[3]; | ||
| 33 | struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; | ||
| 34 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | ||
| 35 | }; | ||
| 36 | DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); | ||
| 37 | |||
| 38 | struct power_pmu *ppmu; | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Normally, to ignore kernel events we set the FCS (freeze counters | ||
| 42 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the | ||
| 43 | * hypervisor bit set in the MSR, or if we are running on a processor | ||
| 44 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | ||
| 45 | * then we need to use the FCHV bit to ignore kernel events. | ||
| 46 | */ | ||
| 47 | static unsigned int freeze_counters_kernel = MMCR0_FCS; | ||
| 48 | |||
| 49 | /* | ||
| 50 | * 32-bit doesn't have MMCRA but does have an MMCR2, | ||
| 51 | * and a few other names are different. | ||
| 52 | */ | ||
| 53 | #ifdef CONFIG_PPC32 | ||
| 54 | |||
| 55 | #define MMCR0_FCHV 0 | ||
| 56 | #define MMCR0_PMCjCE MMCR0_PMCnCE | ||
| 57 | |||
| 58 | #define SPRN_MMCRA SPRN_MMCR2 | ||
| 59 | #define MMCRA_SAMPLE_ENABLE 0 | ||
| 60 | |||
| 61 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | ||
| 62 | { | ||
| 63 | return 0; | ||
| 64 | } | ||
| 65 | static inline void perf_set_pmu_inuse(int inuse) { } | ||
| 66 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } | ||
| 67 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | ||
| 68 | { | ||
| 69 | return 0; | ||
| 70 | } | ||
| 71 | static inline void perf_read_regs(struct pt_regs *regs) { } | ||
| 72 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | ||
| 73 | { | ||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | |||
| 77 | #endif /* CONFIG_PPC32 */ | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Things that are specific to 64-bit implementations. | ||
| 81 | */ | ||
| 82 | #ifdef CONFIG_PPC64 | ||
| 83 | |||
| 84 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | ||
| 85 | { | ||
| 86 | unsigned long mmcra = regs->dsisr; | ||
| 87 | |||
| 88 | if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { | ||
| 89 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; | ||
| 90 | if (slot > 1) | ||
| 91 | return 4 * (slot - 1); | ||
| 92 | } | ||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline void perf_set_pmu_inuse(int inuse) | ||
| 97 | { | ||
| 98 | get_lppaca()->pmcregs_in_use = inuse; | ||
| 99 | } | ||
| 100 | |||
| 101 | /* | ||
| 102 | * The user wants a data address recorded. | ||
| 103 | * If we're not doing instruction sampling, give them the SDAR | ||
| 104 | * (sampled data address). If we are doing instruction sampling, then | ||
| 105 | * only give them the SDAR if it corresponds to the instruction | ||
| 106 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC | ||
| 107 | * bit in MMCRA. | ||
| 108 | */ | ||
| 109 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | ||
| 110 | { | ||
| 111 | unsigned long mmcra = regs->dsisr; | ||
| 112 | unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? | ||
| 113 | POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; | ||
| 114 | |||
| 115 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | ||
| 116 | *addrp = mfspr(SPRN_SDAR); | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | ||
| 120 | { | ||
| 121 | unsigned long mmcra = regs->dsisr; | ||
| 122 | |||
| 123 | if (TRAP(regs) != 0xf00) | ||
| 124 | return 0; /* not a PMU interrupt */ | ||
| 125 | |||
| 126 | if (ppmu->flags & PPMU_ALT_SIPR) { | ||
| 127 | if (mmcra & POWER6_MMCRA_SIHV) | ||
| 128 | return PERF_EVENT_MISC_HYPERVISOR; | ||
| 129 | return (mmcra & POWER6_MMCRA_SIPR) ? | ||
| 130 | PERF_EVENT_MISC_USER : PERF_EVENT_MISC_KERNEL; | ||
| 131 | } | ||
| 132 | if (mmcra & MMCRA_SIHV) | ||
| 133 | return PERF_EVENT_MISC_HYPERVISOR; | ||
| 134 | return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER : | ||
| 135 | PERF_EVENT_MISC_KERNEL; | ||
| 136 | } | ||
| 137 | |||
| 138 | /* | ||
| 139 | * Overload regs->dsisr to store MMCRA so we only need to read it once | ||
| 140 | * on each interrupt. | ||
| 141 | */ | ||
| 142 | static inline void perf_read_regs(struct pt_regs *regs) | ||
| 143 | { | ||
| 144 | regs->dsisr = mfspr(SPRN_MMCRA); | ||
| 145 | } | ||
| 146 | |||
| 147 | /* | ||
| 148 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | ||
| 149 | * it as an NMI. | ||
| 150 | */ | ||
| 151 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | ||
| 152 | { | ||
| 153 | return !regs->softe; | ||
| 154 | } | ||
| 155 | |||
| 156 | #endif /* CONFIG_PPC64 */ | ||
| 157 | |||
| 158 | static void perf_counter_interrupt(struct pt_regs *regs); | ||
| 159 | |||
| 160 | void perf_counter_print_debug(void) | ||
| 161 | { | ||
| 162 | } | ||
| 163 | |||
| 164 | /* | ||
| 165 | * Read one performance monitor counter (PMC). | ||
| 166 | */ | ||
| 167 | static unsigned long read_pmc(int idx) | ||
| 168 | { | ||
| 169 | unsigned long val; | ||
| 170 | |||
| 171 | switch (idx) { | ||
| 172 | case 1: | ||
| 173 | val = mfspr(SPRN_PMC1); | ||
| 174 | break; | ||
| 175 | case 2: | ||
| 176 | val = mfspr(SPRN_PMC2); | ||
| 177 | break; | ||
| 178 | case 3: | ||
| 179 | val = mfspr(SPRN_PMC3); | ||
| 180 | break; | ||
| 181 | case 4: | ||
| 182 | val = mfspr(SPRN_PMC4); | ||
| 183 | break; | ||
| 184 | case 5: | ||
| 185 | val = mfspr(SPRN_PMC5); | ||
| 186 | break; | ||
| 187 | case 6: | ||
| 188 | val = mfspr(SPRN_PMC6); | ||
| 189 | break; | ||
| 190 | #ifdef CONFIG_PPC64 | ||
| 191 | case 7: | ||
| 192 | val = mfspr(SPRN_PMC7); | ||
| 193 | break; | ||
| 194 | case 8: | ||
| 195 | val = mfspr(SPRN_PMC8); | ||
| 196 | break; | ||
| 197 | #endif /* CONFIG_PPC64 */ | ||
| 198 | default: | ||
| 199 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | ||
| 200 | val = 0; | ||
| 201 | } | ||
| 202 | return val; | ||
| 203 | } | ||
| 204 | |||
| 205 | /* | ||
| 206 | * Write one PMC. | ||
| 207 | */ | ||
| 208 | static void write_pmc(int idx, unsigned long val) | ||
| 209 | { | ||
| 210 | switch (idx) { | ||
| 211 | case 1: | ||
| 212 | mtspr(SPRN_PMC1, val); | ||
| 213 | break; | ||
| 214 | case 2: | ||
| 215 | mtspr(SPRN_PMC2, val); | ||
| 216 | break; | ||
| 217 | case 3: | ||
| 218 | mtspr(SPRN_PMC3, val); | ||
| 219 | break; | ||
| 220 | case 4: | ||
| 221 | mtspr(SPRN_PMC4, val); | ||
| 222 | break; | ||
| 223 | case 5: | ||
| 224 | mtspr(SPRN_PMC5, val); | ||
| 225 | break; | ||
| 226 | case 6: | ||
| 227 | mtspr(SPRN_PMC6, val); | ||
| 228 | break; | ||
| 229 | #ifdef CONFIG_PPC64 | ||
| 230 | case 7: | ||
| 231 | mtspr(SPRN_PMC7, val); | ||
| 232 | break; | ||
| 233 | case 8: | ||
| 234 | mtspr(SPRN_PMC8, val); | ||
| 235 | break; | ||
| 236 | #endif /* CONFIG_PPC64 */ | ||
| 237 | default: | ||
| 238 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | ||
| 239 | } | ||
| 240 | } | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Check if a set of events can all go on the PMU at once. | ||
| 244 | * If they can't, this will look at alternative codes for the events | ||
| 245 | * and see if any combination of alternative codes is feasible. | ||
| 246 | * The feasible set is returned in event[]. | ||
| 247 | */ | ||
| 248 | static int power_check_constraints(u64 event[], unsigned int cflags[], | ||
| 249 | int n_ev) | ||
| 250 | { | ||
| 251 | unsigned long mask, value, nv; | ||
| 252 | u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; | ||
| 253 | unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; | ||
| 254 | unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; | ||
| 255 | unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; | ||
| 256 | int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; | ||
| 257 | int i, j; | ||
| 258 | unsigned long addf = ppmu->add_fields; | ||
| 259 | unsigned long tadd = ppmu->test_adder; | ||
| 260 | |||
| 261 | if (n_ev > ppmu->n_counter) | ||
| 262 | return -1; | ||
| 263 | |||
| 264 | /* First see if the events will go on as-is */ | ||
| 265 | for (i = 0; i < n_ev; ++i) { | ||
| 266 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) | ||
| 267 | && !ppmu->limited_pmc_event(event[i])) { | ||
| 268 | ppmu->get_alternatives(event[i], cflags[i], | ||
| 269 | alternatives[i]); | ||
| 270 | event[i] = alternatives[i][0]; | ||
| 271 | } | ||
| 272 | if (ppmu->get_constraint(event[i], &amasks[i][0], | ||
| 273 | &avalues[i][0])) | ||
| 274 | return -1; | ||
| 275 | } | ||
| 276 | value = mask = 0; | ||
| 277 | for (i = 0; i < n_ev; ++i) { | ||
| 278 | nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf); | ||
| 279 | if ((((nv + tadd) ^ value) & mask) != 0 || | ||
| 280 | (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0) | ||
| 281 | break; | ||
| 282 | value = nv; | ||
| 283 | mask |= amasks[i][0]; | ||
| 284 | } | ||
| 285 | if (i == n_ev) | ||
| 286 | return 0; /* all OK */ | ||
| 287 | |||
| 288 | /* doesn't work, gather alternatives... */ | ||
| 289 | if (!ppmu->get_alternatives) | ||
| 290 | return -1; | ||
| 291 | for (i = 0; i < n_ev; ++i) { | ||
| 292 | choice[i] = 0; | ||
| 293 | n_alt[i] = ppmu->get_alternatives(event[i], cflags[i], | ||
| 294 | alternatives[i]); | ||
| 295 | for (j = 1; j < n_alt[i]; ++j) | ||
| 296 | ppmu->get_constraint(alternatives[i][j], | ||
| 297 | &amasks[i][j], &avalues[i][j]); | ||
| 298 | } | ||
| 299 | |||
| 300 | /* enumerate all possibilities and see if any will work */ | ||
| 301 | i = 0; | ||
| 302 | j = -1; | ||
| 303 | value = mask = nv = 0; | ||
| 304 | while (i < n_ev) { | ||
| 305 | if (j >= 0) { | ||
| 306 | /* we're backtracking, restore context */ | ||
| 307 | value = svalues[i]; | ||
| 308 | mask = smasks[i]; | ||
| 309 | j = choice[i]; | ||
| 310 | } | ||
| 311 | /* | ||
| 312 | * See if any alternative k for event i, | ||
| 313 | * where k > j, will satisfy the constraints. | ||
| 314 | */ | ||
| 315 | while (++j < n_alt[i]) { | ||
| 316 | nv = (value | avalues[i][j]) + | ||
| 317 | (value & avalues[i][j] & addf); | ||
| 318 | if ((((nv + tadd) ^ value) & mask) == 0 && | ||
| 319 | (((nv + tadd) ^ avalues[i][j]) | ||
| 320 | & amasks[i][j]) == 0) | ||
| 321 | break; | ||
| 322 | } | ||
| 323 | if (j >= n_alt[i]) { | ||
| 324 | /* | ||
| 325 | * No feasible alternative, backtrack | ||
| 326 | * to event i-1 and continue enumerating its | ||
| 327 | * alternatives from where we got up to. | ||
| 328 | */ | ||
| 329 | if (--i < 0) | ||
| 330 | return -1; | ||
| 331 | } else { | ||
| 332 | /* | ||
| 333 | * Found a feasible alternative for event i, | ||
| 334 | * remember where we got up to with this event, | ||
| 335 | * go on to the next event, and start with | ||
| 336 | * the first alternative for it. | ||
| 337 | */ | ||
| 338 | choice[i] = j; | ||
| 339 | svalues[i] = value; | ||
| 340 | smasks[i] = mask; | ||
| 341 | value = nv; | ||
| 342 | mask |= amasks[i][j]; | ||
| 343 | ++i; | ||
| 344 | j = -1; | ||
| 345 | } | ||
| 346 | } | ||
| 347 | |||
| 348 | /* OK, we have a feasible combination, tell the caller the solution */ | ||
| 349 | for (i = 0; i < n_ev; ++i) | ||
| 350 | event[i] = alternatives[i][choice[i]]; | ||
| 351 | return 0; | ||
| 352 | } | ||
| 353 | |||
| 354 | /* | ||
| 355 | * Check if newly-added counters have consistent settings for | ||
| 356 | * exclude_{user,kernel,hv} with each other and any previously | ||
| 357 | * added counters. | ||
| 358 | */ | ||
| 359 | static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[], | ||
| 360 | int n_prev, int n_new) | ||
| 361 | { | ||
| 362 | int eu = 0, ek = 0, eh = 0; | ||
| 363 | int i, n, first; | ||
| 364 | struct perf_counter *counter; | ||
| 365 | |||
| 366 | n = n_prev + n_new; | ||
| 367 | if (n <= 1) | ||
| 368 | return 0; | ||
| 369 | |||
| 370 | first = 1; | ||
| 371 | for (i = 0; i < n; ++i) { | ||
| 372 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | ||
| 373 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | ||
| 374 | continue; | ||
| 375 | } | ||
| 376 | counter = ctrs[i]; | ||
| 377 | if (first) { | ||
| 378 | eu = counter->attr.exclude_user; | ||
| 379 | ek = counter->attr.exclude_kernel; | ||
| 380 | eh = counter->attr.exclude_hv; | ||
| 381 | first = 0; | ||
| 382 | } else if (counter->attr.exclude_user != eu || | ||
| 383 | counter->attr.exclude_kernel != ek || | ||
| 384 | counter->attr.exclude_hv != eh) { | ||
| 385 | return -EAGAIN; | ||
| 386 | } | ||
| 387 | } | ||
| 388 | |||
| 389 | if (eu || ek || eh) | ||
| 390 | for (i = 0; i < n; ++i) | ||
| 391 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | ||
| 392 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | ||
| 393 | |||
| 394 | return 0; | ||
| 395 | } | ||
| 396 | |||
| 397 | static void power_pmu_read(struct perf_counter *counter) | ||
| 398 | { | ||
| 399 | s64 val, delta, prev; | ||
| 400 | |||
| 401 | if (!counter->hw.idx) | ||
| 402 | return; | ||
| 403 | /* | ||
| 404 | * Performance monitor interrupts come even when interrupts | ||
| 405 | * are soft-disabled, as long as interrupts are hard-enabled. | ||
| 406 | * Therefore we treat them like NMIs. | ||
| 407 | */ | ||
| 408 | do { | ||
| 409 | prev = atomic64_read(&counter->hw.prev_count); | ||
| 410 | barrier(); | ||
| 411 | val = read_pmc(counter->hw.idx); | ||
| 412 | } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev); | ||
| 413 | |||
| 414 | /* The counters are only 32 bits wide */ | ||
| 415 | delta = (val - prev) & 0xfffffffful; | ||
| 416 | atomic64_add(delta, &counter->count); | ||
| 417 | atomic64_sub(delta, &counter->hw.period_left); | ||
| 418 | } | ||
| 419 | |||
| 420 | /* | ||
| 421 | * On some machines, PMC5 and PMC6 can't be written, don't respect | ||
| 422 | * the freeze conditions, and don't generate interrupts. This tells | ||
| 423 | * us if `counter' is using such a PMC. | ||
| 424 | */ | ||
| 425 | static int is_limited_pmc(int pmcnum) | ||
| 426 | { | ||
| 427 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) | ||
| 428 | && (pmcnum == 5 || pmcnum == 6); | ||
| 429 | } | ||
| 430 | |||
| 431 | static void freeze_limited_counters(struct cpu_hw_counters *cpuhw, | ||
| 432 | unsigned long pmc5, unsigned long pmc6) | ||
| 433 | { | ||
| 434 | struct perf_counter *counter; | ||
| 435 | u64 val, prev, delta; | ||
| 436 | int i; | ||
| 437 | |||
| 438 | for (i = 0; i < cpuhw->n_limited; ++i) { | ||
| 439 | counter = cpuhw->limited_counter[i]; | ||
| 440 | if (!counter->hw.idx) | ||
| 441 | continue; | ||
| 442 | val = (counter->hw.idx == 5) ? pmc5 : pmc6; | ||
| 443 | prev = atomic64_read(&counter->hw.prev_count); | ||
| 444 | counter->hw.idx = 0; | ||
| 445 | delta = (val - prev) & 0xfffffffful; | ||
| 446 | atomic64_add(delta, &counter->count); | ||
| 447 | } | ||
| 448 | } | ||
| 449 | |||
| 450 | static void thaw_limited_counters(struct cpu_hw_counters *cpuhw, | ||
| 451 | unsigned long pmc5, unsigned long pmc6) | ||
| 452 | { | ||
| 453 | struct perf_counter *counter; | ||
| 454 | u64 val; | ||
| 455 | int i; | ||
| 456 | |||
| 457 | for (i = 0; i < cpuhw->n_limited; ++i) { | ||
| 458 | counter = cpuhw->limited_counter[i]; | ||
| 459 | counter->hw.idx = cpuhw->limited_hwidx[i]; | ||
| 460 | val = (counter->hw.idx == 5) ? pmc5 : pmc6; | ||
| 461 | atomic64_set(&counter->hw.prev_count, val); | ||
| 462 | perf_counter_update_userpage(counter); | ||
| 463 | } | ||
| 464 | } | ||
| 465 | |||
| 466 | /* | ||
| 467 | * Since limited counters don't respect the freeze conditions, we | ||
| 468 | * have to read them immediately after freezing or unfreezing the | ||
| 469 | * other counters. We try to keep the values from the limited | ||
| 470 | * counters as consistent as possible by keeping the delay (in | ||
| 471 | * cycles and instructions) between freezing/unfreezing and reading | ||
| 472 | * the limited counters as small and consistent as possible. | ||
| 473 | * Therefore, if any limited counters are in use, we read them | ||
| 474 | * both, and always in the same order, to minimize variability, | ||
| 475 | * and do it inside the same asm that writes MMCR0. | ||
| 476 | */ | ||
| 477 | static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) | ||
| 478 | { | ||
| 479 | unsigned long pmc5, pmc6; | ||
| 480 | |||
| 481 | if (!cpuhw->n_limited) { | ||
| 482 | mtspr(SPRN_MMCR0, mmcr0); | ||
| 483 | return; | ||
| 484 | } | ||
| 485 | |||
| 486 | /* | ||
| 487 | * Write MMCR0, then read PMC5 and PMC6 immediately. | ||
| 488 | * To ensure we don't get a performance monitor interrupt | ||
| 489 | * between writing MMCR0 and freezing/thawing the limited | ||
| 490 | * counters, we first write MMCR0 with the counter overflow | ||
| 491 | * interrupt enable bits turned off. | ||
| 492 | */ | ||
| 493 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | ||
| 494 | : "=&r" (pmc5), "=&r" (pmc6) | ||
| 495 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), | ||
| 496 | "i" (SPRN_MMCR0), | ||
| 497 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); | ||
| 498 | |||
| 499 | if (mmcr0 & MMCR0_FC) | ||
| 500 | freeze_limited_counters(cpuhw, pmc5, pmc6); | ||
| 501 | else | ||
| 502 | thaw_limited_counters(cpuhw, pmc5, pmc6); | ||
| 503 | |||
| 504 | /* | ||
| 505 | * Write the full MMCR0 including the counter overflow interrupt | ||
| 506 | * enable bits, if necessary. | ||
| 507 | */ | ||
| 508 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | ||
| 509 | mtspr(SPRN_MMCR0, mmcr0); | ||
| 510 | } | ||
| 511 | |||
| 512 | /* | ||
| 513 | * Disable all counters to prevent PMU interrupts and to allow | ||
| 514 | * counters to be added or removed. | ||
| 515 | */ | ||
| 516 | void hw_perf_disable(void) | ||
| 517 | { | ||
| 518 | struct cpu_hw_counters *cpuhw; | ||
| 519 | unsigned long flags; | ||
| 520 | |||
| 521 | local_irq_save(flags); | ||
| 522 | cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 523 | |||
| 524 | if (!cpuhw->disabled) { | ||
| 525 | cpuhw->disabled = 1; | ||
| 526 | cpuhw->n_added = 0; | ||
| 527 | |||
| 528 | /* | ||
| 529 | * Check if we ever enabled the PMU on this cpu. | ||
| 530 | */ | ||
| 531 | if (!cpuhw->pmcs_enabled) { | ||
| 532 | if (ppc_md.enable_pmcs) | ||
| 533 | ppc_md.enable_pmcs(); | ||
| 534 | cpuhw->pmcs_enabled = 1; | ||
| 535 | } | ||
| 536 | |||
| 537 | /* | ||
| 538 | * Disable instruction sampling if it was enabled | ||
| 539 | */ | ||
| 540 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | ||
| 541 | mtspr(SPRN_MMCRA, | ||
| 542 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | ||
| 543 | mb(); | ||
| 544 | } | ||
| 545 | |||
| 546 | /* | ||
| 547 | * Set the 'freeze counters' bit. | ||
| 548 | * The barrier is to make sure the mtspr has been | ||
| 549 | * executed and the PMU has frozen the counters | ||
| 550 | * before we return. | ||
| 551 | */ | ||
| 552 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); | ||
| 553 | mb(); | ||
| 554 | } | ||
| 555 | local_irq_restore(flags); | ||
| 556 | } | ||
| 557 | |||
| 558 | /* | ||
| 559 | * Re-enable all counters if disable == 0. | ||
| 560 | * If we were previously disabled and counters were added, then | ||
| 561 | * put the new config on the PMU. | ||
| 562 | */ | ||
| 563 | void hw_perf_enable(void) | ||
| 564 | { | ||
| 565 | struct perf_counter *counter; | ||
| 566 | struct cpu_hw_counters *cpuhw; | ||
| 567 | unsigned long flags; | ||
| 568 | long i; | ||
| 569 | unsigned long val; | ||
| 570 | s64 left; | ||
| 571 | unsigned int hwc_index[MAX_HWCOUNTERS]; | ||
| 572 | int n_lim; | ||
| 573 | int idx; | ||
| 574 | |||
| 575 | local_irq_save(flags); | ||
| 576 | cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 577 | if (!cpuhw->disabled) { | ||
| 578 | local_irq_restore(flags); | ||
| 579 | return; | ||
| 580 | } | ||
| 581 | cpuhw->disabled = 0; | ||
| 582 | |||
| 583 | /* | ||
| 584 | * If we didn't change anything, or only removed counters, | ||
| 585 | * no need to recalculate MMCR* settings and reset the PMCs. | ||
| 586 | * Just reenable the PMU with the current MMCR* settings | ||
| 587 | * (possibly updated for removal of counters). | ||
| 588 | */ | ||
| 589 | if (!cpuhw->n_added) { | ||
| 590 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | ||
| 591 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); | ||
| 592 | if (cpuhw->n_counters == 0) | ||
| 593 | perf_set_pmu_inuse(0); | ||
| 594 | goto out_enable; | ||
| 595 | } | ||
| 596 | |||
| 597 | /* | ||
| 598 | * Compute MMCR* values for the new set of counters | ||
| 599 | */ | ||
| 600 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index, | ||
| 601 | cpuhw->mmcr)) { | ||
| 602 | /* shouldn't ever get here */ | ||
| 603 | printk(KERN_ERR "oops compute_mmcr failed\n"); | ||
| 604 | goto out; | ||
| 605 | } | ||
| 606 | |||
| 607 | /* | ||
| 608 | * Add in MMCR0 freeze bits corresponding to the | ||
| 609 | * attr.exclude_* bits for the first counter. | ||
| 610 | * We have already checked that all counters have the | ||
| 611 | * same values for these bits as the first counter. | ||
| 612 | */ | ||
| 613 | counter = cpuhw->counter[0]; | ||
| 614 | if (counter->attr.exclude_user) | ||
| 615 | cpuhw->mmcr[0] |= MMCR0_FCP; | ||
| 616 | if (counter->attr.exclude_kernel) | ||
| 617 | cpuhw->mmcr[0] |= freeze_counters_kernel; | ||
| 618 | if (counter->attr.exclude_hv) | ||
| 619 | cpuhw->mmcr[0] |= MMCR0_FCHV; | ||
| 620 | |||
| 621 | /* | ||
| 622 | * Write the new configuration to MMCR* with the freeze | ||
| 623 | * bit set and set the hardware counters to their initial values. | ||
| 624 | * Then unfreeze the counters. | ||
| 625 | */ | ||
| 626 | perf_set_pmu_inuse(1); | ||
| 627 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | ||
| 628 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); | ||
| 629 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | ||
| 630 | | MMCR0_FC); | ||
| 631 | |||
| 632 | /* | ||
| 633 | * Read off any pre-existing counters that need to move | ||
| 634 | * to another PMC. | ||
| 635 | */ | ||
| 636 | for (i = 0; i < cpuhw->n_counters; ++i) { | ||
| 637 | counter = cpuhw->counter[i]; | ||
| 638 | if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) { | ||
| 639 | power_pmu_read(counter); | ||
| 640 | write_pmc(counter->hw.idx, 0); | ||
| 641 | counter->hw.idx = 0; | ||
| 642 | } | ||
| 643 | } | ||
| 644 | |||
| 645 | /* | ||
| 646 | * Initialize the PMCs for all the new and moved counters. | ||
| 647 | */ | ||
| 648 | cpuhw->n_limited = n_lim = 0; | ||
| 649 | for (i = 0; i < cpuhw->n_counters; ++i) { | ||
| 650 | counter = cpuhw->counter[i]; | ||
| 651 | if (counter->hw.idx) | ||
| 652 | continue; | ||
| 653 | idx = hwc_index[i] + 1; | ||
| 654 | if (is_limited_pmc(idx)) { | ||
| 655 | cpuhw->limited_counter[n_lim] = counter; | ||
| 656 | cpuhw->limited_hwidx[n_lim] = idx; | ||
| 657 | ++n_lim; | ||
| 658 | continue; | ||
| 659 | } | ||
| 660 | val = 0; | ||
| 661 | if (counter->hw.sample_period) { | ||
| 662 | left = atomic64_read(&counter->hw.period_left); | ||
| 663 | if (left < 0x80000000L) | ||
| 664 | val = 0x80000000L - left; | ||
| 665 | } | ||
| 666 | atomic64_set(&counter->hw.prev_count, val); | ||
| 667 | counter->hw.idx = idx; | ||
| 668 | write_pmc(idx, val); | ||
| 669 | perf_counter_update_userpage(counter); | ||
| 670 | } | ||
| 671 | cpuhw->n_limited = n_lim; | ||
| 672 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; | ||
| 673 | |||
| 674 | out_enable: | ||
| 675 | mb(); | ||
| 676 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); | ||
| 677 | |||
| 678 | /* | ||
| 679 | * Enable instruction sampling if necessary | ||
| 680 | */ | ||
| 681 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | ||
| 682 | mb(); | ||
| 683 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | ||
| 684 | } | ||
| 685 | |||
| 686 | out: | ||
| 687 | local_irq_restore(flags); | ||
| 688 | } | ||
| 689 | |||
| 690 | static int collect_events(struct perf_counter *group, int max_count, | ||
| 691 | struct perf_counter *ctrs[], u64 *events, | ||
| 692 | unsigned int *flags) | ||
| 693 | { | ||
| 694 | int n = 0; | ||
| 695 | struct perf_counter *counter; | ||
| 696 | |||
| 697 | if (!is_software_counter(group)) { | ||
| 698 | if (n >= max_count) | ||
| 699 | return -1; | ||
| 700 | ctrs[n] = group; | ||
| 701 | flags[n] = group->hw.counter_base; | ||
| 702 | events[n++] = group->hw.config; | ||
| 703 | } | ||
| 704 | list_for_each_entry(counter, &group->sibling_list, list_entry) { | ||
| 705 | if (!is_software_counter(counter) && | ||
| 706 | counter->state != PERF_COUNTER_STATE_OFF) { | ||
| 707 | if (n >= max_count) | ||
| 708 | return -1; | ||
| 709 | ctrs[n] = counter; | ||
| 710 | flags[n] = counter->hw.counter_base; | ||
| 711 | events[n++] = counter->hw.config; | ||
| 712 | } | ||
| 713 | } | ||
| 714 | return n; | ||
| 715 | } | ||
| 716 | |||
| 717 | static void counter_sched_in(struct perf_counter *counter, int cpu) | ||
| 718 | { | ||
| 719 | counter->state = PERF_COUNTER_STATE_ACTIVE; | ||
| 720 | counter->oncpu = cpu; | ||
| 721 | counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped; | ||
| 722 | if (is_software_counter(counter)) | ||
| 723 | counter->pmu->enable(counter); | ||
| 724 | } | ||
| 725 | |||
| 726 | /* | ||
| 727 | * Called to enable a whole group of counters. | ||
| 728 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. | ||
| 729 | * Assumes the caller has disabled interrupts and has | ||
| 730 | * frozen the PMU with hw_perf_save_disable. | ||
| 731 | */ | ||
| 732 | int hw_perf_group_sched_in(struct perf_counter *group_leader, | ||
| 733 | struct perf_cpu_context *cpuctx, | ||
| 734 | struct perf_counter_context *ctx, int cpu) | ||
| 735 | { | ||
| 736 | struct cpu_hw_counters *cpuhw; | ||
| 737 | long i, n, n0; | ||
| 738 | struct perf_counter *sub; | ||
| 739 | |||
| 740 | cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 741 | n0 = cpuhw->n_counters; | ||
| 742 | n = collect_events(group_leader, ppmu->n_counter - n0, | ||
| 743 | &cpuhw->counter[n0], &cpuhw->events[n0], | ||
| 744 | &cpuhw->flags[n0]); | ||
| 745 | if (n < 0) | ||
| 746 | return -EAGAIN; | ||
| 747 | if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n)) | ||
| 748 | return -EAGAIN; | ||
| 749 | i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0); | ||
| 750 | if (i < 0) | ||
| 751 | return -EAGAIN; | ||
| 752 | cpuhw->n_counters = n0 + n; | ||
| 753 | cpuhw->n_added += n; | ||
| 754 | |||
| 755 | /* | ||
| 756 | * OK, this group can go on; update counter states etc., | ||
| 757 | * and enable any software counters | ||
| 758 | */ | ||
| 759 | for (i = n0; i < n0 + n; ++i) | ||
| 760 | cpuhw->counter[i]->hw.config = cpuhw->events[i]; | ||
| 761 | cpuctx->active_oncpu += n; | ||
| 762 | n = 1; | ||
| 763 | counter_sched_in(group_leader, cpu); | ||
| 764 | list_for_each_entry(sub, &group_leader->sibling_list, list_entry) { | ||
| 765 | if (sub->state != PERF_COUNTER_STATE_OFF) { | ||
| 766 | counter_sched_in(sub, cpu); | ||
| 767 | ++n; | ||
| 768 | } | ||
| 769 | } | ||
| 770 | ctx->nr_active += n; | ||
| 771 | |||
| 772 | return 1; | ||
| 773 | } | ||
| 774 | |||
| 775 | /* | ||
| 776 | * Add a counter to the PMU. | ||
| 777 | * If all counters are not already frozen, then we disable and | ||
| 778 | * re-enable the PMU in order to get hw_perf_enable to do the | ||
| 779 | * actual work of reconfiguring the PMU. | ||
| 780 | */ | ||
| 781 | static int power_pmu_enable(struct perf_counter *counter) | ||
| 782 | { | ||
| 783 | struct cpu_hw_counters *cpuhw; | ||
| 784 | unsigned long flags; | ||
| 785 | int n0; | ||
| 786 | int ret = -EAGAIN; | ||
| 787 | |||
| 788 | local_irq_save(flags); | ||
| 789 | perf_disable(); | ||
| 790 | |||
| 791 | /* | ||
| 792 | * Add the counter to the list (if there is room) | ||
| 793 | * and check whether the total set is still feasible. | ||
| 794 | */ | ||
| 795 | cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 796 | n0 = cpuhw->n_counters; | ||
| 797 | if (n0 >= ppmu->n_counter) | ||
| 798 | goto out; | ||
| 799 | cpuhw->counter[n0] = counter; | ||
| 800 | cpuhw->events[n0] = counter->hw.config; | ||
| 801 | cpuhw->flags[n0] = counter->hw.counter_base; | ||
| 802 | if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1)) | ||
| 803 | goto out; | ||
| 804 | if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1)) | ||
| 805 | goto out; | ||
| 806 | |||
| 807 | counter->hw.config = cpuhw->events[n0]; | ||
| 808 | ++cpuhw->n_counters; | ||
| 809 | ++cpuhw->n_added; | ||
| 810 | |||
| 811 | ret = 0; | ||
| 812 | out: | ||
| 813 | perf_enable(); | ||
| 814 | local_irq_restore(flags); | ||
| 815 | return ret; | ||
| 816 | } | ||
| 817 | |||
| 818 | /* | ||
| 819 | * Remove a counter from the PMU. | ||
| 820 | */ | ||
| 821 | static void power_pmu_disable(struct perf_counter *counter) | ||
| 822 | { | ||
| 823 | struct cpu_hw_counters *cpuhw; | ||
| 824 | long i; | ||
| 825 | unsigned long flags; | ||
| 826 | |||
| 827 | local_irq_save(flags); | ||
| 828 | perf_disable(); | ||
| 829 | |||
| 830 | power_pmu_read(counter); | ||
| 831 | |||
| 832 | cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 833 | for (i = 0; i < cpuhw->n_counters; ++i) { | ||
| 834 | if (counter == cpuhw->counter[i]) { | ||
| 835 | while (++i < cpuhw->n_counters) | ||
| 836 | cpuhw->counter[i-1] = cpuhw->counter[i]; | ||
| 837 | --cpuhw->n_counters; | ||
| 838 | ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr); | ||
| 839 | if (counter->hw.idx) { | ||
| 840 | write_pmc(counter->hw.idx, 0); | ||
| 841 | counter->hw.idx = 0; | ||
| 842 | } | ||
| 843 | perf_counter_update_userpage(counter); | ||
| 844 | break; | ||
| 845 | } | ||
| 846 | } | ||
| 847 | for (i = 0; i < cpuhw->n_limited; ++i) | ||
| 848 | if (counter == cpuhw->limited_counter[i]) | ||
| 849 | break; | ||
| 850 | if (i < cpuhw->n_limited) { | ||
| 851 | while (++i < cpuhw->n_limited) { | ||
| 852 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; | ||
| 853 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; | ||
| 854 | } | ||
| 855 | --cpuhw->n_limited; | ||
| 856 | } | ||
| 857 | if (cpuhw->n_counters == 0) { | ||
| 858 | /* disable exceptions if no counters are running */ | ||
| 859 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); | ||
| 860 | } | ||
| 861 | |||
| 862 | perf_enable(); | ||
| 863 | local_irq_restore(flags); | ||
| 864 | } | ||
| 865 | |||
| 866 | /* | ||
| 867 | * Re-enable interrupts on a counter after they were throttled | ||
| 868 | * because they were coming too fast. | ||
| 869 | */ | ||
| 870 | static void power_pmu_unthrottle(struct perf_counter *counter) | ||
| 871 | { | ||
| 872 | s64 val, left; | ||
| 873 | unsigned long flags; | ||
| 874 | |||
| 875 | if (!counter->hw.idx || !counter->hw.sample_period) | ||
| 876 | return; | ||
| 877 | local_irq_save(flags); | ||
| 878 | perf_disable(); | ||
| 879 | power_pmu_read(counter); | ||
| 880 | left = counter->hw.sample_period; | ||
| 881 | counter->hw.last_period = left; | ||
| 882 | val = 0; | ||
| 883 | if (left < 0x80000000L) | ||
| 884 | val = 0x80000000L - left; | ||
| 885 | write_pmc(counter->hw.idx, val); | ||
| 886 | atomic64_set(&counter->hw.prev_count, val); | ||
| 887 | atomic64_set(&counter->hw.period_left, left); | ||
| 888 | perf_counter_update_userpage(counter); | ||
| 889 | perf_enable(); | ||
| 890 | local_irq_restore(flags); | ||
| 891 | } | ||
| 892 | |||
| 893 | struct pmu power_pmu = { | ||
| 894 | .enable = power_pmu_enable, | ||
| 895 | .disable = power_pmu_disable, | ||
| 896 | .read = power_pmu_read, | ||
| 897 | .unthrottle = power_pmu_unthrottle, | ||
| 898 | }; | ||
| 899 | |||
| 900 | /* | ||
| 901 | * Return 1 if we might be able to put counter on a limited PMC, | ||
| 902 | * or 0 if not. | ||
| 903 | * A counter can only go on a limited PMC if it counts something | ||
| 904 | * that a limited PMC can count, doesn't require interrupts, and | ||
| 905 | * doesn't exclude any processor mode. | ||
| 906 | */ | ||
| 907 | static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev, | ||
| 908 | unsigned int flags) | ||
| 909 | { | ||
| 910 | int n; | ||
| 911 | u64 alt[MAX_EVENT_ALTERNATIVES]; | ||
| 912 | |||
| 913 | if (counter->attr.exclude_user | ||
| 914 | || counter->attr.exclude_kernel | ||
| 915 | || counter->attr.exclude_hv | ||
| 916 | || counter->attr.sample_period) | ||
| 917 | return 0; | ||
| 918 | |||
| 919 | if (ppmu->limited_pmc_event(ev)) | ||
| 920 | return 1; | ||
| 921 | |||
| 922 | /* | ||
| 923 | * The requested event isn't on a limited PMC already; | ||
| 924 | * see if any alternative code goes on a limited PMC. | ||
| 925 | */ | ||
| 926 | if (!ppmu->get_alternatives) | ||
| 927 | return 0; | ||
| 928 | |||
| 929 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | ||
| 930 | n = ppmu->get_alternatives(ev, flags, alt); | ||
| 931 | |||
| 932 | return n > 0; | ||
| 933 | } | ||
| 934 | |||
| 935 | /* | ||
| 936 | * Find an alternative event that goes on a normal PMC, if possible, | ||
| 937 | * and return the event code, or 0 if there is no such alternative. | ||
| 938 | * (Note: event code 0 is "don't count" on all machines.) | ||
| 939 | */ | ||
| 940 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) | ||
| 941 | { | ||
| 942 | u64 alt[MAX_EVENT_ALTERNATIVES]; | ||
| 943 | int n; | ||
| 944 | |||
| 945 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | ||
| 946 | n = ppmu->get_alternatives(ev, flags, alt); | ||
| 947 | if (!n) | ||
| 948 | return 0; | ||
| 949 | return alt[0]; | ||
| 950 | } | ||
| 951 | |||
| 952 | /* Number of perf_counters counting hardware events */ | ||
| 953 | static atomic_t num_counters; | ||
| 954 | /* Used to avoid races in calling reserve/release_pmc_hardware */ | ||
| 955 | static DEFINE_MUTEX(pmc_reserve_mutex); | ||
| 956 | |||
| 957 | /* | ||
| 958 | * Release the PMU if this is the last perf_counter. | ||
| 959 | */ | ||
| 960 | static void hw_perf_counter_destroy(struct perf_counter *counter) | ||
| 961 | { | ||
| 962 | if (!atomic_add_unless(&num_counters, -1, 1)) { | ||
| 963 | mutex_lock(&pmc_reserve_mutex); | ||
| 964 | if (atomic_dec_return(&num_counters) == 0) | ||
| 965 | release_pmc_hardware(); | ||
| 966 | mutex_unlock(&pmc_reserve_mutex); | ||
| 967 | } | ||
| 968 | } | ||
| 969 | |||
| 970 | /* | ||
| 971 | * Translate a generic cache event config to a raw event code. | ||
| 972 | */ | ||
| 973 | static int hw_perf_cache_event(u64 config, u64 *eventp) | ||
| 974 | { | ||
| 975 | unsigned long type, op, result; | ||
| 976 | int ev; | ||
| 977 | |||
| 978 | if (!ppmu->cache_events) | ||
| 979 | return -EINVAL; | ||
| 980 | |||
| 981 | /* unpack config */ | ||
| 982 | type = config & 0xff; | ||
| 983 | op = (config >> 8) & 0xff; | ||
| 984 | result = (config >> 16) & 0xff; | ||
| 985 | |||
| 986 | if (type >= PERF_COUNT_HW_CACHE_MAX || | ||
| 987 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | ||
| 988 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | ||
| 989 | return -EINVAL; | ||
| 990 | |||
| 991 | ev = (*ppmu->cache_events)[type][op][result]; | ||
| 992 | if (ev == 0) | ||
| 993 | return -EOPNOTSUPP; | ||
| 994 | if (ev == -1) | ||
| 995 | return -EINVAL; | ||
| 996 | *eventp = ev; | ||
| 997 | return 0; | ||
| 998 | } | ||
| 999 | |||
| 1000 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) | ||
| 1001 | { | ||
| 1002 | u64 ev; | ||
| 1003 | unsigned long flags; | ||
| 1004 | struct perf_counter *ctrs[MAX_HWCOUNTERS]; | ||
| 1005 | u64 events[MAX_HWCOUNTERS]; | ||
| 1006 | unsigned int cflags[MAX_HWCOUNTERS]; | ||
| 1007 | int n; | ||
| 1008 | int err; | ||
| 1009 | |||
| 1010 | if (!ppmu) | ||
| 1011 | return ERR_PTR(-ENXIO); | ||
| 1012 | switch (counter->attr.type) { | ||
| 1013 | case PERF_TYPE_HARDWARE: | ||
| 1014 | ev = counter->attr.config; | ||
| 1015 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) | ||
| 1016 | return ERR_PTR(-EOPNOTSUPP); | ||
| 1017 | ev = ppmu->generic_events[ev]; | ||
| 1018 | break; | ||
| 1019 | case PERF_TYPE_HW_CACHE: | ||
| 1020 | err = hw_perf_cache_event(counter->attr.config, &ev); | ||
| 1021 | if (err) | ||
| 1022 | return ERR_PTR(err); | ||
| 1023 | break; | ||
| 1024 | case PERF_TYPE_RAW: | ||
| 1025 | ev = counter->attr.config; | ||
| 1026 | break; | ||
| 1027 | default: | ||
| 1028 | return ERR_PTR(-EINVAL); | ||
| 1029 | } | ||
| 1030 | counter->hw.config_base = ev; | ||
| 1031 | counter->hw.idx = 0; | ||
| 1032 | |||
| 1033 | /* | ||
| 1034 | * If we are not running on a hypervisor, force the | ||
| 1035 | * exclude_hv bit to 0 so that we don't care what | ||
| 1036 | * the user set it to. | ||
| 1037 | */ | ||
| 1038 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | ||
| 1039 | counter->attr.exclude_hv = 0; | ||
| 1040 | |||
| 1041 | /* | ||
| 1042 | * If this is a per-task counter, then we can use | ||
| 1043 | * PM_RUN_* events interchangeably with their non RUN_* | ||
| 1044 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | ||
| 1045 | * XXX we should check if the task is an idle task. | ||
| 1046 | */ | ||
| 1047 | flags = 0; | ||
| 1048 | if (counter->ctx->task) | ||
| 1049 | flags |= PPMU_ONLY_COUNT_RUN; | ||
| 1050 | |||
| 1051 | /* | ||
| 1052 | * If this machine has limited counters, check whether this | ||
| 1053 | * event could go on a limited counter. | ||
| 1054 | */ | ||
| 1055 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { | ||
| 1056 | if (can_go_on_limited_pmc(counter, ev, flags)) { | ||
| 1057 | flags |= PPMU_LIMITED_PMC_OK; | ||
| 1058 | } else if (ppmu->limited_pmc_event(ev)) { | ||
| 1059 | /* | ||
| 1060 | * The requested event is on a limited PMC, | ||
| 1061 | * but we can't use a limited PMC; see if any | ||
| 1062 | * alternative goes on a normal PMC. | ||
| 1063 | */ | ||
| 1064 | ev = normal_pmc_alternative(ev, flags); | ||
| 1065 | if (!ev) | ||
| 1066 | return ERR_PTR(-EINVAL); | ||
| 1067 | } | ||
| 1068 | } | ||
| 1069 | |||
| 1070 | /* | ||
| 1071 | * If this is in a group, check if it can go on with all the | ||
| 1072 | * other hardware counters in the group. We assume the counter | ||
| 1073 | * hasn't been linked into its leader's sibling list at this point. | ||
| 1074 | */ | ||
| 1075 | n = 0; | ||
| 1076 | if (counter->group_leader != counter) { | ||
| 1077 | n = collect_events(counter->group_leader, ppmu->n_counter - 1, | ||
| 1078 | ctrs, events, cflags); | ||
| 1079 | if (n < 0) | ||
| 1080 | return ERR_PTR(-EINVAL); | ||
| 1081 | } | ||
| 1082 | events[n] = ev; | ||
| 1083 | ctrs[n] = counter; | ||
| 1084 | cflags[n] = flags; | ||
| 1085 | if (check_excludes(ctrs, cflags, n, 1)) | ||
| 1086 | return ERR_PTR(-EINVAL); | ||
| 1087 | if (power_check_constraints(events, cflags, n + 1)) | ||
| 1088 | return ERR_PTR(-EINVAL); | ||
| 1089 | |||
| 1090 | counter->hw.config = events[n]; | ||
| 1091 | counter->hw.counter_base = cflags[n]; | ||
| 1092 | counter->hw.last_period = counter->hw.sample_period; | ||
| 1093 | atomic64_set(&counter->hw.period_left, counter->hw.last_period); | ||
| 1094 | |||
| 1095 | /* | ||
| 1096 | * See if we need to reserve the PMU. | ||
| 1097 | * If no counters are currently in use, then we have to take a | ||
| 1098 | * mutex to ensure that we don't race with another task doing | ||
| 1099 | * reserve_pmc_hardware or release_pmc_hardware. | ||
| 1100 | */ | ||
| 1101 | err = 0; | ||
| 1102 | if (!atomic_inc_not_zero(&num_counters)) { | ||
| 1103 | mutex_lock(&pmc_reserve_mutex); | ||
| 1104 | if (atomic_read(&num_counters) == 0 && | ||
| 1105 | reserve_pmc_hardware(perf_counter_interrupt)) | ||
| 1106 | err = -EBUSY; | ||
| 1107 | else | ||
| 1108 | atomic_inc(&num_counters); | ||
| 1109 | mutex_unlock(&pmc_reserve_mutex); | ||
| 1110 | } | ||
| 1111 | counter->destroy = hw_perf_counter_destroy; | ||
| 1112 | |||
| 1113 | if (err) | ||
| 1114 | return ERR_PTR(err); | ||
| 1115 | return &power_pmu; | ||
| 1116 | } | ||
| 1117 | |||
| 1118 | /* | ||
| 1119 | * A counter has overflowed; update its count and record | ||
| 1120 | * things if requested. Note that interrupts are hard-disabled | ||
| 1121 | * here so there is no possibility of being interrupted. | ||
| 1122 | */ | ||
| 1123 | static void record_and_restart(struct perf_counter *counter, unsigned long val, | ||
| 1124 | struct pt_regs *regs, int nmi) | ||
| 1125 | { | ||
| 1126 | u64 period = counter->hw.sample_period; | ||
| 1127 | s64 prev, delta, left; | ||
| 1128 | int record = 0; | ||
| 1129 | |||
| 1130 | /* we don't have to worry about interrupts here */ | ||
| 1131 | prev = atomic64_read(&counter->hw.prev_count); | ||
| 1132 | delta = (val - prev) & 0xfffffffful; | ||
| 1133 | atomic64_add(delta, &counter->count); | ||
| 1134 | |||
| 1135 | /* | ||
| 1136 | * See if the total period for this counter has expired, | ||
| 1137 | * and update for the next period. | ||
| 1138 | */ | ||
| 1139 | val = 0; | ||
| 1140 | left = atomic64_read(&counter->hw.period_left) - delta; | ||
| 1141 | if (period) { | ||
| 1142 | if (left <= 0) { | ||
| 1143 | left += period; | ||
| 1144 | if (left <= 0) | ||
| 1145 | left = period; | ||
| 1146 | record = 1; | ||
| 1147 | } | ||
| 1148 | if (left < 0x80000000LL) | ||
| 1149 | val = 0x80000000LL - left; | ||
| 1150 | } | ||
| 1151 | |||
| 1152 | /* | ||
| 1153 | * Finally record data if requested. | ||
| 1154 | */ | ||
| 1155 | if (record) { | ||
| 1156 | struct perf_sample_data data = { | ||
| 1157 | .regs = regs, | ||
| 1158 | .addr = 0, | ||
| 1159 | .period = counter->hw.last_period, | ||
| 1160 | }; | ||
| 1161 | |||
| 1162 | if (counter->attr.sample_type & PERF_SAMPLE_ADDR) | ||
| 1163 | perf_get_data_addr(regs, &data.addr); | ||
| 1164 | |||
| 1165 | if (perf_counter_overflow(counter, nmi, &data)) { | ||
| 1166 | /* | ||
| 1167 | * Interrupts are coming too fast - throttle them | ||
| 1168 | * by setting the counter to 0, so it will be | ||
| 1169 | * at least 2^30 cycles until the next interrupt | ||
| 1170 | * (assuming each counter counts at most 2 counts | ||
| 1171 | * per cycle). | ||
| 1172 | */ | ||
| 1173 | val = 0; | ||
| 1174 | left = ~0ULL >> 1; | ||
| 1175 | } | ||
| 1176 | } | ||
| 1177 | |||
| 1178 | write_pmc(counter->hw.idx, val); | ||
| 1179 | atomic64_set(&counter->hw.prev_count, val); | ||
| 1180 | atomic64_set(&counter->hw.period_left, left); | ||
| 1181 | perf_counter_update_userpage(counter); | ||
| 1182 | } | ||
| 1183 | |||
| 1184 | /* | ||
| 1185 | * Called from generic code to get the misc flags (i.e. processor mode) | ||
| 1186 | * for an event. | ||
| 1187 | */ | ||
| 1188 | unsigned long perf_misc_flags(struct pt_regs *regs) | ||
| 1189 | { | ||
| 1190 | u32 flags = perf_get_misc_flags(regs); | ||
| 1191 | |||
| 1192 | if (flags) | ||
| 1193 | return flags; | ||
| 1194 | return user_mode(regs) ? PERF_EVENT_MISC_USER : | ||
| 1195 | PERF_EVENT_MISC_KERNEL; | ||
| 1196 | } | ||
| 1197 | |||
| 1198 | /* | ||
| 1199 | * Called from generic code to get the instruction pointer | ||
| 1200 | * for an event. | ||
| 1201 | */ | ||
| 1202 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | ||
| 1203 | { | ||
| 1204 | unsigned long ip; | ||
| 1205 | |||
| 1206 | if (TRAP(regs) != 0xf00) | ||
| 1207 | return regs->nip; /* not a PMU interrupt */ | ||
| 1208 | |||
| 1209 | ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs); | ||
| 1210 | return ip; | ||
| 1211 | } | ||
| 1212 | |||
| 1213 | /* | ||
| 1214 | * Performance monitor interrupt stuff | ||
| 1215 | */ | ||
| 1216 | static void perf_counter_interrupt(struct pt_regs *regs) | ||
| 1217 | { | ||
| 1218 | int i; | ||
| 1219 | struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters); | ||
| 1220 | struct perf_counter *counter; | ||
| 1221 | unsigned long val; | ||
| 1222 | int found = 0; | ||
| 1223 | int nmi; | ||
| 1224 | |||
| 1225 | if (cpuhw->n_limited) | ||
| 1226 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), | ||
| 1227 | mfspr(SPRN_PMC6)); | ||
| 1228 | |||
| 1229 | perf_read_regs(regs); | ||
| 1230 | |||
| 1231 | nmi = perf_intr_is_nmi(regs); | ||
| 1232 | if (nmi) | ||
| 1233 | nmi_enter(); | ||
| 1234 | else | ||
| 1235 | irq_enter(); | ||
| 1236 | |||
| 1237 | for (i = 0; i < cpuhw->n_counters; ++i) { | ||
| 1238 | counter = cpuhw->counter[i]; | ||
| 1239 | if (!counter->hw.idx || is_limited_pmc(counter->hw.idx)) | ||
| 1240 | continue; | ||
| 1241 | val = read_pmc(counter->hw.idx); | ||
| 1242 | if ((int)val < 0) { | ||
| 1243 | /* counter has overflowed */ | ||
| 1244 | found = 1; | ||
| 1245 | record_and_restart(counter, val, regs, nmi); | ||
| 1246 | } | ||
| 1247 | } | ||
| 1248 | |||
| 1249 | /* | ||
| 1250 | * In case we didn't find and reset the counter that caused | ||
| 1251 | * the interrupt, scan all counters and reset any that are | ||
| 1252 | * negative, to avoid getting continual interrupts. | ||
| 1253 | * Any that we processed in the previous loop will not be negative. | ||
| 1254 | */ | ||
| 1255 | if (!found) { | ||
| 1256 | for (i = 0; i < ppmu->n_counter; ++i) { | ||
| 1257 | if (is_limited_pmc(i + 1)) | ||
| 1258 | continue; | ||
| 1259 | val = read_pmc(i + 1); | ||
| 1260 | if ((int)val < 0) | ||
| 1261 | write_pmc(i + 1, 0); | ||
| 1262 | } | ||
| 1263 | } | ||
| 1264 | |||
| 1265 | /* | ||
| 1266 | * Reset MMCR0 to its normal value. This will set PMXE and | ||
| 1267 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) | ||
| 1268 | * and thus allow interrupts to occur again. | ||
| 1269 | * XXX might want to use MSR.PM to keep the counters frozen until | ||
| 1270 | * we get back out of this interrupt. | ||
| 1271 | */ | ||
| 1272 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); | ||
| 1273 | |||
| 1274 | if (nmi) | ||
| 1275 | nmi_exit(); | ||
| 1276 | else | ||
| 1277 | irq_exit(); | ||
| 1278 | } | ||
| 1279 | |||
| 1280 | void hw_perf_counter_setup(int cpu) | ||
| 1281 | { | ||
| 1282 | struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu); | ||
| 1283 | |||
| 1284 | memset(cpuhw, 0, sizeof(*cpuhw)); | ||
| 1285 | cpuhw->mmcr[0] = MMCR0_FC; | ||
| 1286 | } | ||
| 1287 | |||
| 1288 | int register_power_pmu(struct power_pmu *pmu) | ||
| 1289 | { | ||
| 1290 | if (ppmu) | ||
| 1291 | return -EBUSY; /* something's already registered */ | ||
| 1292 | |||
| 1293 | ppmu = pmu; | ||
| 1294 | pr_info("%s performance monitor hardware support registered\n", | ||
| 1295 | pmu->name); | ||
| 1296 | |||
| 1297 | #ifdef MSR_HV | ||
| 1298 | /* | ||
| 1299 | * Use FCHV to ignore kernel events if MSR.HV is set. | ||
| 1300 | */ | ||
| 1301 | if (mfmsr() & MSR_HV) | ||
| 1302 | freeze_counters_kernel = MMCR0_FCHV; | ||
| 1303 | #endif /* CONFIG_PPC64 */ | ||
| 1304 | |||
| 1305 | return 0; | ||
| 1306 | } | ||
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c new file mode 100644 index 000000000000..db90b0c5c27b --- /dev/null +++ b/arch/powerpc/kernel/power4-pmu.c | |||
| @@ -0,0 +1,615 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for POWER4 (GP) and POWER4+ (GQ) processors. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for POWER4 | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0xf | ||
| 22 | #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */ | ||
| 23 | #define PM_UNIT_MSK 0xf | ||
| 24 | #define PM_LOWER_SH 6 | ||
| 25 | #define PM_LOWER_MSK 1 | ||
| 26 | #define PM_LOWER_MSKS 0x40 | ||
| 27 | #define PM_BYTE_SH 4 /* Byte number of event bus to use */ | ||
| 28 | #define PM_BYTE_MSK 3 | ||
| 29 | #define PM_PMCSEL_MSK 7 | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Unit code values | ||
| 33 | */ | ||
| 34 | #define PM_FPU 1 | ||
| 35 | #define PM_ISU1 2 | ||
| 36 | #define PM_IFU 3 | ||
| 37 | #define PM_IDU0 4 | ||
| 38 | #define PM_ISU1_ALT 6 | ||
| 39 | #define PM_ISU2 7 | ||
| 40 | #define PM_IFU_ALT 8 | ||
| 41 | #define PM_LSU0 9 | ||
| 42 | #define PM_LSU1 0xc | ||
| 43 | #define PM_GPS 0xf | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Bits in MMCR0 for POWER4 | ||
| 47 | */ | ||
| 48 | #define MMCR0_PMC1SEL_SH 8 | ||
| 49 | #define MMCR0_PMC2SEL_SH 1 | ||
| 50 | #define MMCR_PMCSEL_MSK 0x1f | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Bits in MMCR1 for POWER4 | ||
| 54 | */ | ||
| 55 | #define MMCR1_TTM0SEL_SH 62 | ||
| 56 | #define MMCR1_TTC0SEL_SH 61 | ||
| 57 | #define MMCR1_TTM1SEL_SH 59 | ||
| 58 | #define MMCR1_TTC1SEL_SH 58 | ||
| 59 | #define MMCR1_TTM2SEL_SH 56 | ||
| 60 | #define MMCR1_TTC2SEL_SH 55 | ||
| 61 | #define MMCR1_TTM3SEL_SH 53 | ||
| 62 | #define MMCR1_TTC3SEL_SH 52 | ||
| 63 | #define MMCR1_TTMSEL_MSK 3 | ||
| 64 | #define MMCR1_TD_CP_DBG0SEL_SH 50 | ||
| 65 | #define MMCR1_TD_CP_DBG1SEL_SH 48 | ||
| 66 | #define MMCR1_TD_CP_DBG2SEL_SH 46 | ||
| 67 | #define MMCR1_TD_CP_DBG3SEL_SH 44 | ||
| 68 | #define MMCR1_DEBUG0SEL_SH 43 | ||
| 69 | #define MMCR1_DEBUG1SEL_SH 42 | ||
| 70 | #define MMCR1_DEBUG2SEL_SH 41 | ||
| 71 | #define MMCR1_DEBUG3SEL_SH 40 | ||
| 72 | #define MMCR1_PMC1_ADDER_SEL_SH 39 | ||
| 73 | #define MMCR1_PMC2_ADDER_SEL_SH 38 | ||
| 74 | #define MMCR1_PMC6_ADDER_SEL_SH 37 | ||
| 75 | #define MMCR1_PMC5_ADDER_SEL_SH 36 | ||
| 76 | #define MMCR1_PMC8_ADDER_SEL_SH 35 | ||
| 77 | #define MMCR1_PMC7_ADDER_SEL_SH 34 | ||
| 78 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | ||
| 79 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | ||
| 80 | #define MMCR1_PMC3SEL_SH 27 | ||
| 81 | #define MMCR1_PMC4SEL_SH 22 | ||
| 82 | #define MMCR1_PMC5SEL_SH 17 | ||
| 83 | #define MMCR1_PMC6SEL_SH 12 | ||
| 84 | #define MMCR1_PMC7SEL_SH 7 | ||
| 85 | #define MMCR1_PMC8SEL_SH 2 /* note bit 0 is in MMCRA for GP */ | ||
| 86 | |||
| 87 | static short mmcr1_adder_bits[8] = { | ||
| 88 | MMCR1_PMC1_ADDER_SEL_SH, | ||
| 89 | MMCR1_PMC2_ADDER_SEL_SH, | ||
| 90 | MMCR1_PMC3_ADDER_SEL_SH, | ||
| 91 | MMCR1_PMC4_ADDER_SEL_SH, | ||
| 92 | MMCR1_PMC5_ADDER_SEL_SH, | ||
| 93 | MMCR1_PMC6_ADDER_SEL_SH, | ||
| 94 | MMCR1_PMC7_ADDER_SEL_SH, | ||
| 95 | MMCR1_PMC8_ADDER_SEL_SH | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Bits in MMCRA | ||
| 100 | */ | ||
| 101 | #define MMCRA_PMC8SEL0_SH 17 /* PMC8SEL bit 0 for GP */ | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Layout of constraint bits: | ||
| 105 | * 6666555555555544444444443333333333222222222211111111110000000000 | ||
| 106 | * 3210987654321098765432109876543210987654321098765432109876543210 | ||
| 107 | * |[ >[ >[ >|||[ >[ >< >< >< >< ><><><><><><><><> | ||
| 108 | * | UC1 UC2 UC3 ||| PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8 | ||
| 109 | * \SMPL ||\TTC3SEL | ||
| 110 | * |\TTC_IFU_SEL | ||
| 111 | * \TTM2SEL0 | ||
| 112 | * | ||
| 113 | * SMPL - SAMPLE_ENABLE constraint | ||
| 114 | * 56: SAMPLE_ENABLE value 0x0100_0000_0000_0000 | ||
| 115 | * | ||
| 116 | * UC1 - unit constraint 1: can't have all three of FPU/ISU1/IDU0|ISU2 | ||
| 117 | * 55: UC1 error 0x0080_0000_0000_0000 | ||
| 118 | * 54: FPU events needed 0x0040_0000_0000_0000 | ||
| 119 | * 53: ISU1 events needed 0x0020_0000_0000_0000 | ||
| 120 | * 52: IDU0|ISU2 events needed 0x0010_0000_0000_0000 | ||
| 121 | * | ||
| 122 | * UC2 - unit constraint 2: can't have all three of FPU/IFU/LSU0 | ||
| 123 | * 51: UC2 error 0x0008_0000_0000_0000 | ||
| 124 | * 50: FPU events needed 0x0004_0000_0000_0000 | ||
| 125 | * 49: IFU events needed 0x0002_0000_0000_0000 | ||
| 126 | * 48: LSU0 events needed 0x0001_0000_0000_0000 | ||
| 127 | * | ||
| 128 | * UC3 - unit constraint 3: can't have all four of LSU0/IFU/IDU0|ISU2/ISU1 | ||
| 129 | * 47: UC3 error 0x8000_0000_0000 | ||
| 130 | * 46: LSU0 events needed 0x4000_0000_0000 | ||
| 131 | * 45: IFU events needed 0x2000_0000_0000 | ||
| 132 | * 44: IDU0|ISU2 events needed 0x1000_0000_0000 | ||
| 133 | * 43: ISU1 events needed 0x0800_0000_0000 | ||
| 134 | * | ||
| 135 | * TTM2SEL0 | ||
| 136 | * 42: 0 = IDU0 events needed | ||
| 137 | * 1 = ISU2 events needed 0x0400_0000_0000 | ||
| 138 | * | ||
| 139 | * TTC_IFU_SEL | ||
| 140 | * 41: 0 = IFU.U events needed | ||
| 141 | * 1 = IFU.L events needed 0x0200_0000_0000 | ||
| 142 | * | ||
| 143 | * TTC3SEL | ||
| 144 | * 40: 0 = LSU1.U events needed | ||
| 145 | * 1 = LSU1.L events needed 0x0100_0000_0000 | ||
| 146 | * | ||
| 147 | * PS1 | ||
| 148 | * 39: PS1 error 0x0080_0000_0000 | ||
| 149 | * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000 | ||
| 150 | * | ||
| 151 | * PS2 | ||
| 152 | * 35: PS2 error 0x0008_0000_0000 | ||
| 153 | * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000 | ||
| 154 | * | ||
| 155 | * B0 | ||
| 156 | * 28-31: Byte 0 event source 0xf000_0000 | ||
| 157 | * 1 = FPU | ||
| 158 | * 2 = ISU1 | ||
| 159 | * 3 = IFU | ||
| 160 | * 4 = IDU0 | ||
| 161 | * 7 = ISU2 | ||
| 162 | * 9 = LSU0 | ||
| 163 | * c = LSU1 | ||
| 164 | * f = GPS | ||
| 165 | * | ||
| 166 | * B1, B2, B3 | ||
| 167 | * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources | ||
| 168 | * | ||
| 169 | * P8 | ||
| 170 | * 15: P8 error 0x8000 | ||
| 171 | * 14-15: Count of events needing PMC8 | ||
| 172 | * | ||
| 173 | * P1..P7 | ||
| 174 | * 0-13: Count of events needing PMC1..PMC7 | ||
| 175 | * | ||
| 176 | * Note: this doesn't allow events using IFU.U to be combined with events | ||
| 177 | * using IFU.L, though that is feasible (using TTM0 and TTM2). However | ||
| 178 | * there are no listed events for IFU.L (they are debug events not | ||
| 179 | * verified for performance monitoring) so this shouldn't cause a | ||
| 180 | * problem. | ||
| 181 | */ | ||
| 182 | |||
| 183 | static struct unitinfo { | ||
| 184 | unsigned long value, mask; | ||
| 185 | int unit; | ||
| 186 | int lowerbit; | ||
| 187 | } p4_unitinfo[16] = { | ||
| 188 | [PM_FPU] = { 0x44000000000000ul, 0x88000000000000ul, PM_FPU, 0 }, | ||
| 189 | [PM_ISU1] = { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 }, | ||
| 190 | [PM_ISU1_ALT] = | ||
| 191 | { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 }, | ||
| 192 | [PM_IFU] = { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 }, | ||
| 193 | [PM_IFU_ALT] = | ||
| 194 | { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 }, | ||
| 195 | [PM_IDU0] = { 0x10100000000000ul, 0x80840000000000ul, PM_IDU0, 1 }, | ||
| 196 | [PM_ISU2] = { 0x10140000000000ul, 0x80840000000000ul, PM_ISU2, 0 }, | ||
| 197 | [PM_LSU0] = { 0x01400000000000ul, 0x08800000000000ul, PM_LSU0, 0 }, | ||
| 198 | [PM_LSU1] = { 0x00000000000000ul, 0x00010000000000ul, PM_LSU1, 40 }, | ||
| 199 | [PM_GPS] = { 0x00000000000000ul, 0x00000000000000ul, PM_GPS, 0 } | ||
| 200 | }; | ||
| 201 | |||
| 202 | static unsigned char direct_marked_event[8] = { | ||
| 203 | (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */ | ||
| 204 | (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */ | ||
| 205 | (1<<3), /* PMC3: PM_MRK_ST_CMPL_INT */ | ||
| 206 | (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */ | ||
| 207 | (1<<4) | (1<<5), /* PMC5: PM_MRK_GRP_TIMEO */ | ||
| 208 | (1<<3) | (1<<4) | (1<<5), | ||
| 209 | /* PMC6: PM_MRK_ST_GPS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */ | ||
| 210 | (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */ | ||
| 211 | (1<<4), /* PMC8: PM_MRK_LSU_FIN */ | ||
| 212 | }; | ||
| 213 | |||
| 214 | /* | ||
| 215 | * Returns 1 if event counts things relating to marked instructions | ||
| 216 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 217 | */ | ||
| 218 | static int p4_marked_instr_event(u64 event) | ||
| 219 | { | ||
| 220 | int pmc, psel, unit, byte, bit; | ||
| 221 | unsigned int mask; | ||
| 222 | |||
| 223 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 224 | psel = event & PM_PMCSEL_MSK; | ||
| 225 | if (pmc) { | ||
| 226 | if (direct_marked_event[pmc - 1] & (1 << psel)) | ||
| 227 | return 1; | ||
| 228 | if (psel == 0) /* add events */ | ||
| 229 | bit = (pmc <= 4)? pmc - 1: 8 - pmc; | ||
| 230 | else if (psel == 6) /* decode events */ | ||
| 231 | bit = 4; | ||
| 232 | else | ||
| 233 | return 0; | ||
| 234 | } else | ||
| 235 | bit = psel; | ||
| 236 | |||
| 237 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 238 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 239 | mask = 0; | ||
| 240 | switch (unit) { | ||
| 241 | case PM_LSU1: | ||
| 242 | if (event & PM_LOWER_MSKS) | ||
| 243 | mask = 1 << 28; /* byte 7 bit 4 */ | ||
| 244 | else | ||
| 245 | mask = 6 << 24; /* byte 3 bits 1 and 2 */ | ||
| 246 | break; | ||
| 247 | case PM_LSU0: | ||
| 248 | /* byte 3, bit 3; byte 2 bits 0,2,3,4,5; byte 1 */ | ||
| 249 | mask = 0x083dff00; | ||
| 250 | } | ||
| 251 | return (mask >> (byte * 8 + bit)) & 1; | ||
| 252 | } | ||
| 253 | |||
| 254 | static int p4_get_constraint(u64 event, unsigned long *maskp, | ||
| 255 | unsigned long *valp) | ||
| 256 | { | ||
| 257 | int pmc, byte, unit, lower, sh; | ||
| 258 | unsigned long mask = 0, value = 0; | ||
| 259 | int grp = -1; | ||
| 260 | |||
| 261 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 262 | if (pmc) { | ||
| 263 | if (pmc > 8) | ||
| 264 | return -1; | ||
| 265 | sh = (pmc - 1) * 2; | ||
| 266 | mask |= 2 << sh; | ||
| 267 | value |= 1 << sh; | ||
| 268 | grp = ((pmc - 1) >> 1) & 1; | ||
| 269 | } | ||
| 270 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 271 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 272 | if (unit) { | ||
| 273 | lower = (event >> PM_LOWER_SH) & PM_LOWER_MSK; | ||
| 274 | |||
| 275 | /* | ||
| 276 | * Bus events on bytes 0 and 2 can be counted | ||
| 277 | * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8. | ||
| 278 | */ | ||
| 279 | if (!pmc) | ||
| 280 | grp = byte & 1; | ||
| 281 | |||
| 282 | if (!p4_unitinfo[unit].unit) | ||
| 283 | return -1; | ||
| 284 | mask |= p4_unitinfo[unit].mask; | ||
| 285 | value |= p4_unitinfo[unit].value; | ||
| 286 | sh = p4_unitinfo[unit].lowerbit; | ||
| 287 | if (sh > 1) | ||
| 288 | value |= (unsigned long)lower << sh; | ||
| 289 | else if (lower != sh) | ||
| 290 | return -1; | ||
| 291 | unit = p4_unitinfo[unit].unit; | ||
| 292 | |||
| 293 | /* Set byte lane select field */ | ||
| 294 | mask |= 0xfULL << (28 - 4 * byte); | ||
| 295 | value |= (unsigned long)unit << (28 - 4 * byte); | ||
| 296 | } | ||
| 297 | if (grp == 0) { | ||
| 298 | /* increment PMC1/2/5/6 field */ | ||
| 299 | mask |= 0x8000000000ull; | ||
| 300 | value |= 0x1000000000ull; | ||
| 301 | } else { | ||
| 302 | /* increment PMC3/4/7/8 field */ | ||
| 303 | mask |= 0x800000000ull; | ||
| 304 | value |= 0x100000000ull; | ||
| 305 | } | ||
| 306 | |||
| 307 | /* Marked instruction events need sample_enable set */ | ||
| 308 | if (p4_marked_instr_event(event)) { | ||
| 309 | mask |= 1ull << 56; | ||
| 310 | value |= 1ull << 56; | ||
| 311 | } | ||
| 312 | |||
| 313 | /* PMCSEL=6 decode events on byte 2 need sample_enable clear */ | ||
| 314 | if (pmc && (event & PM_PMCSEL_MSK) == 6 && byte == 2) | ||
| 315 | mask |= 1ull << 56; | ||
| 316 | |||
| 317 | *maskp = mask; | ||
| 318 | *valp = value; | ||
| 319 | return 0; | ||
| 320 | } | ||
| 321 | |||
| 322 | static unsigned int ppc_inst_cmpl[] = { | ||
| 323 | 0x1001, 0x4001, 0x6001, 0x7001, 0x8001 | ||
| 324 | }; | ||
| 325 | |||
| 326 | static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 327 | { | ||
| 328 | int i, j, na; | ||
| 329 | |||
| 330 | alt[0] = event; | ||
| 331 | na = 1; | ||
| 332 | |||
| 333 | /* 2 possibilities for PM_GRP_DISP_REJECT */ | ||
| 334 | if (event == 0x8003 || event == 0x0224) { | ||
| 335 | alt[1] = event ^ (0x8003 ^ 0x0224); | ||
| 336 | return 2; | ||
| 337 | } | ||
| 338 | |||
| 339 | /* 2 possibilities for PM_ST_MISS_L1 */ | ||
| 340 | if (event == 0x0c13 || event == 0x0c23) { | ||
| 341 | alt[1] = event ^ (0x0c13 ^ 0x0c23); | ||
| 342 | return 2; | ||
| 343 | } | ||
| 344 | |||
| 345 | /* several possibilities for PM_INST_CMPL */ | ||
| 346 | for (i = 0; i < ARRAY_SIZE(ppc_inst_cmpl); ++i) { | ||
| 347 | if (event == ppc_inst_cmpl[i]) { | ||
| 348 | for (j = 0; j < ARRAY_SIZE(ppc_inst_cmpl); ++j) | ||
| 349 | if (j != i) | ||
| 350 | alt[na++] = ppc_inst_cmpl[j]; | ||
| 351 | break; | ||
| 352 | } | ||
| 353 | } | ||
| 354 | |||
| 355 | return na; | ||
| 356 | } | ||
| 357 | |||
| 358 | static int p4_compute_mmcr(u64 event[], int n_ev, | ||
| 359 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 360 | { | ||
| 361 | unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0; | ||
| 362 | unsigned int pmc, unit, byte, psel, lower; | ||
| 363 | unsigned int ttm, grp; | ||
| 364 | unsigned int pmc_inuse = 0; | ||
| 365 | unsigned int pmc_grp_use[2]; | ||
| 366 | unsigned char busbyte[4]; | ||
| 367 | unsigned char unituse[16]; | ||
| 368 | unsigned int unitlower = 0; | ||
| 369 | int i; | ||
| 370 | |||
| 371 | if (n_ev > 8) | ||
| 372 | return -1; | ||
| 373 | |||
| 374 | /* First pass to count resource use */ | ||
| 375 | pmc_grp_use[0] = pmc_grp_use[1] = 0; | ||
| 376 | memset(busbyte, 0, sizeof(busbyte)); | ||
| 377 | memset(unituse, 0, sizeof(unituse)); | ||
| 378 | for (i = 0; i < n_ev; ++i) { | ||
| 379 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 380 | if (pmc) { | ||
| 381 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 382 | return -1; | ||
| 383 | pmc_inuse |= 1 << (pmc - 1); | ||
| 384 | /* count 1/2/5/6 vs 3/4/7/8 use */ | ||
| 385 | ++pmc_grp_use[((pmc - 1) >> 1) & 1]; | ||
| 386 | } | ||
| 387 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 388 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 389 | lower = (event[i] >> PM_LOWER_SH) & PM_LOWER_MSK; | ||
| 390 | if (unit) { | ||
| 391 | if (!pmc) | ||
| 392 | ++pmc_grp_use[byte & 1]; | ||
| 393 | if (unit == 6 || unit == 8) | ||
| 394 | /* map alt ISU1/IFU codes: 6->2, 8->3 */ | ||
| 395 | unit = (unit >> 1) - 1; | ||
| 396 | if (busbyte[byte] && busbyte[byte] != unit) | ||
| 397 | return -1; | ||
| 398 | busbyte[byte] = unit; | ||
| 399 | lower <<= unit; | ||
| 400 | if (unituse[unit] && lower != (unitlower & lower)) | ||
| 401 | return -1; | ||
| 402 | unituse[unit] = 1; | ||
| 403 | unitlower |= lower; | ||
| 404 | } | ||
| 405 | } | ||
| 406 | if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4) | ||
| 407 | return -1; | ||
| 408 | |||
| 409 | /* | ||
| 410 | * Assign resources and set multiplexer selects. | ||
| 411 | * | ||
| 412 | * Units 1,2,3 are on TTM0, 4,6,7 on TTM1, 8,10 on TTM2. | ||
| 413 | * Each TTMx can only select one unit, but since | ||
| 414 | * units 2 and 6 are both ISU1, and 3 and 8 are both IFU, | ||
| 415 | * we have some choices. | ||
| 416 | */ | ||
| 417 | if (unituse[2] & (unituse[1] | (unituse[3] & unituse[9]))) { | ||
| 418 | unituse[6] = 1; /* Move 2 to 6 */ | ||
| 419 | unituse[2] = 0; | ||
| 420 | } | ||
| 421 | if (unituse[3] & (unituse[1] | unituse[2])) { | ||
| 422 | unituse[8] = 1; /* Move 3 to 8 */ | ||
| 423 | unituse[3] = 0; | ||
| 424 | unitlower = (unitlower & ~8) | ((unitlower & 8) << 5); | ||
| 425 | } | ||
| 426 | /* Check only one unit per TTMx */ | ||
| 427 | if (unituse[1] + unituse[2] + unituse[3] > 1 || | ||
| 428 | unituse[4] + unituse[6] + unituse[7] > 1 || | ||
| 429 | unituse[8] + unituse[9] > 1 || | ||
| 430 | (unituse[5] | unituse[10] | unituse[11] | | ||
| 431 | unituse[13] | unituse[14])) | ||
| 432 | return -1; | ||
| 433 | |||
| 434 | /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */ | ||
| 435 | mmcr1 |= (unsigned long)(unituse[3] * 2 + unituse[2]) | ||
| 436 | << MMCR1_TTM0SEL_SH; | ||
| 437 | mmcr1 |= (unsigned long)(unituse[7] * 3 + unituse[6] * 2) | ||
| 438 | << MMCR1_TTM1SEL_SH; | ||
| 439 | mmcr1 |= (unsigned long)unituse[9] << MMCR1_TTM2SEL_SH; | ||
| 440 | |||
| 441 | /* Set TTCxSEL fields. */ | ||
| 442 | if (unitlower & 0xe) | ||
| 443 | mmcr1 |= 1ull << MMCR1_TTC0SEL_SH; | ||
| 444 | if (unitlower & 0xf0) | ||
| 445 | mmcr1 |= 1ull << MMCR1_TTC1SEL_SH; | ||
| 446 | if (unitlower & 0xf00) | ||
| 447 | mmcr1 |= 1ull << MMCR1_TTC2SEL_SH; | ||
| 448 | if (unitlower & 0x7000) | ||
| 449 | mmcr1 |= 1ull << MMCR1_TTC3SEL_SH; | ||
| 450 | |||
| 451 | /* Set byte lane select fields. */ | ||
| 452 | for (byte = 0; byte < 4; ++byte) { | ||
| 453 | unit = busbyte[byte]; | ||
| 454 | if (!unit) | ||
| 455 | continue; | ||
| 456 | if (unit == 0xf) { | ||
| 457 | /* special case for GPS */ | ||
| 458 | mmcr1 |= 1ull << (MMCR1_DEBUG0SEL_SH - byte); | ||
| 459 | } else { | ||
| 460 | if (!unituse[unit]) | ||
| 461 | ttm = unit - 1; /* 2->1, 3->2 */ | ||
| 462 | else | ||
| 463 | ttm = unit >> 2; | ||
| 464 | mmcr1 |= (unsigned long)ttm | ||
| 465 | << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); | ||
| 466 | } | ||
| 467 | } | ||
| 468 | |||
| 469 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | ||
| 470 | for (i = 0; i < n_ev; ++i) { | ||
| 471 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 472 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 473 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 474 | psel = event[i] & PM_PMCSEL_MSK; | ||
| 475 | if (!pmc) { | ||
| 476 | /* Bus event or 00xxx direct event (off or cycles) */ | ||
| 477 | if (unit) | ||
| 478 | psel |= 0x10 | ((byte & 2) << 2); | ||
| 479 | for (pmc = 0; pmc < 8; ++pmc) { | ||
| 480 | if (pmc_inuse & (1 << pmc)) | ||
| 481 | continue; | ||
| 482 | grp = (pmc >> 1) & 1; | ||
| 483 | if (unit) { | ||
| 484 | if (grp == (byte & 1)) | ||
| 485 | break; | ||
| 486 | } else if (pmc_grp_use[grp] < 4) { | ||
| 487 | ++pmc_grp_use[grp]; | ||
| 488 | break; | ||
| 489 | } | ||
| 490 | } | ||
| 491 | pmc_inuse |= 1 << pmc; | ||
| 492 | } else { | ||
| 493 | /* Direct event */ | ||
| 494 | --pmc; | ||
| 495 | if (psel == 0 && (byte & 2)) | ||
| 496 | /* add events on higher-numbered bus */ | ||
| 497 | mmcr1 |= 1ull << mmcr1_adder_bits[pmc]; | ||
| 498 | else if (psel == 6 && byte == 3) | ||
| 499 | /* seem to need to set sample_enable here */ | ||
| 500 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 501 | psel |= 8; | ||
| 502 | } | ||
| 503 | if (pmc <= 1) | ||
| 504 | mmcr0 |= psel << (MMCR0_PMC1SEL_SH - 7 * pmc); | ||
| 505 | else | ||
| 506 | mmcr1 |= psel << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); | ||
| 507 | if (pmc == 7) /* PMC8 */ | ||
| 508 | mmcra |= (psel & 1) << MMCRA_PMC8SEL0_SH; | ||
| 509 | hwc[i] = pmc; | ||
| 510 | if (p4_marked_instr_event(event[i])) | ||
| 511 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 512 | } | ||
| 513 | |||
| 514 | if (pmc_inuse & 1) | ||
| 515 | mmcr0 |= MMCR0_PMC1CE; | ||
| 516 | if (pmc_inuse & 0xfe) | ||
| 517 | mmcr0 |= MMCR0_PMCjCE; | ||
| 518 | |||
| 519 | mmcra |= 0x2000; /* mark only one IOP per PPC instruction */ | ||
| 520 | |||
| 521 | /* Return MMCRx values */ | ||
| 522 | mmcr[0] = mmcr0; | ||
| 523 | mmcr[1] = mmcr1; | ||
| 524 | mmcr[2] = mmcra; | ||
| 525 | return 0; | ||
| 526 | } | ||
| 527 | |||
| 528 | static void p4_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 529 | { | ||
| 530 | /* | ||
| 531 | * Setting the PMCxSEL field to 0 disables PMC x. | ||
| 532 | * (Note that pmc is 0-based here, not 1-based.) | ||
| 533 | */ | ||
| 534 | if (pmc <= 1) { | ||
| 535 | mmcr[0] &= ~(0x1fUL << (MMCR0_PMC1SEL_SH - 7 * pmc)); | ||
| 536 | } else { | ||
| 537 | mmcr[1] &= ~(0x1fUL << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2))); | ||
| 538 | if (pmc == 7) | ||
| 539 | mmcr[2] &= ~(1UL << MMCRA_PMC8SEL0_SH); | ||
| 540 | } | ||
| 541 | } | ||
| 542 | |||
| 543 | static int p4_generic_events[] = { | ||
| 544 | [PERF_COUNT_HW_CPU_CYCLES] = 7, | ||
| 545 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x1001, | ||
| 546 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8c10, /* PM_LD_REF_L1 */ | ||
| 547 | [PERF_COUNT_HW_CACHE_MISSES] = 0x3c10, /* PM_LD_MISS_L1 */ | ||
| 548 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x330, /* PM_BR_ISSUED */ | ||
| 549 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x331, /* PM_BR_MPRED_CR */ | ||
| 550 | }; | ||
| 551 | |||
| 552 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 553 | |||
| 554 | /* | ||
| 555 | * Table of generalized cache-related events. | ||
| 556 | * 0 means not supported, -1 means nonsensical, other values | ||
| 557 | * are event codes. | ||
| 558 | */ | ||
| 559 | static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 560 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 561 | [C(OP_READ)] = { 0x8c10, 0x3c10 }, | ||
| 562 | [C(OP_WRITE)] = { 0x7c10, 0xc13 }, | ||
| 563 | [C(OP_PREFETCH)] = { 0xc35, 0 }, | ||
| 564 | }, | ||
| 565 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 566 | [C(OP_READ)] = { 0, 0 }, | ||
| 567 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 568 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 569 | }, | ||
| 570 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 571 | [C(OP_READ)] = { 0, 0 }, | ||
| 572 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 573 | [C(OP_PREFETCH)] = { 0xc34, 0 }, | ||
| 574 | }, | ||
| 575 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 576 | [C(OP_READ)] = { 0, 0x904 }, | ||
| 577 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 578 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 579 | }, | ||
| 580 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 581 | [C(OP_READ)] = { 0, 0x900 }, | ||
| 582 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 583 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 584 | }, | ||
| 585 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 586 | [C(OP_READ)] = { 0x330, 0x331 }, | ||
| 587 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 588 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 589 | }, | ||
| 590 | }; | ||
| 591 | |||
| 592 | static struct power_pmu power4_pmu = { | ||
| 593 | .name = "POWER4/4+", | ||
| 594 | .n_counter = 8, | ||
| 595 | .max_alternatives = 5, | ||
| 596 | .add_fields = 0x0000001100005555ul, | ||
| 597 | .test_adder = 0x0011083300000000ul, | ||
| 598 | .compute_mmcr = p4_compute_mmcr, | ||
| 599 | .get_constraint = p4_get_constraint, | ||
| 600 | .get_alternatives = p4_get_alternatives, | ||
| 601 | .disable_pmc = p4_disable_pmc, | ||
| 602 | .n_generic = ARRAY_SIZE(p4_generic_events), | ||
| 603 | .generic_events = p4_generic_events, | ||
| 604 | .cache_events = &power4_cache_events, | ||
| 605 | }; | ||
| 606 | |||
| 607 | static int init_power4_pmu(void) | ||
| 608 | { | ||
| 609 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4")) | ||
| 610 | return -ENODEV; | ||
| 611 | |||
| 612 | return register_power_pmu(&power4_pmu); | ||
| 613 | } | ||
| 614 | |||
| 615 | arch_initcall(init_power4_pmu); | ||
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c new file mode 100644 index 000000000000..f4adca8e98a4 --- /dev/null +++ b/arch/powerpc/kernel/power5+-pmu.c | |||
| @@ -0,0 +1,688 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for POWER5+/++ (not POWER5) processors. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3) | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0xf | ||
| 22 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | ||
| 23 | #define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */ | ||
| 24 | #define PM_UNIT_MSK 0xf | ||
| 25 | #define PM_BYTE_SH 12 /* Byte number of event bus to use */ | ||
| 26 | #define PM_BYTE_MSK 7 | ||
| 27 | #define PM_GRS_SH 8 /* Storage subsystem mux select */ | ||
| 28 | #define PM_GRS_MSK 7 | ||
| 29 | #define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */ | ||
| 30 | #define PM_PMCSEL_MSK 0x7f | ||
| 31 | |||
| 32 | /* Values in PM_UNIT field */ | ||
| 33 | #define PM_FPU 0 | ||
| 34 | #define PM_ISU0 1 | ||
| 35 | #define PM_IFU 2 | ||
| 36 | #define PM_ISU1 3 | ||
| 37 | #define PM_IDU 4 | ||
| 38 | #define PM_ISU0_ALT 6 | ||
| 39 | #define PM_GRS 7 | ||
| 40 | #define PM_LSU0 8 | ||
| 41 | #define PM_LSU1 0xc | ||
| 42 | #define PM_LASTUNIT 0xc | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Bits in MMCR1 for POWER5+ | ||
| 46 | */ | ||
| 47 | #define MMCR1_TTM0SEL_SH 62 | ||
| 48 | #define MMCR1_TTM1SEL_SH 60 | ||
| 49 | #define MMCR1_TTM2SEL_SH 58 | ||
| 50 | #define MMCR1_TTM3SEL_SH 56 | ||
| 51 | #define MMCR1_TTMSEL_MSK 3 | ||
| 52 | #define MMCR1_TD_CP_DBG0SEL_SH 54 | ||
| 53 | #define MMCR1_TD_CP_DBG1SEL_SH 52 | ||
| 54 | #define MMCR1_TD_CP_DBG2SEL_SH 50 | ||
| 55 | #define MMCR1_TD_CP_DBG3SEL_SH 48 | ||
| 56 | #define MMCR1_GRS_L2SEL_SH 46 | ||
| 57 | #define MMCR1_GRS_L2SEL_MSK 3 | ||
| 58 | #define MMCR1_GRS_L3SEL_SH 44 | ||
| 59 | #define MMCR1_GRS_L3SEL_MSK 3 | ||
| 60 | #define MMCR1_GRS_MCSEL_SH 41 | ||
| 61 | #define MMCR1_GRS_MCSEL_MSK 7 | ||
| 62 | #define MMCR1_GRS_FABSEL_SH 39 | ||
| 63 | #define MMCR1_GRS_FABSEL_MSK 3 | ||
| 64 | #define MMCR1_PMC1_ADDER_SEL_SH 35 | ||
| 65 | #define MMCR1_PMC2_ADDER_SEL_SH 34 | ||
| 66 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | ||
| 67 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | ||
| 68 | #define MMCR1_PMC1SEL_SH 25 | ||
| 69 | #define MMCR1_PMC2SEL_SH 17 | ||
| 70 | #define MMCR1_PMC3SEL_SH 9 | ||
| 71 | #define MMCR1_PMC4SEL_SH 1 | ||
| 72 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | ||
| 73 | #define MMCR1_PMCSEL_MSK 0x7f | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Bits in MMCRA | ||
| 77 | */ | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Layout of constraint bits: | ||
| 81 | * 6666555555555544444444443333333333222222222211111111110000000000 | ||
| 82 | * 3210987654321098765432109876543210987654321098765432109876543210 | ||
| 83 | * [ ><><>< ><> <><>[ > < >< >< >< ><><><><><><> | ||
| 84 | * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P6P5P4P3P2P1 | ||
| 85 | * | ||
| 86 | * NC - number of counters | ||
| 87 | * 51: NC error 0x0008_0000_0000_0000 | ||
| 88 | * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000 | ||
| 89 | * | ||
| 90 | * G0..G3 - GRS mux constraints | ||
| 91 | * 46-47: GRS_L2SEL value | ||
| 92 | * 44-45: GRS_L3SEL value | ||
| 93 | * 41-44: GRS_MCSEL value | ||
| 94 | * 39-40: GRS_FABSEL value | ||
| 95 | * Note that these match up with their bit positions in MMCR1 | ||
| 96 | * | ||
| 97 | * T0 - TTM0 constraint | ||
| 98 | * 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000 | ||
| 99 | * | ||
| 100 | * T1 - TTM1 constraint | ||
| 101 | * 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000 | ||
| 102 | * | ||
| 103 | * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS | ||
| 104 | * 33: UC3 error 0x02_0000_0000 | ||
| 105 | * 32: FPU|IFU|ISU1 events needed 0x01_0000_0000 | ||
| 106 | * 31: ISU0 events needed 0x01_8000_0000 | ||
| 107 | * 30: IDU|GRS events needed 0x00_4000_0000 | ||
| 108 | * | ||
| 109 | * B0 | ||
| 110 | * 24-27: Byte 0 event source 0x0f00_0000 | ||
| 111 | * Encoding as for the event code | ||
| 112 | * | ||
| 113 | * B1, B2, B3 | ||
| 114 | * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources | ||
| 115 | * | ||
| 116 | * P6 | ||
| 117 | * 11: P6 error 0x800 | ||
| 118 | * 10-11: Count of events needing PMC6 | ||
| 119 | * | ||
| 120 | * P1..P5 | ||
| 121 | * 0-9: Count of events needing PMC1..PMC5 | ||
| 122 | */ | ||
| 123 | |||
| 124 | static const int grsel_shift[8] = { | ||
| 125 | MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, | ||
| 126 | MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, | ||
| 127 | MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH | ||
| 128 | }; | ||
| 129 | |||
| 130 | /* Masks and values for using events from the various units */ | ||
| 131 | static unsigned long unit_cons[PM_LASTUNIT+1][2] = { | ||
| 132 | [PM_FPU] = { 0x3200000000ul, 0x0100000000ul }, | ||
| 133 | [PM_ISU0] = { 0x0200000000ul, 0x0080000000ul }, | ||
| 134 | [PM_ISU1] = { 0x3200000000ul, 0x3100000000ul }, | ||
| 135 | [PM_IFU] = { 0x3200000000ul, 0x2100000000ul }, | ||
| 136 | [PM_IDU] = { 0x0e00000000ul, 0x0040000000ul }, | ||
| 137 | [PM_GRS] = { 0x0e00000000ul, 0x0c40000000ul }, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static int power5p_get_constraint(u64 event, unsigned long *maskp, | ||
| 141 | unsigned long *valp) | ||
| 142 | { | ||
| 143 | int pmc, byte, unit, sh; | ||
| 144 | int bit, fmask; | ||
| 145 | unsigned long mask = 0, value = 0; | ||
| 146 | |||
| 147 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 148 | if (pmc) { | ||
| 149 | if (pmc > 6) | ||
| 150 | return -1; | ||
| 151 | sh = (pmc - 1) * 2; | ||
| 152 | mask |= 2 << sh; | ||
| 153 | value |= 1 << sh; | ||
| 154 | if (pmc >= 5 && !(event == 0x500009 || event == 0x600005)) | ||
| 155 | return -1; | ||
| 156 | } | ||
| 157 | if (event & PM_BUSEVENT_MSK) { | ||
| 158 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 159 | if (unit > PM_LASTUNIT) | ||
| 160 | return -1; | ||
| 161 | if (unit == PM_ISU0_ALT) | ||
| 162 | unit = PM_ISU0; | ||
| 163 | mask |= unit_cons[unit][0]; | ||
| 164 | value |= unit_cons[unit][1]; | ||
| 165 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 166 | if (byte >= 4) { | ||
| 167 | if (unit != PM_LSU1) | ||
| 168 | return -1; | ||
| 169 | /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */ | ||
| 170 | ++unit; | ||
| 171 | byte &= 3; | ||
| 172 | } | ||
| 173 | if (unit == PM_GRS) { | ||
| 174 | bit = event & 7; | ||
| 175 | fmask = (bit == 6)? 7: 3; | ||
| 176 | sh = grsel_shift[bit]; | ||
| 177 | mask |= (unsigned long)fmask << sh; | ||
| 178 | value |= (unsigned long)((event >> PM_GRS_SH) & fmask) | ||
| 179 | << sh; | ||
| 180 | } | ||
| 181 | /* Set byte lane select field */ | ||
| 182 | mask |= 0xfUL << (24 - 4 * byte); | ||
| 183 | value |= (unsigned long)unit << (24 - 4 * byte); | ||
| 184 | } | ||
| 185 | if (pmc < 5) { | ||
| 186 | /* need a counter from PMC1-4 set */ | ||
| 187 | mask |= 0x8000000000000ul; | ||
| 188 | value |= 0x1000000000000ul; | ||
| 189 | } | ||
| 190 | *maskp = mask; | ||
| 191 | *valp = value; | ||
| 192 | return 0; | ||
| 193 | } | ||
| 194 | |||
| 195 | static int power5p_limited_pmc_event(u64 event) | ||
| 196 | { | ||
| 197 | int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 198 | |||
| 199 | return pmc == 5 || pmc == 6; | ||
| 200 | } | ||
| 201 | |||
| 202 | #define MAX_ALT 3 /* at most 3 alternatives for any event */ | ||
| 203 | |||
| 204 | static const unsigned int event_alternatives[][MAX_ALT] = { | ||
| 205 | { 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */ | ||
| 206 | { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */ | ||
| 207 | { 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */ | ||
| 208 | { 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */ | ||
| 209 | { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */ | ||
| 210 | { 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */ | ||
| 211 | { 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */ | ||
| 212 | { 0x100005, 0x600005 }, /* PM_RUN_CYC */ | ||
| 213 | { 0x100009, 0x200009 }, /* PM_INST_CMPL */ | ||
| 214 | { 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */ | ||
| 215 | { 0x300009, 0x400009 }, /* PM_INST_DISP */ | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Scan the alternatives table for a match and return the | ||
| 220 | * index into the alternatives table if found, else -1. | ||
| 221 | */ | ||
| 222 | static int find_alternative(unsigned int event) | ||
| 223 | { | ||
| 224 | int i, j; | ||
| 225 | |||
| 226 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | ||
| 227 | if (event < event_alternatives[i][0]) | ||
| 228 | break; | ||
| 229 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | ||
| 230 | if (event == event_alternatives[i][j]) | ||
| 231 | return i; | ||
| 232 | } | ||
| 233 | return -1; | ||
| 234 | } | ||
| 235 | |||
| 236 | static const unsigned char bytedecode_alternatives[4][4] = { | ||
| 237 | /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 }, | ||
| 238 | /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e }, | ||
| 239 | /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 }, | ||
| 240 | /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e } | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* | ||
| 244 | * Some direct events for decodes of event bus byte 3 have alternative | ||
| 245 | * PMCSEL values on other counters. This returns the alternative | ||
| 246 | * event code for those that do, or -1 otherwise. This also handles | ||
| 247 | * alternative PCMSEL values for add events. | ||
| 248 | */ | ||
| 249 | static s64 find_alternative_bdecode(u64 event) | ||
| 250 | { | ||
| 251 | int pmc, altpmc, pp, j; | ||
| 252 | |||
| 253 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 254 | if (pmc == 0 || pmc > 4) | ||
| 255 | return -1; | ||
| 256 | altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */ | ||
| 257 | pp = event & PM_PMCSEL_MSK; | ||
| 258 | for (j = 0; j < 4; ++j) { | ||
| 259 | if (bytedecode_alternatives[pmc - 1][j] == pp) { | ||
| 260 | return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) | | ||
| 261 | (altpmc << PM_PMC_SH) | | ||
| 262 | bytedecode_alternatives[altpmc - 1][j]; | ||
| 263 | } | ||
| 264 | } | ||
| 265 | |||
| 266 | /* new decode alternatives for power5+ */ | ||
| 267 | if (pmc == 1 && (pp == 0x0d || pp == 0x0e)) | ||
| 268 | return event + (2 << PM_PMC_SH) + (0x2e - 0x0d); | ||
| 269 | if (pmc == 3 && (pp == 0x2e || pp == 0x2f)) | ||
| 270 | return event - (2 << PM_PMC_SH) - (0x2e - 0x0d); | ||
| 271 | |||
| 272 | /* alternative add event encodings */ | ||
| 273 | if (pp == 0x10 || pp == 0x28) | ||
| 274 | return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) | | ||
| 275 | (altpmc << PM_PMC_SH); | ||
| 276 | |||
| 277 | return -1; | ||
| 278 | } | ||
| 279 | |||
| 280 | static int power5p_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 281 | { | ||
| 282 | int i, j, nalt = 1; | ||
| 283 | int nlim; | ||
| 284 | s64 ae; | ||
| 285 | |||
| 286 | alt[0] = event; | ||
| 287 | nalt = 1; | ||
| 288 | nlim = power5p_limited_pmc_event(event); | ||
| 289 | i = find_alternative(event); | ||
| 290 | if (i >= 0) { | ||
| 291 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 292 | ae = event_alternatives[i][j]; | ||
| 293 | if (ae && ae != event) | ||
| 294 | alt[nalt++] = ae; | ||
| 295 | nlim += power5p_limited_pmc_event(ae); | ||
| 296 | } | ||
| 297 | } else { | ||
| 298 | ae = find_alternative_bdecode(event); | ||
| 299 | if (ae > 0) | ||
| 300 | alt[nalt++] = ae; | ||
| 301 | } | ||
| 302 | |||
| 303 | if (flags & PPMU_ONLY_COUNT_RUN) { | ||
| 304 | /* | ||
| 305 | * We're only counting in RUN state, | ||
| 306 | * so PM_CYC is equivalent to PM_RUN_CYC | ||
| 307 | * and PM_INST_CMPL === PM_RUN_INST_CMPL. | ||
| 308 | * This doesn't include alternatives that don't provide | ||
| 309 | * any extra flexibility in assigning PMCs (e.g. | ||
| 310 | * 0x100005 for PM_RUN_CYC vs. 0xf for PM_CYC). | ||
| 311 | * Note that even with these additional alternatives | ||
| 312 | * we never end up with more than 3 alternatives for any event. | ||
| 313 | */ | ||
| 314 | j = nalt; | ||
| 315 | for (i = 0; i < nalt; ++i) { | ||
| 316 | switch (alt[i]) { | ||
| 317 | case 0xf: /* PM_CYC */ | ||
| 318 | alt[j++] = 0x600005; /* PM_RUN_CYC */ | ||
| 319 | ++nlim; | ||
| 320 | break; | ||
| 321 | case 0x600005: /* PM_RUN_CYC */ | ||
| 322 | alt[j++] = 0xf; | ||
| 323 | break; | ||
| 324 | case 0x100009: /* PM_INST_CMPL */ | ||
| 325 | alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */ | ||
| 326 | ++nlim; | ||
| 327 | break; | ||
| 328 | case 0x500009: /* PM_RUN_INST_CMPL */ | ||
| 329 | alt[j++] = 0x100009; /* PM_INST_CMPL */ | ||
| 330 | alt[j++] = 0x200009; | ||
| 331 | break; | ||
| 332 | } | ||
| 333 | } | ||
| 334 | nalt = j; | ||
| 335 | } | ||
| 336 | |||
| 337 | if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) { | ||
| 338 | /* remove the limited PMC events */ | ||
| 339 | j = 0; | ||
| 340 | for (i = 0; i < nalt; ++i) { | ||
| 341 | if (!power5p_limited_pmc_event(alt[i])) { | ||
| 342 | alt[j] = alt[i]; | ||
| 343 | ++j; | ||
| 344 | } | ||
| 345 | } | ||
| 346 | nalt = j; | ||
| 347 | } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) { | ||
| 348 | /* remove all but the limited PMC events */ | ||
| 349 | j = 0; | ||
| 350 | for (i = 0; i < nalt; ++i) { | ||
| 351 | if (power5p_limited_pmc_event(alt[i])) { | ||
| 352 | alt[j] = alt[i]; | ||
| 353 | ++j; | ||
| 354 | } | ||
| 355 | } | ||
| 356 | nalt = j; | ||
| 357 | } | ||
| 358 | |||
| 359 | return nalt; | ||
| 360 | } | ||
| 361 | |||
| 362 | /* | ||
| 363 | * Map of which direct events on which PMCs are marked instruction events. | ||
| 364 | * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event. | ||
| 365 | * Bit 0 is set if it is marked for all PMCs. | ||
| 366 | * The 0x80 bit indicates a byte decode PMCSEL value. | ||
| 367 | */ | ||
| 368 | static unsigned char direct_event_is_marked[0x28] = { | ||
| 369 | 0, /* 00 */ | ||
| 370 | 0x1f, /* 01 PM_IOPS_CMPL */ | ||
| 371 | 0x2, /* 02 PM_MRK_GRP_DISP */ | ||
| 372 | 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */ | ||
| 373 | 0, /* 04 */ | ||
| 374 | 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */ | ||
| 375 | 0x80, /* 06 */ | ||
| 376 | 0x80, /* 07 */ | ||
| 377 | 0, 0, 0,/* 08 - 0a */ | ||
| 378 | 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */ | ||
| 379 | 0, /* 0c */ | ||
| 380 | 0x80, /* 0d */ | ||
| 381 | 0x80, /* 0e */ | ||
| 382 | 0, /* 0f */ | ||
| 383 | 0, /* 10 */ | ||
| 384 | 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */ | ||
| 385 | 0, /* 12 */ | ||
| 386 | 0x10, /* 13 PM_MRK_GRP_CMPL */ | ||
| 387 | 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */ | ||
| 388 | 0x2, /* 15 PM_MRK_GRP_ISSUED */ | ||
| 389 | 0x80, /* 16 */ | ||
| 390 | 0x80, /* 17 */ | ||
| 391 | 0, 0, 0, 0, 0, | ||
| 392 | 0x80, /* 1d */ | ||
| 393 | 0x80, /* 1e */ | ||
| 394 | 0, /* 1f */ | ||
| 395 | 0x80, /* 20 */ | ||
| 396 | 0x80, /* 21 */ | ||
| 397 | 0x80, /* 22 */ | ||
| 398 | 0x80, /* 23 */ | ||
| 399 | 0x80, /* 24 */ | ||
| 400 | 0x80, /* 25 */ | ||
| 401 | 0x80, /* 26 */ | ||
| 402 | 0x80, /* 27 */ | ||
| 403 | }; | ||
| 404 | |||
| 405 | /* | ||
| 406 | * Returns 1 if event counts things relating to marked instructions | ||
| 407 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 408 | */ | ||
| 409 | static int power5p_marked_instr_event(u64 event) | ||
| 410 | { | ||
| 411 | int pmc, psel; | ||
| 412 | int bit, byte, unit; | ||
| 413 | u32 mask; | ||
| 414 | |||
| 415 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 416 | psel = event & PM_PMCSEL_MSK; | ||
| 417 | if (pmc >= 5) | ||
| 418 | return 0; | ||
| 419 | |||
| 420 | bit = -1; | ||
| 421 | if (psel < sizeof(direct_event_is_marked)) { | ||
| 422 | if (direct_event_is_marked[psel] & (1 << pmc)) | ||
| 423 | return 1; | ||
| 424 | if (direct_event_is_marked[psel] & 0x80) | ||
| 425 | bit = 4; | ||
| 426 | else if (psel == 0x08) | ||
| 427 | bit = pmc - 1; | ||
| 428 | else if (psel == 0x10) | ||
| 429 | bit = 4 - pmc; | ||
| 430 | else if (psel == 0x1b && (pmc == 1 || pmc == 3)) | ||
| 431 | bit = 4; | ||
| 432 | } else if ((psel & 0x48) == 0x40) { | ||
| 433 | bit = psel & 7; | ||
| 434 | } else if (psel == 0x28) { | ||
| 435 | bit = pmc - 1; | ||
| 436 | } else if (pmc == 3 && (psel == 0x2e || psel == 0x2f)) { | ||
| 437 | bit = 4; | ||
| 438 | } | ||
| 439 | |||
| 440 | if (!(event & PM_BUSEVENT_MSK) || bit == -1) | ||
| 441 | return 0; | ||
| 442 | |||
| 443 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 444 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 445 | if (unit == PM_LSU0) { | ||
| 446 | /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */ | ||
| 447 | mask = 0x5dff00; | ||
| 448 | } else if (unit == PM_LSU1 && byte >= 4) { | ||
| 449 | byte -= 4; | ||
| 450 | /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */ | ||
| 451 | mask = 0x5f11c000; | ||
| 452 | } else | ||
| 453 | return 0; | ||
| 454 | |||
| 455 | return (mask >> (byte * 8 + bit)) & 1; | ||
| 456 | } | ||
| 457 | |||
| 458 | static int power5p_compute_mmcr(u64 event[], int n_ev, | ||
| 459 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 460 | { | ||
| 461 | unsigned long mmcr1 = 0; | ||
| 462 | unsigned long mmcra = 0; | ||
| 463 | unsigned int pmc, unit, byte, psel; | ||
| 464 | unsigned int ttm; | ||
| 465 | int i, isbus, bit, grsel; | ||
| 466 | unsigned int pmc_inuse = 0; | ||
| 467 | unsigned char busbyte[4]; | ||
| 468 | unsigned char unituse[16]; | ||
| 469 | int ttmuse; | ||
| 470 | |||
| 471 | if (n_ev > 6) | ||
| 472 | return -1; | ||
| 473 | |||
| 474 | /* First pass to count resource use */ | ||
| 475 | memset(busbyte, 0, sizeof(busbyte)); | ||
| 476 | memset(unituse, 0, sizeof(unituse)); | ||
| 477 | for (i = 0; i < n_ev; ++i) { | ||
| 478 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 479 | if (pmc) { | ||
| 480 | if (pmc > 6) | ||
| 481 | return -1; | ||
| 482 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 483 | return -1; | ||
| 484 | pmc_inuse |= 1 << (pmc - 1); | ||
| 485 | } | ||
| 486 | if (event[i] & PM_BUSEVENT_MSK) { | ||
| 487 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 488 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 489 | if (unit > PM_LASTUNIT) | ||
| 490 | return -1; | ||
| 491 | if (unit == PM_ISU0_ALT) | ||
| 492 | unit = PM_ISU0; | ||
| 493 | if (byte >= 4) { | ||
| 494 | if (unit != PM_LSU1) | ||
| 495 | return -1; | ||
| 496 | ++unit; | ||
| 497 | byte &= 3; | ||
| 498 | } | ||
| 499 | if (busbyte[byte] && busbyte[byte] != unit) | ||
| 500 | return -1; | ||
| 501 | busbyte[byte] = unit; | ||
| 502 | unituse[unit] = 1; | ||
| 503 | } | ||
| 504 | } | ||
| 505 | |||
| 506 | /* | ||
| 507 | * Assign resources and set multiplexer selects. | ||
| 508 | * | ||
| 509 | * PM_ISU0 can go either on TTM0 or TTM1, but that's the only | ||
| 510 | * choice we have to deal with. | ||
| 511 | */ | ||
| 512 | if (unituse[PM_ISU0] & | ||
| 513 | (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) { | ||
| 514 | unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */ | ||
| 515 | unituse[PM_ISU0] = 0; | ||
| 516 | } | ||
| 517 | /* Set TTM[01]SEL fields. */ | ||
| 518 | ttmuse = 0; | ||
| 519 | for (i = PM_FPU; i <= PM_ISU1; ++i) { | ||
| 520 | if (!unituse[i]) | ||
| 521 | continue; | ||
| 522 | if (ttmuse++) | ||
| 523 | return -1; | ||
| 524 | mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; | ||
| 525 | } | ||
| 526 | ttmuse = 0; | ||
| 527 | for (; i <= PM_GRS; ++i) { | ||
| 528 | if (!unituse[i]) | ||
| 529 | continue; | ||
| 530 | if (ttmuse++) | ||
| 531 | return -1; | ||
| 532 | mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH; | ||
| 533 | } | ||
| 534 | if (ttmuse > 1) | ||
| 535 | return -1; | ||
| 536 | |||
| 537 | /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */ | ||
| 538 | for (byte = 0; byte < 4; ++byte) { | ||
| 539 | unit = busbyte[byte]; | ||
| 540 | if (!unit) | ||
| 541 | continue; | ||
| 542 | if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) { | ||
| 543 | /* get ISU0 through TTM1 rather than TTM0 */ | ||
| 544 | unit = PM_ISU0_ALT; | ||
| 545 | } else if (unit == PM_LSU1 + 1) { | ||
| 546 | /* select lower word of LSU1 for this byte */ | ||
| 547 | mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte); | ||
| 548 | } | ||
| 549 | ttm = unit >> 2; | ||
| 550 | mmcr1 |= (unsigned long)ttm | ||
| 551 | << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); | ||
| 552 | } | ||
| 553 | |||
| 554 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | ||
| 555 | for (i = 0; i < n_ev; ++i) { | ||
| 556 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 557 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 558 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 559 | psel = event[i] & PM_PMCSEL_MSK; | ||
| 560 | isbus = event[i] & PM_BUSEVENT_MSK; | ||
| 561 | if (!pmc) { | ||
| 562 | /* Bus event or any-PMC direct event */ | ||
| 563 | for (pmc = 0; pmc < 4; ++pmc) { | ||
| 564 | if (!(pmc_inuse & (1 << pmc))) | ||
| 565 | break; | ||
| 566 | } | ||
| 567 | if (pmc >= 4) | ||
| 568 | return -1; | ||
| 569 | pmc_inuse |= 1 << pmc; | ||
| 570 | } else if (pmc <= 4) { | ||
| 571 | /* Direct event */ | ||
| 572 | --pmc; | ||
| 573 | if (isbus && (byte & 2) && | ||
| 574 | (psel == 8 || psel == 0x10 || psel == 0x28)) | ||
| 575 | /* add events on higher-numbered bus */ | ||
| 576 | mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc); | ||
| 577 | } else { | ||
| 578 | /* Instructions or run cycles on PMC5/6 */ | ||
| 579 | --pmc; | ||
| 580 | } | ||
| 581 | if (isbus && unit == PM_GRS) { | ||
| 582 | bit = psel & 7; | ||
| 583 | grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; | ||
| 584 | mmcr1 |= (unsigned long)grsel << grsel_shift[bit]; | ||
| 585 | } | ||
| 586 | if (power5p_marked_instr_event(event[i])) | ||
| 587 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 588 | if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1)) | ||
| 589 | /* select alternate byte lane */ | ||
| 590 | psel |= 0x10; | ||
| 591 | if (pmc <= 3) | ||
| 592 | mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); | ||
| 593 | hwc[i] = pmc; | ||
| 594 | } | ||
| 595 | |||
| 596 | /* Return MMCRx values */ | ||
| 597 | mmcr[0] = 0; | ||
| 598 | if (pmc_inuse & 1) | ||
| 599 | mmcr[0] = MMCR0_PMC1CE; | ||
| 600 | if (pmc_inuse & 0x3e) | ||
| 601 | mmcr[0] |= MMCR0_PMCjCE; | ||
| 602 | mmcr[1] = mmcr1; | ||
| 603 | mmcr[2] = mmcra; | ||
| 604 | return 0; | ||
| 605 | } | ||
| 606 | |||
| 607 | static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 608 | { | ||
| 609 | if (pmc <= 3) | ||
| 610 | mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); | ||
| 611 | } | ||
| 612 | |||
| 613 | static int power5p_generic_events[] = { | ||
| 614 | [PERF_COUNT_HW_CPU_CYCLES] = 0xf, | ||
| 615 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x100009, | ||
| 616 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x1c10a8, /* LD_REF_L1 */ | ||
| 617 | [PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */ | ||
| 618 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */ | ||
| 619 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */ | ||
| 620 | }; | ||
| 621 | |||
| 622 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 623 | |||
| 624 | /* | ||
| 625 | * Table of generalized cache-related events. | ||
| 626 | * 0 means not supported, -1 means nonsensical, other values | ||
| 627 | * are event codes. | ||
| 628 | */ | ||
| 629 | static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 630 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 631 | [C(OP_READ)] = { 0x1c10a8, 0x3c1088 }, | ||
| 632 | [C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 }, | ||
| 633 | [C(OP_PREFETCH)] = { 0xc70e7, -1 }, | ||
| 634 | }, | ||
| 635 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 636 | [C(OP_READ)] = { 0, 0 }, | ||
| 637 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 638 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 639 | }, | ||
| 640 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 641 | [C(OP_READ)] = { 0, 0 }, | ||
| 642 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 643 | [C(OP_PREFETCH)] = { 0xc50c3, 0 }, | ||
| 644 | }, | ||
| 645 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 646 | [C(OP_READ)] = { 0xc20e4, 0x800c4 }, | ||
| 647 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 648 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 649 | }, | ||
| 650 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 651 | [C(OP_READ)] = { 0, 0x800c0 }, | ||
| 652 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 653 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 654 | }, | ||
| 655 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 656 | [C(OP_READ)] = { 0x230e4, 0x230e5 }, | ||
| 657 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 658 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 659 | }, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static struct power_pmu power5p_pmu = { | ||
| 663 | .name = "POWER5+/++", | ||
| 664 | .n_counter = 6, | ||
| 665 | .max_alternatives = MAX_ALT, | ||
| 666 | .add_fields = 0x7000000000055ul, | ||
| 667 | .test_adder = 0x3000040000000ul, | ||
| 668 | .compute_mmcr = power5p_compute_mmcr, | ||
| 669 | .get_constraint = power5p_get_constraint, | ||
| 670 | .get_alternatives = power5p_get_alternatives, | ||
| 671 | .disable_pmc = power5p_disable_pmc, | ||
| 672 | .limited_pmc_event = power5p_limited_pmc_event, | ||
| 673 | .flags = PPMU_LIMITED_PMC5_6, | ||
| 674 | .n_generic = ARRAY_SIZE(power5p_generic_events), | ||
| 675 | .generic_events = power5p_generic_events, | ||
| 676 | .cache_events = &power5p_cache_events, | ||
| 677 | }; | ||
| 678 | |||
| 679 | static int init_power5p_pmu(void) | ||
| 680 | { | ||
| 681 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+") | ||
| 682 | && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5++")) | ||
| 683 | return -ENODEV; | ||
| 684 | |||
| 685 | return register_power_pmu(&power5p_pmu); | ||
| 686 | } | ||
| 687 | |||
| 688 | arch_initcall(init_power5p_pmu); | ||
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c new file mode 100644 index 000000000000..29b2c6c0e83a --- /dev/null +++ b/arch/powerpc/kernel/power5-pmu.c | |||
| @@ -0,0 +1,627 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for POWER5 (not POWER5++) processors. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for POWER5 (not POWER5++) | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0xf | ||
| 22 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | ||
| 23 | #define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */ | ||
| 24 | #define PM_UNIT_MSK 0xf | ||
| 25 | #define PM_BYTE_SH 12 /* Byte number of event bus to use */ | ||
| 26 | #define PM_BYTE_MSK 7 | ||
| 27 | #define PM_GRS_SH 8 /* Storage subsystem mux select */ | ||
| 28 | #define PM_GRS_MSK 7 | ||
| 29 | #define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */ | ||
| 30 | #define PM_PMCSEL_MSK 0x7f | ||
| 31 | |||
| 32 | /* Values in PM_UNIT field */ | ||
| 33 | #define PM_FPU 0 | ||
| 34 | #define PM_ISU0 1 | ||
| 35 | #define PM_IFU 2 | ||
| 36 | #define PM_ISU1 3 | ||
| 37 | #define PM_IDU 4 | ||
| 38 | #define PM_ISU0_ALT 6 | ||
| 39 | #define PM_GRS 7 | ||
| 40 | #define PM_LSU0 8 | ||
| 41 | #define PM_LSU1 0xc | ||
| 42 | #define PM_LASTUNIT 0xc | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Bits in MMCR1 for POWER5 | ||
| 46 | */ | ||
| 47 | #define MMCR1_TTM0SEL_SH 62 | ||
| 48 | #define MMCR1_TTM1SEL_SH 60 | ||
| 49 | #define MMCR1_TTM2SEL_SH 58 | ||
| 50 | #define MMCR1_TTM3SEL_SH 56 | ||
| 51 | #define MMCR1_TTMSEL_MSK 3 | ||
| 52 | #define MMCR1_TD_CP_DBG0SEL_SH 54 | ||
| 53 | #define MMCR1_TD_CP_DBG1SEL_SH 52 | ||
| 54 | #define MMCR1_TD_CP_DBG2SEL_SH 50 | ||
| 55 | #define MMCR1_TD_CP_DBG3SEL_SH 48 | ||
| 56 | #define MMCR1_GRS_L2SEL_SH 46 | ||
| 57 | #define MMCR1_GRS_L2SEL_MSK 3 | ||
| 58 | #define MMCR1_GRS_L3SEL_SH 44 | ||
| 59 | #define MMCR1_GRS_L3SEL_MSK 3 | ||
| 60 | #define MMCR1_GRS_MCSEL_SH 41 | ||
| 61 | #define MMCR1_GRS_MCSEL_MSK 7 | ||
| 62 | #define MMCR1_GRS_FABSEL_SH 39 | ||
| 63 | #define MMCR1_GRS_FABSEL_MSK 3 | ||
| 64 | #define MMCR1_PMC1_ADDER_SEL_SH 35 | ||
| 65 | #define MMCR1_PMC2_ADDER_SEL_SH 34 | ||
| 66 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | ||
| 67 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | ||
| 68 | #define MMCR1_PMC1SEL_SH 25 | ||
| 69 | #define MMCR1_PMC2SEL_SH 17 | ||
| 70 | #define MMCR1_PMC3SEL_SH 9 | ||
| 71 | #define MMCR1_PMC4SEL_SH 1 | ||
| 72 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | ||
| 73 | #define MMCR1_PMCSEL_MSK 0x7f | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Bits in MMCRA | ||
| 77 | */ | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Layout of constraint bits: | ||
| 81 | * 6666555555555544444444443333333333222222222211111111110000000000 | ||
| 82 | * 3210987654321098765432109876543210987654321098765432109876543210 | ||
| 83 | * <><>[ ><><>< ><> [ >[ >[ >< >< >< >< ><><><><><><> | ||
| 84 | * T0T1 NC G0G1G2 G3 UC PS1PS2 B0 B1 B2 B3 P6P5P4P3P2P1 | ||
| 85 | * | ||
| 86 | * T0 - TTM0 constraint | ||
| 87 | * 54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000 | ||
| 88 | * | ||
| 89 | * T1 - TTM1 constraint | ||
| 90 | * 52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000 | ||
| 91 | * | ||
| 92 | * NC - number of counters | ||
| 93 | * 51: NC error 0x0008_0000_0000_0000 | ||
| 94 | * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000 | ||
| 95 | * | ||
| 96 | * G0..G3 - GRS mux constraints | ||
| 97 | * 46-47: GRS_L2SEL value | ||
| 98 | * 44-45: GRS_L3SEL value | ||
| 99 | * 41-44: GRS_MCSEL value | ||
| 100 | * 39-40: GRS_FABSEL value | ||
| 101 | * Note that these match up with their bit positions in MMCR1 | ||
| 102 | * | ||
| 103 | * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS | ||
| 104 | * 37: UC3 error 0x20_0000_0000 | ||
| 105 | * 36: FPU|IFU|ISU1 events needed 0x10_0000_0000 | ||
| 106 | * 35: ISU0 events needed 0x08_0000_0000 | ||
| 107 | * 34: IDU|GRS events needed 0x04_0000_0000 | ||
| 108 | * | ||
| 109 | * PS1 | ||
| 110 | * 33: PS1 error 0x2_0000_0000 | ||
| 111 | * 31-32: count of events needing PMC1/2 0x1_8000_0000 | ||
| 112 | * | ||
| 113 | * PS2 | ||
| 114 | * 30: PS2 error 0x4000_0000 | ||
| 115 | * 28-29: count of events needing PMC3/4 0x3000_0000 | ||
| 116 | * | ||
| 117 | * B0 | ||
| 118 | * 24-27: Byte 0 event source 0x0f00_0000 | ||
| 119 | * Encoding as for the event code | ||
| 120 | * | ||
| 121 | * B1, B2, B3 | ||
| 122 | * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources | ||
| 123 | * | ||
| 124 | * P1..P6 | ||
| 125 | * 0-11: Count of events needing PMC1..PMC6 | ||
| 126 | */ | ||
| 127 | |||
| 128 | static const int grsel_shift[8] = { | ||
| 129 | MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, | ||
| 130 | MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, | ||
| 131 | MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* Masks and values for using events from the various units */ | ||
| 135 | static unsigned long unit_cons[PM_LASTUNIT+1][2] = { | ||
| 136 | [PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul }, | ||
| 137 | [PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul }, | ||
| 138 | [PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul }, | ||
| 139 | [PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul }, | ||
| 140 | [PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul }, | ||
| 141 | [PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul }, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static int power5_get_constraint(u64 event, unsigned long *maskp, | ||
| 145 | unsigned long *valp) | ||
| 146 | { | ||
| 147 | int pmc, byte, unit, sh; | ||
| 148 | int bit, fmask; | ||
| 149 | unsigned long mask = 0, value = 0; | ||
| 150 | int grp = -1; | ||
| 151 | |||
| 152 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 153 | if (pmc) { | ||
| 154 | if (pmc > 6) | ||
| 155 | return -1; | ||
| 156 | sh = (pmc - 1) * 2; | ||
| 157 | mask |= 2 << sh; | ||
| 158 | value |= 1 << sh; | ||
| 159 | if (pmc <= 4) | ||
| 160 | grp = (pmc - 1) >> 1; | ||
| 161 | else if (event != 0x500009 && event != 0x600005) | ||
| 162 | return -1; | ||
| 163 | } | ||
| 164 | if (event & PM_BUSEVENT_MSK) { | ||
| 165 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 166 | if (unit > PM_LASTUNIT) | ||
| 167 | return -1; | ||
| 168 | if (unit == PM_ISU0_ALT) | ||
| 169 | unit = PM_ISU0; | ||
| 170 | mask |= unit_cons[unit][0]; | ||
| 171 | value |= unit_cons[unit][1]; | ||
| 172 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 173 | if (byte >= 4) { | ||
| 174 | if (unit != PM_LSU1) | ||
| 175 | return -1; | ||
| 176 | /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */ | ||
| 177 | ++unit; | ||
| 178 | byte &= 3; | ||
| 179 | } | ||
| 180 | if (unit == PM_GRS) { | ||
| 181 | bit = event & 7; | ||
| 182 | fmask = (bit == 6)? 7: 3; | ||
| 183 | sh = grsel_shift[bit]; | ||
| 184 | mask |= (unsigned long)fmask << sh; | ||
| 185 | value |= (unsigned long)((event >> PM_GRS_SH) & fmask) | ||
| 186 | << sh; | ||
| 187 | } | ||
| 188 | /* | ||
| 189 | * Bus events on bytes 0 and 2 can be counted | ||
| 190 | * on PMC1/2; bytes 1 and 3 on PMC3/4. | ||
| 191 | */ | ||
| 192 | if (!pmc) | ||
| 193 | grp = byte & 1; | ||
| 194 | /* Set byte lane select field */ | ||
| 195 | mask |= 0xfUL << (24 - 4 * byte); | ||
| 196 | value |= (unsigned long)unit << (24 - 4 * byte); | ||
| 197 | } | ||
| 198 | if (grp == 0) { | ||
| 199 | /* increment PMC1/2 field */ | ||
| 200 | mask |= 0x200000000ul; | ||
| 201 | value |= 0x080000000ul; | ||
| 202 | } else if (grp == 1) { | ||
| 203 | /* increment PMC3/4 field */ | ||
| 204 | mask |= 0x40000000ul; | ||
| 205 | value |= 0x10000000ul; | ||
| 206 | } | ||
| 207 | if (pmc < 5) { | ||
| 208 | /* need a counter from PMC1-4 set */ | ||
| 209 | mask |= 0x8000000000000ul; | ||
| 210 | value |= 0x1000000000000ul; | ||
| 211 | } | ||
| 212 | *maskp = mask; | ||
| 213 | *valp = value; | ||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | |||
| 217 | #define MAX_ALT 3 /* at most 3 alternatives for any event */ | ||
| 218 | |||
| 219 | static const unsigned int event_alternatives[][MAX_ALT] = { | ||
| 220 | { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */ | ||
| 221 | { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */ | ||
| 222 | { 0x100005, 0x600005 }, /* PM_RUN_CYC */ | ||
| 223 | { 0x100009, 0x200009, 0x500009 }, /* PM_INST_CMPL */ | ||
| 224 | { 0x300009, 0x400009 }, /* PM_INST_DISP */ | ||
| 225 | }; | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Scan the alternatives table for a match and return the | ||
| 229 | * index into the alternatives table if found, else -1. | ||
| 230 | */ | ||
| 231 | static int find_alternative(u64 event) | ||
| 232 | { | ||
| 233 | int i, j; | ||
| 234 | |||
| 235 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | ||
| 236 | if (event < event_alternatives[i][0]) | ||
| 237 | break; | ||
| 238 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | ||
| 239 | if (event == event_alternatives[i][j]) | ||
| 240 | return i; | ||
| 241 | } | ||
| 242 | return -1; | ||
| 243 | } | ||
| 244 | |||
| 245 | static const unsigned char bytedecode_alternatives[4][4] = { | ||
| 246 | /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 }, | ||
| 247 | /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e }, | ||
| 248 | /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 }, | ||
| 249 | /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e } | ||
| 250 | }; | ||
| 251 | |||
| 252 | /* | ||
| 253 | * Some direct events for decodes of event bus byte 3 have alternative | ||
| 254 | * PMCSEL values on other counters. This returns the alternative | ||
| 255 | * event code for those that do, or -1 otherwise. | ||
| 256 | */ | ||
| 257 | static s64 find_alternative_bdecode(u64 event) | ||
| 258 | { | ||
| 259 | int pmc, altpmc, pp, j; | ||
| 260 | |||
| 261 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 262 | if (pmc == 0 || pmc > 4) | ||
| 263 | return -1; | ||
| 264 | altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */ | ||
| 265 | pp = event & PM_PMCSEL_MSK; | ||
| 266 | for (j = 0; j < 4; ++j) { | ||
| 267 | if (bytedecode_alternatives[pmc - 1][j] == pp) { | ||
| 268 | return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) | | ||
| 269 | (altpmc << PM_PMC_SH) | | ||
| 270 | bytedecode_alternatives[altpmc - 1][j]; | ||
| 271 | } | ||
| 272 | } | ||
| 273 | return -1; | ||
| 274 | } | ||
| 275 | |||
| 276 | static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 277 | { | ||
| 278 | int i, j, nalt = 1; | ||
| 279 | s64 ae; | ||
| 280 | |||
| 281 | alt[0] = event; | ||
| 282 | nalt = 1; | ||
| 283 | i = find_alternative(event); | ||
| 284 | if (i >= 0) { | ||
| 285 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 286 | ae = event_alternatives[i][j]; | ||
| 287 | if (ae && ae != event) | ||
| 288 | alt[nalt++] = ae; | ||
| 289 | } | ||
| 290 | } else { | ||
| 291 | ae = find_alternative_bdecode(event); | ||
| 292 | if (ae > 0) | ||
| 293 | alt[nalt++] = ae; | ||
| 294 | } | ||
| 295 | return nalt; | ||
| 296 | } | ||
| 297 | |||
| 298 | /* | ||
| 299 | * Map of which direct events on which PMCs are marked instruction events. | ||
| 300 | * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event. | ||
| 301 | * Bit 0 is set if it is marked for all PMCs. | ||
| 302 | * The 0x80 bit indicates a byte decode PMCSEL value. | ||
| 303 | */ | ||
| 304 | static unsigned char direct_event_is_marked[0x28] = { | ||
| 305 | 0, /* 00 */ | ||
| 306 | 0x1f, /* 01 PM_IOPS_CMPL */ | ||
| 307 | 0x2, /* 02 PM_MRK_GRP_DISP */ | ||
| 308 | 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */ | ||
| 309 | 0, /* 04 */ | ||
| 310 | 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */ | ||
| 311 | 0x80, /* 06 */ | ||
| 312 | 0x80, /* 07 */ | ||
| 313 | 0, 0, 0,/* 08 - 0a */ | ||
| 314 | 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */ | ||
| 315 | 0, /* 0c */ | ||
| 316 | 0x80, /* 0d */ | ||
| 317 | 0x80, /* 0e */ | ||
| 318 | 0, /* 0f */ | ||
| 319 | 0, /* 10 */ | ||
| 320 | 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */ | ||
| 321 | 0, /* 12 */ | ||
| 322 | 0x10, /* 13 PM_MRK_GRP_CMPL */ | ||
| 323 | 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */ | ||
| 324 | 0x2, /* 15 PM_MRK_GRP_ISSUED */ | ||
| 325 | 0x80, /* 16 */ | ||
| 326 | 0x80, /* 17 */ | ||
| 327 | 0, 0, 0, 0, 0, | ||
| 328 | 0x80, /* 1d */ | ||
| 329 | 0x80, /* 1e */ | ||
| 330 | 0, /* 1f */ | ||
| 331 | 0x80, /* 20 */ | ||
| 332 | 0x80, /* 21 */ | ||
| 333 | 0x80, /* 22 */ | ||
| 334 | 0x80, /* 23 */ | ||
| 335 | 0x80, /* 24 */ | ||
| 336 | 0x80, /* 25 */ | ||
| 337 | 0x80, /* 26 */ | ||
| 338 | 0x80, /* 27 */ | ||
| 339 | }; | ||
| 340 | |||
| 341 | /* | ||
| 342 | * Returns 1 if event counts things relating to marked instructions | ||
| 343 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 344 | */ | ||
| 345 | static int power5_marked_instr_event(u64 event) | ||
| 346 | { | ||
| 347 | int pmc, psel; | ||
| 348 | int bit, byte, unit; | ||
| 349 | u32 mask; | ||
| 350 | |||
| 351 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 352 | psel = event & PM_PMCSEL_MSK; | ||
| 353 | if (pmc >= 5) | ||
| 354 | return 0; | ||
| 355 | |||
| 356 | bit = -1; | ||
| 357 | if (psel < sizeof(direct_event_is_marked)) { | ||
| 358 | if (direct_event_is_marked[psel] & (1 << pmc)) | ||
| 359 | return 1; | ||
| 360 | if (direct_event_is_marked[psel] & 0x80) | ||
| 361 | bit = 4; | ||
| 362 | else if (psel == 0x08) | ||
| 363 | bit = pmc - 1; | ||
| 364 | else if (psel == 0x10) | ||
| 365 | bit = 4 - pmc; | ||
| 366 | else if (psel == 0x1b && (pmc == 1 || pmc == 3)) | ||
| 367 | bit = 4; | ||
| 368 | } else if ((psel & 0x58) == 0x40) | ||
| 369 | bit = psel & 7; | ||
| 370 | |||
| 371 | if (!(event & PM_BUSEVENT_MSK)) | ||
| 372 | return 0; | ||
| 373 | |||
| 374 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 375 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 376 | if (unit == PM_LSU0) { | ||
| 377 | /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */ | ||
| 378 | mask = 0x5dff00; | ||
| 379 | } else if (unit == PM_LSU1 && byte >= 4) { | ||
| 380 | byte -= 4; | ||
| 381 | /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */ | ||
| 382 | mask = 0x5f00c0aa; | ||
| 383 | } else | ||
| 384 | return 0; | ||
| 385 | |||
| 386 | return (mask >> (byte * 8 + bit)) & 1; | ||
| 387 | } | ||
| 388 | |||
| 389 | static int power5_compute_mmcr(u64 event[], int n_ev, | ||
| 390 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 391 | { | ||
| 392 | unsigned long mmcr1 = 0; | ||
| 393 | unsigned long mmcra = 0; | ||
| 394 | unsigned int pmc, unit, byte, psel; | ||
| 395 | unsigned int ttm, grp; | ||
| 396 | int i, isbus, bit, grsel; | ||
| 397 | unsigned int pmc_inuse = 0; | ||
| 398 | unsigned int pmc_grp_use[2]; | ||
| 399 | unsigned char busbyte[4]; | ||
| 400 | unsigned char unituse[16]; | ||
| 401 | int ttmuse; | ||
| 402 | |||
| 403 | if (n_ev > 6) | ||
| 404 | return -1; | ||
| 405 | |||
| 406 | /* First pass to count resource use */ | ||
| 407 | pmc_grp_use[0] = pmc_grp_use[1] = 0; | ||
| 408 | memset(busbyte, 0, sizeof(busbyte)); | ||
| 409 | memset(unituse, 0, sizeof(unituse)); | ||
| 410 | for (i = 0; i < n_ev; ++i) { | ||
| 411 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 412 | if (pmc) { | ||
| 413 | if (pmc > 6) | ||
| 414 | return -1; | ||
| 415 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 416 | return -1; | ||
| 417 | pmc_inuse |= 1 << (pmc - 1); | ||
| 418 | /* count 1/2 vs 3/4 use */ | ||
| 419 | if (pmc <= 4) | ||
| 420 | ++pmc_grp_use[(pmc - 1) >> 1]; | ||
| 421 | } | ||
| 422 | if (event[i] & PM_BUSEVENT_MSK) { | ||
| 423 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 424 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 425 | if (unit > PM_LASTUNIT) | ||
| 426 | return -1; | ||
| 427 | if (unit == PM_ISU0_ALT) | ||
| 428 | unit = PM_ISU0; | ||
| 429 | if (byte >= 4) { | ||
| 430 | if (unit != PM_LSU1) | ||
| 431 | return -1; | ||
| 432 | ++unit; | ||
| 433 | byte &= 3; | ||
| 434 | } | ||
| 435 | if (!pmc) | ||
| 436 | ++pmc_grp_use[byte & 1]; | ||
| 437 | if (busbyte[byte] && busbyte[byte] != unit) | ||
| 438 | return -1; | ||
| 439 | busbyte[byte] = unit; | ||
| 440 | unituse[unit] = 1; | ||
| 441 | } | ||
| 442 | } | ||
| 443 | if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2) | ||
| 444 | return -1; | ||
| 445 | |||
| 446 | /* | ||
| 447 | * Assign resources and set multiplexer selects. | ||
| 448 | * | ||
| 449 | * PM_ISU0 can go either on TTM0 or TTM1, but that's the only | ||
| 450 | * choice we have to deal with. | ||
| 451 | */ | ||
| 452 | if (unituse[PM_ISU0] & | ||
| 453 | (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) { | ||
| 454 | unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */ | ||
| 455 | unituse[PM_ISU0] = 0; | ||
| 456 | } | ||
| 457 | /* Set TTM[01]SEL fields. */ | ||
| 458 | ttmuse = 0; | ||
| 459 | for (i = PM_FPU; i <= PM_ISU1; ++i) { | ||
| 460 | if (!unituse[i]) | ||
| 461 | continue; | ||
| 462 | if (ttmuse++) | ||
| 463 | return -1; | ||
| 464 | mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; | ||
| 465 | } | ||
| 466 | ttmuse = 0; | ||
| 467 | for (; i <= PM_GRS; ++i) { | ||
| 468 | if (!unituse[i]) | ||
| 469 | continue; | ||
| 470 | if (ttmuse++) | ||
| 471 | return -1; | ||
| 472 | mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH; | ||
| 473 | } | ||
| 474 | if (ttmuse > 1) | ||
| 475 | return -1; | ||
| 476 | |||
| 477 | /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */ | ||
| 478 | for (byte = 0; byte < 4; ++byte) { | ||
| 479 | unit = busbyte[byte]; | ||
| 480 | if (!unit) | ||
| 481 | continue; | ||
| 482 | if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) { | ||
| 483 | /* get ISU0 through TTM1 rather than TTM0 */ | ||
| 484 | unit = PM_ISU0_ALT; | ||
| 485 | } else if (unit == PM_LSU1 + 1) { | ||
| 486 | /* select lower word of LSU1 for this byte */ | ||
| 487 | mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte); | ||
| 488 | } | ||
| 489 | ttm = unit >> 2; | ||
| 490 | mmcr1 |= (unsigned long)ttm | ||
| 491 | << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); | ||
| 492 | } | ||
| 493 | |||
| 494 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | ||
| 495 | for (i = 0; i < n_ev; ++i) { | ||
| 496 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 497 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 498 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 499 | psel = event[i] & PM_PMCSEL_MSK; | ||
| 500 | isbus = event[i] & PM_BUSEVENT_MSK; | ||
| 501 | if (!pmc) { | ||
| 502 | /* Bus event or any-PMC direct event */ | ||
| 503 | for (pmc = 0; pmc < 4; ++pmc) { | ||
| 504 | if (pmc_inuse & (1 << pmc)) | ||
| 505 | continue; | ||
| 506 | grp = (pmc >> 1) & 1; | ||
| 507 | if (isbus) { | ||
| 508 | if (grp == (byte & 1)) | ||
| 509 | break; | ||
| 510 | } else if (pmc_grp_use[grp] < 2) { | ||
| 511 | ++pmc_grp_use[grp]; | ||
| 512 | break; | ||
| 513 | } | ||
| 514 | } | ||
| 515 | pmc_inuse |= 1 << pmc; | ||
| 516 | } else if (pmc <= 4) { | ||
| 517 | /* Direct event */ | ||
| 518 | --pmc; | ||
| 519 | if ((psel == 8 || psel == 0x10) && isbus && (byte & 2)) | ||
| 520 | /* add events on higher-numbered bus */ | ||
| 521 | mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc); | ||
| 522 | } else { | ||
| 523 | /* Instructions or run cycles on PMC5/6 */ | ||
| 524 | --pmc; | ||
| 525 | } | ||
| 526 | if (isbus && unit == PM_GRS) { | ||
| 527 | bit = psel & 7; | ||
| 528 | grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; | ||
| 529 | mmcr1 |= (unsigned long)grsel << grsel_shift[bit]; | ||
| 530 | } | ||
| 531 | if (power5_marked_instr_event(event[i])) | ||
| 532 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 533 | if (pmc <= 3) | ||
| 534 | mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); | ||
| 535 | hwc[i] = pmc; | ||
| 536 | } | ||
| 537 | |||
| 538 | /* Return MMCRx values */ | ||
| 539 | mmcr[0] = 0; | ||
| 540 | if (pmc_inuse & 1) | ||
| 541 | mmcr[0] = MMCR0_PMC1CE; | ||
| 542 | if (pmc_inuse & 0x3e) | ||
| 543 | mmcr[0] |= MMCR0_PMCjCE; | ||
| 544 | mmcr[1] = mmcr1; | ||
| 545 | mmcr[2] = mmcra; | ||
| 546 | return 0; | ||
| 547 | } | ||
| 548 | |||
| 549 | static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 550 | { | ||
| 551 | if (pmc <= 3) | ||
| 552 | mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); | ||
| 553 | } | ||
| 554 | |||
| 555 | static int power5_generic_events[] = { | ||
| 556 | [PERF_COUNT_HW_CPU_CYCLES] = 0xf, | ||
| 557 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x100009, | ||
| 558 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4c1090, /* LD_REF_L1 */ | ||
| 559 | [PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */ | ||
| 560 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */ | ||
| 561 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */ | ||
| 562 | }; | ||
| 563 | |||
| 564 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 565 | |||
| 566 | /* | ||
| 567 | * Table of generalized cache-related events. | ||
| 568 | * 0 means not supported, -1 means nonsensical, other values | ||
| 569 | * are event codes. | ||
| 570 | */ | ||
| 571 | static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 572 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 573 | [C(OP_READ)] = { 0x4c1090, 0x3c1088 }, | ||
| 574 | [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 }, | ||
| 575 | [C(OP_PREFETCH)] = { 0xc70e7, 0 }, | ||
| 576 | }, | ||
| 577 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 578 | [C(OP_READ)] = { 0, 0 }, | ||
| 579 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 580 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 581 | }, | ||
| 582 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 583 | [C(OP_READ)] = { 0, 0x3c309b }, | ||
| 584 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 585 | [C(OP_PREFETCH)] = { 0xc50c3, 0 }, | ||
| 586 | }, | ||
| 587 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 588 | [C(OP_READ)] = { 0x2c4090, 0x800c4 }, | ||
| 589 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 590 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 591 | }, | ||
| 592 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 593 | [C(OP_READ)] = { 0, 0x800c0 }, | ||
| 594 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 595 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 596 | }, | ||
| 597 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 598 | [C(OP_READ)] = { 0x230e4, 0x230e5 }, | ||
| 599 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 600 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 601 | }, | ||
| 602 | }; | ||
| 603 | |||
| 604 | static struct power_pmu power5_pmu = { | ||
| 605 | .name = "POWER5", | ||
| 606 | .n_counter = 6, | ||
| 607 | .max_alternatives = MAX_ALT, | ||
| 608 | .add_fields = 0x7000090000555ul, | ||
| 609 | .test_adder = 0x3000490000000ul, | ||
| 610 | .compute_mmcr = power5_compute_mmcr, | ||
| 611 | .get_constraint = power5_get_constraint, | ||
| 612 | .get_alternatives = power5_get_alternatives, | ||
| 613 | .disable_pmc = power5_disable_pmc, | ||
| 614 | .n_generic = ARRAY_SIZE(power5_generic_events), | ||
| 615 | .generic_events = power5_generic_events, | ||
| 616 | .cache_events = &power5_cache_events, | ||
| 617 | }; | ||
| 618 | |||
| 619 | static int init_power5_pmu(void) | ||
| 620 | { | ||
| 621 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5")) | ||
| 622 | return -ENODEV; | ||
| 623 | |||
| 624 | return register_power_pmu(&power5_pmu); | ||
| 625 | } | ||
| 626 | |||
| 627 | arch_initcall(init_power5_pmu); | ||
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c new file mode 100644 index 000000000000..09ae5bf5bda7 --- /dev/null +++ b/arch/powerpc/kernel/power6-pmu.c | |||
| @@ -0,0 +1,546 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for POWER6 processors. | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for POWER6 | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0x7 | ||
| 22 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | ||
| 23 | #define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */ | ||
| 24 | #define PM_UNIT_MSK 0xf | ||
| 25 | #define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH) | ||
| 26 | #define PM_LLAV 0x8000 /* Load lookahead match value */ | ||
| 27 | #define PM_LLA 0x4000 /* Load lookahead match enable */ | ||
| 28 | #define PM_BYTE_SH 12 /* Byte of event bus to use */ | ||
| 29 | #define PM_BYTE_MSK 3 | ||
| 30 | #define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */ | ||
| 31 | #define PM_SUBUNIT_MSK 7 | ||
| 32 | #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH) | ||
| 33 | #define PM_PMCSEL_MSK 0xff /* PMCxSEL value */ | ||
| 34 | #define PM_BUSEVENT_MSK 0xf3700 | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Bits in MMCR1 for POWER6 | ||
| 38 | */ | ||
| 39 | #define MMCR1_TTM0SEL_SH 60 | ||
| 40 | #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4) | ||
| 41 | #define MMCR1_TTMSEL_MSK 0xf | ||
| 42 | #define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK) | ||
| 43 | #define MMCR1_NESTSEL_SH 45 | ||
| 44 | #define MMCR1_NESTSEL_MSK 0x7 | ||
| 45 | #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) | ||
| 46 | #define MMCR1_PMC1_LLA (1ul << 44) | ||
| 47 | #define MMCR1_PMC1_LLA_VALUE (1ul << 39) | ||
| 48 | #define MMCR1_PMC1_ADDR_SEL (1ul << 35) | ||
| 49 | #define MMCR1_PMC1SEL_SH 24 | ||
| 50 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | ||
| 51 | #define MMCR1_PMCSEL_MSK 0xff | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Map of which direct events on which PMCs are marked instruction events. | ||
| 55 | * Indexed by PMCSEL value >> 1. | ||
| 56 | * Bottom 4 bits are a map of which PMCs are interesting, | ||
| 57 | * top 4 bits say what sort of event: | ||
| 58 | * 0 = direct marked event, | ||
| 59 | * 1 = byte decode event, | ||
| 60 | * 4 = add/and event (PMC1 -> bits 0 & 4), | ||
| 61 | * 5 = add/and event (PMC1 -> bits 1 & 5), | ||
| 62 | * 6 = add/and event (PMC1 -> bits 2 & 6), | ||
| 63 | * 7 = add/and event (PMC1 -> bits 3 & 7). | ||
| 64 | */ | ||
| 65 | static unsigned char direct_event_is_marked[0x60 >> 1] = { | ||
| 66 | 0, /* 00 */ | ||
| 67 | 0, /* 02 */ | ||
| 68 | 0, /* 04 */ | ||
| 69 | 0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */ | ||
| 70 | 0x04, /* 08 PM_MRK_DFU_FIN */ | ||
| 71 | 0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */ | ||
| 72 | 0, /* 0c */ | ||
| 73 | 0, /* 0e */ | ||
| 74 | 0x02, /* 10 PM_MRK_INST_DISP */ | ||
| 75 | 0x08, /* 12 PM_MRK_LSU_DERAT_MISS */ | ||
| 76 | 0, /* 14 */ | ||
| 77 | 0, /* 16 */ | ||
| 78 | 0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */ | ||
| 79 | 0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */ | ||
| 80 | 0x01, /* 1c PM_MRK_INST_ISSUED */ | ||
| 81 | 0, /* 1e */ | ||
| 82 | 0, /* 20 */ | ||
| 83 | 0, /* 22 */ | ||
| 84 | 0, /* 24 */ | ||
| 85 | 0, /* 26 */ | ||
| 86 | 0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */ | ||
| 87 | 0, /* 2a */ | ||
| 88 | 0, /* 2c */ | ||
| 89 | 0, /* 2e */ | ||
| 90 | 0x4f, /* 30 */ | ||
| 91 | 0x7f, /* 32 */ | ||
| 92 | 0x4f, /* 34 */ | ||
| 93 | 0x5f, /* 36 */ | ||
| 94 | 0x6f, /* 38 */ | ||
| 95 | 0x4f, /* 3a */ | ||
| 96 | 0, /* 3c */ | ||
| 97 | 0x08, /* 3e PM_MRK_INST_TIMEO */ | ||
| 98 | 0x1f, /* 40 */ | ||
| 99 | 0x1f, /* 42 */ | ||
| 100 | 0x1f, /* 44 */ | ||
| 101 | 0x1f, /* 46 */ | ||
| 102 | 0x1f, /* 48 */ | ||
| 103 | 0x1f, /* 4a */ | ||
| 104 | 0x1f, /* 4c */ | ||
| 105 | 0x1f, /* 4e */ | ||
| 106 | 0, /* 50 */ | ||
| 107 | 0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */ | ||
| 108 | 0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */ | ||
| 109 | 0x02, /* 56 PM_MRK_LD_MISS_L1 */ | ||
| 110 | 0, /* 58 */ | ||
| 111 | 0, /* 5a */ | ||
| 112 | 0, /* 5c */ | ||
| 113 | 0, /* 5e */ | ||
| 114 | }; | ||
| 115 | |||
| 116 | /* | ||
| 117 | * Masks showing for each unit which bits are marked events. | ||
| 118 | * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0. | ||
| 119 | */ | ||
| 120 | static u32 marked_bus_events[16] = { | ||
| 121 | 0x01000000, /* direct events set 1: byte 3 bit 0 */ | ||
| 122 | 0x00010000, /* direct events set 2: byte 2 bit 0 */ | ||
| 123 | 0, 0, 0, 0, /* IDU, IFU, nest: nothing */ | ||
| 124 | 0x00000088, /* VMX set 1: byte 0 bits 3, 7 */ | ||
| 125 | 0x000000c0, /* VMX set 2: byte 0 bits 4-7 */ | ||
| 126 | 0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */ | ||
| 127 | 0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */ | ||
| 128 | 0, /* LSU set 3 */ | ||
| 129 | 0x00000010, /* VMX set 3: byte 0 bit 4 */ | ||
| 130 | 0, /* BFP set 1 */ | ||
| 131 | 0x00000022, /* BFP set 2: byte 0 bits 1, 5 */ | ||
| 132 | 0, 0 | ||
| 133 | }; | ||
| 134 | |||
| 135 | /* | ||
| 136 | * Returns 1 if event counts things relating to marked instructions | ||
| 137 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 138 | */ | ||
| 139 | static int power6_marked_instr_event(u64 event) | ||
| 140 | { | ||
| 141 | int pmc, psel, ptype; | ||
| 142 | int bit, byte, unit; | ||
| 143 | u32 mask; | ||
| 144 | |||
| 145 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 146 | psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */ | ||
| 147 | if (pmc >= 5) | ||
| 148 | return 0; | ||
| 149 | |||
| 150 | bit = -1; | ||
| 151 | if (psel < sizeof(direct_event_is_marked)) { | ||
| 152 | ptype = direct_event_is_marked[psel]; | ||
| 153 | if (pmc == 0 || !(ptype & (1 << (pmc - 1)))) | ||
| 154 | return 0; | ||
| 155 | ptype >>= 4; | ||
| 156 | if (ptype == 0) | ||
| 157 | return 1; | ||
| 158 | if (ptype == 1) | ||
| 159 | bit = 0; | ||
| 160 | else | ||
| 161 | bit = ptype ^ (pmc - 1); | ||
| 162 | } else if ((psel & 0x48) == 0x40) | ||
| 163 | bit = psel & 7; | ||
| 164 | |||
| 165 | if (!(event & PM_BUSEVENT_MSK) || bit == -1) | ||
| 166 | return 0; | ||
| 167 | |||
| 168 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 169 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 170 | mask = marked_bus_events[unit]; | ||
| 171 | return (mask >> (byte * 8 + bit)) & 1; | ||
| 172 | } | ||
| 173 | |||
| 174 | /* | ||
| 175 | * Assign PMC numbers and compute MMCR1 value for a set of events | ||
| 176 | */ | ||
| 177 | static int p6_compute_mmcr(u64 event[], int n_ev, | ||
| 178 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 179 | { | ||
| 180 | unsigned long mmcr1 = 0; | ||
| 181 | unsigned long mmcra = 0; | ||
| 182 | int i; | ||
| 183 | unsigned int pmc, ev, b, u, s, psel; | ||
| 184 | unsigned int ttmset = 0; | ||
| 185 | unsigned int pmc_inuse = 0; | ||
| 186 | |||
| 187 | if (n_ev > 6) | ||
| 188 | return -1; | ||
| 189 | for (i = 0; i < n_ev; ++i) { | ||
| 190 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 191 | if (pmc) { | ||
| 192 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 193 | return -1; /* collision! */ | ||
| 194 | pmc_inuse |= 1 << (pmc - 1); | ||
| 195 | } | ||
| 196 | } | ||
| 197 | for (i = 0; i < n_ev; ++i) { | ||
| 198 | ev = event[i]; | ||
| 199 | pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 200 | if (pmc) { | ||
| 201 | --pmc; | ||
| 202 | } else { | ||
| 203 | /* can go on any PMC; find a free one */ | ||
| 204 | for (pmc = 0; pmc < 4; ++pmc) | ||
| 205 | if (!(pmc_inuse & (1 << pmc))) | ||
| 206 | break; | ||
| 207 | if (pmc >= 4) | ||
| 208 | return -1; | ||
| 209 | pmc_inuse |= 1 << pmc; | ||
| 210 | } | ||
| 211 | hwc[i] = pmc; | ||
| 212 | psel = ev & PM_PMCSEL_MSK; | ||
| 213 | if (ev & PM_BUSEVENT_MSK) { | ||
| 214 | /* this event uses the event bus */ | ||
| 215 | b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 216 | u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 217 | /* check for conflict on this byte of event bus */ | ||
| 218 | if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) | ||
| 219 | return -1; | ||
| 220 | mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b); | ||
| 221 | ttmset |= 1 << b; | ||
| 222 | if (u == 5) { | ||
| 223 | /* Nest events have a further mux */ | ||
| 224 | s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; | ||
| 225 | if ((ttmset & 0x10) && | ||
| 226 | MMCR1_NESTSEL(mmcr1) != s) | ||
| 227 | return -1; | ||
| 228 | ttmset |= 0x10; | ||
| 229 | mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH; | ||
| 230 | } | ||
| 231 | if (0x30 <= psel && psel <= 0x3d) { | ||
| 232 | /* these need the PMCx_ADDR_SEL bits */ | ||
| 233 | if (b >= 2) | ||
| 234 | mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc; | ||
| 235 | } | ||
| 236 | /* bus select values are different for PMC3/4 */ | ||
| 237 | if (pmc >= 2 && (psel & 0x90) == 0x80) | ||
| 238 | psel ^= 0x20; | ||
| 239 | } | ||
| 240 | if (ev & PM_LLA) { | ||
| 241 | mmcr1 |= MMCR1_PMC1_LLA >> pmc; | ||
| 242 | if (ev & PM_LLAV) | ||
| 243 | mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc; | ||
| 244 | } | ||
| 245 | if (power6_marked_instr_event(event[i])) | ||
| 246 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 247 | if (pmc < 4) | ||
| 248 | mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc); | ||
| 249 | } | ||
| 250 | mmcr[0] = 0; | ||
| 251 | if (pmc_inuse & 1) | ||
| 252 | mmcr[0] = MMCR0_PMC1CE; | ||
| 253 | if (pmc_inuse & 0xe) | ||
| 254 | mmcr[0] |= MMCR0_PMCjCE; | ||
| 255 | mmcr[1] = mmcr1; | ||
| 256 | mmcr[2] = mmcra; | ||
| 257 | return 0; | ||
| 258 | } | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Layout of constraint bits: | ||
| 262 | * | ||
| 263 | * 0-1 add field: number of uses of PMC1 (max 1) | ||
| 264 | * 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6 | ||
| 265 | * 12-15 add field: number of uses of PMC1-4 (max 4) | ||
| 266 | * 16-19 select field: unit on byte 0 of event bus | ||
| 267 | * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 | ||
| 268 | * 32-34 select field: nest (subunit) event selector | ||
| 269 | */ | ||
| 270 | static int p6_get_constraint(u64 event, unsigned long *maskp, | ||
| 271 | unsigned long *valp) | ||
| 272 | { | ||
| 273 | int pmc, byte, sh, subunit; | ||
| 274 | unsigned long mask = 0, value = 0; | ||
| 275 | |||
| 276 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 277 | if (pmc) { | ||
| 278 | if (pmc > 4 && !(event == 0x500009 || event == 0x600005)) | ||
| 279 | return -1; | ||
| 280 | sh = (pmc - 1) * 2; | ||
| 281 | mask |= 2 << sh; | ||
| 282 | value |= 1 << sh; | ||
| 283 | } | ||
| 284 | if (event & PM_BUSEVENT_MSK) { | ||
| 285 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 286 | sh = byte * 4 + (16 - PM_UNIT_SH); | ||
| 287 | mask |= PM_UNIT_MSKS << sh; | ||
| 288 | value |= (unsigned long)(event & PM_UNIT_MSKS) << sh; | ||
| 289 | if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { | ||
| 290 | subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; | ||
| 291 | mask |= (unsigned long)PM_SUBUNIT_MSK << 32; | ||
| 292 | value |= (unsigned long)subunit << 32; | ||
| 293 | } | ||
| 294 | } | ||
| 295 | if (pmc <= 4) { | ||
| 296 | mask |= 0x8000; /* add field for count of PMC1-4 uses */ | ||
| 297 | value |= 0x1000; | ||
| 298 | } | ||
| 299 | *maskp = mask; | ||
| 300 | *valp = value; | ||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | static int p6_limited_pmc_event(u64 event) | ||
| 305 | { | ||
| 306 | int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 307 | |||
| 308 | return pmc == 5 || pmc == 6; | ||
| 309 | } | ||
| 310 | |||
| 311 | #define MAX_ALT 4 /* at most 4 alternatives for any event */ | ||
| 312 | |||
| 313 | static const unsigned int event_alternatives[][MAX_ALT] = { | ||
| 314 | { 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */ | ||
| 315 | { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */ | ||
| 316 | { 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */ | ||
| 317 | { 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */ | ||
| 318 | { 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */ | ||
| 319 | { 0x10000e, 0x400010 }, /* PM_PURR */ | ||
| 320 | { 0x100010, 0x4000f8 }, /* PM_FLUSH */ | ||
| 321 | { 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */ | ||
| 322 | { 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */ | ||
| 323 | { 0x100054, 0x2000f0 }, /* PM_ST_FIN */ | ||
| 324 | { 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */ | ||
| 325 | { 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */ | ||
| 326 | { 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */ | ||
| 327 | { 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */ | ||
| 328 | { 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */ | ||
| 329 | { 0x200012, 0x300012 }, /* PM_INST_DISP */ | ||
| 330 | { 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */ | ||
| 331 | { 0x2000f8, 0x300010 }, /* PM_EXT_INT */ | ||
| 332 | { 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */ | ||
| 333 | { 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */ | ||
| 334 | { 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */ | ||
| 335 | { 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */ | ||
| 336 | { 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */ | ||
| 337 | }; | ||
| 338 | |||
| 339 | /* | ||
| 340 | * This could be made more efficient with a binary search on | ||
| 341 | * a presorted list, if necessary | ||
| 342 | */ | ||
| 343 | static int find_alternatives_list(u64 event) | ||
| 344 | { | ||
| 345 | int i, j; | ||
| 346 | unsigned int alt; | ||
| 347 | |||
| 348 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | ||
| 349 | if (event < event_alternatives[i][0]) | ||
| 350 | return -1; | ||
| 351 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 352 | alt = event_alternatives[i][j]; | ||
| 353 | if (!alt || event < alt) | ||
| 354 | break; | ||
| 355 | if (event == alt) | ||
| 356 | return i; | ||
| 357 | } | ||
| 358 | } | ||
| 359 | return -1; | ||
| 360 | } | ||
| 361 | |||
| 362 | static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 363 | { | ||
| 364 | int i, j, nlim; | ||
| 365 | unsigned int psel, pmc; | ||
| 366 | unsigned int nalt = 1; | ||
| 367 | u64 aevent; | ||
| 368 | |||
| 369 | alt[0] = event; | ||
| 370 | nlim = p6_limited_pmc_event(event); | ||
| 371 | |||
| 372 | /* check the alternatives table */ | ||
| 373 | i = find_alternatives_list(event); | ||
| 374 | if (i >= 0) { | ||
| 375 | /* copy out alternatives from list */ | ||
| 376 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 377 | aevent = event_alternatives[i][j]; | ||
| 378 | if (!aevent) | ||
| 379 | break; | ||
| 380 | if (aevent != event) | ||
| 381 | alt[nalt++] = aevent; | ||
| 382 | nlim += p6_limited_pmc_event(aevent); | ||
| 383 | } | ||
| 384 | |||
| 385 | } else { | ||
| 386 | /* Check for alternative ways of computing sum events */ | ||
| 387 | /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */ | ||
| 388 | psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */ | ||
| 389 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 390 | if (pmc && (psel == 0x32 || psel == 0x34)) | ||
| 391 | alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) | | ||
| 392 | ((5 - pmc) << PM_PMC_SH); | ||
| 393 | |||
| 394 | /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */ | ||
| 395 | if (pmc && (psel == 0x38 || psel == 0x3a)) | ||
| 396 | alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) | | ||
| 397 | ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH); | ||
| 398 | } | ||
| 399 | |||
| 400 | if (flags & PPMU_ONLY_COUNT_RUN) { | ||
| 401 | /* | ||
| 402 | * We're only counting in RUN state, | ||
| 403 | * so PM_CYC is equivalent to PM_RUN_CYC, | ||
| 404 | * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR. | ||
| 405 | * This doesn't include alternatives that don't provide | ||
| 406 | * any extra flexibility in assigning PMCs (e.g. | ||
| 407 | * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC). | ||
| 408 | * Note that even with these additional alternatives | ||
| 409 | * we never end up with more than 4 alternatives for any event. | ||
| 410 | */ | ||
| 411 | j = nalt; | ||
| 412 | for (i = 0; i < nalt; ++i) { | ||
| 413 | switch (alt[i]) { | ||
| 414 | case 0x1e: /* PM_CYC */ | ||
| 415 | alt[j++] = 0x600005; /* PM_RUN_CYC */ | ||
| 416 | ++nlim; | ||
| 417 | break; | ||
| 418 | case 0x10000a: /* PM_RUN_CYC */ | ||
| 419 | alt[j++] = 0x1e; /* PM_CYC */ | ||
| 420 | break; | ||
| 421 | case 2: /* PM_INST_CMPL */ | ||
| 422 | alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */ | ||
| 423 | ++nlim; | ||
| 424 | break; | ||
| 425 | case 0x500009: /* PM_RUN_INST_CMPL */ | ||
| 426 | alt[j++] = 2; /* PM_INST_CMPL */ | ||
| 427 | break; | ||
| 428 | case 0x10000e: /* PM_PURR */ | ||
| 429 | alt[j++] = 0x4000f4; /* PM_RUN_PURR */ | ||
| 430 | break; | ||
| 431 | case 0x4000f4: /* PM_RUN_PURR */ | ||
| 432 | alt[j++] = 0x10000e; /* PM_PURR */ | ||
| 433 | break; | ||
| 434 | } | ||
| 435 | } | ||
| 436 | nalt = j; | ||
| 437 | } | ||
| 438 | |||
| 439 | if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) { | ||
| 440 | /* remove the limited PMC events */ | ||
| 441 | j = 0; | ||
| 442 | for (i = 0; i < nalt; ++i) { | ||
| 443 | if (!p6_limited_pmc_event(alt[i])) { | ||
| 444 | alt[j] = alt[i]; | ||
| 445 | ++j; | ||
| 446 | } | ||
| 447 | } | ||
| 448 | nalt = j; | ||
| 449 | } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) { | ||
| 450 | /* remove all but the limited PMC events */ | ||
| 451 | j = 0; | ||
| 452 | for (i = 0; i < nalt; ++i) { | ||
| 453 | if (p6_limited_pmc_event(alt[i])) { | ||
| 454 | alt[j] = alt[i]; | ||
| 455 | ++j; | ||
| 456 | } | ||
| 457 | } | ||
| 458 | nalt = j; | ||
| 459 | } | ||
| 460 | |||
| 461 | return nalt; | ||
| 462 | } | ||
| 463 | |||
| 464 | static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 465 | { | ||
| 466 | /* Set PMCxSEL to 0 to disable PMCx */ | ||
| 467 | if (pmc <= 3) | ||
| 468 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); | ||
| 469 | } | ||
| 470 | |||
| 471 | static int power6_generic_events[] = { | ||
| 472 | [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, | ||
| 473 | [PERF_COUNT_HW_INSTRUCTIONS] = 2, | ||
| 474 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */ | ||
| 475 | [PERF_COUNT_HW_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */ | ||
| 476 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */ | ||
| 477 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x400052, /* BR_MPRED */ | ||
| 478 | }; | ||
| 479 | |||
| 480 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 481 | |||
| 482 | /* | ||
| 483 | * Table of generalized cache-related events. | ||
| 484 | * 0 means not supported, -1 means nonsensical, other values | ||
| 485 | * are event codes. | ||
| 486 | * The "DTLB" and "ITLB" events relate to the DERAT and IERAT. | ||
| 487 | */ | ||
| 488 | static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 489 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 490 | [C(OP_READ)] = { 0x80082, 0x80080 }, | ||
| 491 | [C(OP_WRITE)] = { 0x80086, 0x80088 }, | ||
| 492 | [C(OP_PREFETCH)] = { 0x810a4, 0 }, | ||
| 493 | }, | ||
| 494 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 495 | [C(OP_READ)] = { 0, 0x100056 }, | ||
| 496 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 497 | [C(OP_PREFETCH)] = { 0x4008c, 0 }, | ||
| 498 | }, | ||
| 499 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 500 | [C(OP_READ)] = { 0x150730, 0x250532 }, | ||
| 501 | [C(OP_WRITE)] = { 0x250432, 0x150432 }, | ||
| 502 | [C(OP_PREFETCH)] = { 0x810a6, 0 }, | ||
| 503 | }, | ||
| 504 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 505 | [C(OP_READ)] = { 0, 0x20000e }, | ||
| 506 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 507 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 508 | }, | ||
| 509 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 510 | [C(OP_READ)] = { 0, 0x420ce }, | ||
| 511 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 512 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 513 | }, | ||
| 514 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 515 | [C(OP_READ)] = { 0x430e6, 0x400052 }, | ||
| 516 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 517 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 518 | }, | ||
| 519 | }; | ||
| 520 | |||
| 521 | static struct power_pmu power6_pmu = { | ||
| 522 | .name = "POWER6", | ||
| 523 | .n_counter = 6, | ||
| 524 | .max_alternatives = MAX_ALT, | ||
| 525 | .add_fields = 0x1555, | ||
| 526 | .test_adder = 0x3000, | ||
| 527 | .compute_mmcr = p6_compute_mmcr, | ||
| 528 | .get_constraint = p6_get_constraint, | ||
| 529 | .get_alternatives = p6_get_alternatives, | ||
| 530 | .disable_pmc = p6_disable_pmc, | ||
| 531 | .limited_pmc_event = p6_limited_pmc_event, | ||
| 532 | .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR, | ||
| 533 | .n_generic = ARRAY_SIZE(power6_generic_events), | ||
| 534 | .generic_events = power6_generic_events, | ||
| 535 | .cache_events = &power6_cache_events, | ||
| 536 | }; | ||
| 537 | |||
| 538 | static int init_power6_pmu(void) | ||
| 539 | { | ||
| 540 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6")) | ||
| 541 | return -ENODEV; | ||
| 542 | |||
| 543 | return register_power_pmu(&power6_pmu); | ||
| 544 | } | ||
| 545 | |||
| 546 | arch_initcall(init_power6_pmu); | ||
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c new file mode 100644 index 000000000000..5d755ef7ac8f --- /dev/null +++ b/arch/powerpc/kernel/power7-pmu.c | |||
| @@ -0,0 +1,374 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for POWER7 processors. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for POWER7 | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0xf | ||
| 22 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | ||
| 23 | #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */ | ||
| 24 | #define PM_UNIT_MSK 0xf | ||
| 25 | #define PM_COMBINE_SH 11 /* Combined event bit */ | ||
| 26 | #define PM_COMBINE_MSK 1 | ||
| 27 | #define PM_COMBINE_MSKS 0x800 | ||
| 28 | #define PM_L2SEL_SH 8 /* L2 event select */ | ||
| 29 | #define PM_L2SEL_MSK 7 | ||
| 30 | #define PM_PMCSEL_MSK 0xff | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Bits in MMCR1 for POWER7 | ||
| 34 | */ | ||
| 35 | #define MMCR1_TTM0SEL_SH 60 | ||
| 36 | #define MMCR1_TTM1SEL_SH 56 | ||
| 37 | #define MMCR1_TTM2SEL_SH 52 | ||
| 38 | #define MMCR1_TTM3SEL_SH 48 | ||
| 39 | #define MMCR1_TTMSEL_MSK 0xf | ||
| 40 | #define MMCR1_L2SEL_SH 45 | ||
| 41 | #define MMCR1_L2SEL_MSK 7 | ||
| 42 | #define MMCR1_PMC1_COMBINE_SH 35 | ||
| 43 | #define MMCR1_PMC2_COMBINE_SH 34 | ||
| 44 | #define MMCR1_PMC3_COMBINE_SH 33 | ||
| 45 | #define MMCR1_PMC4_COMBINE_SH 32 | ||
| 46 | #define MMCR1_PMC1SEL_SH 24 | ||
| 47 | #define MMCR1_PMC2SEL_SH 16 | ||
| 48 | #define MMCR1_PMC3SEL_SH 8 | ||
| 49 | #define MMCR1_PMC4SEL_SH 0 | ||
| 50 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | ||
| 51 | #define MMCR1_PMCSEL_MSK 0xff | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Bits in MMCRA | ||
| 55 | */ | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Layout of constraint bits: | ||
| 59 | * 6666555555555544444444443333333333222222222211111111110000000000 | ||
| 60 | * 3210987654321098765432109876543210987654321098765432109876543210 | ||
| 61 | * [ ><><><><><><> | ||
| 62 | * NC P6P5P4P3P2P1 | ||
| 63 | * | ||
| 64 | * NC - number of counters | ||
| 65 | * 15: NC error 0x8000 | ||
| 66 | * 12-14: number of events needing PMC1-4 0x7000 | ||
| 67 | * | ||
| 68 | * P6 | ||
| 69 | * 11: P6 error 0x800 | ||
| 70 | * 10-11: Count of events needing PMC6 | ||
| 71 | * | ||
| 72 | * P1..P5 | ||
| 73 | * 0-9: Count of events needing PMC1..PMC5 | ||
| 74 | */ | ||
| 75 | |||
| 76 | static int power7_get_constraint(u64 event, unsigned long *maskp, | ||
| 77 | unsigned long *valp) | ||
| 78 | { | ||
| 79 | int pmc, sh; | ||
| 80 | unsigned long mask = 0, value = 0; | ||
| 81 | |||
| 82 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 83 | if (pmc) { | ||
| 84 | if (pmc > 6) | ||
| 85 | return -1; | ||
| 86 | sh = (pmc - 1) * 2; | ||
| 87 | mask |= 2 << sh; | ||
| 88 | value |= 1 << sh; | ||
| 89 | if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) | ||
| 90 | return -1; | ||
| 91 | } | ||
| 92 | if (pmc < 5) { | ||
| 93 | /* need a counter from PMC1-4 set */ | ||
| 94 | mask |= 0x8000; | ||
| 95 | value |= 0x1000; | ||
| 96 | } | ||
| 97 | *maskp = mask; | ||
| 98 | *valp = value; | ||
| 99 | return 0; | ||
| 100 | } | ||
| 101 | |||
| 102 | #define MAX_ALT 2 /* at most 2 alternatives for any event */ | ||
| 103 | |||
| 104 | static const unsigned int event_alternatives[][MAX_ALT] = { | ||
| 105 | { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ | ||
| 106 | { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ | ||
| 107 | { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Scan the alternatives table for a match and return the | ||
| 112 | * index into the alternatives table if found, else -1. | ||
| 113 | */ | ||
| 114 | static int find_alternative(u64 event) | ||
| 115 | { | ||
| 116 | int i, j; | ||
| 117 | |||
| 118 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | ||
| 119 | if (event < event_alternatives[i][0]) | ||
| 120 | break; | ||
| 121 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | ||
| 122 | if (event == event_alternatives[i][j]) | ||
| 123 | return i; | ||
| 124 | } | ||
| 125 | return -1; | ||
| 126 | } | ||
| 127 | |||
| 128 | static s64 find_alternative_decode(u64 event) | ||
| 129 | { | ||
| 130 | int pmc, psel; | ||
| 131 | |||
| 132 | /* this only handles the 4x decode events */ | ||
| 133 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 134 | psel = event & PM_PMCSEL_MSK; | ||
| 135 | if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) | ||
| 136 | return event - (1 << PM_PMC_SH) + 8; | ||
| 137 | if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48) | ||
| 138 | return event + (1 << PM_PMC_SH) - 8; | ||
| 139 | return -1; | ||
| 140 | } | ||
| 141 | |||
| 142 | static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 143 | { | ||
| 144 | int i, j, nalt = 1; | ||
| 145 | s64 ae; | ||
| 146 | |||
| 147 | alt[0] = event; | ||
| 148 | nalt = 1; | ||
| 149 | i = find_alternative(event); | ||
| 150 | if (i >= 0) { | ||
| 151 | for (j = 0; j < MAX_ALT; ++j) { | ||
| 152 | ae = event_alternatives[i][j]; | ||
| 153 | if (ae && ae != event) | ||
| 154 | alt[nalt++] = ae; | ||
| 155 | } | ||
| 156 | } else { | ||
| 157 | ae = find_alternative_decode(event); | ||
| 158 | if (ae > 0) | ||
| 159 | alt[nalt++] = ae; | ||
| 160 | } | ||
| 161 | |||
| 162 | if (flags & PPMU_ONLY_COUNT_RUN) { | ||
| 163 | /* | ||
| 164 | * We're only counting in RUN state, | ||
| 165 | * so PM_CYC is equivalent to PM_RUN_CYC | ||
| 166 | * and PM_INST_CMPL === PM_RUN_INST_CMPL. | ||
| 167 | * This doesn't include alternatives that don't provide | ||
| 168 | * any extra flexibility in assigning PMCs. | ||
| 169 | */ | ||
| 170 | j = nalt; | ||
| 171 | for (i = 0; i < nalt; ++i) { | ||
| 172 | switch (alt[i]) { | ||
| 173 | case 0x1e: /* PM_CYC */ | ||
| 174 | alt[j++] = 0x600f4; /* PM_RUN_CYC */ | ||
| 175 | break; | ||
| 176 | case 0x600f4: /* PM_RUN_CYC */ | ||
| 177 | alt[j++] = 0x1e; | ||
| 178 | break; | ||
| 179 | case 0x2: /* PM_PPC_CMPL */ | ||
| 180 | alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ | ||
| 181 | break; | ||
| 182 | case 0x500fa: /* PM_RUN_INST_CMPL */ | ||
| 183 | alt[j++] = 0x2; /* PM_PPC_CMPL */ | ||
| 184 | break; | ||
| 185 | } | ||
| 186 | } | ||
| 187 | nalt = j; | ||
| 188 | } | ||
| 189 | |||
| 190 | return nalt; | ||
| 191 | } | ||
| 192 | |||
| 193 | /* | ||
| 194 | * Returns 1 if event counts things relating to marked instructions | ||
| 195 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 196 | */ | ||
| 197 | static int power7_marked_instr_event(u64 event) | ||
| 198 | { | ||
| 199 | int pmc, psel; | ||
| 200 | int unit; | ||
| 201 | |||
| 202 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 203 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 204 | psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */ | ||
| 205 | if (pmc >= 5) | ||
| 206 | return 0; | ||
| 207 | |||
| 208 | switch (psel >> 4) { | ||
| 209 | case 2: | ||
| 210 | return pmc == 2 || pmc == 4; | ||
| 211 | case 3: | ||
| 212 | if (psel == 0x3c) | ||
| 213 | return pmc == 1; | ||
| 214 | if (psel == 0x3e) | ||
| 215 | return pmc != 2; | ||
| 216 | return 1; | ||
| 217 | case 4: | ||
| 218 | case 5: | ||
| 219 | return unit == 0xd; | ||
| 220 | case 6: | ||
| 221 | if (psel == 0x64) | ||
| 222 | return pmc >= 3; | ||
| 223 | case 8: | ||
| 224 | return unit == 0xd; | ||
| 225 | } | ||
| 226 | return 0; | ||
| 227 | } | ||
| 228 | |||
| 229 | static int power7_compute_mmcr(u64 event[], int n_ev, | ||
| 230 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 231 | { | ||
| 232 | unsigned long mmcr1 = 0; | ||
| 233 | unsigned long mmcra = 0; | ||
| 234 | unsigned int pmc, unit, combine, l2sel, psel; | ||
| 235 | unsigned int pmc_inuse = 0; | ||
| 236 | int i; | ||
| 237 | |||
| 238 | /* First pass to count resource use */ | ||
| 239 | for (i = 0; i < n_ev; ++i) { | ||
| 240 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 241 | if (pmc) { | ||
| 242 | if (pmc > 6) | ||
| 243 | return -1; | ||
| 244 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 245 | return -1; | ||
| 246 | pmc_inuse |= 1 << (pmc - 1); | ||
| 247 | } | ||
| 248 | } | ||
| 249 | |||
| 250 | /* Second pass: assign PMCs, set all MMCR1 fields */ | ||
| 251 | for (i = 0; i < n_ev; ++i) { | ||
| 252 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 253 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 254 | combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK; | ||
| 255 | l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK; | ||
| 256 | psel = event[i] & PM_PMCSEL_MSK; | ||
| 257 | if (!pmc) { | ||
| 258 | /* Bus event or any-PMC direct event */ | ||
| 259 | for (pmc = 0; pmc < 4; ++pmc) { | ||
| 260 | if (!(pmc_inuse & (1 << pmc))) | ||
| 261 | break; | ||
| 262 | } | ||
| 263 | if (pmc >= 4) | ||
| 264 | return -1; | ||
| 265 | pmc_inuse |= 1 << pmc; | ||
| 266 | } else { | ||
| 267 | /* Direct or decoded event */ | ||
| 268 | --pmc; | ||
| 269 | } | ||
| 270 | if (pmc <= 3) { | ||
| 271 | mmcr1 |= (unsigned long) unit | ||
| 272 | << (MMCR1_TTM0SEL_SH - 4 * pmc); | ||
| 273 | mmcr1 |= (unsigned long) combine | ||
| 274 | << (MMCR1_PMC1_COMBINE_SH - pmc); | ||
| 275 | mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); | ||
| 276 | if (unit == 6) /* L2 events */ | ||
| 277 | mmcr1 |= (unsigned long) l2sel | ||
| 278 | << MMCR1_L2SEL_SH; | ||
| 279 | } | ||
| 280 | if (power7_marked_instr_event(event[i])) | ||
| 281 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 282 | hwc[i] = pmc; | ||
| 283 | } | ||
| 284 | |||
| 285 | /* Return MMCRx values */ | ||
| 286 | mmcr[0] = 0; | ||
| 287 | if (pmc_inuse & 1) | ||
| 288 | mmcr[0] = MMCR0_PMC1CE; | ||
| 289 | if (pmc_inuse & 0x3e) | ||
| 290 | mmcr[0] |= MMCR0_PMCjCE; | ||
| 291 | mmcr[1] = mmcr1; | ||
| 292 | mmcr[2] = mmcra; | ||
| 293 | return 0; | ||
| 294 | } | ||
| 295 | |||
| 296 | static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 297 | { | ||
| 298 | if (pmc <= 3) | ||
| 299 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); | ||
| 300 | } | ||
| 301 | |||
| 302 | static int power7_generic_events[] = { | ||
| 303 | [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, | ||
| 304 | [PERF_COUNT_HW_INSTRUCTIONS] = 2, | ||
| 305 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ | ||
| 306 | [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */ | ||
| 307 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */ | ||
| 308 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */ | ||
| 309 | }; | ||
| 310 | |||
| 311 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 312 | |||
| 313 | /* | ||
| 314 | * Table of generalized cache-related events. | ||
| 315 | * 0 means not supported, -1 means nonsensical, other values | ||
| 316 | * are event codes. | ||
| 317 | */ | ||
| 318 | static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 319 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 320 | [C(OP_READ)] = { 0x400f0, 0xc880 }, | ||
| 321 | [C(OP_WRITE)] = { 0, 0x300f0 }, | ||
| 322 | [C(OP_PREFETCH)] = { 0xd8b8, 0 }, | ||
| 323 | }, | ||
| 324 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 325 | [C(OP_READ)] = { 0, 0x200fc }, | ||
| 326 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 327 | [C(OP_PREFETCH)] = { 0x408a, 0 }, | ||
| 328 | }, | ||
| 329 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 330 | [C(OP_READ)] = { 0x6080, 0x6084 }, | ||
| 331 | [C(OP_WRITE)] = { 0x6082, 0x6086 }, | ||
| 332 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 333 | }, | ||
| 334 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 335 | [C(OP_READ)] = { 0, 0x300fc }, | ||
| 336 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 337 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 338 | }, | ||
| 339 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 340 | [C(OP_READ)] = { 0, 0x400fc }, | ||
| 341 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 342 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 343 | }, | ||
| 344 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 345 | [C(OP_READ)] = { 0x10068, 0x400f6 }, | ||
| 346 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 347 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 348 | }, | ||
| 349 | }; | ||
| 350 | |||
| 351 | static struct power_pmu power7_pmu = { | ||
| 352 | .name = "POWER7", | ||
| 353 | .n_counter = 6, | ||
| 354 | .max_alternatives = MAX_ALT + 1, | ||
| 355 | .add_fields = 0x1555ul, | ||
| 356 | .test_adder = 0x3000ul, | ||
| 357 | .compute_mmcr = power7_compute_mmcr, | ||
| 358 | .get_constraint = power7_get_constraint, | ||
| 359 | .get_alternatives = power7_get_alternatives, | ||
| 360 | .disable_pmc = power7_disable_pmc, | ||
| 361 | .n_generic = ARRAY_SIZE(power7_generic_events), | ||
| 362 | .generic_events = power7_generic_events, | ||
| 363 | .cache_events = &power7_cache_events, | ||
| 364 | }; | ||
| 365 | |||
| 366 | static int init_power7_pmu(void) | ||
| 367 | { | ||
| 368 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) | ||
| 369 | return -ENODEV; | ||
| 370 | |||
| 371 | return register_power_pmu(&power7_pmu); | ||
| 372 | } | ||
| 373 | |||
| 374 | arch_initcall(init_power7_pmu); | ||
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c new file mode 100644 index 000000000000..6637c87fe70e --- /dev/null +++ b/arch/powerpc/kernel/ppc970-pmu.c | |||
| @@ -0,0 +1,499 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support for PPC970-family processors. | ||
| 3 | * | ||
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/string.h> | ||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <asm/reg.h> | ||
| 15 | #include <asm/cputable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Bits in event code for PPC970 | ||
| 19 | */ | ||
| 20 | #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */ | ||
| 21 | #define PM_PMC_MSK 0xf | ||
| 22 | #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */ | ||
| 23 | #define PM_UNIT_MSK 0xf | ||
| 24 | #define PM_SPCSEL_SH 6 | ||
| 25 | #define PM_SPCSEL_MSK 3 | ||
| 26 | #define PM_BYTE_SH 4 /* Byte number of event bus to use */ | ||
| 27 | #define PM_BYTE_MSK 3 | ||
| 28 | #define PM_PMCSEL_MSK 0xf | ||
| 29 | |||
| 30 | /* Values in PM_UNIT field */ | ||
| 31 | #define PM_NONE 0 | ||
| 32 | #define PM_FPU 1 | ||
| 33 | #define PM_VPU 2 | ||
| 34 | #define PM_ISU 3 | ||
| 35 | #define PM_IFU 4 | ||
| 36 | #define PM_IDU 5 | ||
| 37 | #define PM_STS 6 | ||
| 38 | #define PM_LSU0 7 | ||
| 39 | #define PM_LSU1U 8 | ||
| 40 | #define PM_LSU1L 9 | ||
| 41 | #define PM_LASTUNIT 9 | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Bits in MMCR0 for PPC970 | ||
| 45 | */ | ||
| 46 | #define MMCR0_PMC1SEL_SH 8 | ||
| 47 | #define MMCR0_PMC2SEL_SH 1 | ||
| 48 | #define MMCR_PMCSEL_MSK 0x1f | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Bits in MMCR1 for PPC970 | ||
| 52 | */ | ||
| 53 | #define MMCR1_TTM0SEL_SH 62 | ||
| 54 | #define MMCR1_TTM1SEL_SH 59 | ||
| 55 | #define MMCR1_TTM3SEL_SH 53 | ||
| 56 | #define MMCR1_TTMSEL_MSK 3 | ||
| 57 | #define MMCR1_TD_CP_DBG0SEL_SH 50 | ||
| 58 | #define MMCR1_TD_CP_DBG1SEL_SH 48 | ||
| 59 | #define MMCR1_TD_CP_DBG2SEL_SH 46 | ||
| 60 | #define MMCR1_TD_CP_DBG3SEL_SH 44 | ||
| 61 | #define MMCR1_PMC1_ADDER_SEL_SH 39 | ||
| 62 | #define MMCR1_PMC2_ADDER_SEL_SH 38 | ||
| 63 | #define MMCR1_PMC6_ADDER_SEL_SH 37 | ||
| 64 | #define MMCR1_PMC5_ADDER_SEL_SH 36 | ||
| 65 | #define MMCR1_PMC8_ADDER_SEL_SH 35 | ||
| 66 | #define MMCR1_PMC7_ADDER_SEL_SH 34 | ||
| 67 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | ||
| 68 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | ||
| 69 | #define MMCR1_PMC3SEL_SH 27 | ||
| 70 | #define MMCR1_PMC4SEL_SH 22 | ||
| 71 | #define MMCR1_PMC5SEL_SH 17 | ||
| 72 | #define MMCR1_PMC6SEL_SH 12 | ||
| 73 | #define MMCR1_PMC7SEL_SH 7 | ||
| 74 | #define MMCR1_PMC8SEL_SH 2 | ||
| 75 | |||
| 76 | static short mmcr1_adder_bits[8] = { | ||
| 77 | MMCR1_PMC1_ADDER_SEL_SH, | ||
| 78 | MMCR1_PMC2_ADDER_SEL_SH, | ||
| 79 | MMCR1_PMC3_ADDER_SEL_SH, | ||
| 80 | MMCR1_PMC4_ADDER_SEL_SH, | ||
| 81 | MMCR1_PMC5_ADDER_SEL_SH, | ||
| 82 | MMCR1_PMC6_ADDER_SEL_SH, | ||
| 83 | MMCR1_PMC7_ADDER_SEL_SH, | ||
| 84 | MMCR1_PMC8_ADDER_SEL_SH | ||
| 85 | }; | ||
| 86 | |||
| 87 | /* | ||
| 88 | * Bits in MMCRA | ||
| 89 | */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * Layout of constraint bits: | ||
| 93 | * 6666555555555544444444443333333333222222222211111111110000000000 | ||
| 94 | * 3210987654321098765432109876543210987654321098765432109876543210 | ||
| 95 | * <><><>[ >[ >[ >< >< >< >< ><><><><><><><><> | ||
| 96 | * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8 | ||
| 97 | * | ||
| 98 | * SP - SPCSEL constraint | ||
| 99 | * 48-49: SPCSEL value 0x3_0000_0000_0000 | ||
| 100 | * | ||
| 101 | * T0 - TTM0 constraint | ||
| 102 | * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000 | ||
| 103 | * | ||
| 104 | * T1 - TTM1 constraint | ||
| 105 | * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000 | ||
| 106 | * | ||
| 107 | * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS | ||
| 108 | * 43: UC3 error 0x0800_0000_0000 | ||
| 109 | * 42: FPU|IFU|VPU events needed 0x0400_0000_0000 | ||
| 110 | * 41: ISU events needed 0x0200_0000_0000 | ||
| 111 | * 40: IDU|STS events needed 0x0100_0000_0000 | ||
| 112 | * | ||
| 113 | * PS1 | ||
| 114 | * 39: PS1 error 0x0080_0000_0000 | ||
| 115 | * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000 | ||
| 116 | * | ||
| 117 | * PS2 | ||
| 118 | * 35: PS2 error 0x0008_0000_0000 | ||
| 119 | * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000 | ||
| 120 | * | ||
| 121 | * B0 | ||
| 122 | * 28-31: Byte 0 event source 0xf000_0000 | ||
| 123 | * Encoding as for the event code | ||
| 124 | * | ||
| 125 | * B1, B2, B3 | ||
| 126 | * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources | ||
| 127 | * | ||
| 128 | * P1 | ||
| 129 | * 15: P1 error 0x8000 | ||
| 130 | * 14-15: Count of events needing PMC1 | ||
| 131 | * | ||
| 132 | * P2..P8 | ||
| 133 | * 0-13: Count of events needing PMC2..PMC8 | ||
| 134 | */ | ||
| 135 | |||
| 136 | static unsigned char direct_marked_event[8] = { | ||
| 137 | (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */ | ||
| 138 | (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */ | ||
| 139 | (1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */ | ||
| 140 | (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */ | ||
| 141 | (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */ | ||
| 142 | (1<<3) | (1<<4) | (1<<5), | ||
| 143 | /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */ | ||
| 144 | (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */ | ||
| 145 | (1<<4) /* PMC8: PM_MRK_LSU_FIN */ | ||
| 146 | }; | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Returns 1 if event counts things relating to marked instructions | ||
| 150 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | ||
| 151 | */ | ||
| 152 | static int p970_marked_instr_event(u64 event) | ||
| 153 | { | ||
| 154 | int pmc, psel, unit, byte, bit; | ||
| 155 | unsigned int mask; | ||
| 156 | |||
| 157 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 158 | psel = event & PM_PMCSEL_MSK; | ||
| 159 | if (pmc) { | ||
| 160 | if (direct_marked_event[pmc - 1] & (1 << psel)) | ||
| 161 | return 1; | ||
| 162 | if (psel == 0) /* add events */ | ||
| 163 | bit = (pmc <= 4)? pmc - 1: 8 - pmc; | ||
| 164 | else if (psel == 7 || psel == 13) /* decode events */ | ||
| 165 | bit = 4; | ||
| 166 | else | ||
| 167 | return 0; | ||
| 168 | } else | ||
| 169 | bit = psel; | ||
| 170 | |||
| 171 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 172 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 173 | mask = 0; | ||
| 174 | switch (unit) { | ||
| 175 | case PM_VPU: | ||
| 176 | mask = 0x4c; /* byte 0 bits 2,3,6 */ | ||
| 177 | case PM_LSU0: | ||
| 178 | /* byte 2 bits 0,2,3,4,6; all of byte 1 */ | ||
| 179 | mask = 0x085dff00; | ||
| 180 | case PM_LSU1L: | ||
| 181 | mask = 0x50 << 24; /* byte 3 bits 4,6 */ | ||
| 182 | break; | ||
| 183 | } | ||
| 184 | return (mask >> (byte * 8 + bit)) & 1; | ||
| 185 | } | ||
| 186 | |||
| 187 | /* Masks and values for using events from the various units */ | ||
| 188 | static unsigned long unit_cons[PM_LASTUNIT+1][2] = { | ||
| 189 | [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, | ||
| 190 | [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, | ||
| 191 | [PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, | ||
| 192 | [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull }, | ||
| 193 | [PM_IDU] = { 0x380000000000ull, 0x010000000000ull }, | ||
| 194 | [PM_STS] = { 0x380000000000ull, 0x310000000000ull }, | ||
| 195 | }; | ||
| 196 | |||
| 197 | static int p970_get_constraint(u64 event, unsigned long *maskp, | ||
| 198 | unsigned long *valp) | ||
| 199 | { | ||
| 200 | int pmc, byte, unit, sh, spcsel; | ||
| 201 | unsigned long mask = 0, value = 0; | ||
| 202 | int grp = -1; | ||
| 203 | |||
| 204 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 205 | if (pmc) { | ||
| 206 | if (pmc > 8) | ||
| 207 | return -1; | ||
| 208 | sh = (pmc - 1) * 2; | ||
| 209 | mask |= 2 << sh; | ||
| 210 | value |= 1 << sh; | ||
| 211 | grp = ((pmc - 1) >> 1) & 1; | ||
| 212 | } | ||
| 213 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 214 | if (unit) { | ||
| 215 | if (unit > PM_LASTUNIT) | ||
| 216 | return -1; | ||
| 217 | mask |= unit_cons[unit][0]; | ||
| 218 | value |= unit_cons[unit][1]; | ||
| 219 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 220 | /* | ||
| 221 | * Bus events on bytes 0 and 2 can be counted | ||
| 222 | * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8. | ||
| 223 | */ | ||
| 224 | if (!pmc) | ||
| 225 | grp = byte & 1; | ||
| 226 | /* Set byte lane select field */ | ||
| 227 | mask |= 0xfULL << (28 - 4 * byte); | ||
| 228 | value |= (unsigned long)unit << (28 - 4 * byte); | ||
| 229 | } | ||
| 230 | if (grp == 0) { | ||
| 231 | /* increment PMC1/2/5/6 field */ | ||
| 232 | mask |= 0x8000000000ull; | ||
| 233 | value |= 0x1000000000ull; | ||
| 234 | } else if (grp == 1) { | ||
| 235 | /* increment PMC3/4/7/8 field */ | ||
| 236 | mask |= 0x800000000ull; | ||
| 237 | value |= 0x100000000ull; | ||
| 238 | } | ||
| 239 | spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK; | ||
| 240 | if (spcsel) { | ||
| 241 | mask |= 3ull << 48; | ||
| 242 | value |= (unsigned long)spcsel << 48; | ||
| 243 | } | ||
| 244 | *maskp = mask; | ||
| 245 | *valp = value; | ||
| 246 | return 0; | ||
| 247 | } | ||
| 248 | |||
| 249 | static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | ||
| 250 | { | ||
| 251 | alt[0] = event; | ||
| 252 | |||
| 253 | /* 2 alternatives for LSU empty */ | ||
| 254 | if (event == 0x2002 || event == 0x3002) { | ||
| 255 | alt[1] = event ^ 0x1000; | ||
| 256 | return 2; | ||
| 257 | } | ||
| 258 | |||
| 259 | return 1; | ||
| 260 | } | ||
| 261 | |||
| 262 | static int p970_compute_mmcr(u64 event[], int n_ev, | ||
| 263 | unsigned int hwc[], unsigned long mmcr[]) | ||
| 264 | { | ||
| 265 | unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0; | ||
| 266 | unsigned int pmc, unit, byte, psel; | ||
| 267 | unsigned int ttm, grp; | ||
| 268 | unsigned int pmc_inuse = 0; | ||
| 269 | unsigned int pmc_grp_use[2]; | ||
| 270 | unsigned char busbyte[4]; | ||
| 271 | unsigned char unituse[16]; | ||
| 272 | unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 }; | ||
| 273 | unsigned char ttmuse[2]; | ||
| 274 | unsigned char pmcsel[8]; | ||
| 275 | int i; | ||
| 276 | int spcsel; | ||
| 277 | |||
| 278 | if (n_ev > 8) | ||
| 279 | return -1; | ||
| 280 | |||
| 281 | /* First pass to count resource use */ | ||
| 282 | pmc_grp_use[0] = pmc_grp_use[1] = 0; | ||
| 283 | memset(busbyte, 0, sizeof(busbyte)); | ||
| 284 | memset(unituse, 0, sizeof(unituse)); | ||
| 285 | for (i = 0; i < n_ev; ++i) { | ||
| 286 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 287 | if (pmc) { | ||
| 288 | if (pmc_inuse & (1 << (pmc - 1))) | ||
| 289 | return -1; | ||
| 290 | pmc_inuse |= 1 << (pmc - 1); | ||
| 291 | /* count 1/2/5/6 vs 3/4/7/8 use */ | ||
| 292 | ++pmc_grp_use[((pmc - 1) >> 1) & 1]; | ||
| 293 | } | ||
| 294 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 295 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 296 | if (unit) { | ||
| 297 | if (unit > PM_LASTUNIT) | ||
| 298 | return -1; | ||
| 299 | if (!pmc) | ||
| 300 | ++pmc_grp_use[byte & 1]; | ||
| 301 | if (busbyte[byte] && busbyte[byte] != unit) | ||
| 302 | return -1; | ||
| 303 | busbyte[byte] = unit; | ||
| 304 | unituse[unit] = 1; | ||
| 305 | } | ||
| 306 | } | ||
| 307 | if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4) | ||
| 308 | return -1; | ||
| 309 | |||
| 310 | /* | ||
| 311 | * Assign resources and set multiplexer selects. | ||
| 312 | * | ||
| 313 | * PM_ISU can go either on TTM0 or TTM1, but that's the only | ||
| 314 | * choice we have to deal with. | ||
| 315 | */ | ||
| 316 | if (unituse[PM_ISU] & | ||
| 317 | (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU])) | ||
| 318 | unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */ | ||
| 319 | /* Set TTM[01]SEL fields. */ | ||
| 320 | ttmuse[0] = ttmuse[1] = 0; | ||
| 321 | for (i = PM_FPU; i <= PM_STS; ++i) { | ||
| 322 | if (!unituse[i]) | ||
| 323 | continue; | ||
| 324 | ttm = unitmap[i]; | ||
| 325 | ++ttmuse[(ttm >> 2) & 1]; | ||
| 326 | mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH; | ||
| 327 | } | ||
| 328 | /* Check only one unit per TTMx */ | ||
| 329 | if (ttmuse[0] > 1 || ttmuse[1] > 1) | ||
| 330 | return -1; | ||
| 331 | |||
| 332 | /* Set byte lane select fields and TTM3SEL. */ | ||
| 333 | for (byte = 0; byte < 4; ++byte) { | ||
| 334 | unit = busbyte[byte]; | ||
| 335 | if (!unit) | ||
| 336 | continue; | ||
| 337 | if (unit <= PM_STS) | ||
| 338 | ttm = (unitmap[unit] >> 2) & 1; | ||
| 339 | else if (unit == PM_LSU0) | ||
| 340 | ttm = 2; | ||
| 341 | else { | ||
| 342 | ttm = 3; | ||
| 343 | if (unit == PM_LSU1L && byte >= 2) | ||
| 344 | mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); | ||
| 345 | } | ||
| 346 | mmcr1 |= (unsigned long)ttm | ||
| 347 | << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); | ||
| 348 | } | ||
| 349 | |||
| 350 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | ||
| 351 | memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */ | ||
| 352 | for (i = 0; i < n_ev; ++i) { | ||
| 353 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | ||
| 354 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | ||
| 355 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | ||
| 356 | psel = event[i] & PM_PMCSEL_MSK; | ||
| 357 | if (!pmc) { | ||
| 358 | /* Bus event or any-PMC direct event */ | ||
| 359 | if (unit) | ||
| 360 | psel |= 0x10 | ((byte & 2) << 2); | ||
| 361 | else | ||
| 362 | psel |= 8; | ||
| 363 | for (pmc = 0; pmc < 8; ++pmc) { | ||
| 364 | if (pmc_inuse & (1 << pmc)) | ||
| 365 | continue; | ||
| 366 | grp = (pmc >> 1) & 1; | ||
| 367 | if (unit) { | ||
| 368 | if (grp == (byte & 1)) | ||
| 369 | break; | ||
| 370 | } else if (pmc_grp_use[grp] < 4) { | ||
| 371 | ++pmc_grp_use[grp]; | ||
| 372 | break; | ||
| 373 | } | ||
| 374 | } | ||
| 375 | pmc_inuse |= 1 << pmc; | ||
| 376 | } else { | ||
| 377 | /* Direct event */ | ||
| 378 | --pmc; | ||
| 379 | if (psel == 0 && (byte & 2)) | ||
| 380 | /* add events on higher-numbered bus */ | ||
| 381 | mmcr1 |= 1ull << mmcr1_adder_bits[pmc]; | ||
| 382 | } | ||
| 383 | pmcsel[pmc] = psel; | ||
| 384 | hwc[i] = pmc; | ||
| 385 | spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK; | ||
| 386 | mmcr1 |= spcsel; | ||
| 387 | if (p970_marked_instr_event(event[i])) | ||
| 388 | mmcra |= MMCRA_SAMPLE_ENABLE; | ||
| 389 | } | ||
| 390 | for (pmc = 0; pmc < 2; ++pmc) | ||
| 391 | mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); | ||
| 392 | for (; pmc < 8; ++pmc) | ||
| 393 | mmcr1 |= (unsigned long)pmcsel[pmc] | ||
| 394 | << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); | ||
| 395 | if (pmc_inuse & 1) | ||
| 396 | mmcr0 |= MMCR0_PMC1CE; | ||
| 397 | if (pmc_inuse & 0xfe) | ||
| 398 | mmcr0 |= MMCR0_PMCjCE; | ||
| 399 | |||
| 400 | mmcra |= 0x2000; /* mark only one IOP per PPC instruction */ | ||
| 401 | |||
| 402 | /* Return MMCRx values */ | ||
| 403 | mmcr[0] = mmcr0; | ||
| 404 | mmcr[1] = mmcr1; | ||
| 405 | mmcr[2] = mmcra; | ||
| 406 | return 0; | ||
| 407 | } | ||
| 408 | |||
| 409 | static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | ||
| 410 | { | ||
| 411 | int shift, i; | ||
| 412 | |||
| 413 | if (pmc <= 1) { | ||
| 414 | shift = MMCR0_PMC1SEL_SH - 7 * pmc; | ||
| 415 | i = 0; | ||
| 416 | } else { | ||
| 417 | shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2); | ||
| 418 | i = 1; | ||
| 419 | } | ||
| 420 | /* | ||
| 421 | * Setting the PMCxSEL field to 0x08 disables PMC x. | ||
| 422 | */ | ||
| 423 | mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift); | ||
| 424 | } | ||
| 425 | |||
| 426 | static int ppc970_generic_events[] = { | ||
| 427 | [PERF_COUNT_HW_CPU_CYCLES] = 7, | ||
| 428 | [PERF_COUNT_HW_INSTRUCTIONS] = 1, | ||
| 429 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */ | ||
| 430 | [PERF_COUNT_HW_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */ | ||
| 431 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */ | ||
| 432 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */ | ||
| 433 | }; | ||
| 434 | |||
| 435 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 436 | |||
| 437 | /* | ||
| 438 | * Table of generalized cache-related events. | ||
| 439 | * 0 means not supported, -1 means nonsensical, other values | ||
| 440 | * are event codes. | ||
| 441 | */ | ||
| 442 | static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 443 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 444 | [C(OP_READ)] = { 0x8810, 0x3810 }, | ||
| 445 | [C(OP_WRITE)] = { 0x7810, 0x813 }, | ||
| 446 | [C(OP_PREFETCH)] = { 0x731, 0 }, | ||
| 447 | }, | ||
| 448 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 449 | [C(OP_READ)] = { 0, 0 }, | ||
| 450 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 451 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 452 | }, | ||
| 453 | [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 454 | [C(OP_READ)] = { 0, 0 }, | ||
| 455 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 456 | [C(OP_PREFETCH)] = { 0x733, 0 }, | ||
| 457 | }, | ||
| 458 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 459 | [C(OP_READ)] = { 0, 0x704 }, | ||
| 460 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 461 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 462 | }, | ||
| 463 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 464 | [C(OP_READ)] = { 0, 0x700 }, | ||
| 465 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 466 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 467 | }, | ||
| 468 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 469 | [C(OP_READ)] = { 0x431, 0x327 }, | ||
| 470 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 471 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 472 | }, | ||
| 473 | }; | ||
| 474 | |||
| 475 | static struct power_pmu ppc970_pmu = { | ||
| 476 | .name = "PPC970/FX/MP", | ||
| 477 | .n_counter = 8, | ||
| 478 | .max_alternatives = 2, | ||
| 479 | .add_fields = 0x001100005555ull, | ||
| 480 | .test_adder = 0x013300000000ull, | ||
| 481 | .compute_mmcr = p970_compute_mmcr, | ||
| 482 | .get_constraint = p970_get_constraint, | ||
| 483 | .get_alternatives = p970_get_alternatives, | ||
| 484 | .disable_pmc = p970_disable_pmc, | ||
| 485 | .n_generic = ARRAY_SIZE(ppc970_generic_events), | ||
| 486 | .generic_events = ppc970_generic_events, | ||
| 487 | .cache_events = &ppc970_cache_events, | ||
| 488 | }; | ||
| 489 | |||
| 490 | static int init_ppc970_pmu(void) | ||
| 491 | { | ||
| 492 | if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970") | ||
| 493 | && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP")) | ||
| 494 | return -ENODEV; | ||
| 495 | |||
| 496 | return register_power_pmu(&ppc970_pmu); | ||
| 497 | } | ||
| 498 | |||
| 499 | arch_initcall(init_ppc970_pmu); | ||
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 7b44a33f03c2..3e7135bbe40f 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c | |||
| @@ -650,7 +650,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, | |||
| 650 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + | 650 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
| 651 | _ALIGN_UP(sizeof(struct thread_info), 16); | 651 | _ALIGN_UP(sizeof(struct thread_info), 16); |
| 652 | 652 | ||
| 653 | #ifdef CONFIG_PPC64 | 653 | #ifdef CONFIG_PPC_STD_MMU_64 |
| 654 | if (cpu_has_feature(CPU_FTR_SLB)) { | 654 | if (cpu_has_feature(CPU_FTR_SLB)) { |
| 655 | unsigned long sp_vsid; | 655 | unsigned long sp_vsid; |
| 656 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | 656 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; |
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index ce01ff2474da..d4405b95bfaa 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c | |||
| @@ -585,7 +585,7 @@ static void __init check_cpu_pa_features(unsigned long node) | |||
| 585 | ibm_pa_features, ARRAY_SIZE(ibm_pa_features)); | 585 | ibm_pa_features, ARRAY_SIZE(ibm_pa_features)); |
| 586 | } | 586 | } |
| 587 | 587 | ||
| 588 | #ifdef CONFIG_PPC64 | 588 | #ifdef CONFIG_PPC_STD_MMU_64 |
| 589 | static void __init check_cpu_slb_size(unsigned long node) | 589 | static void __init check_cpu_slb_size(unsigned long node) |
| 590 | { | 590 | { |
| 591 | u32 *slb_size_ptr; | 591 | u32 *slb_size_ptr; |
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 2f0e64b53642..a538824616fd 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c | |||
| @@ -44,10 +44,7 @@ | |||
| 44 | #include <asm/sections.h> | 44 | #include <asm/sections.h> |
| 45 | #include <asm/machdep.h> | 45 | #include <asm/machdep.h> |
| 46 | 46 | ||
| 47 | #ifdef CONFIG_LOGO_LINUX_CLUT224 | ||
| 48 | #include <linux/linux_logo.h> | 47 | #include <linux/linux_logo.h> |
| 49 | extern const struct linux_logo logo_linux_clut224; | ||
| 50 | #endif | ||
| 51 | 48 | ||
| 52 | /* | 49 | /* |
| 53 | * Properties whose value is longer than this get excluded from our | 50 | * Properties whose value is longer than this get excluded from our |
| @@ -1950,8 +1947,47 @@ static void __init fixup_device_tree_maple(void) | |||
| 1950 | prom_setprop(isa, name, "ranges", | 1947 | prom_setprop(isa, name, "ranges", |
| 1951 | isa_ranges, sizeof(isa_ranges)); | 1948 | isa_ranges, sizeof(isa_ranges)); |
| 1952 | } | 1949 | } |
| 1950 | |||
| 1951 | #define CPC925_MC_START 0xf8000000 | ||
| 1952 | #define CPC925_MC_LENGTH 0x1000000 | ||
| 1953 | /* The values for memory-controller don't have right number of cells */ | ||
| 1954 | static void __init fixup_device_tree_maple_memory_controller(void) | ||
| 1955 | { | ||
| 1956 | phandle mc; | ||
| 1957 | u32 mc_reg[4]; | ||
| 1958 | char *name = "/hostbridge@f8000000"; | ||
| 1959 | struct prom_t *_prom = &RELOC(prom); | ||
| 1960 | u32 ac, sc; | ||
| 1961 | |||
| 1962 | mc = call_prom("finddevice", 1, 1, ADDR(name)); | ||
| 1963 | if (!PHANDLE_VALID(mc)) | ||
| 1964 | return; | ||
| 1965 | |||
| 1966 | if (prom_getproplen(mc, "reg") != 8) | ||
| 1967 | return; | ||
| 1968 | |||
| 1969 | prom_getprop(_prom->root, "#address-cells", &ac, sizeof(ac)); | ||
| 1970 | prom_getprop(_prom->root, "#size-cells", &sc, sizeof(sc)); | ||
| 1971 | if ((ac != 2) || (sc != 2)) | ||
| 1972 | return; | ||
| 1973 | |||
| 1974 | if (prom_getprop(mc, "reg", mc_reg, sizeof(mc_reg)) == PROM_ERROR) | ||
| 1975 | return; | ||
| 1976 | |||
| 1977 | if (mc_reg[0] != CPC925_MC_START || mc_reg[1] != CPC925_MC_LENGTH) | ||
| 1978 | return; | ||
| 1979 | |||
| 1980 | prom_printf("Fixing up bogus hostbridge on Maple...\n"); | ||
| 1981 | |||
| 1982 | mc_reg[0] = 0x0; | ||
| 1983 | mc_reg[1] = CPC925_MC_START; | ||
| 1984 | mc_reg[2] = 0x0; | ||
| 1985 | mc_reg[3] = CPC925_MC_LENGTH; | ||
| 1986 | prom_setprop(mc, name, "reg", mc_reg, sizeof(mc_reg)); | ||
| 1987 | } | ||
| 1953 | #else | 1988 | #else |
| 1954 | #define fixup_device_tree_maple() | 1989 | #define fixup_device_tree_maple() |
| 1990 | #define fixup_device_tree_maple_memory_controller() | ||
| 1955 | #endif | 1991 | #endif |
| 1956 | 1992 | ||
| 1957 | #ifdef CONFIG_PPC_CHRP | 1993 | #ifdef CONFIG_PPC_CHRP |
| @@ -2192,6 +2228,7 @@ static void __init fixup_device_tree_efika(void) | |||
| 2192 | static void __init fixup_device_tree(void) | 2228 | static void __init fixup_device_tree(void) |
| 2193 | { | 2229 | { |
| 2194 | fixup_device_tree_maple(); | 2230 | fixup_device_tree_maple(); |
| 2231 | fixup_device_tree_maple_memory_controller(); | ||
| 2195 | fixup_device_tree_chrp(); | 2232 | fixup_device_tree_chrp(); |
| 2196 | fixup_device_tree_pmac(); | 2233 | fixup_device_tree_pmac(); |
| 2197 | fixup_device_tree_efika(); | 2234 | fixup_device_tree_efika(); |
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 3635be61f899..9fa2c7dcd05a 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c | |||
| @@ -704,15 +704,34 @@ void user_enable_single_step(struct task_struct *task) | |||
| 704 | 704 | ||
| 705 | if (regs != NULL) { | 705 | if (regs != NULL) { |
| 706 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | 706 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) |
| 707 | task->thread.dbcr0 &= ~DBCR0_BT; | ||
| 707 | task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | 708 | task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
| 708 | regs->msr |= MSR_DE; | 709 | regs->msr |= MSR_DE; |
| 709 | #else | 710 | #else |
| 711 | regs->msr &= ~MSR_BE; | ||
| 710 | regs->msr |= MSR_SE; | 712 | regs->msr |= MSR_SE; |
| 711 | #endif | 713 | #endif |
| 712 | } | 714 | } |
| 713 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | 715 | set_tsk_thread_flag(task, TIF_SINGLESTEP); |
| 714 | } | 716 | } |
| 715 | 717 | ||
| 718 | void user_enable_block_step(struct task_struct *task) | ||
| 719 | { | ||
| 720 | struct pt_regs *regs = task->thread.regs; | ||
| 721 | |||
| 722 | if (regs != NULL) { | ||
| 723 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | ||
| 724 | task->thread.dbcr0 &= ~DBCR0_IC; | ||
| 725 | task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; | ||
| 726 | regs->msr |= MSR_DE; | ||
| 727 | #else | ||
| 728 | regs->msr &= ~MSR_SE; | ||
| 729 | regs->msr |= MSR_BE; | ||
| 730 | #endif | ||
| 731 | } | ||
| 732 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | ||
| 733 | } | ||
| 734 | |||
| 716 | void user_disable_single_step(struct task_struct *task) | 735 | void user_disable_single_step(struct task_struct *task) |
| 717 | { | 736 | { |
| 718 | struct pt_regs *regs = task->thread.regs; | 737 | struct pt_regs *regs = task->thread.regs; |
| @@ -726,10 +745,10 @@ void user_disable_single_step(struct task_struct *task) | |||
| 726 | 745 | ||
| 727 | if (regs != NULL) { | 746 | if (regs != NULL) { |
| 728 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | 747 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) |
| 729 | task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_IDM); | 748 | task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM); |
| 730 | regs->msr &= ~MSR_DE; | 749 | regs->msr &= ~MSR_DE; |
| 731 | #else | 750 | #else |
| 732 | regs->msr &= ~MSR_SE; | 751 | regs->msr &= ~(MSR_SE | MSR_BE); |
| 733 | #endif | 752 | #endif |
| 734 | } | 753 | } |
| 735 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | 754 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); |
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c index 8869001ab5d7..54e66da8f743 100644 --- a/arch/powerpc/kernel/rtas_pci.c +++ b/arch/powerpc/kernel/rtas_pci.c | |||
| @@ -93,10 +93,7 @@ static int rtas_pci_read_config(struct pci_bus *bus, | |||
| 93 | { | 93 | { |
| 94 | struct device_node *busdn, *dn; | 94 | struct device_node *busdn, *dn; |
| 95 | 95 | ||
| 96 | if (bus->self) | 96 | busdn = pci_bus_to_OF_node(bus); |
| 97 | busdn = pci_device_to_OF_node(bus->self); | ||
| 98 | else | ||
| 99 | busdn = bus->sysdata; /* must be a phb */ | ||
| 100 | 97 | ||
| 101 | /* Search only direct children of the bus */ | 98 | /* Search only direct children of the bus */ |
| 102 | for (dn = busdn->child; dn; dn = dn->sibling) { | 99 | for (dn = busdn->child; dn; dn = dn->sibling) { |
| @@ -140,10 +137,7 @@ static int rtas_pci_write_config(struct pci_bus *bus, | |||
| 140 | { | 137 | { |
| 141 | struct device_node *busdn, *dn; | 138 | struct device_node *busdn, *dn; |
| 142 | 139 | ||
| 143 | if (bus->self) | 140 | busdn = pci_bus_to_OF_node(bus); |
| 144 | busdn = pci_device_to_OF_node(bus->self); | ||
| 145 | else | ||
| 146 | busdn = bus->sysdata; /* must be a phb */ | ||
| 147 | 141 | ||
| 148 | /* Search only direct children of the bus */ | 142 | /* Search only direct children of the bus */ |
| 149 | for (dn = busdn->child; dn; dn = dn->sibling) { | 143 | for (dn = busdn->child; dn; dn = dn->sibling) { |
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 9e1ca745d8f0..1d154248cf40 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #include <asm/serial.h> | 39 | #include <asm/serial.h> |
| 40 | #include <asm/udbg.h> | 40 | #include <asm/udbg.h> |
| 41 | #include <asm/mmu_context.h> | 41 | #include <asm/mmu_context.h> |
| 42 | #include <asm/swiotlb.h> | ||
| 42 | 43 | ||
| 43 | #include "setup.h" | 44 | #include "setup.h" |
| 44 | 45 | ||
| @@ -332,6 +333,11 @@ void __init setup_arch(char **cmdline_p) | |||
| 332 | ppc_md.setup_arch(); | 333 | ppc_md.setup_arch(); |
| 333 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); | 334 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
| 334 | 335 | ||
| 336 | #ifdef CONFIG_SWIOTLB | ||
| 337 | if (ppc_swiotlb_enable) | ||
| 338 | swiotlb_init(); | ||
| 339 | #endif | ||
| 340 | |||
| 335 | paging_init(); | 341 | paging_init(); |
| 336 | 342 | ||
| 337 | /* Initialize the MMU context management stuff */ | 343 | /* Initialize the MMU context management stuff */ |
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index c410c606955d..1f6816003ebe 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c | |||
| @@ -61,6 +61,7 @@ | |||
| 61 | #include <asm/xmon.h> | 61 | #include <asm/xmon.h> |
| 62 | #include <asm/udbg.h> | 62 | #include <asm/udbg.h> |
| 63 | #include <asm/kexec.h> | 63 | #include <asm/kexec.h> |
| 64 | #include <asm/swiotlb.h> | ||
| 64 | 65 | ||
| 65 | #include "setup.h" | 66 | #include "setup.h" |
| 66 | 67 | ||
| @@ -417,12 +418,14 @@ void __init setup_system(void) | |||
| 417 | if (ppc64_caches.iline_size != 0x80) | 418 | if (ppc64_caches.iline_size != 0x80) |
| 418 | printk("ppc64_caches.icache_line_size = 0x%x\n", | 419 | printk("ppc64_caches.icache_line_size = 0x%x\n", |
| 419 | ppc64_caches.iline_size); | 420 | ppc64_caches.iline_size); |
| 421 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 420 | if (htab_address) | 422 | if (htab_address) |
| 421 | printk("htab_address = 0x%p\n", htab_address); | 423 | printk("htab_address = 0x%p\n", htab_address); |
| 422 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); | 424 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
| 425 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 423 | if (PHYSICAL_START > 0) | 426 | if (PHYSICAL_START > 0) |
| 424 | printk("physical_start = 0x%lx\n", | 427 | printk("physical_start = 0x%llx\n", |
| 425 | PHYSICAL_START); | 428 | (unsigned long long)PHYSICAL_START); |
| 426 | printk("-----------------------------------------------------\n"); | 429 | printk("-----------------------------------------------------\n"); |
| 427 | 430 | ||
| 428 | DBG(" <- setup_system()\n"); | 431 | DBG(" <- setup_system()\n"); |
| @@ -511,8 +514,9 @@ void __init setup_arch(char **cmdline_p) | |||
| 511 | irqstack_early_init(); | 514 | irqstack_early_init(); |
| 512 | emergency_stack_init(); | 515 | emergency_stack_init(); |
| 513 | 516 | ||
| 517 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 514 | stabs_alloc(); | 518 | stabs_alloc(); |
| 515 | 519 | #endif | |
| 516 | /* set up the bootmem stuff with available memory */ | 520 | /* set up the bootmem stuff with available memory */ |
| 517 | do_init_bootmem(); | 521 | do_init_bootmem(); |
| 518 | sparse_init(); | 522 | sparse_init(); |
| @@ -524,6 +528,11 @@ void __init setup_arch(char **cmdline_p) | |||
| 524 | if (ppc_md.setup_arch) | 528 | if (ppc_md.setup_arch) |
| 525 | ppc_md.setup_arch(); | 529 | ppc_md.setup_arch(); |
| 526 | 530 | ||
| 531 | #ifdef CONFIG_SWIOTLB | ||
| 532 | if (ppc_swiotlb_enable) | ||
| 533 | swiotlb_init(); | ||
| 534 | #endif | ||
| 535 | |||
| 527 | paging_init(); | 536 | paging_init(); |
| 528 | ppc64_boot_msg(0x15, "Setup Done"); | 537 | ppc64_boot_msg(0x15, "Setup Done"); |
| 529 | } | 538 | } |
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 48571ac56fb7..eae4511ceeac 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c | |||
| @@ -52,6 +52,8 @@ | |||
| 52 | #include <linux/jiffies.h> | 52 | #include <linux/jiffies.h> |
| 53 | #include <linux/posix-timers.h> | 53 | #include <linux/posix-timers.h> |
| 54 | #include <linux/irq.h> | 54 | #include <linux/irq.h> |
| 55 | #include <linux/delay.h> | ||
| 56 | #include <linux/perf_counter.h> | ||
| 55 | 57 | ||
| 56 | #include <asm/io.h> | 58 | #include <asm/io.h> |
| 57 | #include <asm/processor.h> | 59 | #include <asm/processor.h> |
| @@ -109,7 +111,7 @@ static void decrementer_set_mode(enum clock_event_mode mode, | |||
| 109 | static struct clock_event_device decrementer_clockevent = { | 111 | static struct clock_event_device decrementer_clockevent = { |
| 110 | .name = "decrementer", | 112 | .name = "decrementer", |
| 111 | .rating = 200, | 113 | .rating = 200, |
| 112 | .shift = 16, | 114 | .shift = 0, /* To be filled in */ |
| 113 | .mult = 0, /* To be filled in */ | 115 | .mult = 0, /* To be filled in */ |
| 114 | .irq = 0, | 116 | .irq = 0, |
| 115 | .set_next_event = decrementer_set_next_event, | 117 | .set_next_event = decrementer_set_next_event, |
| @@ -524,6 +526,26 @@ void __init iSeries_time_init_early(void) | |||
| 524 | } | 526 | } |
| 525 | #endif /* CONFIG_PPC_ISERIES */ | 527 | #endif /* CONFIG_PPC_ISERIES */ |
| 526 | 528 | ||
| 529 | #if defined(CONFIG_PERF_COUNTERS) && defined(CONFIG_PPC32) | ||
| 530 | DEFINE_PER_CPU(u8, perf_counter_pending); | ||
| 531 | |||
| 532 | void set_perf_counter_pending(void) | ||
| 533 | { | ||
| 534 | get_cpu_var(perf_counter_pending) = 1; | ||
| 535 | set_dec(1); | ||
| 536 | put_cpu_var(perf_counter_pending); | ||
| 537 | } | ||
| 538 | |||
| 539 | #define test_perf_counter_pending() __get_cpu_var(perf_counter_pending) | ||
| 540 | #define clear_perf_counter_pending() __get_cpu_var(perf_counter_pending) = 0 | ||
| 541 | |||
| 542 | #else /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ | ||
| 543 | |||
| 544 | #define test_perf_counter_pending() 0 | ||
| 545 | #define clear_perf_counter_pending() | ||
| 546 | |||
| 547 | #endif /* CONFIG_PERF_COUNTERS && CONFIG_PPC32 */ | ||
| 548 | |||
| 527 | /* | 549 | /* |
| 528 | * For iSeries shared processors, we have to let the hypervisor | 550 | * For iSeries shared processors, we have to let the hypervisor |
| 529 | * set the hardware decrementer. We set a virtual decrementer | 551 | * set the hardware decrementer. We set a virtual decrementer |
| @@ -550,6 +572,10 @@ void timer_interrupt(struct pt_regs * regs) | |||
| 550 | set_dec(DECREMENTER_MAX); | 572 | set_dec(DECREMENTER_MAX); |
| 551 | 573 | ||
| 552 | #ifdef CONFIG_PPC32 | 574 | #ifdef CONFIG_PPC32 |
| 575 | if (test_perf_counter_pending()) { | ||
| 576 | clear_perf_counter_pending(); | ||
| 577 | perf_counter_do_pending(); | ||
| 578 | } | ||
| 553 | if (atomic_read(&ppc_n_lost_interrupts) != 0) | 579 | if (atomic_read(&ppc_n_lost_interrupts) != 0) |
| 554 | do_IRQ(regs); | 580 | do_IRQ(regs); |
| 555 | #endif | 581 | #endif |
| @@ -843,6 +869,22 @@ static void decrementer_set_mode(enum clock_event_mode mode, | |||
| 843 | decrementer_set_next_event(DECREMENTER_MAX, dev); | 869 | decrementer_set_next_event(DECREMENTER_MAX, dev); |
| 844 | } | 870 | } |
| 845 | 871 | ||
| 872 | static void __init setup_clockevent_multiplier(unsigned long hz) | ||
| 873 | { | ||
| 874 | u64 mult, shift = 32; | ||
| 875 | |||
| 876 | while (1) { | ||
| 877 | mult = div_sc(hz, NSEC_PER_SEC, shift); | ||
| 878 | if (mult && (mult >> 32UL) == 0UL) | ||
| 879 | break; | ||
| 880 | |||
| 881 | shift--; | ||
| 882 | } | ||
| 883 | |||
| 884 | decrementer_clockevent.shift = shift; | ||
| 885 | decrementer_clockevent.mult = mult; | ||
| 886 | } | ||
| 887 | |||
| 846 | static void register_decrementer_clockevent(int cpu) | 888 | static void register_decrementer_clockevent(int cpu) |
| 847 | { | 889 | { |
| 848 | struct clock_event_device *dec = &per_cpu(decrementers, cpu).event; | 890 | struct clock_event_device *dec = &per_cpu(decrementers, cpu).event; |
| @@ -860,8 +902,7 @@ static void __init init_decrementer_clockevent(void) | |||
| 860 | { | 902 | { |
| 861 | int cpu = smp_processor_id(); | 903 | int cpu = smp_processor_id(); |
| 862 | 904 | ||
| 863 | decrementer_clockevent.mult = div_sc(ppc_tb_freq, NSEC_PER_SEC, | 905 | setup_clockevent_multiplier(ppc_tb_freq); |
| 864 | decrementer_clockevent.shift); | ||
| 865 | decrementer_clockevent.max_delta_ns = | 906 | decrementer_clockevent.max_delta_ns = |
| 866 | clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent); | 907 | clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent); |
| 867 | decrementer_clockevent.min_delta_ns = | 908 | decrementer_clockevent.min_delta_ns = |
| @@ -1128,6 +1169,15 @@ void div128_by_32(u64 dividend_high, u64 dividend_low, | |||
| 1128 | 1169 | ||
| 1129 | } | 1170 | } |
| 1130 | 1171 | ||
| 1172 | /* We don't need to calibrate delay, we use the CPU timebase for that */ | ||
| 1173 | void calibrate_delay(void) | ||
| 1174 | { | ||
| 1175 | /* Some generic code (such as spinlock debug) use loops_per_jiffy | ||
| 1176 | * as the number of __delay(1) in a jiffy, so make it so | ||
| 1177 | */ | ||
| 1178 | loops_per_jiffy = tb_ticks_per_jiffy; | ||
| 1179 | } | ||
| 1180 | |||
| 1131 | static int __init rtc_init(void) | 1181 | static int __init rtc_init(void) |
| 1132 | { | 1182 | { |
| 1133 | struct platform_device *pdev; | 1183 | struct platform_device *pdev; |
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 678fbff0d206..6f0ae1a9bfae 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c | |||
| @@ -33,7 +33,9 @@ | |||
| 33 | #include <linux/backlight.h> | 33 | #include <linux/backlight.h> |
| 34 | #include <linux/bug.h> | 34 | #include <linux/bug.h> |
| 35 | #include <linux/kdebug.h> | 35 | #include <linux/kdebug.h> |
| 36 | #include <linux/debugfs.h> | ||
| 36 | 37 | ||
| 38 | #include <asm/emulated_ops.h> | ||
| 37 | #include <asm/pgtable.h> | 39 | #include <asm/pgtable.h> |
| 38 | #include <asm/uaccess.h> | 40 | #include <asm/uaccess.h> |
| 39 | #include <asm/system.h> | 41 | #include <asm/system.h> |
| @@ -757,36 +759,44 @@ static int emulate_instruction(struct pt_regs *regs) | |||
| 757 | 759 | ||
| 758 | /* Emulate the mfspr rD, PVR. */ | 760 | /* Emulate the mfspr rD, PVR. */ |
| 759 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { | 761 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
| 762 | PPC_WARN_EMULATED(mfpvr); | ||
| 760 | rd = (instword >> 21) & 0x1f; | 763 | rd = (instword >> 21) & 0x1f; |
| 761 | regs->gpr[rd] = mfspr(SPRN_PVR); | 764 | regs->gpr[rd] = mfspr(SPRN_PVR); |
| 762 | return 0; | 765 | return 0; |
| 763 | } | 766 | } |
| 764 | 767 | ||
| 765 | /* Emulating the dcba insn is just a no-op. */ | 768 | /* Emulating the dcba insn is just a no-op. */ |
| 766 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) | 769 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
| 770 | PPC_WARN_EMULATED(dcba); | ||
| 767 | return 0; | 771 | return 0; |
| 772 | } | ||
| 768 | 773 | ||
| 769 | /* Emulate the mcrxr insn. */ | 774 | /* Emulate the mcrxr insn. */ |
| 770 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { | 775 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
| 771 | int shift = (instword >> 21) & 0x1c; | 776 | int shift = (instword >> 21) & 0x1c; |
| 772 | unsigned long msk = 0xf0000000UL >> shift; | 777 | unsigned long msk = 0xf0000000UL >> shift; |
| 773 | 778 | ||
| 779 | PPC_WARN_EMULATED(mcrxr); | ||
| 774 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | 780 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
| 775 | regs->xer &= ~0xf0000000UL; | 781 | regs->xer &= ~0xf0000000UL; |
| 776 | return 0; | 782 | return 0; |
| 777 | } | 783 | } |
| 778 | 784 | ||
| 779 | /* Emulate load/store string insn. */ | 785 | /* Emulate load/store string insn. */ |
| 780 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) | 786 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
| 787 | PPC_WARN_EMULATED(string); | ||
| 781 | return emulate_string_inst(regs, instword); | 788 | return emulate_string_inst(regs, instword); |
| 789 | } | ||
| 782 | 790 | ||
| 783 | /* Emulate the popcntb (Population Count Bytes) instruction. */ | 791 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
| 784 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { | 792 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
| 793 | PPC_WARN_EMULATED(popcntb); | ||
| 785 | return emulate_popcntb_inst(regs, instword); | 794 | return emulate_popcntb_inst(regs, instword); |
| 786 | } | 795 | } |
| 787 | 796 | ||
| 788 | /* Emulate isel (Integer Select) instruction */ | 797 | /* Emulate isel (Integer Select) instruction */ |
| 789 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { | 798 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
| 799 | PPC_WARN_EMULATED(isel); | ||
| 790 | return emulate_isel(regs, instword); | 800 | return emulate_isel(regs, instword); |
| 791 | } | 801 | } |
| 792 | 802 | ||
| @@ -984,6 +994,8 @@ void SoftwareEmulation(struct pt_regs *regs) | |||
| 984 | 994 | ||
| 985 | #ifdef CONFIG_MATH_EMULATION | 995 | #ifdef CONFIG_MATH_EMULATION |
| 986 | errcode = do_mathemu(regs); | 996 | errcode = do_mathemu(regs); |
| 997 | if (errcode >= 0) | ||
| 998 | PPC_WARN_EMULATED(math); | ||
| 987 | 999 | ||
| 988 | switch (errcode) { | 1000 | switch (errcode) { |
| 989 | case 0: | 1001 | case 0: |
| @@ -1005,6 +1017,9 @@ void SoftwareEmulation(struct pt_regs *regs) | |||
| 1005 | 1017 | ||
| 1006 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | 1018 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1007 | errcode = Soft_emulate_8xx(regs); | 1019 | errcode = Soft_emulate_8xx(regs); |
| 1020 | if (errcode >= 0) | ||
| 1021 | PPC_WARN_EMULATED(8xx); | ||
| 1022 | |||
| 1008 | switch (errcode) { | 1023 | switch (errcode) { |
| 1009 | case 0: | 1024 | case 0: |
| 1010 | emulate_single_step(regs); | 1025 | emulate_single_step(regs); |
| @@ -1026,7 +1041,34 @@ void SoftwareEmulation(struct pt_regs *regs) | |||
| 1026 | 1041 | ||
| 1027 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) | 1042 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
| 1028 | { | 1043 | { |
| 1029 | if (debug_status & DBSR_IC) { /* instruction completion */ | 1044 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
| 1045 | * on server, it stops on the target of the branch. In order to simulate | ||
| 1046 | * the server behaviour, we thus restart right away with a single step | ||
| 1047 | * instead of stopping here when hitting a BT | ||
| 1048 | */ | ||
| 1049 | if (debug_status & DBSR_BT) { | ||
| 1050 | regs->msr &= ~MSR_DE; | ||
| 1051 | |||
| 1052 | /* Disable BT */ | ||
| 1053 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | ||
| 1054 | /* Clear the BT event */ | ||
| 1055 | mtspr(SPRN_DBSR, DBSR_BT); | ||
| 1056 | |||
| 1057 | /* Do the single step trick only when coming from userspace */ | ||
| 1058 | if (user_mode(regs)) { | ||
| 1059 | current->thread.dbcr0 &= ~DBCR0_BT; | ||
| 1060 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | ||
| 1061 | regs->msr |= MSR_DE; | ||
| 1062 | return; | ||
| 1063 | } | ||
| 1064 | |||
| 1065 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | ||
| 1066 | 5, SIGTRAP) == NOTIFY_STOP) { | ||
| 1067 | return; | ||
| 1068 | } | ||
| 1069 | if (debugger_sstep(regs)) | ||
| 1070 | return; | ||
| 1071 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | ||
| 1030 | regs->msr &= ~MSR_DE; | 1072 | regs->msr &= ~MSR_DE; |
| 1031 | 1073 | ||
| 1032 | /* Disable instruction completion */ | 1074 | /* Disable instruction completion */ |
| @@ -1042,9 +1084,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) | |||
| 1042 | if (debugger_sstep(regs)) | 1084 | if (debugger_sstep(regs)) |
| 1043 | return; | 1085 | return; |
| 1044 | 1086 | ||
| 1045 | if (user_mode(regs)) { | 1087 | if (user_mode(regs)) |
| 1046 | current->thread.dbcr0 &= ~DBCR0_IC; | 1088 | current->thread.dbcr0 &= ~(DBCR0_IC); |
| 1047 | } | ||
| 1048 | 1089 | ||
| 1049 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | 1090 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 1050 | } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | 1091 | } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
| @@ -1088,6 +1129,7 @@ void altivec_assist_exception(struct pt_regs *regs) | |||
| 1088 | 1129 | ||
| 1089 | flush_altivec_to_thread(current); | 1130 | flush_altivec_to_thread(current); |
| 1090 | 1131 | ||
| 1132 | PPC_WARN_EMULATED(altivec); | ||
| 1091 | err = emulate_altivec(regs); | 1133 | err = emulate_altivec(regs); |
| 1092 | if (err == 0) { | 1134 | if (err == 0) { |
| 1093 | regs->nip += 4; /* skip emulated instruction */ | 1135 | regs->nip += 4; /* skip emulated instruction */ |
| @@ -1286,3 +1328,79 @@ void kernel_bad_stack(struct pt_regs *regs) | |||
| 1286 | void __init trap_init(void) | 1328 | void __init trap_init(void) |
| 1287 | { | 1329 | { |
| 1288 | } | 1330 | } |
| 1331 | |||
| 1332 | |||
| 1333 | #ifdef CONFIG_PPC_EMULATED_STATS | ||
| 1334 | |||
| 1335 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | ||
| 1336 | |||
| 1337 | struct ppc_emulated ppc_emulated = { | ||
| 1338 | #ifdef CONFIG_ALTIVEC | ||
| 1339 | WARN_EMULATED_SETUP(altivec), | ||
| 1340 | #endif | ||
| 1341 | WARN_EMULATED_SETUP(dcba), | ||
| 1342 | WARN_EMULATED_SETUP(dcbz), | ||
| 1343 | WARN_EMULATED_SETUP(fp_pair), | ||
| 1344 | WARN_EMULATED_SETUP(isel), | ||
| 1345 | WARN_EMULATED_SETUP(mcrxr), | ||
| 1346 | WARN_EMULATED_SETUP(mfpvr), | ||
| 1347 | WARN_EMULATED_SETUP(multiple), | ||
| 1348 | WARN_EMULATED_SETUP(popcntb), | ||
| 1349 | WARN_EMULATED_SETUP(spe), | ||
| 1350 | WARN_EMULATED_SETUP(string), | ||
| 1351 | WARN_EMULATED_SETUP(unaligned), | ||
| 1352 | #ifdef CONFIG_MATH_EMULATION | ||
| 1353 | WARN_EMULATED_SETUP(math), | ||
| 1354 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | ||
| 1355 | WARN_EMULATED_SETUP(8xx), | ||
| 1356 | #endif | ||
| 1357 | #ifdef CONFIG_VSX | ||
| 1358 | WARN_EMULATED_SETUP(vsx), | ||
| 1359 | #endif | ||
| 1360 | }; | ||
| 1361 | |||
| 1362 | u32 ppc_warn_emulated; | ||
| 1363 | |||
| 1364 | void ppc_warn_emulated_print(const char *type) | ||
| 1365 | { | ||
| 1366 | if (printk_ratelimit()) | ||
| 1367 | pr_warning("%s used emulated %s instruction\n", current->comm, | ||
| 1368 | type); | ||
| 1369 | } | ||
| 1370 | |||
| 1371 | static int __init ppc_warn_emulated_init(void) | ||
| 1372 | { | ||
| 1373 | struct dentry *dir, *d; | ||
| 1374 | unsigned int i; | ||
| 1375 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | ||
| 1376 | |||
| 1377 | if (!powerpc_debugfs_root) | ||
| 1378 | return -ENODEV; | ||
| 1379 | |||
| 1380 | dir = debugfs_create_dir("emulated_instructions", | ||
| 1381 | powerpc_debugfs_root); | ||
| 1382 | if (!dir) | ||
| 1383 | return -ENOMEM; | ||
| 1384 | |||
| 1385 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | ||
| 1386 | &ppc_warn_emulated); | ||
| 1387 | if (!d) | ||
| 1388 | goto fail; | ||
| 1389 | |||
| 1390 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | ||
| 1391 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | ||
| 1392 | (u32 *)&entries[i].val.counter); | ||
| 1393 | if (!d) | ||
| 1394 | goto fail; | ||
| 1395 | } | ||
| 1396 | |||
| 1397 | return 0; | ||
| 1398 | |||
| 1399 | fail: | ||
| 1400 | debugfs_remove_recursive(dir); | ||
| 1401 | return -ENOMEM; | ||
| 1402 | } | ||
| 1403 | |||
| 1404 | device_initcall(ppc_warn_emulated_init); | ||
| 1405 | |||
| 1406 | #endif /* CONFIG_PPC_EMULATED_STATS */ | ||
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S index 49ac3d6e1399..ef36cbbc5882 100644 --- a/arch/powerpc/kernel/vector.S +++ b/arch/powerpc/kernel/vector.S | |||
| @@ -1,5 +1,215 @@ | |||
| 1 | #include <asm/processor.h> | ||
| 1 | #include <asm/ppc_asm.h> | 2 | #include <asm/ppc_asm.h> |
| 2 | #include <asm/reg.h> | 3 | #include <asm/reg.h> |
| 4 | #include <asm/asm-offsets.h> | ||
| 5 | #include <asm/cputable.h> | ||
| 6 | #include <asm/thread_info.h> | ||
| 7 | #include <asm/page.h> | ||
| 8 | |||
| 9 | /* | ||
| 10 | * load_up_altivec(unused, unused, tsk) | ||
| 11 | * Disable VMX for the task which had it previously, | ||
| 12 | * and save its vector registers in its thread_struct. | ||
| 13 | * Enables the VMX for use in the kernel on return. | ||
| 14 | * On SMP we know the VMX is free, since we give it up every | ||
| 15 | * switch (ie, no lazy save of the vector registers). | ||
| 16 | */ | ||
| 17 | _GLOBAL(load_up_altivec) | ||
| 18 | mfmsr r5 /* grab the current MSR */ | ||
| 19 | oris r5,r5,MSR_VEC@h | ||
| 20 | MTMSRD(r5) /* enable use of AltiVec now */ | ||
| 21 | isync | ||
| 22 | |||
| 23 | /* | ||
| 24 | * For SMP, we don't do lazy VMX switching because it just gets too | ||
| 25 | * horrendously complex, especially when a task switches from one CPU | ||
| 26 | * to another. Instead we call giveup_altvec in switch_to. | ||
| 27 | * VRSAVE isn't dealt with here, that is done in the normal context | ||
| 28 | * switch code. Note that we could rely on vrsave value to eventually | ||
| 29 | * avoid saving all of the VREGs here... | ||
| 30 | */ | ||
| 31 | #ifndef CONFIG_SMP | ||
| 32 | LOAD_REG_ADDRBASE(r3, last_task_used_altivec) | ||
| 33 | toreal(r3) | ||
| 34 | PPC_LL r4,ADDROFF(last_task_used_altivec)(r3) | ||
| 35 | PPC_LCMPI 0,r4,0 | ||
| 36 | beq 1f | ||
| 37 | |||
| 38 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | ||
| 39 | toreal(r4) | ||
| 40 | addi r4,r4,THREAD | ||
| 41 | SAVE_32VRS(0,r5,r4) | ||
| 42 | mfvscr vr0 | ||
| 43 | li r10,THREAD_VSCR | ||
| 44 | stvx vr0,r10,r4 | ||
| 45 | /* Disable VMX for last_task_used_altivec */ | ||
| 46 | PPC_LL r5,PT_REGS(r4) | ||
| 47 | toreal(r5) | ||
| 48 | PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 49 | lis r10,MSR_VEC@h | ||
| 50 | andc r4,r4,r10 | ||
| 51 | PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 52 | 1: | ||
| 53 | #endif /* CONFIG_SMP */ | ||
| 54 | |||
| 55 | /* Hack: if we get an altivec unavailable trap with VRSAVE | ||
| 56 | * set to all zeros, we assume this is a broken application | ||
| 57 | * that fails to set it properly, and thus we switch it to | ||
| 58 | * all 1's | ||
| 59 | */ | ||
| 60 | mfspr r4,SPRN_VRSAVE | ||
| 61 | cmpdi 0,r4,0 | ||
| 62 | bne+ 1f | ||
| 63 | li r4,-1 | ||
| 64 | mtspr SPRN_VRSAVE,r4 | ||
| 65 | 1: | ||
| 66 | /* enable use of VMX after return */ | ||
| 67 | #ifdef CONFIG_PPC32 | ||
| 68 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | ||
| 69 | oris r9,r9,MSR_VEC@h | ||
| 70 | #else | ||
| 71 | ld r4,PACACURRENT(r13) | ||
| 72 | addi r5,r4,THREAD /* Get THREAD */ | ||
| 73 | oris r12,r12,MSR_VEC@h | ||
| 74 | std r12,_MSR(r1) | ||
| 75 | #endif | ||
| 76 | li r4,1 | ||
| 77 | li r10,THREAD_VSCR | ||
| 78 | stw r4,THREAD_USED_VR(r5) | ||
| 79 | lvx vr0,r10,r5 | ||
| 80 | mtvscr vr0 | ||
| 81 | REST_32VRS(0,r4,r5) | ||
| 82 | #ifndef CONFIG_SMP | ||
| 83 | /* Update last_task_used_math to 'current' */ | ||
| 84 | subi r4,r5,THREAD /* Back to 'current' */ | ||
| 85 | fromreal(r4) | ||
| 86 | PPC_STL r4,ADDROFF(last_task_used_math)(r3) | ||
| 87 | #endif /* CONFIG_SMP */ | ||
| 88 | /* restore registers and return */ | ||
| 89 | blr | ||
| 90 | |||
| 91 | /* | ||
| 92 | * giveup_altivec(tsk) | ||
| 93 | * Disable VMX for the task given as the argument, | ||
| 94 | * and save the vector registers in its thread_struct. | ||
| 95 | * Enables the VMX for use in the kernel on return. | ||
| 96 | */ | ||
| 97 | _GLOBAL(giveup_altivec) | ||
| 98 | mfmsr r5 | ||
| 99 | oris r5,r5,MSR_VEC@h | ||
| 100 | SYNC | ||
| 101 | MTMSRD(r5) /* enable use of VMX now */ | ||
| 102 | isync | ||
| 103 | PPC_LCMPI 0,r3,0 | ||
| 104 | beqlr- /* if no previous owner, done */ | ||
| 105 | addi r3,r3,THREAD /* want THREAD of task */ | ||
| 106 | PPC_LL r5,PT_REGS(r3) | ||
| 107 | PPC_LCMPI 0,r5,0 | ||
| 108 | SAVE_32VRS(0,r4,r3) | ||
| 109 | mfvscr vr0 | ||
| 110 | li r4,THREAD_VSCR | ||
| 111 | stvx vr0,r4,r3 | ||
| 112 | beq 1f | ||
| 113 | PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 114 | #ifdef CONFIG_VSX | ||
| 115 | BEGIN_FTR_SECTION | ||
| 116 | lis r3,(MSR_VEC|MSR_VSX)@h | ||
| 117 | FTR_SECTION_ELSE | ||
| 118 | lis r3,MSR_VEC@h | ||
| 119 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | ||
| 120 | #else | ||
| 121 | lis r3,MSR_VEC@h | ||
| 122 | #endif | ||
| 123 | andc r4,r4,r3 /* disable FP for previous task */ | ||
| 124 | PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 125 | 1: | ||
| 126 | #ifndef CONFIG_SMP | ||
| 127 | li r5,0 | ||
| 128 | LOAD_REG_ADDRBASE(r4,last_task_used_altivec) | ||
| 129 | PPC_STL r5,ADDROFF(last_task_used_altivec)(r4) | ||
| 130 | #endif /* CONFIG_SMP */ | ||
| 131 | blr | ||
| 132 | |||
| 133 | #ifdef CONFIG_VSX | ||
| 134 | |||
| 135 | #ifdef CONFIG_PPC32 | ||
| 136 | #error This asm code isn't ready for 32-bit kernels | ||
| 137 | #endif | ||
| 138 | |||
| 139 | /* | ||
| 140 | * load_up_vsx(unused, unused, tsk) | ||
| 141 | * Disable VSX for the task which had it previously, | ||
| 142 | * and save its vector registers in its thread_struct. | ||
| 143 | * Reuse the fp and vsx saves, but first check to see if they have | ||
| 144 | * been saved already. | ||
| 145 | */ | ||
| 146 | _GLOBAL(load_up_vsx) | ||
| 147 | /* Load FP and VSX registers if they haven't been done yet */ | ||
| 148 | andi. r5,r12,MSR_FP | ||
| 149 | beql+ load_up_fpu /* skip if already loaded */ | ||
| 150 | andis. r5,r12,MSR_VEC@h | ||
| 151 | beql+ load_up_altivec /* skip if already loaded */ | ||
| 152 | |||
| 153 | #ifndef CONFIG_SMP | ||
| 154 | ld r3,last_task_used_vsx@got(r2) | ||
| 155 | ld r4,0(r3) | ||
| 156 | cmpdi 0,r4,0 | ||
| 157 | beq 1f | ||
| 158 | /* Disable VSX for last_task_used_vsx */ | ||
| 159 | addi r4,r4,THREAD | ||
| 160 | ld r5,PT_REGS(r4) | ||
| 161 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 162 | lis r6,MSR_VSX@h | ||
| 163 | andc r6,r4,r6 | ||
| 164 | std r6,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 165 | 1: | ||
| 166 | #endif /* CONFIG_SMP */ | ||
| 167 | ld r4,PACACURRENT(r13) | ||
| 168 | addi r4,r4,THREAD /* Get THREAD */ | ||
| 169 | li r6,1 | ||
| 170 | stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */ | ||
| 171 | /* enable use of VSX after return */ | ||
| 172 | oris r12,r12,MSR_VSX@h | ||
| 173 | std r12,_MSR(r1) | ||
| 174 | #ifndef CONFIG_SMP | ||
| 175 | /* Update last_task_used_math to 'current' */ | ||
| 176 | ld r4,PACACURRENT(r13) | ||
| 177 | std r4,0(r3) | ||
| 178 | #endif /* CONFIG_SMP */ | ||
| 179 | b fast_exception_return | ||
| 180 | |||
| 181 | /* | ||
| 182 | * __giveup_vsx(tsk) | ||
| 183 | * Disable VSX for the task given as the argument. | ||
| 184 | * Does NOT save vsx registers. | ||
| 185 | * Enables the VSX for use in the kernel on return. | ||
| 186 | */ | ||
| 187 | _GLOBAL(__giveup_vsx) | ||
| 188 | mfmsr r5 | ||
| 189 | oris r5,r5,MSR_VSX@h | ||
| 190 | mtmsrd r5 /* enable use of VSX now */ | ||
| 191 | isync | ||
| 192 | |||
| 193 | cmpdi 0,r3,0 | ||
| 194 | beqlr- /* if no previous owner, done */ | ||
| 195 | addi r3,r3,THREAD /* want THREAD of task */ | ||
| 196 | ld r5,PT_REGS(r3) | ||
| 197 | cmpdi 0,r5,0 | ||
| 198 | beq 1f | ||
| 199 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 200 | lis r3,MSR_VSX@h | ||
| 201 | andc r4,r4,r3 /* disable VSX for previous task */ | ||
| 202 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | ||
| 203 | 1: | ||
| 204 | #ifndef CONFIG_SMP | ||
| 205 | li r5,0 | ||
| 206 | ld r4,last_task_used_vsx@got(r2) | ||
| 207 | std r5,0(r4) | ||
| 208 | #endif /* CONFIG_SMP */ | ||
| 209 | blr | ||
| 210 | |||
| 211 | #endif /* CONFIG_VSX */ | ||
| 212 | |||
| 3 | 213 | ||
| 4 | /* | 214 | /* |
| 5 | * The routines below are in assembler so we can closely control the | 215 | * The routines below are in assembler so we can closely control the |
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile index 4b2df66c79d8..459c7ee580f7 100644 --- a/arch/powerpc/kvm/Makefile +++ b/arch/powerpc/kvm/Makefile | |||
| @@ -2,6 +2,8 @@ | |||
| 2 | # Makefile for Kernel-based Virtual Machine module | 2 | # Makefile for Kernel-based Virtual Machine module |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 6 | |||
| 5 | EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm | 7 | EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm |
| 6 | 8 | ||
| 7 | common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) | 9 | common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) |
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index 9057335fdc61..2cf915e51e7e 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c | |||
| @@ -41,6 +41,12 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *v) | |||
| 41 | return !!(v->arch.pending_exceptions); | 41 | return !!(v->arch.pending_exceptions); |
| 42 | } | 42 | } |
| 43 | 43 | ||
| 44 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | ||
| 45 | { | ||
| 46 | /* do real check here */ | ||
| 47 | return 1; | ||
| 48 | } | ||
| 49 | |||
| 44 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) | 50 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) |
| 45 | { | 51 | { |
| 46 | return !(v->arch.msr & MSR_WE); | 52 | return !(v->arch.msr & MSR_WE); |
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 29b742b90f1f..3040dac18a37 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile | |||
| @@ -2,6 +2,8 @@ | |||
| 2 | # Makefile for ppc-specific library files.. | 2 | # Makefile for ppc-specific library files.. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 6 | |||
| 5 | ifeq ($(CONFIG_PPC64),y) | 7 | ifeq ($(CONFIG_PPC64),y) |
| 6 | EXTRA_CFLAGS += -mno-minimal-toc | 8 | EXTRA_CFLAGS += -mno-minimal-toc |
| 7 | endif | 9 | endif |
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index b746f4ca4209..2d2192e48de7 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile | |||
| @@ -2,6 +2,8 @@ | |||
| 2 | # Makefile for the linux ppc-specific parts of the memory manager. | 2 | # Makefile for the linux ppc-specific parts of the memory manager. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 6 | |||
| 5 | ifeq ($(CONFIG_PPC64),y) | 7 | ifeq ($(CONFIG_PPC64),y) |
| 6 | EXTRA_CFLAGS += -mno-minimal-toc | 8 | EXTRA_CFLAGS += -mno-minimal-toc |
| 7 | endif | 9 | endif |
| @@ -11,10 +13,11 @@ obj-y := fault.o mem.o pgtable.o gup.o \ | |||
| 11 | pgtable_$(CONFIG_WORD_SIZE).o | 13 | pgtable_$(CONFIG_WORD_SIZE).o |
| 12 | obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \ | 14 | obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \ |
| 13 | tlb_nohash_low.o | 15 | tlb_nohash_low.o |
| 14 | hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o | 16 | obj-$(CONFIG_PPC64) += mmap_64.o |
| 15 | obj-$(CONFIG_PPC64) += hash_utils_64.o \ | 17 | hash64-$(CONFIG_PPC_NATIVE) := hash_native_64.o |
| 18 | obj-$(CONFIG_PPC_STD_MMU_64) += hash_utils_64.o \ | ||
| 16 | slb_low.o slb.o stab.o \ | 19 | slb_low.o slb.o stab.o \ |
| 17 | mmap_64.o $(hash-y) | 20 | mmap_64.o $(hash64-y) |
| 18 | obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o | 21 | obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o |
| 19 | obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ | 22 | obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ |
| 20 | tlb_hash$(CONFIG_WORD_SIZE).o \ | 23 | tlb_hash$(CONFIG_WORD_SIZE).o \ |
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 76993941cac9..830bef0a1131 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/module.h> | 29 | #include <linux/module.h> |
| 30 | #include <linux/kprobes.h> | 30 | #include <linux/kprobes.h> |
| 31 | #include <linux/kdebug.h> | 31 | #include <linux/kdebug.h> |
| 32 | #include <linux/perf_counter.h> | ||
| 32 | 33 | ||
| 33 | #include <asm/firmware.h> | 34 | #include <asm/firmware.h> |
| 34 | #include <asm/page.h> | 35 | #include <asm/page.h> |
| @@ -170,6 +171,8 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address, | |||
| 170 | die("Weird page fault", regs, SIGSEGV); | 171 | die("Weird page fault", regs, SIGSEGV); |
| 171 | } | 172 | } |
| 172 | 173 | ||
| 174 | perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address); | ||
| 175 | |||
| 173 | /* When running in the kernel we expect faults to occur only to | 176 | /* When running in the kernel we expect faults to occur only to |
| 174 | * addresses in user space. All other faults represent errors in the | 177 | * addresses in user space. All other faults represent errors in the |
| 175 | * kernel and should generate an OOPS. Unfortunately, in the case of an | 178 | * kernel and should generate an OOPS. Unfortunately, in the case of an |
| @@ -299,7 +302,7 @@ good_area: | |||
| 299 | * the fault. | 302 | * the fault. |
| 300 | */ | 303 | */ |
| 301 | survive: | 304 | survive: |
| 302 | ret = handle_mm_fault(mm, vma, address, is_write); | 305 | ret = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0); |
| 303 | if (unlikely(ret & VM_FAULT_ERROR)) { | 306 | if (unlikely(ret & VM_FAULT_ERROR)) { |
| 304 | if (ret & VM_FAULT_OOM) | 307 | if (ret & VM_FAULT_OOM) |
| 305 | goto out_of_memory; | 308 | goto out_of_memory; |
| @@ -309,6 +312,8 @@ good_area: | |||
| 309 | } | 312 | } |
| 310 | if (ret & VM_FAULT_MAJOR) { | 313 | if (ret & VM_FAULT_MAJOR) { |
| 311 | current->maj_flt++; | 314 | current->maj_flt++; |
| 315 | perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, | ||
| 316 | regs, address); | ||
| 312 | #ifdef CONFIG_PPC_SMLPAR | 317 | #ifdef CONFIG_PPC_SMLPAR |
| 313 | if (firmware_has_feature(FW_FEATURE_CMO)) { | 318 | if (firmware_has_feature(FW_FEATURE_CMO)) { |
| 314 | preempt_disable(); | 319 | preempt_disable(); |
| @@ -316,8 +321,11 @@ good_area: | |||
| 316 | preempt_enable(); | 321 | preempt_enable(); |
| 317 | } | 322 | } |
| 318 | #endif | 323 | #endif |
| 319 | } else | 324 | } else { |
| 320 | current->min_flt++; | 325 | current->min_flt++; |
| 326 | perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, | ||
| 327 | regs, address); | ||
| 328 | } | ||
| 321 | up_read(&mm->mmap_sem); | 329 | up_read(&mm->mmap_sem); |
| 322 | return 0; | 330 | return 0; |
| 323 | 331 | ||
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index 34e5c0b219b9..056d23a1b105 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/cputable.h> | 27 | #include <asm/cputable.h> |
| 28 | #include <asm/udbg.h> | 28 | #include <asm/udbg.h> |
| 29 | #include <asm/kexec.h> | 29 | #include <asm/kexec.h> |
| 30 | #include <asm/ppc-opcode.h> | ||
| 30 | 31 | ||
| 31 | #ifdef DEBUG_LOW | 32 | #ifdef DEBUG_LOW |
| 32 | #define DBG_LOW(fmt...) udbg_printf(fmt) | 33 | #define DBG_LOW(fmt...) udbg_printf(fmt) |
| @@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) | |||
| 49 | case MMU_PAGE_4K: | 50 | case MMU_PAGE_4K: |
| 50 | va &= ~0xffful; | 51 | va &= ~0xffful; |
| 51 | va |= ssize << 8; | 52 | va |= ssize << 8; |
| 52 | asm volatile("tlbie %0,0" : : "r" (va) : "memory"); | 53 | asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), |
| 54 | %2) | ||
| 55 | : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206) | ||
| 56 | : "memory"); | ||
| 53 | break; | 57 | break; |
| 54 | default: | 58 | default: |
| 55 | penc = mmu_psize_defs[psize].penc; | 59 | penc = mmu_psize_defs[psize].penc; |
| 56 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | 60 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); |
| 57 | va |= penc << 12; | 61 | va |= penc << 12; |
| 58 | va |= ssize << 8; | 62 | va |= ssize << 8; |
| 59 | asm volatile("tlbie %0,1" : : "r" (va) : "memory"); | 63 | va |= 1; /* L */ |
| 64 | asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), | ||
| 65 | %2) | ||
| 66 | : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206) | ||
| 67 | : "memory"); | ||
| 60 | break; | 68 | break; |
| 61 | } | 69 | } |
| 62 | } | 70 | } |
| @@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize) | |||
| 80 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | 88 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); |
| 81 | va |= penc << 12; | 89 | va |= penc << 12; |
| 82 | va |= ssize << 8; | 90 | va |= ssize << 8; |
| 91 | va |= 1; /* L */ | ||
| 83 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" | 92 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
| 84 | : : "r"(va) : "memory"); | 93 | : : "r"(va) : "memory"); |
| 85 | break; | 94 | break; |
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c index 3e6a6543f53a..68a821add28d 100644 --- a/arch/powerpc/mm/init_64.c +++ b/arch/powerpc/mm/init_64.c | |||
| @@ -66,6 +66,7 @@ | |||
| 66 | 66 | ||
| 67 | #include "mmu_decl.h" | 67 | #include "mmu_decl.h" |
| 68 | 68 | ||
| 69 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
| 69 | #if PGTABLE_RANGE > USER_VSID_RANGE | 70 | #if PGTABLE_RANGE > USER_VSID_RANGE |
| 70 | #warning Limited user VSID range means pagetable space is wasted | 71 | #warning Limited user VSID range means pagetable space is wasted |
| 71 | #endif | 72 | #endif |
| @@ -73,6 +74,7 @@ | |||
| 73 | #if (TASK_SIZE_USER64 < PGTABLE_RANGE) && (TASK_SIZE_USER64 < USER_VSID_RANGE) | 74 | #if (TASK_SIZE_USER64 < PGTABLE_RANGE) && (TASK_SIZE_USER64 < USER_VSID_RANGE) |
| 74 | #warning TASK_SIZE is smaller than it needs to be. | 75 | #warning TASK_SIZE is smaller than it needs to be. |
| 75 | #endif | 76 | #endif |
| 77 | #endif /* CONFIG_PPC_STD_MMU_64 */ | ||
| 76 | 78 | ||
| 77 | phys_addr_t memstart_addr = ~0; | 79 | phys_addr_t memstart_addr = ~0; |
| 78 | phys_addr_t kernstart_addr; | 80 | phys_addr_t kernstart_addr; |
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c index 030d0005b4d2..8343986809c0 100644 --- a/arch/powerpc/mm/mmu_context_nohash.c +++ b/arch/powerpc/mm/mmu_context_nohash.c | |||
| @@ -46,7 +46,7 @@ static unsigned int next_context, nr_free_contexts; | |||
| 46 | static unsigned long *context_map; | 46 | static unsigned long *context_map; |
| 47 | static unsigned long *stale_map[NR_CPUS]; | 47 | static unsigned long *stale_map[NR_CPUS]; |
| 48 | static struct mm_struct **context_mm; | 48 | static struct mm_struct **context_mm; |
| 49 | static spinlock_t context_lock = SPIN_LOCK_UNLOCKED; | 49 | static DEFINE_SPINLOCK(context_lock); |
| 50 | 50 | ||
| 51 | #define CTX_MAP_SIZE \ | 51 | #define CTX_MAP_SIZE \ |
| 52 | (sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1)) | 52 | (sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1)) |
| @@ -73,7 +73,6 @@ static unsigned int steal_context_smp(unsigned int id) | |||
| 73 | struct mm_struct *mm; | 73 | struct mm_struct *mm; |
| 74 | unsigned int cpu, max; | 74 | unsigned int cpu, max; |
| 75 | 75 | ||
| 76 | again: | ||
| 77 | max = last_context - first_context; | 76 | max = last_context - first_context; |
| 78 | 77 | ||
| 79 | /* Attempt to free next_context first and then loop until we manage */ | 78 | /* Attempt to free next_context first and then loop until we manage */ |
| @@ -108,7 +107,9 @@ static unsigned int steal_context_smp(unsigned int id) | |||
| 108 | spin_unlock(&context_lock); | 107 | spin_unlock(&context_lock); |
| 109 | cpu_relax(); | 108 | cpu_relax(); |
| 110 | spin_lock(&context_lock); | 109 | spin_lock(&context_lock); |
| 111 | goto again; | 110 | |
| 111 | /* This will cause the caller to try again */ | ||
| 112 | return MMU_NO_CONTEXT; | ||
| 112 | } | 113 | } |
| 113 | #endif /* CONFIG_SMP */ | 114 | #endif /* CONFIG_SMP */ |
| 114 | 115 | ||
| @@ -194,6 +195,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) | |||
| 194 | WARN_ON(prev->context.active < 1); | 195 | WARN_ON(prev->context.active < 1); |
| 195 | prev->context.active--; | 196 | prev->context.active--; |
| 196 | } | 197 | } |
| 198 | |||
| 199 | again: | ||
| 197 | #endif /* CONFIG_SMP */ | 200 | #endif /* CONFIG_SMP */ |
| 198 | 201 | ||
| 199 | /* If we already have a valid assigned context, skip all that */ | 202 | /* If we already have a valid assigned context, skip all that */ |
| @@ -212,7 +215,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) | |||
| 212 | #ifdef CONFIG_SMP | 215 | #ifdef CONFIG_SMP |
| 213 | if (num_online_cpus() > 1) { | 216 | if (num_online_cpus() > 1) { |
| 214 | id = steal_context_smp(id); | 217 | id = steal_context_smp(id); |
| 215 | goto stolen; | 218 | if (id == MMU_NO_CONTEXT) |
| 219 | goto again; | ||
| 216 | } | 220 | } |
| 217 | #endif /* CONFIG_SMP */ | 221 | #endif /* CONFIG_SMP */ |
| 218 | id = steal_context_up(id); | 222 | id = steal_context_up(id); |
| @@ -272,6 +276,7 @@ int init_new_context(struct task_struct *t, struct mm_struct *mm) | |||
| 272 | */ | 276 | */ |
| 273 | void destroy_context(struct mm_struct *mm) | 277 | void destroy_context(struct mm_struct *mm) |
| 274 | { | 278 | { |
| 279 | unsigned long flags; | ||
| 275 | unsigned int id; | 280 | unsigned int id; |
| 276 | 281 | ||
| 277 | if (mm->context.id == MMU_NO_CONTEXT) | 282 | if (mm->context.id == MMU_NO_CONTEXT) |
| @@ -279,18 +284,18 @@ void destroy_context(struct mm_struct *mm) | |||
| 279 | 284 | ||
| 280 | WARN_ON(mm->context.active != 0); | 285 | WARN_ON(mm->context.active != 0); |
| 281 | 286 | ||
| 282 | spin_lock(&context_lock); | 287 | spin_lock_irqsave(&context_lock, flags); |
| 283 | id = mm->context.id; | 288 | id = mm->context.id; |
| 284 | if (id != MMU_NO_CONTEXT) { | 289 | if (id != MMU_NO_CONTEXT) { |
| 285 | __clear_bit(id, context_map); | 290 | __clear_bit(id, context_map); |
| 286 | mm->context.id = MMU_NO_CONTEXT; | 291 | mm->context.id = MMU_NO_CONTEXT; |
| 287 | #ifdef DEBUG_MAP_CONSISTENCY | 292 | #ifdef DEBUG_MAP_CONSISTENCY |
| 288 | mm->context.active = 0; | 293 | mm->context.active = 0; |
| 289 | context_mm[id] = NULL; | ||
| 290 | #endif | 294 | #endif |
| 295 | context_mm[id] = NULL; | ||
| 291 | nr_free_contexts++; | 296 | nr_free_contexts++; |
| 292 | } | 297 | } |
| 293 | spin_unlock(&context_lock); | 298 | spin_unlock_irqrestore(&context_lock, flags); |
| 294 | } | 299 | } |
| 295 | 300 | ||
| 296 | #ifdef CONFIG_SMP | 301 | #ifdef CONFIG_SMP |
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 9047145095aa..b037d95eeadc 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c | |||
| @@ -981,6 +981,8 @@ void __init do_init_bootmem(void) | |||
| 981 | mark_reserved_regions_for_nid(nid); | 981 | mark_reserved_regions_for_nid(nid); |
| 982 | sparse_memory_present_with_active_regions(nid); | 982 | sparse_memory_present_with_active_regions(nid); |
| 983 | } | 983 | } |
| 984 | |||
| 985 | init_bootmem_done = 1; | ||
| 984 | } | 986 | } |
| 985 | 987 | ||
| 986 | void __init paging_init(void) | 988 | void __init paging_init(void) |
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index 89497fb04280..3b52c80e5e33 100644 --- a/arch/powerpc/mm/slb.c +++ b/arch/powerpc/mm/slb.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * PowerPC64 SLB support. | 2 | * PowerPC64 SLB support. |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM | 4 | * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM |
| 5 | * Based on earlier code writteh by: | 5 | * Based on earlier code written by: |
| 6 | * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com | 6 | * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com |
| 7 | * Copyright (c) 2001 Dave Engebretsen | 7 | * Copyright (c) 2001 Dave Engebretsen |
| 8 | * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM | 8 | * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM |
diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile index 2ef6b0dddd8c..73e1c2ca0552 100644 --- a/arch/powerpc/oprofile/Makefile +++ b/arch/powerpc/oprofile/Makefile | |||
| @@ -1,3 +1,5 @@ | |||
| 1 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 2 | |||
| 1 | ifeq ($(CONFIG_PPC64),y) | 3 | ifeq ($(CONFIG_PPC64),y) |
| 2 | EXTRA_CFLAGS += -mno-minimal-toc | 4 | EXTRA_CFLAGS += -mno-minimal-toc |
| 3 | endif | 5 | endif |
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c index 91596f6ba1f4..62312abffa28 100644 --- a/arch/powerpc/oprofile/op_model_fsl_emb.c +++ b/arch/powerpc/oprofile/op_model_fsl_emb.c | |||
| @@ -228,20 +228,6 @@ static void pmc_stop_ctrs(void) | |||
| 228 | mtpmr(PMRN_PMGC0, pmgc0); | 228 | mtpmr(PMRN_PMGC0, pmgc0); |
| 229 | } | 229 | } |
| 230 | 230 | ||
| 231 | static void dump_pmcs(void) | ||
| 232 | { | ||
| 233 | printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0)); | ||
| 234 | printk("pmc\t\tpmlca\t\tpmlcb\n"); | ||
| 235 | printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0), | ||
| 236 | mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0)); | ||
| 237 | printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1), | ||
| 238 | mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1)); | ||
| 239 | printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2), | ||
| 240 | mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2)); | ||
| 241 | printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3), | ||
| 242 | mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3)); | ||
| 243 | } | ||
| 244 | |||
| 245 | static int fsl_emb_cpu_setup(struct op_counter_config *ctr) | 231 | static int fsl_emb_cpu_setup(struct op_counter_config *ctr) |
| 246 | { | 232 | { |
| 247 | int i; | 233 | int i; |
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig index f39c953d5353..a6e43cb6f825 100644 --- a/arch/powerpc/platforms/40x/Kconfig +++ b/arch/powerpc/platforms/40x/Kconfig | |||
| @@ -45,6 +45,7 @@ config KILAUEA | |||
| 45 | depends on 40x | 45 | depends on 40x |
| 46 | default n | 46 | default n |
| 47 | select 405EX | 47 | select 405EX |
| 48 | select PPC40x_SIMPLE | ||
| 48 | select PPC4xx_PCI_EXPRESS | 49 | select PPC4xx_PCI_EXPRESS |
| 49 | help | 50 | help |
| 50 | This option enables support for the AMCC PPC405EX evaluation board. | 51 | This option enables support for the AMCC PPC405EX evaluation board. |
| @@ -56,6 +57,7 @@ config MAKALU | |||
| 56 | select 405EX | 57 | select 405EX |
| 57 | select PCI | 58 | select PCI |
| 58 | select PPC4xx_PCI_EXPRESS | 59 | select PPC4xx_PCI_EXPRESS |
| 60 | select PPC40x_SIMPLE | ||
| 59 | help | 61 | help |
| 60 | This option enables support for the AMCC PPC405EX board. | 62 | This option enables support for the AMCC PPC405EX board. |
| 61 | 63 | ||
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile index 9bab76a652a6..56e89004c468 100644 --- a/arch/powerpc/platforms/40x/Makefile +++ b/arch/powerpc/platforms/40x/Makefile | |||
| @@ -1,6 +1,4 @@ | |||
| 1 | obj-$(CONFIG_KILAUEA) += kilauea.o | ||
| 2 | obj-$(CONFIG_HCU4) += hcu4.o | 1 | obj-$(CONFIG_HCU4) += hcu4.o |
| 3 | obj-$(CONFIG_MAKALU) += makalu.o | ||
| 4 | obj-$(CONFIG_WALNUT) += walnut.o | 2 | obj-$(CONFIG_WALNUT) += walnut.o |
| 5 | obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o | 3 | obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o |
| 6 | obj-$(CONFIG_EP405) += ep405.o | 4 | obj-$(CONFIG_EP405) += ep405.o |
diff --git a/arch/powerpc/platforms/40x/kilauea.c b/arch/powerpc/platforms/40x/kilauea.c deleted file mode 100644 index fd7d934dac8b..000000000000 --- a/arch/powerpc/platforms/40x/kilauea.c +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Kilauea board specific routines | ||
| 3 | * | ||
| 4 | * Copyright 2007-2008 DENX Software Engineering, Stefan Roese <sr@denx.de> | ||
| 5 | * | ||
| 6 | * Based on the Walnut code by | ||
| 7 | * Josh Boyer <jwboyer@linux.vnet.ibm.com> | ||
| 8 | * Copyright 2007 IBM Corporation | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | */ | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/of_platform.h> | ||
| 17 | #include <asm/machdep.h> | ||
| 18 | #include <asm/prom.h> | ||
| 19 | #include <asm/udbg.h> | ||
| 20 | #include <asm/time.h> | ||
| 21 | #include <asm/uic.h> | ||
| 22 | #include <asm/pci-bridge.h> | ||
| 23 | #include <asm/ppc4xx.h> | ||
| 24 | |||
| 25 | static __initdata struct of_device_id kilauea_of_bus[] = { | ||
| 26 | { .compatible = "ibm,plb4", }, | ||
| 27 | { .compatible = "ibm,opb", }, | ||
| 28 | { .compatible = "ibm,ebc", }, | ||
| 29 | {}, | ||
| 30 | }; | ||
| 31 | |||
| 32 | static int __init kilauea_device_probe(void) | ||
| 33 | { | ||
| 34 | of_platform_bus_probe(NULL, kilauea_of_bus, NULL); | ||
| 35 | |||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | machine_device_initcall(kilauea, kilauea_device_probe); | ||
| 39 | |||
| 40 | static int __init kilauea_probe(void) | ||
| 41 | { | ||
| 42 | unsigned long root = of_get_flat_dt_root(); | ||
| 43 | |||
| 44 | if (!of_flat_dt_is_compatible(root, "amcc,kilauea")) | ||
| 45 | return 0; | ||
| 46 | |||
| 47 | ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); | ||
| 48 | |||
| 49 | return 1; | ||
| 50 | } | ||
| 51 | |||
| 52 | define_machine(kilauea) { | ||
| 53 | .name = "Kilauea", | ||
| 54 | .probe = kilauea_probe, | ||
| 55 | .progress = udbg_progress, | ||
| 56 | .init_IRQ = uic_init_tree, | ||
| 57 | .get_irq = uic_get_irq, | ||
| 58 | .restart = ppc4xx_reset_system, | ||
| 59 | .calibrate_decr = generic_calibrate_decr, | ||
| 60 | }; | ||
diff --git a/arch/powerpc/platforms/40x/makalu.c b/arch/powerpc/platforms/40x/makalu.c deleted file mode 100644 index a6a1d6017b71..000000000000 --- a/arch/powerpc/platforms/40x/makalu.c +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Makalu board specific routines | ||
| 3 | * | ||
| 4 | * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> | ||
| 5 | * | ||
| 6 | * Based on the Walnut code by | ||
| 7 | * Josh Boyer <jwboyer@linux.vnet.ibm.com> | ||
| 8 | * Copyright 2007 IBM Corporation | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | */ | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/of_platform.h> | ||
| 17 | #include <asm/machdep.h> | ||
| 18 | #include <asm/prom.h> | ||
| 19 | #include <asm/udbg.h> | ||
| 20 | #include <asm/time.h> | ||
| 21 | #include <asm/uic.h> | ||
| 22 | #include <asm/pci-bridge.h> | ||
| 23 | #include <asm/ppc4xx.h> | ||
| 24 | |||
| 25 | static __initdata struct of_device_id makalu_of_bus[] = { | ||
| 26 | { .compatible = "ibm,plb4", }, | ||
| 27 | { .compatible = "ibm,opb", }, | ||
| 28 | { .compatible = "ibm,ebc", }, | ||
| 29 | {}, | ||
| 30 | }; | ||
| 31 | |||
| 32 | static int __init makalu_device_probe(void) | ||
| 33 | { | ||
| 34 | of_platform_bus_probe(NULL, makalu_of_bus, NULL); | ||
| 35 | |||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | machine_device_initcall(makalu, makalu_device_probe); | ||
| 39 | |||
| 40 | static int __init makalu_probe(void) | ||
| 41 | { | ||
| 42 | unsigned long root = of_get_flat_dt_root(); | ||
| 43 | |||
| 44 | if (!of_flat_dt_is_compatible(root, "amcc,makalu")) | ||
| 45 | return 0; | ||
| 46 | |||
| 47 | ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC; | ||
| 48 | |||
| 49 | return 1; | ||
| 50 | } | ||
| 51 | |||
| 52 | define_machine(makalu) { | ||
| 53 | .name = "Makalu", | ||
| 54 | .probe = makalu_probe, | ||
| 55 | .progress = udbg_progress, | ||
| 56 | .init_IRQ = uic_init_tree, | ||
| 57 | .get_irq = uic_get_irq, | ||
| 58 | .restart = ppc4xx_reset_system, | ||
| 59 | .calibrate_decr = generic_calibrate_decr, | ||
| 60 | }; | ||
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c index f40ac9b8f99f..5fd5a5974001 100644 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c | |||
| @@ -51,7 +51,10 @@ machine_device_initcall(ppc40x_simple, ppc40x_device_probe); | |||
| 51 | * board.c file for it rather than adding it to this list. | 51 | * board.c file for it rather than adding it to this list. |
| 52 | */ | 52 | */ |
| 53 | static char *board[] __initdata = { | 53 | static char *board[] __initdata = { |
| 54 | "amcc,acadia" | 54 | "amcc,acadia", |
| 55 | "amcc,haleakala", | ||
| 56 | "amcc,kilauea", | ||
| 57 | "amcc,makalu" | ||
| 55 | }; | 58 | }; |
| 56 | 59 | ||
| 57 | static int __init ppc40x_probe(void) | 60 | static int __init ppc40x_probe(void) |
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c index fc7fb001276c..d0fc6866b00c 100644 --- a/arch/powerpc/platforms/40x/virtex.c +++ b/arch/powerpc/platforms/40x/virtex.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <asm/prom.h> | 14 | #include <asm/prom.h> |
| 15 | #include <asm/time.h> | 15 | #include <asm/time.h> |
| 16 | #include <asm/xilinx_intc.h> | 16 | #include <asm/xilinx_intc.h> |
| 17 | #include <asm/xilinx_pci.h> | ||
| 17 | #include <asm/ppc4xx.h> | 18 | #include <asm/ppc4xx.h> |
| 18 | 19 | ||
| 19 | static struct of_device_id xilinx_of_bus_ids[] __initdata = { | 20 | static struct of_device_id xilinx_of_bus_ids[] __initdata = { |
| @@ -47,6 +48,7 @@ static int __init virtex_probe(void) | |||
| 47 | define_machine(virtex) { | 48 | define_machine(virtex) { |
| 48 | .name = "Xilinx Virtex", | 49 | .name = "Xilinx Virtex", |
| 49 | .probe = virtex_probe, | 50 | .probe = virtex_probe, |
| 51 | .setup_arch = xilinx_pci_init, | ||
| 50 | .init_IRQ = xilinx_intc_init_tree, | 52 | .init_IRQ = xilinx_intc_init_tree, |
| 51 | .get_irq = xilinx_intc_get_irq, | 53 | .get_irq = xilinx_intc_get_irq, |
| 52 | .restart = ppc4xx_reset_system, | 54 | .restart = ppc4xx_reset_system, |
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index 0d83a6a0397d..90e3192611a4 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig | |||
| @@ -156,7 +156,7 @@ config YOSEMITE | |||
| 156 | # This option enables support for the IBM PPC440GX evaluation board. | 156 | # This option enables support for the IBM PPC440GX evaluation board. |
| 157 | 157 | ||
| 158 | config XILINX_VIRTEX440_GENERIC_BOARD | 158 | config XILINX_VIRTEX440_GENERIC_BOARD |
| 159 | bool "Generic Xilinx Virtex 440 board" | 159 | bool "Generic Xilinx Virtex 5 FXT board support" |
| 160 | depends on 44x | 160 | depends on 44x |
| 161 | default n | 161 | default n |
| 162 | select XILINX_VIRTEX_5_FXT | 162 | select XILINX_VIRTEX_5_FXT |
| @@ -171,6 +171,17 @@ config XILINX_VIRTEX440_GENERIC_BOARD | |||
| 171 | Most Virtex 5 designs should use this unless it needs to do some | 171 | Most Virtex 5 designs should use this unless it needs to do some |
| 172 | special configuration at board probe time. | 172 | special configuration at board probe time. |
| 173 | 173 | ||
| 174 | config XILINX_ML510 | ||
| 175 | bool "Xilinx ML510 extra support" | ||
| 176 | depends on XILINX_VIRTEX440_GENERIC_BOARD | ||
| 177 | select PPC_PCI_CHOICE | ||
| 178 | select XILINX_PCI if PCI | ||
| 179 | select PPC_INDIRECT_PCI if PCI | ||
| 180 | select PPC_I8259 if PCI | ||
| 181 | help | ||
| 182 | This option enables extra support for features on the Xilinx ML510 | ||
| 183 | board. The ML510 has a PCI bus with ALI south bridge. | ||
| 184 | |||
| 174 | config PPC44x_SIMPLE | 185 | config PPC44x_SIMPLE |
| 175 | bool "Simple PowerPC 44x board support" | 186 | bool "Simple PowerPC 44x board support" |
| 176 | depends on 44x | 187 | depends on 44x |
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile index 01f51daace13..ee6185aeaa3b 100644 --- a/arch/powerpc/platforms/44x/Makefile +++ b/arch/powerpc/platforms/44x/Makefile | |||
| @@ -4,3 +4,4 @@ obj-$(CONFIG_EBONY) += ebony.o | |||
| 4 | obj-$(CONFIG_SAM440EP) += sam440ep.o | 4 | obj-$(CONFIG_SAM440EP) += sam440ep.o |
| 5 | obj-$(CONFIG_WARP) += warp.o | 5 | obj-$(CONFIG_WARP) += warp.o |
| 6 | obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o | 6 | obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o |
| 7 | obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o | ||
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c index 68637faf70ae..cf96ccaa760c 100644 --- a/arch/powerpc/platforms/44x/virtex.c +++ b/arch/powerpc/platforms/44x/virtex.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <asm/prom.h> | 16 | #include <asm/prom.h> |
| 17 | #include <asm/time.h> | 17 | #include <asm/time.h> |
| 18 | #include <asm/xilinx_intc.h> | 18 | #include <asm/xilinx_intc.h> |
| 19 | #include <asm/xilinx_pci.h> | ||
| 19 | #include <asm/reg.h> | 20 | #include <asm/reg.h> |
| 20 | #include <asm/ppc4xx.h> | 21 | #include <asm/ppc4xx.h> |
| 21 | #include "44x.h" | 22 | #include "44x.h" |
| @@ -53,6 +54,7 @@ static int __init virtex_probe(void) | |||
| 53 | define_machine(virtex) { | 54 | define_machine(virtex) { |
| 54 | .name = "Xilinx Virtex440", | 55 | .name = "Xilinx Virtex440", |
| 55 | .probe = virtex_probe, | 56 | .probe = virtex_probe, |
| 57 | .setup_arch = xilinx_pci_init, | ||
| 56 | .init_IRQ = xilinx_intc_init_tree, | 58 | .init_IRQ = xilinx_intc_init_tree, |
| 57 | .get_irq = xilinx_intc_get_irq, | 59 | .get_irq = xilinx_intc_get_irq, |
| 58 | .calibrate_decr = generic_calibrate_decr, | 60 | .calibrate_decr = generic_calibrate_decr, |
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c new file mode 100644 index 000000000000..ba4a6e388a46 --- /dev/null +++ b/arch/powerpc/platforms/44x/virtex_ml510.c | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #include <asm/i8259.h> | ||
| 2 | #include <linux/pci.h> | ||
| 3 | #include "44x.h" | ||
| 4 | |||
| 5 | /** | ||
| 6 | * ml510_ail_quirk | ||
| 7 | */ | ||
| 8 | static void __devinit ml510_ali_quirk(struct pci_dev *dev) | ||
| 9 | { | ||
| 10 | /* Enable the IDE controller */ | ||
| 11 | pci_write_config_byte(dev, 0x58, 0x4c); | ||
| 12 | /* Assign irq 14 to the primary ide channel */ | ||
| 13 | pci_write_config_byte(dev, 0x44, 0x0d); | ||
| 14 | /* Assign irq 15 to the secondary ide channel */ | ||
| 15 | pci_write_config_byte(dev, 0x75, 0x0f); | ||
| 16 | /* Set the ide controller in native mode */ | ||
| 17 | pci_write_config_byte(dev, 0x09, 0xff); | ||
| 18 | |||
| 19 | /* INTB = disabled, INTA = disabled */ | ||
| 20 | pci_write_config_byte(dev, 0x48, 0x00); | ||
| 21 | /* INTD = disabled, INTC = disabled */ | ||
| 22 | pci_write_config_byte(dev, 0x4a, 0x00); | ||
| 23 | /* Audio = INT7, Modem = disabled. */ | ||
| 24 | pci_write_config_byte(dev, 0x4b, 0x60); | ||
| 25 | /* USB = INT7 */ | ||
| 26 | pci_write_config_byte(dev, 0x74, 0x06); | ||
| 27 | } | ||
| 28 | DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk); | ||
| 29 | |||
diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c index 960edf89be51..42e09a9f77e2 100644 --- a/arch/powerpc/platforms/44x/warp.c +++ b/arch/powerpc/platforms/44x/warp.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * PIKA Warp(tm) board specific routines | 2 | * PIKA Warp(tm) board specific routines |
| 3 | * | 3 | * |
| 4 | * Copyright (c) 2008 PIKA Technologies | 4 | * Copyright (c) 2008-2009 PIKA Technologies |
| 5 | * Sean MacLennan <smaclennan@pikatech.com> | 5 | * Sean MacLennan <smaclennan@pikatech.com> |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/i2c.h> | 15 | #include <linux/i2c.h> |
| 16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
| 18 | #include <linux/of_gpio.h> | ||
| 18 | 19 | ||
| 19 | #include <asm/machdep.h> | 20 | #include <asm/machdep.h> |
| 20 | #include <asm/prom.h> | 21 | #include <asm/prom.h> |
| @@ -23,6 +24,7 @@ | |||
| 23 | #include <asm/uic.h> | 24 | #include <asm/uic.h> |
| 24 | #include <asm/ppc4xx.h> | 25 | #include <asm/ppc4xx.h> |
| 25 | 26 | ||
| 27 | |||
| 26 | static __initdata struct of_device_id warp_of_bus[] = { | 28 | static __initdata struct of_device_id warp_of_bus[] = { |
| 27 | { .compatible = "ibm,plb4", }, | 29 | { .compatible = "ibm,plb4", }, |
| 28 | { .compatible = "ibm,opb", }, | 30 | { .compatible = "ibm,opb", }, |
| @@ -41,7 +43,13 @@ static int __init warp_probe(void) | |||
| 41 | { | 43 | { |
| 42 | unsigned long root = of_get_flat_dt_root(); | 44 | unsigned long root = of_get_flat_dt_root(); |
| 43 | 45 | ||
| 44 | return of_flat_dt_is_compatible(root, "pika,warp"); | 46 | if (!of_flat_dt_is_compatible(root, "pika,warp")) |
| 47 | return 0; | ||
| 48 | |||
| 49 | /* For __dma_alloc_coherent */ | ||
| 50 | ISA_DMA_THRESHOLD = ~0L; | ||
| 51 | |||
| 52 | return 1; | ||
| 45 | } | 53 | } |
| 46 | 54 | ||
| 47 | define_machine(warp) { | 55 | define_machine(warp) { |
| @@ -55,6 +63,8 @@ define_machine(warp) { | |||
| 55 | }; | 63 | }; |
| 56 | 64 | ||
| 57 | 65 | ||
| 66 | static u32 post_info; | ||
| 67 | |||
| 58 | /* I am not sure this is the best place for this... */ | 68 | /* I am not sure this is the best place for this... */ |
| 59 | static int __init warp_post_info(void) | 69 | static int __init warp_post_info(void) |
| 60 | { | 70 | { |
| @@ -77,21 +87,21 @@ static int __init warp_post_info(void) | |||
| 77 | 87 | ||
| 78 | iounmap(fpga); | 88 | iounmap(fpga); |
| 79 | 89 | ||
| 80 | if (post1 || post2) | 90 | if (post1 || post2) { |
| 81 | printk(KERN_INFO "Warp POST %08x %08x\n", post1, post2); | 91 | printk(KERN_INFO "Warp POST %08x %08x\n", post1, post2); |
| 82 | else | 92 | post_info = 1; |
| 93 | } else | ||
| 83 | printk(KERN_INFO "Warp POST OK\n"); | 94 | printk(KERN_INFO "Warp POST OK\n"); |
| 84 | 95 | ||
| 85 | return 0; | 96 | return 0; |
| 86 | } | 97 | } |
| 87 | machine_late_initcall(warp, warp_post_info); | ||
| 88 | 98 | ||
| 89 | 99 | ||
| 90 | #ifdef CONFIG_SENSORS_AD7414 | 100 | #ifdef CONFIG_SENSORS_AD7414 |
| 91 | 101 | ||
| 92 | static LIST_HEAD(dtm_shutdown_list); | 102 | static LIST_HEAD(dtm_shutdown_list); |
| 93 | static void __iomem *dtm_fpga; | 103 | static void __iomem *dtm_fpga; |
| 94 | static void __iomem *gpio_base; | 104 | static unsigned green_led, red_led; |
| 95 | 105 | ||
| 96 | 106 | ||
| 97 | struct dtm_shutdown { | 107 | struct dtm_shutdown { |
| @@ -134,14 +144,17 @@ int pika_dtm_unregister_shutdown(void (*func)(void *arg), void *arg) | |||
| 134 | static irqreturn_t temp_isr(int irq, void *context) | 144 | static irqreturn_t temp_isr(int irq, void *context) |
| 135 | { | 145 | { |
| 136 | struct dtm_shutdown *shutdown; | 146 | struct dtm_shutdown *shutdown; |
| 147 | int value = 1; | ||
| 137 | 148 | ||
| 138 | local_irq_disable(); | 149 | local_irq_disable(); |
| 139 | 150 | ||
| 151 | gpio_set_value(green_led, 0); | ||
| 152 | |||
| 140 | /* Run through the shutdown list. */ | 153 | /* Run through the shutdown list. */ |
| 141 | list_for_each_entry(shutdown, &dtm_shutdown_list, list) | 154 | list_for_each_entry(shutdown, &dtm_shutdown_list, list) |
| 142 | shutdown->func(shutdown->arg); | 155 | shutdown->func(shutdown->arg); |
| 143 | 156 | ||
| 144 | printk(KERN_EMERG "\n\nCritical Temperature Shutdown\n"); | 157 | printk(KERN_EMERG "\n\nCritical Temperature Shutdown\n\n"); |
| 145 | 158 | ||
| 146 | while (1) { | 159 | while (1) { |
| 147 | if (dtm_fpga) { | 160 | if (dtm_fpga) { |
| @@ -149,52 +162,34 @@ static irqreturn_t temp_isr(int irq, void *context) | |||
| 149 | out_be32(dtm_fpga + 0x14, reset); | 162 | out_be32(dtm_fpga + 0x14, reset); |
| 150 | } | 163 | } |
| 151 | 164 | ||
| 152 | if (gpio_base) { | 165 | gpio_set_value(red_led, value); |
| 153 | unsigned leds = in_be32(gpio_base); | 166 | value ^= 1; |
| 154 | |||
| 155 | /* green off, red toggle */ | ||
| 156 | leds &= ~0x80000000; | ||
| 157 | leds ^= 0x40000000; | ||
| 158 | |||
| 159 | out_be32(gpio_base, leds); | ||
| 160 | } | ||
| 161 | |||
| 162 | mdelay(500); | 167 | mdelay(500); |
| 163 | } | 168 | } |
| 164 | } | 169 | } |
| 165 | 170 | ||
| 166 | static int pika_setup_leds(void) | 171 | static int pika_setup_leds(void) |
| 167 | { | 172 | { |
| 168 | struct device_node *np; | 173 | struct device_node *np, *child; |
| 169 | const u32 *gpios; | ||
| 170 | int len; | ||
| 171 | 174 | ||
| 172 | np = of_find_compatible_node(NULL, NULL, "linux,gpio-led"); | 175 | np = of_find_compatible_node(NULL, NULL, "gpio-leds"); |
| 173 | if (!np) { | 176 | if (!np) { |
| 174 | printk(KERN_ERR __FILE__ ": Unable to find gpio-led\n"); | 177 | printk(KERN_ERR __FILE__ ": Unable to find leds\n"); |
| 175 | return -ENOENT; | 178 | return -ENOENT; |
| 176 | } | 179 | } |
| 177 | 180 | ||
| 178 | gpios = of_get_property(np, "gpios", &len); | 181 | for_each_child_of_node(np, child) |
| 179 | of_node_put(np); | 182 | if (strcmp(child->name, "green") == 0) { |
| 180 | if (!gpios || len < 4) { | 183 | green_led = of_get_gpio(child, 0); |
| 181 | printk(KERN_ERR __FILE__ | 184 | /* Turn back on the green LED */ |
| 182 | ": Unable to get gpios property (%d)\n", len); | 185 | gpio_set_value(green_led, 1); |
| 183 | return -ENOENT; | 186 | } else if (strcmp(child->name, "red") == 0) { |
| 184 | } | 187 | red_led = of_get_gpio(child, 0); |
| 185 | 188 | /* Set based on post */ | |
| 186 | np = of_find_node_by_phandle(gpios[0]); | 189 | gpio_set_value(red_led, post_info); |
| 187 | if (!np) { | 190 | } |
| 188 | printk(KERN_ERR __FILE__ ": Unable to find gpio\n"); | ||
| 189 | return -ENOENT; | ||
| 190 | } | ||
| 191 | 191 | ||
| 192 | gpio_base = of_iomap(np, 0); | ||
| 193 | of_node_put(np); | 192 | of_node_put(np); |
| 194 | if (!gpio_base) { | ||
| 195 | printk(KERN_ERR __FILE__ ": Unable to map gpio"); | ||
| 196 | return -ENOMEM; | ||
| 197 | } | ||
| 198 | 193 | ||
| 199 | return 0; | 194 | return 0; |
| 200 | } | 195 | } |
| @@ -270,10 +265,10 @@ static int pika_dtm_thread(void __iomem *fpga) | |||
| 270 | } | 265 | } |
| 271 | 266 | ||
| 272 | found_it: | 267 | found_it: |
| 273 | i2c_put_adapter(adap); | ||
| 274 | |||
| 275 | pika_setup_critical_temp(client); | 268 | pika_setup_critical_temp(client); |
| 276 | 269 | ||
| 270 | i2c_put_adapter(adap); | ||
| 271 | |||
| 277 | printk(KERN_INFO "PIKA DTM thread running.\n"); | 272 | printk(KERN_INFO "PIKA DTM thread running.\n"); |
| 278 | 273 | ||
| 279 | while (!kthread_should_stop()) { | 274 | while (!kthread_should_stop()) { |
| @@ -311,6 +306,9 @@ static int __init pika_dtm_start(void) | |||
| 311 | if (dtm_fpga == NULL) | 306 | if (dtm_fpga == NULL) |
| 312 | return -ENOENT; | 307 | return -ENOENT; |
| 313 | 308 | ||
| 309 | /* Must get post info before thread starts. */ | ||
| 310 | warp_post_info(); | ||
| 311 | |||
| 314 | dtm_thread = kthread_run(pika_dtm_thread, dtm_fpga, "pika-dtm"); | 312 | dtm_thread = kthread_run(pika_dtm_thread, dtm_fpga, "pika-dtm"); |
| 315 | if (IS_ERR(dtm_thread)) { | 313 | if (IS_ERR(dtm_thread)) { |
| 316 | iounmap(dtm_fpga); | 314 | iounmap(dtm_fpga); |
| @@ -333,6 +331,8 @@ int pika_dtm_unregister_shutdown(void (*func)(void *arg), void *arg) | |||
| 333 | return 0; | 331 | return 0; |
| 334 | } | 332 | } |
| 335 | 333 | ||
| 334 | machine_late_initcall(warp, warp_post_info); | ||
| 335 | |||
| 336 | #endif | 336 | #endif |
| 337 | 337 | ||
| 338 | EXPORT_SYMBOL(pika_dtm_register_shutdown); | 338 | EXPORT_SYMBOL(pika_dtm_register_shutdown); |
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c index 1bcff94eb924..84544d072043 100644 --- a/arch/powerpc/platforms/512x/clock.c +++ b/arch/powerpc/platforms/512x/clock.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 25 | 25 | ||
| 26 | #include <linux/of_platform.h> | 26 | #include <linux/of_platform.h> |
| 27 | #include <asm/mpc512x.h> | 27 | #include <asm/mpc5xxx.h> |
| 28 | #include <asm/clk_interface.h> | 28 | #include <asm/clk_interface.h> |
| 29 | 29 | ||
| 30 | #undef CLK_DEBUG | 30 | #undef CLK_DEBUG |
| @@ -83,13 +83,13 @@ static void dump_clocks(void) | |||
| 83 | mutex_lock(&clocks_mutex); | 83 | mutex_lock(&clocks_mutex); |
| 84 | printk(KERN_INFO "CLOCKS:\n"); | 84 | printk(KERN_INFO "CLOCKS:\n"); |
| 85 | list_for_each_entry(p, &clocks, node) { | 85 | list_for_each_entry(p, &clocks, node) { |
| 86 | printk(KERN_INFO " %s %ld", p->name, p->rate); | 86 | pr_info(" %s=%ld", p->name, p->rate); |
| 87 | if (p->parent) | 87 | if (p->parent) |
| 88 | printk(KERN_INFO " %s %ld", p->parent->name, | 88 | pr_cont(" %s=%ld", p->parent->name, |
| 89 | p->parent->rate); | 89 | p->parent->rate); |
| 90 | if (p->flags & CLK_HAS_CTRL) | 90 | if (p->flags & CLK_HAS_CTRL) |
| 91 | printk(KERN_INFO " reg/bit %d/%d", p->reg, p->bit); | 91 | pr_cont(" reg/bit=%d/%d", p->reg, p->bit); |
| 92 | printk("\n"); | 92 | pr_cont("\n"); |
| 93 | } | 93 | } |
| 94 | mutex_unlock(&clocks_mutex); | 94 | mutex_unlock(&clocks_mutex); |
| 95 | } | 95 | } |
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h index 9c03693cb009..22a5352407e0 100644 --- a/arch/powerpc/platforms/512x/mpc512x.h +++ b/arch/powerpc/platforms/512x/mpc512x.h | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | 11 | ||
| 12 | #ifndef __MPC512X_H__ | 12 | #ifndef __MPC512X_H__ |
| 13 | #define __MPC512X_H__ | 13 | #define __MPC512X_H__ |
| 14 | extern unsigned long mpc512x_find_ips_freq(struct device_node *node); | ||
| 15 | extern void __init mpc512x_init_IRQ(void); | 14 | extern void __init mpc512x_init_IRQ(void); |
| 16 | void __init mpc512x_declare_of_platform_devices(void); | 15 | void __init mpc512x_declare_of_platform_devices(void); |
| 17 | #endif /* __MPC512X_H__ */ | 16 | #endif /* __MPC512X_H__ */ |
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c index d8cd579f3191..434d683df5a0 100644 --- a/arch/powerpc/platforms/512x/mpc512x_shared.c +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c | |||
| @@ -24,29 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include "mpc512x.h" | 25 | #include "mpc512x.h" |
| 26 | 26 | ||
| 27 | unsigned long | ||
| 28 | mpc512x_find_ips_freq(struct device_node *node) | ||
| 29 | { | ||
| 30 | struct device_node *np; | ||
| 31 | const unsigned int *p_ips_freq = NULL; | ||
| 32 | |||
| 33 | of_node_get(node); | ||
| 34 | while (node) { | ||
| 35 | p_ips_freq = of_get_property(node, "bus-frequency", NULL); | ||
| 36 | if (p_ips_freq) | ||
| 37 | break; | ||
| 38 | |||
| 39 | np = of_get_parent(node); | ||
| 40 | of_node_put(node); | ||
| 41 | node = np; | ||
| 42 | } | ||
| 43 | if (node) | ||
| 44 | of_node_put(node); | ||
| 45 | |||
| 46 | return p_ips_freq ? *p_ips_freq : 0; | ||
| 47 | } | ||
| 48 | EXPORT_SYMBOL(mpc512x_find_ips_freq); | ||
| 49 | |||
| 50 | void __init mpc512x_init_IRQ(void) | 27 | void __init mpc512x_init_IRQ(void) |
| 51 | { | 28 | { |
| 52 | struct device_node *np; | 29 | struct device_node *np; |
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c index a2068faef6ea..bcc69e1f77c1 100644 --- a/arch/powerpc/platforms/52xx/efika.c +++ b/arch/powerpc/platforms/52xx/efika.c | |||
| @@ -34,7 +34,7 @@ | |||
| 34 | static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | 34 | static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 35 | int len, u32 * val) | 35 | int len, u32 * val) |
| 36 | { | 36 | { |
| 37 | struct pci_controller *hose = bus->sysdata; | 37 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 38 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | 38 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 39 | | (((bus->number - hose->first_busno) & 0xff) << 16) | 39 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 40 | | (hose->global_number << 24); | 40 | | (hose->global_number << 24); |
| @@ -49,7 +49,7 @@ static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |||
| 49 | static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, | 49 | static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, |
| 50 | int offset, int len, u32 val) | 50 | int offset, int len, u32 val) |
| 51 | { | 51 | { |
| 52 | struct pci_controller *hose = bus->sysdata; | 52 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 53 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | 53 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 54 | | (((bus->number - hose->first_busno) & 0xff) << 16) | 54 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 55 | | (hose->global_number << 24); | 55 | | (hose->global_number << 24); |
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c index 8e3dd5a0f228..a46bad0c2339 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c | |||
| @@ -47,36 +47,6 @@ static DEFINE_SPINLOCK(mpc52xx_lock); | |||
| 47 | static struct mpc52xx_gpt __iomem *mpc52xx_wdt; | 47 | static struct mpc52xx_gpt __iomem *mpc52xx_wdt; |
| 48 | static struct mpc52xx_cdm __iomem *mpc52xx_cdm; | 48 | static struct mpc52xx_cdm __iomem *mpc52xx_cdm; |
| 49 | 49 | ||
| 50 | /** | ||
| 51 | * mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device | ||
| 52 | * @node: device node | ||
| 53 | * | ||
| 54 | * Returns IPB bus frequency, or 0 if the bus frequency cannot be found. | ||
| 55 | */ | ||
| 56 | unsigned int | ||
| 57 | mpc52xx_find_ipb_freq(struct device_node *node) | ||
| 58 | { | ||
| 59 | struct device_node *np; | ||
| 60 | const unsigned int *p_ipb_freq = NULL; | ||
| 61 | |||
| 62 | of_node_get(node); | ||
| 63 | while (node) { | ||
| 64 | p_ipb_freq = of_get_property(node, "bus-frequency", NULL); | ||
| 65 | if (p_ipb_freq) | ||
| 66 | break; | ||
| 67 | |||
| 68 | np = of_get_parent(node); | ||
| 69 | of_node_put(node); | ||
| 70 | node = np; | ||
| 71 | } | ||
| 72 | if (node) | ||
| 73 | of_node_put(node); | ||
| 74 | |||
| 75 | return p_ipb_freq ? *p_ipb_freq : 0; | ||
| 76 | } | ||
| 77 | EXPORT_SYMBOL(mpc52xx_find_ipb_freq); | ||
| 78 | |||
| 79 | |||
| 80 | /* | 50 | /* |
| 81 | * Configure the XLB arbiter settings to match what Linux expects. | 51 | * Configure the XLB arbiter settings to match what Linux expects. |
| 82 | */ | 52 | */ |
| @@ -221,7 +191,7 @@ unsigned int mpc52xx_get_xtal_freq(struct device_node *node) | |||
| 221 | if (!mpc52xx_cdm) | 191 | if (!mpc52xx_cdm) |
| 222 | return 0; | 192 | return 0; |
| 223 | 193 | ||
| 224 | freq = mpc52xx_find_ipb_freq(node); | 194 | freq = mpc5xxx_get_bus_frequency(node); |
| 225 | if (!freq) | 195 | if (!freq) |
| 226 | return 0; | 196 | return 0; |
| 227 | 197 | ||
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c index 87ff522f28b5..dd43114e9684 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c | |||
| @@ -107,7 +107,7 @@ static int | |||
| 107 | mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, | 107 | mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
| 108 | int offset, int len, u32 *val) | 108 | int offset, int len, u32 *val) |
| 109 | { | 109 | { |
| 110 | struct pci_controller *hose = bus->sysdata; | 110 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 111 | u32 value; | 111 | u32 value; |
| 112 | 112 | ||
| 113 | if (ppc_md.pci_exclude_device) | 113 | if (ppc_md.pci_exclude_device) |
| @@ -164,7 +164,7 @@ static int | |||
| 164 | mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, | 164 | mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
| 165 | int offset, int len, u32 val) | 165 | int offset, int len, u32 val) |
| 166 | { | 166 | { |
| 167 | struct pci_controller *hose = bus->sysdata; | 167 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 168 | u32 value, mask; | 168 | u32 value, mask; |
| 169 | 169 | ||
| 170 | if (ppc_md.pci_exclude_device) | 170 | if (ppc_md.pci_exclude_device) |
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c index 0eb6d7f62241..51fcae41f08a 100644 --- a/arch/powerpc/platforms/82xx/ep8248e.c +++ b/arch/powerpc/platforms/82xx/ep8248e.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/fsl_devices.h> | 15 | #include <linux/fsl_devices.h> |
| 16 | #include <linux/mdio-bitbang.h> | 16 | #include <linux/mdio-bitbang.h> |
| 17 | #include <linux/of_mdio.h> | ||
| 17 | #include <linux/of_platform.h> | 18 | #include <linux/of_platform.h> |
| 18 | 19 | ||
| 19 | #include <asm/io.h> | 20 | #include <asm/io.h> |
| @@ -115,7 +116,7 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, | |||
| 115 | struct mii_bus *bus; | 116 | struct mii_bus *bus; |
| 116 | struct resource res; | 117 | struct resource res; |
| 117 | struct device_node *node; | 118 | struct device_node *node; |
| 118 | int ret, i; | 119 | int ret; |
| 119 | 120 | ||
| 120 | node = of_get_parent(ofdev->node); | 121 | node = of_get_parent(ofdev->node); |
| 121 | of_node_put(node); | 122 | of_node_put(node); |
| @@ -130,17 +131,13 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, | |||
| 130 | if (!bus) | 131 | if (!bus) |
| 131 | return -ENOMEM; | 132 | return -ENOMEM; |
| 132 | 133 | ||
| 133 | bus->phy_mask = 0; | ||
| 134 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | 134 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); |
| 135 | 135 | ||
| 136 | for (i = 0; i < PHY_MAX_ADDR; i++) | ||
| 137 | bus->irq[i] = -1; | ||
| 138 | |||
| 139 | bus->name = "ep8248e-mdio-bitbang"; | 136 | bus->name = "ep8248e-mdio-bitbang"; |
| 140 | bus->parent = &ofdev->dev; | 137 | bus->parent = &ofdev->dev; |
| 141 | snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); | 138 | snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); |
| 142 | 139 | ||
| 143 | return mdiobus_register(bus); | 140 | return of_mdiobus_register(bus, ofdev->node); |
| 144 | } | 141 | } |
| 145 | 142 | ||
| 146 | static int ep8248e_mdio_remove(struct of_device *ofdev) | 143 | static int ep8248e_mdio_remove(struct of_device *ofdev) |
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h b/arch/powerpc/platforms/82xx/pq2ads.h index 984db42cc8e7..6cf0f97486e2 100644 --- a/arch/powerpc/platforms/82xx/pq2ads.h +++ b/arch/powerpc/platforms/82xx/pq2ads.h | |||
| @@ -24,10 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <linux/seq_file.h> | 25 | #include <linux/seq_file.h> |
| 26 | 26 | ||
| 27 | /* Backword-compatibility stuff for the drivers */ | ||
| 28 | #define CPM_MAP_ADDR ((uint)0xf0000000) | ||
| 29 | #define CPM_IRQ_OFFSET 0 | ||
| 30 | |||
| 31 | /* The ADS8260 has 16, 32-bit wide control/status registers, accessed | 27 | /* The ADS8260 has 16, 32-bit wide control/status registers, accessed |
| 32 | * only on word boundaries. | 28 | * only on word boundaries. |
| 33 | * Not all are used (yet), or are interesting to us (yet). | 29 | * Not all are used (yet), or are interesting to us (yet). |
| @@ -44,14 +40,5 @@ | |||
| 44 | #define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/ | 40 | #define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/ |
| 45 | #define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */ | 41 | #define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */ |
| 46 | 42 | ||
| 47 | /* cpm serial driver works with constants below */ | ||
| 48 | |||
| 49 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) | ||
| 50 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) | ||
| 51 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) | ||
| 52 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) | ||
| 53 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) | ||
| 54 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) | ||
| 55 | |||
| 56 | #endif /* __MACH_ADS8260_DEFS */ | 43 | #endif /* __MACH_ADS8260_DEFS */ |
| 57 | #endif /* __KERNEL__ */ | 44 | #endif /* __KERNEL__ */ |
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig index 437d29a59d72..083ebee9a16d 100644 --- a/arch/powerpc/platforms/83xx/Kconfig +++ b/arch/powerpc/platforms/83xx/Kconfig | |||
| @@ -96,6 +96,13 @@ config ASP834x | |||
| 96 | This enables support for the Analogue & Micro ASP 83xx | 96 | This enables support for the Analogue & Micro ASP 83xx |
| 97 | board. | 97 | board. |
| 98 | 98 | ||
| 99 | config KMETER1 | ||
| 100 | bool "Keymile KMETER1" | ||
| 101 | select DEFAULT_UIMAGE | ||
| 102 | select QUICC_ENGINE | ||
| 103 | help | ||
| 104 | This enables support for the Keymile KMETER1 board. | ||
| 105 | |||
| 99 | 106 | ||
| 100 | endif | 107 | endif |
| 101 | 108 | ||
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile index 051777c542c7..e139c36572ec 100644 --- a/arch/powerpc/platforms/83xx/Makefile +++ b/arch/powerpc/platforms/83xx/Makefile | |||
| @@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o | |||
| 15 | obj-$(CONFIG_SBC834x) += sbc834x.o | 15 | obj-$(CONFIG_SBC834x) += sbc834x.o |
| 16 | obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o | 16 | obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o |
| 17 | obj-$(CONFIG_ASP834x) += asp834x.o | 17 | obj-$(CONFIG_ASP834x) += asp834x.o |
| 18 | obj-$(CONFIG_KMETER1) += kmeter1.o | ||
diff --git a/arch/powerpc/platforms/83xx/kmeter1.c b/arch/powerpc/platforms/83xx/kmeter1.c new file mode 100644 index 000000000000..903acfd851ac --- /dev/null +++ b/arch/powerpc/platforms/83xx/kmeter1.c | |||
| @@ -0,0 +1,191 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 DENX Software Engineering GmbH | ||
| 3 | * Author: Heiko Schocher <hs@denx.de> | ||
| 4 | * | ||
| 5 | * Description: | ||
| 6 | * Keymile KMETER1 board specific routines. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/stddef.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/reboot.h> | ||
| 19 | #include <linux/pci.h> | ||
| 20 | #include <linux/kdev_t.h> | ||
| 21 | #include <linux/major.h> | ||
| 22 | #include <linux/console.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/seq_file.h> | ||
| 25 | #include <linux/root_dev.h> | ||
| 26 | #include <linux/initrd.h> | ||
| 27 | #include <linux/of_platform.h> | ||
| 28 | #include <linux/of_device.h> | ||
| 29 | |||
| 30 | #include <asm/system.h> | ||
| 31 | #include <asm/atomic.h> | ||
| 32 | #include <asm/time.h> | ||
| 33 | #include <asm/io.h> | ||
| 34 | #include <asm/machdep.h> | ||
| 35 | #include <asm/ipic.h> | ||
| 36 | #include <asm/irq.h> | ||
| 37 | #include <asm/prom.h> | ||
| 38 | #include <asm/udbg.h> | ||
| 39 | #include <sysdev/fsl_soc.h> | ||
| 40 | #include <sysdev/fsl_pci.h> | ||
| 41 | #include <asm/qe.h> | ||
| 42 | #include <asm/qe_ic.h> | ||
| 43 | |||
| 44 | #include "mpc83xx.h" | ||
| 45 | |||
| 46 | #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ | ||
| 47 | /* ************************************************************************ | ||
| 48 | * | ||
| 49 | * Setup the architecture | ||
| 50 | * | ||
| 51 | */ | ||
| 52 | static void __init kmeter1_setup_arch(void) | ||
| 53 | { | ||
| 54 | struct device_node *np; | ||
| 55 | |||
| 56 | if (ppc_md.progress) | ||
| 57 | ppc_md.progress("kmeter1_setup_arch()", 0); | ||
| 58 | |||
| 59 | #ifdef CONFIG_PCI | ||
| 60 | for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") | ||
| 61 | mpc83xx_add_bridge(np); | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #ifdef CONFIG_QUICC_ENGINE | ||
| 65 | qe_reset(); | ||
| 66 | |||
| 67 | np = of_find_node_by_name(NULL, "par_io"); | ||
| 68 | if (np != NULL) { | ||
| 69 | par_io_init(np); | ||
| 70 | of_node_put(np); | ||
| 71 | |||
| 72 | for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) | ||
| 73 | par_io_of_config(np); | ||
| 74 | } | ||
| 75 | |||
| 76 | np = of_find_compatible_node(NULL, "network", "ucc_geth"); | ||
| 77 | if (np != NULL) { | ||
| 78 | uint svid; | ||
| 79 | |||
| 80 | /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ | ||
| 81 | svid = mfspr(SPRN_SVR); | ||
| 82 | if (SVR_REV(svid) == 0x0021) { | ||
| 83 | struct device_node *np_par; | ||
| 84 | struct resource res; | ||
| 85 | void __iomem *base; | ||
| 86 | int ret; | ||
| 87 | |||
| 88 | np_par = of_find_node_by_name(NULL, "par_io"); | ||
| 89 | if (np_par == NULL) { | ||
| 90 | printk(KERN_WARNING "%s couldn;t find par_io node\n", | ||
| 91 | __func__); | ||
| 92 | return; | ||
| 93 | } | ||
| 94 | /* Map Parallel I/O ports registers */ | ||
| 95 | ret = of_address_to_resource(np_par, 0, &res); | ||
| 96 | if (ret) { | ||
| 97 | printk(KERN_WARNING "%s couldn;t map par_io registers\n", | ||
| 98 | __func__); | ||
| 99 | return; | ||
| 100 | } | ||
| 101 | base = ioremap(res.start, res.end - res.start + 1); | ||
| 102 | |||
| 103 | /* | ||
| 104 | * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) | ||
| 105 | * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) | ||
| 106 | */ | ||
| 107 | setbits32((base + 0xa8), 0x0c003000); | ||
| 108 | |||
| 109 | /* | ||
| 110 | * IMMR + 0x14AC[20:27] = 10101010 | ||
| 111 | * (data delay for both UCC's) | ||
| 112 | */ | ||
| 113 | clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); | ||
| 114 | iounmap(base); | ||
| 115 | of_node_put(np_par); | ||
| 116 | } | ||
| 117 | of_node_put(np); | ||
| 118 | } | ||
| 119 | #endif /* CONFIG_QUICC_ENGINE */ | ||
| 120 | } | ||
| 121 | |||
| 122 | static struct of_device_id kmeter_ids[] = { | ||
| 123 | { .type = "soc", }, | ||
| 124 | { .compatible = "soc", }, | ||
| 125 | { .compatible = "simple-bus", }, | ||
| 126 | { .type = "qe", }, | ||
| 127 | { .compatible = "fsl,qe", }, | ||
| 128 | {}, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static int __init kmeter_declare_of_platform_devices(void) | ||
| 132 | { | ||
| 133 | /* Publish the QE devices */ | ||
| 134 | of_platform_bus_probe(NULL, kmeter_ids, NULL); | ||
| 135 | |||
| 136 | return 0; | ||
| 137 | } | ||
| 138 | machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices); | ||
| 139 | |||
| 140 | static void __init kmeter1_init_IRQ(void) | ||
| 141 | { | ||
| 142 | struct device_node *np; | ||
| 143 | |||
| 144 | np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic"); | ||
| 145 | if (!np) { | ||
| 146 | np = of_find_node_by_type(NULL, "ipic"); | ||
| 147 | if (!np) | ||
| 148 | return; | ||
| 149 | } | ||
| 150 | |||
| 151 | ipic_init(np, 0); | ||
| 152 | |||
| 153 | /* Initialize the default interrupt mapping priorities, | ||
| 154 | * in case the boot rom changed something on us. | ||
| 155 | */ | ||
| 156 | ipic_set_default_priority(); | ||
| 157 | of_node_put(np); | ||
| 158 | |||
| 159 | #ifdef CONFIG_QUICC_ENGINE | ||
| 160 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | ||
| 161 | if (!np) { | ||
| 162 | np = of_find_node_by_type(NULL, "qeic"); | ||
| 163 | if (!np) | ||
| 164 | return; | ||
| 165 | } | ||
| 166 | qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); | ||
| 167 | of_node_put(np); | ||
| 168 | #endif /* CONFIG_QUICC_ENGINE */ | ||
| 169 | } | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Called very early, MMU is off, device-tree isn't unflattened | ||
| 173 | */ | ||
| 174 | static int __init kmeter1_probe(void) | ||
| 175 | { | ||
| 176 | unsigned long root = of_get_flat_dt_root(); | ||
| 177 | |||
| 178 | return of_flat_dt_is_compatible(root, "keymile,KMETER1"); | ||
| 179 | } | ||
| 180 | |||
| 181 | define_machine(kmeter1) { | ||
| 182 | .name = "KMETER1", | ||
| 183 | .probe = kmeter1_probe, | ||
| 184 | .setup_arch = kmeter1_setup_arch, | ||
| 185 | .init_IRQ = kmeter1_init_IRQ, | ||
| 186 | .get_irq = ipic_get_irq, | ||
| 187 | .restart = mpc83xx_restart, | ||
| 188 | .time_init = mpc83xx_time_init, | ||
| 189 | .calibrate_decr = generic_calibrate_decr, | ||
| 190 | .progress = udbg_progress, | ||
| 191 | }; | ||
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h index 83cfe51526ec..d1dc5b0b4fbf 100644 --- a/arch/powerpc/platforms/83xx/mpc83xx.h +++ b/arch/powerpc/platforms/83xx/mpc83xx.h | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | /* system i/o configuration register low */ | 22 | /* system i/o configuration register low */ |
| 23 | #define MPC83XX_SICRL_OFFS 0x114 | 23 | #define MPC83XX_SICRL_OFFS 0x114 |
| 24 | #define MPC834X_SICRL_USB_MASK 0x60000000 | 24 | #define MPC834X_SICRL_USB_MASK 0x60000000 |
| 25 | #define MPC834X_SICRL_USB0 0x40000000 | 25 | #define MPC834X_SICRL_USB0 0x20000000 |
| 26 | #define MPC834X_SICRL_USB1 0x20000000 | 26 | #define MPC834X_SICRL_USB1 0x40000000 |
| 27 | #define MPC831X_SICRL_USB_MASK 0x00000c00 | 27 | #define MPC831X_SICRL_USB_MASK 0x00000c00 |
| 28 | #define MPC831X_SICRL_USB_ULPI 0x00000800 | 28 | #define MPC831X_SICRL_USB_ULPI 0x00000800 |
| 29 | #define MPC8315_SICRL_USB_MASK 0x000000fc | 29 | #define MPC8315_SICRL_USB_MASK 0x000000fc |
diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c index 11e1fac17c7f..3ba4bb7d41bb 100644 --- a/arch/powerpc/platforms/83xx/usb.c +++ b/arch/powerpc/platforms/83xx/usb.c | |||
| @@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void) | |||
| 47 | sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ | 47 | sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ |
| 48 | 48 | ||
| 49 | prop = of_get_property(np, "phy_type", NULL); | 49 | prop = of_get_property(np, "phy_type", NULL); |
| 50 | port1_is_dr = 1; | ||
| 50 | if (prop && (!strcmp(prop, "utmi") || | 51 | if (prop && (!strcmp(prop, "utmi") || |
| 51 | !strcmp(prop, "utmi_wide"))) { | 52 | !strcmp(prop, "utmi_wide"))) { |
| 52 | sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; | 53 | sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; |
| 53 | sicrh |= MPC834X_SICRH_USB_UTMI; | 54 | sicrh |= MPC834X_SICRH_USB_UTMI; |
| 54 | port1_is_dr = 1; | 55 | port0_is_dr = 1; |
| 55 | } else if (prop && !strcmp(prop, "serial")) { | 56 | } else if (prop && !strcmp(prop, "serial")) { |
| 56 | dr_mode = of_get_property(np, "dr_mode", NULL); | 57 | dr_mode = of_get_property(np, "dr_mode", NULL); |
| 57 | if (dr_mode && !strcmp(dr_mode, "otg")) { | 58 | if (dr_mode && !strcmp(dr_mode, "otg")) { |
| 58 | sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; | 59 | sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; |
| 59 | port1_is_dr = 1; | 60 | port0_is_dr = 1; |
| 60 | } else { | 61 | } else { |
| 61 | sicrl |= MPC834X_SICRL_USB0; | 62 | sicrl |= MPC834X_SICRL_USB1; |
| 62 | } | 63 | } |
| 63 | } else if (prop && !strcmp(prop, "ulpi")) { | 64 | } else if (prop && !strcmp(prop, "ulpi")) { |
| 64 | sicrl |= MPC834X_SICRL_USB0; | 65 | sicrl |= MPC834X_SICRL_USB1; |
| 65 | } else { | 66 | } else { |
| 66 | printk(KERN_WARNING "834x USB PHY type not supported\n"); | 67 | printk(KERN_WARNING "834x USB PHY type not supported\n"); |
| 67 | } | 68 | } |
| 68 | port0_is_dr = 1; | ||
| 69 | of_node_put(np); | 69 | of_node_put(np); |
| 70 | } | 70 | } |
| 71 | np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph"); | 71 | np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph"); |
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 7f066adc068c..a9b416688975 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig | |||
| @@ -34,12 +34,15 @@ config MPC85xx_MDS | |||
| 34 | bool "Freescale MPC85xx MDS" | 34 | bool "Freescale MPC85xx MDS" |
| 35 | select DEFAULT_UIMAGE | 35 | select DEFAULT_UIMAGE |
| 36 | select PHYLIB | 36 | select PHYLIB |
| 37 | select HAS_RAPIDIO | ||
| 38 | select SWIOTLB | ||
| 37 | help | 39 | help |
| 38 | This option enables support for the MPC85xx MDS board | 40 | This option enables support for the MPC85xx MDS board |
| 39 | 41 | ||
| 40 | config MPC8536_DS | 42 | config MPC8536_DS |
| 41 | bool "Freescale MPC8536 DS" | 43 | bool "Freescale MPC8536 DS" |
| 42 | select DEFAULT_UIMAGE | 44 | select DEFAULT_UIMAGE |
| 45 | select SWIOTLB | ||
| 43 | help | 46 | help |
| 44 | This option enables support for the MPC8536 DS board | 47 | This option enables support for the MPC8536 DS board |
| 45 | 48 | ||
| @@ -48,6 +51,7 @@ config MPC85xx_DS | |||
| 48 | select PPC_I8259 | 51 | select PPC_I8259 |
| 49 | select DEFAULT_UIMAGE | 52 | select DEFAULT_UIMAGE |
| 50 | select FSL_ULI1575 | 53 | select FSL_ULI1575 |
| 54 | select SWIOTLB | ||
| 51 | help | 55 | help |
| 52 | This option enables support for the MPC85xx DS (MPC8544 DS) board | 56 | This option enables support for the MPC85xx DS (MPC8544 DS) board |
| 53 | 57 | ||
| @@ -63,6 +67,16 @@ config KSI8560 | |||
| 63 | help | 67 | help |
| 64 | This option enables support for the Emerson KSI8560 board | 68 | This option enables support for the Emerson KSI8560 board |
| 65 | 69 | ||
| 70 | config XES_MPC85xx | ||
| 71 | bool "X-ES single-board computer" | ||
| 72 | select DEFAULT_UIMAGE | ||
| 73 | help | ||
| 74 | This option enables support for the various single-board | ||
| 75 | computers from Extreme Engineering Solutions (X-ES) based on | ||
| 76 | Freescale MPC85xx processors. | ||
| 77 | Manufacturer: Extreme Engineering Solutions, Inc. | ||
| 78 | URL: <http://www.xes-inc.com/> | ||
| 79 | |||
| 66 | config STX_GP3 | 80 | config STX_GP3 |
| 67 | bool "Silicon Turnkey Express GP3" | 81 | bool "Silicon Turnkey Express GP3" |
| 68 | help | 82 | help |
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index a857b35b9828..835733f2b12c 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile | |||
| @@ -15,3 +15,4 @@ obj-$(CONFIG_SBC8560) += sbc8560.o | |||
| 15 | obj-$(CONFIG_SBC8548) += sbc8548.o | 15 | obj-$(CONFIG_SBC8548) += sbc8548.o |
| 16 | obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o | 16 | obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o |
| 17 | obj-$(CONFIG_KSI8560) += ksi8560.o | 17 | obj-$(CONFIG_KSI8560) += ksi8560.o |
| 18 | obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o \ No newline at end of file | ||
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c index 63efca20d7bd..055ff417bae9 100644 --- a/arch/powerpc/platforms/85xx/mpc8536_ds.c +++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/seq_file.h> | 17 | #include <linux/seq_file.h> |
| 18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/lmb.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/system.h> | 22 | #include <asm/system.h> |
| 22 | #include <asm/time.h> | 23 | #include <asm/time.h> |
| @@ -26,6 +27,7 @@ | |||
| 26 | #include <asm/prom.h> | 27 | #include <asm/prom.h> |
| 27 | #include <asm/udbg.h> | 28 | #include <asm/udbg.h> |
| 28 | #include <asm/mpic.h> | 29 | #include <asm/mpic.h> |
| 30 | #include <asm/swiotlb.h> | ||
| 29 | 31 | ||
| 30 | #include <sysdev/fsl_soc.h> | 32 | #include <sysdev/fsl_soc.h> |
| 31 | #include <sysdev/fsl_pci.h> | 33 | #include <sysdev/fsl_pci.h> |
| @@ -65,7 +67,9 @@ static void __init mpc8536_ds_setup_arch(void) | |||
| 65 | { | 67 | { |
| 66 | #ifdef CONFIG_PCI | 68 | #ifdef CONFIG_PCI |
| 67 | struct device_node *np; | 69 | struct device_node *np; |
| 70 | struct pci_controller *hose; | ||
| 68 | #endif | 71 | #endif |
| 72 | dma_addr_t max = 0xffffffff; | ||
| 69 | 73 | ||
| 70 | if (ppc_md.progress) | 74 | if (ppc_md.progress) |
| 71 | ppc_md.progress("mpc8536_ds_setup_arch()", 0); | 75 | ppc_md.progress("mpc8536_ds_setup_arch()", 0); |
| @@ -80,11 +84,22 @@ static void __init mpc8536_ds_setup_arch(void) | |||
| 80 | fsl_add_bridge(np, 1); | 84 | fsl_add_bridge(np, 1); |
| 81 | else | 85 | else |
| 82 | fsl_add_bridge(np, 0); | 86 | fsl_add_bridge(np, 0); |
| 87 | |||
| 88 | hose = pci_find_hose_for_OF_device(np); | ||
| 89 | max = min(max, hose->dma_window_base_cur + | ||
| 90 | hose->dma_window_size); | ||
| 83 | } | 91 | } |
| 84 | } | 92 | } |
| 85 | 93 | ||
| 86 | #endif | 94 | #endif |
| 87 | 95 | ||
| 96 | #ifdef CONFIG_SWIOTLB | ||
| 97 | if (lmb_end_of_DRAM() > max) { | ||
| 98 | ppc_swiotlb_enable = 1; | ||
| 99 | set_pci_dma_ops(&swiotlb_pci_dma_ops); | ||
| 100 | } | ||
| 101 | #endif | ||
| 102 | |||
| 88 | printk("MPC8536 DS board from Freescale Semiconductor\n"); | 103 | printk("MPC8536 DS board from Freescale Semiconductor\n"); |
| 89 | } | 104 | } |
| 90 | 105 | ||
| @@ -102,6 +117,8 @@ static int __init mpc8536_ds_publish_devices(void) | |||
| 102 | } | 117 | } |
| 103 | machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices); | 118 | machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices); |
| 104 | 119 | ||
| 120 | machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier); | ||
| 121 | |||
| 105 | /* | 122 | /* |
| 106 | * Called very early, device-tree isn't unflattened | 123 | * Called very early, device-tree isn't unflattened |
| 107 | */ | 124 | */ |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index de66de7a9ca2..849c0ac0025f 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/seq_file.h> | 20 | #include <linux/seq_file.h> |
| 21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
| 23 | #include <linux/lmb.h> | ||
| 23 | 24 | ||
| 24 | #include <asm/system.h> | 25 | #include <asm/system.h> |
| 25 | #include <asm/time.h> | 26 | #include <asm/time.h> |
| @@ -30,6 +31,7 @@ | |||
| 30 | #include <asm/udbg.h> | 31 | #include <asm/udbg.h> |
| 31 | #include <asm/mpic.h> | 32 | #include <asm/mpic.h> |
| 32 | #include <asm/i8259.h> | 33 | #include <asm/i8259.h> |
| 34 | #include <asm/swiotlb.h> | ||
| 33 | 35 | ||
| 34 | #include <sysdev/fsl_soc.h> | 36 | #include <sysdev/fsl_soc.h> |
| 35 | #include <sysdev/fsl_pci.h> | 37 | #include <sysdev/fsl_pci.h> |
| @@ -155,7 +157,9 @@ static void __init mpc85xx_ds_setup_arch(void) | |||
| 155 | { | 157 | { |
| 156 | #ifdef CONFIG_PCI | 158 | #ifdef CONFIG_PCI |
| 157 | struct device_node *np; | 159 | struct device_node *np; |
| 160 | struct pci_controller *hose; | ||
| 158 | #endif | 161 | #endif |
| 162 | dma_addr_t max = 0xffffffff; | ||
| 159 | 163 | ||
| 160 | if (ppc_md.progress) | 164 | if (ppc_md.progress) |
| 161 | ppc_md.progress("mpc85xx_ds_setup_arch()", 0); | 165 | ppc_md.progress("mpc85xx_ds_setup_arch()", 0); |
| @@ -163,13 +167,18 @@ static void __init mpc85xx_ds_setup_arch(void) | |||
| 163 | #ifdef CONFIG_PCI | 167 | #ifdef CONFIG_PCI |
| 164 | for_each_node_by_type(np, "pci") { | 168 | for_each_node_by_type(np, "pci") { |
| 165 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | 169 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || |
| 166 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | 170 | of_device_is_compatible(np, "fsl,mpc8548-pcie") || |
| 171 | of_device_is_compatible(np, "fsl,p2020-pcie")) { | ||
| 167 | struct resource rsrc; | 172 | struct resource rsrc; |
| 168 | of_address_to_resource(np, 0, &rsrc); | 173 | of_address_to_resource(np, 0, &rsrc); |
| 169 | if ((rsrc.start & 0xfffff) == primary_phb_addr) | 174 | if ((rsrc.start & 0xfffff) == primary_phb_addr) |
| 170 | fsl_add_bridge(np, 1); | 175 | fsl_add_bridge(np, 1); |
| 171 | else | 176 | else |
| 172 | fsl_add_bridge(np, 0); | 177 | fsl_add_bridge(np, 0); |
| 178 | |||
| 179 | hose = pci_find_hose_for_OF_device(np); | ||
| 180 | max = min(max, hose->dma_window_base_cur + | ||
| 181 | hose->dma_window_size); | ||
| 173 | } | 182 | } |
| 174 | } | 183 | } |
| 175 | 184 | ||
| @@ -180,6 +189,13 @@ static void __init mpc85xx_ds_setup_arch(void) | |||
| 180 | mpc85xx_smp_init(); | 189 | mpc85xx_smp_init(); |
| 181 | #endif | 190 | #endif |
| 182 | 191 | ||
| 192 | #ifdef CONFIG_SWIOTLB | ||
| 193 | if (lmb_end_of_DRAM() > max) { | ||
| 194 | ppc_swiotlb_enable = 1; | ||
| 195 | set_pci_dma_ops(&swiotlb_pci_dma_ops); | ||
| 196 | } | ||
| 197 | #endif | ||
| 198 | |||
| 183 | printk("MPC85xx DS board from Freescale Semiconductor\n"); | 199 | printk("MPC85xx DS board from Freescale Semiconductor\n"); |
| 184 | } | 200 | } |
| 185 | 201 | ||
| @@ -195,9 +211,9 @@ static int __init mpc8544_ds_probe(void) | |||
| 195 | primary_phb_addr = 0xb000; | 211 | primary_phb_addr = 0xb000; |
| 196 | #endif | 212 | #endif |
| 197 | return 1; | 213 | return 1; |
| 198 | } else { | ||
| 199 | return 0; | ||
| 200 | } | 214 | } |
| 215 | |||
| 216 | return 0; | ||
| 201 | } | 217 | } |
| 202 | 218 | ||
| 203 | static struct of_device_id __initdata mpc85xxds_ids[] = { | 219 | static struct of_device_id __initdata mpc85xxds_ids[] = { |
| @@ -214,6 +230,11 @@ static int __init mpc85xxds_publish_devices(void) | |||
| 214 | } | 230 | } |
| 215 | machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices); | 231 | machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices); |
| 216 | machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices); | 232 | machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices); |
| 233 | machine_device_initcall(p2020_ds, mpc85xxds_publish_devices); | ||
| 234 | |||
| 235 | machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); | ||
| 236 | machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); | ||
| 237 | machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier); | ||
| 217 | 238 | ||
| 218 | /* | 239 | /* |
| 219 | * Called very early, device-tree isn't unflattened | 240 | * Called very early, device-tree isn't unflattened |
| @@ -227,9 +248,26 @@ static int __init mpc8572_ds_probe(void) | |||
| 227 | primary_phb_addr = 0x8000; | 248 | primary_phb_addr = 0x8000; |
| 228 | #endif | 249 | #endif |
| 229 | return 1; | 250 | return 1; |
| 230 | } else { | ||
| 231 | return 0; | ||
| 232 | } | 251 | } |
| 252 | |||
| 253 | return 0; | ||
| 254 | } | ||
| 255 | |||
| 256 | /* | ||
| 257 | * Called very early, device-tree isn't unflattened | ||
| 258 | */ | ||
| 259 | static int __init p2020_ds_probe(void) | ||
| 260 | { | ||
| 261 | unsigned long root = of_get_flat_dt_root(); | ||
| 262 | |||
| 263 | if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) { | ||
| 264 | #ifdef CONFIG_PCI | ||
| 265 | primary_phb_addr = 0x9000; | ||
| 266 | #endif | ||
| 267 | return 1; | ||
| 268 | } | ||
| 269 | |||
| 270 | return 0; | ||
| 233 | } | 271 | } |
| 234 | 272 | ||
| 235 | define_machine(mpc8544_ds) { | 273 | define_machine(mpc8544_ds) { |
| @@ -259,3 +297,17 @@ define_machine(mpc8572_ds) { | |||
| 259 | .calibrate_decr = generic_calibrate_decr, | 297 | .calibrate_decr = generic_calibrate_decr, |
| 260 | .progress = udbg_progress, | 298 | .progress = udbg_progress, |
| 261 | }; | 299 | }; |
| 300 | |||
| 301 | define_machine(p2020_ds) { | ||
| 302 | .name = "P2020 DS", | ||
| 303 | .probe = p2020_ds_probe, | ||
| 304 | .setup_arch = mpc85xx_ds_setup_arch, | ||
| 305 | .init_IRQ = mpc85xx_ds_pic_init, | ||
| 306 | #ifdef CONFIG_PCI | ||
| 307 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | ||
| 308 | #endif | ||
| 309 | .get_irq = mpic_get_irq, | ||
| 310 | .restart = fsl_rstcr_restart, | ||
| 311 | .calibrate_decr = generic_calibrate_decr, | ||
| 312 | .progress = udbg_progress, | ||
| 313 | }; | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 7dd029034aec..77f90b356356 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/of_platform.h> | 33 | #include <linux/of_platform.h> |
| 34 | #include <linux/of_device.h> | 34 | #include <linux/of_device.h> |
| 35 | #include <linux/phy.h> | 35 | #include <linux/phy.h> |
| 36 | #include <linux/lmb.h> | ||
| 36 | 37 | ||
| 37 | #include <asm/system.h> | 38 | #include <asm/system.h> |
| 38 | #include <asm/atomic.h> | 39 | #include <asm/atomic.h> |
| @@ -49,6 +50,7 @@ | |||
| 49 | #include <asm/qe.h> | 50 | #include <asm/qe.h> |
| 50 | #include <asm/qe_ic.h> | 51 | #include <asm/qe_ic.h> |
| 51 | #include <asm/mpic.h> | 52 | #include <asm/mpic.h> |
| 53 | #include <asm/swiotlb.h> | ||
| 52 | 54 | ||
| 53 | #undef DEBUG | 55 | #undef DEBUG |
| 54 | #ifdef DEBUG | 56 | #ifdef DEBUG |
| @@ -155,6 +157,10 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
| 155 | { | 157 | { |
| 156 | struct device_node *np; | 158 | struct device_node *np; |
| 157 | static u8 __iomem *bcsr_regs = NULL; | 159 | static u8 __iomem *bcsr_regs = NULL; |
| 160 | #ifdef CONFIG_PCI | ||
| 161 | struct pci_controller *hose; | ||
| 162 | #endif | ||
| 163 | dma_addr_t max = 0xffffffff; | ||
| 158 | 164 | ||
| 159 | if (ppc_md.progress) | 165 | if (ppc_md.progress) |
| 160 | ppc_md.progress("mpc85xx_mds_setup_arch()", 0); | 166 | ppc_md.progress("mpc85xx_mds_setup_arch()", 0); |
| @@ -179,6 +185,10 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
| 179 | fsl_add_bridge(np, 1); | 185 | fsl_add_bridge(np, 1); |
| 180 | else | 186 | else |
| 181 | fsl_add_bridge(np, 0); | 187 | fsl_add_bridge(np, 0); |
| 188 | |||
| 189 | hose = pci_find_hose_for_OF_device(np); | ||
| 190 | max = min(max, hose->dma_window_base_cur + | ||
| 191 | hose->dma_window_size); | ||
| 182 | } | 192 | } |
| 183 | } | 193 | } |
| 184 | #endif | 194 | #endif |
| @@ -206,26 +216,34 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
| 206 | } | 216 | } |
| 207 | 217 | ||
| 208 | if (bcsr_regs) { | 218 | if (bcsr_regs) { |
| 219 | if (machine_is(mpc8568_mds)) { | ||
| 209 | #define BCSR_UCC1_GETH_EN (0x1 << 7) | 220 | #define BCSR_UCC1_GETH_EN (0x1 << 7) |
| 210 | #define BCSR_UCC2_GETH_EN (0x1 << 7) | 221 | #define BCSR_UCC2_GETH_EN (0x1 << 7) |
| 211 | #define BCSR_UCC1_MODE_MSK (0x3 << 4) | 222 | #define BCSR_UCC1_MODE_MSK (0x3 << 4) |
| 212 | #define BCSR_UCC2_MODE_MSK (0x3 << 0) | 223 | #define BCSR_UCC2_MODE_MSK (0x3 << 0) |
| 213 | 224 | ||
| 214 | /* Turn off UCC1 & UCC2 */ | 225 | /* Turn off UCC1 & UCC2 */ |
| 215 | clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | 226 | clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); |
| 216 | clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | 227 | clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); |
| 217 | 228 | ||
| 218 | /* Mode is RGMII, all bits clear */ | 229 | /* Mode is RGMII, all bits clear */ |
| 219 | clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | | 230 | clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | |
| 220 | BCSR_UCC2_MODE_MSK); | 231 | BCSR_UCC2_MODE_MSK); |
| 221 | |||
| 222 | /* Turn UCC1 & UCC2 on */ | ||
| 223 | setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | ||
| 224 | setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | ||
| 225 | 232 | ||
| 233 | /* Turn UCC1 & UCC2 on */ | ||
| 234 | setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | ||
| 235 | setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | ||
| 236 | } | ||
| 226 | iounmap(bcsr_regs); | 237 | iounmap(bcsr_regs); |
| 227 | } | 238 | } |
| 228 | #endif /* CONFIG_QUICC_ENGINE */ | 239 | #endif /* CONFIG_QUICC_ENGINE */ |
| 240 | |||
| 241 | #ifdef CONFIG_SWIOTLB | ||
| 242 | if (lmb_end_of_DRAM() > max) { | ||
| 243 | ppc_swiotlb_enable = 1; | ||
| 244 | set_pci_dma_ops(&swiotlb_pci_dma_ops); | ||
| 245 | } | ||
| 246 | #endif | ||
| 229 | } | 247 | } |
| 230 | 248 | ||
| 231 | 249 | ||
| @@ -257,7 +275,8 @@ static int __init board_fixups(void) | |||
| 257 | 275 | ||
| 258 | return 0; | 276 | return 0; |
| 259 | } | 277 | } |
| 260 | machine_arch_initcall(mpc85xx_mds, board_fixups); | 278 | machine_arch_initcall(mpc8568_mds, board_fixups); |
| 279 | machine_arch_initcall(mpc8569_mds, board_fixups); | ||
| 261 | 280 | ||
| 262 | static struct of_device_id mpc85xx_ids[] = { | 281 | static struct of_device_id mpc85xx_ids[] = { |
| 263 | { .type = "soc", }, | 282 | { .type = "soc", }, |
| @@ -276,7 +295,11 @@ static int __init mpc85xx_publish_devices(void) | |||
| 276 | 295 | ||
| 277 | return 0; | 296 | return 0; |
| 278 | } | 297 | } |
| 279 | machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices); | 298 | machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); |
| 299 | machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); | ||
| 300 | |||
| 301 | machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); | ||
| 302 | machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); | ||
| 280 | 303 | ||
| 281 | static void __init mpc85xx_mds_pic_init(void) | 304 | static void __init mpc85xx_mds_pic_init(void) |
| 282 | { | 305 | { |
| @@ -321,8 +344,8 @@ static int __init mpc85xx_mds_probe(void) | |||
| 321 | return of_flat_dt_is_compatible(root, "MPC85xxMDS"); | 344 | return of_flat_dt_is_compatible(root, "MPC85xxMDS"); |
| 322 | } | 345 | } |
| 323 | 346 | ||
| 324 | define_machine(mpc85xx_mds) { | 347 | define_machine(mpc8568_mds) { |
| 325 | .name = "MPC85xx MDS", | 348 | .name = "MPC8568 MDS", |
| 326 | .probe = mpc85xx_mds_probe, | 349 | .probe = mpc85xx_mds_probe, |
| 327 | .setup_arch = mpc85xx_mds_setup_arch, | 350 | .setup_arch = mpc85xx_mds_setup_arch, |
| 328 | .init_IRQ = mpc85xx_mds_pic_init, | 351 | .init_IRQ = mpc85xx_mds_pic_init, |
| @@ -334,3 +357,24 @@ define_machine(mpc85xx_mds) { | |||
| 334 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 357 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
| 335 | #endif | 358 | #endif |
| 336 | }; | 359 | }; |
| 360 | |||
| 361 | static int __init mpc8569_mds_probe(void) | ||
| 362 | { | ||
| 363 | unsigned long root = of_get_flat_dt_root(); | ||
| 364 | |||
| 365 | return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS"); | ||
| 366 | } | ||
| 367 | |||
| 368 | define_machine(mpc8569_mds) { | ||
| 369 | .name = "MPC8569 MDS", | ||
| 370 | .probe = mpc8569_mds_probe, | ||
| 371 | .setup_arch = mpc85xx_mds_setup_arch, | ||
| 372 | .init_IRQ = mpc85xx_mds_pic_init, | ||
| 373 | .get_irq = mpic_get_irq, | ||
| 374 | .restart = fsl_rstcr_restart, | ||
| 375 | .calibrate_decr = generic_calibrate_decr, | ||
| 376 | .progress = udbg_progress, | ||
| 377 | #ifdef CONFIG_PCI | ||
| 378 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | ||
| 379 | #endif | ||
| 380 | }; | ||
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c new file mode 100644 index 000000000000..ee01532786e4 --- /dev/null +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c | |||
| @@ -0,0 +1,282 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Extreme Engineering Solutions, Inc. | ||
| 3 | * | ||
| 4 | * X-ES board-specific functionality | ||
| 5 | * | ||
| 6 | * Based on mpc85xx_ds code from Freescale Semiconductor, Inc. | ||
| 7 | * | ||
| 8 | * Author: Nate Case <ncase@xes-inc.com> | ||
| 9 | * | ||
| 10 | * This is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/stddef.h> | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/pci.h> | ||
| 18 | #include <linux/kdev_t.h> | ||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/seq_file.h> | ||
| 21 | #include <linux/interrupt.h> | ||
| 22 | #include <linux/of_platform.h> | ||
| 23 | |||
| 24 | #include <asm/system.h> | ||
| 25 | #include <asm/time.h> | ||
| 26 | #include <asm/machdep.h> | ||
| 27 | #include <asm/pci-bridge.h> | ||
| 28 | #include <mm/mmu_decl.h> | ||
| 29 | #include <asm/prom.h> | ||
| 30 | #include <asm/udbg.h> | ||
| 31 | #include <asm/mpic.h> | ||
| 32 | |||
| 33 | #include <sysdev/fsl_soc.h> | ||
| 34 | #include <sysdev/fsl_pci.h> | ||
| 35 | #include <linux/of_platform.h> | ||
| 36 | |||
| 37 | /* A few bit definitions needed for fixups on some boards */ | ||
| 38 | #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ | ||
| 39 | #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */ | ||
| 40 | #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */ | ||
| 41 | |||
| 42 | void __init xes_mpc85xx_pic_init(void) | ||
| 43 | { | ||
| 44 | struct mpic *mpic; | ||
| 45 | struct resource r; | ||
| 46 | struct device_node *np; | ||
| 47 | |||
| 48 | np = of_find_node_by_type(NULL, "open-pic"); | ||
| 49 | if (np == NULL) { | ||
| 50 | printk(KERN_ERR "Could not find open-pic node\n"); | ||
| 51 | return; | ||
| 52 | } | ||
| 53 | |||
| 54 | if (of_address_to_resource(np, 0, &r)) { | ||
| 55 | printk(KERN_ERR "Failed to map mpic register space\n"); | ||
| 56 | of_node_put(np); | ||
| 57 | return; | ||
| 58 | } | ||
| 59 | |||
| 60 | mpic = mpic_alloc(np, r.start, | ||
| 61 | MPIC_PRIMARY | MPIC_WANTS_RESET | | ||
| 62 | MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, | ||
| 63 | 0, 256, " OpenPIC "); | ||
| 64 | BUG_ON(mpic == NULL); | ||
| 65 | of_node_put(np); | ||
| 66 | |||
| 67 | mpic_init(mpic); | ||
| 68 | } | ||
| 69 | |||
| 70 | static void xes_mpc85xx_configure_l2(void __iomem *l2_base) | ||
| 71 | { | ||
| 72 | volatile uint32_t ctl, tmp; | ||
| 73 | |||
| 74 | asm volatile("msync; isync"); | ||
| 75 | tmp = in_be32(l2_base); | ||
| 76 | |||
| 77 | /* | ||
| 78 | * xMon may have enabled part of L2 as SRAM, so we need to set it | ||
| 79 | * up for all cache mode just to be safe. | ||
| 80 | */ | ||
| 81 | printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); | ||
| 82 | |||
| 83 | ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; | ||
| 84 | if (machine_is_compatible("MPC8540") || | ||
| 85 | machine_is_compatible("MPC8560")) | ||
| 86 | /* | ||
| 87 | * Assume L2 SRAM is used fully for cache, so set | ||
| 88 | * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). | ||
| 89 | */ | ||
| 90 | ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; | ||
| 91 | |||
| 92 | asm volatile("msync; isync"); | ||
| 93 | out_be32(l2_base, ctl); | ||
| 94 | asm volatile("msync; isync"); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void xes_mpc85xx_fixups(void) | ||
| 98 | { | ||
| 99 | struct device_node *np; | ||
| 100 | int err; | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Legacy xMon firmware on some X-ES boards does not enable L2 | ||
| 104 | * as cache. We must ensure that they get enabled here. | ||
| 105 | */ | ||
| 106 | for_each_node_by_name(np, "l2-cache-controller") { | ||
| 107 | struct resource r[2]; | ||
| 108 | void __iomem *l2_base; | ||
| 109 | |||
| 110 | /* Only MPC8548, MPC8540, and MPC8560 boards are affected */ | ||
| 111 | if (!of_device_is_compatible(np, | ||
| 112 | "fsl,mpc8548-l2-cache-controller") && | ||
| 113 | !of_device_is_compatible(np, | ||
| 114 | "fsl,mpc8540-l2-cache-controller") && | ||
| 115 | !of_device_is_compatible(np, | ||
| 116 | "fsl,mpc8560-l2-cache-controller")) | ||
| 117 | continue; | ||
| 118 | |||
| 119 | err = of_address_to_resource(np, 0, &r[0]); | ||
| 120 | if (err) { | ||
| 121 | printk(KERN_WARNING "xes_mpc85xx: Could not get " | ||
| 122 | "resource for device tree node '%s'", | ||
| 123 | np->full_name); | ||
| 124 | continue; | ||
| 125 | } | ||
| 126 | |||
| 127 | l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1); | ||
| 128 | |||
| 129 | xes_mpc85xx_configure_l2(l2_base); | ||
| 130 | } | ||
| 131 | } | ||
| 132 | |||
| 133 | #ifdef CONFIG_PCI | ||
| 134 | static int primary_phb_addr; | ||
| 135 | #endif | ||
| 136 | |||
| 137 | /* | ||
| 138 | * Setup the architecture | ||
| 139 | */ | ||
| 140 | #ifdef CONFIG_SMP | ||
| 141 | extern void __init mpc85xx_smp_init(void); | ||
| 142 | #endif | ||
| 143 | static void __init xes_mpc85xx_setup_arch(void) | ||
| 144 | { | ||
| 145 | #ifdef CONFIG_PCI | ||
| 146 | struct device_node *np; | ||
| 147 | #endif | ||
| 148 | struct device_node *root; | ||
| 149 | const char *model = "Unknown"; | ||
| 150 | |||
| 151 | root = of_find_node_by_path("/"); | ||
| 152 | if (root == NULL) | ||
| 153 | return; | ||
| 154 | |||
| 155 | model = of_get_property(root, "model", NULL); | ||
| 156 | |||
| 157 | printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n", | ||
| 158 | model + strlen("xes,")); | ||
| 159 | |||
| 160 | xes_mpc85xx_fixups(); | ||
| 161 | |||
| 162 | #ifdef CONFIG_PCI | ||
| 163 | for_each_node_by_type(np, "pci") { | ||
| 164 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | ||
| 165 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | ||
| 166 | struct resource rsrc; | ||
| 167 | of_address_to_resource(np, 0, &rsrc); | ||
| 168 | if ((rsrc.start & 0xfffff) == primary_phb_addr) | ||
| 169 | fsl_add_bridge(np, 1); | ||
| 170 | else | ||
| 171 | fsl_add_bridge(np, 0); | ||
| 172 | } | ||
| 173 | } | ||
| 174 | #endif | ||
| 175 | |||
| 176 | #ifdef CONFIG_SMP | ||
| 177 | mpc85xx_smp_init(); | ||
| 178 | #endif | ||
| 179 | } | ||
| 180 | |||
| 181 | static struct of_device_id __initdata xes_mpc85xx_ids[] = { | ||
| 182 | { .type = "soc", }, | ||
| 183 | { .compatible = "soc", }, | ||
| 184 | { .compatible = "simple-bus", }, | ||
| 185 | { .compatible = "gianfar", }, | ||
| 186 | {}, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static int __init xes_mpc85xx_publish_devices(void) | ||
| 190 | { | ||
| 191 | return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL); | ||
| 192 | } | ||
| 193 | machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices); | ||
| 194 | machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices); | ||
| 195 | machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices); | ||
| 196 | |||
| 197 | /* | ||
| 198 | * Called very early, device-tree isn't unflattened | ||
| 199 | */ | ||
| 200 | static int __init xes_mpc8572_probe(void) | ||
| 201 | { | ||
| 202 | unsigned long root = of_get_flat_dt_root(); | ||
| 203 | |||
| 204 | if (of_flat_dt_is_compatible(root, "xes,MPC8572")) { | ||
| 205 | #ifdef CONFIG_PCI | ||
| 206 | primary_phb_addr = 0x8000; | ||
| 207 | #endif | ||
| 208 | return 1; | ||
| 209 | } else { | ||
| 210 | return 0; | ||
| 211 | } | ||
| 212 | } | ||
| 213 | |||
| 214 | static int __init xes_mpc8548_probe(void) | ||
| 215 | { | ||
| 216 | unsigned long root = of_get_flat_dt_root(); | ||
| 217 | |||
| 218 | if (of_flat_dt_is_compatible(root, "xes,MPC8548")) { | ||
| 219 | #ifdef CONFIG_PCI | ||
| 220 | primary_phb_addr = 0xb000; | ||
| 221 | #endif | ||
| 222 | return 1; | ||
| 223 | } else { | ||
| 224 | return 0; | ||
| 225 | } | ||
| 226 | } | ||
| 227 | |||
| 228 | static int __init xes_mpc8540_probe(void) | ||
| 229 | { | ||
| 230 | unsigned long root = of_get_flat_dt_root(); | ||
| 231 | |||
| 232 | if (of_flat_dt_is_compatible(root, "xes,MPC8540")) { | ||
| 233 | #ifdef CONFIG_PCI | ||
| 234 | primary_phb_addr = 0xb000; | ||
| 235 | #endif | ||
| 236 | return 1; | ||
| 237 | } else { | ||
| 238 | return 0; | ||
| 239 | } | ||
| 240 | } | ||
| 241 | |||
| 242 | define_machine(xes_mpc8572) { | ||
| 243 | .name = "X-ES MPC8572", | ||
| 244 | .probe = xes_mpc8572_probe, | ||
| 245 | .setup_arch = xes_mpc85xx_setup_arch, | ||
| 246 | .init_IRQ = xes_mpc85xx_pic_init, | ||
| 247 | #ifdef CONFIG_PCI | ||
| 248 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | ||
| 249 | #endif | ||
| 250 | .get_irq = mpic_get_irq, | ||
| 251 | .restart = fsl_rstcr_restart, | ||
| 252 | .calibrate_decr = generic_calibrate_decr, | ||
| 253 | .progress = udbg_progress, | ||
| 254 | }; | ||
| 255 | |||
| 256 | define_machine(xes_mpc8548) { | ||
| 257 | .name = "X-ES MPC8548", | ||
| 258 | .probe = xes_mpc8548_probe, | ||
| 259 | .setup_arch = xes_mpc85xx_setup_arch, | ||
| 260 | .init_IRQ = xes_mpc85xx_pic_init, | ||
| 261 | #ifdef CONFIG_PCI | ||
| 262 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | ||
| 263 | #endif | ||
| 264 | .get_irq = mpic_get_irq, | ||
| 265 | .restart = fsl_rstcr_restart, | ||
| 266 | .calibrate_decr = generic_calibrate_decr, | ||
| 267 | .progress = udbg_progress, | ||
| 268 | }; | ||
| 269 | |||
| 270 | define_machine(xes_mpc8540) { | ||
| 271 | .name = "X-ES MPC8540", | ||
| 272 | .probe = xes_mpc8540_probe, | ||
| 273 | .setup_arch = xes_mpc85xx_setup_arch, | ||
| 274 | .init_IRQ = xes_mpc85xx_pic_init, | ||
| 275 | #ifdef CONFIG_PCI | ||
| 276 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | ||
| 277 | #endif | ||
| 278 | .get_irq = mpic_get_irq, | ||
| 279 | .restart = fsl_rstcr_restart, | ||
| 280 | .calibrate_decr = generic_calibrate_decr, | ||
| 281 | .progress = udbg_progress, | ||
| 282 | }; | ||
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index fdaf4ddaa955..9c7b64a3402b 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig | |||
| @@ -15,6 +15,7 @@ config MPC8641_HPCN | |||
| 15 | select DEFAULT_UIMAGE | 15 | select DEFAULT_UIMAGE |
| 16 | select FSL_ULI1575 | 16 | select FSL_ULI1575 |
| 17 | select HAS_RAPIDIO | 17 | select HAS_RAPIDIO |
| 18 | select SWIOTLB | ||
| 18 | help | 19 | help |
| 19 | This option enables support for the MPC8641 HPCN board. | 20 | This option enables support for the MPC8641 HPCN board. |
| 20 | 21 | ||
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c index d79104669cdc..2efa052975e6 100644 --- a/arch/powerpc/platforms/86xx/gef_ppc9a.c +++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/time.h> | 28 | #include <asm/time.h> |
| 29 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 30 | #include <asm/pci-bridge.h> | 30 | #include <asm/pci-bridge.h> |
| 31 | #include <asm/mpc86xx.h> | ||
| 32 | #include <asm/prom.h> | 31 | #include <asm/prom.h> |
| 33 | #include <mm/mmu_decl.h> | 32 | #include <mm/mmu_decl.h> |
| 34 | #include <asm/udbg.h> | 33 | #include <asm/udbg.h> |
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c index af14f852d747..90754e752bd8 100644 --- a/arch/powerpc/platforms/86xx/gef_sbc310.c +++ b/arch/powerpc/platforms/86xx/gef_sbc310.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/time.h> | 28 | #include <asm/time.h> |
| 29 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 30 | #include <asm/pci-bridge.h> | 30 | #include <asm/pci-bridge.h> |
| 31 | #include <asm/mpc86xx.h> | ||
| 32 | #include <asm/prom.h> | 31 | #include <asm/prom.h> |
| 33 | #include <mm/mmu_decl.h> | 32 | #include <mm/mmu_decl.h> |
| 34 | #include <asm/udbg.h> | 33 | #include <asm/udbg.h> |
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c index ea2360639652..72b31a6010a0 100644 --- a/arch/powerpc/platforms/86xx/gef_sbc610.c +++ b/arch/powerpc/platforms/86xx/gef_sbc610.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/time.h> | 28 | #include <asm/time.h> |
| 29 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 30 | #include <asm/pci-bridge.h> | 30 | #include <asm/pci-bridge.h> |
| 31 | #include <asm/mpc86xx.h> | ||
| 32 | #include <asm/prom.h> | 31 | #include <asm/prom.h> |
| 33 | #include <mm/mmu_decl.h> | 32 | #include <mm/mmu_decl.h> |
| 34 | #include <asm/udbg.h> | 33 | #include <asm/udbg.h> |
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c index 3f49a6f893a3..627908a4cd77 100644 --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/time.h> | 28 | #include <asm/time.h> |
| 29 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 30 | #include <asm/pci-bridge.h> | 30 | #include <asm/pci-bridge.h> |
| 31 | #include <asm/mpc86xx.h> | ||
| 32 | #include <asm/prom.h> | 31 | #include <asm/prom.h> |
| 33 | #include <mm/mmu_decl.h> | 32 | #include <mm/mmu_decl.h> |
| 34 | #include <asm/udbg.h> | 33 | #include <asm/udbg.h> |
| @@ -38,6 +37,7 @@ | |||
| 38 | #include <linux/of_platform.h> | 37 | #include <linux/of_platform.h> |
| 39 | #include <sysdev/fsl_pci.h> | 38 | #include <sysdev/fsl_pci.h> |
| 40 | #include <sysdev/fsl_soc.h> | 39 | #include <sysdev/fsl_soc.h> |
| 40 | #include <sysdev/simple_gpio.h> | ||
| 41 | 41 | ||
| 42 | #include "mpc86xx.h" | 42 | #include "mpc86xx.h" |
| 43 | 43 | ||
| @@ -52,6 +52,9 @@ static struct of_device_id __initdata mpc8610_ids[] = { | |||
| 52 | 52 | ||
| 53 | static int __init mpc8610_declare_of_platform_devices(void) | 53 | static int __init mpc8610_declare_of_platform_devices(void) |
| 54 | { | 54 | { |
| 55 | /* Firstly, register PIXIS GPIOs. */ | ||
| 56 | simple_gpiochip_init("fsl,fpga-pixis-gpio-bank"); | ||
| 57 | |||
| 55 | /* Without this call, the SSI device driver won't get probed. */ | 58 | /* Without this call, the SSI device driver won't get probed. */ |
| 56 | of_platform_bus_probe(NULL, mpc8610_ids, NULL); | 59 | of_platform_bus_probe(NULL, mpc8610_ids, NULL); |
| 57 | 60 | ||
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index c4ec49b5f7f8..66327024a6a6 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | |||
| @@ -19,15 +19,16 @@ | |||
| 19 | #include <linux/delay.h> | 19 | #include <linux/delay.h> |
| 20 | #include <linux/seq_file.h> | 20 | #include <linux/seq_file.h> |
| 21 | #include <linux/of_platform.h> | 21 | #include <linux/of_platform.h> |
| 22 | #include <linux/lmb.h> | ||
| 22 | 23 | ||
| 23 | #include <asm/system.h> | 24 | #include <asm/system.h> |
| 24 | #include <asm/time.h> | 25 | #include <asm/time.h> |
| 25 | #include <asm/machdep.h> | 26 | #include <asm/machdep.h> |
| 26 | #include <asm/pci-bridge.h> | 27 | #include <asm/pci-bridge.h> |
| 27 | #include <asm/mpc86xx.h> | ||
| 28 | #include <asm/prom.h> | 28 | #include <asm/prom.h> |
| 29 | #include <mm/mmu_decl.h> | 29 | #include <mm/mmu_decl.h> |
| 30 | #include <asm/udbg.h> | 30 | #include <asm/udbg.h> |
| 31 | #include <asm/swiotlb.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/mpic.h> | 33 | #include <asm/mpic.h> |
| 33 | 34 | ||
| @@ -71,7 +72,9 @@ mpc86xx_hpcn_setup_arch(void) | |||
| 71 | { | 72 | { |
| 72 | #ifdef CONFIG_PCI | 73 | #ifdef CONFIG_PCI |
| 73 | struct device_node *np; | 74 | struct device_node *np; |
| 75 | struct pci_controller *hose; | ||
| 74 | #endif | 76 | #endif |
| 77 | dma_addr_t max = 0xffffffff; | ||
| 75 | 78 | ||
| 76 | if (ppc_md.progress) | 79 | if (ppc_md.progress) |
| 77 | ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); | 80 | ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); |
| @@ -84,6 +87,9 @@ mpc86xx_hpcn_setup_arch(void) | |||
| 84 | fsl_add_bridge(np, 1); | 87 | fsl_add_bridge(np, 1); |
| 85 | else | 88 | else |
| 86 | fsl_add_bridge(np, 0); | 89 | fsl_add_bridge(np, 0); |
| 90 | hose = pci_find_hose_for_OF_device(np); | ||
| 91 | max = min(max, hose->dma_window_base_cur + | ||
| 92 | hose->dma_window_size); | ||
| 87 | } | 93 | } |
| 88 | 94 | ||
| 89 | ppc_md.pci_exclude_device = mpc86xx_exclude_device; | 95 | ppc_md.pci_exclude_device = mpc86xx_exclude_device; |
| @@ -95,6 +101,13 @@ mpc86xx_hpcn_setup_arch(void) | |||
| 95 | #ifdef CONFIG_SMP | 101 | #ifdef CONFIG_SMP |
| 96 | mpc86xx_smp_init(); | 102 | mpc86xx_smp_init(); |
| 97 | #endif | 103 | #endif |
| 104 | |||
| 105 | #ifdef CONFIG_SWIOTLB | ||
| 106 | if (lmb_end_of_DRAM() > max) { | ||
| 107 | ppc_swiotlb_enable = 1; | ||
| 108 | set_pci_dma_ops(&swiotlb_pci_dma_ops); | ||
| 109 | } | ||
| 110 | #endif | ||
| 98 | } | 111 | } |
| 99 | 112 | ||
| 100 | 113 | ||
| @@ -159,6 +172,7 @@ static int __init declare_of_platform_devices(void) | |||
| 159 | return 0; | 172 | return 0; |
| 160 | } | 173 | } |
| 161 | machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices); | 174 | machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices); |
| 175 | machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier); | ||
| 162 | 176 | ||
| 163 | define_machine(mpc86xx_hpcn) { | 177 | define_machine(mpc86xx_hpcn) { |
| 164 | .name = "MPC86xx HPCN", | 178 | .name = "MPC86xx HPCN", |
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c index 014e26cda08d..d84bbb508ee7 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <asm/pgtable.h> | 20 | #include <asm/pgtable.h> |
| 21 | #include <asm/pci-bridge.h> | 21 | #include <asm/pci-bridge.h> |
| 22 | #include <asm/mpic.h> | 22 | #include <asm/mpic.h> |
| 23 | #include <asm/mpc86xx.h> | ||
| 24 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
| 25 | 24 | ||
| 26 | #include <sysdev/fsl_soc.h> | 25 | #include <sysdev/fsl_soc.h> |
| @@ -30,6 +29,11 @@ | |||
| 30 | extern void __secondary_start_mpc86xx(void); | 29 | extern void __secondary_start_mpc86xx(void); |
| 31 | extern unsigned long __secondary_hold_acknowledge; | 30 | extern unsigned long __secondary_hold_acknowledge; |
| 32 | 31 | ||
| 32 | #define MCM_PORT_CONFIG_OFFSET 0x10 | ||
| 33 | |||
| 34 | /* Offset from CCSRBAR */ | ||
| 35 | #define MPC86xx_MCM_OFFSET (0x1000) | ||
| 36 | #define MPC86xx_MCM_SIZE (0x1000) | ||
| 33 | 37 | ||
| 34 | static void __init | 38 | static void __init |
| 35 | smp_86xx_release_core(int nr) | 39 | smp_86xx_release_core(int nr) |
| @@ -48,6 +52,8 @@ smp_86xx_release_core(int nr) | |||
| 48 | pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2)); | 52 | pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2)); |
| 49 | pcr |= 1 << (nr + 24); | 53 | pcr |= 1 << (nr + 24); |
| 50 | out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr); | 54 | out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr); |
| 55 | |||
| 56 | iounmap(mcm_vaddr); | ||
| 51 | } | 57 | } |
| 52 | 58 | ||
| 53 | 59 | ||
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c index 2886a36fc085..51c8f331b671 100644 --- a/arch/powerpc/platforms/86xx/sbc8641d.c +++ b/arch/powerpc/platforms/86xx/sbc8641d.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <asm/time.h> | 25 | #include <asm/time.h> |
| 26 | #include <asm/machdep.h> | 26 | #include <asm/machdep.h> |
| 27 | #include <asm/pci-bridge.h> | 27 | #include <asm/pci-bridge.h> |
| 28 | #include <asm/mpc86xx.h> | ||
| 29 | #include <asm/prom.h> | 28 | #include <asm/prom.h> |
| 30 | #include <mm/mmu_decl.h> | 29 | #include <mm/mmu_decl.h> |
| 31 | #include <asm/udbg.h> | 30 | #include <asm/udbg.h> |
diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h index a5076668bad6..19412f76fa3b 100644 --- a/arch/powerpc/platforms/8xx/mpc885ads.h +++ b/arch/powerpc/platforms/8xx/mpc885ads.h | |||
| @@ -17,10 +17,6 @@ | |||
| 17 | 17 | ||
| 18 | #include <sysdev/fsl_soc.h> | 18 | #include <sysdev/fsl_soc.h> |
| 19 | 19 | ||
| 20 | #define MPC8xx_CPM_OFFSET (0x9c0) | ||
| 21 | #define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) | ||
| 22 | #define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver | ||
| 23 | |||
| 24 | /* Bits of interest in the BCSRs. | 20 | /* Bits of interest in the BCSRs. |
| 25 | */ | 21 | */ |
| 26 | #define BCSR1_ETHEN ((uint)0x20000000) | 22 | #define BCSR1_ETHEN ((uint)0x20000000) |
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index e3e87078d03f..04a8061045c4 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig | |||
| @@ -329,4 +329,8 @@ config MCU_MPC8349EMITX | |||
| 329 | also register MCU GPIOs with the generic GPIO API, so you'll able | 329 | also register MCU GPIOs with the generic GPIO API, so you'll able |
| 330 | to use MCU pins as GPIOs. | 330 | to use MCU pins as GPIOs. |
| 331 | 331 | ||
| 332 | config XILINX_PCI | ||
| 333 | bool "Xilinx PCI host bridge support" | ||
| 334 | depends on PCI && XILINX_VIRTEX | ||
| 335 | |||
| 332 | endmenu | 336 | endmenu |
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index 9da795e49337..61187bec7506 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | config PPC64 | 1 | config PPC64 |
| 2 | bool "64-bit kernel" | 2 | bool "64-bit kernel" |
| 3 | default n | 3 | default n |
| 4 | select PPC_HAVE_PMU_SUPPORT | ||
| 4 | help | 5 | help |
| 5 | This option selects whether a 32-bit or a 64-bit kernel | 6 | This option selects whether a 32-bit or a 64-bit kernel |
| 6 | will be built. | 7 | will be built. |
| @@ -9,7 +10,6 @@ menu "Processor support" | |||
| 9 | choice | 10 | choice |
| 10 | prompt "Processor Type" | 11 | prompt "Processor Type" |
| 11 | depends on PPC32 | 12 | depends on PPC32 |
| 12 | default 6xx | ||
| 13 | help | 13 | help |
| 14 | There are five families of 32 bit PowerPC chips supported. | 14 | There are five families of 32 bit PowerPC chips supported. |
| 15 | The most common ones are the desktop and server CPUs (601, 603, | 15 | The most common ones are the desktop and server CPUs (601, 603, |
| @@ -21,7 +21,7 @@ choice | |||
| 21 | 21 | ||
| 22 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. | 22 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. |
| 23 | 23 | ||
| 24 | config 6xx | 24 | config PPC_BOOK3S_32 |
| 25 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" | 25 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" |
| 26 | select PPC_FPU | 26 | select PPC_FPU |
| 27 | 27 | ||
| @@ -57,13 +57,14 @@ config E200 | |||
| 57 | 57 | ||
| 58 | endchoice | 58 | endchoice |
| 59 | 59 | ||
| 60 | # Until we have a choice of exclusive CPU types on 64-bit, we always | 60 | config PPC_BOOK3S_64 |
| 61 | # use PPC_BOOK3S. On 32-bit, this is equivalent to 6xx which is | 61 | def_bool y |
| 62 | # "classic" MMU | 62 | depends on PPC64 |
| 63 | select PPC_FPU | ||
| 63 | 64 | ||
| 64 | config PPC_BOOK3S | 65 | config PPC_BOOK3S |
| 65 | def_bool y | 66 | def_bool y |
| 66 | depends on PPC64 || 6xx | 67 | depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 |
| 67 | 68 | ||
| 68 | config POWER4_ONLY | 69 | config POWER4_ONLY |
| 69 | bool "Optimize for POWER4" | 70 | bool "Optimize for POWER4" |
| @@ -74,6 +75,11 @@ config POWER4_ONLY | |||
| 74 | The resulting binary will not work on POWER3 or RS64 processors | 75 | The resulting binary will not work on POWER3 or RS64 processors |
| 75 | when compiled with binutils 2.15 or later. | 76 | when compiled with binutils 2.15 or later. |
| 76 | 77 | ||
| 78 | config 6xx | ||
| 79 | def_bool y | ||
| 80 | depends on PPC32 && PPC_BOOK3S | ||
| 81 | select PPC_HAVE_PMU_SUPPORT | ||
| 82 | |||
| 77 | config POWER3 | 83 | config POWER3 |
| 78 | bool | 84 | bool |
| 79 | depends on PPC64 && PPC_BOOK3S | 85 | depends on PPC64 && PPC_BOOK3S |
| @@ -202,9 +208,8 @@ config SPE | |||
| 202 | If in doubt, say Y here. | 208 | If in doubt, say Y here. |
| 203 | 209 | ||
| 204 | config PPC_STD_MMU | 210 | config PPC_STD_MMU |
| 205 | bool | 211 | def_bool y |
| 206 | depends on 6xx || PPC64 | 212 | depends on PPC_BOOK3S |
| 207 | default y | ||
| 208 | 213 | ||
| 209 | config PPC_STD_MMU_32 | 214 | config PPC_STD_MMU_32 |
| 210 | def_bool y | 215 | def_bool y |
| @@ -242,6 +247,15 @@ config VIRT_CPU_ACCOUNTING | |||
| 242 | 247 | ||
| 243 | If in doubt, say Y here. | 248 | If in doubt, say Y here. |
| 244 | 249 | ||
| 250 | config PPC_HAVE_PMU_SUPPORT | ||
| 251 | bool | ||
| 252 | |||
| 253 | config PPC_PERF_CTRS | ||
| 254 | def_bool y | ||
| 255 | depends on PERF_COUNTERS && PPC_HAVE_PMU_SUPPORT | ||
| 256 | help | ||
| 257 | This enables the powerpc-specific perf_counter back-end. | ||
| 258 | |||
| 245 | config SMP | 259 | config SMP |
| 246 | depends on PPC_STD_MMU || FSL_BOOKE | 260 | depends on PPC_STD_MMU || FSL_BOOKE |
| 247 | bool "Symmetric multi-processing support" | 261 | bool "Symmetric multi-processing support" |
| @@ -262,8 +276,8 @@ config SMP | |||
| 262 | If you don't know what to do here, say N. | 276 | If you don't know what to do here, say N. |
| 263 | 277 | ||
| 264 | config NR_CPUS | 278 | config NR_CPUS |
| 265 | int "Maximum number of CPUs (2-1024)" | 279 | int "Maximum number of CPUs (2-8192)" |
| 266 | range 2 1024 | 280 | range 2 8192 |
| 267 | depends on SMP | 281 | depends on SMP |
| 268 | default "32" if PPC64 | 282 | default "32" if PPC64 |
| 269 | default "4" | 283 | default "4" |
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile index f7419198e635..a6812ee00100 100644 --- a/arch/powerpc/platforms/Makefile +++ b/arch/powerpc/platforms/Makefile | |||
| @@ -1,4 +1,6 @@ | |||
| 1 | 1 | ||
| 2 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 3 | |||
| 2 | obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o | 4 | obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o |
| 3 | 5 | ||
| 4 | obj-$(CONFIG_PPC_PMAC) += powermac/ | 6 | obj-$(CONFIG_PPC_PMAC) += powermac/ |
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index 0ce45c2b42f8..c71498dbf211 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
| @@ -329,7 +329,7 @@ static struct irq_host_ops msic_host_ops = { | |||
| 329 | 329 | ||
| 330 | static int axon_msi_shutdown(struct of_device *device) | 330 | static int axon_msi_shutdown(struct of_device *device) |
| 331 | { | 331 | { |
| 332 | struct axon_msic *msic = device->dev.platform_data; | 332 | struct axon_msic *msic = dev_get_drvdata(&device->dev); |
| 333 | u32 tmp; | 333 | u32 tmp; |
| 334 | 334 | ||
| 335 | pr_debug("axon_msi: disabling %s\n", | 335 | pr_debug("axon_msi: disabling %s\n", |
| @@ -416,7 +416,7 @@ static int axon_msi_probe(struct of_device *device, | |||
| 416 | msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) | 416 | msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) |
| 417 | & MSIC_FIFO_SIZE_MASK; | 417 | & MSIC_FIFO_SIZE_MASK; |
| 418 | 418 | ||
| 419 | device->dev.platform_data = msic; | 419 | dev_set_drvdata(&device->dev, msic); |
| 420 | 420 | ||
| 421 | ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; | 421 | ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; |
| 422 | ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs; | 422 | ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs; |
diff --git a/arch/powerpc/platforms/cell/celleb_pci.c b/arch/powerpc/platforms/cell/celleb_pci.c index f39a3b2a1667..00eaaa71630f 100644 --- a/arch/powerpc/platforms/cell/celleb_pci.c +++ b/arch/powerpc/platforms/cell/celleb_pci.c | |||
| @@ -162,8 +162,7 @@ static int celleb_fake_pci_read_config(struct pci_bus *bus, | |||
| 162 | unsigned int devfn, int where, int size, u32 *val) | 162 | unsigned int devfn, int where, int size, u32 *val) |
| 163 | { | 163 | { |
| 164 | char *config; | 164 | char *config; |
| 165 | struct device_node *node; | 165 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 166 | struct pci_controller *hose; | ||
| 167 | unsigned int devno = devfn >> 3; | 166 | unsigned int devno = devfn >> 3; |
| 168 | unsigned int fn = devfn & 0x7; | 167 | unsigned int fn = devfn & 0x7; |
| 169 | 168 | ||
| @@ -171,8 +170,6 @@ static int celleb_fake_pci_read_config(struct pci_bus *bus, | |||
| 171 | BUG_ON(where % size); | 170 | BUG_ON(where % size); |
| 172 | 171 | ||
| 173 | pr_debug(" fake read: bus=0x%x, ", bus->number); | 172 | pr_debug(" fake read: bus=0x%x, ", bus->number); |
| 174 | node = (struct device_node *)bus->sysdata; | ||
| 175 | hose = pci_find_hose_for_OF_device(node); | ||
| 176 | config = get_fake_config_start(hose, devno, fn); | 173 | config = get_fake_config_start(hose, devno, fn); |
| 177 | 174 | ||
| 178 | pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size); | 175 | pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size); |
| @@ -192,8 +189,7 @@ static int celleb_fake_pci_write_config(struct pci_bus *bus, | |||
| 192 | unsigned int devfn, int where, int size, u32 val) | 189 | unsigned int devfn, int where, int size, u32 val) |
| 193 | { | 190 | { |
| 194 | char *config; | 191 | char *config; |
| 195 | struct device_node *node; | 192 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 196 | struct pci_controller *hose; | ||
| 197 | struct celleb_pci_resource *res; | 193 | struct celleb_pci_resource *res; |
| 198 | unsigned int devno = devfn >> 3; | 194 | unsigned int devno = devfn >> 3; |
| 199 | unsigned int fn = devfn & 0x7; | 195 | unsigned int fn = devfn & 0x7; |
| @@ -201,8 +197,6 @@ static int celleb_fake_pci_write_config(struct pci_bus *bus, | |||
| 201 | /* allignment check */ | 197 | /* allignment check */ |
| 202 | BUG_ON(where % size); | 198 | BUG_ON(where % size); |
| 203 | 199 | ||
| 204 | node = (struct device_node *)bus->sysdata; | ||
| 205 | hose = pci_find_hose_for_OF_device(node); | ||
| 206 | config = get_fake_config_start(hose, devno, fn); | 200 | config = get_fake_config_start(hose, devno, fn); |
| 207 | 201 | ||
| 208 | if (!config) | 202 | if (!config) |
diff --git a/arch/powerpc/platforms/cell/celleb_scc_epci.c b/arch/powerpc/platforms/cell/celleb_scc_epci.c index 48ec88a38a12..05b0db3ef638 100644 --- a/arch/powerpc/platforms/cell/celleb_scc_epci.c +++ b/arch/powerpc/platforms/cell/celleb_scc_epci.c | |||
| @@ -134,15 +134,11 @@ static int celleb_epci_read_config(struct pci_bus *bus, | |||
| 134 | { | 134 | { |
| 135 | PCI_IO_ADDR epci_base; | 135 | PCI_IO_ADDR epci_base; |
| 136 | PCI_IO_ADDR addr; | 136 | PCI_IO_ADDR addr; |
| 137 | struct device_node *node; | 137 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 138 | struct pci_controller *hose; | ||
| 139 | 138 | ||
| 140 | /* allignment check */ | 139 | /* allignment check */ |
| 141 | BUG_ON(where % size); | 140 | BUG_ON(where % size); |
| 142 | 141 | ||
| 143 | node = (struct device_node *)bus->sysdata; | ||
| 144 | hose = pci_find_hose_for_OF_device(node); | ||
| 145 | |||
| 146 | if (!celleb_epci_get_epci_cfg(hose)) | 142 | if (!celleb_epci_get_epci_cfg(hose)) |
| 147 | return PCIBIOS_DEVICE_NOT_FOUND; | 143 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 148 | 144 | ||
| @@ -198,16 +194,11 @@ static int celleb_epci_write_config(struct pci_bus *bus, | |||
| 198 | { | 194 | { |
| 199 | PCI_IO_ADDR epci_base; | 195 | PCI_IO_ADDR epci_base; |
| 200 | PCI_IO_ADDR addr; | 196 | PCI_IO_ADDR addr; |
| 201 | struct device_node *node; | 197 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 202 | struct pci_controller *hose; | ||
| 203 | 198 | ||
| 204 | /* allignment check */ | 199 | /* allignment check */ |
| 205 | BUG_ON(where % size); | 200 | BUG_ON(where % size); |
| 206 | 201 | ||
| 207 | node = (struct device_node *)bus->sysdata; | ||
| 208 | hose = pci_find_hose_for_OF_device(node); | ||
| 209 | |||
| 210 | |||
| 211 | if (!celleb_epci_get_epci_cfg(hose)) | 202 | if (!celleb_epci_get_epci_cfg(hose)) |
| 212 | return PCIBIOS_DEVICE_NOT_FOUND; | 203 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 213 | 204 | ||
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c index 3e7e0f1568ef..7fca09f990ba 100644 --- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c +++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c | |||
| @@ -366,11 +366,7 @@ static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where, | |||
| 366 | static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | 366 | static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn, |
| 367 | int where, int size, unsigned int *val) | 367 | int where, int size, unsigned int *val) |
| 368 | { | 368 | { |
| 369 | struct device_node *dn; | 369 | struct pci_controller *phb = pci_bus_to_host(bus); |
| 370 | struct pci_controller *phb; | ||
| 371 | |||
| 372 | dn = bus->sysdata; | ||
| 373 | phb = pci_find_hose_for_OF_device(dn); | ||
| 374 | 370 | ||
| 375 | if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) { | 371 | if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) { |
| 376 | *val = ~0; | 372 | *val = ~0; |
| @@ -389,11 +385,7 @@ static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | |||
| 389 | static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn, | 385 | static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn, |
| 390 | int where, int size, unsigned int val) | 386 | int where, int size, unsigned int val) |
| 391 | { | 387 | { |
| 392 | struct device_node *dn; | 388 | struct pci_controller *phb = pci_bus_to_host(bus); |
| 393 | struct pci_controller *phb; | ||
| 394 | |||
| 395 | dn = bus->sysdata; | ||
| 396 | phb = pci_find_hose_for_OF_device(dn); | ||
| 397 | 389 | ||
| 398 | if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) | 390 | if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) |
| 399 | return PCIBIOS_DEVICE_NOT_FOUND; | 391 | return PCIBIOS_DEVICE_NOT_FOUND; |
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c index bed4690de394..5b34fc211f35 100644 --- a/arch/powerpc/platforms/cell/iommu.c +++ b/arch/powerpc/platforms/cell/iommu.c | |||
| @@ -100,16 +100,6 @@ | |||
| 100 | #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ | 100 | #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ |
| 101 | #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ | 101 | #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ |
| 102 | 102 | ||
| 103 | /* Page table entries */ | ||
| 104 | #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ | ||
| 105 | #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ | ||
| 106 | #define IOPTE_M 0x2000000000000000ul /* coherency required */ | ||
| 107 | #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ | ||
| 108 | #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ | ||
| 109 | #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ | ||
| 110 | #define IOPTE_H 0x0000000000000800ul /* cache hint */ | ||
| 111 | #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ | ||
| 112 | |||
| 113 | 103 | ||
| 114 | /* IOMMU sizing */ | 104 | /* IOMMU sizing */ |
| 115 | #define IO_SEGMENT_SHIFT 28 | 105 | #define IO_SEGMENT_SHIFT 28 |
| @@ -193,19 +183,21 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages, | |||
| 193 | */ | 183 | */ |
| 194 | const unsigned long prot = 0xc48; | 184 | const unsigned long prot = 0xc48; |
| 195 | base_pte = | 185 | base_pte = |
| 196 | ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) | 186 | ((prot << (52 + 4 * direction)) & |
| 197 | | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); | 187 | (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) | |
| 188 | CBE_IOPTE_M | CBE_IOPTE_SO_RW | | ||
| 189 | (window->ioid & CBE_IOPTE_IOID_Mask); | ||
| 198 | #else | 190 | #else |
| 199 | base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | | 191 | base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | |
| 200 | (window->ioid & IOPTE_IOID_Mask); | 192 | CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask); |
| 201 | #endif | 193 | #endif |
| 202 | if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) | 194 | if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) |
| 203 | base_pte &= ~IOPTE_SO_RW; | 195 | base_pte &= ~CBE_IOPTE_SO_RW; |
| 204 | 196 | ||
| 205 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); | 197 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
| 206 | 198 | ||
| 207 | for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) | 199 | for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) |
| 208 | io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); | 200 | io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask); |
| 209 | 201 | ||
| 210 | mb(); | 202 | mb(); |
| 211 | 203 | ||
| @@ -231,8 +223,9 @@ static void tce_free_cell(struct iommu_table *tbl, long index, long npages) | |||
| 231 | #else | 223 | #else |
| 232 | /* spider bridge does PCI reads after freeing - insert a mapping | 224 | /* spider bridge does PCI reads after freeing - insert a mapping |
| 233 | * to a scratch page instead of an invalid entry */ | 225 | * to a scratch page instead of an invalid entry */ |
| 234 | pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) | 226 | pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW | |
| 235 | | (window->ioid & IOPTE_IOID_Mask); | 227 | __pa(window->iommu->pad_page) | |
| 228 | (window->ioid & CBE_IOPTE_IOID_Mask); | ||
| 236 | #endif | 229 | #endif |
| 237 | 230 | ||
| 238 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); | 231 | io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); |
| @@ -1001,7 +994,7 @@ static void insert_16M_pte(unsigned long addr, unsigned long *ptab, | |||
| 1001 | pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", | 994 | pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", |
| 1002 | addr, ptab, segment, offset); | 995 | addr, ptab, segment, offset); |
| 1003 | 996 | ||
| 1004 | ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask); | 997 | ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask); |
| 1005 | } | 998 | } |
| 1006 | 999 | ||
| 1007 | static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, | 1000 | static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, |
| @@ -1016,14 +1009,14 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, | |||
| 1016 | 1009 | ||
| 1017 | pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); | 1010 | pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); |
| 1018 | 1011 | ||
| 1019 | base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | 1012 | base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | |
| 1020 | | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); | 1013 | (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask); |
| 1021 | 1014 | ||
| 1022 | if (iommu_fixed_is_weak) | 1015 | if (iommu_fixed_is_weak) |
| 1023 | pr_info("IOMMU: Using weak ordering for fixed mapping\n"); | 1016 | pr_info("IOMMU: Using weak ordering for fixed mapping\n"); |
| 1024 | else { | 1017 | else { |
| 1025 | pr_info("IOMMU: Using strong ordering for fixed mapping\n"); | 1018 | pr_info("IOMMU: Using strong ordering for fixed mapping\n"); |
| 1026 | base_pte |= IOPTE_SO_RW; | 1019 | base_pte |= CBE_IOPTE_SO_RW; |
| 1027 | } | 1020 | } |
| 1028 | 1021 | ||
| 1029 | for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { | 1022 | for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { |
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c index 296b5268754e..5e0a191764fc 100644 --- a/arch/powerpc/platforms/cell/ras.c +++ b/arch/powerpc/platforms/cell/ras.c | |||
| @@ -122,8 +122,8 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order) | |||
| 122 | 122 | ||
| 123 | area->nid = nid; | 123 | area->nid = nid; |
| 124 | area->order = order; | 124 | area->order = order; |
| 125 | area->pages = alloc_pages_node(area->nid, GFP_KERNEL | GFP_THISNODE, | 125 | area->pages = alloc_pages_exact_node(area->nid, GFP_KERNEL|GFP_THISNODE, |
| 126 | area->order); | 126 | area->order); |
| 127 | 127 | ||
| 128 | if (!area->pages) { | 128 | if (!area->pages) { |
| 129 | printk(KERN_WARNING "%s: no page on node %d\n", | 129 | printk(KERN_WARNING "%s: no page on node %d\n", |
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 9abd210d87c1..8547e86bfb42 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c | |||
| @@ -752,17 +752,8 @@ static int __init init_spu_base(void) | |||
| 752 | goto out_unregister_sysdev_class; | 752 | goto out_unregister_sysdev_class; |
| 753 | } | 753 | } |
| 754 | 754 | ||
| 755 | if (ret > 0) { | 755 | if (ret > 0) |
| 756 | /* | ||
| 757 | * We cannot put the forward declaration in | ||
| 758 | * <linux/linux_logo.h> because of conflicting session type | ||
| 759 | * conflicts for const and __initdata with different compiler | ||
| 760 | * versions | ||
| 761 | */ | ||
| 762 | extern const struct linux_logo logo_spe_clut224; | ||
| 763 | |||
| 764 | fb_append_extra_logo(&logo_spe_clut224, ret); | 756 | fb_append_extra_logo(&logo_spe_clut224, ret); |
| 765 | } | ||
| 766 | 757 | ||
| 767 | mutex_lock(&spu_full_list_mutex); | 758 | mutex_lock(&spu_full_list_mutex); |
| 768 | xmon_register_spus(&spu_full_list); | 759 | xmon_register_spus(&spu_full_list); |
diff --git a/arch/powerpc/platforms/cell/spu_fault.c b/arch/powerpc/platforms/cell/spu_fault.c index 95d8dadf2d87..d06ba87f1a19 100644 --- a/arch/powerpc/platforms/cell/spu_fault.c +++ b/arch/powerpc/platforms/cell/spu_fault.c | |||
| @@ -70,7 +70,7 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, | |||
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | ret = 0; | 72 | ret = 0; |
| 73 | *flt = handle_mm_fault(mm, vma, ea, is_write); | 73 | *flt = handle_mm_fault(mm, vma, ea, is_write ? FAULT_FLAG_WRITE : 0); |
| 74 | if (unlikely(*flt & VM_FAULT_ERROR)) { | 74 | if (unlikely(*flt & VM_FAULT_ERROR)) { |
| 75 | if (*flt & VM_FAULT_OOM) { | 75 | if (*flt & VM_FAULT_OOM) { |
| 76 | ret = -ENOMEM; | 76 | ret = -ENOMEM; |
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c index 706eb5c7e2ee..24b30b6909c4 100644 --- a/arch/powerpc/platforms/cell/spufs/inode.c +++ b/arch/powerpc/platforms/cell/spufs/inode.c | |||
| @@ -631,10 +631,6 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode, | |||
| 631 | if (IS_ERR(dentry)) | 631 | if (IS_ERR(dentry)) |
| 632 | goto out_dir; | 632 | goto out_dir; |
| 633 | 633 | ||
| 634 | ret = -EEXIST; | ||
| 635 | if (dentry->d_inode) | ||
| 636 | goto out_dput; | ||
| 637 | |||
| 638 | mode &= ~current_umask(); | 634 | mode &= ~current_umask(); |
| 639 | 635 | ||
| 640 | if (flags & SPU_CREATE_GANG) | 636 | if (flags & SPU_CREATE_GANG) |
| @@ -648,8 +644,6 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode, | |||
| 648 | fsnotify_mkdir(nd->path.dentry->d_inode, dentry); | 644 | fsnotify_mkdir(nd->path.dentry->d_inode, dentry); |
| 649 | return ret; | 645 | return ret; |
| 650 | 646 | ||
| 651 | out_dput: | ||
| 652 | dput(dentry); | ||
| 653 | out_dir: | 647 | out_dir: |
| 654 | mutex_unlock(&nd->path.dentry->d_inode->i_mutex); | 648 | mutex_unlock(&nd->path.dentry->d_inode->i_mutex); |
| 655 | out: | 649 | out: |
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c index f6b0c519d5a2..8f67a394b2d0 100644 --- a/arch/powerpc/platforms/chrp/pci.c +++ b/arch/powerpc/platforms/chrp/pci.c | |||
| @@ -34,7 +34,7 @@ int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, | |||
| 34 | int len, u32 *val) | 34 | int len, u32 *val) |
| 35 | { | 35 | { |
| 36 | volatile void __iomem *cfg_data; | 36 | volatile void __iomem *cfg_data; |
| 37 | struct pci_controller *hose = bus->sysdata; | 37 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 38 | 38 | ||
| 39 | if (bus->number > 7) | 39 | if (bus->number > 7) |
| 40 | return PCIBIOS_DEVICE_NOT_FOUND; | 40 | return PCIBIOS_DEVICE_NOT_FOUND; |
| @@ -61,7 +61,7 @@ int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, | |||
| 61 | int len, u32 val) | 61 | int len, u32 val) |
| 62 | { | 62 | { |
| 63 | volatile void __iomem *cfg_data; | 63 | volatile void __iomem *cfg_data; |
| 64 | struct pci_controller *hose = bus->sysdata; | 64 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 65 | 65 | ||
| 66 | if (bus->number > 7) | 66 | if (bus->number > 7) |
| 67 | return PCIBIOS_DEVICE_NOT_FOUND; | 67 | return PCIBIOS_DEVICE_NOT_FOUND; |
| @@ -96,7 +96,7 @@ static struct pci_ops gg2_pci_ops = | |||
| 96 | int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | 96 | int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 97 | int len, u32 *val) | 97 | int len, u32 *val) |
| 98 | { | 98 | { |
| 99 | struct pci_controller *hose = bus->sysdata; | 99 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 100 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | 100 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 101 | | (((bus->number - hose->first_busno) & 0xff) << 16) | 101 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 102 | | (hose->global_number << 24); | 102 | | (hose->global_number << 24); |
| @@ -111,7 +111,7 @@ int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |||
| 111 | int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | 111 | int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 112 | int len, u32 val) | 112 | int len, u32 val) |
| 113 | { | 113 | { |
| 114 | struct pci_controller *hose = bus->sysdata; | 114 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 115 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | 115 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) |
| 116 | | (((bus->number - hose->first_busno) & 0xff) << 16) | 116 | | (((bus->number - hose->first_busno) & 0xff) << 16) |
| 117 | | (hose->global_number << 24); | 117 | | (hose->global_number << 24); |
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c index 65a35f38e062..fd23a1d4b39d 100644 --- a/arch/powerpc/platforms/fsl_uli1575.c +++ b/arch/powerpc/platforms/fsl_uli1575.c | |||
| @@ -51,13 +51,20 @@ u8 uli_pirq_to_irq[8] = { | |||
| 51 | ULI_8259_NONE, /* PIRQH */ | 51 | ULI_8259_NONE, /* PIRQH */ |
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | static inline bool is_quirk_valid(void) | ||
| 55 | { | ||
| 56 | return (machine_is(mpc86xx_hpcn) || | ||
| 57 | machine_is(mpc8544_ds) || | ||
| 58 | machine_is(p2020_ds) || | ||
| 59 | machine_is(mpc8572_ds)); | ||
| 60 | } | ||
| 61 | |||
| 54 | /* Bridge */ | 62 | /* Bridge */ |
| 55 | static void __devinit early_uli5249(struct pci_dev *dev) | 63 | static void __devinit early_uli5249(struct pci_dev *dev) |
| 56 | { | 64 | { |
| 57 | unsigned char temp; | 65 | unsigned char temp; |
| 58 | 66 | ||
| 59 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && | 67 | if (!is_quirk_valid()) |
| 60 | !machine_is(mpc8572_ds)) | ||
| 61 | return; | 68 | return; |
| 62 | 69 | ||
| 63 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | | 70 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | |
| @@ -80,8 +87,7 @@ static void __devinit quirk_uli1575(struct pci_dev *dev) | |||
| 80 | { | 87 | { |
| 81 | int i; | 88 | int i; |
| 82 | 89 | ||
| 83 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && | 90 | if (!is_quirk_valid()) |
| 84 | !machine_is(mpc8572_ds)) | ||
| 85 | return; | 91 | return; |
| 86 | 92 | ||
| 87 | /* | 93 | /* |
| @@ -149,8 +155,7 @@ static void __devinit quirk_final_uli1575(struct pci_dev *dev) | |||
| 149 | * IRQ 14: Edge | 155 | * IRQ 14: Edge |
| 150 | * IRQ 15: Edge | 156 | * IRQ 15: Edge |
| 151 | */ | 157 | */ |
| 152 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && | 158 | if (!is_quirk_valid()) |
| 153 | !machine_is(mpc8572_ds)) | ||
| 154 | return; | 159 | return; |
| 155 | 160 | ||
| 156 | outb(0xfa, 0x4d0); | 161 | outb(0xfa, 0x4d0); |
| @@ -176,8 +181,7 @@ static void __devinit quirk_uli5288(struct pci_dev *dev) | |||
| 176 | unsigned char c; | 181 | unsigned char c; |
| 177 | unsigned int d; | 182 | unsigned int d; |
| 178 | 183 | ||
| 179 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && | 184 | if (!is_quirk_valid()) |
| 180 | !machine_is(mpc8572_ds)) | ||
| 181 | return; | 185 | return; |
| 182 | 186 | ||
| 183 | /* read/write lock */ | 187 | /* read/write lock */ |
| @@ -201,8 +205,7 @@ static void __devinit quirk_uli5229(struct pci_dev *dev) | |||
| 201 | { | 205 | { |
| 202 | unsigned short temp; | 206 | unsigned short temp; |
| 203 | 207 | ||
| 204 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && | 208 | if (!is_quirk_valid()) |
| 205 | !machine_is(mpc8572_ds)) | ||
| 206 | return; | 209 | return; |
| 207 | 210 | ||
| 208 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | | 211 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | |
| @@ -270,7 +273,6 @@ static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev) | |||
| 270 | static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev) | 273 | static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev) |
| 271 | { | 274 | { |
| 272 | unsigned char c; | 275 | unsigned char c; |
| 273 | unsigned short temp; | ||
| 274 | 276 | ||
| 275 | if (!machine_is(mpc86xx_hpcd)) | 277 | if (!machine_is(mpc86xx_hpcd)) |
| 276 | return; | 278 | return; |
diff --git a/arch/powerpc/platforms/iseries/dt.c b/arch/powerpc/platforms/iseries/dt.c index 4543c4bc3a56..c5a87a72057b 100644 --- a/arch/powerpc/platforms/iseries/dt.c +++ b/arch/powerpc/platforms/iseries/dt.c | |||
| @@ -204,7 +204,8 @@ static void __init dt_prop_u32(struct iseries_flat_dt *dt, const char *name, | |||
| 204 | dt_prop(dt, name, &data, sizeof(u32)); | 204 | dt_prop(dt, name, &data, sizeof(u32)); |
| 205 | } | 205 | } |
| 206 | 206 | ||
| 207 | static void __init dt_prop_u64(struct iseries_flat_dt *dt, const char *name, | 207 | static void __init __maybe_unused dt_prop_u64(struct iseries_flat_dt *dt, |
| 208 | const char *name, | ||
| 208 | u64 data) | 209 | u64 data) |
| 209 | { | 210 | { |
| 210 | dt_prop(dt, name, &data, sizeof(u64)); | 211 | dt_prop(dt, name, &data, sizeof(u64)); |
diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c index 40219823d9b0..6c1e1011959e 100644 --- a/arch/powerpc/platforms/iseries/iommu.c +++ b/arch/powerpc/platforms/iseries/iommu.c | |||
| @@ -177,7 +177,7 @@ static struct iommu_table *iommu_table_find(struct iommu_table * tbl) | |||
| 177 | static void pci_dma_dev_setup_iseries(struct pci_dev *pdev) | 177 | static void pci_dma_dev_setup_iseries(struct pci_dev *pdev) |
| 178 | { | 178 | { |
| 179 | struct iommu_table *tbl; | 179 | struct iommu_table *tbl; |
| 180 | struct device_node *dn = pdev->sysdata; | 180 | struct device_node *dn = pci_device_to_OF_node(pdev); |
| 181 | struct pci_dn *pdn = PCI_DN(dn); | 181 | struct pci_dn *pdn = PCI_DN(dn); |
| 182 | const u32 *lsn = of_get_property(dn, "linux,logical-slot-number", NULL); | 182 | const u32 *lsn = of_get_property(dn, "linux,logical-slot-number", NULL); |
| 183 | 183 | ||
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c index 3689c2413d24..fef4d5150517 100644 --- a/arch/powerpc/platforms/iseries/mf.c +++ b/arch/powerpc/platforms/iseries/mf.c | |||
| @@ -267,7 +267,8 @@ static struct pending_event *new_pending_event(void) | |||
| 267 | return ev; | 267 | return ev; |
| 268 | } | 268 | } |
| 269 | 269 | ||
| 270 | static int signal_vsp_instruction(struct vsp_cmd_data *vsp_cmd) | 270 | static int __maybe_unused |
| 271 | signal_vsp_instruction(struct vsp_cmd_data *vsp_cmd) | ||
| 271 | { | 272 | { |
| 272 | struct pending_event *ev = new_pending_event(); | 273 | struct pending_event *ev = new_pending_event(); |
| 273 | int rc; | 274 | int rc; |
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c index 21cddc30220b..175aac8ca7e5 100644 --- a/arch/powerpc/platforms/iseries/pci.c +++ b/arch/powerpc/platforms/iseries/pci.c | |||
| @@ -318,6 +318,7 @@ static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |||
| 318 | { | 318 | { |
| 319 | struct resource *bar_res = &dev->resource[bar_num]; | 319 | struct resource *bar_res = &dev->resource[bar_num]; |
| 320 | long bar_size = pci_resource_len(dev, bar_num); | 320 | long bar_size = pci_resource_len(dev, bar_num); |
| 321 | struct device_node *dn = pci_device_to_OF_node(dev); | ||
| 321 | 322 | ||
| 322 | /* | 323 | /* |
| 323 | * No space to allocate, quick exit, skip Allocation. | 324 | * No space to allocate, quick exit, skip Allocation. |
| @@ -335,9 +336,9 @@ static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |||
| 335 | * Allocate the number of table entries needed for BAR. | 336 | * Allocate the number of table entries needed for BAR. |
| 336 | */ | 337 | */ |
| 337 | while (bar_size > 0 ) { | 338 | while (bar_size > 0 ) { |
| 338 | iomm_table[current_iomm_table_entry] = dev->sysdata; | 339 | iomm_table[current_iomm_table_entry] = dn; |
| 339 | ds_addr_table[current_iomm_table_entry] = | 340 | ds_addr_table[current_iomm_table_entry] = |
| 340 | iseries_ds_addr(dev->sysdata) | (bar_num << 24); | 341 | iseries_ds_addr(dn) | (bar_num << 24); |
| 341 | bar_size -= IOMM_TABLE_ENTRY_SIZE; | 342 | bar_size -= IOMM_TABLE_ENTRY_SIZE; |
| 342 | ++current_iomm_table_entry; | 343 | ++current_iomm_table_entry; |
| 343 | } | 344 | } |
| @@ -410,7 +411,7 @@ void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev) | |||
| 410 | struct device_node *node; | 411 | struct device_node *node; |
| 411 | int i; | 412 | int i; |
| 412 | 413 | ||
| 413 | node = find_device_node(bus, pdev->devfn); | 414 | node = pci_device_to_OF_node(pdev); |
| 414 | pr_debug("PCI: iSeries %s, pdev %p, node %p\n", | 415 | pr_debug("PCI: iSeries %s, pdev %p, node %p\n", |
| 415 | pci_name(pdev), pdev, node); | 416 | pci_name(pdev), pdev, node); |
| 416 | if (!node) { | 417 | if (!node) { |
| @@ -441,7 +442,6 @@ void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev) | |||
| 441 | } | 442 | } |
| 442 | } | 443 | } |
| 443 | 444 | ||
| 444 | pdev->sysdata = node; | ||
| 445 | allocate_device_bars(pdev); | 445 | allocate_device_bars(pdev); |
| 446 | iseries_device_information(pdev, bus, *sub_bus); | 446 | iseries_device_information(pdev, bus, *sub_bus); |
| 447 | } | 447 | } |
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c index bfd60e4accee..0636a3df6978 100644 --- a/arch/powerpc/platforms/maple/setup.c +++ b/arch/powerpc/platforms/maple/setup.c | |||
| @@ -335,3 +335,62 @@ define_machine(maple) { | |||
| 335 | .progress = maple_progress, | 335 | .progress = maple_progress, |
| 336 | .power_save = power4_idle, | 336 | .power_save = power4_idle, |
| 337 | }; | 337 | }; |
| 338 | |||
| 339 | #ifdef CONFIG_EDAC | ||
| 340 | /* | ||
| 341 | * Register a platform device for CPC925 memory controller on | ||
| 342 | * Motorola ATCA-6101 blade. | ||
| 343 | */ | ||
| 344 | #define MAPLE_CPC925_MODEL "Motorola,ATCA-6101" | ||
| 345 | static int __init maple_cpc925_edac_setup(void) | ||
| 346 | { | ||
| 347 | struct platform_device *pdev; | ||
| 348 | struct device_node *np = NULL; | ||
| 349 | struct resource r; | ||
| 350 | const unsigned char *model; | ||
| 351 | int ret; | ||
| 352 | |||
| 353 | np = of_find_node_by_path("/"); | ||
| 354 | if (!np) { | ||
| 355 | printk(KERN_ERR "%s: Unable to get root node\n", __func__); | ||
| 356 | return -ENODEV; | ||
| 357 | } | ||
| 358 | |||
| 359 | model = (const unsigned char *)of_get_property(np, "model", NULL); | ||
| 360 | if (!model) { | ||
| 361 | printk(KERN_ERR "%s: Unabel to get model info\n", __func__); | ||
| 362 | return -ENODEV; | ||
| 363 | } | ||
| 364 | |||
| 365 | ret = strcmp(model, MAPLE_CPC925_MODEL); | ||
| 366 | of_node_put(np); | ||
| 367 | |||
| 368 | if (ret != 0) | ||
| 369 | return 0; | ||
| 370 | |||
| 371 | np = of_find_node_by_type(NULL, "memory-controller"); | ||
| 372 | if (!np) { | ||
| 373 | printk(KERN_ERR "%s: Unable to find memory-controller node\n", | ||
| 374 | __func__); | ||
| 375 | return -ENODEV; | ||
| 376 | } | ||
| 377 | |||
| 378 | ret = of_address_to_resource(np, 0, &r); | ||
| 379 | of_node_put(np); | ||
| 380 | |||
| 381 | if (ret < 0) { | ||
| 382 | printk(KERN_ERR "%s: Unable to get memory-controller reg\n", | ||
| 383 | __func__); | ||
| 384 | return -ENODEV; | ||
| 385 | } | ||
| 386 | |||
| 387 | pdev = platform_device_register_simple("cpc925_edac", 0, &r, 1); | ||
| 388 | if (IS_ERR(pdev)) | ||
| 389 | return PTR_ERR(pdev); | ||
| 390 | |||
| 391 | printk(KERN_INFO "%s: CPC925 platform device created\n", __func__); | ||
| 392 | |||
| 393 | return 0; | ||
| 394 | } | ||
| 395 | machine_device_initcall(maple, maple_cpc925_edac_setup); | ||
| 396 | #endif | ||
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c index 75cc165d5bee..3bf546797cbb 100644 --- a/arch/powerpc/platforms/pasemi/gpio_mdio.c +++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c | |||
| @@ -29,7 +29,7 @@ | |||
| 29 | #include <linux/ioport.h> | 29 | #include <linux/ioport.h> |
| 30 | #include <linux/interrupt.h> | 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/phy.h> | 31 | #include <linux/phy.h> |
| 32 | #include <linux/platform_device.h> | 32 | #include <linux/of_mdio.h> |
| 33 | #include <linux/of_platform.h> | 33 | #include <linux/of_platform.h> |
| 34 | 34 | ||
| 35 | #define DELAY 1 | 35 | #define DELAY 1 |
| @@ -39,6 +39,7 @@ static void __iomem *gpio_regs; | |||
| 39 | struct gpio_priv { | 39 | struct gpio_priv { |
| 40 | int mdc_pin; | 40 | int mdc_pin; |
| 41 | int mdio_pin; | 41 | int mdio_pin; |
| 42 | int mdio_irqs[PHY_MAX_ADDR]; | ||
| 42 | }; | 43 | }; |
| 43 | 44 | ||
| 44 | #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) | 45 | #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) |
| @@ -218,12 +219,11 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev, | |||
| 218 | const struct of_device_id *match) | 219 | const struct of_device_id *match) |
| 219 | { | 220 | { |
| 220 | struct device *dev = &ofdev->dev; | 221 | struct device *dev = &ofdev->dev; |
| 221 | struct device_node *phy_dn, *np = ofdev->node; | 222 | struct device_node *np = ofdev->node; |
| 222 | struct mii_bus *new_bus; | 223 | struct mii_bus *new_bus; |
| 223 | struct gpio_priv *priv; | 224 | struct gpio_priv *priv; |
| 224 | const unsigned int *prop; | 225 | const unsigned int *prop; |
| 225 | int err; | 226 | int err; |
| 226 | int i; | ||
| 227 | 227 | ||
| 228 | err = -ENOMEM; | 228 | err = -ENOMEM; |
| 229 | priv = kzalloc(sizeof(struct gpio_priv), GFP_KERNEL); | 229 | priv = kzalloc(sizeof(struct gpio_priv), GFP_KERNEL); |
| @@ -244,27 +244,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev, | |||
| 244 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop); | 244 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop); |
| 245 | new_bus->priv = priv; | 245 | new_bus->priv = priv; |
| 246 | 246 | ||
| 247 | new_bus->phy_mask = 0; | 247 | new_bus->irq = priv->mdio_irqs; |
| 248 | |||
| 249 | new_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | ||
| 250 | |||
| 251 | if (!new_bus->irq) | ||
| 252 | goto out_free_bus; | ||
| 253 | |||
| 254 | for (i = 0; i < PHY_MAX_ADDR; i++) | ||
| 255 | new_bus->irq[i] = NO_IRQ; | ||
| 256 | |||
| 257 | for (phy_dn = of_get_next_child(np, NULL); | ||
| 258 | phy_dn != NULL; | ||
| 259 | phy_dn = of_get_next_child(np, phy_dn)) { | ||
| 260 | const unsigned int *ip, *regp; | ||
| 261 | |||
| 262 | ip = of_get_property(phy_dn, "interrupts", NULL); | ||
| 263 | regp = of_get_property(phy_dn, "reg", NULL); | ||
| 264 | if (!ip || !regp || *regp >= PHY_MAX_ADDR) | ||
| 265 | continue; | ||
| 266 | new_bus->irq[*regp] = irq_create_mapping(NULL, *ip); | ||
| 267 | } | ||
| 268 | 248 | ||
| 269 | prop = of_get_property(np, "mdc-pin", NULL); | 249 | prop = of_get_property(np, "mdc-pin", NULL); |
| 270 | priv->mdc_pin = *prop; | 250 | priv->mdc_pin = *prop; |
| @@ -275,7 +255,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev, | |||
| 275 | new_bus->parent = dev; | 255 | new_bus->parent = dev; |
| 276 | dev_set_drvdata(dev, new_bus); | 256 | dev_set_drvdata(dev, new_bus); |
| 277 | 257 | ||
| 278 | err = mdiobus_register(new_bus); | 258 | err = of_mdiobus_register(new_bus, np); |
| 279 | 259 | ||
| 280 | if (err != 0) { | 260 | if (err != 0) { |
| 281 | printk(KERN_ERR "%s: Cannot register as MDIO bus, err %d\n", | 261 | printk(KERN_ERR "%s: Cannot register as MDIO bus, err %d\n", |
| @@ -286,8 +266,6 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev, | |||
| 286 | return 0; | 266 | return 0; |
| 287 | 267 | ||
| 288 | out_free_irq: | 268 | out_free_irq: |
| 289 | kfree(new_bus->irq); | ||
| 290 | out_free_bus: | ||
| 291 | kfree(new_bus); | 269 | kfree(new_bus); |
| 292 | out_free_priv: | 270 | out_free_priv: |
| 293 | kfree(priv); | 271 | kfree(priv); |
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 7039d8f1d3ba..dce736349107 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c | |||
| @@ -221,7 +221,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id) | |||
| 221 | continue; | 221 | continue; |
| 222 | irq += __ilog2(bits); | 222 | irq += __ilog2(bits); |
| 223 | spin_unlock_irqrestore(&pmac_pic_lock, flags); | 223 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
| 224 | __do_IRQ(irq); | 224 | generic_handle_irq(irq); |
| 225 | spin_lock_irqsave(&pmac_pic_lock, flags); | 225 | spin_lock_irqsave(&pmac_pic_lock, flags); |
| 226 | rc = IRQ_HANDLED; | 226 | rc = IRQ_HANDLED; |
| 227 | } | 227 | } |
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index 45936c9ed0ec..86f69a4eb49b 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c | |||
| @@ -655,7 +655,7 @@ static int __init pmac_probe(void) | |||
| 655 | /* Move that to pci.c */ | 655 | /* Move that to pci.c */ |
| 656 | static int pmac_pci_probe_mode(struct pci_bus *bus) | 656 | static int pmac_pci_probe_mode(struct pci_bus *bus) |
| 657 | { | 657 | { |
| 658 | struct device_node *node = bus->sysdata; | 658 | struct device_node *node = pci_bus_to_OF_node(bus); |
| 659 | 659 | ||
| 660 | /* We need to use normal PCI probing for the AGP bus, | 660 | /* We need to use normal PCI probing for the AGP bus, |
| 661 | * since the device for the AGP bridge isn't in the tree. | 661 | * since the device for the AGP bridge isn't in the tree. |
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c index 9a2b6d948610..846eb8b57fd1 100644 --- a/arch/powerpc/platforms/ps3/mm.c +++ b/arch/powerpc/platforms/ps3/mm.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <linux/lmb.h> | 24 | #include <linux/lmb.h> |
| 25 | 25 | ||
| 26 | #include <asm/firmware.h> | 26 | #include <asm/firmware.h> |
| 27 | #include <asm/iommu.h> | ||
| 27 | #include <asm/prom.h> | 28 | #include <asm/prom.h> |
| 28 | #include <asm/udbg.h> | 29 | #include <asm/udbg.h> |
| 29 | #include <asm/lv1call.h> | 30 | #include <asm/lv1call.h> |
| @@ -605,9 +606,8 @@ static int dma_ioc0_map_pages(struct ps3_dma_region *r, unsigned long phys_addr, | |||
| 605 | r->ioid, | 606 | r->ioid, |
| 606 | iopte_flag); | 607 | iopte_flag); |
| 607 | if (result) { | 608 | if (result) { |
| 608 | printk(KERN_WARNING "%s:%d: lv1_map_device_dma_region " | 609 | pr_warning("%s:%d: lv1_put_iopte failed: %s\n", |
| 609 | "failed: %s\n", __func__, __LINE__, | 610 | __func__, __LINE__, ps3_result(result)); |
| 610 | ps3_result(result)); | ||
| 611 | goto fail_map; | 611 | goto fail_map; |
| 612 | } | 612 | } |
| 613 | DBG("%s: pg=%d bus=%#lx, lpar=%#lx, ioid=%#x\n", __func__, | 613 | DBG("%s: pg=%d bus=%#lx, lpar=%#lx, ioid=%#x\n", __func__, |
| @@ -1001,7 +1001,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r) | |||
| 1001 | if (len > r->len) | 1001 | if (len > r->len) |
| 1002 | len = r->len; | 1002 | len = r->len; |
| 1003 | result = dma_sb_map_area(r, virt_addr, len, &tmp, | 1003 | result = dma_sb_map_area(r, virt_addr, len, &tmp, |
| 1004 | IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); | 1004 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW | |
| 1005 | CBE_IOPTE_M); | ||
| 1005 | BUG_ON(result); | 1006 | BUG_ON(result); |
| 1006 | } | 1007 | } |
| 1007 | 1008 | ||
| @@ -1014,7 +1015,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r) | |||
| 1014 | else | 1015 | else |
| 1015 | len -= map.rm.size - r->offset; | 1016 | len -= map.rm.size - r->offset; |
| 1016 | result = dma_sb_map_area(r, virt_addr, len, &tmp, | 1017 | result = dma_sb_map_area(r, virt_addr, len, &tmp, |
| 1017 | IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); | 1018 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW | |
| 1019 | CBE_IOPTE_M); | ||
| 1018 | BUG_ON(result); | 1020 | BUG_ON(result); |
| 1019 | } | 1021 | } |
| 1020 | 1022 | ||
diff --git a/arch/powerpc/platforms/ps3/os-area.c b/arch/powerpc/platforms/ps3/os-area.c index cf1cd0f8c18f..d6487a9c8019 100644 --- a/arch/powerpc/platforms/ps3/os-area.c +++ b/arch/powerpc/platforms/ps3/os-area.c | |||
| @@ -226,6 +226,44 @@ static struct property property_av_multi_out = { | |||
| 226 | .value = &saved_params.av_multi_out, | 226 | .value = &saved_params.av_multi_out, |
| 227 | }; | 227 | }; |
| 228 | 228 | ||
| 229 | |||
| 230 | static DEFINE_MUTEX(os_area_flash_mutex); | ||
| 231 | |||
| 232 | static const struct ps3_os_area_flash_ops *os_area_flash_ops; | ||
| 233 | |||
| 234 | void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops) | ||
| 235 | { | ||
| 236 | mutex_lock(&os_area_flash_mutex); | ||
| 237 | os_area_flash_ops = ops; | ||
| 238 | mutex_unlock(&os_area_flash_mutex); | ||
| 239 | } | ||
| 240 | EXPORT_SYMBOL_GPL(ps3_os_area_flash_register); | ||
| 241 | |||
| 242 | static ssize_t os_area_flash_read(void *buf, size_t count, loff_t pos) | ||
| 243 | { | ||
| 244 | ssize_t res = -ENODEV; | ||
| 245 | |||
| 246 | mutex_lock(&os_area_flash_mutex); | ||
| 247 | if (os_area_flash_ops) | ||
| 248 | res = os_area_flash_ops->read(buf, count, pos); | ||
| 249 | mutex_unlock(&os_area_flash_mutex); | ||
| 250 | |||
| 251 | return res; | ||
| 252 | } | ||
| 253 | |||
| 254 | static ssize_t os_area_flash_write(const void *buf, size_t count, loff_t pos) | ||
| 255 | { | ||
| 256 | ssize_t res = -ENODEV; | ||
| 257 | |||
| 258 | mutex_lock(&os_area_flash_mutex); | ||
| 259 | if (os_area_flash_ops) | ||
| 260 | res = os_area_flash_ops->write(buf, count, pos); | ||
| 261 | mutex_unlock(&os_area_flash_mutex); | ||
| 262 | |||
| 263 | return res; | ||
| 264 | } | ||
| 265 | |||
| 266 | |||
| 229 | /** | 267 | /** |
| 230 | * os_area_set_property - Add or overwrite a saved_params value to the device tree. | 268 | * os_area_set_property - Add or overwrite a saved_params value to the device tree. |
| 231 | * | 269 | * |
| @@ -352,12 +390,12 @@ static int db_verify(const struct os_area_db *db) | |||
| 352 | if (memcmp(db->magic_num, OS_AREA_DB_MAGIC_NUM, | 390 | if (memcmp(db->magic_num, OS_AREA_DB_MAGIC_NUM, |
| 353 | sizeof(db->magic_num))) { | 391 | sizeof(db->magic_num))) { |
| 354 | pr_debug("%s:%d magic_num failed\n", __func__, __LINE__); | 392 | pr_debug("%s:%d magic_num failed\n", __func__, __LINE__); |
| 355 | return -1; | 393 | return -EINVAL; |
| 356 | } | 394 | } |
| 357 | 395 | ||
| 358 | if (db->version != 1) { | 396 | if (db->version != 1) { |
| 359 | pr_debug("%s:%d version failed\n", __func__, __LINE__); | 397 | pr_debug("%s:%d version failed\n", __func__, __LINE__); |
| 360 | return -1; | 398 | return -EINVAL; |
| 361 | } | 399 | } |
| 362 | 400 | ||
| 363 | return 0; | 401 | return 0; |
| @@ -578,59 +616,48 @@ static void os_area_db_init(struct os_area_db *db) | |||
| 578 | * | 616 | * |
| 579 | */ | 617 | */ |
| 580 | 618 | ||
| 581 | static void __maybe_unused update_flash_db(void) | 619 | static int update_flash_db(void) |
| 582 | { | 620 | { |
| 583 | int result; | 621 | const unsigned int buf_len = 8 * OS_AREA_SEGMENT_SIZE; |
| 584 | int file; | 622 | struct os_area_header *header; |
| 585 | off_t offset; | ||
| 586 | ssize_t count; | 623 | ssize_t count; |
| 587 | static const unsigned int buf_len = 8 * OS_AREA_SEGMENT_SIZE; | 624 | int error; |
| 588 | const struct os_area_header *header; | 625 | loff_t pos; |
| 589 | struct os_area_db* db; | 626 | struct os_area_db* db; |
| 590 | 627 | ||
| 591 | /* Read in header and db from flash. */ | 628 | /* Read in header and db from flash. */ |
| 592 | 629 | ||
| 593 | file = sys_open("/dev/ps3flash", O_RDWR, 0); | ||
| 594 | |||
| 595 | if (file < 0) { | ||
| 596 | pr_debug("%s:%d sys_open failed\n", __func__, __LINE__); | ||
| 597 | goto fail_open; | ||
| 598 | } | ||
| 599 | |||
| 600 | header = kmalloc(buf_len, GFP_KERNEL); | 630 | header = kmalloc(buf_len, GFP_KERNEL); |
| 601 | |||
| 602 | if (!header) { | 631 | if (!header) { |
| 603 | pr_debug("%s:%d kmalloc failed\n", __func__, __LINE__); | 632 | pr_debug("%s: kmalloc failed\n", __func__); |
| 604 | goto fail_malloc; | 633 | return -ENOMEM; |
| 605 | } | 634 | } |
| 606 | 635 | ||
| 607 | offset = sys_lseek(file, 0, SEEK_SET); | 636 | count = os_area_flash_read(header, buf_len, 0); |
| 608 | 637 | if (count < 0) { | |
| 609 | if (offset != 0) { | 638 | pr_debug("%s: os_area_flash_read failed %zd\n", __func__, |
| 610 | pr_debug("%s:%d sys_lseek failed\n", __func__, __LINE__); | 639 | count); |
| 611 | goto fail_header_seek; | 640 | error = count; |
| 641 | goto fail; | ||
| 612 | } | 642 | } |
| 613 | 643 | ||
| 614 | count = sys_read(file, (char __user *)header, buf_len); | 644 | pos = header->db_area_offset * OS_AREA_SEGMENT_SIZE; |
| 615 | 645 | if (count < OS_AREA_SEGMENT_SIZE || verify_header(header) || | |
| 616 | result = count < OS_AREA_SEGMENT_SIZE || verify_header(header) | 646 | count < pos) { |
| 617 | || count < header->db_area_offset * OS_AREA_SEGMENT_SIZE; | 647 | pr_debug("%s: verify_header failed\n", __func__); |
| 618 | |||
| 619 | if (result) { | ||
| 620 | pr_debug("%s:%d verify_header failed\n", __func__, __LINE__); | ||
| 621 | dump_header(header); | 648 | dump_header(header); |
| 622 | goto fail_header; | 649 | error = -EINVAL; |
| 650 | goto fail; | ||
| 623 | } | 651 | } |
| 624 | 652 | ||
| 625 | /* Now got a good db offset and some maybe good db data. */ | 653 | /* Now got a good db offset and some maybe good db data. */ |
| 626 | 654 | ||
| 627 | db = (void*)header + header->db_area_offset * OS_AREA_SEGMENT_SIZE; | 655 | db = (void *)header + pos; |
| 628 | 656 | ||
| 629 | result = db_verify(db); | 657 | error = db_verify(db); |
| 630 | 658 | if (error) { | |
| 631 | if (result) { | 659 | pr_notice("%s: Verify of flash database failed, formatting.\n", |
| 632 | printk(KERN_NOTICE "%s:%d: Verify of flash database failed, " | 660 | __func__); |
| 633 | "formatting.\n", __func__, __LINE__); | ||
| 634 | dump_db(db); | 661 | dump_db(db); |
| 635 | os_area_db_init(db); | 662 | os_area_db_init(db); |
| 636 | } | 663 | } |
| @@ -639,29 +666,16 @@ static void __maybe_unused update_flash_db(void) | |||
| 639 | 666 | ||
| 640 | db_set_64(db, &os_area_db_id_rtc_diff, saved_params.rtc_diff); | 667 | db_set_64(db, &os_area_db_id_rtc_diff, saved_params.rtc_diff); |
| 641 | 668 | ||
| 642 | offset = sys_lseek(file, header->db_area_offset * OS_AREA_SEGMENT_SIZE, | 669 | count = os_area_flash_write(db, sizeof(struct os_area_db), pos); |
| 643 | SEEK_SET); | ||
| 644 | |||
| 645 | if (offset != header->db_area_offset * OS_AREA_SEGMENT_SIZE) { | ||
| 646 | pr_debug("%s:%d sys_lseek failed\n", __func__, __LINE__); | ||
| 647 | goto fail_db_seek; | ||
| 648 | } | ||
| 649 | |||
| 650 | count = sys_write(file, (const char __user *)db, | ||
| 651 | sizeof(struct os_area_db)); | ||
| 652 | |||
| 653 | if (count < sizeof(struct os_area_db)) { | 670 | if (count < sizeof(struct os_area_db)) { |
| 654 | pr_debug("%s:%d sys_write failed\n", __func__, __LINE__); | 671 | pr_debug("%s: os_area_flash_write failed %zd\n", __func__, |
| 672 | count); | ||
| 673 | error = count < 0 ? count : -EIO; | ||
| 655 | } | 674 | } |
| 656 | 675 | ||
| 657 | fail_db_seek: | 676 | fail: |
| 658 | fail_header: | ||
| 659 | fail_header_seek: | ||
| 660 | kfree(header); | 677 | kfree(header); |
| 661 | fail_malloc: | 678 | return error; |
| 662 | sys_close(file); | ||
| 663 | fail_open: | ||
| 664 | return; | ||
| 665 | } | 679 | } |
| 666 | 680 | ||
| 667 | /** | 681 | /** |
| @@ -674,11 +688,11 @@ fail_open: | |||
| 674 | static void os_area_queue_work_handler(struct work_struct *work) | 688 | static void os_area_queue_work_handler(struct work_struct *work) |
| 675 | { | 689 | { |
| 676 | struct device_node *node; | 690 | struct device_node *node; |
| 691 | int error; | ||
| 677 | 692 | ||
| 678 | pr_debug(" -> %s:%d\n", __func__, __LINE__); | 693 | pr_debug(" -> %s:%d\n", __func__, __LINE__); |
| 679 | 694 | ||
| 680 | node = of_find_node_by_path("/"); | 695 | node = of_find_node_by_path("/"); |
| 681 | |||
| 682 | if (node) { | 696 | if (node) { |
| 683 | os_area_set_property(node, &property_rtc_diff); | 697 | os_area_set_property(node, &property_rtc_diff); |
| 684 | of_node_put(node); | 698 | of_node_put(node); |
| @@ -686,12 +700,10 @@ static void os_area_queue_work_handler(struct work_struct *work) | |||
| 686 | pr_debug("%s:%d of_find_node_by_path failed\n", | 700 | pr_debug("%s:%d of_find_node_by_path failed\n", |
| 687 | __func__, __LINE__); | 701 | __func__, __LINE__); |
| 688 | 702 | ||
| 689 | #if defined(CONFIG_PS3_FLASH) || defined(CONFIG_PS3_FLASH_MODULE) | 703 | error = update_flash_db(); |
| 690 | update_flash_db(); | 704 | if (error) |
| 691 | #else | 705 | pr_warning("%s: Could not update FLASH ROM\n", __func__); |
| 692 | printk(KERN_WARNING "%s:%d: No flash rom driver configured.\n", | 706 | |
| 693 | __func__, __LINE__); | ||
| 694 | #endif | ||
| 695 | pr_debug(" <- %s:%d\n", __func__, __LINE__); | 707 | pr_debug(" <- %s:%d\n", __func__, __LINE__); |
| 696 | } | 708 | } |
| 697 | 709 | ||
| @@ -808,7 +820,7 @@ u64 ps3_os_area_get_rtc_diff(void) | |||
| 808 | { | 820 | { |
| 809 | return saved_params.rtc_diff; | 821 | return saved_params.rtc_diff; |
| 810 | } | 822 | } |
| 811 | EXPORT_SYMBOL(ps3_os_area_get_rtc_diff); | 823 | EXPORT_SYMBOL_GPL(ps3_os_area_get_rtc_diff); |
| 812 | 824 | ||
| 813 | /** | 825 | /** |
| 814 | * ps3_os_area_set_rtc_diff - Set the rtc diff value. | 826 | * ps3_os_area_set_rtc_diff - Set the rtc diff value. |
| @@ -824,7 +836,7 @@ void ps3_os_area_set_rtc_diff(u64 rtc_diff) | |||
| 824 | os_area_queue_work(); | 836 | os_area_queue_work(); |
| 825 | } | 837 | } |
| 826 | } | 838 | } |
| 827 | EXPORT_SYMBOL(ps3_os_area_set_rtc_diff); | 839 | EXPORT_SYMBOL_GPL(ps3_os_area_set_rtc_diff); |
| 828 | 840 | ||
| 829 | /** | 841 | /** |
| 830 | * ps3_os_area_get_av_multi_out - Returns the default video mode. | 842 | * ps3_os_area_get_av_multi_out - Returns the default video mode. |
diff --git a/arch/powerpc/platforms/ps3/platform.h b/arch/powerpc/platforms/ps3/platform.h index 136aa0637d9c..9a196a88eda7 100644 --- a/arch/powerpc/platforms/ps3/platform.h +++ b/arch/powerpc/platforms/ps3/platform.h | |||
| @@ -232,14 +232,4 @@ int ps3_repository_read_spu_resource_id(unsigned int res_index, | |||
| 232 | int ps3_repository_read_vuart_av_port(unsigned int *port); | 232 | int ps3_repository_read_vuart_av_port(unsigned int *port); |
| 233 | int ps3_repository_read_vuart_sysmgr_port(unsigned int *port); | 233 | int ps3_repository_read_vuart_sysmgr_port(unsigned int *port); |
| 234 | 234 | ||
| 235 | /* Page table entries */ | ||
| 236 | #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ | ||
| 237 | #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ | ||
| 238 | #define IOPTE_M 0x2000000000000000ul /* coherency required */ | ||
| 239 | #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ | ||
| 240 | #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ | ||
| 241 | #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ | ||
| 242 | #define IOPTE_H 0x0000000000000800ul /* cache hint */ | ||
| 243 | #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ | ||
| 244 | |||
| 245 | #endif | 235 | #endif |
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c index 1a7b5ae0c83e..149bea2ce583 100644 --- a/arch/powerpc/platforms/ps3/setup.c +++ b/arch/powerpc/platforms/ps3/setup.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <asm/udbg.h> | 32 | #include <asm/udbg.h> |
| 33 | #include <asm/prom.h> | 33 | #include <asm/prom.h> |
| 34 | #include <asm/lv1call.h> | 34 | #include <asm/lv1call.h> |
| 35 | #include <asm/ps3gpu.h> | ||
| 35 | 36 | ||
| 36 | #include "platform.h" | 37 | #include "platform.h" |
| 37 | 38 | ||
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c index a0927a3bacb7..f6e04bcc70ef 100644 --- a/arch/powerpc/platforms/ps3/smp.c +++ b/arch/powerpc/platforms/ps3/smp.c | |||
| @@ -32,12 +32,6 @@ | |||
| 32 | #define DBG pr_debug | 32 | #define DBG pr_debug |
| 33 | #endif | 33 | #endif |
| 34 | 34 | ||
| 35 | static irqreturn_t ipi_function_handler(int irq, void *msg) | ||
| 36 | { | ||
| 37 | smp_message_recv((int)(long)msg); | ||
| 38 | return IRQ_HANDLED; | ||
| 39 | } | ||
| 40 | |||
| 41 | /** | 35 | /** |
| 42 | * ps3_ipi_virqs - a per cpu array of virqs for ipi use | 36 | * ps3_ipi_virqs - a per cpu array of virqs for ipi use |
| 43 | */ | 37 | */ |
| @@ -45,13 +39,6 @@ static irqreturn_t ipi_function_handler(int irq, void *msg) | |||
| 45 | #define MSG_COUNT 4 | 39 | #define MSG_COUNT 4 |
| 46 | static DEFINE_PER_CPU(unsigned int, ps3_ipi_virqs[MSG_COUNT]); | 40 | static DEFINE_PER_CPU(unsigned int, ps3_ipi_virqs[MSG_COUNT]); |
| 47 | 41 | ||
| 48 | static const char *names[MSG_COUNT] = { | ||
| 49 | "ipi call", | ||
| 50 | "ipi reschedule", | ||
| 51 | "ipi migrate", | ||
| 52 | "ipi debug brk" | ||
| 53 | }; | ||
| 54 | |||
| 55 | static void do_message_pass(int target, int msg) | 42 | static void do_message_pass(int target, int msg) |
| 56 | { | 43 | { |
| 57 | int result; | 44 | int result; |
| @@ -119,8 +106,7 @@ static void __init ps3_smp_setup_cpu(int cpu) | |||
| 119 | DBG("%s:%d: (%d, %d) => virq %u\n", | 106 | DBG("%s:%d: (%d, %d) => virq %u\n", |
| 120 | __func__, __LINE__, cpu, i, virqs[i]); | 107 | __func__, __LINE__, cpu, i, virqs[i]); |
| 121 | 108 | ||
| 122 | result = request_irq(virqs[i], ipi_function_handler, | 109 | result = smp_request_message_ipi(virqs[i], i); |
| 123 | IRQF_DISABLED, names[i], (void*)(long)i); | ||
| 124 | 110 | ||
| 125 | if (result) | 111 | if (result) |
| 126 | virqs[i] = NO_IRQ; | 112 | virqs[i] = NO_IRQ; |
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index 9a73d0238639..9fead0faf38b 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/udbg.h> | 27 | #include <asm/udbg.h> |
| 28 | #include <asm/lv1call.h> | 28 | #include <asm/lv1call.h> |
| 29 | #include <asm/firmware.h> | 29 | #include <asm/firmware.h> |
| 30 | #include <asm/iommu.h> | ||
| 30 | 31 | ||
| 31 | #include "platform.h" | 32 | #include "platform.h" |
| 32 | 33 | ||
| @@ -531,7 +532,8 @@ static void * ps3_alloc_coherent(struct device *_dev, size_t size, | |||
| 531 | } | 532 | } |
| 532 | 533 | ||
| 533 | result = ps3_dma_map(dev->d_region, virt_addr, size, dma_handle, | 534 | result = ps3_dma_map(dev->d_region, virt_addr, size, dma_handle, |
| 534 | IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); | 535 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | |
| 536 | CBE_IOPTE_SO_RW | CBE_IOPTE_M); | ||
| 535 | 537 | ||
| 536 | if (result) { | 538 | if (result) { |
| 537 | pr_debug("%s:%d: ps3_dma_map failed (%d)\n", | 539 | pr_debug("%s:%d: ps3_dma_map failed (%d)\n", |
| @@ -575,7 +577,8 @@ static dma_addr_t ps3_sb_map_page(struct device *_dev, struct page *page, | |||
| 575 | 577 | ||
| 576 | result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size, | 578 | result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size, |
| 577 | &bus_addr, | 579 | &bus_addr, |
| 578 | IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW | IOPTE_M); | 580 | CBE_IOPTE_PP_R | CBE_IOPTE_PP_W | |
| 581 | CBE_IOPTE_SO_RW | CBE_IOPTE_M); | ||
| 579 | 582 | ||
| 580 | if (result) { | 583 | if (result) { |
| 581 | pr_debug("%s:%d: ps3_dma_map failed (%d)\n", | 584 | pr_debug("%s:%d: ps3_dma_map failed (%d)\n", |
| @@ -596,16 +599,16 @@ static dma_addr_t ps3_ioc0_map_page(struct device *_dev, struct page *page, | |||
| 596 | u64 iopte_flag; | 599 | u64 iopte_flag; |
| 597 | void *ptr = page_address(page) + offset; | 600 | void *ptr = page_address(page) + offset; |
| 598 | 601 | ||
| 599 | iopte_flag = IOPTE_M; | 602 | iopte_flag = CBE_IOPTE_M; |
| 600 | switch (direction) { | 603 | switch (direction) { |
| 601 | case DMA_BIDIRECTIONAL: | 604 | case DMA_BIDIRECTIONAL: |
| 602 | iopte_flag |= IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW; | 605 | iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW; |
| 603 | break; | 606 | break; |
| 604 | case DMA_TO_DEVICE: | 607 | case DMA_TO_DEVICE: |
| 605 | iopte_flag |= IOPTE_PP_R | IOPTE_SO_R; | 608 | iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_SO_R; |
| 606 | break; | 609 | break; |
| 607 | case DMA_FROM_DEVICE: | 610 | case DMA_FROM_DEVICE: |
| 608 | iopte_flag |= IOPTE_PP_W | IOPTE_SO_RW; | 611 | iopte_flag |= CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW; |
| 609 | break; | 612 | break; |
| 610 | default: | 613 | default: |
| 611 | /* not happned */ | 614 | /* not happned */ |
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c index 9a2a6e32f00f..0e8db6771252 100644 --- a/arch/powerpc/platforms/pseries/eeh_driver.c +++ b/arch/powerpc/platforms/pseries/eeh_driver.c | |||
| @@ -122,7 +122,7 @@ static void eeh_enable_irq(struct pci_dev *dev) | |||
| 122 | * passed back in "userdata". | 122 | * passed back in "userdata". |
| 123 | */ | 123 | */ |
| 124 | 124 | ||
| 125 | static void eeh_report_error(struct pci_dev *dev, void *userdata) | 125 | static int eeh_report_error(struct pci_dev *dev, void *userdata) |
| 126 | { | 126 | { |
| 127 | enum pci_ers_result rc, *res = userdata; | 127 | enum pci_ers_result rc, *res = userdata; |
| 128 | struct pci_driver *driver = dev->driver; | 128 | struct pci_driver *driver = dev->driver; |
| @@ -130,19 +130,21 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) | |||
| 130 | dev->error_state = pci_channel_io_frozen; | 130 | dev->error_state = pci_channel_io_frozen; |
| 131 | 131 | ||
| 132 | if (!driver) | 132 | if (!driver) |
| 133 | return; | 133 | return 0; |
| 134 | 134 | ||
| 135 | eeh_disable_irq(dev); | 135 | eeh_disable_irq(dev); |
| 136 | 136 | ||
| 137 | if (!driver->err_handler || | 137 | if (!driver->err_handler || |
| 138 | !driver->err_handler->error_detected) | 138 | !driver->err_handler->error_detected) |
| 139 | return; | 139 | return 0; |
| 140 | 140 | ||
| 141 | rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); | 141 | rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); |
| 142 | 142 | ||
| 143 | /* A driver that needs a reset trumps all others */ | 143 | /* A driver that needs a reset trumps all others */ |
| 144 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 144 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 145 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; | 145 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; |
| 146 | |||
| 147 | return 0; | ||
| 146 | } | 148 | } |
| 147 | 149 | ||
| 148 | /** | 150 | /** |
| @@ -153,7 +155,7 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) | |||
| 153 | * Cumulative response passed back in "userdata". | 155 | * Cumulative response passed back in "userdata". |
| 154 | */ | 156 | */ |
| 155 | 157 | ||
| 156 | static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) | 158 | static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) |
| 157 | { | 159 | { |
| 158 | enum pci_ers_result rc, *res = userdata; | 160 | enum pci_ers_result rc, *res = userdata; |
| 159 | struct pci_driver *driver = dev->driver; | 161 | struct pci_driver *driver = dev->driver; |
| @@ -161,26 +163,28 @@ static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) | |||
| 161 | if (!driver || | 163 | if (!driver || |
| 162 | !driver->err_handler || | 164 | !driver->err_handler || |
| 163 | !driver->err_handler->mmio_enabled) | 165 | !driver->err_handler->mmio_enabled) |
| 164 | return; | 166 | return 0; |
| 165 | 167 | ||
| 166 | rc = driver->err_handler->mmio_enabled (dev); | 168 | rc = driver->err_handler->mmio_enabled (dev); |
| 167 | 169 | ||
| 168 | /* A driver that needs a reset trumps all others */ | 170 | /* A driver that needs a reset trumps all others */ |
| 169 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 171 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 170 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; | 172 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; |
| 173 | |||
| 174 | return 0; | ||
| 171 | } | 175 | } |
| 172 | 176 | ||
| 173 | /** | 177 | /** |
| 174 | * eeh_report_reset - tell device that slot has been reset | 178 | * eeh_report_reset - tell device that slot has been reset |
| 175 | */ | 179 | */ |
| 176 | 180 | ||
| 177 | static void eeh_report_reset(struct pci_dev *dev, void *userdata) | 181 | static int eeh_report_reset(struct pci_dev *dev, void *userdata) |
| 178 | { | 182 | { |
| 179 | enum pci_ers_result rc, *res = userdata; | 183 | enum pci_ers_result rc, *res = userdata; |
| 180 | struct pci_driver *driver = dev->driver; | 184 | struct pci_driver *driver = dev->driver; |
| 181 | 185 | ||
| 182 | if (!driver) | 186 | if (!driver) |
| 183 | return; | 187 | return 0; |
| 184 | 188 | ||
| 185 | dev->error_state = pci_channel_io_normal; | 189 | dev->error_state = pci_channel_io_normal; |
| 186 | 190 | ||
| @@ -188,35 +192,39 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata) | |||
| 188 | 192 | ||
| 189 | if (!driver->err_handler || | 193 | if (!driver->err_handler || |
| 190 | !driver->err_handler->slot_reset) | 194 | !driver->err_handler->slot_reset) |
| 191 | return; | 195 | return 0; |
| 192 | 196 | ||
| 193 | rc = driver->err_handler->slot_reset(dev); | 197 | rc = driver->err_handler->slot_reset(dev); |
| 194 | if ((*res == PCI_ERS_RESULT_NONE) || | 198 | if ((*res == PCI_ERS_RESULT_NONE) || |
| 195 | (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; | 199 | (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; |
| 196 | if (*res == PCI_ERS_RESULT_DISCONNECT && | 200 | if (*res == PCI_ERS_RESULT_DISCONNECT && |
| 197 | rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 201 | rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 202 | |||
| 203 | return 0; | ||
| 198 | } | 204 | } |
| 199 | 205 | ||
| 200 | /** | 206 | /** |
| 201 | * eeh_report_resume - tell device to resume normal operations | 207 | * eeh_report_resume - tell device to resume normal operations |
| 202 | */ | 208 | */ |
| 203 | 209 | ||
| 204 | static void eeh_report_resume(struct pci_dev *dev, void *userdata) | 210 | static int eeh_report_resume(struct pci_dev *dev, void *userdata) |
| 205 | { | 211 | { |
| 206 | struct pci_driver *driver = dev->driver; | 212 | struct pci_driver *driver = dev->driver; |
| 207 | 213 | ||
| 208 | dev->error_state = pci_channel_io_normal; | 214 | dev->error_state = pci_channel_io_normal; |
| 209 | 215 | ||
| 210 | if (!driver) | 216 | if (!driver) |
| 211 | return; | 217 | return 0; |
| 212 | 218 | ||
| 213 | eeh_enable_irq(dev); | 219 | eeh_enable_irq(dev); |
| 214 | 220 | ||
| 215 | if (!driver->err_handler || | 221 | if (!driver->err_handler || |
| 216 | !driver->err_handler->resume) | 222 | !driver->err_handler->resume) |
| 217 | return; | 223 | return 0; |
| 218 | 224 | ||
| 219 | driver->err_handler->resume(dev); | 225 | driver->err_handler->resume(dev); |
| 226 | |||
| 227 | return 0; | ||
| 220 | } | 228 | } |
| 221 | 229 | ||
| 222 | /** | 230 | /** |
| @@ -226,22 +234,24 @@ static void eeh_report_resume(struct pci_dev *dev, void *userdata) | |||
| 226 | * dead, and that no further recovery attempts will be made on it. | 234 | * dead, and that no further recovery attempts will be made on it. |
| 227 | */ | 235 | */ |
| 228 | 236 | ||
| 229 | static void eeh_report_failure(struct pci_dev *dev, void *userdata) | 237 | static int eeh_report_failure(struct pci_dev *dev, void *userdata) |
| 230 | { | 238 | { |
| 231 | struct pci_driver *driver = dev->driver; | 239 | struct pci_driver *driver = dev->driver; |
| 232 | 240 | ||
| 233 | dev->error_state = pci_channel_io_perm_failure; | 241 | dev->error_state = pci_channel_io_perm_failure; |
| 234 | 242 | ||
| 235 | if (!driver) | 243 | if (!driver) |
| 236 | return; | 244 | return 0; |
| 237 | 245 | ||
| 238 | eeh_disable_irq(dev); | 246 | eeh_disable_irq(dev); |
| 239 | 247 | ||
| 240 | if (!driver->err_handler || | 248 | if (!driver->err_handler || |
| 241 | !driver->err_handler->error_detected) | 249 | !driver->err_handler->error_detected) |
| 242 | return; | 250 | return 0; |
| 243 | 251 | ||
| 244 | driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); | 252 | driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); |
| 253 | |||
| 254 | return 0; | ||
| 245 | } | 255 | } |
| 246 | 256 | ||
| 247 | /* ------------------------------------------------------- */ | 257 | /* ------------------------------------------------------- */ |
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 3ee01b4f4257..661c8e02bcba 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c | |||
| @@ -388,7 +388,7 @@ static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) | |||
| 388 | 388 | ||
| 389 | while (pci->phb->dma_window_size * children > 0x80000000ul) | 389 | while (pci->phb->dma_window_size * children > 0x80000000ul) |
| 390 | pci->phb->dma_window_size >>= 1; | 390 | pci->phb->dma_window_size >>= 1; |
| 391 | pr_debug("No ISA/IDE, window size is 0x%lx\n", | 391 | pr_debug("No ISA/IDE, window size is 0x%llx\n", |
| 392 | pci->phb->dma_window_size); | 392 | pci->phb->dma_window_size); |
| 393 | pci->phb->dma_window_base_cur = 0; | 393 | pci->phb->dma_window_base_cur = 0; |
| 394 | 394 | ||
| @@ -414,7 +414,7 @@ static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) | |||
| 414 | while (pci->phb->dma_window_size * children > 0x70000000ul) | 414 | while (pci->phb->dma_window_size * children > 0x70000000ul) |
| 415 | pci->phb->dma_window_size >>= 1; | 415 | pci->phb->dma_window_size >>= 1; |
| 416 | 416 | ||
| 417 | pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); | 417 | pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); |
| 418 | } | 418 | } |
| 419 | 419 | ||
| 420 | 420 | ||
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c index 52a80e5840e8..e3139fa5e556 100644 --- a/arch/powerpc/platforms/pseries/lpar.c +++ b/arch/powerpc/platforms/pseries/lpar.c | |||
| @@ -609,3 +609,55 @@ void __init hpte_init_lpar(void) | |||
| 609 | ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range; | 609 | ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range; |
| 610 | ppc_md.hpte_clear_all = pSeries_lpar_hptab_clear; | 610 | ppc_md.hpte_clear_all = pSeries_lpar_hptab_clear; |
| 611 | } | 611 | } |
| 612 | |||
| 613 | #ifdef CONFIG_PPC_SMLPAR | ||
| 614 | #define CMO_FREE_HINT_DEFAULT 1 | ||
| 615 | static int cmo_free_hint_flag = CMO_FREE_HINT_DEFAULT; | ||
| 616 | |||
| 617 | static int __init cmo_free_hint(char *str) | ||
| 618 | { | ||
| 619 | char *parm; | ||
| 620 | parm = strstrip(str); | ||
| 621 | |||
| 622 | if (strcasecmp(parm, "no") == 0 || strcasecmp(parm, "off") == 0) { | ||
| 623 | printk(KERN_INFO "cmo_free_hint: CMO free page hinting is not active.\n"); | ||
| 624 | cmo_free_hint_flag = 0; | ||
| 625 | return 1; | ||
| 626 | } | ||
| 627 | |||
| 628 | cmo_free_hint_flag = 1; | ||
| 629 | printk(KERN_INFO "cmo_free_hint: CMO free page hinting is active.\n"); | ||
| 630 | |||
| 631 | if (strcasecmp(parm, "yes") == 0 || strcasecmp(parm, "on") == 0) | ||
| 632 | return 1; | ||
| 633 | |||
| 634 | return 0; | ||
| 635 | } | ||
| 636 | |||
| 637 | __setup("cmo_free_hint=", cmo_free_hint); | ||
| 638 | |||
| 639 | static void pSeries_set_page_state(struct page *page, int order, | ||
| 640 | unsigned long state) | ||
| 641 | { | ||
| 642 | int i, j; | ||
| 643 | unsigned long cmo_page_sz, addr; | ||
| 644 | |||
| 645 | cmo_page_sz = cmo_get_page_size(); | ||
| 646 | addr = __pa((unsigned long)page_address(page)); | ||
| 647 | |||
| 648 | for (i = 0; i < (1 << order); i++, addr += PAGE_SIZE) { | ||
| 649 | for (j = 0; j < PAGE_SIZE; j += cmo_page_sz) | ||
| 650 | plpar_hcall_norets(H_PAGE_INIT, state, addr + j, 0); | ||
| 651 | } | ||
| 652 | } | ||
| 653 | |||
| 654 | void arch_free_page(struct page *page, int order) | ||
| 655 | { | ||
| 656 | if (!cmo_free_hint_flag || !firmware_has_feature(FW_FEATURE_CMO)) | ||
| 657 | return; | ||
| 658 | |||
| 659 | pSeries_set_page_state(page, order, H_PAGE_SET_UNUSED); | ||
| 660 | } | ||
| 661 | EXPORT_SYMBOL(arch_free_page); | ||
| 662 | |||
| 663 | #endif | ||
diff --git a/arch/powerpc/platforms/pseries/rtasd.c b/arch/powerpc/platforms/pseries/rtasd.c index afad9f5ac0ac..b3cbac855924 100644 --- a/arch/powerpc/platforms/pseries/rtasd.c +++ b/arch/powerpc/platforms/pseries/rtasd.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <linux/vmalloc.h> | 19 | #include <linux/vmalloc.h> |
| 20 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/cpu.h> | 21 | #include <linux/cpu.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/workqueue.h> |
| 23 | 23 | ||
| 24 | #include <asm/uaccess.h> | 24 | #include <asm/uaccess.h> |
| 25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
| @@ -387,36 +387,51 @@ static void do_event_scan(void) | |||
| 387 | } while(error == 0); | 387 | } while(error == 0); |
| 388 | } | 388 | } |
| 389 | 389 | ||
| 390 | static void do_event_scan_all_cpus(long delay) | 390 | static void rtas_event_scan(struct work_struct *w); |
| 391 | DECLARE_DELAYED_WORK(event_scan_work, rtas_event_scan); | ||
| 392 | |||
| 393 | /* | ||
| 394 | * Delay should be at least one second since some machines have problems if | ||
| 395 | * we call event-scan too quickly. | ||
| 396 | */ | ||
| 397 | static unsigned long event_scan_delay = 1*HZ; | ||
| 398 | static int first_pass = 1; | ||
| 399 | |||
| 400 | static void rtas_event_scan(struct work_struct *w) | ||
| 391 | { | 401 | { |
| 392 | int cpu; | 402 | unsigned int cpu; |
| 403 | |||
| 404 | do_event_scan(); | ||
| 393 | 405 | ||
| 394 | get_online_cpus(); | 406 | get_online_cpus(); |
| 395 | cpu = first_cpu(cpu_online_map); | 407 | |
| 396 | for (;;) { | 408 | cpu = next_cpu(smp_processor_id(), cpu_online_map); |
| 397 | set_cpus_allowed(current, cpumask_of_cpu(cpu)); | 409 | if (cpu == NR_CPUS) { |
| 398 | do_event_scan(); | 410 | cpu = first_cpu(cpu_online_map); |
| 399 | set_cpus_allowed(current, CPU_MASK_ALL); | 411 | |
| 400 | 412 | if (first_pass) { | |
| 401 | /* Drop hotplug lock, and sleep for the specified delay */ | 413 | first_pass = 0; |
| 402 | put_online_cpus(); | 414 | event_scan_delay = 30*HZ/rtas_event_scan_rate; |
| 403 | msleep_interruptible(delay); | 415 | |
| 404 | get_online_cpus(); | 416 | if (surveillance_timeout != -1) { |
| 405 | 417 | pr_debug("rtasd: enabling surveillance\n"); | |
| 406 | cpu = next_cpu(cpu, cpu_online_map); | 418 | enable_surveillance(surveillance_timeout); |
| 407 | if (cpu == NR_CPUS) | 419 | pr_debug("rtasd: surveillance enabled\n"); |
| 408 | break; | 420 | } |
| 421 | } | ||
| 409 | } | 422 | } |
| 423 | |||
| 424 | schedule_delayed_work_on(cpu, &event_scan_work, | ||
| 425 | __round_jiffies_relative(event_scan_delay, cpu)); | ||
| 426 | |||
| 410 | put_online_cpus(); | 427 | put_online_cpus(); |
| 411 | } | 428 | } |
| 412 | 429 | ||
| 413 | static int rtasd(void *unused) | 430 | static void start_event_scan(void) |
| 414 | { | 431 | { |
| 415 | unsigned int err_type; | 432 | unsigned int err_type; |
| 416 | int rc; | 433 | int rc; |
| 417 | 434 | ||
| 418 | daemonize("rtasd"); | ||
| 419 | |||
| 420 | printk(KERN_DEBUG "RTAS daemon started\n"); | 435 | printk(KERN_DEBUG "RTAS daemon started\n"); |
| 421 | pr_debug("rtasd: will sleep for %d milliseconds\n", | 436 | pr_debug("rtasd: will sleep for %d milliseconds\n", |
| 422 | (30000 / rtas_event_scan_rate)); | 437 | (30000 / rtas_event_scan_rate)); |
| @@ -434,22 +449,8 @@ static int rtasd(void *unused) | |||
| 434 | } | 449 | } |
| 435 | } | 450 | } |
| 436 | 451 | ||
| 437 | /* First pass. */ | 452 | schedule_delayed_work_on(first_cpu(cpu_online_map), &event_scan_work, |
| 438 | do_event_scan_all_cpus(1000); | 453 | event_scan_delay); |
| 439 | |||
| 440 | if (surveillance_timeout != -1) { | ||
| 441 | pr_debug("rtasd: enabling surveillance\n"); | ||
| 442 | enable_surveillance(surveillance_timeout); | ||
| 443 | pr_debug("rtasd: surveillance enabled\n"); | ||
| 444 | } | ||
| 445 | |||
| 446 | /* Delay should be at least one second since some | ||
| 447 | * machines have problems if we call event-scan too | ||
| 448 | * quickly. */ | ||
| 449 | for (;;) | ||
| 450 | do_event_scan_all_cpus(30000/rtas_event_scan_rate); | ||
| 451 | |||
| 452 | return -EINVAL; | ||
| 453 | } | 454 | } |
| 454 | 455 | ||
| 455 | static int __init rtas_init(void) | 456 | static int __init rtas_init(void) |
| @@ -487,8 +488,7 @@ static int __init rtas_init(void) | |||
| 487 | if (!entry) | 488 | if (!entry) |
| 488 | printk(KERN_ERR "Failed to create error_log proc entry\n"); | 489 | printk(KERN_ERR "Failed to create error_log proc entry\n"); |
| 489 | 490 | ||
| 490 | if (kernel_thread(rtasd, NULL, CLONE_FS) < 0) | 491 | start_event_scan(); |
| 491 | printk(KERN_ERR "Failed to start RTAS daemon\n"); | ||
| 492 | 492 | ||
| 493 | return 0; | 493 | return 0; |
| 494 | } | 494 | } |
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index ec341707e41b..8d75ea21296f 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c | |||
| @@ -63,6 +63,7 @@ | |||
| 63 | #include <asm/smp.h> | 63 | #include <asm/smp.h> |
| 64 | #include <asm/firmware.h> | 64 | #include <asm/firmware.h> |
| 65 | #include <asm/eeh.h> | 65 | #include <asm/eeh.h> |
| 66 | #include <asm/pSeries_reconfig.h> | ||
| 66 | 67 | ||
| 67 | #include "plpar_wrappers.h" | 68 | #include "plpar_wrappers.h" |
| 68 | #include "pseries.h" | 69 | #include "pseries.h" |
| @@ -254,6 +255,29 @@ static void __init pseries_discover_pic(void) | |||
| 254 | " interrupt-controller\n"); | 255 | " interrupt-controller\n"); |
| 255 | } | 256 | } |
| 256 | 257 | ||
| 258 | static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | ||
| 259 | { | ||
| 260 | struct device_node *np = node; | ||
| 261 | struct pci_dn *pci = NULL; | ||
| 262 | int err = NOTIFY_OK; | ||
| 263 | |||
| 264 | switch (action) { | ||
| 265 | case PSERIES_RECONFIG_ADD: | ||
| 266 | pci = np->parent->data; | ||
| 267 | if (pci) | ||
| 268 | update_dn_pci_info(np, pci->phb); | ||
| 269 | break; | ||
| 270 | default: | ||
| 271 | err = NOTIFY_DONE; | ||
| 272 | break; | ||
| 273 | } | ||
| 274 | return err; | ||
| 275 | } | ||
| 276 | |||
| 277 | static struct notifier_block pci_dn_reconfig_nb = { | ||
| 278 | .notifier_call = pci_dn_reconfig_notifier, | ||
| 279 | }; | ||
| 280 | |||
| 257 | static void __init pSeries_setup_arch(void) | 281 | static void __init pSeries_setup_arch(void) |
| 258 | { | 282 | { |
| 259 | /* Discover PIC type and setup ppc_md accordingly */ | 283 | /* Discover PIC type and setup ppc_md accordingly */ |
| @@ -271,6 +295,7 @@ static void __init pSeries_setup_arch(void) | |||
| 271 | /* Find and initialize PCI host bridges */ | 295 | /* Find and initialize PCI host bridges */ |
| 272 | init_pci_config_tokens(); | 296 | init_pci_config_tokens(); |
| 273 | find_and_init_phbs(); | 297 | find_and_init_phbs(); |
| 298 | pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb); | ||
| 274 | eeh_init(); | 299 | eeh_init(); |
| 275 | 300 | ||
| 276 | pSeries_nvram_init(); | 301 | pSeries_nvram_init(); |
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 80b513449f4c..be3581a8c294 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c | |||
| @@ -333,7 +333,7 @@ static void xics_eoi_lpar(unsigned int virq) | |||
| 333 | lpar_xirr_info_set((0xff << 24) | irq); | 333 | lpar_xirr_info_set((0xff << 24) | irq); |
| 334 | } | 334 | } |
| 335 | 335 | ||
| 336 | static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | 336 | static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) |
| 337 | { | 337 | { |
| 338 | unsigned int irq; | 338 | unsigned int irq; |
| 339 | int status; | 339 | int status; |
| @@ -342,14 +342,14 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | |||
| 342 | 342 | ||
| 343 | irq = (unsigned int)irq_map[virq].hwirq; | 343 | irq = (unsigned int)irq_map[virq].hwirq; |
| 344 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 344 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
| 345 | return; | 345 | return -1; |
| 346 | 346 | ||
| 347 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | 347 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); |
| 348 | 348 | ||
| 349 | if (status) { | 349 | if (status) { |
| 350 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", | 350 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
| 351 | __func__, irq, status); | 351 | __func__, irq, status); |
| 352 | return; | 352 | return -1; |
| 353 | } | 353 | } |
| 354 | 354 | ||
| 355 | /* | 355 | /* |
| @@ -363,7 +363,7 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | |||
| 363 | printk(KERN_WARNING | 363 | printk(KERN_WARNING |
| 364 | "%s: No online cpus in the mask %s for irq %d\n", | 364 | "%s: No online cpus in the mask %s for irq %d\n", |
| 365 | __func__, cpulist, virq); | 365 | __func__, cpulist, virq); |
| 366 | return; | 366 | return -1; |
| 367 | } | 367 | } |
| 368 | 368 | ||
| 369 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | 369 | status = rtas_call(ibm_set_xive, 3, 1, NULL, |
| @@ -372,8 +372,10 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | |||
| 372 | if (status) { | 372 | if (status) { |
| 373 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", | 373 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", |
| 374 | __func__, irq, status); | 374 | __func__, irq, status); |
| 375 | return; | 375 | return -1; |
| 376 | } | 376 | } |
| 377 | |||
| 378 | return 0; | ||
| 377 | } | 379 | } |
| 378 | 380 | ||
| 379 | static struct irq_chip xics_pic_direct = { | 381 | static struct irq_chip xics_pic_direct = { |
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index b33b28a6fe12..9d4b17462f13 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile | |||
| @@ -1,3 +1,5 @@ | |||
| 1 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 2 | |||
| 1 | ifeq ($(CONFIG_PPC64),y) | 3 | ifeq ($(CONFIG_PPC64),y) |
| 2 | EXTRA_CFLAGS += -mno-minimal-toc | 4 | EXTRA_CFLAGS += -mno-minimal-toc |
| 3 | endif | 5 | endif |
| @@ -34,6 +36,7 @@ obj-$(CONFIG_IPIC) += ipic.o | |||
| 34 | obj-$(CONFIG_4xx) += uic.o | 36 | obj-$(CONFIG_4xx) += uic.o |
| 35 | obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o | 37 | obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o |
| 36 | obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o | 38 | obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o |
| 39 | obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o | ||
| 37 | obj-$(CONFIG_OF_RTC) += of_rtc.o | 40 | obj-$(CONFIG_OF_RTC) += of_rtc.o |
| 38 | ifeq ($(CONFIG_PCI),y) | 41 | ifeq ($(CONFIG_PCI),y) |
| 39 | obj-$(CONFIG_4xx) += ppc4xx_pci.o | 42 | obj-$(CONFIG_4xx) += ppc4xx_pci.o |
| @@ -47,6 +50,9 @@ obj-$(CONFIG_PPC_DCR) += dcr.o | |||
| 47 | obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o | 50 | obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o |
| 48 | obj-$(CONFIG_UCODE_PATCH) += micropatch.o | 51 | obj-$(CONFIG_UCODE_PATCH) += micropatch.o |
| 49 | 52 | ||
| 53 | obj-$(CONFIG_PPC_MPC512x) += mpc5xxx_clocks.o | ||
| 54 | obj-$(CONFIG_PPC_MPC52xx) += mpc5xxx_clocks.o | ||
| 55 | |||
| 50 | ifeq ($(CONFIG_SUSPEND),y) | 56 | ifeq ($(CONFIG_SUSPEND),y) |
| 51 | obj-$(CONFIG_6xx) += 6xx-suspend.o | 57 | obj-$(CONFIG_6xx) += 6xx-suspend.o |
| 52 | endif | 58 | endif |
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c index 9e105cbc5e5f..a4779912a5ca 100644 --- a/arch/powerpc/sysdev/axonram.c +++ b/arch/powerpc/sysdev/axonram.c | |||
| @@ -250,7 +250,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id) | |||
| 250 | 250 | ||
| 251 | set_capacity(bank->disk, bank->size >> AXON_RAM_SECTOR_SHIFT); | 251 | set_capacity(bank->disk, bank->size >> AXON_RAM_SECTOR_SHIFT); |
| 252 | blk_queue_make_request(bank->disk->queue, axon_ram_make_request); | 252 | blk_queue_make_request(bank->disk->queue, axon_ram_make_request); |
| 253 | blk_queue_hardsect_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE); | 253 | blk_queue_logical_block_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE); |
| 254 | add_disk(bank->disk); | 254 | add_disk(bank->disk); |
| 255 | 255 | ||
| 256 | bank->irq_id = irq_of_parse_and_map(device->node, 0); | 256 | bank->irq_id = irq_of_parse_and_map(device->node, 0); |
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c index fd969f0e3121..eb5927212fab 100644 --- a/arch/powerpc/sysdev/cpm2.c +++ b/arch/powerpc/sysdev/cpm2.c | |||
| @@ -61,7 +61,7 @@ EXPORT_SYMBOL(cpm2_immr); | |||
| 61 | void __init cpm2_reset(void) | 61 | void __init cpm2_reset(void) |
| 62 | { | 62 | { |
| 63 | #ifdef CONFIG_PPC_85xx | 63 | #ifdef CONFIG_PPC_85xx |
| 64 | cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); | 64 | cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE); |
| 65 | #else | 65 | #else |
| 66 | cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE); | 66 | cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE); |
| 67 | #endif | 67 | #endif |
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index f25ce818d40a..da38a1ff97bb 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c | |||
| @@ -113,8 +113,13 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, | |||
| 113 | struct msi_msg *msg) | 113 | struct msi_msg *msg) |
| 114 | { | 114 | { |
| 115 | struct fsl_msi *msi_data = fsl_msi; | 115 | struct fsl_msi *msi_data = fsl_msi; |
| 116 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | ||
| 117 | u32 base = 0; | ||
| 116 | 118 | ||
| 117 | msg->address_lo = msi_data->msi_addr_lo; | 119 | pci_bus_read_config_dword(hose->bus, |
| 120 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | ||
| 121 | |||
| 122 | msg->address_lo = msi_data->msi_addr_lo + base; | ||
| 118 | msg->address_hi = msi_data->msi_addr_hi; | 123 | msg->address_hi = msi_data->msi_addr_hi; |
| 119 | msg->data = hwirq; | 124 | msg->data = hwirq; |
| 120 | 125 | ||
| @@ -271,7 +276,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev, | |||
| 271 | msi->irqhost->host_data = msi; | 276 | msi->irqhost->host_data = msi; |
| 272 | 277 | ||
| 273 | msi->msi_addr_hi = 0x0; | 278 | msi->msi_addr_hi = 0x0; |
| 274 | msi->msi_addr_lo = res.start + features->msiir_offset; | 279 | msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff); |
| 275 | 280 | ||
| 276 | rc = fsl_msi_init_allocator(msi); | 281 | rc = fsl_msi_init_allocator(msi); |
| 277 | if (rc) { | 282 | if (rc) { |
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 78021d8afc53..ae88b1448018 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
| @@ -23,6 +23,8 @@ | |||
| 23 | #include <linux/string.h> | 23 | #include <linux/string.h> |
| 24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
| 25 | #include <linux/bootmem.h> | 25 | #include <linux/bootmem.h> |
| 26 | #include <linux/lmb.h> | ||
| 27 | #include <linux/log2.h> | ||
| 26 | 28 | ||
| 27 | #include <asm/io.h> | 29 | #include <asm/io.h> |
| 28 | #include <asm/prom.h> | 30 | #include <asm/prom.h> |
| @@ -96,7 +98,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
| 96 | struct resource *rsrc) | 98 | struct resource *rsrc) |
| 97 | { | 99 | { |
| 98 | struct ccsr_pci __iomem *pci; | 100 | struct ccsr_pci __iomem *pci; |
| 99 | int i, j, n; | 101 | int i, j, n, mem_log, win_idx = 2; |
| 102 | u64 mem, sz, paddr_hi = 0; | ||
| 103 | u64 paddr_lo = ULLONG_MAX; | ||
| 104 | u32 pcicsrbar = 0, pcicsrbar_sz; | ||
| 105 | u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | | ||
| 106 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; | ||
| 107 | char *name = hose->dn->full_name; | ||
| 100 | 108 | ||
| 101 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", | 109 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
| 102 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); | 110 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); |
| @@ -117,6 +125,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
| 117 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) | 125 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) |
| 118 | continue; | 126 | continue; |
| 119 | 127 | ||
| 128 | paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); | ||
| 129 | paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); | ||
| 130 | |||
| 120 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], | 131 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], |
| 121 | hose->pci_mem_offset); | 132 | hose->pci_mem_offset); |
| 122 | 133 | ||
| @@ -147,10 +158,105 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
| 147 | } | 158 | } |
| 148 | } | 159 | } |
| 149 | 160 | ||
| 150 | /* Setup 2G inbound Memory Window @ 1 */ | 161 | /* convert to pci address space */ |
| 151 | out_be32(&pci->piw[2].pitar, 0x00000000); | 162 | paddr_hi -= hose->pci_mem_offset; |
| 152 | out_be32(&pci->piw[2].piwbar,0x00000000); | 163 | paddr_lo -= hose->pci_mem_offset; |
| 153 | out_be32(&pci->piw[2].piwar, PIWAR_2G); | 164 | |
| 165 | if (paddr_hi == paddr_lo) { | ||
| 166 | pr_err("%s: No outbound window space\n", name); | ||
| 167 | return ; | ||
| 168 | } | ||
| 169 | |||
| 170 | if (paddr_lo == 0) { | ||
| 171 | pr_err("%s: No space for inbound window\n", name); | ||
| 172 | return ; | ||
| 173 | } | ||
| 174 | |||
| 175 | /* setup PCSRBAR/PEXCSRBAR */ | ||
| 176 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); | ||
| 177 | early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); | ||
| 178 | pcicsrbar_sz = ~pcicsrbar_sz + 1; | ||
| 179 | |||
| 180 | if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || | ||
| 181 | (paddr_lo > 0x100000000ull)) | ||
| 182 | pcicsrbar = 0x100000000ull - pcicsrbar_sz; | ||
| 183 | else | ||
| 184 | pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; | ||
| 185 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); | ||
| 186 | |||
| 187 | paddr_lo = min(paddr_lo, (u64)pcicsrbar); | ||
| 188 | |||
| 189 | pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); | ||
| 190 | |||
| 191 | /* Setup inbound mem window */ | ||
| 192 | mem = lmb_end_of_DRAM(); | ||
| 193 | sz = min(mem, paddr_lo); | ||
| 194 | mem_log = __ilog2_u64(sz); | ||
| 195 | |||
| 196 | /* PCIe can overmap inbound & outbound since RX & TX are separated */ | ||
| 197 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { | ||
| 198 | /* Size window to exact size if power-of-two or one size up */ | ||
| 199 | if ((1ull << mem_log) != mem) { | ||
| 200 | if ((1ull << mem_log) > mem) | ||
| 201 | pr_info("%s: Setting PCI inbound window " | ||
| 202 | "greater than memory size\n", name); | ||
| 203 | mem_log++; | ||
| 204 | } | ||
| 205 | |||
| 206 | piwar |= (mem_log - 1); | ||
| 207 | |||
| 208 | /* Setup inbound memory window */ | ||
| 209 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | ||
| 210 | out_be32(&pci->piw[win_idx].piwbar, 0x00000000); | ||
| 211 | out_be32(&pci->piw[win_idx].piwar, piwar); | ||
| 212 | win_idx--; | ||
| 213 | |||
| 214 | hose->dma_window_base_cur = 0x00000000; | ||
| 215 | hose->dma_window_size = (resource_size_t)sz; | ||
| 216 | } else { | ||
| 217 | u64 paddr = 0; | ||
| 218 | |||
| 219 | /* Setup inbound memory window */ | ||
| 220 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | ||
| 221 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | ||
| 222 | out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); | ||
| 223 | win_idx--; | ||
| 224 | |||
| 225 | paddr += 1ull << mem_log; | ||
| 226 | sz -= 1ull << mem_log; | ||
| 227 | |||
| 228 | if (sz) { | ||
| 229 | mem_log = __ilog2_u64(sz); | ||
| 230 | piwar |= (mem_log - 1); | ||
| 231 | |||
| 232 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | ||
| 233 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | ||
| 234 | out_be32(&pci->piw[win_idx].piwar, piwar); | ||
| 235 | win_idx--; | ||
| 236 | |||
| 237 | paddr += 1ull << mem_log; | ||
| 238 | } | ||
| 239 | |||
| 240 | hose->dma_window_base_cur = 0x00000000; | ||
| 241 | hose->dma_window_size = (resource_size_t)paddr; | ||
| 242 | } | ||
| 243 | |||
| 244 | if (hose->dma_window_size < mem) { | ||
| 245 | #ifndef CONFIG_SWIOTLB | ||
| 246 | pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " | ||
| 247 | "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", | ||
| 248 | name); | ||
| 249 | #endif | ||
| 250 | /* adjusting outbound windows could reclaim space in mem map */ | ||
| 251 | if (paddr_hi < 0xffffffffull) | ||
| 252 | pr_warning("%s: WARNING: Outbound window cfg leaves " | ||
| 253 | "gaps in memory map. Adjusting the memory map " | ||
| 254 | "could reduce unnecessary bounce buffering.\n", | ||
| 255 | name); | ||
| 256 | |||
| 257 | pr_info("%s: DMA window size is 0x%llx\n", name, | ||
| 258 | (u64)hose->dma_window_size); | ||
| 259 | } | ||
| 154 | 260 | ||
| 155 | iounmap(pci); | 261 | iounmap(pci); |
| 156 | } | 262 | } |
| @@ -176,19 +282,9 @@ static void __init setup_pci_cmd(struct pci_controller *hose) | |||
| 176 | } | 282 | } |
| 177 | } | 283 | } |
| 178 | 284 | ||
| 179 | static void __init setup_pci_pcsrbar(struct pci_controller *hose) | ||
| 180 | { | ||
| 181 | #ifdef CONFIG_PCI_MSI | ||
| 182 | phys_addr_t immr_base; | ||
| 183 | |||
| 184 | immr_base = get_immrbase(); | ||
| 185 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base); | ||
| 186 | #endif | ||
| 187 | } | ||
| 188 | |||
| 189 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) | 285 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
| 190 | { | 286 | { |
| 191 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | 287 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 192 | int i; | 288 | int i; |
| 193 | 289 | ||
| 194 | if ((bus->parent == hose->bus) && | 290 | if ((bus->parent == hose->bus) && |
| @@ -269,8 +365,6 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) | |||
| 269 | /* Setup PEX window registers */ | 365 | /* Setup PEX window registers */ |
| 270 | setup_pci_atmu(hose, &rsrc); | 366 | setup_pci_atmu(hose, &rsrc); |
| 271 | 367 | ||
| 272 | /* Setup PEXCSRBAR */ | ||
| 273 | setup_pci_pcsrbar(hose); | ||
| 274 | return 0; | 368 | return 0; |
| 275 | } | 369 | } |
| 276 | 370 | ||
| @@ -281,6 +375,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header); | |||
| 281 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); | 375 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header); |
| 282 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); | 376 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header); |
| 283 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); | 377 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header); |
| 378 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header); | ||
| 379 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header); | ||
| 284 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); | 380 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header); |
| 285 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); | 381 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header); |
| 286 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); | 382 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header); |
| @@ -296,6 +392,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); | |||
| 296 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); | 392 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); |
| 297 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); | 393 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); |
| 298 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); | 394 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); |
| 395 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); | ||
| 396 | DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); | ||
| 299 | #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ | 397 | #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ |
| 300 | 398 | ||
| 301 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) | 399 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
| @@ -324,7 +422,7 @@ struct mpc83xx_pcie_priv { | |||
| 324 | 422 | ||
| 325 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) | 423 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) |
| 326 | { | 424 | { |
| 327 | struct pci_controller *hose = bus->sysdata; | 425 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 328 | 426 | ||
| 329 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) | 427 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) |
| 330 | return PCIBIOS_DEVICE_NOT_FOUND; | 428 | return PCIBIOS_DEVICE_NOT_FOUND; |
| @@ -350,7 +448,7 @@ static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) | |||
| 350 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, | 448 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, |
| 351 | unsigned int devfn, int offset) | 449 | unsigned int devfn, int offset) |
| 352 | { | 450 | { |
| 353 | struct pci_controller *hose = bus->sysdata; | 451 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 354 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; | 452 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
| 355 | u8 bus_no = bus->number - hose->first_busno; | 453 | u8 bus_no = bus->number - hose->first_busno; |
| 356 | u32 dev_base = bus_no << 24 | devfn << 16; | 454 | u32 dev_base = bus_no << 24 | devfn << 16; |
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 13f30c2a61e7..a9d8bbebed80 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
| @@ -16,7 +16,11 @@ | |||
| 16 | 16 | ||
| 17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ | 17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ |
| 18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | 18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ |
| 19 | #define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ | 19 | #define PIWAR_EN 0x80000000 /* Enable */ |
| 20 | #define PIWAR_PF 0x20000000 /* prefetch */ | ||
| 21 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ | ||
| 22 | #define PIWAR_READ_SNOOP 0x00050000 | ||
| 23 | #define PIWAR_WRITE_SNOOP 0x00005000 | ||
| 20 | 24 | ||
| 21 | /* PCI/PCI Express outbound window reg */ | 25 | /* PCI/PCI Express outbound window reg */ |
| 22 | struct pci_outbound_window_regs { | 26 | struct pci_outbound_window_regs { |
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index abdb124e1e2f..39db9d1155d2 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c | |||
| @@ -1026,8 +1026,7 @@ int fsl_rio_setup(struct of_device *dev) | |||
| 1026 | return -EFAULT; | 1026 | return -EFAULT; |
| 1027 | } | 1027 | } |
| 1028 | dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name); | 1028 | dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name); |
| 1029 | dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n", regs.start, | 1029 | dev_info(&dev->dev, "Regs: %pR\n", ®s); |
| 1030 | regs.end - regs.start + 1); | ||
| 1031 | 1030 | ||
| 1032 | dt_range = of_get_property(dev->node, "ranges", &rlen); | 1031 | dt_range = of_get_property(dev->node, "ranges", &rlen); |
| 1033 | if (!dt_range) { | 1032 | if (!dt_range) { |
| @@ -1077,8 +1076,9 @@ int fsl_rio_setup(struct of_device *dev) | |||
| 1077 | 1076 | ||
| 1078 | INIT_LIST_HEAD(&port->dbells); | 1077 | INIT_LIST_HEAD(&port->dbells); |
| 1079 | port->iores.start = law_start; | 1078 | port->iores.start = law_start; |
| 1080 | port->iores.end = law_start + law_size; | 1079 | port->iores.end = law_start + law_size - 1; |
| 1081 | port->iores.flags = IORESOURCE_MEM; | 1080 | port->iores.flags = IORESOURCE_MEM; |
| 1081 | port->iores.name = "rio_io_win"; | ||
| 1082 | 1082 | ||
| 1083 | priv->bellirq = irq_of_parse_and_map(dev->node, 2); | 1083 | priv->bellirq = irq_of_parse_and_map(dev->node, 2); |
| 1084 | priv->txirq = irq_of_parse_and_map(dev->node, 3); | 1084 | priv->txirq = irq_of_parse_and_map(dev->node, 3); |
| @@ -1156,14 +1156,15 @@ int fsl_rio_setup(struct of_device *dev) | |||
| 1156 | out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); | 1156 | out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); |
| 1157 | 1157 | ||
| 1158 | /* Configure maintenance transaction window */ | 1158 | /* Configure maintenance transaction window */ |
| 1159 | out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000); | 1159 | out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); |
| 1160 | out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); | 1160 | out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); /* 4M */ |
| 1161 | 1161 | ||
| 1162 | priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); | 1162 | priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); |
| 1163 | 1163 | ||
| 1164 | /* Configure outbound doorbell window */ | 1164 | /* Configure outbound doorbell window */ |
| 1165 | out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400); | 1165 | out_be32(&priv->dbell_atmu_regs->rowbar, |
| 1166 | out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); | 1166 | (law_start + RIO_MAINT_WIN_SIZE) >> 12); |
| 1167 | out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ | ||
| 1167 | fsl_rio_doorbell_init(port); | 1168 | fsl_rio_doorbell_init(port); |
| 1168 | 1169 | ||
| 1169 | return 0; | 1170 | return 0; |
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 5c64ccd402e2..95dbc643c4fc 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c | |||
| @@ -379,16 +379,10 @@ static int __init setup_rstcr(void) | |||
| 379 | struct device_node *np; | 379 | struct device_node *np; |
| 380 | np = of_find_node_by_name(NULL, "global-utilities"); | 380 | np = of_find_node_by_name(NULL, "global-utilities"); |
| 381 | if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { | 381 | if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { |
| 382 | const u32 *prop = of_get_property(np, "reg", NULL); | 382 | rstcr = of_iomap(np, 0) + 0xb0; |
| 383 | if (prop) { | 383 | if (!rstcr) |
| 384 | /* map reset control register | 384 | printk (KERN_EMERG "Error: reset control register " |
| 385 | * 0xE00B0 is offset of reset control register | 385 | "not mapped!\n"); |
| 386 | */ | ||
| 387 | rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff); | ||
| 388 | if (!rstcr) | ||
| 389 | printk (KERN_EMERG "Error: reset control " | ||
| 390 | "register not mapped!\n"); | ||
| 391 | } | ||
| 392 | } else | 386 | } else |
| 393 | printk (KERN_INFO "rstcr compatible register does not exist!\n"); | 387 | printk (KERN_INFO "rstcr compatible register does not exist!\n"); |
| 394 | if (np) | 388 | if (np) |
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 7fd49c97501a..7ed809676642 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c | |||
| @@ -24,7 +24,7 @@ static int | |||
| 24 | indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | 24 | indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 25 | int len, u32 *val) | 25 | int len, u32 *val) |
| 26 | { | 26 | { |
| 27 | struct pci_controller *hose = bus->sysdata; | 27 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 28 | volatile void __iomem *cfg_data; | 28 | volatile void __iomem *cfg_data; |
| 29 | u8 cfg_type = 0; | 29 | u8 cfg_type = 0; |
| 30 | u32 bus_no, reg; | 30 | u32 bus_no, reg; |
| @@ -82,7 +82,7 @@ static int | |||
| 82 | indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | 82 | indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 83 | int len, u32 val) | 83 | int len, u32 val) |
| 84 | { | 84 | { |
| 85 | struct pci_controller *hose = bus->sysdata; | 85 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 86 | volatile void __iomem *cfg_data; | 86 | volatile void __iomem *cfg_data; |
| 87 | u8 cfg_type = 0; | 87 | u8 cfg_type = 0; |
| 88 | u32 bus_no, reg; | 88 | u32 bus_no, reg; |
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c new file mode 100644 index 000000000000..34e12f9995fe --- /dev/null +++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /** | ||
| 2 | * mpc5xxx_get_bus_frequency - Find the bus frequency for a device | ||
| 3 | * @node: device node | ||
| 4 | * | ||
| 5 | * Returns bus frequency (IPS on MPC512x, IPB on MPC52xx), | ||
| 6 | * or 0 if the bus frequency cannot be found. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/of_platform.h> | ||
| 11 | |||
| 12 | unsigned int | ||
| 13 | mpc5xxx_get_bus_frequency(struct device_node *node) | ||
| 14 | { | ||
| 15 | struct device_node *np; | ||
| 16 | const unsigned int *p_bus_freq = NULL; | ||
| 17 | |||
| 18 | of_node_get(node); | ||
| 19 | while (node) { | ||
| 20 | p_bus_freq = of_get_property(node, "bus-frequency", NULL); | ||
| 21 | if (p_bus_freq) | ||
| 22 | break; | ||
| 23 | |||
| 24 | np = of_get_parent(node); | ||
| 25 | of_node_put(node); | ||
| 26 | node = np; | ||
| 27 | } | ||
| 28 | if (node) | ||
| 29 | of_node_put(node); | ||
| 30 | |||
| 31 | return p_bus_freq ? *p_bus_freq : 0; | ||
| 32 | } | ||
| 33 | EXPORT_SYMBOL(mpc5xxx_get_bus_frequency); | ||
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 0efc12d1a3d7..9c3af5045495 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
| @@ -613,23 +613,23 @@ static int irq_choose_cpu(unsigned int virt_irq) | |||
| 613 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) | 613 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
| 614 | 614 | ||
| 615 | /* Find an mpic associated with a given linux interrupt */ | 615 | /* Find an mpic associated with a given linux interrupt */ |
| 616 | static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) | 616 | static struct mpic *mpic_find(unsigned int irq) |
| 617 | { | 617 | { |
| 618 | unsigned int src = mpic_irq_to_hw(irq); | ||
| 619 | struct mpic *mpic; | ||
| 620 | |||
| 621 | if (irq < NUM_ISA_INTERRUPTS) | 618 | if (irq < NUM_ISA_INTERRUPTS) |
| 622 | return NULL; | 619 | return NULL; |
| 623 | 620 | ||
| 624 | mpic = irq_desc[irq].chip_data; | 621 | return irq_desc[irq].chip_data; |
| 622 | } | ||
| 625 | 623 | ||
| 626 | if (is_ipi) | 624 | /* Determine if the linux irq is an IPI */ |
| 627 | *is_ipi = (src >= mpic->ipi_vecs[0] && | 625 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) |
| 628 | src <= mpic->ipi_vecs[3]); | 626 | { |
| 627 | unsigned int src = mpic_irq_to_hw(irq); | ||
| 629 | 628 | ||
| 630 | return mpic; | 629 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
| 631 | } | 630 | } |
| 632 | 631 | ||
| 632 | |||
| 633 | /* Convert a cpu mask from logical to physical cpu numbers. */ | 633 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
| 634 | static inline u32 mpic_physmask(u32 cpumask) | 634 | static inline u32 mpic_physmask(u32 cpumask) |
| 635 | { | 635 | { |
| @@ -807,7 +807,7 @@ static void mpic_end_ipi(unsigned int irq) | |||
| 807 | 807 | ||
| 808 | #endif /* CONFIG_SMP */ | 808 | #endif /* CONFIG_SMP */ |
| 809 | 809 | ||
| 810 | void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | 810 | int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) |
| 811 | { | 811 | { |
| 812 | struct mpic *mpic = mpic_from_irq(irq); | 812 | struct mpic *mpic = mpic_from_irq(irq); |
| 813 | unsigned int src = mpic_irq_to_hw(irq); | 813 | unsigned int src = mpic_irq_to_hw(irq); |
| @@ -824,6 +824,8 @@ void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |||
| 824 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | 824 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), |
| 825 | mpic_physmask(cpus_addr(tmp)[0])); | 825 | mpic_physmask(cpus_addr(tmp)[0])); |
| 826 | } | 826 | } |
| 827 | |||
| 828 | return 0; | ||
| 827 | } | 829 | } |
| 828 | 830 | ||
| 829 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) | 831 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
| @@ -1381,8 +1383,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable) | |||
| 1381 | 1383 | ||
| 1382 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | 1384 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) |
| 1383 | { | 1385 | { |
| 1384 | unsigned int is_ipi; | 1386 | struct mpic *mpic = mpic_find(irq); |
| 1385 | struct mpic *mpic = mpic_find(irq, &is_ipi); | ||
| 1386 | unsigned int src = mpic_irq_to_hw(irq); | 1387 | unsigned int src = mpic_irq_to_hw(irq); |
| 1387 | unsigned long flags; | 1388 | unsigned long flags; |
| 1388 | u32 reg; | 1389 | u32 reg; |
| @@ -1391,7 +1392,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |||
| 1391 | return; | 1392 | return; |
| 1392 | 1393 | ||
| 1393 | spin_lock_irqsave(&mpic_lock, flags); | 1394 | spin_lock_irqsave(&mpic_lock, flags); |
| 1394 | if (is_ipi) { | 1395 | if (mpic_is_ipi(mpic, irq)) { |
| 1395 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & | 1396 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
| 1396 | ~MPIC_VECPRI_PRIORITY_MASK; | 1397 | ~MPIC_VECPRI_PRIORITY_MASK; |
| 1397 | mpic_ipi_write(src - mpic->ipi_vecs[0], | 1398 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h index 3cef2af10f42..eff433c322a0 100644 --- a/arch/powerpc/sysdev/mpic.h +++ b/arch/powerpc/sysdev/mpic.h | |||
| @@ -36,6 +36,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic) | |||
| 36 | 36 | ||
| 37 | extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); | 37 | extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); |
| 38 | extern void mpic_set_vector(unsigned int virq, unsigned int vector); | 38 | extern void mpic_set_vector(unsigned int virq, unsigned int vector); |
| 39 | extern void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask); | 39 | extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask); |
| 40 | 40 | ||
| 41 | #endif /* _POWERPC_SYSDEV_MPIC_H */ | 41 | #endif /* _POWERPC_SYSDEV_MPIC_H */ |
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 6a2d473c345a..daefc93ddffe 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c | |||
| @@ -1295,7 +1295,7 @@ static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port | |||
| 1295 | static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | 1295 | static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, |
| 1296 | int offset, int len, u32 *val) | 1296 | int offset, int len, u32 *val) |
| 1297 | { | 1297 | { |
| 1298 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | 1298 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 1299 | struct ppc4xx_pciex_port *port = | 1299 | struct ppc4xx_pciex_port *port = |
| 1300 | &ppc4xx_pciex_ports[hose->indirect_type]; | 1300 | &ppc4xx_pciex_ports[hose->indirect_type]; |
| 1301 | void __iomem *addr; | 1301 | void __iomem *addr; |
| @@ -1352,7 +1352,7 @@ static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | |||
| 1352 | static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, | 1352 | static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, |
| 1353 | int offset, int len, u32 val) | 1353 | int offset, int len, u32 val) |
| 1354 | { | 1354 | { |
| 1355 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | 1355 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 1356 | struct ppc4xx_pciex_port *port = | 1356 | struct ppc4xx_pciex_port *port = |
| 1357 | &ppc4xx_pciex_ports[hose->indirect_type]; | 1357 | &ppc4xx_pciex_ports[hose->indirect_type]; |
| 1358 | void __iomem *addr; | 1358 | void __iomem *addr; |
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 01bce3784b0a..b28b0e512d67 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c | |||
| @@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr; | |||
| 61 | EXPORT_SYMBOL(qe_immr); | 61 | EXPORT_SYMBOL(qe_immr); |
| 62 | 62 | ||
| 63 | static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ | 63 | static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ |
| 64 | static unsigned int qe_num_of_snum; | ||
| 64 | 65 | ||
| 65 | static phys_addr_t qebase = -1; | 66 | static phys_addr_t qebase = -1; |
| 66 | 67 | ||
| @@ -264,10 +265,14 @@ static void qe_snums_init(void) | |||
| 264 | 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, | 265 | 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, |
| 265 | 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, | 266 | 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, |
| 266 | 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, | 267 | 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, |
| 267 | 0xD8, 0xD9, 0xE8, 0xE9, | 268 | 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19, |
| 269 | 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, | ||
| 270 | 0x68, 0x69, 0x78, 0x79, 0x80, 0x81, | ||
| 268 | }; | 271 | }; |
| 269 | 272 | ||
| 270 | for (i = 0; i < QE_NUM_OF_SNUM; i++) { | 273 | qe_num_of_snum = qe_get_num_of_snums(); |
| 274 | |||
| 275 | for (i = 0; i < qe_num_of_snum; i++) { | ||
| 271 | snums[i].num = snum_init[i]; | 276 | snums[i].num = snum_init[i]; |
| 272 | snums[i].state = QE_SNUM_STATE_FREE; | 277 | snums[i].state = QE_SNUM_STATE_FREE; |
| 273 | } | 278 | } |
| @@ -280,7 +285,7 @@ int qe_get_snum(void) | |||
| 280 | int i; | 285 | int i; |
| 281 | 286 | ||
| 282 | spin_lock_irqsave(&qe_lock, flags); | 287 | spin_lock_irqsave(&qe_lock, flags); |
| 283 | for (i = 0; i < QE_NUM_OF_SNUM; i++) { | 288 | for (i = 0; i < qe_num_of_snum; i++) { |
| 284 | if (snums[i].state == QE_SNUM_STATE_FREE) { | 289 | if (snums[i].state == QE_SNUM_STATE_FREE) { |
| 285 | snums[i].state = QE_SNUM_STATE_USED; | 290 | snums[i].state = QE_SNUM_STATE_USED; |
| 286 | snum = snums[i].num; | 291 | snum = snums[i].num; |
| @@ -297,7 +302,7 @@ void qe_put_snum(u8 snum) | |||
| 297 | { | 302 | { |
| 298 | int i; | 303 | int i; |
| 299 | 304 | ||
| 300 | for (i = 0; i < QE_NUM_OF_SNUM; i++) { | 305 | for (i = 0; i < qe_num_of_snum; i++) { |
| 301 | if (snums[i].num == snum) { | 306 | if (snums[i].num == snum) { |
| 302 | snums[i].state = QE_SNUM_STATE_FREE; | 307 | snums[i].state = QE_SNUM_STATE_FREE; |
| 303 | break; | 308 | break; |
| @@ -575,3 +580,65 @@ struct qe_firmware_info *qe_get_firmware_info(void) | |||
| 575 | } | 580 | } |
| 576 | EXPORT_SYMBOL(qe_get_firmware_info); | 581 | EXPORT_SYMBOL(qe_get_firmware_info); |
| 577 | 582 | ||
| 583 | unsigned int qe_get_num_of_risc(void) | ||
| 584 | { | ||
| 585 | struct device_node *qe; | ||
| 586 | int size; | ||
| 587 | unsigned int num_of_risc = 0; | ||
| 588 | const u32 *prop; | ||
| 589 | |||
| 590 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); | ||
| 591 | if (!qe) { | ||
| 592 | /* Older devices trees did not have an "fsl,qe" | ||
| 593 | * compatible property, so we need to look for | ||
| 594 | * the QE node by name. | ||
| 595 | */ | ||
| 596 | qe = of_find_node_by_type(NULL, "qe"); | ||
| 597 | if (!qe) | ||
| 598 | return num_of_risc; | ||
| 599 | } | ||
| 600 | |||
| 601 | prop = of_get_property(qe, "fsl,qe-num-riscs", &size); | ||
| 602 | if (prop && size == sizeof(*prop)) | ||
| 603 | num_of_risc = *prop; | ||
| 604 | |||
| 605 | of_node_put(qe); | ||
| 606 | |||
| 607 | return num_of_risc; | ||
| 608 | } | ||
| 609 | EXPORT_SYMBOL(qe_get_num_of_risc); | ||
| 610 | |||
| 611 | unsigned int qe_get_num_of_snums(void) | ||
| 612 | { | ||
| 613 | struct device_node *qe; | ||
| 614 | int size; | ||
| 615 | unsigned int num_of_snums; | ||
| 616 | const u32 *prop; | ||
| 617 | |||
| 618 | num_of_snums = 28; /* The default number of snum for threads is 28 */ | ||
| 619 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); | ||
| 620 | if (!qe) { | ||
| 621 | /* Older devices trees did not have an "fsl,qe" | ||
| 622 | * compatible property, so we need to look for | ||
| 623 | * the QE node by name. | ||
| 624 | */ | ||
| 625 | qe = of_find_node_by_type(NULL, "qe"); | ||
| 626 | if (!qe) | ||
| 627 | return num_of_snums; | ||
| 628 | } | ||
| 629 | |||
| 630 | prop = of_get_property(qe, "fsl,qe-num-snums", &size); | ||
| 631 | if (prop && size == sizeof(*prop)) { | ||
| 632 | num_of_snums = *prop; | ||
| 633 | if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) { | ||
| 634 | /* No QE ever has fewer than 28 SNUMs */ | ||
| 635 | pr_err("QE: number of snum is invalid\n"); | ||
| 636 | return -EINVAL; | ||
| 637 | } | ||
| 638 | } | ||
| 639 | |||
| 640 | of_node_put(qe); | ||
| 641 | |||
| 642 | return num_of_snums; | ||
| 643 | } | ||
| 644 | EXPORT_SYMBOL(qe_get_num_of_snums); | ||
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 24e1f5a197ae..cf244a419e96 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c | |||
| @@ -63,7 +63,7 @@ tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, | |||
| 63 | int offset, int len, u32 val) | 63 | int offset, int len, u32 val) |
| 64 | { | 64 | { |
| 65 | volatile unsigned char *cfg_addr; | 65 | volatile unsigned char *cfg_addr; |
| 66 | struct pci_controller *hose = bus->sysdata; | 66 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 67 | 67 | ||
| 68 | if (ppc_md.pci_exclude_device) | 68 | if (ppc_md.pci_exclude_device) |
| 69 | if (ppc_md.pci_exclude_device(hose, bus->number, devfunc)) | 69 | if (ppc_md.pci_exclude_device(hose, bus->number, devfunc)) |
| @@ -149,7 +149,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |||
| 149 | int len, u32 * val) | 149 | int len, u32 * val) |
| 150 | { | 150 | { |
| 151 | volatile unsigned char *cfg_addr; | 151 | volatile unsigned char *cfg_addr; |
| 152 | struct pci_controller *hose = bus->sysdata; | 152 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 153 | u32 temp; | 153 | u32 temp; |
| 154 | 154 | ||
| 155 | if (ppc_md.pci_exclude_device) | 155 | if (ppc_md.pci_exclude_device) |
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index c658b413c9b4..3ee1fd37bbfc 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
| 26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
| 27 | #include <asm/processor.h> | 27 | #include <asm/processor.h> |
| 28 | #include <asm/i8259.h> | ||
| 28 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
| 29 | 30 | ||
| 30 | /* | 31 | /* |
| @@ -191,20 +192,14 @@ struct irq_host * __init | |||
| 191 | xilinx_intc_init(struct device_node *np) | 192 | xilinx_intc_init(struct device_node *np) |
| 192 | { | 193 | { |
| 193 | struct irq_host * irq; | 194 | struct irq_host * irq; |
| 194 | struct resource res; | ||
| 195 | void * regs; | 195 | void * regs; |
| 196 | int rc; | ||
| 197 | 196 | ||
| 198 | /* Find and map the intc registers */ | 197 | /* Find and map the intc registers */ |
| 199 | rc = of_address_to_resource(np, 0, &res); | 198 | regs = of_iomap(np, 0); |
| 200 | if (rc) { | 199 | if (!regs) { |
| 201 | printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n"); | 200 | pr_err("xilinx_intc: could not map registers\n"); |
| 202 | return NULL; | 201 | return NULL; |
| 203 | } | 202 | } |
| 204 | regs = ioremap(res.start, 32); | ||
| 205 | |||
| 206 | printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n", | ||
| 207 | (unsigned long long) res.start, regs); | ||
| 208 | 203 | ||
| 209 | /* Setup interrupt controller */ | 204 | /* Setup interrupt controller */ |
| 210 | out_be32(regs + XINTC_IER, 0); /* disable all irqs */ | 205 | out_be32(regs + XINTC_IER, 0); /* disable all irqs */ |
| @@ -217,6 +212,7 @@ xilinx_intc_init(struct device_node *np) | |||
| 217 | if (!irq) | 212 | if (!irq) |
| 218 | panic(__FILE__ ": Cannot allocate IRQ host\n"); | 213 | panic(__FILE__ ": Cannot allocate IRQ host\n"); |
| 219 | irq->host_data = regs; | 214 | irq->host_data = regs; |
| 215 | |||
| 220 | return irq; | 216 | return irq; |
| 221 | } | 217 | } |
| 222 | 218 | ||
| @@ -227,23 +223,70 @@ int xilinx_intc_get_irq(void) | |||
| 227 | return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR)); | 223 | return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR)); |
| 228 | } | 224 | } |
| 229 | 225 | ||
| 226 | #if defined(CONFIG_PPC_I8259) | ||
| 227 | /* | ||
| 228 | * Support code for cascading to 8259 interrupt controllers | ||
| 229 | */ | ||
| 230 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) | ||
| 231 | { | ||
| 232 | unsigned int cascade_irq = i8259_irq(); | ||
| 233 | if (cascade_irq) | ||
| 234 | generic_handle_irq(cascade_irq); | ||
| 235 | |||
| 236 | /* Let xilinx_intc end the interrupt */ | ||
| 237 | desc->chip->ack(irq); | ||
| 238 | desc->chip->unmask(irq); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void __init xilinx_i8259_setup_cascade(void) | ||
| 242 | { | ||
| 243 | struct device_node *cascade_node; | ||
| 244 | int cascade_irq; | ||
| 245 | |||
| 246 | /* Initialize i8259 controller */ | ||
| 247 | cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic"); | ||
| 248 | if (!cascade_node) | ||
| 249 | return; | ||
| 250 | |||
| 251 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); | ||
| 252 | if (!cascade_irq) { | ||
| 253 | pr_err("virtex_ml510: Failed to map cascade interrupt\n"); | ||
| 254 | goto out; | ||
| 255 | } | ||
| 256 | |||
| 257 | i8259_init(cascade_node, 0); | ||
| 258 | set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); | ||
| 259 | |||
| 260 | /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ | ||
| 261 | /* This looks like a dirty hack to me --gcl */ | ||
| 262 | outb(0xc0, 0x4d0); | ||
| 263 | outb(0xc0, 0x4d1); | ||
| 264 | |||
| 265 | out: | ||
| 266 | of_node_put(cascade_node); | ||
| 267 | } | ||
| 268 | #else | ||
| 269 | static inline void xilinx_i8259_setup_cascade(void) { return; } | ||
| 270 | #endif /* defined(CONFIG_PPC_I8259) */ | ||
| 271 | |||
| 272 | static struct of_device_id xilinx_intc_match[] __initconst = { | ||
| 273 | { .compatible = "xlnx,opb-intc-1.00.c", }, | ||
| 274 | { .compatible = "xlnx,xps-intc-1.00.a", }, | ||
| 275 | {} | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* | ||
| 279 | * Initialize master Xilinx interrupt controller | ||
| 280 | */ | ||
| 230 | void __init xilinx_intc_init_tree(void) | 281 | void __init xilinx_intc_init_tree(void) |
| 231 | { | 282 | { |
| 232 | struct device_node *np; | 283 | struct device_node *np; |
| 233 | 284 | ||
| 234 | /* find top level interrupt controller */ | 285 | /* find top level interrupt controller */ |
| 235 | for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") { | 286 | for_each_matching_node(np, xilinx_intc_match) { |
| 236 | if (!of_get_property(np, "interrupts", NULL)) | 287 | if (!of_get_property(np, "interrupts", NULL)) |
| 237 | break; | 288 | break; |
| 238 | } | 289 | } |
| 239 | if (!np) { | ||
| 240 | for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") { | ||
| 241 | if (!of_get_property(np, "interrupts", NULL)) | ||
| 242 | break; | ||
| 243 | } | ||
| 244 | } | ||
| 245 | |||
| 246 | /* xilinx interrupt controller needs to be top level */ | ||
| 247 | BUG_ON(!np); | 290 | BUG_ON(!np); |
| 248 | 291 | ||
| 249 | master_irqhost = xilinx_intc_init(np); | 292 | master_irqhost = xilinx_intc_init(np); |
| @@ -251,4 +294,6 @@ void __init xilinx_intc_init_tree(void) | |||
| 251 | 294 | ||
| 252 | irq_set_default_host(master_irqhost); | 295 | irq_set_default_host(master_irqhost); |
| 253 | of_node_put(np); | 296 | of_node_put(np); |
| 297 | |||
| 298 | xilinx_i8259_setup_cascade(); | ||
| 254 | } | 299 | } |
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c new file mode 100644 index 000000000000..1453b0eed220 --- /dev/null +++ b/arch/powerpc/sysdev/xilinx_pci.c | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * PCI support for Xilinx plbv46_pci soft-core which can be used on | ||
| 3 | * Xilinx Virtex ML410 / ML510 boards. | ||
| 4 | * | ||
| 5 | * Copyright 2009 Roderick Colenbrander | ||
| 6 | * Copyright 2009 Secret Lab Technologies Ltd. | ||
| 7 | * | ||
| 8 | * The pci bridge fixup code was copied from ppc4xx_pci.c and was written | ||
| 9 | * by Benjamin Herrenschmidt. | ||
| 10 | * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. | ||
| 11 | * | ||
| 12 | * This file is licensed under the terms of the GNU General Public License | ||
| 13 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 14 | * kind, whether express or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/ioport.h> | ||
| 18 | #include <linux/of.h> | ||
| 19 | #include <linux/pci.h> | ||
| 20 | #include <mm/mmu_decl.h> | ||
| 21 | #include <asm/io.h> | ||
| 22 | #include <asm/xilinx_pci.h> | ||
| 23 | |||
| 24 | #define XPLB_PCI_ADDR 0x10c | ||
| 25 | #define XPLB_PCI_DATA 0x110 | ||
| 26 | #define XPLB_PCI_BUS 0x114 | ||
| 27 | |||
| 28 | #define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | ||
| 29 | |||
| 30 | static struct of_device_id xilinx_pci_match[] = { | ||
| 31 | { .compatible = "xlnx,plbv46-pci-1.03.a", }, | ||
| 32 | {} | ||
| 33 | }; | ||
| 34 | |||
| 35 | /** | ||
| 36 | * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. | ||
| 37 | */ | ||
| 38 | static void xilinx_pci_fixup_bridge(struct pci_dev *dev) | ||
| 39 | { | ||
| 40 | struct pci_controller *hose; | ||
| 41 | int i; | ||
| 42 | |||
| 43 | if (dev->devfn || dev->bus->self) | ||
| 44 | return; | ||
| 45 | |||
| 46 | hose = pci_bus_to_host(dev->bus); | ||
| 47 | if (!hose) | ||
| 48 | return; | ||
| 49 | |||
| 50 | if (!of_match_node(xilinx_pci_match, hose->dn)) | ||
| 51 | return; | ||
| 52 | |||
| 53 | /* Hide the PCI host BARs from the kernel as their content doesn't | ||
| 54 | * fit well in the resource management | ||
| 55 | */ | ||
| 56 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
| 57 | dev->resource[i].start = 0; | ||
| 58 | dev->resource[i].end = 0; | ||
| 59 | dev->resource[i].flags = 0; | ||
| 60 | } | ||
| 61 | |||
| 62 | dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", | ||
| 63 | pci_name(dev)); | ||
| 64 | } | ||
| 65 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); | ||
| 66 | |||
| 67 | /** | ||
| 68 | * xilinx_pci_exclude_device - Don't do config access for non-root bus | ||
| 69 | * | ||
| 70 | * This is a hack. Config access to any bus other than bus 0 does not | ||
| 71 | * currently work on the ML510 so we prevent it here. | ||
| 72 | */ | ||
| 73 | static int | ||
| 74 | xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) | ||
| 75 | { | ||
| 76 | return (bus != 0); | ||
| 77 | } | ||
| 78 | |||
| 79 | /** | ||
| 80 | * xilinx_pci_init - Find and register a Xilinx PCI host bridge | ||
| 81 | */ | ||
| 82 | void __init xilinx_pci_init(void) | ||
| 83 | { | ||
| 84 | struct pci_controller *hose; | ||
| 85 | struct resource r; | ||
| 86 | void __iomem *pci_reg; | ||
| 87 | struct device_node *pci_node; | ||
| 88 | |||
| 89 | pci_node = of_find_matching_node(NULL, xilinx_pci_match); | ||
| 90 | if(!pci_node) | ||
| 91 | return; | ||
| 92 | |||
| 93 | if (of_address_to_resource(pci_node, 0, &r)) { | ||
| 94 | pr_err("xilinx-pci: cannot resolve base address\n"); | ||
| 95 | return; | ||
| 96 | } | ||
| 97 | |||
| 98 | hose = pcibios_alloc_controller(pci_node); | ||
| 99 | if (!hose) { | ||
| 100 | pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); | ||
| 101 | return; | ||
| 102 | } | ||
| 103 | |||
| 104 | /* Setup config space */ | ||
| 105 | setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, | ||
| 106 | r.start + XPLB_PCI_DATA, | ||
| 107 | PPC_INDIRECT_TYPE_SET_CFG_TYPE); | ||
| 108 | |||
| 109 | /* According to the xilinx plbv46_pci documentation the soft-core starts | ||
| 110 | * a self-init when the bus master enable bit is set. Without this bit | ||
| 111 | * set the pci bus can't be scanned. | ||
| 112 | */ | ||
| 113 | early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD); | ||
| 114 | |||
| 115 | /* Set the max latency timer to 255 */ | ||
| 116 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff); | ||
| 117 | |||
| 118 | /* Set the max bus number to 255 */ | ||
| 119 | pci_reg = of_iomap(pci_node, 0); | ||
| 120 | out_8(pci_reg + XPLB_PCI_BUS, 0xff); | ||
| 121 | iounmap(pci_reg); | ||
| 122 | |||
| 123 | /* Nothing past the root bridge is working right now. By default | ||
| 124 | * exclude config access to anything except bus 0 */ | ||
| 125 | if (!ppc_md.pci_exclude_device) | ||
| 126 | ppc_md.pci_exclude_device = xilinx_pci_exclude_device; | ||
| 127 | |||
| 128 | /* Register the host bridge with the linux kernel! */ | ||
| 129 | pci_process_bridge_OF_ranges(hose, pci_node, 1); | ||
| 130 | |||
| 131 | pr_info("xilinx-pci: Registered PCI host bridge\n"); | ||
| 132 | } | ||
diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile index 9cb03b71b9d6..85ab97ab840a 100644 --- a/arch/powerpc/xmon/Makefile +++ b/arch/powerpc/xmon/Makefile | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | # Makefile for xmon | 1 | # Makefile for xmon |
| 2 | 2 | ||
| 3 | subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror | ||
| 4 | |||
| 3 | ifdef CONFIG_PPC64 | 5 | ifdef CONFIG_PPC64 |
| 4 | EXTRA_CFLAGS += -mno-minimal-toc | 6 | EXTRA_CFLAGS += -mno-minimal-toc |
| 5 | endif | 7 | endif |
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 8dfad7d9a004..e1f33a81e5e1 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c | |||
| @@ -110,6 +110,7 @@ static int bsesc(void); | |||
| 110 | static void dump(void); | 110 | static void dump(void); |
| 111 | static void prdump(unsigned long, long); | 111 | static void prdump(unsigned long, long); |
| 112 | static int ppc_inst_dump(unsigned long, long, int); | 112 | static int ppc_inst_dump(unsigned long, long, int); |
| 113 | static void dump_log_buf(void); | ||
| 113 | static void backtrace(struct pt_regs *); | 114 | static void backtrace(struct pt_regs *); |
| 114 | static void excprint(struct pt_regs *); | 115 | static void excprint(struct pt_regs *); |
| 115 | static void prregs(struct pt_regs *); | 116 | static void prregs(struct pt_regs *); |
| @@ -197,6 +198,7 @@ Commands:\n\ | |||
| 197 | di dump instructions\n\ | 198 | di dump instructions\n\ |
| 198 | df dump float values\n\ | 199 | df dump float values\n\ |
| 199 | dd dump double values\n\ | 200 | dd dump double values\n\ |
| 201 | dl dump the kernel log buffer\n\ | ||
| 200 | dr dump stream of raw bytes\n\ | 202 | dr dump stream of raw bytes\n\ |
| 201 | e print exception information\n\ | 203 | e print exception information\n\ |
| 202 | f flush cache\n\ | 204 | f flush cache\n\ |
| @@ -2009,6 +2011,8 @@ dump(void) | |||
| 2009 | nidump = MAX_DUMP; | 2011 | nidump = MAX_DUMP; |
| 2010 | adrs += ppc_inst_dump(adrs, nidump, 1); | 2012 | adrs += ppc_inst_dump(adrs, nidump, 1); |
| 2011 | last_cmd = "di\n"; | 2013 | last_cmd = "di\n"; |
| 2014 | } else if (c == 'l') { | ||
| 2015 | dump_log_buf(); | ||
| 2012 | } else if (c == 'r') { | 2016 | } else if (c == 'r') { |
| 2013 | scanhex(&ndump); | 2017 | scanhex(&ndump); |
| 2014 | if (ndump == 0) | 2018 | if (ndump == 0) |
| @@ -2122,6 +2126,49 @@ print_address(unsigned long addr) | |||
| 2122 | xmon_print_symbol(addr, "\t# ", ""); | 2126 | xmon_print_symbol(addr, "\t# ", ""); |
| 2123 | } | 2127 | } |
| 2124 | 2128 | ||
| 2129 | void | ||
| 2130 | dump_log_buf(void) | ||
| 2131 | { | ||
| 2132 | const unsigned long size = 128; | ||
| 2133 | unsigned long end, addr; | ||
| 2134 | unsigned char buf[size + 1]; | ||
| 2135 | |||
| 2136 | addr = 0; | ||
| 2137 | buf[size] = '\0'; | ||
| 2138 | |||
| 2139 | if (setjmp(bus_error_jmp) != 0) { | ||
| 2140 | printf("Unable to lookup symbol __log_buf!\n"); | ||
| 2141 | return; | ||
| 2142 | } | ||
| 2143 | |||
| 2144 | catch_memory_errors = 1; | ||
| 2145 | sync(); | ||
| 2146 | addr = kallsyms_lookup_name("__log_buf"); | ||
| 2147 | |||
| 2148 | if (! addr) | ||
| 2149 | printf("Symbol __log_buf not found!\n"); | ||
| 2150 | else { | ||
| 2151 | end = addr + (1 << CONFIG_LOG_BUF_SHIFT); | ||
| 2152 | while (addr < end) { | ||
| 2153 | if (! mread(addr, buf, size)) { | ||
| 2154 | printf("Can't read memory at address 0x%lx\n", addr); | ||
| 2155 | break; | ||
| 2156 | } | ||
| 2157 | |||
| 2158 | printf("%s", buf); | ||
| 2159 | |||
| 2160 | if (strlen(buf) < size) | ||
| 2161 | break; | ||
| 2162 | |||
| 2163 | addr += size; | ||
| 2164 | } | ||
| 2165 | } | ||
| 2166 | |||
| 2167 | sync(); | ||
| 2168 | /* wait a little while to see if we get a machine check */ | ||
| 2169 | __delay(200); | ||
| 2170 | catch_memory_errors = 0; | ||
| 2171 | } | ||
| 2125 | 2172 | ||
| 2126 | /* | 2173 | /* |
| 2127 | * Memory operations - move, set, print differences | 2174 | * Memory operations - move, set, print differences |