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authorLEROY Christophe <christophe.leroy@c-s.fr>2014-09-19 04:36:10 -0400
committerScott Wood <scottwood@freescale.com>2014-11-07 19:10:44 -0500
commitb0168eb97b8b02594f47ce44faf1502f79e540df (patch)
treef71de298e449a605d41f04ed329c3fb069f5b8e4 /arch/powerpc
parentc9a803fb17bcec0e7527dc8fa055e56a9691abbb (diff)
powerpc/8xx: Don't restore regs to save them again.
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss handler as they are saved again to the same place in ITLBError handler we are jumping to. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/kernel/head_8xx.S8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 46b47e1fe2a9..330d54418494 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -383,8 +383,7 @@ InstructionTLBMiss:
383 lwz r3, 8(r0) 383 lwz r3, 8(r0)
384#endif 384#endif
385 mfspr r10, SPRN_SPRG_SCRATCH2 385 mfspr r10, SPRN_SPRG_SCRATCH2
386 EXCEPTION_EPILOG_0 386 b InstructionTLBError1
387 b InstructionTLBError
388 387
389 . = 0x1200 388 . = 0x1200
390DataStoreTLBMiss: 389DataStoreTLBMiss:
@@ -473,7 +472,10 @@ DataStoreTLBMiss:
473 */ 472 */
474 . = 0x1300 473 . = 0x1300
475InstructionTLBError: 474InstructionTLBError:
476 EXCEPTION_PROLOG 475 EXCEPTION_PROLOG_0
476InstructionTLBError1:
477 EXCEPTION_PROLOG_1
478 EXCEPTION_PROLOG_2
477 mr r4,r12 479 mr r4,r12
478 mr r5,r9 480 mr r5,r9
479 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 481 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */