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authorKumar Gala <galak@kernel.crashing.org>2011-08-30 23:27:59 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-10-07 00:32:57 -0400
commitd70cb31de8b33f19a381132ffb69cf99d45b48e6 (patch)
treeb7777b200e55ce6b1c4862c7f17626205b869bd3 /arch/powerpc
parent66b77a7540e8c08e19d58657689269487e1349da (diff)
powerpc/85xx: Rename PowerPC core nodes to match other e500mc based .dts
The P4080 silicon device tree was using PowerPC,4080 while the other e500mc based SoCs used PowerPC,e500mc. Use the core name to be consistent going forward. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
index b71051f506c1..4984edbb63a2 100644
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -77,7 +77,7 @@
77 #address-cells = <1>; 77 #address-cells = <1>;
78 #size-cells = <0>; 78 #size-cells = <0>;
79 79
80 cpu0: PowerPC,4080@0 { 80 cpu0: PowerPC,e500mc@0 {
81 device_type = "cpu"; 81 device_type = "cpu";
82 reg = <0>; 82 reg = <0>;
83 next-level-cache = <&L2_0>; 83 next-level-cache = <&L2_0>;
@@ -85,7 +85,7 @@
85 next-level-cache = <&cpc>; 85 next-level-cache = <&cpc>;
86 }; 86 };
87 }; 87 };
88 cpu1: PowerPC,4080@1 { 88 cpu1: PowerPC,e500mc@1 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 reg = <1>; 90 reg = <1>;
91 next-level-cache = <&L2_1>; 91 next-level-cache = <&L2_1>;
@@ -93,7 +93,7 @@
93 next-level-cache = <&cpc>; 93 next-level-cache = <&cpc>;
94 }; 94 };
95 }; 95 };
96 cpu2: PowerPC,4080@2 { 96 cpu2: PowerPC,e500mc@2 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 reg = <2>; 98 reg = <2>;
99 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
@@ -101,7 +101,7 @@
101 next-level-cache = <&cpc>; 101 next-level-cache = <&cpc>;
102 }; 102 };
103 }; 103 };
104 cpu3: PowerPC,4080@3 { 104 cpu3: PowerPC,e500mc@3 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 reg = <3>; 106 reg = <3>;
107 next-level-cache = <&L2_3>; 107 next-level-cache = <&L2_3>;
@@ -109,7 +109,7 @@
109 next-level-cache = <&cpc>; 109 next-level-cache = <&cpc>;
110 }; 110 };
111 }; 111 };
112 cpu4: PowerPC,4080@4 { 112 cpu4: PowerPC,e500mc@4 {
113 device_type = "cpu"; 113 device_type = "cpu";
114 reg = <4>; 114 reg = <4>;
115 next-level-cache = <&L2_4>; 115 next-level-cache = <&L2_4>;
@@ -117,7 +117,7 @@
117 next-level-cache = <&cpc>; 117 next-level-cache = <&cpc>;
118 }; 118 };
119 }; 119 };
120 cpu5: PowerPC,4080@5 { 120 cpu5: PowerPC,e500mc@5 {
121 device_type = "cpu"; 121 device_type = "cpu";
122 reg = <5>; 122 reg = <5>;
123 next-level-cache = <&L2_5>; 123 next-level-cache = <&L2_5>;
@@ -125,7 +125,7 @@
125 next-level-cache = <&cpc>; 125 next-level-cache = <&cpc>;
126 }; 126 };
127 }; 127 };
128 cpu6: PowerPC,4080@6 { 128 cpu6: PowerPC,e500mc@6 {
129 device_type = "cpu"; 129 device_type = "cpu";
130 reg = <6>; 130 reg = <6>;
131 next-level-cache = <&L2_6>; 131 next-level-cache = <&L2_6>;
@@ -133,7 +133,7 @@
133 next-level-cache = <&cpc>; 133 next-level-cache = <&cpc>;
134 }; 134 };
135 }; 135 };
136 cpu7: PowerPC,4080@7 { 136 cpu7: PowerPC,e500mc@7 {
137 device_type = "cpu"; 137 device_type = "cpu";
138 reg = <7>; 138 reg = <7>;
139 next-level-cache = <&L2_7>; 139 next-level-cache = <&L2_7>;