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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 01:59:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 01:59:39 -0400
commit184475029a724b6b900d88fc3a5f462a6107d5af (patch)
tree408320b46df221a2424bf94282b1b8e5b7aff7a1 /arch/powerpc
parent3b76eefe0f970c2e19f165d4a1650abc523d10bc (diff)
parentf1f4ee01c0d3dce0e3aa7d04e4332677db7af478 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (99 commits) drivers/virt: add missing linux/interrupt.h to fsl_hypervisor.c powerpc/85xx: fix mpic configuration in CAMP mode powerpc: Copy back TIF flags on return from softirq stack powerpc/64: Make server perfmon only built on ppc64 server devices powerpc/pseries: Fix hvc_vio.c build due to recent changes powerpc: Exporting boot_cpuid_phys powerpc: Add CFAR to oops output hvc_console: Add kdb support powerpc/pseries: Fix hvterm_raw_get_chars to accept < 16 chars, fixing xmon powerpc/irq: Quieten irq mapping printks powerpc: Enable lockup and hung task detectors in pseries and ppc64 defeconfigs powerpc: Add mpt2sas driver to pseries and ppc64 defconfig powerpc: Disable IRQs off tracer in ppc64 defconfig powerpc: Sync pseries and ppc64 defconfigs powerpc/pseries/hvconsole: Fix dropped console output hvc_console: Improve tty/console put_chars handling powerpc/kdump: Fix timeout in crash_kexec_wait_realmode powerpc/mm: Fix output of total_ram. powerpc/cpufreq: Add cpufreq driver for Momentum Maple boards powerpc: Correct annotations of pmu registration functions ... Fix up trivial Kconfig/Makefile conflicts in arch/powerpc, drivers, and drivers/cpufreq
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig3
-rw-r--r--arch/powerpc/Kconfig.debug15
-rw-r--r--arch/powerpc/Makefile2
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts5
-rw-r--r--arch/powerpc/boot/dts/glacier.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts2
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts280
-rw-r--r--arch/powerpc/boot/dts/p1010si.dtsi376
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts2
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts546
-rw-r--r--arch/powerpc/boot/dts/p2040rdb.dts166
-rw-r--r--arch/powerpc/boot/dts/p2040si.dtsi623
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts214
-rw-r--r--arch/powerpc/boot/dts/p3041si.dtsi660
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts533
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi661
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts215
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi652
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts12
-rw-r--r--arch/powerpc/boot/dts/socrates.dts2
-rw-r--r--arch/powerpc/boot/dts/taishan.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts42
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts2
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts2
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts2
-rw-r--r--arch/powerpc/boot/dts/xpedite5200.dts2
-rw-r--r--arch/powerpc/boot/dts/xpedite5200_xmon.dts2
-rw-r--r--arch/powerpc/boot/treeboot-iss4xx.c23
-rw-r--r--arch/powerpc/configs/44x/iss476-smp_defconfig6
-rw-r--r--arch/powerpc/configs/85xx/p1023rds_defconfig173
-rw-r--r--arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig5
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig187
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig (renamed from arch/powerpc/configs/e55xx_smp_defconfig)0
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig12
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig10
-rw-r--r--arch/powerpc/configs/ppc64_defconfig16
-rw-r--r--arch/powerpc/configs/pseries_defconfig3
-rw-r--r--arch/powerpc/include/asm/dbell.h2
-rw-r--r--arch/powerpc/include/asm/ehv_pic.h40
-rw-r--r--arch/powerpc/include/asm/epapr_hcalls.h502
-rw-r--r--arch/powerpc/include/asm/exception-64e.h52
-rw-r--r--arch/powerpc/include/asm/fsl_hcalls.h655
-rw-r--r--arch/powerpc/include/asm/hvsi.h94
-rw-r--r--arch/powerpc/include/asm/irq.h2
-rw-r--r--arch/powerpc/include/asm/jump_label.h47
-rw-r--r--arch/powerpc/include/asm/mmu.h12
-rw-r--r--arch/powerpc/include/asm/pSeries_reconfig.h2
-rw-r--r--arch/powerpc/include/asm/paca.h7
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h3
-rw-r--r--arch/powerpc/include/asm/processor.h5
-rw-r--r--arch/powerpc/include/asm/reg.h4
-rw-r--r--arch/powerpc/include/asm/setup.h4
-rw-r--r--arch/powerpc/include/asm/smp.h3
-rw-r--r--arch/powerpc/include/asm/udbg.h1
-rw-r--r--arch/powerpc/kernel/Makefile1
-rw-r--r--arch/powerpc/kernel/asm-offsets.c3
-rw-r--r--arch/powerpc/kernel/crash.c6
-rw-r--r--arch/powerpc/kernel/dma.c4
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S22
-rw-r--r--arch/powerpc/kernel/head_44x.S42
-rw-r--r--arch/powerpc/kernel/head_64.S2
-rw-r--r--arch/powerpc/kernel/head_booke.h42
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S49
-rw-r--r--arch/powerpc/kernel/idle_e500.S12
-rw-r--r--arch/powerpc/kernel/irq.c50
-rw-r--r--arch/powerpc/kernel/jump_label.c23
-rw-r--r--arch/powerpc/kernel/misc_64.S4
-rw-r--r--arch/powerpc/kernel/mpc7450-pmu.c2
-rw-r--r--arch/powerpc/kernel/pci-common.c18
-rw-r--r--arch/powerpc/kernel/pci_32.c19
-rw-r--r--arch/powerpc/kernel/perf_event.c2
-rw-r--r--arch/powerpc/kernel/power4-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5-pmu.c2
-rw-r--r--arch/powerpc/kernel/power6-pmu.c2
-rw-r--r--arch/powerpc/kernel/power7-pmu.c2
-rw-r--r--arch/powerpc/kernel/ppc970-pmu.c2
-rw-r--r--arch/powerpc/kernel/process.c4
-rw-r--r--arch/powerpc/kernel/prom.c16
-rw-r--r--arch/powerpc/kernel/setup-common.c27
-rw-r--r--arch/powerpc/kernel/setup_32.c4
-rw-r--r--arch/powerpc/kernel/setup_64.c6
-rw-r--r--arch/powerpc/kernel/smp.c30
-rw-r--r--arch/powerpc/kernel/udbg.c5
-rw-r--r--arch/powerpc/mm/44x_mmu.c13
-rw-r--r--arch/powerpc/mm/init_32.c32
-rw-r--r--arch/powerpc/mm/init_64.c16
-rw-r--r--arch/powerpc/mm/mem.c35
-rw-r--r--arch/powerpc/mm/tlb_hash32.c4
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S206
-rw-r--r--arch/powerpc/mm/tlb_nohash.c64
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig31
-rw-r--r--arch/powerpc/platforms/85xx/Makefile3
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c41
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c3
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c5
-rw-r--r--arch/powerpc/platforms/85xx/p1010rdb.c122
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c18
-rw-r--r--arch/powerpc/platforms/85xx/p1023_rds.c162
-rw-r--r--arch/powerpc/platforms/85xx/p2040_rdb.c88
-rw-r--r--arch/powerpc/platforms/85xx/p3041_ds.c28
-rw-r--r--arch/powerpc/platforms/85xx/p4080_ds.c38
-rw-r--r--arch/powerpc/platforms/85xx/p5020_ds.c32
-rw-r--r--arch/powerpc/platforms/85xx/smp.c30
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c107
-rw-r--r--arch/powerpc/platforms/Kconfig6
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype2
-rw-r--r--arch/powerpc/platforms/iseries/smp.c2
-rw-r--r--arch/powerpc/platforms/maple/setup.c41
-rw-r--r--arch/powerpc/platforms/powermac/setup.c3
-rw-r--r--arch/powerpc/platforms/powermac/smp.c2
-rw-r--r--arch/powerpc/platforms/pseries/dlpar.c10
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-cpu.c10
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c16
-rw-r--r--arch/powerpc/platforms/pseries/hvconsole.c2
-rw-r--r--arch/powerpc/platforms/pseries/lpar.c191
-rw-r--r--arch/powerpc/platforms/pseries/pseries.h3
-rw-r--r--arch/powerpc/platforms/pseries/reconfig.c28
-rw-r--r--arch/powerpc/platforms/pseries/setup.c5
-rw-r--r--arch/powerpc/platforms/pseries/smp.c2
-rw-r--r--arch/powerpc/platforms/wsp/smp.c2
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/ehv_pic.c302
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c83
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c27
-rw-r--r--arch/powerpc/sysdev/fsl_soc.h3
-rw-r--r--arch/powerpc/sysdev/mpic.c38
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c147
128 files changed, 8022 insertions, 1290 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index cdf7a0a64406..374c475e56a3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -135,6 +135,7 @@ config PPC
135 select HAVE_RCU_TABLE_FREE if SMP 135 select HAVE_RCU_TABLE_FREE if SMP
136 select HAVE_SYSCALL_TRACEPOINTS 136 select HAVE_SYSCALL_TRACEPOINTS
137 select HAVE_BPF_JIT if (PPC64 && NET) 137 select HAVE_BPF_JIT if (PPC64 && NET)
138 select HAVE_ARCH_JUMP_LABEL
138 139
139config EARLY_PRINTK 140config EARLY_PRINTK
140 bool 141 bool
@@ -842,7 +843,7 @@ config LOWMEM_CAM_NUM
842 843
843config RELOCATABLE 844config RELOCATABLE
844 bool "Build a relocatable kernel (EXPERIMENTAL)" 845 bool "Build a relocatable kernel (EXPERIMENTAL)"
845 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE 846 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x)
846 help 847 help
847 This builds a kernel image that is capable of running at the 848 This builds a kernel image that is capable of running at the
848 location the kernel is loaded at (some alignment restrictions may 849 location the kernel is loaded at (some alignment restrictions may
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index e72dcf6a421d..067cb8480747 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -167,6 +167,13 @@ config PPC_EARLY_DEBUG_LPAR
167 Select this to enable early debugging for a machine with a HVC 167 Select this to enable early debugging for a machine with a HVC
168 console on vterm 0. 168 console on vterm 0.
169 169
170config PPC_EARLY_DEBUG_LPAR_HVSI
171 bool "LPAR HVSI Console"
172 depends on PPC_PSERIES
173 help
174 Select this to enable early debugging for a machine with a HVSI
175 console on a specified vterm.
176
170config PPC_EARLY_DEBUG_G5 177config PPC_EARLY_DEBUG_G5
171 bool "Apple G5" 178 bool "Apple G5"
172 depends on PPC_PMAC64 179 depends on PPC_PMAC64
@@ -253,6 +260,14 @@ config PPC_EARLY_DEBUG_WSP
253 260
254endchoice 261endchoice
255 262
263config PPC_EARLY_DEBUG_HVSI_VTERMNO
264 hex "vterm number to use with early debug HVSI"
265 depends on PPC_EARLY_DEBUG_LPAR_HVSI
266 default "0x30000000"
267 help
268 You probably want 0x30000000 for your first serial port and
269 0x30000001 for your second one
270
256config PPC_EARLY_DEBUG_44x_PHYSLOW 271config PPC_EARLY_DEBUG_44x_PHYSLOW
257 hex "Low 32 bits of early debug UART physical address" 272 hex "Low 32 bits of early debug UART physical address"
258 depends on PPC_EARLY_DEBUG_44x 273 depends on PPC_EARLY_DEBUG_44x
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index b94740f36b1a..57af16edc192 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -67,7 +67,7 @@ LDFLAGS_vmlinux-yy := -Bstatic
67LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie 67LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie
68LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-yy) 68LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-yy)
69 69
70CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc 70CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=no -mcall-aixdesc
71CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple 71CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
72KBUILD_CPPFLAGS += -Iarch/$(ARCH) 72KBUILD_CPPFLAGS += -Iarch/$(ARCH)
73KBUILD_AFLAGS += -Iarch/$(ARCH) 73KBUILD_AFLAGS += -Iarch/$(ARCH)
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 22dd6ae84da0..3dc75deafbb3 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -143,6 +143,11 @@
143 interrupts = <0x1d 0x4>; 143 interrupts = <0x1d 0x4>;
144 }; 144 };
145 145
146 HWRNG: hwrng@110000 {
147 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
148 reg = <4 0x00110000 0x50>;
149 };
150
146 MAL0: mcmal { 151 MAL0: mcmal {
147 compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 152 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
148 dcr-reg = <0x180 0x062>; 153 dcr-reg = <0x180 0x062>;
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index e618fc4cbc9e..2000060386d7 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -130,12 +130,18 @@
130 }; 130 };
131 131
132 CRYPTO: crypto@180000 { 132 CRYPTO: crypto@180000 {
133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; 133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
134 "amcc,ppc4xx-crypto";
134 reg = <4 0x00180000 0x80400>; 135 reg = <4 0x00180000 0x80400>;
135 interrupt-parent = <&UIC0>; 136 interrupt-parent = <&UIC0>;
136 interrupts = <0x1d 0x4>; 137 interrupts = <0x1d 0x4>;
137 }; 138 };
138 139
140 HWRNG: hwrng@110000 {
141 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
142 reg = <4 0x00110000 0x50>;
143 };
144
139 MAL0: mcmal { 145 MAL0: mcmal {
140 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 146 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
141 dcr-reg = <0x180 0x062>; 147 dcr-reg = <0x180 0x062>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 30cf0e098bb9..647daf8e7291 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -60,6 +60,8 @@
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", 60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus"; 61 "simple-bus";
62 reg = <0xe0005000 0x1000>; 62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
63 65
64 ranges = <0x0 0x0 0xfe000000 0x02000000 66 ranges = <0x0 0x0 0xfe000000 0x02000000
65 0x1 0x0 0xf8000000 0x00008000 67 0x1 0x0 0xf8000000 0x00008000
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
new file mode 100644
index 000000000000..6b33b73a5ba0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -0,0 +1,280 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "p1010si.dtsi"
13
14/ {
15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB";
17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory {
29 device_type = "memory";
30 };
31
32 ifc@ffe1e000 {
33 /* NOR, NAND Flashes and CPLD on board */
34 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
35 0x1 0x0 0x0 0xff800000 0x00010000
36 0x3 0x0 0x0 0xffb00000 0x00000020>;
37
38 nor@0,0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "cfi-flash";
42 reg = <0x0 0x0 0x2000000>;
43 bank-width = <2>;
44 device-width = <1>;
45
46 partition@40000 {
47 /* 256KB for DTB Image */
48 reg = <0x00040000 0x00040000>;
49 label = "NOR DTB Image";
50 };
51
52 partition@80000 {
53 /* 7 MB for Linux Kernel Image */
54 reg = <0x00080000 0x00700000>;
55 label = "NOR Linux Kernel Image";
56 };
57
58 partition@800000 {
59 /* 20MB for JFFS2 based Root file System */
60 reg = <0x00800000 0x01400000>;
61 label = "NOR JFFS2 Root File System";
62 };
63
64 partition@1f00000 {
65 /* This location must not be altered */
66 /* 512KB for u-boot Bootloader Image */
67 /* 512KB for u-boot Environment Variables */
68 reg = <0x01f00000 0x00100000>;
69 label = "NOR U-Boot Image";
70 read-only;
71 };
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,ifc-nand";
78 reg = <0x1 0x0 0x10000>;
79
80 partition@0 {
81 /* This location must not be altered */
82 /* 1MB for u-boot Bootloader Image */
83 reg = <0x0 0x00100000>;
84 label = "NAND U-Boot Image";
85 read-only;
86 };
87
88 partition@100000 {
89 /* 1MB for DTB Image */
90 reg = <0x00100000 0x00100000>;
91 label = "NAND DTB Image";
92 };
93
94 partition@200000 {
95 /* 4MB for Linux Kernel Image */
96 reg = <0x00200000 0x00400000>;
97 label = "NAND Linux Kernel Image";
98 };
99
100 partition@600000 {
101 /* 4MB for Compressed Root file System Image */
102 reg = <0x00600000 0x00400000>;
103 label = "NAND Compressed RFS Image";
104 };
105
106 partition@a00000 {
107 /* 15MB for JFFS2 based Root file System */
108 reg = <0x00a00000 0x00f00000>;
109 label = "NAND JFFS2 Root File System";
110 };
111
112 partition@1900000 {
113 /* 7MB for User Area */
114 reg = <0x01900000 0x00700000>;
115 label = "NAND User area";
116 };
117 };
118
119 cpld@3,0 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,p1010rdb-cpld";
123 reg = <0x3 0x0 0x0000020>;
124 bank-width = <1>;
125 device-width = <1>;
126 };
127 };
128
129 soc@ffe00000 {
130 spi@7000 {
131 flash@0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "spansion,s25sl12801";
135 reg = <0>;
136 spi-max-frequency = <50000000>;
137
138 partition@0 {
139 /* 1MB for u-boot Bootloader Image */
140 /* 1MB for Environment */
141 reg = <0x0 0x00100000>;
142 label = "SPI Flash U-Boot Image";
143 read-only;
144 };
145
146 partition@100000 {
147 /* 512KB for DTB Image */
148 reg = <0x00100000 0x00080000>;
149 label = "SPI Flash DTB Image";
150 };
151
152 partition@180000 {
153 /* 4MB for Linux Kernel Image */
154 reg = <0x00180000 0x00400000>;
155 label = "SPI Flash Linux Kernel Image";
156 };
157
158 partition@580000 {
159 /* 4MB for Compressed RFS Image */
160 reg = <0x00580000 0x00400000>;
161 label = "SPI Flash Compressed RFSImage";
162 };
163
164 partition@980000 {
165 /* 6.5MB for JFFS2 based RFS */
166 reg = <0x00980000 0x00680000>;
167 label = "SPI Flash JFFS2 RFS";
168 };
169 };
170 };
171
172 can0@1c000 {
173 fsl,flexcan-clock-source = "platform";
174 };
175
176 can1@1d000 {
177 fsl,flexcan-clock-source = "platform";
178 };
179
180 usb@22000 {
181 phy_type = "utmi";
182 };
183
184 mdio@24000 {
185 phy0: ethernet-phy@0 {
186 interrupt-parent = <&mpic>;
187 interrupts = <3 1>;
188 reg = <0x1>;
189 };
190
191 phy1: ethernet-phy@1 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x0>;
195 };
196
197 phy2: ethernet-phy@2 {
198 interrupt-parent = <&mpic>;
199 interrupts = <2 1>;
200 reg = <0x2>;
201 };
202 };
203
204 enet0: ethernet@b0000 {
205 phy-handle = <&phy0>;
206 phy-connection-type = "rgmii-id";
207 };
208
209 enet1: ethernet@b1000 {
210 phy-handle = <&phy1>;
211 tbi-handle = <&tbi0>;
212 phy-connection-type = "sgmii";
213 };
214
215 enet2: ethernet@b2000 {
216 phy-handle = <&phy2>;
217 tbi-handle = <&tbi1>;
218 phy-connection-type = "sgmii";
219 };
220 };
221
222 pci0: pcie@ffe09000 {
223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
224 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
225 pcie@0 {
226 reg = <0x0 0x0 0x0 0x0 0x0>;
227 #interrupt-cells = <1>;
228 #size-cells = <2>;
229 #address-cells = <3>;
230 device_type = "pci";
231 interrupt-parent = <&mpic>;
232 interrupts = <16 2>;
233 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
234 interrupt-map = <
235 /* IDSEL 0x0 */
236 0000 0x0 0x0 0x1 &mpic 0x4 0x1
237 0000 0x0 0x0 0x2 &mpic 0x5 0x1
238 0000 0x0 0x0 0x3 &mpic 0x6 0x1
239 0000 0x0 0x0 0x4 &mpic 0x7 0x1
240 >;
241
242 ranges = <0x2000000 0x0 0xa0000000
243 0x2000000 0x0 0xa0000000
244 0x0 0x20000000
245
246 0x1000000 0x0 0x0
247 0x1000000 0x0 0x0
248 0x0 0x100000>;
249 };
250 };
251
252 pci1: pcie@ffe0a000 {
253 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
254 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
255 pcie@0 {
256 reg = <0x0 0x0 0x0 0x0 0x0>;
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 device_type = "pci";
261 interrupt-parent = <&mpic>;
262 interrupts = <16 2>;
263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
264 interrupt-map = <
265 /* IDSEL 0x0 */
266 0000 0x0 0x0 0x1 &mpic 0x4 0x1
267 0000 0x0 0x0 0x2 &mpic 0x5 0x1
268 0000 0x0 0x0 0x3 &mpic 0x6 0x1
269 0000 0x0 0x0 0x4 &mpic 0x7 0x1
270 >;
271 ranges = <0x2000000 0x0 0x80000000
272 0x2000000 0x0 0x80000000
273 0x0 0x20000000
274
275 0x1000000 0x0 0x0
276 0x1000000 0x0 0x0
277 0x0 0x100000>;
278 };
279 };
280};
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
new file mode 100644
index 000000000000..7f51104f2e36
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010si.dtsi
@@ -0,0 +1,376 @@
1/*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
28
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
37
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
45
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
51
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
58
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
65
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
76
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
97
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
117
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
126
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
134
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
142
143 can0@1c000 {
144 compatible = "fsl,flexcan-v1.0";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 fsl,flexcan-clock-divider = <2>;
149 };
150
151 can1@1d000 {
152 compatible = "fsl,flexcan-v1.0";
153 reg = <0x1d000 0x1000>;
154 interrupts = <61 0x2>;
155 interrupt-parent = <&mpic>;
156 fsl,flexcan-clock-divider = <2>;
157 };
158
159 L2: l2-cache-controller@20000 {
160 compatible = "fsl,p1010-l2-cache-controller",
161 "fsl,p1014-l2-cache-controller";
162 reg = <0x20000 0x1000>;
163 cache-line-size = <32>; // 32 bytes
164 cache-size = <0x40000>; // L2,256K
165 interrupt-parent = <&mpic>;
166 interrupts = <16 2>;
167 };
168
169 dma@21300 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
173 reg = <0x21300 0x4>;
174 ranges = <0x0 0x21100 0x200>;
175 cell-index = <0>;
176 dma-channel@0 {
177 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
178 reg = <0x0 0x80>;
179 cell-index = <0>;
180 interrupt-parent = <&mpic>;
181 interrupts = <20 2>;
182 };
183 dma-channel@80 {
184 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <21 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
192 reg = <0x100 0x80>;
193 cell-index = <2>;
194 interrupt-parent = <&mpic>;
195 interrupts = <22 2>;
196 };
197 dma-channel@180 {
198 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
199 reg = <0x180 0x80>;
200 cell-index = <3>;
201 interrupt-parent = <&mpic>;
202 interrupts = <23 2>;
203 };
204 };
205
206 usb@22000 {
207 compatible = "fsl-usb2-dr";
208 reg = <0x22000 0x1000>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupt-parent = <&mpic>;
212 interrupts = <28 0x2>;
213 dr_mode = "host";
214 };
215
216 mdio@24000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,etsec2-mdio";
220 reg = <0x24000 0x1000 0xb0030 0x4>;
221 };
222
223 mdio@25000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,etsec2-tbi";
227 reg = <0x25000 0x1000 0xb1030 0x4>;
228 tbi0: tbi-phy@11 {
229 reg = <0x11>;
230 device_type = "tbi-phy";
231 };
232 };
233
234 mdio@26000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "fsl,etsec2-tbi";
238 reg = <0x26000 0x1000 0xb1030 0x4>;
239 tbi1: tbi-phy@11 {
240 reg = <0x11>;
241 device_type = "tbi-phy";
242 };
243 };
244
245 sdhci@2e000 {
246 compatible = "fsl,esdhc";
247 reg = <0x2e000 0x1000>;
248 interrupts = <72 0x8>;
249 interrupt-parent = <&mpic>;
250 /* Filled in by U-Boot */
251 clock-frequency = <0>;
252 fsl,sdhci-auto-cmd12;
253 };
254
255 enet0: ethernet@b0000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 device_type = "network";
259 model = "eTSEC";
260 compatible = "fsl,etsec2";
261 fsl,num_rx_queues = <0x8>;
262 fsl,num_tx_queues = <0x8>;
263 local-mac-address = [ 00 00 00 00 00 00 ];
264 interrupt-parent = <&mpic>;
265
266 queue-group@0 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb0000 0x1000>;
270 fsl,rx-bit-map = <0xff>;
271 fsl,tx-bit-map = <0xff>;
272 interrupts = <29 2 30 2 34 2>;
273 };
274
275 };
276
277 enet1: ethernet@b1000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "fsl,etsec2";
283 fsl,num_rx_queues = <0x8>;
284 fsl,num_tx_queues = <0x8>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupt-parent = <&mpic>;
287
288 queue-group@0 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 reg = <0xb1000 0x1000>;
292 fsl,rx-bit-map = <0xff>;
293 fsl,tx-bit-map = <0xff>;
294 interrupts = <35 2 36 2 40 2>;
295 };
296
297 };
298
299 enet2: ethernet@b2000 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 device_type = "network";
303 model = "eTSEC";
304 compatible = "fsl,etsec2";
305 fsl,num_rx_queues = <0x8>;
306 fsl,num_tx_queues = <0x8>;
307 local-mac-address = [ 00 00 00 00 00 00 ];
308 interrupt-parent = <&mpic>;
309
310 queue-group@0 {
311 #address-cells = <1>;
312 #size-cells = <1>;
313 reg = <0xb2000 0x1000>;
314 fsl,rx-bit-map = <0xff>;
315 fsl,tx-bit-map = <0xff>;
316 interrupts = <31 2 32 2 33 2>;
317 };
318
319 };
320
321 mpic: pic@40000 {
322 interrupt-controller;
323 #address-cells = <0>;
324 #interrupt-cells = <2>;
325 reg = <0x40000 0x40000>;
326 compatible = "chrp,open-pic";
327 device_type = "open-pic";
328 };
329
330 msi@41600 {
331 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
332 reg = <0x41600 0x80>;
333 msi-available-ranges = <0 0x100>;
334 interrupts = <
335 0xe0 0
336 0xe1 0
337 0xe2 0
338 0xe3 0
339 0xe4 0
340 0xe5 0
341 0xe6 0
342 0xe7 0>;
343 interrupt-parent = <&mpic>;
344 };
345
346 global-utilities@e0000 { //global utilities block
347 compatible = "fsl,p1010-guts";
348 reg = <0xe0000 0x1000>;
349 fsl,has-rstcr;
350 };
351 };
352
353 pci0: pcie@ffe09000 {
354 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
355 device_type = "pci";
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
367 device_type = "pci";
368 #size-cells = <2>;
369 #address-cells = <3>;
370 reg = <0 0xffe0a000 0 0x1000>;
371 bus-range = <0 255>;
372 clock-frequency = <33333333>;
373 interrupt-parent = <&mpic>;
374 interrupts = <16 2>;
375 };
376};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 98d9426d4b85..1be9743ab5e0 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -412,7 +412,6 @@
412 fsl,magic-packet; 412 fsl,magic-packet;
413 fsl,wake-on-filer; 413 fsl,wake-on-filer;
414 local-mac-address = [ 00 00 00 00 00 00 ]; 414 local-mac-address = [ 00 00 00 00 00 00 ];
415 fixed-link = <1 1 1000 0 0>;
416 phy-handle = <&phy0>; 415 phy-handle = <&phy0>;
417 phy-connection-type = "rgmii-id"; 416 phy-connection-type = "rgmii-id";
418 queue-group@0{ 417 queue-group@0{
@@ -439,7 +438,6 @@
439 fsl,num_rx_queues = <0x8>; 438 fsl,num_rx_queues = <0x8>;
440 fsl,num_tx_queues = <0x8>; 439 fsl,num_tx_queues = <0x8>;
441 local-mac-address = [ 00 00 00 00 00 00 ]; 440 local-mac-address = [ 00 00 00 00 00 00 ];
442 fixed-link = <1 1 1000 0 0>;
443 phy-handle = <&phy1>; 441 phy-handle = <&phy1>;
444 phy-connection-type = "rgmii-id"; 442 phy-connection-type = "rgmii-id";
445 queue-group@0{ 443 queue-group@0{
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
new file mode 100644
index 000000000000..bfa96aa8f2ca
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -0,0 +1,546 @@
1/*
2 * P1023 RDS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Author: Roy Zang <tie-fei.zang@freescale.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of Freescale Semiconductor nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation, either version 2 of that License or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
26 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/dts-v1/;
38
39/ {
40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 aliases {
46 serial0 = &serial0;
47 serial1 = &serial1;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51
52 crypto = &crypto;
53 sec_jr0 = &sec_jr0;
54 sec_jr1 = &sec_jr1;
55 sec_jr2 = &sec_jr2;
56 sec_jr3 = &sec_jr3;
57 rtic_a = &rtic_a;
58 rtic_b = &rtic_b;
59 rtic_c = &rtic_c;
60 rtic_d = &rtic_d;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,P1023@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 next-level-cache = <&L2>;
71 };
72
73 cpu1: PowerPC,P1023@1 {
74 device_type = "cpu";
75 reg = <0x1>;
76 next-level-cache = <&L2>;
77 };
78 };
79
80 memory {
81 device_type = "memory";
82 };
83
84 soc@ff600000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 device_type = "soc";
88 compatible = "fsl,p1023-immr", "simple-bus";
89 ranges = <0x0 0x0 0xff600000 0x200000>;
90 bus-frequency = <0>; // Filled out by uboot.
91
92 ecm-law@0 {
93 compatible = "fsl,ecm-law";
94 reg = <0x0 0x1000>;
95 fsl,num-laws = <12>;
96 };
97
98 ecm@1000 {
99 compatible = "fsl,p1023-ecm", "fsl,ecm";
100 reg = <0x1000 0x1000>;
101 interrupts = <16 2>;
102 interrupt-parent = <&mpic>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,p1023-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupt-parent = <&mpic>;
109 interrupts = <16 2>;
110 };
111
112 i2c@3000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 cell-index = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <43 2>;
119 interrupt-parent = <&mpic>;
120 dfsrr;
121 rtc@68 {
122 compatible = "dallas,ds1374";
123 reg = <0x68>;
124 };
125 };
126
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3100 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136 };
137
138 serial0: serial@4500 {
139 cell-index = <0>;
140 device_type = "serial";
141 compatible = "ns16550";
142 reg = <0x4500 0x100>;
143 clock-frequency = <0>;
144 interrupts = <42 2>;
145 interrupt-parent = <&mpic>;
146 };
147
148 serial1: serial@4600 {
149 cell-index = <1>;
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <0x4600 0x100>;
153 clock-frequency = <0>;
154 interrupts = <42 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 spi@7000 {
159 cell-index = <0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
163 reg = <0x7000 0x1000>;
164 interrupts = <59 0x2>;
165 interrupt-parent = <&mpic>;
166 fsl,espi-num-chipselects = <4>;
167
168 fsl_dataflash@0 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "atmel,at45db081d";
172 reg = <0>;
173 spi-max-frequency = <40000000>; /* input clock */
174 partition@u-boot {
175 /* 512KB for u-boot Bootloader Image */
176 label = "u-boot-spi";
177 reg = <0x00000000 0x00080000>;
178 read-only;
179 };
180 partition@dtb {
181 /* 512KB for DTB Image */
182 label = "dtb-spi";
183 reg = <0x00080000 0x00080000>;
184 read-only;
185 };
186 };
187 };
188
189 gpio: gpio-controller@f000 {
190 #gpio-cells = <2>;
191 compatible = "fsl,qoriq-gpio";
192 reg = <0xf000 0x100>;
193 interrupts = <47 0x2>;
194 interrupt-parent = <&mpic>;
195 gpio-controller;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,p1023-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x40000>; // L2,256K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,eloplus-dma-channel";
216 reg = <0x0 0x80>;
217 cell-index = <0>;
218 interrupt-parent = <&mpic>;
219 interrupts = <20 2>;
220 };
221 dma-channel@80 {
222 compatible = "fsl,eloplus-dma-channel";
223 reg = <0x80 0x80>;
224 cell-index = <1>;
225 interrupt-parent = <&mpic>;
226 interrupts = <21 2>;
227 };
228 dma-channel@100 {
229 compatible = "fsl,eloplus-dma-channel";
230 reg = <0x100 0x80>;
231 cell-index = <2>;
232 interrupt-parent = <&mpic>;
233 interrupts = <22 2>;
234 };
235 dma-channel@180 {
236 compatible = "fsl,eloplus-dma-channel";
237 reg = <0x180 0x80>;
238 cell-index = <3>;
239 interrupt-parent = <&mpic>;
240 interrupts = <23 2>;
241 };
242 };
243
244 usb@22000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl-usb2-dr";
248 reg = <0x22000 0x1000>;
249 interrupt-parent = <&mpic>;
250 interrupts = <28 0x2>;
251 dr_mode = "host";
252 phy_type = "ulpi";
253 };
254
255 crypto: crypto@300000 {
256 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 reg = <0x30000 0x10000>;
260 ranges = <0 0x30000 0x10000>;
261 interrupt-parent = <&mpic>;
262 interrupts = <58 2>;
263
264 sec_jr0: jr@1000 {
265 compatible = "fsl,sec-v4.2-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x1000 0x1000>;
268 interrupts = <45 2>;
269 };
270
271 sec_jr1: jr@2000 {
272 compatible = "fsl,sec-v4.2-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x2000 0x1000>;
275 interrupts = <45 2>;
276 };
277
278 sec_jr2: jr@3000 {
279 compatible = "fsl,sec-v4.2-job-ring",
280 "fsl,sec-v4.0-job-ring";
281 reg = <0x3000 0x1000>;
282 interrupts = <57 2>;
283 };
284
285 sec_jr3: jr@4000 {
286 compatible = "fsl,sec-v4.2-job-ring",
287 "fsl,sec-v4.0-job-ring";
288 reg = <0x4000 0x1000>;
289 interrupts = <57 2>;
290 };
291
292 rtic@6000 {
293 compatible = "fsl,sec-v4.2-rtic",
294 "fsl,sec-v4.0-rtic";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x6000 0x100>;
298 ranges = <0x0 0x6100 0xe00>;
299
300 rtic_a: rtic-a@0 {
301 compatible = "fsl,sec-v4.2-rtic-memory",
302 "fsl,sec-v4.0-rtic-memory";
303 reg = <0x00 0x20 0x100 0x80>;
304 };
305
306 rtic_b: rtic-b@20 {
307 compatible = "fsl,sec-v4.2-rtic-memory",
308 "fsl,sec-v4.0-rtic-memory";
309 reg = <0x20 0x20 0x200 0x80>;
310 };
311
312 rtic_c: rtic-c@40 {
313 compatible = "fsl,sec-v4.2-rtic-memory",
314 "fsl,sec-v4.0-rtic-memory";
315 reg = <0x40 0x20 0x300 0x80>;
316 };
317
318 rtic_d: rtic-d@60 {
319 compatible = "fsl,sec-v4.2-rtic-memory",
320 "fsl,sec-v4.0-rtic-memory";
321 reg = <0x60 0x20 0x500 0x80>;
322 };
323 };
324 };
325
326 power@e0070{
327 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
328 "fsl,p1022-pmc";
329 reg = <0xe0070 0x20>;
330 etsec1_clk: soc-clk@B0{
331 fsl,pmcdr-mask = <0x00000080>;
332 };
333 etsec2_clk: soc-clk@B1{
334 fsl,pmcdr-mask = <0x00000040>;
335 };
336 etsec3_clk: soc-clk@B2{
337 fsl,pmcdr-mask = <0x00000020>;
338 };
339 };
340
341 mpic: pic@40000 {
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <2>;
345 reg = <0x40000 0x40000>;
346 compatible = "chrp,open-pic";
347 device_type = "open-pic";
348 };
349
350 msi@41600 {
351 compatible = "fsl,p1023-msi", "fsl,mpic-msi";
352 reg = <0x41600 0x80>;
353 msi-available-ranges = <0 0x100>;
354 interrupts = <
355 0xe0 0
356 0xe1 0
357 0xe2 0
358 0xe3 0
359 0xe4 0
360 0xe5 0
361 0xe6 0
362 0xe7 0>;
363 interrupt-parent = <&mpic>;
364 };
365
366 global-utilities@e0000 { //global utilities block
367 compatible = "fsl,p1023-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 };
372
373 localbus@ff605000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
377 reg = <0 0xff605000 0 0x1000>;
378 interrupts = <19 2>;
379 interrupt-parent = <&mpic>;
380
381 /* NOR Flash, BCSR */
382 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
383 0x1 0x0 0x0 0xe0000000 0x00008000>;
384
385 nor@0,0 {
386 #address-cells = <1>;
387 #size-cells = <1>;
388 compatible = "cfi-flash";
389 reg = <0x0 0x0 0x02000000>;
390 bank-width = <1>;
391 device-width = <1>;
392 partition@0 {
393 label = "ramdisk";
394 reg = <0x00000000 0x01c00000>;
395 };
396 partition@1c00000 {
397 label = "kernel";
398 reg = <0x01c00000 0x002e0000>;
399 };
400 partiton@1ee0000 {
401 label = "dtb";
402 reg = <0x01ee0000 0x00020000>;
403 };
404 partition@1f00000 {
405 label = "firmware";
406 reg = <0x01f00000 0x00080000>;
407 read-only;
408 };
409 partition@1f80000 {
410 label = "u-boot";
411 reg = <0x01f80000 0x00080000>;
412 read-only;
413 };
414 };
415
416 fpga@1,0 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "fsl,p1023rds-fpga";
420 reg = <1 0 0x8000>;
421 ranges = <0 1 0 0x8000>;
422
423 bcsr@20 {
424 compatible = "fsl,p1023rds-bcsr";
425 reg = <0x20 0x20>;
426 };
427 };
428 };
429
430 pci0: pcie@ff60a000 {
431 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
432 cell-index = <1>;
433 device_type = "pci";
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0 0xff60a000 0 0x1000>;
437 bus-range = <0 255>;
438 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
439 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
440 clock-frequency = <33333333>;
441 interrupt-parent = <&mpic>;
442 interrupts = <16 2>;
443 pcie@0 {
444 reg = <0x0 0x0 0x0 0x0 0x0>;
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 device_type = "pci";
449 interrupt-parent = <&mpic>;
450 interrupts = <16 2>;
451 interrupt-map-mask = <0xf800 0 0 7>;
452 interrupt-map = <
453 /* IDSEL 0x0 */
454 0000 0 0 1 &mpic 0 1
455 0000 0 0 2 &mpic 1 1
456 0000 0 0 3 &mpic 2 1
457 0000 0 0 4 &mpic 3 1
458 >;
459 ranges = <0x2000000 0x0 0xc0000000
460 0x2000000 0x0 0xc0000000
461 0x0 0x20000000
462
463 0x1000000 0x0 0x0
464 0x1000000 0x0 0x0
465 0x0 0x100000>;
466 };
467 };
468
469 pci1: pcie@ff609000 {
470 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
471 cell-index = <2>;
472 device_type = "pci";
473 #size-cells = <2>;
474 #address-cells = <3>;
475 reg = <0 0xff609000 0 0x1000>;
476 bus-range = <0 255>;
477 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
478 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
479 clock-frequency = <33333333>;
480 interrupt-parent = <&mpic>;
481 interrupts = <16 2>;
482 pcie@0 {
483 reg = <0x0 0x0 0x0 0x0 0x0>;
484 #interrupt-cells = <1>;
485 #size-cells = <2>;
486 #address-cells = <3>;
487 device_type = "pci";
488 interrupt-parent = <&mpic>;
489 interrupts = <16 2>;
490 interrupt-map-mask = <0xf800 0 0 7>;
491 interrupt-map = <
492 /* IDSEL 0x0 */
493 0000 0 0 1 &mpic 4 1
494 0000 0 0 2 &mpic 5 1
495 0000 0 0 3 &mpic 6 1
496 0000 0 0 4 &mpic 7 1
497 >;
498 ranges = <0x2000000 0x0 0xa0000000
499 0x2000000 0x0 0xa0000000
500 0x0 0x20000000
501
502 0x1000000 0x0 0x0
503 0x1000000 0x0 0x0
504 0x0 0x100000>;
505 };
506 };
507
508 pci2: pcie@ff60b000 {
509 cell-index = <3>;
510 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
511 device_type = "pci";
512 #size-cells = <2>;
513 #address-cells = <3>;
514 reg = <0 0xff60b000 0 0x1000>;
515 bus-range = <0 255>;
516 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
517 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
518 clock-frequency = <33333333>;
519 interrupt-parent = <&mpic>;
520 interrupts = <16 2>;
521 pcie@0 {
522 reg = <0x0 0x0 0x0 0x0 0x0>;
523 #interrupt-cells = <1>;
524 #size-cells = <2>;
525 #address-cells = <3>;
526 device_type = "pci";
527 interrupt-parent = <&mpic>;
528 interrupts = <16 2>;
529 interrupt-map-mask = <0xf800 0 0 7>;
530 interrupt-map = <
531 /* IDSEL 0x0 */
532 0000 0 0 1 &mpic 8 1
533 0000 0 0 2 &mpic 9 1
534 0000 0 0 3 &mpic 10 1
535 0000 0 0 4 &mpic 11 1
536 >;
537 ranges = <0x2000000 0x0 0x80000000
538 0x2000000 0x0 0x80000000
539 0x0 0x20000000
540
541 0x1000000 0x0 0x0
542 0x1000000 0x0 0x0
543 0x0 0x100000>;
544 };
545 };
546};
diff --git a/arch/powerpc/boot/dts/p2040rdb.dts b/arch/powerpc/boot/dts/p2040rdb.dts
new file mode 100644
index 000000000000..7d84e391c632
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040rdb.dts
@@ -0,0 +1,166 @@
1/*
2 * P2040RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p2040si.dtsi"
36
37/ {
38 model = "fsl,P2040RDB";
39 compatible = "fsl,P2040RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118000 {
79 lm75b@48 {
80 compatible = "nxp,lm75a";
81 reg = <0x48>;
82 };
83 eeprom@50 {
84 compatible = "at24,24c256";
85 reg = <0x50>;
86 };
87 rtc@68 {
88 compatible = "pericom,pt7c4338";
89 reg = <0x68>;
90 };
91 };
92
93 i2c@118100 {
94 eeprom@50 {
95 compatible = "at24,24c256";
96 reg = <0x50>;
97 };
98 };
99
100 usb0: usb@210000 {
101 phy_type = "utmi";
102 };
103
104 usb1: usb@211000 {
105 dr_mode = "host";
106 phy_type = "utmi";
107 };
108 };
109
110 localbus@ffe124000 {
111 reg = <0xf 0xfe124000 0 0x1000>;
112 ranges = <0 0 0xf 0xe8000000 0x08000000>;
113
114 flash@0,0 {
115 compatible = "cfi-flash";
116 reg = <0 0 0x08000000>;
117 bank-width = <2>;
118 device-width = <2>;
119 };
120 };
121
122 pci0: pcie@ffe200000 {
123 reg = <0xf 0xfe200000 0 0x1000>;
124 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
125 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126 pcie@0 {
127 ranges = <0x02000000 0 0xe0000000
128 0x02000000 0 0xe0000000
129 0 0x20000000
130
131 0x01000000 0 0x00000000
132 0x01000000 0 0x00000000
133 0 0x00010000>;
134 };
135 };
136
137 pci1: pcie@ffe201000 {
138 reg = <0xf 0xfe201000 0 0x1000>;
139 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
140 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141 pcie@0 {
142 ranges = <0x02000000 0 0xe0000000
143 0x02000000 0 0xe0000000
144 0 0x20000000
145
146 0x01000000 0 0x00000000
147 0x01000000 0 0x00000000
148 0 0x00010000>;
149 };
150 };
151
152 pci2: pcie@ffe202000 {
153 reg = <0xf 0xfe202000 0 0x1000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
155 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x20000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166};
diff --git a/arch/powerpc/boot/dts/p2040si.dtsi b/arch/powerpc/boot/dts/p2040si.dtsi
new file mode 100644
index 000000000000..5fdbb24c0763
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040si.dtsi
@@ -0,0 +1,623 @@
1/*
2 * P2040 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P2040";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 };
111
112 soc: soc@ffe000000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 device_type = "soc";
116 compatible = "simple-bus";
117 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
118 reg = <0xf 0xfe000000 0 0x00001000>;
119
120 soc-sram-error {
121 compatible = "fsl,soc-sram-error";
122 interrupts = <16 2 1 29>;
123 };
124
125 corenet-law@0 {
126 compatible = "fsl,corenet-law";
127 reg = <0x0 0x1000>;
128 fsl,num-laws = <32>;
129 };
130
131 memory-controller@8000 {
132 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
133 reg = <0x8000 0x1000>;
134 interrupts = <16 2 1 23>;
135 };
136
137 cpc: l3-cache-controller@10000 {
138 compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
139 reg = <0x10000 0x1000>;
140 interrupts = <16 2 1 27>;
141 };
142
143 corenet-cf@18000 {
144 compatible = "fsl,corenet-cf";
145 reg = <0x18000 0x1000>;
146 interrupts = <16 2 1 31>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,pamu-v1.0", "fsl,pamu";
153 reg = <0x20000 0x4000>;
154 interrupts = <
155 24 2 0 0
156 16 2 1 30>;
157 };
158
159 mpic: pic@40000 {
160 clock-frequency = <0>;
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <4>;
164 reg = <0x40000 0x40000>;
165 compatible = "fsl,mpic", "chrp,open-pic";
166 device_type = "open-pic";
167 };
168
169 msi0: msi@41600 {
170 compatible = "fsl,mpic-msi";
171 reg = <0x41600 0x200>;
172 msi-available-ranges = <0 0x100>;
173 interrupts = <
174 0xe0 0 0 0
175 0xe1 0 0 0
176 0xe2 0 0 0
177 0xe3 0 0 0
178 0xe4 0 0 0
179 0xe5 0 0 0
180 0xe6 0 0 0
181 0xe7 0 0 0>;
182 };
183
184 msi1: msi@41800 {
185 compatible = "fsl,mpic-msi";
186 reg = <0x41800 0x200>;
187 msi-available-ranges = <0 0x100>;
188 interrupts = <
189 0xe8 0 0 0
190 0xe9 0 0 0
191 0xea 0 0 0
192 0xeb 0 0 0
193 0xec 0 0 0
194 0xed 0 0 0
195 0xee 0 0 0
196 0xef 0 0 0>;
197 };
198
199 msi2: msi@41a00 {
200 compatible = "fsl,mpic-msi";
201 reg = <0x41a00 0x200>;
202 msi-available-ranges = <0 0x100>;
203 interrupts = <
204 0xf0 0 0 0
205 0xf1 0 0 0
206 0xf2 0 0 0
207 0xf3 0 0 0
208 0xf4 0 0 0
209 0xf5 0 0 0
210 0xf6 0 0 0
211 0xf7 0 0 0>;
212 };
213
214 guts: global-utilities@e0000 {
215 compatible = "fsl,qoriq-device-config-1.0";
216 reg = <0xe0000 0xe00>;
217 fsl,has-rstcr;
218 #sleep-cells = <1>;
219 fsl,liodn-bits = <12>;
220 };
221
222 pins: global-utilities@e0e00 {
223 compatible = "fsl,qoriq-pin-control-1.0";
224 reg = <0xe0e00 0x200>;
225 #sleep-cells = <2>;
226 };
227
228 clockgen: global-utilities@e1000 {
229 compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
230 reg = <0xe1000 0x1000>;
231 clock-frequency = <0>;
232 };
233
234 rcpm: global-utilities@e2000 {
235 compatible = "fsl,qoriq-rcpm-1.0";
236 reg = <0xe2000 0x1000>;
237 #sleep-cells = <1>;
238 };
239
240 sfp: sfp@e8000 {
241 compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
242 reg = <0xe8000 0x1000>;
243 };
244
245 serdes: serdes@ea000 {
246 compatible = "fsl,p2040-serdes";
247 reg = <0xea000 0x1000>;
248 };
249
250 dma0: dma@100300 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
254 reg = <0x100300 0x4>;
255 ranges = <0x0 0x100100 0x200>;
256 cell-index = <0>;
257 dma-channel@0 {
258 compatible = "fsl,p2040-dma-channel",
259 "fsl,eloplus-dma-channel";
260 reg = <0x0 0x80>;
261 cell-index = <0>;
262 interrupts = <28 2 0 0>;
263 };
264 dma-channel@80 {
265 compatible = "fsl,p2040-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x80 0x80>;
268 cell-index = <1>;
269 interrupts = <29 2 0 0>;
270 };
271 dma-channel@100 {
272 compatible = "fsl,p2040-dma-channel",
273 "fsl,eloplus-dma-channel";
274 reg = <0x100 0x80>;
275 cell-index = <2>;
276 interrupts = <30 2 0 0>;
277 };
278 dma-channel@180 {
279 compatible = "fsl,p2040-dma-channel",
280 "fsl,eloplus-dma-channel";
281 reg = <0x180 0x80>;
282 cell-index = <3>;
283 interrupts = <31 2 0 0>;
284 };
285 };
286
287 dma1: dma@101300 {
288 #address-cells = <1>;
289 #size-cells = <1>;
290 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
291 reg = <0x101300 0x4>;
292 ranges = <0x0 0x101100 0x200>;
293 cell-index = <1>;
294 dma-channel@0 {
295 compatible = "fsl,p2040-dma-channel",
296 "fsl,eloplus-dma-channel";
297 reg = <0x0 0x80>;
298 cell-index = <0>;
299 interrupts = <32 2 0 0>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,p2040-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <33 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,p2040-dma-channel",
310 "fsl,eloplus-dma-channel";
311 reg = <0x100 0x80>;
312 cell-index = <2>;
313 interrupts = <34 2 0 0>;
314 };
315 dma-channel@180 {
316 compatible = "fsl,p2040-dma-channel",
317 "fsl,eloplus-dma-channel";
318 reg = <0x180 0x80>;
319 cell-index = <3>;
320 interrupts = <35 2 0 0>;
321 };
322 };
323
324 spi@110000 {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
328 reg = <0x110000 0x1000>;
329 interrupts = <53 0x2 0 0>;
330 fsl,espi-num-chipselects = <4>;
331
332 };
333
334 sdhc: sdhc@114000 {
335 compatible = "fsl,p2040-esdhc", "fsl,esdhc";
336 reg = <0x114000 0x1000>;
337 interrupts = <48 2 0 0>;
338 sdhci,auto-cmd12;
339 clock-frequency = <0>;
340 };
341
342
343 i2c@118000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 cell-index = <0>;
347 compatible = "fsl-i2c";
348 reg = <0x118000 0x100>;
349 interrupts = <38 2 0 0>;
350 dfsrr;
351 };
352
353 i2c@118100 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 cell-index = <1>;
357 compatible = "fsl-i2c";
358 reg = <0x118100 0x100>;
359 interrupts = <38 2 0 0>;
360 dfsrr;
361 };
362
363 i2c@119000 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 cell-index = <2>;
367 compatible = "fsl-i2c";
368 reg = <0x119000 0x100>;
369 interrupts = <39 2 0 0>;
370 dfsrr;
371 };
372
373 i2c@119100 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 cell-index = <3>;
377 compatible = "fsl-i2c";
378 reg = <0x119100 0x100>;
379 interrupts = <39 2 0 0>;
380 dfsrr;
381 };
382
383 serial0: serial@11c500 {
384 cell-index = <0>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11c500 0x100>;
388 clock-frequency = <0>;
389 interrupts = <36 2 0 0>;
390 };
391
392 serial1: serial@11c600 {
393 cell-index = <1>;
394 device_type = "serial";
395 compatible = "ns16550";
396 reg = <0x11c600 0x100>;
397 clock-frequency = <0>;
398 interrupts = <36 2 0 0>;
399 };
400
401 serial2: serial@11d500 {
402 cell-index = <2>;
403 device_type = "serial";
404 compatible = "ns16550";
405 reg = <0x11d500 0x100>;
406 clock-frequency = <0>;
407 interrupts = <37 2 0 0>;
408 };
409
410 serial3: serial@11d600 {
411 cell-index = <3>;
412 device_type = "serial";
413 compatible = "ns16550";
414 reg = <0x11d600 0x100>;
415 clock-frequency = <0>;
416 interrupts = <37 2 0 0>;
417 };
418
419 gpio0: gpio@130000 {
420 compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
421 reg = <0x130000 0x1000>;
422 interrupts = <55 2 0 0>;
423 #gpio-cells = <2>;
424 gpio-controller;
425 };
426
427 usb0: usb@210000 {
428 compatible = "fsl,p2040-usb2-mph",
429 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
430 reg = <0x210000 0x1000>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 interrupts = <44 0x2 0 0>;
434 port0;
435 };
436
437 usb1: usb@211000 {
438 compatible = "fsl,p2040-usb2-dr",
439 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
440 reg = <0x211000 0x1000>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 interrupts = <45 0x2 0 0>;
444 };
445
446 sata@220000 {
447 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
448 reg = <0x220000 0x1000>;
449 interrupts = <68 0x2 0 0>;
450 };
451
452 sata@221000 {
453 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
454 reg = <0x221000 0x1000>;
455 interrupts = <69 0x2 0 0>;
456 };
457
458 crypto: crypto@300000 {
459 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
460 #address-cells = <1>;
461 #size-cells = <1>;
462 reg = <0x300000 0x10000>;
463 ranges = <0 0x300000 0x10000>;
464 interrupts = <92 2 0 0>;
465
466 sec_jr0: jr@1000 {
467 compatible = "fsl,sec-v4.2-job-ring",
468 "fsl,sec-v4.0-job-ring";
469 reg = <0x1000 0x1000>;
470 interrupts = <88 2 0 0>;
471 };
472
473 sec_jr1: jr@2000 {
474 compatible = "fsl,sec-v4.2-job-ring",
475 "fsl,sec-v4.0-job-ring";
476 reg = <0x2000 0x1000>;
477 interrupts = <89 2 0 0>;
478 };
479
480 sec_jr2: jr@3000 {
481 compatible = "fsl,sec-v4.2-job-ring",
482 "fsl,sec-v4.0-job-ring";
483 reg = <0x3000 0x1000>;
484 interrupts = <90 2 0 0>;
485 };
486
487 sec_jr3: jr@4000 {
488 compatible = "fsl,sec-v4.2-job-ring",
489 "fsl,sec-v4.0-job-ring";
490 reg = <0x4000 0x1000>;
491 interrupts = <91 2 0 0>;
492 };
493
494 rtic@6000 {
495 compatible = "fsl,sec-v4.2-rtic",
496 "fsl,sec-v4.0-rtic";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x6000 0x100>;
500 ranges = <0x0 0x6100 0xe00>;
501
502 rtic_a: rtic-a@0 {
503 compatible = "fsl,sec-v4.2-rtic-memory",
504 "fsl,sec-v4.0-rtic-memory";
505 reg = <0x00 0x20 0x100 0x80>;
506 };
507
508 rtic_b: rtic-b@20 {
509 compatible = "fsl,sec-v4.2-rtic-memory",
510 "fsl,sec-v4.0-rtic-memory";
511 reg = <0x20 0x20 0x200 0x80>;
512 };
513
514 rtic_c: rtic-c@40 {
515 compatible = "fsl,sec-v4.2-rtic-memory",
516 "fsl,sec-v4.0-rtic-memory";
517 reg = <0x40 0x20 0x300 0x80>;
518 };
519
520 rtic_d: rtic-d@60 {
521 compatible = "fsl,sec-v4.2-rtic-memory",
522 "fsl,sec-v4.0-rtic-memory";
523 reg = <0x60 0x20 0x500 0x80>;
524 };
525 };
526 };
527
528 sec_mon: sec_mon@314000 {
529 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
530 reg = <0x314000 0x1000>;
531 interrupts = <93 2 0 0>;
532 };
533
534 };
535
536 localbus@ffe124000 {
537 compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
538 interrupts = <25 2 0 0>;
539 #address-cells = <2>;
540 #size-cells = <1>;
541 };
542
543 pci0: pcie@ffe200000 {
544 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
545 device_type = "pci";
546 #size-cells = <2>;
547 #address-cells = <3>;
548 bus-range = <0x0 0xff>;
549 clock-frequency = <0x1fca055>;
550 fsl,msi = <&msi0>;
551 interrupts = <16 2 1 15>;
552 pcie@0 {
553 reg = <0 0 0 0 0>;
554 #interrupt-cells = <1>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 interrupts = <16 2 1 15>;
559 interrupt-map-mask = <0xf800 0 0 7>;
560 interrupt-map = <
561 /* IDSEL 0x0 */
562 0000 0 0 1 &mpic 40 1 0 0
563 0000 0 0 2 &mpic 1 1 0 0
564 0000 0 0 3 &mpic 2 1 0 0
565 0000 0 0 4 &mpic 3 1 0 0
566 >;
567 };
568 };
569
570 pci1: pcie@ffe201000 {
571 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
572 device_type = "pci";
573 #size-cells = <2>;
574 #address-cells = <3>;
575 bus-range = <0 0xff>;
576 clock-frequency = <0x1fca055>;
577 fsl,msi = <&msi1>;
578 interrupts = <16 2 1 14>;
579 pcie@0 {
580 reg = <0 0 0 0 0>;
581 #interrupt-cells = <1>;
582 #size-cells = <2>;
583 #address-cells = <3>;
584 device_type = "pci";
585 interrupts = <16 2 1 14>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 41 1 0 0
590 0000 0 0 2 &mpic 5 1 0 0
591 0000 0 0 3 &mpic 6 1 0 0
592 0000 0 0 4 &mpic 7 1 0 0
593 >;
594 };
595 };
596
597 pci2: pcie@ffe202000 {
598 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
599 device_type = "pci";
600 #size-cells = <2>;
601 #address-cells = <3>;
602 bus-range = <0x0 0xff>;
603 clock-frequency = <0x1fca055>;
604 fsl,msi = <&msi2>;
605 interrupts = <16 2 1 13>;
606 pcie@0 {
607 reg = <0 0 0 0 0>;
608 #interrupt-cells = <1>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 interrupts = <16 2 1 13>;
613 interrupt-map-mask = <0xf800 0 0 7>;
614 interrupt-map = <
615 /* IDSEL 0x0 */
616 0000 0 0 1 &mpic 42 1 0 0
617 0000 0 0 2 &mpic 9 1 0 0
618 0000 0 0 3 &mpic 10 1 0 0
619 0000 0 0 4 &mpic 11 1 0 0
620 >;
621 };
622 };
623};
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
new file mode 100644
index 000000000000..69cae674f396
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -0,0 +1,214 @@
1/*
2 * P3041DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p3041si.dtsi"
36
37/ {
38 model = "fsl,P3041DS";
39 compatible = "fsl,P3041DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118100 {
79 eeprom@51 {
80 compatible = "at24,24c256";
81 reg = <0x51>;
82 };
83 eeprom@52 {
84 compatible = "at24,24c256";
85 reg = <0x52>;
86 };
87 };
88
89 i2c@119100 {
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 interrupts = <0x1 0x1 0 0>;
94 };
95 };
96 };
97
98 localbus@ffe124000 {
99 reg = <0xf 0xfe124000 0 0x1000>;
100 ranges = <0 0 0xf 0xe8000000 0x08000000
101 2 0 0xf 0xffa00000 0x00040000
102 3 0 0xf 0xffdf0000 0x00008000>;
103
104 flash@0,0 {
105 compatible = "cfi-flash";
106 reg = <0 0 0x08000000>;
107 bank-width = <2>;
108 device-width = <2>;
109 };
110
111 nand@2,0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,elbc-fcm-nand";
115 reg = <0x2 0x0 0x40000>;
116
117 partition@0 {
118 label = "NAND U-Boot Image";
119 reg = <0x0 0x02000000>;
120 read-only;
121 };
122
123 partition@2000000 {
124 label = "NAND Root File System";
125 reg = <0x02000000 0x10000000>;
126 };
127
128 partition@12000000 {
129 label = "NAND Compressed RFS Image";
130 reg = <0x12000000 0x08000000>;
131 };
132
133 partition@1a000000 {
134 label = "NAND Linux Kernel Image";
135 reg = <0x1a000000 0x04000000>;
136 };
137
138 partition@1e000000 {
139 label = "NAND DTB Image";
140 reg = <0x1e000000 0x01000000>;
141 };
142
143 partition@1f000000 {
144 label = "NAND Writable User area";
145 reg = <0x1f000000 0x21000000>;
146 };
147 };
148
149 board-control@3,0 {
150 compatible = "fsl,p3041ds-pixis";
151 reg = <3 0 0x20>;
152 };
153 };
154
155 pci0: pcie@ffe200000 {
156 reg = <0xf 0xfe200000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
159 pcie@0 {
160 ranges = <0x02000000 0 0xe0000000
161 0x02000000 0 0xe0000000
162 0 0x20000000
163
164 0x01000000 0 0x00000000
165 0x01000000 0 0x00000000
166 0 0x00010000>;
167 };
168 };
169
170 pci1: pcie@ffe201000 {
171 reg = <0xf 0xfe201000 0 0x1000>;
172 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
173 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
174 pcie@0 {
175 ranges = <0x02000000 0 0xe0000000
176 0x02000000 0 0xe0000000
177 0 0x20000000
178
179 0x01000000 0 0x00000000
180 0x01000000 0 0x00000000
181 0 0x00010000>;
182 };
183 };
184
185 pci2: pcie@ffe202000 {
186 reg = <0xf 0xfe202000 0 0x1000>;
187 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
188 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
189 pcie@0 {
190 ranges = <0x02000000 0 0xe0000000
191 0x02000000 0 0xe0000000
192 0 0x20000000
193
194 0x01000000 0 0x00000000
195 0x01000000 0 0x00000000
196 0 0x00010000>;
197 };
198 };
199
200 pci3: pcie@ffe203000 {
201 reg = <0xf 0xfe203000 0 0x1000>;
202 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
203 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
204 pcie@0 {
205 ranges = <0x02000000 0 0xe0000000
206 0x02000000 0 0xe0000000
207 0 0x20000000
208
209 0x01000000 0 0x00000000
210 0x01000000 0 0x00000000
211 0 0x00010000>;
212 };
213 };
214};
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
new file mode 100644
index 000000000000..8b695801f505
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041si.dtsi
@@ -0,0 +1,660 @@
1/*
2 * P3041 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74/*
75 rio0 = &rapidio0;
76 */
77 };
78
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu0: PowerPC,e500mc@0 {
84 device_type = "cpu";
85 reg = <0>;
86 next-level-cache = <&L2_0>;
87 L2_0: l2-cache {
88 next-level-cache = <&cpc>;
89 };
90 };
91 cpu1: PowerPC,e500mc@1 {
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2_1>;
95 L2_1: l2-cache {
96 next-level-cache = <&cpc>;
97 };
98 };
99 cpu2: PowerPC,e500mc@2 {
100 device_type = "cpu";
101 reg = <2>;
102 next-level-cache = <&L2_2>;
103 L2_2: l2-cache {
104 next-level-cache = <&cpc>;
105 };
106 };
107 cpu3: PowerPC,e500mc@3 {
108 device_type = "cpu";
109 reg = <3>;
110 next-level-cache = <&L2_3>;
111 L2_3: l2-cache {
112 next-level-cache = <&cpc>;
113 };
114 };
115 };
116
117 soc: soc@ffe000000 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 device_type = "soc";
121 compatible = "simple-bus";
122 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
123 reg = <0xf 0xfe000000 0 0x00001000>;
124
125 soc-sram-error {
126 compatible = "fsl,soc-sram-error";
127 interrupts = <16 2 1 29>;
128 };
129
130 corenet-law@0 {
131 compatible = "fsl,corenet-law";
132 reg = <0x0 0x1000>;
133 fsl,num-laws = <32>;
134 };
135
136 memory-controller@8000 {
137 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
138 reg = <0x8000 0x1000>;
139 interrupts = <16 2 1 23>;
140 };
141
142 cpc: l3-cache-controller@10000 {
143 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
144 reg = <0x10000 0x1000>;
145 interrupts = <16 2 1 27>;
146 };
147
148 corenet-cf@18000 {
149 compatible = "fsl,corenet-cf";
150 reg = <0x18000 0x1000>;
151 interrupts = <16 2 1 31>;
152 fsl,ccf-num-csdids = <32>;
153 fsl,ccf-num-snoopids = <32>;
154 };
155
156 iommu@20000 {
157 compatible = "fsl,pamu-v1.0", "fsl,pamu";
158 reg = <0x20000 0x4000>;
159 interrupts = <
160 24 2 0 0
161 16 2 1 30>;
162 };
163
164 mpic: pic@40000 {
165 clock-frequency = <0>;
166 interrupt-controller;
167 #address-cells = <0>;
168 #interrupt-cells = <4>;
169 reg = <0x40000 0x40000>;
170 compatible = "fsl,mpic", "chrp,open-pic";
171 device_type = "open-pic";
172 };
173
174 msi0: msi@41600 {
175 compatible = "fsl,mpic-msi";
176 reg = <0x41600 0x200>;
177 msi-available-ranges = <0 0x100>;
178 interrupts = <
179 0xe0 0 0 0
180 0xe1 0 0 0
181 0xe2 0 0 0
182 0xe3 0 0 0
183 0xe4 0 0 0
184 0xe5 0 0 0
185 0xe6 0 0 0
186 0xe7 0 0 0>;
187 };
188
189 msi1: msi@41800 {
190 compatible = "fsl,mpic-msi";
191 reg = <0x41800 0x200>;
192 msi-available-ranges = <0 0x100>;
193 interrupts = <
194 0xe8 0 0 0
195 0xe9 0 0 0
196 0xea 0 0 0
197 0xeb 0 0 0
198 0xec 0 0 0
199 0xed 0 0 0
200 0xee 0 0 0
201 0xef 0 0 0>;
202 };
203
204 msi2: msi@41a00 {
205 compatible = "fsl,mpic-msi";
206 reg = <0x41a00 0x200>;
207 msi-available-ranges = <0 0x100>;
208 interrupts = <
209 0xf0 0 0 0
210 0xf1 0 0 0
211 0xf2 0 0 0
212 0xf3 0 0 0
213 0xf4 0 0 0
214 0xf5 0 0 0
215 0xf6 0 0 0
216 0xf7 0 0 0>;
217 };
218
219 guts: global-utilities@e0000 {
220 compatible = "fsl,qoriq-device-config-1.0";
221 reg = <0xe0000 0xe00>;
222 fsl,has-rstcr;
223 #sleep-cells = <1>;
224 fsl,liodn-bits = <12>;
225 };
226
227 pins: global-utilities@e0e00 {
228 compatible = "fsl,qoriq-pin-control-1.0";
229 reg = <0xe0e00 0x200>;
230 #sleep-cells = <2>;
231 };
232
233 clockgen: global-utilities@e1000 {
234 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
235 reg = <0xe1000 0x1000>;
236 clock-frequency = <0>;
237 };
238
239 rcpm: global-utilities@e2000 {
240 compatible = "fsl,qoriq-rcpm-1.0";
241 reg = <0xe2000 0x1000>;
242 #sleep-cells = <1>;
243 };
244
245 sfp: sfp@e8000 {
246 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
247 reg = <0xe8000 0x1000>;
248 };
249
250 serdes: serdes@ea000 {
251 compatible = "fsl,p3041-serdes";
252 reg = <0xea000 0x1000>;
253 };
254
255 dma0: dma@100300 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
259 reg = <0x100300 0x4>;
260 ranges = <0x0 0x100100 0x200>;
261 cell-index = <0>;
262 dma-channel@0 {
263 compatible = "fsl,p3041-dma-channel",
264 "fsl,eloplus-dma-channel";
265 reg = <0x0 0x80>;
266 cell-index = <0>;
267 interrupts = <28 2 0 0>;
268 };
269 dma-channel@80 {
270 compatible = "fsl,p3041-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x80 0x80>;
273 cell-index = <1>;
274 interrupts = <29 2 0 0>;
275 };
276 dma-channel@100 {
277 compatible = "fsl,p3041-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x100 0x80>;
280 cell-index = <2>;
281 interrupts = <30 2 0 0>;
282 };
283 dma-channel@180 {
284 compatible = "fsl,p3041-dma-channel",
285 "fsl,eloplus-dma-channel";
286 reg = <0x180 0x80>;
287 cell-index = <3>;
288 interrupts = <31 2 0 0>;
289 };
290 };
291
292 dma1: dma@101300 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
296 reg = <0x101300 0x4>;
297 ranges = <0x0 0x101100 0x200>;
298 cell-index = <1>;
299 dma-channel@0 {
300 compatible = "fsl,p3041-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x0 0x80>;
303 cell-index = <0>;
304 interrupts = <32 2 0 0>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,p3041-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x80 0x80>;
310 cell-index = <1>;
311 interrupts = <33 2 0 0>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,p3041-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x100 0x80>;
317 cell-index = <2>;
318 interrupts = <34 2 0 0>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,p3041-dma-channel",
322 "fsl,eloplus-dma-channel";
323 reg = <0x180 0x80>;
324 cell-index = <3>;
325 interrupts = <35 2 0 0>;
326 };
327 };
328
329 spi@110000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
333 reg = <0x110000 0x1000>;
334 interrupts = <53 0x2 0 0>;
335 fsl,espi-num-chipselects = <4>;
336 };
337
338 sdhc: sdhc@114000 {
339 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
340 reg = <0x114000 0x1000>;
341 interrupts = <48 2 0 0>;
342 sdhci,auto-cmd12;
343 clock-frequency = <0>;
344 };
345
346 i2c@118000 {
347 #address-cells = <1>;
348 #size-cells = <0>;
349 cell-index = <0>;
350 compatible = "fsl-i2c";
351 reg = <0x118000 0x100>;
352 interrupts = <38 2 0 0>;
353 dfsrr;
354 };
355
356 i2c@118100 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 cell-index = <1>;
360 compatible = "fsl-i2c";
361 reg = <0x118100 0x100>;
362 interrupts = <38 2 0 0>;
363 dfsrr;
364 };
365
366 i2c@119000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 cell-index = <2>;
370 compatible = "fsl-i2c";
371 reg = <0x119000 0x100>;
372 interrupts = <39 2 0 0>;
373 dfsrr;
374 };
375
376 i2c@119100 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 cell-index = <3>;
380 compatible = "fsl-i2c";
381 reg = <0x119100 0x100>;
382 interrupts = <39 2 0 0>;
383 dfsrr;
384 };
385
386 serial0: serial@11c500 {
387 cell-index = <0>;
388 device_type = "serial";
389 compatible = "ns16550";
390 reg = <0x11c500 0x100>;
391 clock-frequency = <0>;
392 interrupts = <36 2 0 0>;
393 };
394
395 serial1: serial@11c600 {
396 cell-index = <1>;
397 device_type = "serial";
398 compatible = "ns16550";
399 reg = <0x11c600 0x100>;
400 clock-frequency = <0>;
401 interrupts = <36 2 0 0>;
402 };
403
404 serial2: serial@11d500 {
405 cell-index = <2>;
406 device_type = "serial";
407 compatible = "ns16550";
408 reg = <0x11d500 0x100>;
409 clock-frequency = <0>;
410 interrupts = <37 2 0 0>;
411 };
412
413 serial3: serial@11d600 {
414 cell-index = <3>;
415 device_type = "serial";
416 compatible = "ns16550";
417 reg = <0x11d600 0x100>;
418 clock-frequency = <0>;
419 interrupts = <37 2 0 0>;
420 };
421
422 gpio0: gpio@130000 {
423 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
424 reg = <0x130000 0x1000>;
425 interrupts = <55 2 0 0>;
426 #gpio-cells = <2>;
427 gpio-controller;
428 };
429
430 usb0: usb@210000 {
431 compatible = "fsl,p3041-usb2-mph",
432 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
433 reg = <0x210000 0x1000>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 interrupts = <44 0x2 0 0>;
437 phy_type = "utmi";
438 port0;
439 };
440
441 usb1: usb@211000 {
442 compatible = "fsl,p3041-usb2-dr",
443 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
444 reg = <0x211000 0x1000>;
445 #address-cells = <1>;
446 #size-cells = <0>;
447 interrupts = <45 0x2 0 0>;
448 dr_mode = "host";
449 phy_type = "utmi";
450 };
451
452 sata@220000 {
453 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
454 reg = <0x220000 0x1000>;
455 interrupts = <68 0x2 0 0>;
456 };
457
458 sata@221000 {
459 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
460 reg = <0x221000 0x1000>;
461 interrupts = <69 0x2 0 0>;
462 };
463
464 crypto: crypto@300000 {
465 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
466 #address-cells = <1>;
467 #size-cells = <1>;
468 reg = <0x300000 0x10000>;
469 ranges = <0 0x300000 0x10000>;
470 interrupts = <92 2 0 0>;
471
472 sec_jr0: jr@1000 {
473 compatible = "fsl,sec-v4.2-job-ring",
474 "fsl,sec-v4.0-job-ring";
475 reg = <0x1000 0x1000>;
476 interrupts = <88 2 0 0>;
477 };
478
479 sec_jr1: jr@2000 {
480 compatible = "fsl,sec-v4.2-job-ring",
481 "fsl,sec-v4.0-job-ring";
482 reg = <0x2000 0x1000>;
483 interrupts = <89 2 0 0>;
484 };
485
486 sec_jr2: jr@3000 {
487 compatible = "fsl,sec-v4.2-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x3000 0x1000>;
490 interrupts = <90 2 0 0>;
491 };
492
493 sec_jr3: jr@4000 {
494 compatible = "fsl,sec-v4.2-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x4000 0x1000>;
497 interrupts = <91 2 0 0>;
498 };
499
500 rtic@6000 {
501 compatible = "fsl,sec-v4.2-rtic",
502 "fsl,sec-v4.0-rtic";
503 #address-cells = <1>;
504 #size-cells = <1>;
505 reg = <0x6000 0x100>;
506 ranges = <0x0 0x6100 0xe00>;
507
508 rtic_a: rtic-a@0 {
509 compatible = "fsl,sec-v4.2-rtic-memory",
510 "fsl,sec-v4.0-rtic-memory";
511 reg = <0x00 0x20 0x100 0x80>;
512 };
513
514 rtic_b: rtic-b@20 {
515 compatible = "fsl,sec-v4.2-rtic-memory",
516 "fsl,sec-v4.0-rtic-memory";
517 reg = <0x20 0x20 0x200 0x80>;
518 };
519
520 rtic_c: rtic-c@40 {
521 compatible = "fsl,sec-v4.2-rtic-memory",
522 "fsl,sec-v4.0-rtic-memory";
523 reg = <0x40 0x20 0x300 0x80>;
524 };
525
526 rtic_d: rtic-d@60 {
527 compatible = "fsl,sec-v4.2-rtic-memory",
528 "fsl,sec-v4.0-rtic-memory";
529 reg = <0x60 0x20 0x500 0x80>;
530 };
531 };
532 };
533
534 sec_mon: sec_mon@314000 {
535 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
536 reg = <0x314000 0x1000>;
537 interrupts = <93 2 0 0>;
538 };
539 };
540
541/*
542 rapidio0: rapidio@ffe0c0000
543*/
544
545 localbus@ffe124000 {
546 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
547 interrupts = <25 2 0 0>;
548 #address-cells = <2>;
549 #size-cells = <1>;
550 };
551
552 pci0: pcie@ffe200000 {
553 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
554 device_type = "pci";
555 #size-cells = <2>;
556 #address-cells = <3>;
557 bus-range = <0x0 0xff>;
558 clock-frequency = <0x1fca055>;
559 fsl,msi = <&msi0>;
560 interrupts = <16 2 1 15>;
561
562 pcie@0 {
563 reg = <0 0 0 0 0>;
564 #interrupt-cells = <1>;
565 #size-cells = <2>;
566 #address-cells = <3>;
567 device_type = "pci";
568 interrupts = <16 2 1 15>;
569 interrupt-map-mask = <0xf800 0 0 7>;
570 interrupt-map = <
571 /* IDSEL 0x0 */
572 0000 0 0 1 &mpic 40 1 0 0
573 0000 0 0 2 &mpic 1 1 0 0
574 0000 0 0 3 &mpic 2 1 0 0
575 0000 0 0 4 &mpic 3 1 0 0
576 >;
577 };
578 };
579
580 pci1: pcie@ffe201000 {
581 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
582 device_type = "pci";
583 #size-cells = <2>;
584 #address-cells = <3>;
585 bus-range = <0 0xff>;
586 clock-frequency = <0x1fca055>;
587 fsl,msi = <&msi1>;
588 interrupts = <16 2 1 14>;
589 pcie@0 {
590 reg = <0 0 0 0 0>;
591 #interrupt-cells = <1>;
592 #size-cells = <2>;
593 #address-cells = <3>;
594 device_type = "pci";
595 interrupts = <16 2 1 14>;
596 interrupt-map-mask = <0xf800 0 0 7>;
597 interrupt-map = <
598 /* IDSEL 0x0 */
599 0000 0 0 1 &mpic 41 1 0 0
600 0000 0 0 2 &mpic 5 1 0 0
601 0000 0 0 3 &mpic 6 1 0 0
602 0000 0 0 4 &mpic 7 1 0 0
603 >;
604 };
605 };
606
607 pci2: pcie@ffe202000 {
608 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
609 device_type = "pci";
610 #size-cells = <2>;
611 #address-cells = <3>;
612 bus-range = <0x0 0xff>;
613 clock-frequency = <0x1fca055>;
614 fsl,msi = <&msi2>;
615 interrupts = <16 2 1 13>;
616 pcie@0 {
617 reg = <0 0 0 0 0>;
618 #interrupt-cells = <1>;
619 #size-cells = <2>;
620 #address-cells = <3>;
621 device_type = "pci";
622 interrupts = <16 2 1 13>;
623 interrupt-map-mask = <0xf800 0 0 7>;
624 interrupt-map = <
625 /* IDSEL 0x0 */
626 0000 0 0 1 &mpic 42 1 0 0
627 0000 0 0 2 &mpic 9 1 0 0
628 0000 0 0 3 &mpic 10 1 0 0
629 0000 0 0 4 &mpic 11 1 0 0
630 >;
631 };
632 };
633
634 pci3: pcie@ffe203000 {
635 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
636 device_type = "pci";
637 #size-cells = <2>;
638 #address-cells = <3>;
639 bus-range = <0x0 0xff>;
640 clock-frequency = <0x1fca055>;
641 fsl,msi = <&msi2>;
642 interrupts = <16 2 1 12>;
643 pcie@0 {
644 reg = <0 0 0 0 0>;
645 #interrupt-cells = <1>;
646 #size-cells = <2>;
647 #address-cells = <3>;
648 device_type = "pci";
649 interrupts = <16 2 1 12>;
650 interrupt-map-mask = <0xf800 0 0 7>;
651 interrupt-map = <
652 /* IDSEL 0x0 */
653 0000 0 0 1 &mpic 43 1 0 0
654 0000 0 0 2 &mpic 0 1 0 0
655 0000 0 0 3 &mpic 4 1 0 0
656 0000 0 0 4 &mpic 8 1 0 0
657 >;
658 };
659 };
660};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 927f94d16e9b..eb11098bb687 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -3,258 +3,50 @@
3 * 3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * Redistribution and use in source and binary forms, with or without
7 * under the terms of the GNU General Public License as published by the 7 * modification, are permitted provided that the following conditions are met:
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * * Redistributions of source code must retain the above copyright
9 * option) any later version. 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10 */ 33 */
11 34
12/dts-v1/; 35/include/ "p4080si.dtsi"
13 36
14/ { 37/ {
15 model = "fsl,P4080DS"; 38 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS";
17 #address-cells = <2>; 40 #address-cells = <2>;
18 #size-cells = <2>; 41 #size-cells = <2>;
19 42 interrupt-parent = <&mpic>;
20 aliases {
21 ccsr = &soc;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
35
36 crypto = &crypto;
37 sec_jr0 = &sec_jr0;
38 sec_jr1 = &sec_jr1;
39 sec_jr2 = &sec_jr2;
40 sec_jr3 = &sec_jr3;
41 rtic_a = &rtic_a;
42 rtic_b = &rtic_b;
43 rtic_c = &rtic_c;
44 rtic_d = &rtic_d;
45 sec_mon = &sec_mon;
46
47 rio0 = &rapidio0;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: PowerPC,4080@0 {
55 device_type = "cpu";
56 reg = <0>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 };
60 };
61 cpu1: PowerPC,4080@1 {
62 device_type = "cpu";
63 reg = <1>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
66 };
67 };
68 cpu2: PowerPC,4080@2 {
69 device_type = "cpu";
70 reg = <2>;
71 next-level-cache = <&L2_2>;
72 L2_2: l2-cache {
73 };
74 };
75 cpu3: PowerPC,4080@3 {
76 device_type = "cpu";
77 reg = <3>;
78 next-level-cache = <&L2_3>;
79 L2_3: l2-cache {
80 };
81 };
82 cpu4: PowerPC,4080@4 {
83 device_type = "cpu";
84 reg = <4>;
85 next-level-cache = <&L2_4>;
86 L2_4: l2-cache {
87 };
88 };
89 cpu5: PowerPC,4080@5 {
90 device_type = "cpu";
91 reg = <5>;
92 next-level-cache = <&L2_5>;
93 L2_5: l2-cache {
94 };
95 };
96 cpu6: PowerPC,4080@6 {
97 device_type = "cpu";
98 reg = <6>;
99 next-level-cache = <&L2_6>;
100 L2_6: l2-cache {
101 };
102 };
103 cpu7: PowerPC,4080@7 {
104 device_type = "cpu";
105 reg = <7>;
106 next-level-cache = <&L2_7>;
107 L2_7: l2-cache {
108 };
109 };
110 };
111 43
112 memory { 44 memory {
113 device_type = "memory"; 45 device_type = "memory";
114 }; 46 };
115 47
116 soc: soc@ffe000000 { 48 soc: soc@ffe000000 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 device_type = "soc";
120 compatible = "simple-bus";
121 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
122 reg = <0xf 0xfe000000 0 0x00001000>;
123
124 corenet-law@0 {
125 compatible = "fsl,corenet-law";
126 reg = <0x0 0x1000>;
127 fsl,num-laws = <32>;
128 };
129
130 memory-controller@8000 {
131 compatible = "fsl,p4080-memory-controller";
132 reg = <0x8000 0x1000>;
133 interrupt-parent = <&mpic>;
134 interrupts = <0x12 2>;
135 };
136
137 memory-controller@9000 {
138 compatible = "fsl,p4080-memory-controller";
139 reg = <0x9000 0x1000>;
140 interrupt-parent = <&mpic>;
141 interrupts = <0x12 2>;
142 };
143
144 corenet-cf@18000 {
145 compatible = "fsl,corenet-cf";
146 reg = <0x18000 0x1000>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,p4080-pamu";
153 reg = <0x20000 0x10000>;
154 interrupts = <24 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 mpic: pic@40000 {
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <2>;
162 reg = <0x40000 0x40000>;
163 compatible = "chrp,open-pic";
164 device_type = "open-pic";
165 };
166
167 dma0: dma@100300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
171 reg = <0x100300 0x4>;
172 ranges = <0x0 0x100100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p4080-dma-channel",
176 "fsl,eloplus-dma-channel";
177 reg = <0x0 0x80>;
178 cell-index = <0>;
179 interrupt-parent = <&mpic>;
180 interrupts = <28 2>;
181 };
182 dma-channel@80 {
183 compatible = "fsl,p4080-dma-channel",
184 "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <29 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p4080-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x100 0x80>;
194 cell-index = <2>;
195 interrupt-parent = <&mpic>;
196 interrupts = <30 2>;
197 };
198 dma-channel@180 {
199 compatible = "fsl,p4080-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x180 0x80>;
202 cell-index = <3>;
203 interrupt-parent = <&mpic>;
204 interrupts = <31 2>;
205 };
206 };
207
208 dma1: dma@101300 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
212 reg = <0x101300 0x4>;
213 ranges = <0x0 0x101100 0x200>;
214 cell-index = <1>;
215 dma-channel@0 {
216 compatible = "fsl,p4080-dma-channel",
217 "fsl,eloplus-dma-channel";
218 reg = <0x0 0x80>;
219 cell-index = <0>;
220 interrupt-parent = <&mpic>;
221 interrupts = <32 2>;
222 };
223 dma-channel@80 {
224 compatible = "fsl,p4080-dma-channel",
225 "fsl,eloplus-dma-channel";
226 reg = <0x80 0x80>;
227 cell-index = <1>;
228 interrupt-parent = <&mpic>;
229 interrupts = <33 2>;
230 };
231 dma-channel@100 {
232 compatible = "fsl,p4080-dma-channel",
233 "fsl,eloplus-dma-channel";
234 reg = <0x100 0x80>;
235 cell-index = <2>;
236 interrupt-parent = <&mpic>;
237 interrupts = <34 2>;
238 };
239 dma-channel@180 {
240 compatible = "fsl,p4080-dma-channel",
241 "fsl,eloplus-dma-channel";
242 reg = <0x180 0x80>;
243 cell-index = <3>;
244 interrupt-parent = <&mpic>;
245 interrupts = <35 2>;
246 };
247 };
248
249 spi@110000 { 49 spi@110000 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
253 reg = <0x110000 0x1000>;
254 interrupts = <53 0x2>;
255 interrupt-parent = <&mpic>;
256 fsl,espi-num-chipselects = <4>;
257
258 flash@0 { 50 flash@0 {
259 #address-cells = <1>; 51 #address-cells = <1>;
260 #size-cells = <1>; 52 #size-cells = <1>;
@@ -283,35 +75,7 @@
283 }; 75 };
284 }; 76 };
285 77
286 sdhc: sdhc@114000 {
287 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
288 reg = <0x114000 0x1000>;
289 interrupts = <48 2>;
290 interrupt-parent = <&mpic>;
291 voltage-ranges = <3300 3300>;
292 sdhci,auto-cmd12;
293 };
294
295 i2c@118000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 cell-index = <0>;
299 compatible = "fsl-i2c";
300 reg = <0x118000 0x100>;
301 interrupts = <38 2>;
302 interrupt-parent = <&mpic>;
303 dfsrr;
304 };
305
306 i2c@118100 { 78 i2c@118100 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 cell-index = <1>;
310 compatible = "fsl-i2c";
311 reg = <0x118100 0x100>;
312 interrupts = <38 2>;
313 interrupt-parent = <&mpic>;
314 dfsrr;
315 eeprom@51 { 79 eeprom@51 {
316 compatible = "at24,24c256"; 80 compatible = "at24,24c256";
317 reg = <0x51>; 81 reg = <0x51>;
@@ -323,198 +87,27 @@
323 rtc@68 { 87 rtc@68 {
324 compatible = "dallas,ds3232"; 88 compatible = "dallas,ds3232";
325 reg = <0x68>; 89 reg = <0x68>;
326 interrupts = <0 0x1>; 90 interrupts = <0x1 0x1 0 0>;
327 interrupt-parent = <&mpic>;
328 }; 91 };
329 }; 92 };
330 93
331 i2c@119000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 cell-index = <2>;
335 compatible = "fsl-i2c";
336 reg = <0x119000 0x100>;
337 interrupts = <39 2>;
338 interrupt-parent = <&mpic>;
339 dfsrr;
340 };
341
342 i2c@119100 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 cell-index = <3>;
346 compatible = "fsl-i2c";
347 reg = <0x119100 0x100>;
348 interrupts = <39 2>;
349 interrupt-parent = <&mpic>;
350 dfsrr;
351 };
352
353 serial0: serial@11c500 {
354 cell-index = <0>;
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c500 0x100>;
358 clock-frequency = <0>;
359 interrupts = <36 2>;
360 interrupt-parent = <&mpic>;
361 };
362
363 serial1: serial@11c600 {
364 cell-index = <1>;
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11c600 0x100>;
368 clock-frequency = <0>;
369 interrupts = <36 2>;
370 interrupt-parent = <&mpic>;
371 };
372
373 serial2: serial@11d500 {
374 cell-index = <2>;
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d500 0x100>;
378 clock-frequency = <0>;
379 interrupts = <37 2>;
380 interrupt-parent = <&mpic>;
381 };
382
383 serial3: serial@11d600 {
384 cell-index = <3>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11d600 0x100>;
388 clock-frequency = <0>;
389 interrupts = <37 2>;
390 interrupt-parent = <&mpic>;
391 };
392
393 gpio0: gpio@130000 {
394 compatible = "fsl,p4080-gpio";
395 reg = <0x130000 0x1000>;
396 interrupts = <55 2>;
397 interrupt-parent = <&mpic>;
398 #gpio-cells = <2>;
399 gpio-controller;
400 };
401
402 usb0: usb@210000 { 94 usb0: usb@210000 {
403 compatible = "fsl,p4080-usb2-mph",
404 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
405 reg = <0x210000 0x1000>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 interrupt-parent = <&mpic>;
409 interrupts = <44 0x2>;
410 phy_type = "ulpi"; 95 phy_type = "ulpi";
411 }; 96 };
412 97
413 usb1: usb@211000 { 98 usb1: usb@211000 {
414 compatible = "fsl,p4080-usb2-dr",
415 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
416 reg = <0x211000 0x1000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 interrupt-parent = <&mpic>;
420 interrupts = <45 0x2>;
421 dr_mode = "host"; 99 dr_mode = "host";
422 phy_type = "ulpi"; 100 phy_type = "ulpi";
423 }; 101 };
424
425 crypto: crypto@300000 {
426 compatible = "fsl,sec-v4.0";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>;
432 interrupts = <92 2>;
433
434 sec_jr0: jr@1000 {
435 compatible = "fsl,sec-v4.0-job-ring";
436 reg = <0x1000 0x1000>;
437 interrupt-parent = <&mpic>;
438 interrupts = <88 2>;
439 };
440
441 sec_jr1: jr@2000 {
442 compatible = "fsl,sec-v4.0-job-ring";
443 reg = <0x2000 0x1000>;
444 interrupt-parent = <&mpic>;
445 interrupts = <89 2>;
446 };
447
448 sec_jr2: jr@3000 {
449 compatible = "fsl,sec-v4.0-job-ring";
450 reg = <0x3000 0x1000>;
451 interrupt-parent = <&mpic>;
452 interrupts = <90 2>;
453 };
454
455 sec_jr3: jr@4000 {
456 compatible = "fsl,sec-v4.0-job-ring";
457 reg = <0x4000 0x1000>;
458 interrupt-parent = <&mpic>;
459 interrupts = <91 2>;
460 };
461
462 rtic@6000 {
463 compatible = "fsl,sec-v4.0-rtic";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 reg = <0x6000 0x100>;
467 ranges = <0x0 0x6100 0xe00>;
468
469 rtic_a: rtic-a@0 {
470 compatible = "fsl,sec-v4.0-rtic-memory";
471 reg = <0x00 0x20 0x100 0x80>;
472 };
473
474 rtic_b: rtic-b@20 {
475 compatible = "fsl,sec-v4.0-rtic-memory";
476 reg = <0x20 0x20 0x200 0x80>;
477 };
478
479 rtic_c: rtic-c@40 {
480 compatible = "fsl,sec-v4.0-rtic-memory";
481 reg = <0x40 0x20 0x300 0x80>;
482 };
483
484 rtic_d: rtic-d@60 {
485 compatible = "fsl,sec-v4.0-rtic-memory";
486 reg = <0x60 0x20 0x500 0x80>;
487 };
488 };
489 };
490
491 sec_mon: sec_mon@314000 {
492 compatible = "fsl,sec-v4.0-mon";
493 reg = <0x314000 0x1000>;
494 interrupt-parent = <&mpic>;
495 interrupts = <93 2>;
496 };
497 }; 102 };
498 103
499 rapidio0: rapidio@ffe0c0000 { 104 rapidio0: rapidio@ffe0c0000 {
500 #address-cells = <2>;
501 #size-cells = <2>;
502 compatible = "fsl,rapidio-delta";
503 reg = <0xf 0xfe0c0000 0 0x20000>; 105 reg = <0xf 0xfe0c0000 0 0x20000>;
504 ranges = <0 0 0xf 0xf5000000 0 0x01000000>; 106 ranges = <0 0 0xc 0x20000000 0 0x01000000>;
505 interrupt-parent = <&mpic>;
506 /* err_irq bell_outb_irq bell_inb_irq
507 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
508 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
509 }; 107 };
510 108
511 localbus@ffe124000 { 109 localbus@ffe124000 {
512 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
513 reg = <0xf 0xfe124000 0 0x1000>; 110 reg = <0xf 0xfe124000 0 0x1000>;
514 interrupts = <25 2>;
515 #address-cells = <2>;
516 #size-cells = <1>;
517
518 ranges = <0 0 0xf 0xe8000000 0x08000000>; 111 ranges = <0 0 0xf 0xe8000000 0x08000000>;
519 112
520 flash@0,0 { 113 flash@0,0 {
@@ -526,32 +119,10 @@
526 }; 119 };
527 120
528 pci0: pcie@ffe200000 { 121 pci0: pcie@ffe200000 {
529 compatible = "fsl,p4080-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xfe200000 0 0x1000>; 122 reg = <0xf 0xfe200000 0 0x1000>;
535 bus-range = <0x0 0xff>;
536 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 123 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 124 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
538 clock-frequency = <0x1fca055>;
539 interrupt-parent = <&mpic>;
540 interrupts = <16 2>;
541
542 interrupt-map-mask = <0xf800 0 0 7>;
543 interrupt-map = <
544 /* IDSEL 0x0 */
545 0000 0 0 1 &mpic 40 1
546 0000 0 0 2 &mpic 1 1
547 0000 0 0 3 &mpic 2 1
548 0000 0 0 4 &mpic 3 1
549 >;
550 pcie@0 { 125 pcie@0 {
551 reg = <0 0 0 0 0>;
552 #size-cells = <2>;
553 #address-cells = <3>;
554 device_type = "pci";
555 ranges = <0x02000000 0 0xe0000000 126 ranges = <0x02000000 0 0xe0000000
556 0x02000000 0 0xe0000000 127 0x02000000 0 0xe0000000
557 0 0x20000000 128 0 0x20000000
@@ -563,31 +134,10 @@
563 }; 134 };
564 135
565 pci1: pcie@ffe201000 { 136 pci1: pcie@ffe201000 {
566 compatible = "fsl,p4080-pcie";
567 device_type = "pci";
568 #interrupt-cells = <1>;
569 #size-cells = <2>;
570 #address-cells = <3>;
571 reg = <0xf 0xfe201000 0 0x1000>; 137 reg = <0xf 0xfe201000 0 0x1000>;
572 bus-range = <0 0xff>;
573 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 138 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
574 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 139 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
575 clock-frequency = <0x1fca055>;
576 interrupt-parent = <&mpic>;
577 interrupts = <16 2>;
578 interrupt-map-mask = <0xf800 0 0 7>;
579 interrupt-map = <
580 /* IDSEL 0x0 */
581 0000 0 0 1 &mpic 41 1
582 0000 0 0 2 &mpic 5 1
583 0000 0 0 3 &mpic 6 1
584 0000 0 0 4 &mpic 7 1
585 >;
586 pcie@0 { 140 pcie@0 {
587 reg = <0 0 0 0 0>;
588 #size-cells = <2>;
589 #address-cells = <3>;
590 device_type = "pci";
591 ranges = <0x02000000 0 0xe0000000 141 ranges = <0x02000000 0 0xe0000000
592 0x02000000 0 0xe0000000 142 0x02000000 0 0xe0000000
593 0 0x20000000 143 0 0x20000000
@@ -599,31 +149,10 @@
599 }; 149 };
600 150
601 pci2: pcie@ffe202000 { 151 pci2: pcie@ffe202000 {
602 compatible = "fsl,p4080-pcie";
603 device_type = "pci";
604 #interrupt-cells = <1>;
605 #size-cells = <2>;
606 #address-cells = <3>;
607 reg = <0xf 0xfe202000 0 0x1000>; 152 reg = <0xf 0xfe202000 0 0x1000>;
608 bus-range = <0x0 0xff>;
609 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 153 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
610 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 154 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
611 clock-frequency = <0x1fca055>;
612 interrupt-parent = <&mpic>;
613 interrupts = <16 2>;
614 interrupt-map-mask = <0xf800 0 0 7>;
615 interrupt-map = <
616 /* IDSEL 0x0 */
617 0000 0 0 1 &mpic 42 1
618 0000 0 0 2 &mpic 9 1
619 0000 0 0 3 &mpic 10 1
620 0000 0 0 4 &mpic 11 1
621 >;
622 pcie@0 { 155 pcie@0 {
623 reg = <0 0 0 0 0>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 device_type = "pci";
627 ranges = <0x02000000 0 0xe0000000 156 ranges = <0x02000000 0 0xe0000000
628 0x02000000 0 0xe0000000 157 0x02000000 0 0xe0000000
629 0 0x20000000 158 0 0x20000000
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
new file mode 100644
index 000000000000..b71051f506c1
--- /dev/null
+++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -0,0 +1,661 @@
1/*
2 * P4080 Silicon Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P4080";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72
73 rio0 = &rapidio0;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,4080@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,4080@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 cpu2: PowerPC,4080@2 {
97 device_type = "cpu";
98 reg = <2>;
99 next-level-cache = <&L2_2>;
100 L2_2: l2-cache {
101 next-level-cache = <&cpc>;
102 };
103 };
104 cpu3: PowerPC,4080@3 {
105 device_type = "cpu";
106 reg = <3>;
107 next-level-cache = <&L2_3>;
108 L2_3: l2-cache {
109 next-level-cache = <&cpc>;
110 };
111 };
112 cpu4: PowerPC,4080@4 {
113 device_type = "cpu";
114 reg = <4>;
115 next-level-cache = <&L2_4>;
116 L2_4: l2-cache {
117 next-level-cache = <&cpc>;
118 };
119 };
120 cpu5: PowerPC,4080@5 {
121 device_type = "cpu";
122 reg = <5>;
123 next-level-cache = <&L2_5>;
124 L2_5: l2-cache {
125 next-level-cache = <&cpc>;
126 };
127 };
128 cpu6: PowerPC,4080@6 {
129 device_type = "cpu";
130 reg = <6>;
131 next-level-cache = <&L2_6>;
132 L2_6: l2-cache {
133 next-level-cache = <&cpc>;
134 };
135 };
136 cpu7: PowerPC,4080@7 {
137 device_type = "cpu";
138 reg = <7>;
139 next-level-cache = <&L2_7>;
140 L2_7: l2-cache {
141 next-level-cache = <&cpc>;
142 };
143 };
144 };
145
146 soc: soc@ffe000000 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 device_type = "soc";
150 compatible = "simple-bus";
151 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
152 reg = <0xf 0xfe000000 0 0x00001000>;
153
154 soc-sram-error {
155 compatible = "fsl,soc-sram-error";
156 interrupts = <16 2 1 29>;
157 };
158
159 corenet-law@0 {
160 compatible = "fsl,corenet-law";
161 reg = <0x0 0x1000>;
162 fsl,num-laws = <32>;
163 };
164
165 memory-controller@8000 {
166 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
167 reg = <0x8000 0x1000>;
168 interrupts = <16 2 1 23>;
169 };
170
171 memory-controller@9000 {
172 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
173 reg = <0x9000 0x1000>;
174 interrupts = <16 2 1 22>;
175 };
176
177 cpc: l3-cache-controller@10000 {
178 compatible = "fsl,p4080-l3-cache-controller", "cache";
179 reg = <0x10000 0x1000
180 0x11000 0x1000>;
181 interrupts = <16 2 1 27
182 16 2 1 26>;
183 };
184
185 corenet-cf@18000 {
186 compatible = "fsl,corenet-cf";
187 reg = <0x18000 0x1000>;
188 interrupts = <16 2 1 31>;
189 fsl,ccf-num-csdids = <32>;
190 fsl,ccf-num-snoopids = <32>;
191 };
192
193 iommu@20000 {
194 compatible = "fsl,pamu-v1.0", "fsl,pamu";
195 reg = <0x20000 0x5000>;
196 interrupts = <
197 24 2 0 0
198 16 2 1 30>;
199 };
200
201 mpic: pic@40000 {
202 clock-frequency = <0>;
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <4>;
206 reg = <0x40000 0x40000>;
207 compatible = "fsl,mpic", "chrp,open-pic";
208 device_type = "open-pic";
209 };
210
211 msi0: msi@41600 {
212 compatible = "fsl,mpic-msi";
213 reg = <0x41600 0x200>;
214 msi-available-ranges = <0 0x100>;
215 interrupts = <
216 0xe0 0 0 0
217 0xe1 0 0 0
218 0xe2 0 0 0
219 0xe3 0 0 0
220 0xe4 0 0 0
221 0xe5 0 0 0
222 0xe6 0 0 0
223 0xe7 0 0 0>;
224 };
225
226 msi1: msi@41800 {
227 compatible = "fsl,mpic-msi";
228 reg = <0x41800 0x200>;
229 msi-available-ranges = <0 0x100>;
230 interrupts = <
231 0xe8 0 0 0
232 0xe9 0 0 0
233 0xea 0 0 0
234 0xeb 0 0 0
235 0xec 0 0 0
236 0xed 0 0 0
237 0xee 0 0 0
238 0xef 0 0 0>;
239 };
240
241 msi2: msi@41a00 {
242 compatible = "fsl,mpic-msi";
243 reg = <0x41a00 0x200>;
244 msi-available-ranges = <0 0x100>;
245 interrupts = <
246 0xf0 0 0 0
247 0xf1 0 0 0
248 0xf2 0 0 0
249 0xf3 0 0 0
250 0xf4 0 0 0
251 0xf5 0 0 0
252 0xf6 0 0 0
253 0xf7 0 0 0>;
254 };
255
256 guts: global-utilities@e0000 {
257 compatible = "fsl,qoriq-device-config-1.0";
258 reg = <0xe0000 0xe00>;
259 fsl,has-rstcr;
260 #sleep-cells = <1>;
261 fsl,liodn-bits = <12>;
262 };
263
264 pins: global-utilities@e0e00 {
265 compatible = "fsl,qoriq-pin-control-1.0";
266 reg = <0xe0e00 0x200>;
267 #sleep-cells = <2>;
268 };
269
270 clockgen: global-utilities@e1000 {
271 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
272 reg = <0xe1000 0x1000>;
273 clock-frequency = <0>;
274 };
275
276 rcpm: global-utilities@e2000 {
277 compatible = "fsl,qoriq-rcpm-1.0";
278 reg = <0xe2000 0x1000>;
279 #sleep-cells = <1>;
280 };
281
282 sfp: sfp@e8000 {
283 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
284 reg = <0xe8000 0x1000>;
285 };
286
287 serdes: serdes@ea000 {
288 compatible = "fsl,p4080-serdes";
289 reg = <0xea000 0x1000>;
290 };
291
292 dma0: dma@100300 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
296 reg = <0x100300 0x4>;
297 ranges = <0x0 0x100100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,p4080-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x0 0x80>;
303 cell-index = <0>;
304 interrupts = <28 2 0 0>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,p4080-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x80 0x80>;
310 cell-index = <1>;
311 interrupts = <29 2 0 0>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,p4080-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x100 0x80>;
317 cell-index = <2>;
318 interrupts = <30 2 0 0>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,p4080-dma-channel",
322 "fsl,eloplus-dma-channel";
323 reg = <0x180 0x80>;
324 cell-index = <3>;
325 interrupts = <31 2 0 0>;
326 };
327 };
328
329 dma1: dma@101300 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
333 reg = <0x101300 0x4>;
334 ranges = <0x0 0x101100 0x200>;
335 cell-index = <1>;
336 dma-channel@0 {
337 compatible = "fsl,p4080-dma-channel",
338 "fsl,eloplus-dma-channel";
339 reg = <0x0 0x80>;
340 cell-index = <0>;
341 interrupts = <32 2 0 0>;
342 };
343 dma-channel@80 {
344 compatible = "fsl,p4080-dma-channel",
345 "fsl,eloplus-dma-channel";
346 reg = <0x80 0x80>;
347 cell-index = <1>;
348 interrupts = <33 2 0 0>;
349 };
350 dma-channel@100 {
351 compatible = "fsl,p4080-dma-channel",
352 "fsl,eloplus-dma-channel";
353 reg = <0x100 0x80>;
354 cell-index = <2>;
355 interrupts = <34 2 0 0>;
356 };
357 dma-channel@180 {
358 compatible = "fsl,p4080-dma-channel",
359 "fsl,eloplus-dma-channel";
360 reg = <0x180 0x80>;
361 cell-index = <3>;
362 interrupts = <35 2 0 0>;
363 };
364 };
365
366 spi@110000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
370 reg = <0x110000 0x1000>;
371 interrupts = <53 0x2 0 0>;
372 fsl,espi-num-chipselects = <4>;
373 };
374
375 sdhc: sdhc@114000 {
376 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
377 reg = <0x114000 0x1000>;
378 interrupts = <48 2 0 0>;
379 voltage-ranges = <3300 3300>;
380 sdhci,auto-cmd12;
381 clock-frequency = <0>;
382 };
383
384 i2c@118000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 cell-index = <0>;
388 compatible = "fsl-i2c";
389 reg = <0x118000 0x100>;
390 interrupts = <38 2 0 0>;
391 dfsrr;
392 };
393
394 i2c@118100 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 cell-index = <1>;
398 compatible = "fsl-i2c";
399 reg = <0x118100 0x100>;
400 interrupts = <38 2 0 0>;
401 dfsrr;
402 };
403
404 i2c@119000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 cell-index = <2>;
408 compatible = "fsl-i2c";
409 reg = <0x119000 0x100>;
410 interrupts = <39 2 0 0>;
411 dfsrr;
412 };
413
414 i2c@119100 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 cell-index = <3>;
418 compatible = "fsl-i2c";
419 reg = <0x119100 0x100>;
420 interrupts = <39 2 0 0>;
421 dfsrr;
422 };
423
424 serial0: serial@11c500 {
425 cell-index = <0>;
426 device_type = "serial";
427 compatible = "ns16550";
428 reg = <0x11c500 0x100>;
429 clock-frequency = <0>;
430 interrupts = <36 2 0 0>;
431 };
432
433 serial1: serial@11c600 {
434 cell-index = <1>;
435 device_type = "serial";
436 compatible = "ns16550";
437 reg = <0x11c600 0x100>;
438 clock-frequency = <0>;
439 interrupts = <36 2 0 0>;
440 };
441
442 serial2: serial@11d500 {
443 cell-index = <2>;
444 device_type = "serial";
445 compatible = "ns16550";
446 reg = <0x11d500 0x100>;
447 clock-frequency = <0>;
448 interrupts = <37 2 0 0>;
449 };
450
451 serial3: serial@11d600 {
452 cell-index = <3>;
453 device_type = "serial";
454 compatible = "ns16550";
455 reg = <0x11d600 0x100>;
456 clock-frequency = <0>;
457 interrupts = <37 2 0 0>;
458 };
459
460 gpio0: gpio@130000 {
461 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
462 reg = <0x130000 0x1000>;
463 interrupts = <55 2 0 0>;
464 #gpio-cells = <2>;
465 gpio-controller;
466 };
467
468 usb0: usb@210000 {
469 compatible = "fsl,p4080-usb2-mph",
470 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
471 reg = <0x210000 0x1000>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 interrupts = <44 0x2 0 0>;
475 };
476
477 usb1: usb@211000 {
478 compatible = "fsl,p4080-usb2-dr",
479 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
480 reg = <0x211000 0x1000>;
481 #address-cells = <1>;
482 #size-cells = <0>;
483 interrupts = <45 0x2 0 0>;
484 };
485
486 crypto: crypto@300000 {
487 compatible = "fsl,sec-v4.0";
488 #address-cells = <1>;
489 #size-cells = <1>;
490 reg = <0x300000 0x10000>;
491 ranges = <0 0x300000 0x10000>;
492 interrupt-parent = <&mpic>;
493 interrupts = <92 2 0 0>;
494
495 sec_jr0: jr@1000 {
496 compatible = "fsl,sec-v4.0-job-ring";
497 reg = <0x1000 0x1000>;
498 interrupt-parent = <&mpic>;
499 interrupts = <88 2 0 0>;
500 };
501
502 sec_jr1: jr@2000 {
503 compatible = "fsl,sec-v4.0-job-ring";
504 reg = <0x2000 0x1000>;
505 interrupt-parent = <&mpic>;
506 interrupts = <89 2 0 0>;
507 };
508
509 sec_jr2: jr@3000 {
510 compatible = "fsl,sec-v4.0-job-ring";
511 reg = <0x3000 0x1000>;
512 interrupt-parent = <&mpic>;
513 interrupts = <90 2 0 0>;
514 };
515
516 sec_jr3: jr@4000 {
517 compatible = "fsl,sec-v4.0-job-ring";
518 reg = <0x4000 0x1000>;
519 interrupt-parent = <&mpic>;
520 interrupts = <91 2 0 0>;
521 };
522
523 rtic@6000 {
524 compatible = "fsl,sec-v4.0-rtic";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 reg = <0x6000 0x100>;
528 ranges = <0x0 0x6100 0xe00>;
529
530 rtic_a: rtic-a@0 {
531 compatible = "fsl,sec-v4.0-rtic-memory";
532 reg = <0x00 0x20 0x100 0x80>;
533 };
534
535 rtic_b: rtic-b@20 {
536 compatible = "fsl,sec-v4.0-rtic-memory";
537 reg = <0x20 0x20 0x200 0x80>;
538 };
539
540 rtic_c: rtic-c@40 {
541 compatible = "fsl,sec-v4.0-rtic-memory";
542 reg = <0x40 0x20 0x300 0x80>;
543 };
544
545 rtic_d: rtic-d@60 {
546 compatible = "fsl,sec-v4.0-rtic-memory";
547 reg = <0x60 0x20 0x500 0x80>;
548 };
549 };
550 };
551
552 sec_mon: sec_mon@314000 {
553 compatible = "fsl,sec-v4.0-mon";
554 reg = <0x314000 0x1000>;
555 interrupt-parent = <&mpic>;
556 interrupts = <93 2 0 0>;
557 };
558 };
559
560 rapidio0: rapidio@ffe0c0000 {
561 #address-cells = <2>;
562 #size-cells = <2>;
563 compatible = "fsl,rapidio-delta";
564 interrupts = <
565 16 2 1 11 /* err_irq */
566 56 2 0 0 /* bell_outb_irq */
567 57 2 0 0 /* bell_inb_irq */
568 60 2 0 0 /* msg1_tx_irq */
569 61 2 0 0 /* msg1_rx_irq */
570 62 2 0 0 /* msg2_tx_irq */
571 63 2 0 0>; /* msg2_rx_irq */
572 };
573
574 localbus@ffe124000 {
575 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
576 interrupts = <25 2 0 0>;
577 #address-cells = <2>;
578 #size-cells = <1>;
579 };
580
581 pci0: pcie@ffe200000 {
582 compatible = "fsl,p4080-pcie";
583 device_type = "pci";
584 #size-cells = <2>;
585 #address-cells = <3>;
586 bus-range = <0x0 0xff>;
587 clock-frequency = <0x1fca055>;
588 fsl,msi = <&msi0>;
589 interrupts = <16 2 1 15>;
590 pcie@0 {
591 reg = <0 0 0 0 0>;
592 #interrupt-cells = <1>;
593 #size-cells = <2>;
594 #address-cells = <3>;
595 device_type = "pci";
596 interrupts = <16 2 1 15>;
597 interrupt-map-mask = <0xf800 0 0 7>;
598 interrupt-map = <
599 /* IDSEL 0x0 */
600 0000 0 0 1 &mpic 40 1 0 0
601 0000 0 0 2 &mpic 1 1 0 0
602 0000 0 0 3 &mpic 2 1 0 0
603 0000 0 0 4 &mpic 3 1 0 0
604 >;
605 };
606 };
607
608 pci1: pcie@ffe201000 {
609 compatible = "fsl,p4080-pcie";
610 device_type = "pci";
611 #size-cells = <2>;
612 #address-cells = <3>;
613 bus-range = <0 0xff>;
614 clock-frequency = <0x1fca055>;
615 fsl,msi = <&msi1>;
616 interrupts = <16 2 1 14>;
617 pcie@0 {
618 reg = <0 0 0 0 0>;
619 #interrupt-cells = <1>;
620 #size-cells = <2>;
621 #address-cells = <3>;
622 device_type = "pci";
623 interrupts = <16 2 1 14>;
624 interrupt-map-mask = <0xf800 0 0 7>;
625 interrupt-map = <
626 /* IDSEL 0x0 */
627 0000 0 0 1 &mpic 41 1 0 0
628 0000 0 0 2 &mpic 5 1 0 0
629 0000 0 0 3 &mpic 6 1 0 0
630 0000 0 0 4 &mpic 7 1 0 0
631 >;
632 };
633 };
634
635 pci2: pcie@ffe202000 {
636 compatible = "fsl,p4080-pcie";
637 device_type = "pci";
638 #size-cells = <2>;
639 #address-cells = <3>;
640 bus-range = <0x0 0xff>;
641 clock-frequency = <0x1fca055>;
642 fsl,msi = <&msi2>;
643 interrupts = <16 2 1 13>;
644 pcie@0 {
645 reg = <0 0 0 0 0>;
646 #interrupt-cells = <1>;
647 #size-cells = <2>;
648 #address-cells = <3>;
649 device_type = "pci";
650 interrupts = <16 2 1 13>;
651 interrupt-map-mask = <0xf800 0 0 7>;
652 interrupt-map = <
653 /* IDSEL 0x0 */
654 0000 0 0 1 &mpic 42 1 0 0
655 0000 0 0 2 &mpic 9 1 0 0
656 0000 0 0 3 &mpic 10 1 0 0
657 0000 0 0 4 &mpic 11 1 0 0
658 >;
659 };
660 };
661};
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
new file mode 100644
index 000000000000..8366e2fd2fba
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -0,0 +1,215 @@
1/*
2 * P5020DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p5020si.dtsi"
36
37/ {
38 model = "fsl,P5020DS";
39 compatible = "fsl,P5020DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118100 {
79 eeprom@51 {
80 compatible = "at24,24c256";
81 reg = <0x51>;
82 };
83 eeprom@52 {
84 compatible = "at24,24c256";
85 reg = <0x52>;
86 };
87 };
88
89 i2c@119100 {
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 interrupts = <0x1 0x1 0 0>;
94 };
95 };
96 };
97
98 localbus@ffe124000 {
99 reg = <0xf 0xfe124000 0 0x1000>;
100 ranges = <0 0 0xf 0xe8000000 0x08000000
101 2 0 0xf 0xffa00000 0x00040000
102 3 0 0xf 0xffdf0000 0x00008000>;
103
104 flash@0,0 {
105 compatible = "cfi-flash";
106 reg = <0 0 0x08000000>;
107 bank-width = <2>;
108 device-width = <2>;
109 };
110
111 nand@2,0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,elbc-fcm-nand";
115 reg = <0x2 0x0 0x40000>;
116
117 partition@0 {
118 label = "NAND U-Boot Image";
119 reg = <0x0 0x02000000>;
120 read-only;
121 };
122
123 partition@2000000 {
124 label = "NAND Root File System";
125 reg = <0x02000000 0x10000000>;
126 };
127
128 partition@12000000 {
129 label = "NAND Compressed RFS Image";
130 reg = <0x12000000 0x08000000>;
131 };
132
133 partition@1a000000 {
134 label = "NAND Linux Kernel Image";
135 reg = <0x1a000000 0x04000000>;
136 };
137
138 partition@1e000000 {
139 label = "NAND DTB Image";
140 reg = <0x1e000000 0x01000000>;
141 };
142
143 partition@1f000000 {
144 label = "NAND Writable User area";
145 reg = <0x1f000000 0x21000000>;
146 };
147 };
148
149 board-control@3,0 {
150 compatible = "fsl,p5020ds-pixis";
151 reg = <3 0 0x20>;
152 };
153 };
154
155 pci0: pcie@ffe200000 {
156 reg = <0xf 0xfe200000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
159
160 pcie@0 {
161 ranges = <0x02000000 0 0xe0000000
162 0x02000000 0 0xe0000000
163 0 0x20000000
164
165 0x01000000 0 0x00000000
166 0x01000000 0 0x00000000
167 0 0x00010000>;
168 };
169 };
170
171 pci1: pcie@ffe201000 {
172 reg = <0xf 0xfe201000 0 0x1000>;
173 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
174 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
175 pcie@0 {
176 ranges = <0x02000000 0 0xe0000000
177 0x02000000 0 0xe0000000
178 0 0x20000000
179
180 0x01000000 0 0x00000000
181 0x01000000 0 0x00000000
182 0 0x00010000>;
183 };
184 };
185
186 pci2: pcie@ffe202000 {
187 reg = <0xf 0xfe202000 0 0x1000>;
188 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
189 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
190 pcie@0 {
191 ranges = <0x02000000 0 0xe0000000
192 0x02000000 0 0xe0000000
193 0 0x20000000
194
195 0x01000000 0 0x00000000
196 0x01000000 0 0x00000000
197 0 0x00010000>;
198 };
199 };
200
201 pci3: pcie@ffe203000 {
202 reg = <0xf 0xfe203000 0 0x1000>;
203 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
204 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
205 pcie@0 {
206 ranges = <0x02000000 0 0xe0000000
207 0x02000000 0 0xe0000000
208 0 0x20000000
209
210 0x01000000 0 0x00000000
211 0x01000000 0 0x00000000
212 0 0x00010000>;
213 };
214 };
215};
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
new file mode 100644
index 000000000000..5e6048ec55bb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020si.dtsi
@@ -0,0 +1,652 @@
1/*
2 * P5020 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P5020";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74/*
75 rio0 = &rapidio0;
76 */
77 };
78
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu0: PowerPC,e5500@0 {
84 device_type = "cpu";
85 reg = <0>;
86 next-level-cache = <&L2_0>;
87 L2_0: l2-cache {
88 next-level-cache = <&cpc>;
89 };
90 };
91 cpu1: PowerPC,e5500@1 {
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2_1>;
95 L2_1: l2-cache {
96 next-level-cache = <&cpc>;
97 };
98 };
99 };
100
101 soc: soc@ffe000000 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 device_type = "soc";
105 compatible = "simple-bus";
106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
107 reg = <0xf 0xfe000000 0 0x00001000>;
108
109 soc-sram-error {
110 compatible = "fsl,soc-sram-error";
111 interrupts = <16 2 1 29>;
112 };
113
114 corenet-law@0 {
115 compatible = "fsl,corenet-law";
116 reg = <0x0 0x1000>;
117 fsl,num-laws = <32>;
118 };
119
120 memory-controller@8000 {
121 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
122 reg = <0x8000 0x1000>;
123 interrupts = <16 2 1 23>;
124 };
125
126 memory-controller@9000 {
127 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupts = <16 2 1 22>;
130 };
131
132 cpc: l3-cache-controller@10000 {
133 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
134 reg = <0x10000 0x1000
135 0x11000 0x1000>;
136 interrupts = <16 2 1 27
137 16 2 1 26>;
138 };
139
140 corenet-cf@18000 {
141 compatible = "fsl,corenet-cf";
142 reg = <0x18000 0x1000>;
143 interrupts = <16 2 1 31>;
144 fsl,ccf-num-csdids = <32>;
145 fsl,ccf-num-snoopids = <32>;
146 };
147
148 iommu@20000 {
149 compatible = "fsl,pamu-v1.0", "fsl,pamu";
150 reg = <0x20000 0x4000>;
151 interrupts = <
152 24 2 0 0
153 16 2 1 30>;
154 };
155
156 mpic: pic@40000 {
157 clock-frequency = <0>;
158 interrupt-controller;
159 #address-cells = <0>;
160 #interrupt-cells = <4>;
161 reg = <0x40000 0x40000>;
162 compatible = "fsl,mpic", "chrp,open-pic";
163 device_type = "open-pic";
164 };
165
166 msi0: msi@41600 {
167 compatible = "fsl,mpic-msi";
168 reg = <0x41600 0x200>;
169 msi-available-ranges = <0 0x100>;
170 interrupts = <
171 0xe0 0 0 0
172 0xe1 0 0 0
173 0xe2 0 0 0
174 0xe3 0 0 0
175 0xe4 0 0 0
176 0xe5 0 0 0
177 0xe6 0 0 0
178 0xe7 0 0 0>;
179 };
180
181 msi1: msi@41800 {
182 compatible = "fsl,mpic-msi";
183 reg = <0x41800 0x200>;
184 msi-available-ranges = <0 0x100>;
185 interrupts = <
186 0xe8 0 0 0
187 0xe9 0 0 0
188 0xea 0 0 0
189 0xeb 0 0 0
190 0xec 0 0 0
191 0xed 0 0 0
192 0xee 0 0 0
193 0xef 0 0 0>;
194 };
195
196 msi2: msi@41a00 {
197 compatible = "fsl,mpic-msi";
198 reg = <0x41a00 0x200>;
199 msi-available-ranges = <0 0x100>;
200 interrupts = <
201 0xf0 0 0 0
202 0xf1 0 0 0
203 0xf2 0 0 0
204 0xf3 0 0 0
205 0xf4 0 0 0
206 0xf5 0 0 0
207 0xf6 0 0 0
208 0xf7 0 0 0>;
209 };
210
211 guts: global-utilities@e0000 {
212 compatible = "fsl,qoriq-device-config-1.0";
213 reg = <0xe0000 0xe00>;
214 fsl,has-rstcr;
215 #sleep-cells = <1>;
216 fsl,liodn-bits = <12>;
217 };
218
219 pins: global-utilities@e0e00 {
220 compatible = "fsl,qoriq-pin-control-1.0";
221 reg = <0xe0e00 0x200>;
222 #sleep-cells = <2>;
223 };
224
225 clockgen: global-utilities@e1000 {
226 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
227 reg = <0xe1000 0x1000>;
228 clock-frequency = <0>;
229 };
230
231 rcpm: global-utilities@e2000 {
232 compatible = "fsl,qoriq-rcpm-1.0";
233 reg = <0xe2000 0x1000>;
234 #sleep-cells = <1>;
235 };
236
237 sfp: sfp@e8000 {
238 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
239 reg = <0xe8000 0x1000>;
240 };
241
242 serdes: serdes@ea000 {
243 compatible = "fsl,p5020-serdes";
244 reg = <0xea000 0x1000>;
245 };
246
247 dma0: dma@100300 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
251 reg = <0x100300 0x4>;
252 ranges = <0x0 0x100100 0x200>;
253 cell-index = <0>;
254 dma-channel@0 {
255 compatible = "fsl,p5020-dma-channel",
256 "fsl,eloplus-dma-channel";
257 reg = <0x0 0x80>;
258 cell-index = <0>;
259 interrupts = <28 2 0 0>;
260 };
261 dma-channel@80 {
262 compatible = "fsl,p5020-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x80 0x80>;
265 cell-index = <1>;
266 interrupts = <29 2 0 0>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,p5020-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupts = <30 2 0 0>;
274 };
275 dma-channel@180 {
276 compatible = "fsl,p5020-dma-channel",
277 "fsl,eloplus-dma-channel";
278 reg = <0x180 0x80>;
279 cell-index = <3>;
280 interrupts = <31 2 0 0>;
281 };
282 };
283
284 dma1: dma@101300 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
288 reg = <0x101300 0x4>;
289 ranges = <0x0 0x101100 0x200>;
290 cell-index = <1>;
291 dma-channel@0 {
292 compatible = "fsl,p5020-dma-channel",
293 "fsl,eloplus-dma-channel";
294 reg = <0x0 0x80>;
295 cell-index = <0>;
296 interrupts = <32 2 0 0>;
297 };
298 dma-channel@80 {
299 compatible = "fsl,p5020-dma-channel",
300 "fsl,eloplus-dma-channel";
301 reg = <0x80 0x80>;
302 cell-index = <1>;
303 interrupts = <33 2 0 0>;
304 };
305 dma-channel@100 {
306 compatible = "fsl,p5020-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x100 0x80>;
309 cell-index = <2>;
310 interrupts = <34 2 0 0>;
311 };
312 dma-channel@180 {
313 compatible = "fsl,p5020-dma-channel",
314 "fsl,eloplus-dma-channel";
315 reg = <0x180 0x80>;
316 cell-index = <3>;
317 interrupts = <35 2 0 0>;
318 };
319 };
320
321 spi@110000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
325 reg = <0x110000 0x1000>;
326 interrupts = <53 0x2 0 0>;
327 fsl,espi-num-chipselects = <4>;
328 };
329
330 sdhc: sdhc@114000 {
331 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
332 reg = <0x114000 0x1000>;
333 interrupts = <48 2 0 0>;
334 sdhci,auto-cmd12;
335 clock-frequency = <0>;
336 };
337
338 i2c@118000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 cell-index = <0>;
342 compatible = "fsl-i2c";
343 reg = <0x118000 0x100>;
344 interrupts = <38 2 0 0>;
345 dfsrr;
346 };
347
348 i2c@118100 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 cell-index = <1>;
352 compatible = "fsl-i2c";
353 reg = <0x118100 0x100>;
354 interrupts = <38 2 0 0>;
355 dfsrr;
356 };
357
358 i2c@119000 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 cell-index = <2>;
362 compatible = "fsl-i2c";
363 reg = <0x119000 0x100>;
364 interrupts = <39 2 0 0>;
365 dfsrr;
366 };
367
368 i2c@119100 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 cell-index = <3>;
372 compatible = "fsl-i2c";
373 reg = <0x119100 0x100>;
374 interrupts = <39 2 0 0>;
375 dfsrr;
376 };
377
378 serial0: serial@11c500 {
379 cell-index = <0>;
380 device_type = "serial";
381 compatible = "ns16550";
382 reg = <0x11c500 0x100>;
383 clock-frequency = <0>;
384 interrupts = <36 2 0 0>;
385 };
386
387 serial1: serial@11c600 {
388 cell-index = <1>;
389 device_type = "serial";
390 compatible = "ns16550";
391 reg = <0x11c600 0x100>;
392 clock-frequency = <0>;
393 interrupts = <36 2 0 0>;
394 };
395
396 serial2: serial@11d500 {
397 cell-index = <2>;
398 device_type = "serial";
399 compatible = "ns16550";
400 reg = <0x11d500 0x100>;
401 clock-frequency = <0>;
402 interrupts = <37 2 0 0>;
403 };
404
405 serial3: serial@11d600 {
406 cell-index = <3>;
407 device_type = "serial";
408 compatible = "ns16550";
409 reg = <0x11d600 0x100>;
410 clock-frequency = <0>;
411 interrupts = <37 2 0 0>;
412 };
413
414 gpio0: gpio@130000 {
415 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
416 reg = <0x130000 0x1000>;
417 interrupts = <55 2 0 0>;
418 #gpio-cells = <2>;
419 gpio-controller;
420 };
421
422 usb0: usb@210000 {
423 compatible = "fsl,p5020-usb2-mph",
424 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
425 reg = <0x210000 0x1000>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 interrupts = <44 0x2 0 0>;
429 phy_type = "utmi";
430 port0;
431 };
432
433 usb1: usb@211000 {
434 compatible = "fsl,p5020-usb2-dr",
435 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
436 reg = <0x211000 0x1000>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 interrupts = <45 0x2 0 0>;
440 dr_mode = "host";
441 phy_type = "utmi";
442 };
443
444 sata@220000 {
445 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
446 reg = <0x220000 0x1000>;
447 interrupts = <68 0x2 0 0>;
448 };
449
450 sata@221000 {
451 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
452 reg = <0x221000 0x1000>;
453 interrupts = <69 0x2 0 0>;
454 };
455
456 crypto: crypto@300000 {
457 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 reg = <0x300000 0x10000>;
461 ranges = <0 0x300000 0x10000>;
462 interrupts = <92 2 0 0>;
463
464 sec_jr0: jr@1000 {
465 compatible = "fsl,sec-v4.2-job-ring",
466 "fsl,sec-v4.0-job-ring";
467 reg = <0x1000 0x1000>;
468 interrupts = <88 2 0 0>;
469 };
470
471 sec_jr1: jr@2000 {
472 compatible = "fsl,sec-v4.2-job-ring",
473 "fsl,sec-v4.0-job-ring";
474 reg = <0x2000 0x1000>;
475 interrupts = <89 2 0 0>;
476 };
477
478 sec_jr2: jr@3000 {
479 compatible = "fsl,sec-v4.2-job-ring",
480 "fsl,sec-v4.0-job-ring";
481 reg = <0x3000 0x1000>;
482 interrupts = <90 2 0 0>;
483 };
484
485 sec_jr3: jr@4000 {
486 compatible = "fsl,sec-v4.2-job-ring",
487 "fsl,sec-v4.0-job-ring";
488 reg = <0x4000 0x1000>;
489 interrupts = <91 2 0 0>;
490 };
491
492 rtic@6000 {
493 compatible = "fsl,sec-v4.2-rtic",
494 "fsl,sec-v4.0-rtic";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 reg = <0x6000 0x100>;
498 ranges = <0x0 0x6100 0xe00>;
499
500 rtic_a: rtic-a@0 {
501 compatible = "fsl,sec-v4.2-rtic-memory",
502 "fsl,sec-v4.0-rtic-memory";
503 reg = <0x00 0x20 0x100 0x80>;
504 };
505
506 rtic_b: rtic-b@20 {
507 compatible = "fsl,sec-v4.2-rtic-memory",
508 "fsl,sec-v4.0-rtic-memory";
509 reg = <0x20 0x20 0x200 0x80>;
510 };
511
512 rtic_c: rtic-c@40 {
513 compatible = "fsl,sec-v4.2-rtic-memory",
514 "fsl,sec-v4.0-rtic-memory";
515 reg = <0x40 0x20 0x300 0x80>;
516 };
517
518 rtic_d: rtic-d@60 {
519 compatible = "fsl,sec-v4.2-rtic-memory",
520 "fsl,sec-v4.0-rtic-memory";
521 reg = <0x60 0x20 0x500 0x80>;
522 };
523 };
524 };
525
526 sec_mon: sec_mon@314000 {
527 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
528 reg = <0x314000 0x1000>;
529 interrupts = <93 2 0 0>;
530 };
531 };
532
533/*
534 rapidio0: rapidio@ffe0c0000
535*/
536
537 localbus@ffe124000 {
538 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
539 interrupts = <25 2 0 0>;
540 #address-cells = <2>;
541 #size-cells = <1>;
542 };
543
544 pci0: pcie@ffe200000 {
545 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
546 device_type = "pci";
547 #size-cells = <2>;
548 #address-cells = <3>;
549 bus-range = <0x0 0xff>;
550 clock-frequency = <0x1fca055>;
551 fsl,msi = <&msi0>;
552 interrupts = <16 2 1 15>;
553
554 pcie@0 {
555 reg = <0 0 0 0 0>;
556 #interrupt-cells = <1>;
557 #size-cells = <2>;
558 #address-cells = <3>;
559 device_type = "pci";
560 interrupts = <16 2 1 15>;
561 interrupt-map-mask = <0xf800 0 0 7>;
562 interrupt-map = <
563 /* IDSEL 0x0 */
564 0000 0 0 1 &mpic 40 1 0 0
565 0000 0 0 2 &mpic 1 1 0 0
566 0000 0 0 3 &mpic 2 1 0 0
567 0000 0 0 4 &mpic 3 1 0 0
568 >;
569 };
570 };
571
572 pci1: pcie@ffe201000 {
573 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
574 device_type = "pci";
575 #size-cells = <2>;
576 #address-cells = <3>;
577 bus-range = <0 0xff>;
578 clock-frequency = <0x1fca055>;
579 fsl,msi = <&msi1>;
580 interrupts = <16 2 1 14>;
581 pcie@0 {
582 reg = <0 0 0 0 0>;
583 #interrupt-cells = <1>;
584 #size-cells = <2>;
585 #address-cells = <3>;
586 device_type = "pci";
587 interrupts = <16 2 1 14>;
588 interrupt-map-mask = <0xf800 0 0 7>;
589 interrupt-map = <
590 /* IDSEL 0x0 */
591 0000 0 0 1 &mpic 41 1 0 0
592 0000 0 0 2 &mpic 5 1 0 0
593 0000 0 0 3 &mpic 6 1 0 0
594 0000 0 0 4 &mpic 7 1 0 0
595 >;
596 };
597 };
598
599 pci2: pcie@ffe202000 {
600 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
601 device_type = "pci";
602 #size-cells = <2>;
603 #address-cells = <3>;
604 bus-range = <0x0 0xff>;
605 clock-frequency = <0x1fca055>;
606 fsl,msi = <&msi2>;
607 interrupts = <16 2 1 13>;
608 pcie@0 {
609 reg = <0 0 0 0 0>;
610 #interrupt-cells = <1>;
611 #size-cells = <2>;
612 #address-cells = <3>;
613 device_type = "pci";
614 interrupts = <16 2 1 13>;
615 interrupt-map-mask = <0xf800 0 0 7>;
616 interrupt-map = <
617 /* IDSEL 0x0 */
618 0000 0 0 1 &mpic 42 1 0 0
619 0000 0 0 2 &mpic 9 1 0 0
620 0000 0 0 3 &mpic 10 1 0 0
621 0000 0 0 4 &mpic 11 1 0 0
622 >;
623 };
624 };
625
626 pci3: pcie@ffe203000 {
627 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
628 device_type = "pci";
629 #size-cells = <2>;
630 #address-cells = <3>;
631 bus-range = <0x0 0xff>;
632 clock-frequency = <0x1fca055>;
633 fsl,msi = <&msi2>;
634 interrupts = <16 2 1 12>;
635 pcie@0 {
636 reg = <0 0 0 0 0>;
637 #interrupt-cells = <1>;
638 #size-cells = <2>;
639 #address-cells = <3>;
640 device_type = "pci";
641 interrupts = <16 2 1 12>;
642 interrupt-map-mask = <0xf800 0 0 7>;
643 interrupt-map = <
644 /* IDSEL 0x0 */
645 0000 0 0 1 &mpic 43 1 0 0
646 0000 0 0 2 &mpic 0 1 0 0
647 0000 0 0 3 &mpic 4 1 0 0
648 0000 0 0 4 &mpic 8 1 0 0
649 >;
650 };
651 };
652};
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 739dd0da2416..b1d329246b08 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -110,6 +110,18 @@
110 dcr-reg = <0x010 0x002>; 110 dcr-reg = <0x010 0x002>;
111 }; 111 };
112 112
113 CRYPTO: crypto@e0100000 {
114 compatible = "amcc,ppc440epx-crypto","amcc,ppc4xx-crypto";
115 reg = <0 0xE0100000 0x80400>;
116 interrupt-parent = <&UIC0>;
117 interrupts = <0x17 0x4>;
118 };
119
120 rng@e0120000 {
121 compatible = "amcc,ppc440epx-rng","amcc,ppc4xx-rng";
122 reg = <0 0xE0120000 0x150>;
123 };
124
113 DMA0: dma { 125 DMA0: dma {
114 compatible = "ibm,dma-440epx", "ibm,dma-4xx"; 126 compatible = "ibm,dma-440epx", "ibm,dma-4xx";
115 dcr-reg = <0x100 0x027>; 127 dcr-reg = <0x100 0x027>;
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index feb4ef6bd144..38c35404bdc3 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -240,6 +240,8 @@
240 #address-cells = <2>; 240 #address-cells = <2>;
241 #size-cells = <1>; 241 #size-cells = <1>;
242 reg = <0xe0005000 0x40>; 242 reg = <0xe0005000 0x40>;
243 interrupt-parent = <&mpic>;
244 interrupts = <19 2>;
243 245
244 ranges = <0 0 0xfc000000 0x04000000 246 ranges = <0 0 0xfc000000 0x04000000
245 2 0 0xc8000000 0x04000000 247 2 0 0xc8000000 0x04000000
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 058438f9629b..1657ad0bf8a6 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -337,7 +337,7 @@
337 rx-fifo-size = <4096>; 337 rx-fifo-size = <4096>;
338 tx-fifo-size = <2048>; 338 tx-fifo-size = <2048>;
339 phy-mode = "rgmii"; 339 phy-mode = "rgmii";
340 phy-map = <0x00000001>; 340 phy-address = <1>;
341 rgmii-device = <&RGMII0>; 341 rgmii-device = <&RGMII0>;
342 rgmii-channel = <0>; 342 rgmii-channel = <0>;
343 zmii-device = <&ZMII0>; 343 zmii-device = <&ZMII0>;
@@ -361,7 +361,7 @@
361 rx-fifo-size = <4096>; 361 rx-fifo-size = <4096>;
362 tx-fifo-size = <2048>; 362 tx-fifo-size = <2048>;
363 phy-mode = "rgmii"; 363 phy-mode = "rgmii";
364 phy-map = <0x00000003>; 364 phy-address = <3>;
365 rgmii-device = <&RGMII0>; 365 rgmii-device = <&RGMII0>;
366 rgmii-channel = <1>; 366 rgmii-channel = <1>;
367 zmii-device = <&ZMII0>; 367 zmii-device = <&ZMII0>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 15ca731bc24e..0a4cedbdcb55 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -277,6 +277,48 @@
277 }; 277 };
278 }; 278 };
279 279
280 localbus@e0005000 {
281 #address-cells = <2>;
282 #size-cells = <1>;
283 compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
284 "simple-bus";
285 reg = <0xe0005000 0x1000>;
286 interrupt-parent = <&mpic>;
287 interrupts = <19 2>;
288
289 ranges = <0x0 0x0 0xfe000000 0x02000000>;
290
291 nor@0,0 {
292 #address-cells = <1>;
293 #size-cells = <1>;
294 compatible = "cfi-flash";
295 reg = <0x0 0x0 0x02000000>;
296 bank-width = <4>;
297 device-width = <2>;
298 partition@0 {
299 label = "kernel";
300 reg = <0x00000000 0x00180000>;
301 };
302 partition@180000 {
303 label = "root";
304 reg = <0x00180000 0x01dc0000>;
305 };
306 partition@1f40000 {
307 label = "env1";
308 reg = <0x01f40000 0x00040000>;
309 };
310 partition@1f80000 {
311 label = "env2";
312 reg = <0x01f80000 0x00040000>;
313 };
314 partition@1fc0000 {
315 label = "u-boot";
316 reg = <0x01fc0000 0x00040000>;
317 read-only;
318 };
319 };
320 };
321
280 pci0: pci@e0008000 { 322 pci0: pci@e0008000 {
281 #interrupt-cells = <1>; 323 #interrupt-cells = <1>;
282 #size-cells = <2>; 324 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 5dbb36edb038..9452c3c05114 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -346,6 +346,8 @@
346 #address-cells = <2>; 346 #address-cells = <2>;
347 #size-cells = <1>; 347 #size-cells = <1>;
348 reg = <0xa0005000 0x100>; // BRx, ORx, etc. 348 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
349 351
350 ranges = < 352 ranges = <
351 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index a050ae427108..619776f72c90 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -346,6 +346,8 @@
346 #address-cells = <2>; 346 #address-cells = <2>;
347 #size-cells = <1>; 347 #size-cells = <1>;
348 reg = <0xe0005000 0x100>; // BRx, ORx, etc. 348 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
349 351
350 ranges = < 352 ranges = <
351 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 22ec39b5beeb..7665a16a8b9a 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -312,6 +312,8 @@
312 #address-cells = <2>; 312 #address-cells = <2>;
313 #size-cells = <1>; 313 #size-cells = <1>;
314 reg = <0xe0005000 0x100>; // BRx, ORx, etc. 314 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
315 interrupt-parent = <&mpic>;
316 interrupts = <19 2>;
315 317
316 ranges = < 318 ranges = <
317 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 319 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
index a0cf53fbd55c..c41a80c55e47 100644
--- a/arch/powerpc/boot/dts/xpedite5200.dts
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -374,6 +374,8 @@
374 #address-cells = <2>; 374 #address-cells = <2>;
375 #size-cells = <1>; 375 #size-cells = <1>;
376 reg = <0xef005000 0x100>; // BRx, ORx, etc. 376 reg = <0xef005000 0x100>; // BRx, ORx, etc.
377 interrupt-parent = <&mpic>;
378 interrupts = <19 2>;
377 379
378 ranges = < 380 ranges = <
379 0 0x0 0xfc000000 0x04000000 // NOR boot flash 381 0 0x0 0xfc000000 0x04000000 // NOR boot flash
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
index c5b29752651a..c0efcbb45137 100644
--- a/arch/powerpc/boot/dts/xpedite5200_xmon.dts
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -378,6 +378,8 @@
378 #address-cells = <2>; 378 #address-cells = <2>;
379 #size-cells = <1>; 379 #size-cells = <1>;
380 reg = <0xef005000 0x100>; // BRx, ORx, etc. 380 reg = <0xef005000 0x100>; // BRx, ORx, etc.
381 interrupt-parent = <&mpic>;
382 interrupts = <19 2>;
381 383
382 ranges = < 384 ranges = <
383 0 0x0 0xf8000000 0x08000000 // NOR boot flash 385 0 0x0 0xf8000000 0x08000000 // NOR boot flash
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c b/arch/powerpc/boot/treeboot-iss4xx.c
index fcc44952874e..329e710feda2 100644
--- a/arch/powerpc/boot/treeboot-iss4xx.c
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -34,9 +34,29 @@
34 34
35BSS_STACK(4096); 35BSS_STACK(4096);
36 36
37static u32 ibm4xx_memstart;
38
37static void iss_4xx_fixups(void) 39static void iss_4xx_fixups(void)
38{ 40{
39 ibm4xx_sdram_fixup_memsize(); 41 void *memory;
42 u32 reg[3];
43
44 memory = finddevice("/memory");
45 if (!memory)
46 fatal("Can't find memory node\n");
47 /* This assumes #address-cells = 2, #size-cells =1 and that */
48 getprop(memory, "reg", reg, sizeof(reg));
49 if (reg[2])
50 /* If the device tree specifies the memory range, use it */
51 ibm4xx_memstart = reg[1];
52 else
53 /* othersize, read it from the SDRAM controller */
54 ibm4xx_sdram_fixup_memsize();
55}
56
57static void *iss_4xx_vmlinux_alloc(unsigned long size)
58{
59 return (void *)ibm4xx_memstart;
40} 60}
41 61
42#define SPRN_PIR 0x11E /* Processor Indentification Register */ 62#define SPRN_PIR 0x11E /* Processor Indentification Register */
@@ -48,6 +68,7 @@ void platform_init(void)
48 68
49 simple_alloc_init(_end, avail_ram, 128, 64); 69 simple_alloc_init(_end, avail_ram, 128, 64);
50 platform_ops.fixups = iss_4xx_fixups; 70 platform_ops.fixups = iss_4xx_fixups;
71 platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc;
51 platform_ops.exit = ibm44x_dbcr_reset; 72 platform_ops.exit = ibm44x_dbcr_reset;
52 pir_reg = mfspr(SPRN_PIR); 73 pir_reg = mfspr(SPRN_PIR);
53 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); 74 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig
index 92f863ac8443..a6eb6ad05b2d 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -3,8 +3,8 @@ CONFIG_SMP=y
3CONFIG_EXPERIMENTAL=y 3CONFIG_EXPERIMENTAL=y
4CONFIG_SYSVIPC=y 4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y 5CONFIG_POSIX_MQUEUE=y
6CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14 7CONFIG_LOG_BUF_SHIFT=14
7CONFIG_SYSFS_DEPRECATED_V2=y
8CONFIG_BLK_DEV_INITRD=y 8CONFIG_BLK_DEV_INITRD=y
9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10CONFIG_EXPERT=y 10CONFIG_EXPERT=y
@@ -21,10 +21,11 @@ CONFIG_ISS4xx=y
21CONFIG_HZ_100=y 21CONFIG_HZ_100=y
22CONFIG_MATH_EMULATION=y 22CONFIG_MATH_EMULATION=y
23CONFIG_IRQ_ALL_CPUS=y 23CONFIG_IRQ_ALL_CPUS=y
24CONFIG_SPARSE_IRQ=y
25CONFIG_CMDLINE_BOOL=y 24CONFIG_CMDLINE_BOOL=y
26CONFIG_CMDLINE="root=/dev/issblk0" 25CONFIG_CMDLINE="root=/dev/issblk0"
27# CONFIG_PCI is not set 26# CONFIG_PCI is not set
27CONFIG_ADVANCED_OPTIONS=y
28CONFIG_RELOCATABLE=y
28CONFIG_NET=y 29CONFIG_NET=y
29CONFIG_PACKET=y 30CONFIG_PACKET=y
30CONFIG_UNIX=y 31CONFIG_UNIX=y
@@ -67,7 +68,6 @@ CONFIG_EXT3_FS=y
67# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 68# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
68CONFIG_EXT3_FS_POSIX_ACL=y 69CONFIG_EXT3_FS_POSIX_ACL=y
69CONFIG_EXT3_FS_SECURITY=y 70CONFIG_EXT3_FS_SECURITY=y
70CONFIG_INOTIFY=y
71CONFIG_PROC_KCORE=y 71CONFIG_PROC_KCORE=y
72CONFIG_TMPFS=y 72CONFIG_TMPFS=y
73CONFIG_CRAMFS=y 73CONFIG_CRAMFS=y
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig
new file mode 100644
index 000000000000..980ff8f61fd4
--- /dev/null
+++ b/arch/powerpc/configs/85xx/p1023rds_defconfig
@@ -0,0 +1,173 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=2
4CONFIG_EXPERIMENTAL=y
5CONFIG_SYSVIPC=y
6CONFIG_POSIX_MQUEUE=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_AUDIT=y
9CONFIG_SPARSE_IRQ=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=14
13CONFIG_BLK_DEV_INITRD=y
14# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
15CONFIG_KALLSYMS_ALL=y
16CONFIG_KALLSYMS_EXTRA_PASS=y
17CONFIG_EMBEDDED=y
18CONFIG_MODULES=y
19CONFIG_MODULE_UNLOAD=y
20CONFIG_MODULE_FORCE_UNLOAD=y
21CONFIG_MODVERSIONS=y
22# CONFIG_BLK_DEV_BSG is not set
23CONFIG_P1023_RDS=y
24CONFIG_QUICC_ENGINE=y
25CONFIG_QE_GPIO=y
26CONFIG_CPM2=y
27CONFIG_MPC8xxx_GPIO=y
28CONFIG_HIGHMEM=y
29CONFIG_NO_HZ=y
30CONFIG_HIGH_RES_TIMERS=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32CONFIG_BINFMT_MISC=m
33CONFIG_MATH_EMULATION=y
34CONFIG_SWIOTLB=y
35CONFIG_PCI=y
36CONFIG_PCIEPORTBUS=y
37# CONFIG_PCIEAER is not set
38# CONFIG_PCIEASPM is not set
39CONFIG_PCI_MSI=y
40CONFIG_NET=y
41CONFIG_PACKET=y
42CONFIG_UNIX=y
43CONFIG_XFRM_USER=y
44CONFIG_NET_KEY=y
45CONFIG_INET=y
46CONFIG_IP_MULTICAST=y
47CONFIG_IP_ADVANCED_ROUTER=y
48CONFIG_IP_MULTIPLE_TABLES=y
49CONFIG_IP_ROUTE_MULTIPATH=y
50CONFIG_IP_ROUTE_VERBOSE=y
51CONFIG_IP_PNP=y
52CONFIG_IP_PNP_DHCP=y
53CONFIG_IP_PNP_BOOTP=y
54CONFIG_IP_PNP_RARP=y
55CONFIG_NET_IPIP=y
56CONFIG_IP_MROUTE=y
57CONFIG_IP_PIMSM_V1=y
58CONFIG_IP_PIMSM_V2=y
59CONFIG_ARPD=y
60CONFIG_INET_ESP=y
61# CONFIG_INET_XFRM_MODE_BEET is not set
62# CONFIG_INET_LRO is not set
63CONFIG_IPV6=y
64CONFIG_IP_SCTP=m
65CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
66CONFIG_PROC_DEVICETREE=y
67CONFIG_BLK_DEV_LOOP=y
68CONFIG_BLK_DEV_RAM=y
69CONFIG_BLK_DEV_RAM_SIZE=131072
70CONFIG_MISC_DEVICES=y
71CONFIG_EEPROM_LEGACY=y
72CONFIG_BLK_DEV_SD=y
73CONFIG_CHR_DEV_ST=y
74CONFIG_BLK_DEV_SR=y
75CONFIG_CHR_DEV_SG=y
76CONFIG_SCSI_MULTI_LUN=y
77CONFIG_SCSI_LOGGING=y
78CONFIG_ATA=y
79CONFIG_SATA_FSL=y
80CONFIG_SATA_SIL24=y
81CONFIG_NETDEVICES=y
82CONFIG_DUMMY=y
83CONFIG_MARVELL_PHY=y
84CONFIG_DAVICOM_PHY=y
85CONFIG_CICADA_PHY=y
86CONFIG_VITESSE_PHY=y
87CONFIG_FIXED_PHY=y
88CONFIG_NET_ETHERNET=y
89CONFIG_FS_ENET=y
90CONFIG_E1000E=y
91CONFIG_FSL_PQ_MDIO=y
92CONFIG_INPUT_FF_MEMLESS=m
93# CONFIG_INPUT_MOUSEDEV is not set
94# CONFIG_INPUT_KEYBOARD is not set
95# CONFIG_INPUT_MOUSE is not set
96CONFIG_SERIO_LIBPS2=y
97CONFIG_SERIAL_8250=y
98CONFIG_SERIAL_8250_CONSOLE=y
99CONFIG_SERIAL_8250_NR_UARTS=2
100CONFIG_SERIAL_8250_RUNTIME_UARTS=2
101CONFIG_SERIAL_8250_EXTENDED=y
102CONFIG_SERIAL_8250_MANY_PORTS=y
103CONFIG_SERIAL_8250_DETECT_IRQ=y
104CONFIG_SERIAL_8250_RSA=y
105CONFIG_SERIAL_QE=m
106CONFIG_HW_RANDOM=y
107CONFIG_NVRAM=y
108CONFIG_I2C=y
109CONFIG_I2C_CPM=m
110CONFIG_I2C_MPC=y
111# CONFIG_HWMON is not set
112CONFIG_VIDEO_OUTPUT_CONTROL=y
113CONFIG_SOUND=y
114CONFIG_SND=y
115CONFIG_SND_MIXER_OSS=y
116CONFIG_SND_PCM_OSS=y
117# CONFIG_SND_SUPPORT_OLD_API is not set
118CONFIG_EDAC=y
119CONFIG_EDAC_MM_EDAC=y
120CONFIG_RTC_CLASS=y
121CONFIG_RTC_DRV_CMOS=y
122CONFIG_DMADEVICES=y
123CONFIG_FSL_DMA=y
124# CONFIG_NET_DMA is not set
125CONFIG_STAGING=y
126# CONFIG_STAGING_EXCLUDE_BUILD is not set
127CONFIG_EXT2_FS=y
128CONFIG_EXT3_FS=y
129# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
130CONFIG_ISO9660_FS=m
131CONFIG_JOLIET=y
132CONFIG_ZISOFS=y
133CONFIG_UDF_FS=m
134CONFIG_MSDOS_FS=m
135CONFIG_VFAT_FS=y
136CONFIG_NTFS_FS=y
137CONFIG_PROC_KCORE=y
138CONFIG_TMPFS=y
139CONFIG_ADFS_FS=m
140CONFIG_AFFS_FS=m
141CONFIG_HFS_FS=m
142CONFIG_HFSPLUS_FS=m
143CONFIG_BEFS_FS=m
144CONFIG_BFS_FS=m
145CONFIG_EFS_FS=m
146CONFIG_CRAMFS=y
147CONFIG_VXFS_FS=m
148CONFIG_HPFS_FS=m
149CONFIG_QNX4FS_FS=m
150CONFIG_SYSV_FS=m
151CONFIG_UFS_FS=m
152CONFIG_NFS_FS=y
153CONFIG_NFS_V3=y
154CONFIG_NFS_V4=y
155CONFIG_ROOT_NFS=y
156CONFIG_NFSD=y
157CONFIG_PARTITION_ADVANCED=y
158CONFIG_MAC_PARTITION=y
159CONFIG_CRC_T10DIF=y
160CONFIG_FRAME_WARN=8092
161CONFIG_DEBUG_FS=y
162CONFIG_DEBUG_KERNEL=y
163CONFIG_DETECT_HUNG_TASK=y
164# CONFIG_DEBUG_BUGVERBOSE is not set
165CONFIG_DEBUG_INFO=y
166# CONFIG_RCU_CPU_STALL_DETECTOR is not set
167CONFIG_SYSCTL_SYSCALL_CHECK=y
168CONFIG_VIRQ_DEBUG=y
169CONFIG_CRYPTO_PCBC=m
170CONFIG_CRYPTO_SHA256=y
171CONFIG_CRYPTO_SHA512=y
172CONFIG_CRYPTO_AES=y
173# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
index 036bfb2d18cd..0db9ba0423ff 100644
--- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
@@ -89,6 +89,11 @@ CONFIG_I2C_MPC=y
89CONFIG_VIDEO_OUTPUT_CONTROL=y 89CONFIG_VIDEO_OUTPUT_CONTROL=y
90CONFIG_FB=y 90CONFIG_FB=y
91CONFIG_FB_FSL_DIU=y 91CONFIG_FB_FSL_DIU=y
92CONFIG_VGACON_SOFT_SCROLLBACK=y
93CONFIG_FRAMEBUFFER_CONSOLE=y
94CONFIG_FONTS=y
95CONFIG_FONT_8x8=y
96CONFIG_FONT_8x16=y
92CONFIG_SOUND=y 97CONFIG_SOUND=y
93CONFIG_SND=y 98CONFIG_SND=y
94CONFIG_SND_MIXER_OSS=y 99CONFIG_SND_MIXER_OSS=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
new file mode 100644
index 000000000000..10562a5c65b9
--- /dev/null
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -0,0 +1,187 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=8
4CONFIG_EXPERIMENTAL=y
5CONFIG_SYSVIPC=y
6CONFIG_POSIX_MQUEUE=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_AUDIT=y
9CONFIG_SPARSE_IRQ=y
10CONFIG_RCU_TRACE=y
11CONFIG_IKCONFIG=y
12CONFIG_IKCONFIG_PROC=y
13CONFIG_LOG_BUF_SHIFT=14
14CONFIG_BLK_DEV_INITRD=y
15# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
16CONFIG_KALLSYMS_ALL=y
17CONFIG_KALLSYMS_EXTRA_PASS=y
18CONFIG_EMBEDDED=y
19CONFIG_PERF_EVENTS=y
20CONFIG_SLAB=y
21CONFIG_MODULES=y
22CONFIG_MODULE_UNLOAD=y
23CONFIG_MODULE_FORCE_UNLOAD=y
24CONFIG_MODVERSIONS=y
25# CONFIG_BLK_DEV_BSG is not set
26CONFIG_P2040_RDB=y
27CONFIG_P3041_DS=y
28CONFIG_P4080_DS=y
29CONFIG_P5020_DS=y
30CONFIG_HIGHMEM=y
31CONFIG_NO_HZ=y
32CONFIG_HIGH_RES_TIMERS=y
33# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
34CONFIG_BINFMT_MISC=m
35CONFIG_KEXEC=y
36CONFIG_FORCE_MAX_ZONEORDER=13
37CONFIG_FSL_LBC=y
38CONFIG_PCI=y
39CONFIG_PCIEPORTBUS=y
40# CONFIG_PCIEASPM is not set
41CONFIG_NET=y
42CONFIG_PACKET=y
43CONFIG_UNIX=y
44CONFIG_XFRM_USER=y
45CONFIG_XFRM_SUB_POLICY=y
46CONFIG_XFRM_STATISTICS=y
47CONFIG_NET_KEY=y
48CONFIG_NET_KEY_MIGRATE=y
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_ADVANCED_ROUTER=y
52CONFIG_IP_MULTIPLE_TABLES=y
53CONFIG_IP_ROUTE_MULTIPATH=y
54CONFIG_IP_ROUTE_VERBOSE=y
55CONFIG_IP_PNP=y
56CONFIG_IP_PNP_DHCP=y
57CONFIG_IP_PNP_BOOTP=y
58CONFIG_IP_PNP_RARP=y
59CONFIG_NET_IPIP=y
60CONFIG_IP_MROUTE=y
61CONFIG_IP_PIMSM_V1=y
62CONFIG_IP_PIMSM_V2=y
63CONFIG_ARPD=y
64CONFIG_INET_AH=y
65CONFIG_INET_ESP=y
66CONFIG_INET_IPCOMP=y
67# CONFIG_INET_LRO is not set
68CONFIG_IPV6=y
69CONFIG_IP_SCTP=m
70CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
71CONFIG_MTD=y
72CONFIG_MTD_PARTITIONS=y
73CONFIG_MTD_CMDLINE_PARTS=y
74CONFIG_MTD_CHAR=y
75CONFIG_MTD_BLOCK=y
76CONFIG_MTD_CFI=y
77CONFIG_MTD_CFI_AMDSTD=y
78CONFIG_MTD_PHYSMAP_OF=y
79CONFIG_MTD_M25P80=y
80CONFIG_PROC_DEVICETREE=y
81CONFIG_BLK_DEV_LOOP=y
82CONFIG_BLK_DEV_RAM=y
83CONFIG_BLK_DEV_RAM_SIZE=131072
84CONFIG_MISC_DEVICES=y
85CONFIG_BLK_DEV_SD=y
86CONFIG_CHR_DEV_ST=y
87CONFIG_BLK_DEV_SR=y
88CONFIG_CHR_DEV_SG=y
89CONFIG_SCSI_MULTI_LUN=y
90CONFIG_SCSI_LOGGING=y
91CONFIG_SCSI_SYM53C8XX_2=y
92CONFIG_ATA=y
93CONFIG_SATA_AHCI=y
94CONFIG_SATA_FSL=y
95CONFIG_SATA_SIL24=y
96CONFIG_SATA_SIL=y
97CONFIG_PATA_SIL680=y
98CONFIG_NETDEVICES=y
99CONFIG_VITESSE_PHY=y
100CONFIG_FIXED_PHY=y
101CONFIG_NET_ETHERNET=y
102CONFIG_E1000=y
103CONFIG_E1000E=y
104CONFIG_FSL_PQ_MDIO=y
105# CONFIG_INPUT_MOUSEDEV is not set
106# CONFIG_INPUT_KEYBOARD is not set
107# CONFIG_INPUT_MOUSE is not set
108CONFIG_SERIO_LIBPS2=y
109# CONFIG_LEGACY_PTYS is not set
110CONFIG_PPC_EPAPR_HV_BYTECHAN=y
111CONFIG_SERIAL_8250=y
112CONFIG_SERIAL_8250_CONSOLE=y
113CONFIG_SERIAL_8250_EXTENDED=y
114CONFIG_SERIAL_8250_MANY_PORTS=y
115CONFIG_SERIAL_8250_DETECT_IRQ=y
116CONFIG_SERIAL_8250_RSA=y
117CONFIG_HW_RANDOM=y
118CONFIG_NVRAM=y
119CONFIG_I2C=y
120CONFIG_I2C_MPC=y
121CONFIG_SPI=y
122CONFIG_SPI_GPIO=y
123CONFIG_SPI_FSL_SPI=y
124CONFIG_SPI_FSL_ESPI=y
125# CONFIG_HWMON is not set
126CONFIG_VIDEO_OUTPUT_CONTROL=y
127CONFIG_USB_HID=m
128CONFIG_USB=y
129CONFIG_USB_DEVICEFS=y
130CONFIG_USB_MON=y
131CONFIG_USB_EHCI_HCD=y
132CONFIG_USB_EHCI_FSL=y
133CONFIG_USB_OHCI_HCD=y
134CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
135CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
136CONFIG_USB_STORAGE=y
137CONFIG_MMC=y
138CONFIG_MMC_SDHCI=y
139CONFIG_MMC_SDHCI_OF=y
140CONFIG_MMC_SDHCI_OF_ESDHC=y
141CONFIG_EDAC=y
142CONFIG_EDAC_MM_EDAC=y
143CONFIG_EDAC_MPC85XX=y
144CONFIG_RTC_CLASS=y
145CONFIG_RTC_DRV_DS3232=y
146CONFIG_RTC_DRV_CMOS=y
147CONFIG_UIO=y
148CONFIG_STAGING=y
149# CONFIG_STAGING_EXCLUDE_BUILD is not set
150CONFIG_VIRT_DRIVERS=y
151CONFIG_FSL_HV_MANAGER=y
152CONFIG_EXT2_FS=y
153CONFIG_EXT3_FS=y
154# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
155CONFIG_ISO9660_FS=m
156CONFIG_JOLIET=y
157CONFIG_ZISOFS=y
158CONFIG_UDF_FS=m
159CONFIG_MSDOS_FS=m
160CONFIG_VFAT_FS=y
161CONFIG_NTFS_FS=y
162CONFIG_PROC_KCORE=y
163CONFIG_TMPFS=y
164CONFIG_JFFS2_FS=y
165CONFIG_CRAMFS=y
166CONFIG_NFS_FS=y
167CONFIG_NFS_V3=y
168CONFIG_NFS_V4=y
169CONFIG_ROOT_NFS=y
170CONFIG_NFSD=m
171CONFIG_PARTITION_ADVANCED=y
172CONFIG_MAC_PARTITION=y
173CONFIG_NLS_ISO8859_1=y
174CONFIG_NLS_UTF8=m
175CONFIG_MAGIC_SYSRQ=y
176CONFIG_DEBUG_KERNEL=y
177CONFIG_DEBUG_SHIRQ=y
178CONFIG_DETECT_HUNG_TASK=y
179CONFIG_DEBUG_INFO=y
180CONFIG_SYSCTL_SYSCALL_CHECK=y
181CONFIG_CRYPTO_NULL=y
182CONFIG_CRYPTO_PCBC=m
183CONFIG_CRYPTO_MD4=y
184CONFIG_CRYPTO_SHA256=y
185CONFIG_CRYPTO_SHA512=y
186CONFIG_CRYPTO_AES=y
187# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index d32283555b53..d32283555b53 100644
--- a/arch/powerpc/configs/e55xx_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 96b89df7752a..fcd85d2c72dc 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y 5CONFIG_POSIX_MQUEUE=y
6CONFIG_BSD_PROCESS_ACCT=y 6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_AUDIT=y 7CONFIG_AUDIT=y
8CONFIG_SPARSE_IRQ=y
8CONFIG_IKCONFIG=y 9CONFIG_IKCONFIG=y
9CONFIG_IKCONFIG_PROC=y 10CONFIG_IKCONFIG_PROC=y
10CONFIG_LOG_BUF_SHIFT=14 11CONFIG_LOG_BUF_SHIFT=14
@@ -25,7 +26,9 @@ CONFIG_MPC85xx_MDS=y
25CONFIG_MPC8536_DS=y 26CONFIG_MPC8536_DS=y
26CONFIG_MPC85xx_DS=y 27CONFIG_MPC85xx_DS=y
27CONFIG_MPC85xx_RDB=y 28CONFIG_MPC85xx_RDB=y
29CONFIG_P1010_RDB=y
28CONFIG_P1022_DS=y 30CONFIG_P1022_DS=y
31CONFIG_P1023_RDS=y
29CONFIG_SOCRATES=y 32CONFIG_SOCRATES=y
30CONFIG_KSI8560=y 33CONFIG_KSI8560=y
31CONFIG_XES_MPC85xx=y 34CONFIG_XES_MPC85xx=y
@@ -44,7 +47,6 @@ CONFIG_NO_HZ=y
44CONFIG_HIGH_RES_TIMERS=y 47CONFIG_HIGH_RES_TIMERS=y
45CONFIG_BINFMT_MISC=m 48CONFIG_BINFMT_MISC=m
46CONFIG_MATH_EMULATION=y 49CONFIG_MATH_EMULATION=y
47CONFIG_SPARSE_IRQ=y
48CONFIG_FORCE_MAX_ZONEORDER=12 50CONFIG_FORCE_MAX_ZONEORDER=12
49CONFIG_PCI=y 51CONFIG_PCI=y
50CONFIG_PCI_MSI=y 52CONFIG_PCI_MSI=y
@@ -65,8 +67,6 @@ CONFIG_IP_PNP_DHCP=y
65CONFIG_IP_PNP_BOOTP=y 67CONFIG_IP_PNP_BOOTP=y
66CONFIG_IP_PNP_RARP=y 68CONFIG_IP_PNP_RARP=y
67CONFIG_NET_IPIP=y 69CONFIG_NET_IPIP=y
68CONFIG_NET_IPGRE=y
69CONFIG_NET_IPGRE_BROADCAST=y
70CONFIG_IP_MROUTE=y 70CONFIG_IP_MROUTE=y
71CONFIG_IP_PIMSM_V1=y 71CONFIG_IP_PIMSM_V1=y
72CONFIG_IP_PIMSM_V2=y 72CONFIG_IP_PIMSM_V2=y
@@ -128,6 +128,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
128CONFIG_FB=y 128CONFIG_FB=y
129CONFIG_FB_FSL_DIU=y 129CONFIG_FB_FSL_DIU=y
130# CONFIG_VGA_CONSOLE is not set 130# CONFIG_VGA_CONSOLE is not set
131CONFIG_FRAMEBUFFER_CONSOLE=y
132CONFIG_FONTS=y
133CONFIG_FONT_8x8=y
134CONFIG_FONT_8x16=y
131CONFIG_SOUND=y 135CONFIG_SOUND=y
132CONFIG_SND=y 136CONFIG_SND=y
133# CONFIG_SND_SUPPORT_OLD_API is not set 137# CONFIG_SND_SUPPORT_OLD_API is not set
@@ -170,7 +174,6 @@ CONFIG_FSL_DMA=y
170CONFIG_EXT2_FS=y 174CONFIG_EXT2_FS=y
171CONFIG_EXT3_FS=y 175CONFIG_EXT3_FS=y
172# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 176# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
173CONFIG_INOTIFY=y
174CONFIG_ISO9660_FS=m 177CONFIG_ISO9660_FS=m
175CONFIG_JOLIET=y 178CONFIG_JOLIET=y
176CONFIG_ZISOFS=y 179CONFIG_ZISOFS=y
@@ -205,7 +208,6 @@ CONFIG_DEBUG_FS=y
205CONFIG_DEBUG_KERNEL=y 208CONFIG_DEBUG_KERNEL=y
206CONFIG_DETECT_HUNG_TASK=y 209CONFIG_DETECT_HUNG_TASK=y
207CONFIG_DEBUG_INFO=y 210CONFIG_DEBUG_INFO=y
208# CONFIG_RCU_CPU_STALL_DETECTOR is not set
209CONFIG_SYSCTL_SYSCALL_CHECK=y 211CONFIG_SYSCTL_SYSCALL_CHECK=y
210CONFIG_VIRQ_DEBUG=y 212CONFIG_VIRQ_DEBUG=y
211CONFIG_CRYPTO_PCBC=m 213CONFIG_CRYPTO_PCBC=m
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index de65841aa04e..908c941fc24c 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYSVIPC=y
7CONFIG_POSIX_MQUEUE=y 7CONFIG_POSIX_MQUEUE=y
8CONFIG_BSD_PROCESS_ACCT=y 8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_AUDIT=y 9CONFIG_AUDIT=y
10CONFIG_SPARSE_IRQ=y
10CONFIG_IKCONFIG=y 11CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y 12CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=14 13CONFIG_LOG_BUF_SHIFT=14
@@ -28,6 +29,7 @@ CONFIG_MPC8536_DS=y
28CONFIG_MPC85xx_DS=y 29CONFIG_MPC85xx_DS=y
29CONFIG_MPC85xx_RDB=y 30CONFIG_MPC85xx_RDB=y
30CONFIG_P1022_DS=y 31CONFIG_P1022_DS=y
32CONFIG_P1023_RDS=y
31CONFIG_SOCRATES=y 33CONFIG_SOCRATES=y
32CONFIG_KSI8560=y 34CONFIG_KSI8560=y
33CONFIG_XES_MPC85xx=y 35CONFIG_XES_MPC85xx=y
@@ -46,7 +48,6 @@ CONFIG_NO_HZ=y
46CONFIG_HIGH_RES_TIMERS=y 48CONFIG_HIGH_RES_TIMERS=y
47CONFIG_BINFMT_MISC=m 49CONFIG_BINFMT_MISC=m
48CONFIG_MATH_EMULATION=y 50CONFIG_MATH_EMULATION=y
49CONFIG_SPARSE_IRQ=y
50CONFIG_FORCE_MAX_ZONEORDER=12 51CONFIG_FORCE_MAX_ZONEORDER=12
51CONFIG_PCI=y 52CONFIG_PCI=y
52CONFIG_PCI_MSI=y 53CONFIG_PCI_MSI=y
@@ -67,8 +68,6 @@ CONFIG_IP_PNP_DHCP=y
67CONFIG_IP_PNP_BOOTP=y 68CONFIG_IP_PNP_BOOTP=y
68CONFIG_IP_PNP_RARP=y 69CONFIG_IP_PNP_RARP=y
69CONFIG_NET_IPIP=y 70CONFIG_NET_IPIP=y
70CONFIG_NET_IPGRE=y
71CONFIG_NET_IPGRE_BROADCAST=y
72CONFIG_IP_MROUTE=y 71CONFIG_IP_MROUTE=y
73CONFIG_IP_PIMSM_V1=y 72CONFIG_IP_PIMSM_V1=y
74CONFIG_IP_PIMSM_V2=y 73CONFIG_IP_PIMSM_V2=y
@@ -130,6 +129,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
130CONFIG_FB=y 129CONFIG_FB=y
131CONFIG_FB_FSL_DIU=y 130CONFIG_FB_FSL_DIU=y
132# CONFIG_VGA_CONSOLE is not set 131# CONFIG_VGA_CONSOLE is not set
132CONFIG_FRAMEBUFFER_CONSOLE=y
133CONFIG_FONTS=y
134CONFIG_FONT_8x8=y
135CONFIG_FONT_8x16=y
133CONFIG_SOUND=y 136CONFIG_SOUND=y
134CONFIG_SND=y 137CONFIG_SND=y
135# CONFIG_SND_SUPPORT_OLD_API is not set 138# CONFIG_SND_SUPPORT_OLD_API is not set
@@ -172,7 +175,6 @@ CONFIG_FSL_DMA=y
172CONFIG_EXT2_FS=y 175CONFIG_EXT2_FS=y
173CONFIG_EXT3_FS=y 176CONFIG_EXT3_FS=y
174# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 177# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
175CONFIG_INOTIFY=y
176CONFIG_ISO9660_FS=m 178CONFIG_ISO9660_FS=m
177CONFIG_JOLIET=y 179CONFIG_JOLIET=y
178CONFIG_ZISOFS=y 180CONFIG_ZISOFS=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 76736017cd34..84a685a505fe 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -176,12 +176,19 @@ CONFIG_CHR_DEV_SG=y
176CONFIG_SCSI_MULTI_LUN=y 176CONFIG_SCSI_MULTI_LUN=y
177CONFIG_SCSI_CONSTANTS=y 177CONFIG_SCSI_CONSTANTS=y
178CONFIG_SCSI_FC_ATTRS=y 178CONFIG_SCSI_FC_ATTRS=y
179CONFIG_SCSI_SAS_ATTRS=m
180CONFIG_SCSI_CXGB3_ISCSI=m
181CONFIG_SCSI_CXGB4_ISCSI=m
182CONFIG_SCSI_BNX2_ISCSI=m
183CONFIG_BE2ISCSI=m
184CONFIG_SCSI_MPT2SAS=m
179CONFIG_SCSI_IBMVSCSI=y 185CONFIG_SCSI_IBMVSCSI=y
180CONFIG_SCSI_IBMVFC=m 186CONFIG_SCSI_IBMVFC=m
181CONFIG_SCSI_SYM53C8XX_2=y 187CONFIG_SCSI_SYM53C8XX_2=y
182CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 188CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
183CONFIG_SCSI_IPR=y 189CONFIG_SCSI_IPR=y
184CONFIG_SCSI_QLA_FC=m 190CONFIG_SCSI_QLA_FC=m
191CONFIG_SCSI_QLA_ISCSI=m
185CONFIG_SCSI_LPFC=m 192CONFIG_SCSI_LPFC=m
186CONFIG_ATA=y 193CONFIG_ATA=y
187CONFIG_SATA_SIL24=y 194CONFIG_SATA_SIL24=y
@@ -235,11 +242,13 @@ CONFIG_ACENIC_OMIT_TIGON_I=y
235CONFIG_E1000=y 242CONFIG_E1000=y
236CONFIG_E1000E=y 243CONFIG_E1000E=y
237CONFIG_TIGON3=y 244CONFIG_TIGON3=y
245CONFIG_BNX2=m
238CONFIG_SPIDER_NET=m 246CONFIG_SPIDER_NET=m
239CONFIG_GELIC_NET=m 247CONFIG_GELIC_NET=m
240CONFIG_GELIC_WIRELESS=y 248CONFIG_GELIC_WIRELESS=y
241CONFIG_CHELSIO_T1=m 249CONFIG_CHELSIO_T1=m
242CONFIG_CHELSIO_T3=m 250CONFIG_CHELSIO_T3=m
251CONFIG_CHELSIO_T4=m
243CONFIG_EHEA=m 252CONFIG_EHEA=m
244CONFIG_IXGBE=m 253CONFIG_IXGBE=m
245CONFIG_IXGB=m 254CONFIG_IXGB=m
@@ -248,6 +257,8 @@ CONFIG_MYRI10GE=m
248CONFIG_NETXEN_NIC=m 257CONFIG_NETXEN_NIC=m
249CONFIG_PASEMI_MAC=y 258CONFIG_PASEMI_MAC=y
250CONFIG_MLX4_EN=m 259CONFIG_MLX4_EN=m
260CONFIG_QLGE=m
261CONFIG_BE2NET=m
251CONFIG_ISERIES_VETH=m 262CONFIG_ISERIES_VETH=m
252CONFIG_PPP=m 263CONFIG_PPP=m
253CONFIG_PPP_ASYNC=m 264CONFIG_PPP_ASYNC=m
@@ -330,6 +341,8 @@ CONFIG_INFINIBAND_USER_MAD=m
330CONFIG_INFINIBAND_USER_ACCESS=m 341CONFIG_INFINIBAND_USER_ACCESS=m
331CONFIG_INFINIBAND_MTHCA=m 342CONFIG_INFINIBAND_MTHCA=m
332CONFIG_INFINIBAND_EHCA=m 343CONFIG_INFINIBAND_EHCA=m
344CONFIG_INFINIBAND_CXGB3=m
345CONFIG_INFINIBAND_CXGB4=m
333CONFIG_MLX4_INFINIBAND=m 346CONFIG_MLX4_INFINIBAND=m
334CONFIG_INFINIBAND_IPOIB=m 347CONFIG_INFINIBAND_IPOIB=m
335CONFIG_INFINIBAND_IPOIB_CM=y 348CONFIG_INFINIBAND_IPOIB_CM=y
@@ -430,11 +443,12 @@ CONFIG_NLS_KOI8_U=m
430CONFIG_CRC_T10DIF=y 443CONFIG_CRC_T10DIF=y
431CONFIG_MAGIC_SYSRQ=y 444CONFIG_MAGIC_SYSRQ=y
432CONFIG_DEBUG_KERNEL=y 445CONFIG_DEBUG_KERNEL=y
446CONFIG_LOCKUP_DETECTOR=y
447CONFIG_DETECT_HUNG_TASK=y
433CONFIG_DEBUG_MUTEXES=y 448CONFIG_DEBUG_MUTEXES=y
434# CONFIG_RCU_CPU_STALL_DETECTOR is not set 449# CONFIG_RCU_CPU_STALL_DETECTOR is not set
435CONFIG_LATENCYTOP=y 450CONFIG_LATENCYTOP=y
436CONFIG_SYSCTL_SYSCALL_CHECK=y 451CONFIG_SYSCTL_SYSCALL_CHECK=y
437CONFIG_IRQSOFF_TRACER=y
438CONFIG_SCHED_TRACER=y 452CONFIG_SCHED_TRACER=y
439CONFIG_BLK_DEV_IO_TRACE=y 453CONFIG_BLK_DEV_IO_TRACE=y
440CONFIG_DEBUG_STACKOVERFLOW=y 454CONFIG_DEBUG_STACKOVERFLOW=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 80bc5de7ee1d..96a58b709705 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -149,6 +149,7 @@ CONFIG_SCSI_CXGB3_ISCSI=m
149CONFIG_SCSI_CXGB4_ISCSI=m 149CONFIG_SCSI_CXGB4_ISCSI=m
150CONFIG_SCSI_BNX2_ISCSI=m 150CONFIG_SCSI_BNX2_ISCSI=m
151CONFIG_BE2ISCSI=m 151CONFIG_BE2ISCSI=m
152CONFIG_SCSI_MPT2SAS=m
152CONFIG_SCSI_IBMVSCSI=y 153CONFIG_SCSI_IBMVSCSI=y
153CONFIG_SCSI_IBMVFC=m 154CONFIG_SCSI_IBMVFC=m
154CONFIG_SCSI_SYM53C8XX_2=y 155CONFIG_SCSI_SYM53C8XX_2=y
@@ -320,6 +321,8 @@ CONFIG_NLS_ISO8859_1=y
320CONFIG_CRC_T10DIF=y 321CONFIG_CRC_T10DIF=y
321CONFIG_MAGIC_SYSRQ=y 322CONFIG_MAGIC_SYSRQ=y
322CONFIG_DEBUG_KERNEL=y 323CONFIG_DEBUG_KERNEL=y
324CONFIG_LOCKUP_DETECTOR=y
325CONFIG_DETECT_HUNG_TASK=y
323# CONFIG_RCU_CPU_STALL_DETECTOR is not set 326# CONFIG_RCU_CPU_STALL_DETECTOR is not set
324CONFIG_LATENCYTOP=y 327CONFIG_LATENCYTOP=y
325CONFIG_SYSCTL_SYSCALL_CHECK=y 328CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 9c70d0ca96d4..efa74ac44a35 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -18,7 +18,7 @@
18#include <asm/ppc-opcode.h> 18#include <asm/ppc-opcode.h>
19 19
20#define PPC_DBELL_MSG_BRDCAST (0x04000000) 20#define PPC_DBELL_MSG_BRDCAST (0x04000000)
21#define PPC_DBELL_TYPE(x) (((x) & 0xf) << 28) 21#define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
22enum ppc_dbell { 22enum ppc_dbell {
23 PPC_DBELL = 0, /* doorbell */ 23 PPC_DBELL = 0, /* doorbell */
24 PPC_DBELL_CRIT = 1, /* critical doorbell */ 24 PPC_DBELL_CRIT = 1, /* critical doorbell */
diff --git a/arch/powerpc/include/asm/ehv_pic.h b/arch/powerpc/include/asm/ehv_pic.h
new file mode 100644
index 000000000000..a9e1f4f796f6
--- /dev/null
+++ b/arch/powerpc/include/asm/ehv_pic.h
@@ -0,0 +1,40 @@
1/*
2 * EHV_PIC private definitions and structure.
3 *
4 * Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef __EHV_PIC_H__
11#define __EHV_PIC_H__
12
13#include <linux/irq.h>
14
15#define NR_EHV_PIC_INTS 1024
16
17#define EHV_PIC_INFO(name) EHV_PIC_##name
18
19#define EHV_PIC_VECPRI_POLARITY_NEGATIVE 0
20#define EHV_PIC_VECPRI_POLARITY_POSITIVE 1
21#define EHV_PIC_VECPRI_SENSE_EDGE 0
22#define EHV_PIC_VECPRI_SENSE_LEVEL 0x2
23#define EHV_PIC_VECPRI_POLARITY_MASK 0x1
24#define EHV_PIC_VECPRI_SENSE_MASK 0x2
25
26struct ehv_pic {
27 /* The remapper for this EHV_PIC */
28 struct irq_host *irqhost;
29
30 /* The "linux" controller struct */
31 struct irq_chip hc_irq;
32
33 /* core int flag */
34 int coreint_flag;
35};
36
37void ehv_pic_init(void);
38unsigned int ehv_pic_get_irq(void);
39
40#endif /* __EHV_PIC_H__ */
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
new file mode 100644
index 000000000000..f3b0c2cc9fea
--- /dev/null
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -0,0 +1,502 @@
1/*
2 * ePAPR hcall interface
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Author: Timur Tabi <timur@freescale.com>
7 *
8 * This file is provided under a dual BSD/GPL license. When using or
9 * redistributing this file, you may do so under either license.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 * * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * * Neither the name of Freescale Semiconductor nor the
19 * names of its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") as published by the Free Software
25 * Foundation, either version 2 of that License or (at your option) any
26 * later version.
27 *
28 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
29 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
30 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
32 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40/* A "hypercall" is an "sc 1" instruction. This header file file provides C
41 * wrapper functions for the ePAPR hypervisor interface. It is inteded
42 * for use by Linux device drivers and other operating systems.
43 *
44 * The hypercalls are implemented as inline assembly, rather than assembly
45 * language functions in a .S file, for optimization. It allows
46 * the caller to issue the hypercall instruction directly, improving both
47 * performance and memory footprint.
48 */
49
50#ifndef _EPAPR_HCALLS_H
51#define _EPAPR_HCALLS_H
52
53#include <linux/types.h>
54#include <linux/errno.h>
55#include <asm/byteorder.h>
56
57#define EV_BYTE_CHANNEL_SEND 1
58#define EV_BYTE_CHANNEL_RECEIVE 2
59#define EV_BYTE_CHANNEL_POLL 3
60#define EV_INT_SET_CONFIG 4
61#define EV_INT_GET_CONFIG 5
62#define EV_INT_SET_MASK 6
63#define EV_INT_GET_MASK 7
64#define EV_INT_IACK 9
65#define EV_INT_EOI 10
66#define EV_INT_SEND_IPI 11
67#define EV_INT_SET_TASK_PRIORITY 12
68#define EV_INT_GET_TASK_PRIORITY 13
69#define EV_DOORBELL_SEND 14
70#define EV_MSGSND 15
71#define EV_IDLE 16
72
73/* vendor ID: epapr */
74#define EV_LOCAL_VENDOR_ID 0 /* for private use */
75#define EV_EPAPR_VENDOR_ID 1
76#define EV_FSL_VENDOR_ID 2 /* Freescale Semiconductor */
77#define EV_IBM_VENDOR_ID 3 /* IBM */
78#define EV_GHS_VENDOR_ID 4 /* Green Hills Software */
79#define EV_ENEA_VENDOR_ID 5 /* Enea */
80#define EV_WR_VENDOR_ID 6 /* Wind River Systems */
81#define EV_AMCC_VENDOR_ID 7 /* Applied Micro Circuits */
82#define EV_KVM_VENDOR_ID 42 /* KVM */
83
84/* The max number of bytes that a byte channel can send or receive per call */
85#define EV_BYTE_CHANNEL_MAX_BYTES 16
86
87
88#define _EV_HCALL_TOKEN(id, num) (((id) << 16) | (num))
89#define EV_HCALL_TOKEN(hcall_num) _EV_HCALL_TOKEN(EV_EPAPR_VENDOR_ID, hcall_num)
90
91/* epapr error codes */
92#define EV_EPERM 1 /* Operation not permitted */
93#define EV_ENOENT 2 /* Entry Not Found */
94#define EV_EIO 3 /* I/O error occured */
95#define EV_EAGAIN 4 /* The operation had insufficient
96 * resources to complete and should be
97 * retried
98 */
99#define EV_ENOMEM 5 /* There was insufficient memory to
100 * complete the operation */
101#define EV_EFAULT 6 /* Bad guest address */
102#define EV_ENODEV 7 /* No such device */
103#define EV_EINVAL 8 /* An argument supplied to the hcall
104 was out of range or invalid */
105#define EV_INTERNAL 9 /* An internal error occured */
106#define EV_CONFIG 10 /* A configuration error was detected */
107#define EV_INVALID_STATE 11 /* The object is in an invalid state */
108#define EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */
109#define EV_BUFFER_OVERFLOW 13 /* Caller-supplied buffer too small */
110
111/*
112 * Hypercall register clobber list
113 *
114 * These macros are used to define the list of clobbered registers during a
115 * hypercall. Technically, registers r0 and r3-r12 are always clobbered,
116 * but the gcc inline assembly syntax does not allow us to specify registers
117 * on the clobber list that are also on the input/output list. Therefore,
118 * the lists of clobbered registers depends on the number of register
119 * parmeters ("+r" and "=r") passed to the hypercall.
120 *
121 * Each assembly block should use one of the HCALL_CLOBBERSx macros. As a
122 * general rule, 'x' is the number of parameters passed to the assembly
123 * block *except* for r11.
124 *
125 * If you're not sure, just use the smallest value of 'x' that does not
126 * generate a compilation error. Because these are static inline functions,
127 * the compiler will only check the clobber list for a function if you
128 * compile code that calls that function.
129 *
130 * r3 and r11 are not included in any clobbers list because they are always
131 * listed as output registers.
132 *
133 * XER, CTR, and LR are currently listed as clobbers because it's uncertain
134 * whether they will be clobbered.
135 *
136 * Note that r11 can be used as an output parameter.
137*/
138
139/* List of common clobbered registers. Do not use this macro. */
140#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc"
141
142#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
143#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
144#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9"
145#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8"
146#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7"
147#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6"
148#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
149#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
150
151
152/*
153 * We use "uintptr_t" to define a register because it's guaranteed to be a
154 * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
155 * platform.
156 *
157 * All registers are either input/output or output only. Registers that are
158 * initialized before making the hypercall are input/output. All
159 * input/output registers are represented with "+r". Output-only registers
160 * are represented with "=r". Do not specify any unused registers. The
161 * clobber list will tell the compiler that the hypercall modifies those
162 * registers, which is good enough.
163 */
164
165/**
166 * ev_int_set_config - configure the specified interrupt
167 * @interrupt: the interrupt number
168 * @config: configuration for this interrupt
169 * @priority: interrupt priority
170 * @destination: destination CPU number
171 *
172 * Returns 0 for success, or an error code.
173 */
174static inline unsigned int ev_int_set_config(unsigned int interrupt,
175 uint32_t config, unsigned int priority, uint32_t destination)
176{
177 register uintptr_t r11 __asm__("r11");
178 register uintptr_t r3 __asm__("r3");
179 register uintptr_t r4 __asm__("r4");
180 register uintptr_t r5 __asm__("r5");
181 register uintptr_t r6 __asm__("r6");
182
183 r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG);
184 r3 = interrupt;
185 r4 = config;
186 r5 = priority;
187 r6 = destination;
188
189 __asm__ __volatile__ ("sc 1"
190 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6)
191 : : EV_HCALL_CLOBBERS4
192 );
193
194 return r3;
195}
196
197/**
198 * ev_int_get_config - return the config of the specified interrupt
199 * @interrupt: the interrupt number
200 * @config: returned configuration for this interrupt
201 * @priority: returned interrupt priority
202 * @destination: returned destination CPU number
203 *
204 * Returns 0 for success, or an error code.
205 */
206static inline unsigned int ev_int_get_config(unsigned int interrupt,
207 uint32_t *config, unsigned int *priority, uint32_t *destination)
208{
209 register uintptr_t r11 __asm__("r11");
210 register uintptr_t r3 __asm__("r3");
211 register uintptr_t r4 __asm__("r4");
212 register uintptr_t r5 __asm__("r5");
213 register uintptr_t r6 __asm__("r6");
214
215 r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG);
216 r3 = interrupt;
217
218 __asm__ __volatile__ ("sc 1"
219 : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6)
220 : : EV_HCALL_CLOBBERS4
221 );
222
223 *config = r4;
224 *priority = r5;
225 *destination = r6;
226
227 return r3;
228}
229
230/**
231 * ev_int_set_mask - sets the mask for the specified interrupt source
232 * @interrupt: the interrupt number
233 * @mask: 0=enable interrupts, 1=disable interrupts
234 *
235 * Returns 0 for success, or an error code.
236 */
237static inline unsigned int ev_int_set_mask(unsigned int interrupt,
238 unsigned int mask)
239{
240 register uintptr_t r11 __asm__("r11");
241 register uintptr_t r3 __asm__("r3");
242 register uintptr_t r4 __asm__("r4");
243
244 r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK);
245 r3 = interrupt;
246 r4 = mask;
247
248 __asm__ __volatile__ ("sc 1"
249 : "+r" (r11), "+r" (r3), "+r" (r4)
250 : : EV_HCALL_CLOBBERS2
251 );
252
253 return r3;
254}
255
256/**
257 * ev_int_get_mask - returns the mask for the specified interrupt source
258 * @interrupt: the interrupt number
259 * @mask: returned mask for this interrupt (0=enabled, 1=disabled)
260 *
261 * Returns 0 for success, or an error code.
262 */
263static inline unsigned int ev_int_get_mask(unsigned int interrupt,
264 unsigned int *mask)
265{
266 register uintptr_t r11 __asm__("r11");
267 register uintptr_t r3 __asm__("r3");
268 register uintptr_t r4 __asm__("r4");
269
270 r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK);
271 r3 = interrupt;
272
273 __asm__ __volatile__ ("sc 1"
274 : "+r" (r11), "+r" (r3), "=r" (r4)
275 : : EV_HCALL_CLOBBERS2
276 );
277
278 *mask = r4;
279
280 return r3;
281}
282
283/**
284 * ev_int_eoi - signal the end of interrupt processing
285 * @interrupt: the interrupt number
286 *
287 * This function signals the end of processing for the the specified
288 * interrupt, which must be the interrupt currently in service. By
289 * definition, this is also the highest-priority interrupt.
290 *
291 * Returns 0 for success, or an error code.
292 */
293static inline unsigned int ev_int_eoi(unsigned int interrupt)
294{
295 register uintptr_t r11 __asm__("r11");
296 register uintptr_t r3 __asm__("r3");
297
298 r11 = EV_HCALL_TOKEN(EV_INT_EOI);
299 r3 = interrupt;
300
301 __asm__ __volatile__ ("sc 1"
302 : "+r" (r11), "+r" (r3)
303 : : EV_HCALL_CLOBBERS1
304 );
305
306 return r3;
307}
308
309/**
310 * ev_byte_channel_send - send characters to a byte stream
311 * @handle: byte stream handle
312 * @count: (input) num of chars to send, (output) num chars sent
313 * @buffer: pointer to a 16-byte buffer
314 *
315 * @buffer must be at least 16 bytes long, because all 16 bytes will be
316 * read from memory into registers, even if count < 16.
317 *
318 * Returns 0 for success, or an error code.
319 */
320static inline unsigned int ev_byte_channel_send(unsigned int handle,
321 unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
322{
323 register uintptr_t r11 __asm__("r11");
324 register uintptr_t r3 __asm__("r3");
325 register uintptr_t r4 __asm__("r4");
326 register uintptr_t r5 __asm__("r5");
327 register uintptr_t r6 __asm__("r6");
328 register uintptr_t r7 __asm__("r7");
329 register uintptr_t r8 __asm__("r8");
330 const uint32_t *p = (const uint32_t *) buffer;
331
332 r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND);
333 r3 = handle;
334 r4 = *count;
335 r5 = be32_to_cpu(p[0]);
336 r6 = be32_to_cpu(p[1]);
337 r7 = be32_to_cpu(p[2]);
338 r8 = be32_to_cpu(p[3]);
339
340 __asm__ __volatile__ ("sc 1"
341 : "+r" (r11), "+r" (r3),
342 "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8)
343 : : EV_HCALL_CLOBBERS6
344 );
345
346 *count = r4;
347
348 return r3;
349}
350
351/**
352 * ev_byte_channel_receive - fetch characters from a byte channel
353 * @handle: byte channel handle
354 * @count: (input) max num of chars to receive, (output) num chars received
355 * @buffer: pointer to a 16-byte buffer
356 *
357 * The size of @buffer must be at least 16 bytes, even if you request fewer
358 * than 16 characters, because we always write 16 bytes to @buffer. This is
359 * for performance reasons.
360 *
361 * Returns 0 for success, or an error code.
362 */
363static inline unsigned int ev_byte_channel_receive(unsigned int handle,
364 unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
365{
366 register uintptr_t r11 __asm__("r11");
367 register uintptr_t r3 __asm__("r3");
368 register uintptr_t r4 __asm__("r4");
369 register uintptr_t r5 __asm__("r5");
370 register uintptr_t r6 __asm__("r6");
371 register uintptr_t r7 __asm__("r7");
372 register uintptr_t r8 __asm__("r8");
373 uint32_t *p = (uint32_t *) buffer;
374
375 r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE);
376 r3 = handle;
377 r4 = *count;
378
379 __asm__ __volatile__ ("sc 1"
380 : "+r" (r11), "+r" (r3), "+r" (r4),
381 "=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8)
382 : : EV_HCALL_CLOBBERS6
383 );
384
385 *count = r4;
386 p[0] = cpu_to_be32(r5);
387 p[1] = cpu_to_be32(r6);
388 p[2] = cpu_to_be32(r7);
389 p[3] = cpu_to_be32(r8);
390
391 return r3;
392}
393
394/**
395 * ev_byte_channel_poll - returns the status of the byte channel buffers
396 * @handle: byte channel handle
397 * @rx_count: returned count of bytes in receive queue
398 * @tx_count: returned count of free space in transmit queue
399 *
400 * This function reports the amount of data in the receive queue (i.e. the
401 * number of bytes you can read), and the amount of free space in the transmit
402 * queue (i.e. the number of bytes you can write).
403 *
404 * Returns 0 for success, or an error code.
405 */
406static inline unsigned int ev_byte_channel_poll(unsigned int handle,
407 unsigned int *rx_count, unsigned int *tx_count)
408{
409 register uintptr_t r11 __asm__("r11");
410 register uintptr_t r3 __asm__("r3");
411 register uintptr_t r4 __asm__("r4");
412 register uintptr_t r5 __asm__("r5");
413
414 r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL);
415 r3 = handle;
416
417 __asm__ __volatile__ ("sc 1"
418 : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5)
419 : : EV_HCALL_CLOBBERS3
420 );
421
422 *rx_count = r4;
423 *tx_count = r5;
424
425 return r3;
426}
427
428/**
429 * ev_int_iack - acknowledge an interrupt
430 * @handle: handle to the target interrupt controller
431 * @vector: returned interrupt vector
432 *
433 * If handle is zero, the function returns the next interrupt source
434 * number to be handled irrespective of the hierarchy or cascading
435 * of interrupt controllers. If non-zero, specifies a handle to the
436 * interrupt controller that is the target of the acknowledge.
437 *
438 * Returns 0 for success, or an error code.
439 */
440static inline unsigned int ev_int_iack(unsigned int handle,
441 unsigned int *vector)
442{
443 register uintptr_t r11 __asm__("r11");
444 register uintptr_t r3 __asm__("r3");
445 register uintptr_t r4 __asm__("r4");
446
447 r11 = EV_HCALL_TOKEN(EV_INT_IACK);
448 r3 = handle;
449
450 __asm__ __volatile__ ("sc 1"
451 : "+r" (r11), "+r" (r3), "=r" (r4)
452 : : EV_HCALL_CLOBBERS2
453 );
454
455 *vector = r4;
456
457 return r3;
458}
459
460/**
461 * ev_doorbell_send - send a doorbell to another partition
462 * @handle: doorbell send handle
463 *
464 * Returns 0 for success, or an error code.
465 */
466static inline unsigned int ev_doorbell_send(unsigned int handle)
467{
468 register uintptr_t r11 __asm__("r11");
469 register uintptr_t r3 __asm__("r3");
470
471 r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND);
472 r3 = handle;
473
474 __asm__ __volatile__ ("sc 1"
475 : "+r" (r11), "+r" (r3)
476 : : EV_HCALL_CLOBBERS1
477 );
478
479 return r3;
480}
481
482/**
483 * ev_idle -- wait for next interrupt on this core
484 *
485 * Returns 0 for success, or an error code.
486 */
487static inline unsigned int ev_idle(void)
488{
489 register uintptr_t r11 __asm__("r11");
490 register uintptr_t r3 __asm__("r3");
491
492 r11 = EV_HCALL_TOKEN(EV_IDLE);
493
494 __asm__ __volatile__ ("sc 1"
495 : "+r" (r11), "=r" (r3)
496 : : EV_HCALL_CLOBBERS1
497 );
498
499 return r3;
500}
501
502#endif
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index 6d53f311d942..ac13addb8495 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -48,30 +48,33 @@
48#define EX_R14 (4 * 8) 48#define EX_R14 (4 * 8)
49#define EX_R15 (5 * 8) 49#define EX_R15 (5 * 8)
50 50
51/* The TLB miss exception uses different slots */ 51/*
52 * The TLB miss exception uses different slots.
53 *
54 * The bolted variant uses only the first six fields,
55 * which in combination with pgd and kernel_pgd fits in
56 * one 64-byte cache line.
57 */
52 58
53#define EX_TLB_R10 ( 0 * 8) 59#define EX_TLB_R10 ( 0 * 8)
54#define EX_TLB_R11 ( 1 * 8) 60#define EX_TLB_R11 ( 1 * 8)
55#define EX_TLB_R12 ( 2 * 8) 61#define EX_TLB_R14 ( 2 * 8)
56#define EX_TLB_R13 ( 3 * 8) 62#define EX_TLB_R15 ( 3 * 8)
57#define EX_TLB_R14 ( 4 * 8) 63#define EX_TLB_R16 ( 4 * 8)
58#define EX_TLB_R15 ( 5 * 8) 64#define EX_TLB_CR ( 5 * 8)
59#define EX_TLB_R16 ( 6 * 8) 65#define EX_TLB_R12 ( 6 * 8)
60#define EX_TLB_CR ( 7 * 8) 66#define EX_TLB_R13 ( 7 * 8)
61#define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */ 67#define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
62#define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */ 68#define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
63#define EX_TLB_SRR0 (10 * 8) 69#define EX_TLB_SRR0 (10 * 8)
64#define EX_TLB_SRR1 (11 * 8) 70#define EX_TLB_SRR1 (11 * 8)
65#define EX_TLB_MMUCR0 (12 * 8) /* Level 0 */
66#define EX_TLB_MAS1 (12 * 8) /* Level 0 */
67#define EX_TLB_MAS2 (13 * 8) /* Level 0 */
68#ifdef CONFIG_BOOK3E_MMU_TLB_STATS 71#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
69#define EX_TLB_R8 (14 * 8) 72#define EX_TLB_R8 (12 * 8)
70#define EX_TLB_R9 (15 * 8) 73#define EX_TLB_R9 (13 * 8)
71#define EX_TLB_LR (16 * 8) 74#define EX_TLB_LR (14 * 8)
72#define EX_TLB_SIZE (17 * 8) 75#define EX_TLB_SIZE (15 * 8)
73#else 76#else
74#define EX_TLB_SIZE (14 * 8) 77#define EX_TLB_SIZE (12 * 8)
75#endif 78#endif
76 79
77#define START_EXCEPTION(label) \ 80#define START_EXCEPTION(label) \
@@ -168,6 +171,16 @@ exc_##label##_book3e:
168 ld r9,EX_TLB_R9(r12); \ 171 ld r9,EX_TLB_R9(r12); \
169 ld r8,EX_TLB_R8(r12); \ 172 ld r8,EX_TLB_R8(r12); \
170 mtlr r16; 173 mtlr r16;
174#define TLB_MISS_PROLOG_STATS_BOLTED \
175 mflr r10; \
176 std r8,PACA_EXTLB+EX_TLB_R8(r13); \
177 std r9,PACA_EXTLB+EX_TLB_R9(r13); \
178 std r10,PACA_EXTLB+EX_TLB_LR(r13);
179#define TLB_MISS_RESTORE_STATS_BOLTED \
180 ld r16,PACA_EXTLB+EX_TLB_LR(r13); \
181 ld r9,PACA_EXTLB+EX_TLB_R9(r13); \
182 ld r8,PACA_EXTLB+EX_TLB_R8(r13); \
183 mtlr r16;
171#define TLB_MISS_STATS_D(name) \ 184#define TLB_MISS_STATS_D(name) \
172 addi r9,r13,MMSTAT_DSTATS+name; \ 185 addi r9,r13,MMSTAT_DSTATS+name; \
173 bl .tlb_stat_inc; 186 bl .tlb_stat_inc;
@@ -183,17 +196,20 @@ exc_##label##_book3e:
18361: addi r9,r13,MMSTAT_ISTATS+name; \ 19661: addi r9,r13,MMSTAT_ISTATS+name; \
18462: bl .tlb_stat_inc; 19762: bl .tlb_stat_inc;
185#define TLB_MISS_STATS_SAVE_INFO \ 198#define TLB_MISS_STATS_SAVE_INFO \
186 std r14,EX_TLB_ESR(r12); /* save ESR */ \ 199 std r14,EX_TLB_ESR(r12); /* save ESR */
187 200#define TLB_MISS_STATS_SAVE_INFO_BOLTED \
188 201 std r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
189#else 202#else
190#define TLB_MISS_PROLOG_STATS 203#define TLB_MISS_PROLOG_STATS
191#define TLB_MISS_RESTORE_STATS 204#define TLB_MISS_RESTORE_STATS
205#define TLB_MISS_PROLOG_STATS_BOLTED
206#define TLB_MISS_RESTORE_STATS_BOLTED
192#define TLB_MISS_STATS_D(name) 207#define TLB_MISS_STATS_D(name)
193#define TLB_MISS_STATS_I(name) 208#define TLB_MISS_STATS_I(name)
194#define TLB_MISS_STATS_X(name) 209#define TLB_MISS_STATS_X(name)
195#define TLB_MISS_STATS_Y(name) 210#define TLB_MISS_STATS_Y(name)
196#define TLB_MISS_STATS_SAVE_INFO 211#define TLB_MISS_STATS_SAVE_INFO
212#define TLB_MISS_STATS_SAVE_INFO_BOLTED
197#endif 213#endif
198 214
199#define SET_IVOR(vector_number, vector_offset) \ 215#define SET_IVOR(vector_number, vector_offset) \
diff --git a/arch/powerpc/include/asm/fsl_hcalls.h b/arch/powerpc/include/asm/fsl_hcalls.h
new file mode 100644
index 000000000000..922d9b5fe3d5
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_hcalls.h
@@ -0,0 +1,655 @@
1/*
2 * Freescale hypervisor call interface
3 *
4 * Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * Author: Timur Tabi <timur@freescale.com>
7 *
8 * This file is provided under a dual BSD/GPL license. When using or
9 * redistributing this file, you may do so under either license.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 * * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * * Neither the name of Freescale Semiconductor nor the
19 * names of its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") as published by the Free Software
25 * Foundation, either version 2 of that License or (at your option) any
26 * later version.
27 *
28 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
29 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
30 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
32 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef _FSL_HCALLS_H
41#define _FSL_HCALLS_H
42
43#include <linux/types.h>
44#include <linux/errno.h>
45#include <asm/byteorder.h>
46#include <asm/epapr_hcalls.h>
47
48#define FH_API_VERSION 1
49
50#define FH_ERR_GET_INFO 1
51#define FH_PARTITION_GET_DTPROP 2
52#define FH_PARTITION_SET_DTPROP 3
53#define FH_PARTITION_RESTART 4
54#define FH_PARTITION_GET_STATUS 5
55#define FH_PARTITION_START 6
56#define FH_PARTITION_STOP 7
57#define FH_PARTITION_MEMCPY 8
58#define FH_DMA_ENABLE 9
59#define FH_DMA_DISABLE 10
60#define FH_SEND_NMI 11
61#define FH_VMPIC_GET_MSIR 12
62#define FH_SYSTEM_RESET 13
63#define FH_GET_CORE_STATE 14
64#define FH_ENTER_NAP 15
65#define FH_EXIT_NAP 16
66#define FH_CLAIM_DEVICE 17
67#define FH_PARTITION_STOP_DMA 18
68
69/* vendor ID: Freescale Semiconductor */
70#define FH_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_FSL_VENDOR_ID, num)
71
72/*
73 * We use "uintptr_t" to define a register because it's guaranteed to be a
74 * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
75 * platform.
76 *
77 * All registers are either input/output or output only. Registers that are
78 * initialized before making the hypercall are input/output. All
79 * input/output registers are represented with "+r". Output-only registers
80 * are represented with "=r". Do not specify any unused registers. The
81 * clobber list will tell the compiler that the hypercall modifies those
82 * registers, which is good enough.
83 */
84
85/**
86 * fh_send_nmi - send NMI to virtual cpu(s).
87 * @vcpu_mask: send NMI to virtual cpu(s) specified by this mask.
88 *
89 * Returns 0 for success, or EINVAL for invalid vcpu_mask.
90 */
91static inline unsigned int fh_send_nmi(unsigned int vcpu_mask)
92{
93 register uintptr_t r11 __asm__("r11");
94 register uintptr_t r3 __asm__("r3");
95
96 r11 = FH_HCALL_TOKEN(FH_SEND_NMI);
97 r3 = vcpu_mask;
98
99 __asm__ __volatile__ ("sc 1"
100 : "+r" (r11), "+r" (r3)
101 : : EV_HCALL_CLOBBERS1
102 );
103
104 return r3;
105}
106
107/* Arbitrary limits to avoid excessive memory allocation in hypervisor */
108#define FH_DTPROP_MAX_PATHLEN 4096
109#define FH_DTPROP_MAX_PROPLEN 32768
110
111/**
112 * fh_partiton_get_dtprop - get a property from a guest device tree.
113 * @handle: handle of partition whose device tree is to be accessed
114 * @dtpath_addr: physical address of device tree path to access
115 * @propname_addr: physical address of name of property
116 * @propvalue_addr: physical address of property value buffer
117 * @propvalue_len: length of buffer on entry, length of property on return
118 *
119 * Returns zero on success, non-zero on error.
120 */
121static inline unsigned int fh_partition_get_dtprop(int handle,
122 uint64_t dtpath_addr,
123 uint64_t propname_addr,
124 uint64_t propvalue_addr,
125 uint32_t *propvalue_len)
126{
127 register uintptr_t r11 __asm__("r11");
128 register uintptr_t r3 __asm__("r3");
129 register uintptr_t r4 __asm__("r4");
130 register uintptr_t r5 __asm__("r5");
131 register uintptr_t r6 __asm__("r6");
132 register uintptr_t r7 __asm__("r7");
133 register uintptr_t r8 __asm__("r8");
134 register uintptr_t r9 __asm__("r9");
135 register uintptr_t r10 __asm__("r10");
136
137 r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_DTPROP);
138 r3 = handle;
139
140#ifdef CONFIG_PHYS_64BIT
141 r4 = dtpath_addr >> 32;
142 r6 = propname_addr >> 32;
143 r8 = propvalue_addr >> 32;
144#else
145 r4 = 0;
146 r6 = 0;
147 r8 = 0;
148#endif
149 r5 = (uint32_t)dtpath_addr;
150 r7 = (uint32_t)propname_addr;
151 r9 = (uint32_t)propvalue_addr;
152 r10 = *propvalue_len;
153
154 __asm__ __volatile__ ("sc 1"
155 : "+r" (r11),
156 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
157 "+r" (r8), "+r" (r9), "+r" (r10)
158 : : EV_HCALL_CLOBBERS8
159 );
160
161 *propvalue_len = r4;
162 return r3;
163}
164
165/**
166 * Set a property in a guest device tree.
167 * @handle: handle of partition whose device tree is to be accessed
168 * @dtpath_addr: physical address of device tree path to access
169 * @propname_addr: physical address of name of property
170 * @propvalue_addr: physical address of property value
171 * @propvalue_len: length of property
172 *
173 * Returns zero on success, non-zero on error.
174 */
175static inline unsigned int fh_partition_set_dtprop(int handle,
176 uint64_t dtpath_addr,
177 uint64_t propname_addr,
178 uint64_t propvalue_addr,
179 uint32_t propvalue_len)
180{
181 register uintptr_t r11 __asm__("r11");
182 register uintptr_t r3 __asm__("r3");
183 register uintptr_t r4 __asm__("r4");
184 register uintptr_t r6 __asm__("r6");
185 register uintptr_t r8 __asm__("r8");
186 register uintptr_t r5 __asm__("r5");
187 register uintptr_t r7 __asm__("r7");
188 register uintptr_t r9 __asm__("r9");
189 register uintptr_t r10 __asm__("r10");
190
191 r11 = FH_HCALL_TOKEN(FH_PARTITION_SET_DTPROP);
192 r3 = handle;
193
194#ifdef CONFIG_PHYS_64BIT
195 r4 = dtpath_addr >> 32;
196 r6 = propname_addr >> 32;
197 r8 = propvalue_addr >> 32;
198#else
199 r4 = 0;
200 r6 = 0;
201 r8 = 0;
202#endif
203 r5 = (uint32_t)dtpath_addr;
204 r7 = (uint32_t)propname_addr;
205 r9 = (uint32_t)propvalue_addr;
206 r10 = propvalue_len;
207
208 __asm__ __volatile__ ("sc 1"
209 : "+r" (r11),
210 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
211 "+r" (r8), "+r" (r9), "+r" (r10)
212 : : EV_HCALL_CLOBBERS8
213 );
214
215 return r3;
216}
217
218/**
219 * fh_partition_restart - reboot the current partition
220 * @partition: partition ID
221 *
222 * Returns an error code if reboot failed. Does not return if it succeeds.
223 */
224static inline unsigned int fh_partition_restart(unsigned int partition)
225{
226 register uintptr_t r11 __asm__("r11");
227 register uintptr_t r3 __asm__("r3");
228
229 r11 = FH_HCALL_TOKEN(FH_PARTITION_RESTART);
230 r3 = partition;
231
232 __asm__ __volatile__ ("sc 1"
233 : "+r" (r11), "+r" (r3)
234 : : EV_HCALL_CLOBBERS1
235 );
236
237 return r3;
238}
239
240#define FH_PARTITION_STOPPED 0
241#define FH_PARTITION_RUNNING 1
242#define FH_PARTITION_STARTING 2
243#define FH_PARTITION_STOPPING 3
244#define FH_PARTITION_PAUSING 4
245#define FH_PARTITION_PAUSED 5
246#define FH_PARTITION_RESUMING 6
247
248/**
249 * fh_partition_get_status - gets the status of a partition
250 * @partition: partition ID
251 * @status: returned status code
252 *
253 * Returns 0 for success, or an error code.
254 */
255static inline unsigned int fh_partition_get_status(unsigned int partition,
256 unsigned int *status)
257{
258 register uintptr_t r11 __asm__("r11");
259 register uintptr_t r3 __asm__("r3");
260 register uintptr_t r4 __asm__("r4");
261
262 r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_STATUS);
263 r3 = partition;
264
265 __asm__ __volatile__ ("sc 1"
266 : "+r" (r11), "+r" (r3), "=r" (r4)
267 : : EV_HCALL_CLOBBERS2
268 );
269
270 *status = r4;
271
272 return r3;
273}
274
275/**
276 * fh_partition_start - boots and starts execution of the specified partition
277 * @partition: partition ID
278 * @entry_point: guest physical address to start execution
279 *
280 * The hypervisor creates a 1-to-1 virtual/physical IMA mapping, so at boot
281 * time, guest physical address are the same as guest virtual addresses.
282 *
283 * Returns 0 for success, or an error code.
284 */
285static inline unsigned int fh_partition_start(unsigned int partition,
286 uint32_t entry_point, int load)
287{
288 register uintptr_t r11 __asm__("r11");
289 register uintptr_t r3 __asm__("r3");
290 register uintptr_t r4 __asm__("r4");
291 register uintptr_t r5 __asm__("r5");
292
293 r11 = FH_HCALL_TOKEN(FH_PARTITION_START);
294 r3 = partition;
295 r4 = entry_point;
296 r5 = load;
297
298 __asm__ __volatile__ ("sc 1"
299 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5)
300 : : EV_HCALL_CLOBBERS3
301 );
302
303 return r3;
304}
305
306/**
307 * fh_partition_stop - stops another partition
308 * @partition: partition ID
309 *
310 * Returns 0 for success, or an error code.
311 */
312static inline unsigned int fh_partition_stop(unsigned int partition)
313{
314 register uintptr_t r11 __asm__("r11");
315 register uintptr_t r3 __asm__("r3");
316
317 r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP);
318 r3 = partition;
319
320 __asm__ __volatile__ ("sc 1"
321 : "+r" (r11), "+r" (r3)
322 : : EV_HCALL_CLOBBERS1
323 );
324
325 return r3;
326}
327
328/**
329 * struct fh_sg_list: definition of the fh_partition_memcpy S/G list
330 * @source: guest physical address to copy from
331 * @target: guest physical address to copy to
332 * @size: number of bytes to copy
333 * @reserved: reserved, must be zero
334 *
335 * The scatter/gather list for fh_partition_memcpy() is an array of these
336 * structures. The array must be guest physically contiguous.
337 *
338 * This structure must be aligned on 32-byte boundary, so that no single
339 * strucuture can span two pages.
340 */
341struct fh_sg_list {
342 uint64_t source; /**< guest physical address to copy from */
343 uint64_t target; /**< guest physical address to copy to */
344 uint64_t size; /**< number of bytes to copy */
345 uint64_t reserved; /**< reserved, must be zero */
346} __attribute__ ((aligned(32)));
347
348/**
349 * fh_partition_memcpy - copies data from one guest to another
350 * @source: the ID of the partition to copy from
351 * @target: the ID of the partition to copy to
352 * @sg_list: guest physical address of an array of &fh_sg_list structures
353 * @count: the number of entries in @sg_list
354 *
355 * Returns 0 for success, or an error code.
356 */
357static inline unsigned int fh_partition_memcpy(unsigned int source,
358 unsigned int target, phys_addr_t sg_list, unsigned int count)
359{
360 register uintptr_t r11 __asm__("r11");
361 register uintptr_t r3 __asm__("r3");
362 register uintptr_t r4 __asm__("r4");
363 register uintptr_t r5 __asm__("r5");
364 register uintptr_t r6 __asm__("r6");
365 register uintptr_t r7 __asm__("r7");
366
367 r11 = FH_HCALL_TOKEN(FH_PARTITION_MEMCPY);
368 r3 = source;
369 r4 = target;
370 r5 = (uint32_t) sg_list;
371
372#ifdef CONFIG_PHYS_64BIT
373 r6 = sg_list >> 32;
374#else
375 r6 = 0;
376#endif
377 r7 = count;
378
379 __asm__ __volatile__ ("sc 1"
380 : "+r" (r11),
381 "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7)
382 : : EV_HCALL_CLOBBERS5
383 );
384
385 return r3;
386}
387
388/**
389 * fh_dma_enable - enable DMA for the specified device
390 * @liodn: the LIODN of the I/O device for which to enable DMA
391 *
392 * Returns 0 for success, or an error code.
393 */
394static inline unsigned int fh_dma_enable(unsigned int liodn)
395{
396 register uintptr_t r11 __asm__("r11");
397 register uintptr_t r3 __asm__("r3");
398
399 r11 = FH_HCALL_TOKEN(FH_DMA_ENABLE);
400 r3 = liodn;
401
402 __asm__ __volatile__ ("sc 1"
403 : "+r" (r11), "+r" (r3)
404 : : EV_HCALL_CLOBBERS1
405 );
406
407 return r3;
408}
409
410/**
411 * fh_dma_disable - disable DMA for the specified device
412 * @liodn: the LIODN of the I/O device for which to disable DMA
413 *
414 * Returns 0 for success, or an error code.
415 */
416static inline unsigned int fh_dma_disable(unsigned int liodn)
417{
418 register uintptr_t r11 __asm__("r11");
419 register uintptr_t r3 __asm__("r3");
420
421 r11 = FH_HCALL_TOKEN(FH_DMA_DISABLE);
422 r3 = liodn;
423
424 __asm__ __volatile__ ("sc 1"
425 : "+r" (r11), "+r" (r3)
426 : : EV_HCALL_CLOBBERS1
427 );
428
429 return r3;
430}
431
432
433/**
434 * fh_vmpic_get_msir - returns the MPIC-MSI register value
435 * @interrupt: the interrupt number
436 * @msir_val: returned MPIC-MSI register value
437 *
438 * Returns 0 for success, or an error code.
439 */
440static inline unsigned int fh_vmpic_get_msir(unsigned int interrupt,
441 unsigned int *msir_val)
442{
443 register uintptr_t r11 __asm__("r11");
444 register uintptr_t r3 __asm__("r3");
445 register uintptr_t r4 __asm__("r4");
446
447 r11 = FH_HCALL_TOKEN(FH_VMPIC_GET_MSIR);
448 r3 = interrupt;
449
450 __asm__ __volatile__ ("sc 1"
451 : "+r" (r11), "+r" (r3), "=r" (r4)
452 : : EV_HCALL_CLOBBERS2
453 );
454
455 *msir_val = r4;
456
457 return r3;
458}
459
460/**
461 * fh_system_reset - reset the system
462 *
463 * Returns 0 for success, or an error code.
464 */
465static inline unsigned int fh_system_reset(void)
466{
467 register uintptr_t r11 __asm__("r11");
468 register uintptr_t r3 __asm__("r3");
469
470 r11 = FH_HCALL_TOKEN(FH_SYSTEM_RESET);
471
472 __asm__ __volatile__ ("sc 1"
473 : "+r" (r11), "=r" (r3)
474 : : EV_HCALL_CLOBBERS1
475 );
476
477 return r3;
478}
479
480
481/**
482 * fh_err_get_info - get platform error information
483 * @queue id:
484 * 0 for guest error event queue
485 * 1 for global error event queue
486 *
487 * @pointer to store the platform error data:
488 * platform error data is returned in registers r4 - r11
489 *
490 * Returns 0 for success, or an error code.
491 */
492static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize,
493 uint32_t addr_hi, uint32_t addr_lo, int peek)
494{
495 register uintptr_t r11 __asm__("r11");
496 register uintptr_t r3 __asm__("r3");
497 register uintptr_t r4 __asm__("r4");
498 register uintptr_t r5 __asm__("r5");
499 register uintptr_t r6 __asm__("r6");
500 register uintptr_t r7 __asm__("r7");
501
502 r11 = FH_HCALL_TOKEN(FH_ERR_GET_INFO);
503 r3 = queue;
504 r4 = *bufsize;
505 r5 = addr_hi;
506 r6 = addr_lo;
507 r7 = peek;
508
509 __asm__ __volatile__ ("sc 1"
510 : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6),
511 "+r" (r7)
512 : : EV_HCALL_CLOBBERS5
513 );
514
515 *bufsize = r4;
516
517 return r3;
518}
519
520
521#define FH_VCPU_RUN 0
522#define FH_VCPU_IDLE 1
523#define FH_VCPU_NAP 2
524
525/**
526 * fh_get_core_state - get the state of a vcpu
527 *
528 * @handle: handle of partition containing the vcpu
529 * @vcpu: vcpu number within the partition
530 * @state:the current state of the vcpu, see FH_VCPU_*
531 *
532 * Returns 0 for success, or an error code.
533 */
534static inline unsigned int fh_get_core_state(unsigned int handle,
535 unsigned int vcpu, unsigned int *state)
536{
537 register uintptr_t r11 __asm__("r11");
538 register uintptr_t r3 __asm__("r3");
539 register uintptr_t r4 __asm__("r4");
540
541 r11 = FH_HCALL_TOKEN(FH_GET_CORE_STATE);
542 r3 = handle;
543 r4 = vcpu;
544
545 __asm__ __volatile__ ("sc 1"
546 : "+r" (r11), "+r" (r3), "+r" (r4)
547 : : EV_HCALL_CLOBBERS2
548 );
549
550 *state = r4;
551 return r3;
552}
553
554/**
555 * fh_enter_nap - enter nap on a vcpu
556 *
557 * Note that though the API supports entering nap on a vcpu other
558 * than the caller, this may not be implmented and may return EINVAL.
559 *
560 * @handle: handle of partition containing the vcpu
561 * @vcpu: vcpu number within the partition
562 *
563 * Returns 0 for success, or an error code.
564 */
565static inline unsigned int fh_enter_nap(unsigned int handle, unsigned int vcpu)
566{
567 register uintptr_t r11 __asm__("r11");
568 register uintptr_t r3 __asm__("r3");
569 register uintptr_t r4 __asm__("r4");
570
571 r11 = FH_HCALL_TOKEN(FH_ENTER_NAP);
572 r3 = handle;
573 r4 = vcpu;
574
575 __asm__ __volatile__ ("sc 1"
576 : "+r" (r11), "+r" (r3), "+r" (r4)
577 : : EV_HCALL_CLOBBERS2
578 );
579
580 return r3;
581}
582
583/**
584 * fh_exit_nap - exit nap on a vcpu
585 * @handle: handle of partition containing the vcpu
586 * @vcpu: vcpu number within the partition
587 *
588 * Returns 0 for success, or an error code.
589 */
590static inline unsigned int fh_exit_nap(unsigned int handle, unsigned int vcpu)
591{
592 register uintptr_t r11 __asm__("r11");
593 register uintptr_t r3 __asm__("r3");
594 register uintptr_t r4 __asm__("r4");
595
596 r11 = FH_HCALL_TOKEN(FH_EXIT_NAP);
597 r3 = handle;
598 r4 = vcpu;
599
600 __asm__ __volatile__ ("sc 1"
601 : "+r" (r11), "+r" (r3), "+r" (r4)
602 : : EV_HCALL_CLOBBERS2
603 );
604
605 return r3;
606}
607/**
608 * fh_claim_device - claim a "claimable" shared device
609 * @handle: fsl,hv-device-handle of node to claim
610 *
611 * Returns 0 for success, or an error code.
612 */
613static inline unsigned int fh_claim_device(unsigned int handle)
614{
615 register uintptr_t r11 __asm__("r11");
616 register uintptr_t r3 __asm__("r3");
617
618 r11 = FH_HCALL_TOKEN(FH_CLAIM_DEVICE);
619 r3 = handle;
620
621 __asm__ __volatile__ ("sc 1"
622 : "+r" (r11), "+r" (r3)
623 : : EV_HCALL_CLOBBERS1
624 );
625
626 return r3;
627}
628
629/**
630 * Run deferred DMA disabling on a partition's private devices
631 *
632 * This applies to devices which a partition owns either privately,
633 * or which are claimable and still actively owned by that partition,
634 * and which do not have the no-dma-disable property.
635 *
636 * @handle: partition (must be stopped) whose DMA is to be disabled
637 *
638 * Returns 0 for success, or an error code.
639 */
640static inline unsigned int fh_partition_stop_dma(unsigned int handle)
641{
642 register uintptr_t r11 __asm__("r11");
643 register uintptr_t r3 __asm__("r3");
644
645 r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP_DMA);
646 r3 = handle;
647
648 __asm__ __volatile__ ("sc 1"
649 : "+r" (r11), "+r" (r3)
650 : : EV_HCALL_CLOBBERS1
651 );
652
653 return r3;
654}
655#endif
diff --git a/arch/powerpc/include/asm/hvsi.h b/arch/powerpc/include/asm/hvsi.h
new file mode 100644
index 000000000000..d3f64f361814
--- /dev/null
+++ b/arch/powerpc/include/asm/hvsi.h
@@ -0,0 +1,94 @@
1#ifndef _HVSI_H
2#define _HVSI_H
3
4#define VS_DATA_PACKET_HEADER 0xff
5#define VS_CONTROL_PACKET_HEADER 0xfe
6#define VS_QUERY_PACKET_HEADER 0xfd
7#define VS_QUERY_RESPONSE_PACKET_HEADER 0xfc
8
9/* control verbs */
10#define VSV_SET_MODEM_CTL 1 /* to service processor only */
11#define VSV_MODEM_CTL_UPDATE 2 /* from service processor only */
12#define VSV_CLOSE_PROTOCOL 3
13
14/* query verbs */
15#define VSV_SEND_VERSION_NUMBER 1
16#define VSV_SEND_MODEM_CTL_STATUS 2
17
18/* yes, these masks are not consecutive. */
19#define HVSI_TSDTR 0x01
20#define HVSI_TSCD 0x20
21
22#define HVSI_MAX_OUTGOING_DATA 12
23#define HVSI_VERSION 1
24
25struct hvsi_header {
26 uint8_t type;
27 uint8_t len;
28 uint16_t seqno;
29} __attribute__((packed));
30
31struct hvsi_data {
32 struct hvsi_header hdr;
33 uint8_t data[HVSI_MAX_OUTGOING_DATA];
34} __attribute__((packed));
35
36struct hvsi_control {
37 struct hvsi_header hdr;
38 uint16_t verb;
39 /* optional depending on verb: */
40 uint32_t word;
41 uint32_t mask;
42} __attribute__((packed));
43
44struct hvsi_query {
45 struct hvsi_header hdr;
46 uint16_t verb;
47} __attribute__((packed));
48
49struct hvsi_query_response {
50 struct hvsi_header hdr;
51 uint16_t verb;
52 uint16_t query_seqno;
53 union {
54 uint8_t version;
55 uint32_t mctrl_word;
56 } u;
57} __attribute__((packed));
58
59/* hvsi lib struct definitions */
60#define HVSI_INBUF_SIZE 255
61struct tty_struct;
62struct hvsi_priv {
63 unsigned int inbuf_len; /* data in input buffer */
64 unsigned char inbuf[HVSI_INBUF_SIZE];
65 unsigned int inbuf_cur; /* Cursor in input buffer */
66 unsigned int inbuf_pktlen; /* packet lenght from cursor */
67 atomic_t seqno; /* packet sequence number */
68 unsigned int opened:1; /* driver opened */
69 unsigned int established:1; /* protocol established */
70 unsigned int is_console:1; /* used as a kernel console device */
71 unsigned int mctrl_update:1; /* modem control updated */
72 unsigned short mctrl; /* modem control */
73 struct tty_struct *tty; /* tty structure */
74 int (*get_chars)(uint32_t termno, char *buf, int count);
75 int (*put_chars)(uint32_t termno, const char *buf, int count);
76 uint32_t termno;
77};
78
79/* hvsi lib functions */
80struct hvc_struct;
81extern void hvsilib_init(struct hvsi_priv *pv,
82 int (*get_chars)(uint32_t termno, char *buf, int count),
83 int (*put_chars)(uint32_t termno, const char *buf,
84 int count),
85 int termno, int is_console);
86extern int hvsilib_open(struct hvsi_priv *pv, struct hvc_struct *hp);
87extern void hvsilib_close(struct hvsi_priv *pv, struct hvc_struct *hp);
88extern int hvsilib_read_mctrl(struct hvsi_priv *pv);
89extern int hvsilib_write_mctrl(struct hvsi_priv *pv, int dtr);
90extern void hvsilib_establish(struct hvsi_priv *pv);
91extern int hvsilib_get_chars(struct hvsi_priv *pv, char *buf, int count);
92extern int hvsilib_put_chars(struct hvsi_priv *pv, const char *buf, int count);
93
94#endif /* _HVSI_H */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index 1bff591f7f72..c57a28e52b64 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -330,5 +330,7 @@ extern int call_handle_irq(int irq, void *p1,
330 struct thread_info *tp, void *func); 330 struct thread_info *tp, void *func);
331extern void do_IRQ(struct pt_regs *regs); 331extern void do_IRQ(struct pt_regs *regs);
332 332
333int irq_choose_cpu(const struct cpumask *mask);
334
333#endif /* _ASM_IRQ_H */ 335#endif /* _ASM_IRQ_H */
334#endif /* __KERNEL__ */ 336#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/jump_label.h b/arch/powerpc/include/asm/jump_label.h
new file mode 100644
index 000000000000..1f780b95c0f0
--- /dev/null
+++ b/arch/powerpc/include/asm/jump_label.h
@@ -0,0 +1,47 @@
1#ifndef _ASM_POWERPC_JUMP_LABEL_H
2#define _ASM_POWERPC_JUMP_LABEL_H
3
4/*
5 * Copyright 2010 Michael Ellerman, IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/types.h>
14
15#include <asm/feature-fixups.h>
16
17#define JUMP_ENTRY_TYPE stringify_in_c(FTR_ENTRY_LONG)
18#define JUMP_LABEL_NOP_SIZE 4
19
20static __always_inline bool arch_static_branch(struct jump_label_key *key)
21{
22 asm goto("1:\n\t"
23 "nop\n\t"
24 ".pushsection __jump_table, \"aw\"\n\t"
25 ".align 4\n\t"
26 JUMP_ENTRY_TYPE "1b, %l[l_yes], %c0\n\t"
27 ".popsection \n\t"
28 : : "i" (key) : : l_yes);
29 return false;
30l_yes:
31 return true;
32}
33
34#ifdef CONFIG_PPC64
35typedef u64 jump_label_t;
36#else
37typedef u32 jump_label_t;
38#endif
39
40struct jump_entry {
41 jump_label_t code;
42 jump_label_t target;
43 jump_label_t key;
44 jump_label_t pad;
45};
46
47#endif /* _ASM_POWERPC_JUMP_LABEL_H */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 4138b21ae80a..698b30638681 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -115,14 +115,24 @@
115#ifndef __ASSEMBLY__ 115#ifndef __ASSEMBLY__
116#include <asm/cputable.h> 116#include <asm/cputable.h>
117 117
118#ifdef CONFIG_PPC_FSL_BOOK3E
119#include <asm/percpu.h>
120DECLARE_PER_CPU(int, next_tlbcam_idx);
121#endif
122
118static inline int mmu_has_feature(unsigned long feature) 123static inline int mmu_has_feature(unsigned long feature)
119{ 124{
120 return (cur_cpu_spec->mmu_features & feature); 125 return (cur_cpu_spec->mmu_features & feature);
121} 126}
122 127
128static inline void mmu_clear_feature(unsigned long feature)
129{
130 cur_cpu_spec->mmu_features &= ~feature;
131}
132
123extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 133extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
124 134
125/* MMU initialization (64-bit only fo now) */ 135/* MMU initialization */
126extern void early_init_mmu(void); 136extern void early_init_mmu(void);
127extern void early_init_mmu_secondary(void); 137extern void early_init_mmu_secondary(void);
128 138
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
index 89d2f99c1bf4..23cd6cc30bcf 100644
--- a/arch/powerpc/include/asm/pSeries_reconfig.h
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -17,7 +17,7 @@
17#ifdef CONFIG_PPC_PSERIES 17#ifdef CONFIG_PPC_PSERIES
18extern int pSeries_reconfig_notifier_register(struct notifier_block *); 18extern int pSeries_reconfig_notifier_register(struct notifier_block *);
19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *); 19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
20extern struct blocking_notifier_head pSeries_reconfig_chain; 20extern int pSeries_reconfig_notify(unsigned long action, void *p);
21/* Not the best place to put this, will be fixed when we move some 21/* Not the best place to put this, will be fixed when we move some
22 * of the rtas suspend-me stuff to pseries */ 22 * of the rtas suspend-me stuff to pseries */
23extern void pSeries_coalesce_init(void); 23extern void pSeries_coalesce_init(void);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index a6da12859959..516bfb3f47d9 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -103,11 +103,12 @@ struct paca_struct {
103#endif /* CONFIG_PPC_STD_MMU_64 */ 103#endif /* CONFIG_PPC_STD_MMU_64 */
104 104
105#ifdef CONFIG_PPC_BOOK3E 105#ifdef CONFIG_PPC_BOOK3E
106 pgd_t *pgd; /* Current PGD */
107 pgd_t *kernel_pgd; /* Kernel PGD */
108 u64 exgen[8] __attribute__((aligned(0x80))); 106 u64 exgen[8] __attribute__((aligned(0x80)));
107 /* Keep pgd in the same cacheline as the start of extlb */
108 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
109 pgd_t *kernel_pgd; /* Kernel PGD */
109 /* We can have up to 3 levels of reentrancy in the TLB miss handler */ 110 /* We can have up to 3 levels of reentrancy in the TLB miss handler */
110 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80))); 111 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
111 u64 exmc[8]; /* used for machine checks */ 112 u64 exmc[8]; /* used for machine checks */
112 u64 excrit[8]; /* used for crit interrupts */ 113 u64 excrit[8]; /* used for crit interrupts */
113 u64 exdbg[8]; /* used for debug interrupts */ 114 u64 exdbg[8]; /* used for debug interrupts */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 81576ee0cfb1..c4205616dfb5 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -357,7 +357,8 @@ void pgtable_cache_init(void);
357/* 357/*
358 * find_linux_pte returns the address of a linux pte for a given 358 * find_linux_pte returns the address of a linux pte for a given
359 * effective address and directory. If not found, it returns zero. 359 * effective address and directory. If not found, it returns zero.
360 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) 360 */
361static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
361{ 362{
362 pgd_t *pg; 363 pgd_t *pg;
363 pud_t *pu; 364 pud_t *pu;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index d50c2b6d9bc3..eb11a446720e 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -20,6 +20,7 @@
20 20
21#ifndef __ASSEMBLY__ 21#ifndef __ASSEMBLY__
22#include <linux/compiler.h> 22#include <linux/compiler.h>
23#include <linux/cache.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
24#include <asm/types.h> 25#include <asm/types.h>
25 26
@@ -156,6 +157,10 @@ struct thread_struct {
156#endif 157#endif
157 struct pt_regs *regs; /* Pointer to saved register state */ 158 struct pt_regs *regs; /* Pointer to saved register state */
158 mm_segment_t fs; /* for get_fs() validation */ 159 mm_segment_t fs; /* for get_fs() validation */
160#ifdef CONFIG_BOOKE
161 /* BookE base exception scratch space; align on cacheline */
162 unsigned long normsave[8] ____cacheline_aligned;
163#endif
159#ifdef CONFIG_PPC32 164#ifdef CONFIG_PPC32
160 void *pgdir; /* root of page-table tree */ 165 void *pgdir; /* root of page-table tree */
161#endif 166#endif
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index ddbe57ae8584..e8aaf6fce38b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -889,8 +889,8 @@
889#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 889#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
890#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 890#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
891#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 891#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
892#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R 892#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
893#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W 893#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
894#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 894#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
895#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 895#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
896#ifdef CONFIG_E200 896#ifdef CONFIG_E200
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index dae19342f0b9..186e0fb835bd 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -3,4 +3,8 @@
3 3
4#include <asm-generic/setup.h> 4#include <asm-generic/setup.h>
5 5
6#ifndef __ASSEMBLY__
7extern void ppc_printk_progress(char *s, unsigned short hex);
8#endif
9
6#endif /* _ASM_POWERPC_SETUP_H */ 10#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 11eb404b5606..15a70b7f638b 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -30,7 +30,7 @@
30#include <asm/percpu.h> 30#include <asm/percpu.h>
31 31
32extern int boot_cpuid; 32extern int boot_cpuid;
33extern int boot_cpu_count; 33extern int spinning_secondaries;
34 34
35extern void cpu_die(void); 35extern void cpu_die(void);
36 36
@@ -119,7 +119,6 @@ extern const char *smp_ipi_name[];
119/* for irq controllers with only a single ipi */ 119/* for irq controllers with only a single ipi */
120extern void smp_muxed_ipi_set_data(int cpu, unsigned long data); 120extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
121extern void smp_muxed_ipi_message_pass(int cpu, int msg); 121extern void smp_muxed_ipi_message_pass(int cpu, int msg);
122extern void smp_muxed_ipi_resend(void);
123extern irqreturn_t smp_ipi_demux(void); 122extern irqreturn_t smp_ipi_demux(void);
124 123
125void smp_init_iSeries(void); 124void smp_init_iSeries(void);
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 58580e94a2bb..93e05d1b34b2 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -40,6 +40,7 @@ extern void udbg_adb_init_early(void);
40 40
41extern void __init udbg_early_init(void); 41extern void __init udbg_early_init(void);
42extern void __init udbg_init_debug_lpar(void); 42extern void __init udbg_init_debug_lpar(void);
43extern void __init udbg_init_debug_lpar_hvsi(void);
43extern void __init udbg_init_pmac_realmode(void); 44extern void __init udbg_init_pmac_realmode(void);
44extern void __init udbg_init_maple_realmode(void); 45extern void __init udbg_init_maple_realmode(void);
45extern void __init udbg_init_pas_realmode(void); 46extern void __init udbg_init_pas_realmode(void);
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index e8b981897d44..ce4f7f179117 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
76obj-$(CONFIG_44x) += cpu_setup_44x.o 76obj-$(CONFIG_44x) += cpu_setup_44x.o
77obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o dbell.o 77obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o dbell.o
78obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o 78obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o
79obj-$(CONFIG_JUMP_LABEL) += jump_label.o
79 80
80extra-y := head_$(CONFIG_WORD_SIZE).o 81extra-y := head_$(CONFIG_WORD_SIZE).o
81extra-$(CONFIG_40x) := head_40x.o 82extra-$(CONFIG_40x) := head_40x.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 54b935f2f5de..5f078bc2063e 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -82,6 +82,9 @@ int main(void)
82 DEFINE(KSP, offsetof(struct thread_struct, ksp)); 82 DEFINE(KSP, offsetof(struct thread_struct, ksp));
83 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit)); 83 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
84 DEFINE(PT_REGS, offsetof(struct thread_struct, regs)); 84 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
85#ifdef CONFIG_BOOKE
86 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
87#endif
85 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode)); 88 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
86 DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0])); 89 DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0]));
87 DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr)); 90 DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr));
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 4e6ee944495a..cc6a9d5d69ab 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -242,12 +242,8 @@ static void crash_kexec_wait_realmode(int cpu)
242 242
243 while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) { 243 while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) {
244 barrier(); 244 barrier();
245 if (!cpu_possible(i)) { 245 if (!cpu_possible(i) || !cpu_online(i) || (msecs <= 0))
246 break; 246 break;
247 }
248 if (!cpu_online(i)) {
249 break;
250 }
251 msecs--; 247 msecs--;
252 mdelay(1); 248 mdelay(1);
253 } 249 }
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index d238c082c3c5..4f0959fbfbee 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -161,9 +161,7 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
161 161
162 if (ppc_md.dma_set_mask) 162 if (ppc_md.dma_set_mask)
163 return ppc_md.dma_set_mask(dev, dma_mask); 163 return ppc_md.dma_set_mask(dev, dma_mask);
164 if (unlikely(dma_ops == NULL)) 164 if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
165 return -EIO;
166 if (dma_ops->set_dma_mask != NULL)
167 return dma_ops->set_dma_mask(dev, dma_mask); 165 return dma_ops->set_dma_mask(dev, dma_mask);
168 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 166 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
169 return -EIO; 167 return -EIO;
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index d24d4400cc79..429983c06f91 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -120,6 +120,12 @@
120 std r14,PACA_EXMC+EX_R14(r13); \ 120 std r14,PACA_EXMC+EX_R14(r13); \
121 std r15,PACA_EXMC+EX_R15(r13) 121 std r15,PACA_EXMC+EX_R15(r13)
122 122
123#define PROLOG_ADDITION_DOORBELL_GEN \
124 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
125 cmpwi cr0,r11,0; /* yes -> go out of line */ \
126 beq masked_doorbell_book3e
127
128
123/* Core exception code for all exceptions except TLB misses. 129/* Core exception code for all exceptions except TLB misses.
124 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type 130 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
125 */ 131 */
@@ -522,7 +528,13 @@ kernel_dbg_exc:
522 MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE) 528 MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
523 529
524/* Doorbell interrupt */ 530/* Doorbell interrupt */
525 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE) 531 START_EXCEPTION(doorbell)
532 NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
533 EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
534 CHECK_NAPPING()
535 addi r3,r1,STACK_FRAME_OVERHEAD
536 bl .doorbell_exception
537 b .ret_from_except_lite
526 538
527/* Doorbell critical Interrupt */ 539/* Doorbell critical Interrupt */
528 START_EXCEPTION(doorbell_crit); 540 START_EXCEPTION(doorbell_crit);
@@ -545,8 +557,16 @@ kernel_dbg_exc:
545 * An interrupt came in while soft-disabled; clear EE in SRR1, 557 * An interrupt came in while soft-disabled; clear EE in SRR1,
546 * clear paca->hard_enabled and return. 558 * clear paca->hard_enabled and return.
547 */ 559 */
560masked_doorbell_book3e:
561 mtcr r10
562 /* Resend the doorbell to fire again when ints enabled */
563 mfspr r10,SPRN_PIR
564 PPC_MSGSND(r10)
565 b masked_interrupt_book3e_common
566
548masked_interrupt_book3e: 567masked_interrupt_book3e:
549 mtcr r10 568 mtcr r10
569masked_interrupt_book3e_common:
550 stb r11,PACAHARDIRQEN(r13) 570 stb r11,PACAHARDIRQEN(r13)
551 mfspr r10,SPRN_SRR1 571 mfspr r10,SPRN_SRR1
552 rldicl r11,r10,48,1 /* clear MSR_EE */ 572 rldicl r11,r10,48,1 /* clear MSR_EE */
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 5e12b741ba5f..f8e971ba94f5 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -93,6 +93,30 @@ _ENTRY(_start);
93 93
94 bl early_init 94 bl early_init
95 95
96#ifdef CONFIG_RELOCATABLE
97 /*
98 * r25 will contain RPN/ERPN for the start address of memory
99 *
100 * Add the difference between KERNELBASE and PAGE_OFFSET to the
101 * start of physical memory to get kernstart_addr.
102 */
103 lis r3,kernstart_addr@ha
104 la r3,kernstart_addr@l(r3)
105
106 lis r4,KERNELBASE@h
107 ori r4,r4,KERNELBASE@l
108 lis r5,PAGE_OFFSET@h
109 ori r5,r5,PAGE_OFFSET@l
110 subf r4,r5,r4
111
112 rlwinm r6,r25,0,28,31 /* ERPN */
113 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
114 add r7,r7,r4
115
116 stw r6,0(r3)
117 stw r7,4(r3)
118#endif
119
96/* 120/*
97 * Decide what sort of machine this is and initialize the MMU. 121 * Decide what sort of machine this is and initialize the MMU.
98 */ 122 */
@@ -1001,9 +1025,6 @@ clear_utlb_entry:
1001 lis r3,PAGE_OFFSET@h 1025 lis r3,PAGE_OFFSET@h
1002 ori r3,r3,PAGE_OFFSET@l 1026 ori r3,r3,PAGE_OFFSET@l
1003 1027
1004 /* Kernel is at the base of RAM */
1005 li r4, 0 /* Load the kernel physical address */
1006
1007 /* Load the kernel PID = 0 */ 1028 /* Load the kernel PID = 0 */
1008 li r0,0 1029 li r0,0
1009 mtspr SPRN_PID,r0 1030 mtspr SPRN_PID,r0
@@ -1013,9 +1034,8 @@ clear_utlb_entry:
1013 clrrwi r3,r3,12 /* Mask off the effective page number */ 1034 clrrwi r3,r3,12 /* Mask off the effective page number */
1014 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M 1035 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
1015 1036
1016 /* Word 1 */ 1037 /* Word 1 - use r25. RPN is the same as the original entry */
1017 clrrwi r4,r4,12 /* Mask off the real page number */ 1038
1018 /* ERPN is 0 for first 4GB page */
1019 /* Word 2 */ 1039 /* Word 2 */
1020 li r5,0 1040 li r5,0
1021 ori r5,r5,PPC47x_TLB2_S_RWX 1041 ori r5,r5,PPC47x_TLB2_S_RWX
@@ -1026,7 +1046,7 @@ clear_utlb_entry:
1026 /* We write to way 0 and bolted 0 */ 1046 /* We write to way 0 and bolted 0 */
1027 lis r0,0x8800 1047 lis r0,0x8800
1028 tlbwe r3,r0,0 1048 tlbwe r3,r0,0
1029 tlbwe r4,r0,1 1049 tlbwe r25,r0,1
1030 tlbwe r5,r0,2 1050 tlbwe r5,r0,2
1031 1051
1032/* 1052/*
@@ -1124,7 +1144,13 @@ head_start_common:
1124 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 1144 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1125 mtspr SPRN_IVPR,r4 1145 mtspr SPRN_IVPR,r4
1126 1146
1127 addis r22,r22,KERNELBASE@h 1147 /*
1148 * If the kernel was loaded at a non-zero 256 MB page, we need to
1149 * mask off the most significant 4 bits to get the relative address
1150 * from the start of physical memory
1151 */
1152 rlwinm r22,r22,0,4,31
1153 addis r22,r22,PAGE_OFFSET@h
1128 mtlr r22 1154 mtlr r22
1129 isync 1155 isync
1130 blr 1156 blr
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index ba504099844a..3564c49c683e 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -255,7 +255,7 @@ generic_secondary_common_init:
255 mtctr r23 255 mtctr r23
256 bctrl 256 bctrl
257 257
2583: LOAD_REG_ADDR(r3, boot_cpu_count) /* Decrement boot_cpu_count */ 2583: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
259 lwarx r4,0,r3 259 lwarx r4,0,r3
260 subi r4,r4,1 260 subi r4,r4,1
261 stwcx. r4,0,r3 261 stwcx. r4,0,r3
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index a0bf158c8b47..fc921bf62e15 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -20,33 +20,43 @@
20 addi reg,reg,val@l 20 addi reg,reg,val@l
21#endif 21#endif
22 22
23/*
24 * Macro used to get to thread save registers.
25 * Note that entries 0-3 are used for the prolog code, and the remaining
26 * entries are available for specific exception use in the event a handler
27 * requires more than 4 scratch registers.
28 */
29#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
30
23#define NORMAL_EXCEPTION_PROLOG \ 31#define NORMAL_EXCEPTION_PROLOG \
24 mtspr SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\ 32 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
25 mtspr SPRN_SPRG_WSCRATCH1,r11; \ 33 mfspr r10, SPRN_SPRG_THREAD; \
26 mtspr SPRN_SPRG_WSCRATCH2,r1; \ 34 stw r11, THREAD_NORMSAVE(0)(r10); \
27 mfcr r10; /* save CR in r10 for now */\ 35 stw r13, THREAD_NORMSAVE(2)(r10); \
36 mfcr r13; /* save CR in r13 for now */\
28 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ 37 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
29 andi. r11,r11,MSR_PR; \ 38 andi. r11,r11,MSR_PR; \
39 mr r11, r1; \
30 beq 1f; \ 40 beq 1f; \
31 mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 41 /* if from user, start at top of this thread's kernel stack */ \
32 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ 42 lwz r11, THREAD_INFO-THREAD(r10); \
33 ALLOC_STACK_FRAME(r1, THREAD_SIZE); \ 43 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
341: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ 441 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
35 mr r11,r1; \ 45 stw r13, _CCR(r11); /* save various registers */ \
36 stw r10,_CCR(r11); /* save various registers */\
37 stw r12,GPR12(r11); \ 46 stw r12,GPR12(r11); \
38 stw r9,GPR9(r11); \ 47 stw r9,GPR9(r11); \
39 mfspr r10,SPRN_SPRG_RSCRATCH0; \ 48 mfspr r13, SPRN_SPRG_RSCRATCH0; \
40 stw r10,GPR10(r11); \ 49 stw r13, GPR10(r11); \
41 mfspr r12,SPRN_SPRG_RSCRATCH1; \ 50 lwz r12, THREAD_NORMSAVE(0)(r10); \
42 stw r12,GPR11(r11); \ 51 stw r12,GPR11(r11); \
52 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
43 mflr r10; \ 53 mflr r10; \
44 stw r10,_LINK(r11); \ 54 stw r10,_LINK(r11); \
45 mfspr r10,SPRN_SPRG_RSCRATCH2; \
46 mfspr r12,SPRN_SRR0; \ 55 mfspr r12,SPRN_SRR0; \
47 stw r10,GPR1(r11); \ 56 stw r1, GPR1(r11); \
48 mfspr r9,SPRN_SRR1; \ 57 mfspr r9,SPRN_SRR1; \
49 stw r10,0(r11); \ 58 stw r1, 0(r11); \
59 mr r1, r11; \
50 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 60 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
51 stw r0,GPR0(r11); \ 61 stw r0,GPR0(r11); \
52 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \ 62 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index fe37dd0dfd17..50845924b7d9 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -346,11 +346,12 @@ interrupt_base:
346 /* Data TLB Error Interrupt */ 346 /* Data TLB Error Interrupt */
347 START_EXCEPTION(DataTLBError) 347 START_EXCEPTION(DataTLBError)
348 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 348 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
349 mtspr SPRN_SPRG_WSCRATCH1, r11 349 mfspr r10, SPRN_SPRG_THREAD
350 mtspr SPRN_SPRG_WSCRATCH2, r12 350 stw r11, THREAD_NORMSAVE(0)(r10)
351 mtspr SPRN_SPRG_WSCRATCH3, r13 351 stw r12, THREAD_NORMSAVE(1)(r10)
352 mfcr r11 352 stw r13, THREAD_NORMSAVE(2)(r10)
353 mtspr SPRN_SPRG_WSCRATCH4, r11 353 mfcr r13
354 stw r13, THREAD_NORMSAVE(3)(r10)
354 mfspr r10, SPRN_DEAR /* Get faulting address */ 355 mfspr r10, SPRN_DEAR /* Get faulting address */
355 356
356 /* If we are faulting a kernel address, we have to use the 357 /* If we are faulting a kernel address, we have to use the
@@ -416,11 +417,12 @@ interrupt_base:
416 /* The bailout. Restore registers to pre-exception conditions 417 /* The bailout. Restore registers to pre-exception conditions
417 * and call the heavyweights to help us out. 418 * and call the heavyweights to help us out.
418 */ 419 */
419 mfspr r11, SPRN_SPRG_RSCRATCH4 420 mfspr r10, SPRN_SPRG_THREAD
421 lwz r11, THREAD_NORMSAVE(3)(r10)
420 mtcr r11 422 mtcr r11
421 mfspr r13, SPRN_SPRG_RSCRATCH3 423 lwz r13, THREAD_NORMSAVE(2)(r10)
422 mfspr r12, SPRN_SPRG_RSCRATCH2 424 lwz r12, THREAD_NORMSAVE(1)(r10)
423 mfspr r11, SPRN_SPRG_RSCRATCH1 425 lwz r11, THREAD_NORMSAVE(0)(r10)
424 mfspr r10, SPRN_SPRG_RSCRATCH0 426 mfspr r10, SPRN_SPRG_RSCRATCH0
425 b DataStorage 427 b DataStorage
426 428
@@ -432,11 +434,12 @@ interrupt_base:
432 */ 434 */
433 START_EXCEPTION(InstructionTLBError) 435 START_EXCEPTION(InstructionTLBError)
434 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 436 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
435 mtspr SPRN_SPRG_WSCRATCH1, r11 437 mfspr r10, SPRN_SPRG_THREAD
436 mtspr SPRN_SPRG_WSCRATCH2, r12 438 stw r11, THREAD_NORMSAVE(0)(r10)
437 mtspr SPRN_SPRG_WSCRATCH3, r13 439 stw r12, THREAD_NORMSAVE(1)(r10)
438 mfcr r11 440 stw r13, THREAD_NORMSAVE(2)(r10)
439 mtspr SPRN_SPRG_WSCRATCH4, r11 441 mfcr r13
442 stw r13, THREAD_NORMSAVE(3)(r10)
440 mfspr r10, SPRN_SRR0 /* Get faulting address */ 443 mfspr r10, SPRN_SRR0 /* Get faulting address */
441 444
442 /* If we are faulting a kernel address, we have to use the 445 /* If we are faulting a kernel address, we have to use the
@@ -496,11 +499,12 @@ interrupt_base:
496 /* The bailout. Restore registers to pre-exception conditions 499 /* The bailout. Restore registers to pre-exception conditions
497 * and call the heavyweights to help us out. 500 * and call the heavyweights to help us out.
498 */ 501 */
499 mfspr r11, SPRN_SPRG_RSCRATCH4 502 mfspr r10, SPRN_SPRG_THREAD
503 lwz r11, THREAD_NORMSAVE(3)(r10)
500 mtcr r11 504 mtcr r11
501 mfspr r13, SPRN_SPRG_RSCRATCH3 505 lwz r13, THREAD_NORMSAVE(2)(r10)
502 mfspr r12, SPRN_SPRG_RSCRATCH2 506 lwz r12, THREAD_NORMSAVE(1)(r10)
503 mfspr r11, SPRN_SPRG_RSCRATCH1 507 lwz r11, THREAD_NORMSAVE(0)(r10)
504 mfspr r10, SPRN_SPRG_RSCRATCH0 508 mfspr r10, SPRN_SPRG_RSCRATCH0
505 b InstructionStorage 509 b InstructionStorage
506 510
@@ -621,11 +625,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
621 tlbwe 625 tlbwe
622 626
623 /* Done...restore registers and get out of here. */ 627 /* Done...restore registers and get out of here. */
624 mfspr r11, SPRN_SPRG_RSCRATCH4 628 mfspr r10, SPRN_SPRG_THREAD
629 lwz r11, THREAD_NORMSAVE(3)(r10)
625 mtcr r11 630 mtcr r11
626 mfspr r13, SPRN_SPRG_RSCRATCH3 631 lwz r13, THREAD_NORMSAVE(2)(r10)
627 mfspr r12, SPRN_SPRG_RSCRATCH2 632 lwz r12, THREAD_NORMSAVE(1)(r10)
628 mfspr r11, SPRN_SPRG_RSCRATCH1 633 lwz r11, THREAD_NORMSAVE(0)(r10)
629 mfspr r10, SPRN_SPRG_RSCRATCH0 634 mfspr r10, SPRN_SPRG_RSCRATCH0
630 rfi /* Force context change */ 635 rfi /* Force context change */
631 636
diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
index 47a1a983ff88..3e2b95c6ae67 100644
--- a/arch/powerpc/kernel/idle_e500.S
+++ b/arch/powerpc/kernel/idle_e500.S
@@ -26,6 +26,17 @@ _GLOBAL(e500_idle)
26 ori r4,r4,_TLF_NAPPING /* so when we take an exception */ 26 ori r4,r4,_TLF_NAPPING /* so when we take an exception */
27 stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */ 27 stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
28 28
29#ifdef CONFIG_E500MC
30 wrteei 1
311: wait
32
33 /*
34 * Guard against spurious wakeups (e.g. from a hypervisor) --
35 * any real interrupt will cause us to return to LR due to
36 * _TLF_NAPPING.
37 */
38 b 1b
39#else
29 /* Check if we can nap or doze, put HID0 mask in r3 */ 40 /* Check if we can nap or doze, put HID0 mask in r3 */
30 lis r3,0 41 lis r3,0
31BEGIN_FTR_SECTION 42BEGIN_FTR_SECTION
@@ -72,6 +83,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
72 mtmsr r7 83 mtmsr r7
73 isync 84 isync
742: b 2b 852: b 2b
86#endif /* !E500MC */
75 87
76/* 88/*
77 * Return from NAP/DOZE mode, restore some CPU specific registers, 89 * Return from NAP/DOZE mode, restore some CPU specific registers,
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5b428e308666..d281fb6f12f3 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -157,12 +157,6 @@ notrace void arch_local_irq_restore(unsigned long en)
157 if (get_hard_enabled()) 157 if (get_hard_enabled())
158 return; 158 return;
159 159
160#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
161 /* Check for pending doorbell interrupts and resend to ourself */
162 if (cpu_has_feature(CPU_FTR_DBELL))
163 smp_muxed_ipi_resend();
164#endif
165
166 /* 160 /*
167 * Need to hard-enable interrupts here. Since currently disabled, 161 * Need to hard-enable interrupts here. Since currently disabled,
168 * no need to take further asm precautions against preemption; but 162 * no need to take further asm precautions against preemption; but
@@ -457,11 +451,18 @@ static inline void do_softirq_onstack(void)
457 curtp = current_thread_info(); 451 curtp = current_thread_info();
458 irqtp = softirq_ctx[smp_processor_id()]; 452 irqtp = softirq_ctx[smp_processor_id()];
459 irqtp->task = curtp->task; 453 irqtp->task = curtp->task;
454 irqtp->flags = 0;
460 current->thread.ksp_limit = (unsigned long)irqtp + 455 current->thread.ksp_limit = (unsigned long)irqtp +
461 _ALIGN_UP(sizeof(struct thread_info), 16); 456 _ALIGN_UP(sizeof(struct thread_info), 16);
462 call_do_softirq(irqtp); 457 call_do_softirq(irqtp);
463 current->thread.ksp_limit = saved_sp_limit; 458 current->thread.ksp_limit = saved_sp_limit;
464 irqtp->task = NULL; 459 irqtp->task = NULL;
460
461 /* Set any flag that may have been set on the
462 * alternate stack
463 */
464 if (irqtp->flags)
465 set_bits(irqtp->flags, &curtp->flags);
465} 466}
466 467
467void do_softirq(void) 468void do_softirq(void)
@@ -750,7 +751,7 @@ unsigned int irq_create_mapping(struct irq_host *host,
750 if (irq_setup_virq(host, virq, hwirq)) 751 if (irq_setup_virq(host, virq, hwirq))
751 return NO_IRQ; 752 return NO_IRQ;
752 753
753 printk(KERN_DEBUG "irq: irq %lu on host %s mapped to virtual irq %u\n", 754 pr_debug("irq: irq %lu on host %s mapped to virtual irq %u\n",
754 hwirq, host->of_node ? host->of_node->full_name : "null", virq); 755 hwirq, host->of_node ? host->of_node->full_name : "null", virq);
755 756
756 return virq; 757 return virq;
@@ -882,6 +883,41 @@ unsigned int irq_find_mapping(struct irq_host *host,
882} 883}
883EXPORT_SYMBOL_GPL(irq_find_mapping); 884EXPORT_SYMBOL_GPL(irq_find_mapping);
884 885
886#ifdef CONFIG_SMP
887int irq_choose_cpu(const struct cpumask *mask)
888{
889 int cpuid;
890
891 if (cpumask_equal(mask, cpu_all_mask)) {
892 static int irq_rover;
893 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
894 unsigned long flags;
895
896 /* Round-robin distribution... */
897do_round_robin:
898 raw_spin_lock_irqsave(&irq_rover_lock, flags);
899
900 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
901 if (irq_rover >= nr_cpu_ids)
902 irq_rover = cpumask_first(cpu_online_mask);
903
904 cpuid = irq_rover;
905
906 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
907 } else {
908 cpuid = cpumask_first_and(mask, cpu_online_mask);
909 if (cpuid >= nr_cpu_ids)
910 goto do_round_robin;
911 }
912
913 return get_hard_smp_processor_id(cpuid);
914}
915#else
916int irq_choose_cpu(const struct cpumask *mask)
917{
918 return hard_smp_processor_id();
919}
920#endif
885 921
886unsigned int irq_radix_revmap_lookup(struct irq_host *host, 922unsigned int irq_radix_revmap_lookup(struct irq_host *host,
887 irq_hw_number_t hwirq) 923 irq_hw_number_t hwirq)
diff --git a/arch/powerpc/kernel/jump_label.c b/arch/powerpc/kernel/jump_label.c
new file mode 100644
index 000000000000..368d158d665d
--- /dev/null
+++ b/arch/powerpc/kernel/jump_label.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2010 Michael Ellerman, IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/kernel.h>
11#include <linux/jump_label.h>
12#include <asm/code-patching.h>
13
14void arch_jump_label_transform(struct jump_entry *entry,
15 enum jump_label_type type)
16{
17 u32 *addr = (u32 *)(unsigned long)entry->code;
18
19 if (type == JUMP_LABEL_ENABLE)
20 patch_branch(addr, entry->target, 0);
21 else
22 patch_instruction(addr, PPC_INST_NOP);
23}
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index e89df59cdc5a..616921ef1439 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -339,7 +339,7 @@ _GLOBAL(real_205_writeb)
339#endif /* CONFIG_PPC_PASEMI */ 339#endif /* CONFIG_PPC_PASEMI */
340 340
341 341
342#ifdef CONFIG_CPU_FREQ_PMAC64 342#if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
343/* 343/*
344 * SCOM access functions for 970 (FX only for now) 344 * SCOM access functions for 970 (FX only for now)
345 * 345 *
@@ -408,7 +408,7 @@ _GLOBAL(scom970_write)
408 /* restore interrupts */ 408 /* restore interrupts */
409 mtmsrd r5,1 409 mtmsrd r5,1
410 blr 410 blr
411#endif /* CONFIG_CPU_FREQ_PMAC64 */ 411#endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
412 412
413 413
414/* 414/*
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c
index 845a58478890..fe21b515ca44 100644
--- a/arch/powerpc/kernel/mpc7450-pmu.c
+++ b/arch/powerpc/kernel/mpc7450-pmu.c
@@ -410,7 +410,7 @@ struct power_pmu mpc7450_pmu = {
410 .cache_events = &mpc7450_cache_events, 410 .cache_events = &mpc7450_cache_events,
411}; 411};
412 412
413static int init_mpc7450_pmu(void) 413static int __init init_mpc7450_pmu(void)
414{ 414{
415 if (!cur_cpu_spec->oprofile_cpu_type || 415 if (!cur_cpu_spec->oprofile_cpu_type ||
416 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450")) 416 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 45ebb14c5c27..0187829c3382 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1731,3 +1731,21 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1731 if (mode == PCI_PROBE_NORMAL) 1731 if (mode == PCI_PROBE_NORMAL)
1732 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1732 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1733} 1733}
1734
1735static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1736{
1737 int i, class = dev->class >> 8;
1738
1739 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1740 class == PCI_CLASS_BRIDGE_OTHER) &&
1741 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1742 (dev->bus->parent == NULL)) {
1743 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1744 dev->resource[i].start = 0;
1745 dev->resource[i].end = 0;
1746 dev->resource[i].flags = 0;
1747 }
1748 }
1749}
1750DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1751DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index 86585508e9c1..e2f24badf787 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -51,25 +51,6 @@ struct pci_dev *isa_bridge_pcidev;
51EXPORT_SYMBOL_GPL(isa_bridge_pcidev); 51EXPORT_SYMBOL_GPL(isa_bridge_pcidev);
52 52
53static void 53static void
54fixup_hide_host_resource_fsl(struct pci_dev *dev)
55{
56 int i, class = dev->class >> 8;
57
58 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
59 class == PCI_CLASS_BRIDGE_OTHER) &&
60 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
61 (dev->bus->parent == NULL)) {
62 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
63 dev->resource[i].start = 0;
64 dev->resource[i].end = 0;
65 dev->resource[i].flags = 0;
66 }
67 }
68}
69DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
70DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
71
72static void
73fixup_cpc710_pci64(struct pci_dev* dev) 54fixup_cpc710_pci64(struct pci_dev* dev)
74{ 55{
75 /* Hide the PCI64 BARs from the kernel as their content doesn't 56 /* Hide the PCI64 BARs from the kernel as their content doesn't
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 14967de98876..10a140f82cb8 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1408,7 +1408,7 @@ power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu
1408 return NOTIFY_OK; 1408 return NOTIFY_OK;
1409} 1409}
1410 1410
1411int register_power_pmu(struct power_pmu *pmu) 1411int __cpuinit register_power_pmu(struct power_pmu *pmu)
1412{ 1412{
1413 if (ppmu) 1413 if (ppmu)
1414 return -EBUSY; /* something's already registered */ 1414 return -EBUSY; /* something's already registered */
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index e9dbc2d35c9c..b4f1dda4d089 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -609,7 +609,7 @@ static struct power_pmu power4_pmu = {
609 .cache_events = &power4_cache_events, 609 .cache_events = &power4_cache_events,
610}; 610};
611 611
612static int init_power4_pmu(void) 612static int __init init_power4_pmu(void)
613{ 613{
614 if (!cur_cpu_spec->oprofile_cpu_type || 614 if (!cur_cpu_spec->oprofile_cpu_type ||
615 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4")) 615 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4"))
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index f58a2bd41b59..a8757baa28f3 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -677,7 +677,7 @@ static struct power_pmu power5p_pmu = {
677 .cache_events = &power5p_cache_events, 677 .cache_events = &power5p_cache_events,
678}; 678};
679 679
680static int init_power5p_pmu(void) 680static int __init init_power5p_pmu(void)
681{ 681{
682 if (!cur_cpu_spec->oprofile_cpu_type || 682 if (!cur_cpu_spec->oprofile_cpu_type ||
683 (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+") 683 (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index b1acab684142..e7f06eb7a861 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -617,7 +617,7 @@ static struct power_pmu power5_pmu = {
617 .cache_events = &power5_cache_events, 617 .cache_events = &power5_cache_events,
618}; 618};
619 619
620static int init_power5_pmu(void) 620static int __init init_power5_pmu(void)
621{ 621{
622 if (!cur_cpu_spec->oprofile_cpu_type || 622 if (!cur_cpu_spec->oprofile_cpu_type ||
623 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5")) 623 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index b24a3a23d073..03b95e2c6d65 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -540,7 +540,7 @@ static struct power_pmu power6_pmu = {
540 .cache_events = &power6_cache_events, 540 .cache_events = &power6_cache_events,
541}; 541};
542 542
543static int init_power6_pmu(void) 543static int __init init_power6_pmu(void)
544{ 544{
545 if (!cur_cpu_spec->oprofile_cpu_type || 545 if (!cur_cpu_spec->oprofile_cpu_type ||
546 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6")) 546 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 6d9dccb2ea59..de83d6060dda 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -365,7 +365,7 @@ static struct power_pmu power7_pmu = {
365 .cache_events = &power7_cache_events, 365 .cache_events = &power7_cache_events,
366}; 366};
367 367
368static int init_power7_pmu(void) 368static int __init init_power7_pmu(void)
369{ 369{
370 if (!cur_cpu_spec->oprofile_cpu_type || 370 if (!cur_cpu_spec->oprofile_cpu_type ||
371 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) 371 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index b121de9658eb..8c2190206964 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -489,7 +489,7 @@ static struct power_pmu ppc970_pmu = {
489 .cache_events = &ppc970_cache_events, 489 .cache_events = &ppc970_cache_events,
490}; 490};
491 491
492static int init_ppc970_pmu(void) 492static int __init init_ppc970_pmu(void)
493{ 493{
494 if (!cur_cpu_spec->oprofile_cpu_type || 494 if (!cur_cpu_spec->oprofile_cpu_type ||
495 (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970") 495 (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index ec2d0edeb134..8f53954e75a3 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -654,6 +654,8 @@ void show_regs(struct pt_regs * regs)
654 printbits(regs->msr, msr_bits); 654 printbits(regs->msr, msr_bits);
655 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); 655 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
656 trap = TRAP(regs); 656 trap = TRAP(regs);
657 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
658 printk("CFAR: "REG"\n", regs->orig_gpr3);
657 if (trap == 0x300 || trap == 0x600) 659 if (trap == 0x300 || trap == 0x600)
658#ifdef CONFIG_PPC_ADV_DEBUG_REGS 660#ifdef CONFIG_PPC_ADV_DEBUG_REGS
659 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); 661 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
@@ -835,8 +837,6 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
835 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ 837 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
836#endif 838#endif
837 839
838 set_fs(USER_DS);
839
840 /* 840 /*
841 * If we exec out of a kernel thread then thread.regs will not be 841 * If we exec out of a kernel thread then thread.regs will not be
842 * set. Do it now. 842 * set. Do it now.
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 8c3112a57cf2..174e1e96175e 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -69,6 +69,7 @@ unsigned long tce_alloc_start, tce_alloc_end;
69u64 ppc64_rma_size; 69u64 ppc64_rma_size;
70#endif 70#endif
71static phys_addr_t first_memblock_size; 71static phys_addr_t first_memblock_size;
72static int __initdata boot_cpu_count;
72 73
73static int __init early_parse_mem(char *p) 74static int __init early_parse_mem(char *p)
74{ 75{
@@ -769,6 +770,13 @@ void __init early_init_devtree(void *params)
769 */ 770 */
770 of_scan_flat_dt(early_init_dt_scan_cpus, NULL); 771 of_scan_flat_dt(early_init_dt_scan_cpus, NULL);
771 772
773#if defined(CONFIG_SMP) && defined(CONFIG_PPC64)
774 /* We'll later wait for secondaries to check in; there are
775 * NCPUS-1 non-boot CPUs :-)
776 */
777 spinning_secondaries = boot_cpu_count - 1;
778#endif
779
772 DBG(" <- early_init_devtree()\n"); 780 DBG(" <- early_init_devtree()\n");
773} 781}
774 782
@@ -862,16 +870,14 @@ static int prom_reconfig_notifier(struct notifier_block *nb,
862 switch (action) { 870 switch (action) {
863 case PSERIES_RECONFIG_ADD: 871 case PSERIES_RECONFIG_ADD:
864 err = of_finish_dynamic_node(node); 872 err = of_finish_dynamic_node(node);
865 if (err < 0) { 873 if (err < 0)
866 printk(KERN_ERR "finish_node returned %d\n", err); 874 printk(KERN_ERR "finish_node returned %d\n", err);
867 err = NOTIFY_BAD;
868 }
869 break; 875 break;
870 default: 876 default:
871 err = NOTIFY_DONE; 877 err = 0;
872 break; 878 break;
873 } 879 }
874 return err; 880 return notifier_from_errno(err);
875} 881}
876 882
877static struct notifier_block prom_reconfig_nb = { 883static struct notifier_block prom_reconfig_nb = {
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 22051ef04bd9..b1d738d12890 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -707,29 +707,14 @@ static int powerpc_debugfs_init(void)
707arch_initcall(powerpc_debugfs_init); 707arch_initcall(powerpc_debugfs_init);
708#endif 708#endif
709 709
710static int ppc_dflt_bus_notify(struct notifier_block *nb, 710void ppc_printk_progress(char *s, unsigned short hex)
711 unsigned long action, void *data)
712{ 711{
713 struct device *dev = data; 712 pr_info("%s\n", s);
714
715 /* We are only intereted in device addition */
716 if (action != BUS_NOTIFY_ADD_DEVICE)
717 return 0;
718
719 set_dma_ops(dev, &dma_direct_ops);
720
721 return NOTIFY_DONE;
722} 713}
723 714
724static struct notifier_block ppc_dflt_plat_bus_notifier = { 715void arch_setup_pdev_archdata(struct platform_device *pdev)
725 .notifier_call = ppc_dflt_bus_notify,
726 .priority = INT_MAX,
727};
728
729static int __init setup_bus_notifier(void)
730{ 716{
731 bus_register_notifier(&platform_bus_type, &ppc_dflt_plat_bus_notifier); 717 pdev->archdata.dma_mask = DMA_BIT_MASK(32);
732 return 0; 718 pdev->dev.dma_mask = &pdev->archdata.dma_mask;
719 set_dma_ops(&pdev->dev, &dma_direct_ops);
733} 720}
734
735arch_initcall(setup_bus_notifier);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 620d792b52e4..209135af0a40 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -48,8 +48,8 @@ extern void bootx_init(unsigned long r4, unsigned long phys);
48 48
49int boot_cpuid = -1; 49int boot_cpuid = -1;
50EXPORT_SYMBOL_GPL(boot_cpuid); 50EXPORT_SYMBOL_GPL(boot_cpuid);
51int __initdata boot_cpu_count;
52int boot_cpuid_phys; 51int boot_cpuid_phys;
52EXPORT_SYMBOL_GPL(boot_cpuid_phys);
53 53
54int smp_hw_index[NR_CPUS]; 54int smp_hw_index[NR_CPUS];
55 55
@@ -127,6 +127,8 @@ notrace void __init machine_init(unsigned long dt_ptr)
127 /* Do some early initialization based on the flat device tree */ 127 /* Do some early initialization based on the flat device tree */
128 early_init_devtree(__va(dt_ptr)); 128 early_init_devtree(__va(dt_ptr));
129 129
130 early_init_mmu();
131
130 probe_machine(); 132 probe_machine();
131 133
132 setup_kdump_trampoline(); 134 setup_kdump_trampoline();
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 532054f24ecb..aebef1320ed7 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -74,7 +74,7 @@
74#endif 74#endif
75 75
76int boot_cpuid = 0; 76int boot_cpuid = 0;
77int __initdata boot_cpu_count; 77int __initdata spinning_secondaries;
78u64 ppc64_pft_size; 78u64 ppc64_pft_size;
79 79
80/* Pick defaults since we might want to patch instructions 80/* Pick defaults since we might want to patch instructions
@@ -254,11 +254,11 @@ void smp_release_cpus(void)
254 for (i = 0; i < 100000; i++) { 254 for (i = 0; i < 100000; i++) {
255 mb(); 255 mb();
256 HMT_low(); 256 HMT_low();
257 if (boot_cpu_count == 0) 257 if (spinning_secondaries == 0)
258 break; 258 break;
259 udelay(1); 259 udelay(1);
260 } 260 }
261 DBG("boot_cpu_count = %d\n", boot_cpu_count); 261 DBG("spinning_secondaries = %d\n", spinning_secondaries);
262 262
263 DBG(" <- smp_release_cpus()\n"); 263 DBG(" <- smp_release_cpus()\n");
264} 264}
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 09a85a9045d6..f932f8a0cf0c 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -202,14 +202,6 @@ void smp_muxed_ipi_message_pass(int cpu, int msg)
202 smp_ops->cause_ipi(cpu, info->data); 202 smp_ops->cause_ipi(cpu, info->data);
203} 203}
204 204
205void smp_muxed_ipi_resend(void)
206{
207 struct cpu_messages *info = &__get_cpu_var(ipi_message);
208
209 if (info->messages)
210 smp_ops->cause_ipi(smp_processor_id(), info->data);
211}
212
213irqreturn_t smp_ipi_demux(void) 205irqreturn_t smp_ipi_demux(void)
214{ 206{
215 struct cpu_messages *info = &__get_cpu_var(ipi_message); 207 struct cpu_messages *info = &__get_cpu_var(ipi_message);
@@ -238,16 +230,26 @@ irqreturn_t smp_ipi_demux(void)
238} 230}
239#endif /* CONFIG_PPC_SMP_MUXED_IPI */ 231#endif /* CONFIG_PPC_SMP_MUXED_IPI */
240 232
233static inline void do_message_pass(int cpu, int msg)
234{
235 if (smp_ops->message_pass)
236 smp_ops->message_pass(cpu, msg);
237#ifdef CONFIG_PPC_SMP_MUXED_IPI
238 else
239 smp_muxed_ipi_message_pass(cpu, msg);
240#endif
241}
242
241void smp_send_reschedule(int cpu) 243void smp_send_reschedule(int cpu)
242{ 244{
243 if (likely(smp_ops)) 245 if (likely(smp_ops))
244 smp_ops->message_pass(cpu, PPC_MSG_RESCHEDULE); 246 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
245} 247}
246EXPORT_SYMBOL_GPL(smp_send_reschedule); 248EXPORT_SYMBOL_GPL(smp_send_reschedule);
247 249
248void arch_send_call_function_single_ipi(int cpu) 250void arch_send_call_function_single_ipi(int cpu)
249{ 251{
250 smp_ops->message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE); 252 do_message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE);
251} 253}
252 254
253void arch_send_call_function_ipi_mask(const struct cpumask *mask) 255void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -255,7 +257,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
255 unsigned int cpu; 257 unsigned int cpu;
256 258
257 for_each_cpu(cpu, mask) 259 for_each_cpu(cpu, mask)
258 smp_ops->message_pass(cpu, PPC_MSG_CALL_FUNCTION); 260 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
259} 261}
260 262
261#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 263#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
@@ -269,7 +271,7 @@ void smp_send_debugger_break(void)
269 271
270 for_each_online_cpu(cpu) 272 for_each_online_cpu(cpu)
271 if (cpu != me) 273 if (cpu != me)
272 smp_ops->message_pass(cpu, PPC_MSG_DEBUGGER_BREAK); 274 do_message_pass(cpu, PPC_MSG_DEBUGGER_BREAK);
273} 275}
274#endif 276#endif
275 277
@@ -304,6 +306,10 @@ struct thread_info *current_set[NR_CPUS];
304static void __devinit smp_store_cpu_info(int id) 306static void __devinit smp_store_cpu_info(int id)
305{ 307{
306 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); 308 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
309#ifdef CONFIG_PPC_FSL_BOOK3E
310 per_cpu(next_tlbcam_idx, id)
311 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
312#endif
307} 313}
308 314
309void __init smp_prepare_cpus(unsigned int max_cpus) 315void __init smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index 23d65abbedce..faa82c1f3f68 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -31,6 +31,9 @@ void __init udbg_early_init(void)
31#if defined(CONFIG_PPC_EARLY_DEBUG_LPAR) 31#if defined(CONFIG_PPC_EARLY_DEBUG_LPAR)
32 /* For LPAR machines that have an HVC console on vterm 0 */ 32 /* For LPAR machines that have an HVC console on vterm 0 */
33 udbg_init_debug_lpar(); 33 udbg_init_debug_lpar();
34#elif defined(CONFIG_PPC_EARLY_DEBUG_LPAR_HVSI)
35 /* For LPAR machines that have an HVSI console on vterm 0 */
36 udbg_init_debug_lpar_hvsi();
34#elif defined(CONFIG_PPC_EARLY_DEBUG_G5) 37#elif defined(CONFIG_PPC_EARLY_DEBUG_G5)
35 /* For use on Apple G5 machines */ 38 /* For use on Apple G5 machines */
36 udbg_init_pmac_realmode(); 39 udbg_init_pmac_realmode();
@@ -68,6 +71,8 @@ void __init udbg_early_init(void)
68 71
69#ifdef CONFIG_PPC_EARLY_DEBUG 72#ifdef CONFIG_PPC_EARLY_DEBUG
70 console_loglevel = 10; 73 console_loglevel = 10;
74
75 register_early_udbg_console();
71#endif 76#endif
72} 77}
73 78
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 024acab588fd..f60e006d90c3 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -186,10 +186,11 @@ void __init MMU_init_hw(void)
186unsigned long __init mmu_mapin_ram(unsigned long top) 186unsigned long __init mmu_mapin_ram(unsigned long top)
187{ 187{
188 unsigned long addr; 188 unsigned long addr;
189 unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
189 190
190 /* Pin in enough TLBs to cover any lowmem not covered by the 191 /* Pin in enough TLBs to cover any lowmem not covered by the
191 * initial 256M mapping established in head_44x.S */ 192 * initial 256M mapping established in head_44x.S */
192 for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr; 193 for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
193 addr += PPC_PIN_SIZE) { 194 addr += PPC_PIN_SIZE) {
194 if (mmu_has_feature(MMU_FTR_TYPE_47x)) 195 if (mmu_has_feature(MMU_FTR_TYPE_47x))
195 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr); 196 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
@@ -218,19 +219,25 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
218void setup_initial_memory_limit(phys_addr_t first_memblock_base, 219void setup_initial_memory_limit(phys_addr_t first_memblock_base,
219 phys_addr_t first_memblock_size) 220 phys_addr_t first_memblock_size)
220{ 221{
222 u64 size;
223
224#ifndef CONFIG_RELOCATABLE
221 /* We don't currently support the first MEMBLOCK not mapping 0 225 /* We don't currently support the first MEMBLOCK not mapping 0
222 * physical on those processors 226 * physical on those processors
223 */ 227 */
224 BUG_ON(first_memblock_base != 0); 228 BUG_ON(first_memblock_base != 0);
229#endif
225 230
226 /* 44x has a 256M TLB entry pinned at boot */ 231 /* 44x has a 256M TLB entry pinned at boot */
227 memblock_set_current_limit(min_t(u64, first_memblock_size, PPC_PIN_SIZE)); 232 size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
233 memblock_set_current_limit(first_memblock_base + size);
228} 234}
229 235
230#ifdef CONFIG_SMP 236#ifdef CONFIG_SMP
231void __cpuinit mmu_init_secondary(int cpu) 237void __cpuinit mmu_init_secondary(int cpu)
232{ 238{
233 unsigned long addr; 239 unsigned long addr;
240 unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
234 241
235 /* Pin in enough TLBs to cover any lowmem not covered by the 242 /* Pin in enough TLBs to cover any lowmem not covered by the
236 * initial 256M mapping established in head_44x.S 243 * initial 256M mapping established in head_44x.S
@@ -241,7 +248,7 @@ void __cpuinit mmu_init_secondary(int cpu)
241 * stack. current (r2) isn't initialized, smp_processor_id() 248 * stack. current (r2) isn't initialized, smp_processor_id()
242 * will not work, current thread info isn't accessible, ... 249 * will not work, current thread info isn't accessible, ...
243 */ 250 */
244 for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr; 251 for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
245 addr += PPC_PIN_SIZE) { 252 addr += PPC_PIN_SIZE) {
246 if (mmu_has_feature(MMU_FTR_TYPE_47x)) 253 if (mmu_has_feature(MMU_FTR_TYPE_47x))
247 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr); 254 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 5de0f254dbb5..c77fef56dad6 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -191,38 +191,6 @@ void __init *early_get_page(void)
191 return __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE)); 191 return __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
192} 192}
193 193
194/* Free up now-unused memory */
195static void free_sec(unsigned long start, unsigned long end, const char *name)
196{
197 unsigned long cnt = 0;
198
199 while (start < end) {
200 ClearPageReserved(virt_to_page(start));
201 init_page_count(virt_to_page(start));
202 free_page(start);
203 cnt++;
204 start += PAGE_SIZE;
205 }
206 if (cnt) {
207 printk(" %ldk %s", cnt << (PAGE_SHIFT - 10), name);
208 totalram_pages += cnt;
209 }
210}
211
212void free_initmem(void)
213{
214#define FREESEC(TYPE) \
215 free_sec((unsigned long)(&__ ## TYPE ## _begin), \
216 (unsigned long)(&__ ## TYPE ## _end), \
217 #TYPE);
218
219 printk ("Freeing unused kernel memory:");
220 FREESEC(init);
221 printk("\n");
222 ppc_md.progress = NULL;
223#undef FREESEC
224}
225
226#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */ 194#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */
227void setup_initial_memory_limit(phys_addr_t first_memblock_base, 195void setup_initial_memory_limit(phys_addr_t first_memblock_base,
228 phys_addr_t first_memblock_size) 196 phys_addr_t first_memblock_size)
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index f6dbb4c20e64..e94b57fb79a0 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -83,22 +83,6 @@ EXPORT_SYMBOL_GPL(memstart_addr);
83phys_addr_t kernstart_addr; 83phys_addr_t kernstart_addr;
84EXPORT_SYMBOL_GPL(kernstart_addr); 84EXPORT_SYMBOL_GPL(kernstart_addr);
85 85
86void free_initmem(void)
87{
88 unsigned long addr;
89
90 addr = (unsigned long)__init_begin;
91 for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
92 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
93 ClearPageReserved(virt_to_page(addr));
94 init_page_count(virt_to_page(addr));
95 free_page(addr);
96 totalram_pages++;
97 }
98 printk ("Freeing unused kernel memory: %luk freed\n",
99 ((unsigned long)__init_end - (unsigned long)__init_begin) >> 10);
100}
101
102static void pgd_ctor(void *addr) 86static void pgd_ctor(void *addr)
103{ 87{
104 memset(addr, 0, PGD_TABLE_SIZE); 88 memset(addr, 0, PGD_TABLE_SIZE);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 29d4dde65c45..c781bbcf7338 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -249,7 +249,7 @@ static int __init mark_nonram_nosave(void)
249 */ 249 */
250void __init paging_init(void) 250void __init paging_init(void)
251{ 251{
252 unsigned long total_ram = memblock_phys_mem_size(); 252 unsigned long long total_ram = memblock_phys_mem_size();
253 phys_addr_t top_of_ram = memblock_end_of_DRAM(); 253 phys_addr_t top_of_ram = memblock_end_of_DRAM();
254 unsigned long max_zone_pfns[MAX_NR_ZONES]; 254 unsigned long max_zone_pfns[MAX_NR_ZONES];
255 255
@@ -269,7 +269,7 @@ void __init paging_init(void)
269 kmap_prot = PAGE_KERNEL; 269 kmap_prot = PAGE_KERNEL;
270#endif /* CONFIG_HIGHMEM */ 270#endif /* CONFIG_HIGHMEM */
271 271
272 printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%lx\n", 272 printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
273 (unsigned long long)top_of_ram, total_ram); 273 (unsigned long long)top_of_ram, total_ram);
274 printk(KERN_DEBUG "Memory hole size: %ldMB\n", 274 printk(KERN_DEBUG "Memory hole size: %ldMB\n",
275 (long int)((top_of_ram - total_ram) >> 20)); 275 (long int)((top_of_ram - total_ram) >> 20));
@@ -337,8 +337,9 @@ void __init mem_init(void)
337 337
338 highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT; 338 highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
339 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) { 339 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
340 phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
340 struct page *page = pfn_to_page(pfn); 341 struct page *page = pfn_to_page(pfn);
341 if (memblock_is_reserved(pfn << PAGE_SHIFT)) 342 if (memblock_is_reserved(paddr))
342 continue; 343 continue;
343 ClearPageReserved(page); 344 ClearPageReserved(page);
344 init_page_count(page); 345 init_page_count(page);
@@ -352,6 +353,15 @@ void __init mem_init(void)
352 } 353 }
353#endif /* CONFIG_HIGHMEM */ 354#endif /* CONFIG_HIGHMEM */
354 355
356#if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
357 /*
358 * If smp is enabled, next_tlbcam_idx is initialized in the cpu up
359 * functions.... do it here for the non-smp case.
360 */
361 per_cpu(next_tlbcam_idx, smp_processor_id()) =
362 (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
363#endif
364
355 printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " 365 printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, "
356 "%luk reserved, %luk data, %luk bss, %luk init)\n", 366 "%luk reserved, %luk data, %luk bss, %luk init)\n",
357 nr_free_pages() << (PAGE_SHIFT-10), 367 nr_free_pages() << (PAGE_SHIFT-10),
@@ -382,6 +392,25 @@ void __init mem_init(void)
382 mem_init_done = 1; 392 mem_init_done = 1;
383} 393}
384 394
395void free_initmem(void)
396{
397 unsigned long addr;
398
399 ppc_md.progress = ppc_printk_progress;
400
401 addr = (unsigned long)__init_begin;
402 for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
403 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
404 ClearPageReserved(virt_to_page(addr));
405 init_page_count(virt_to_page(addr));
406 free_page(addr);
407 totalram_pages++;
408 }
409 pr_info("Freeing unused kernel memory: %luk freed\n",
410 ((unsigned long)__init_end -
411 (unsigned long)__init_begin) >> 10);
412}
413
385#ifdef CONFIG_BLK_DEV_INITRD 414#ifdef CONFIG_BLK_DEV_INITRD
386void __init free_initrd_mem(unsigned long start, unsigned long end) 415void __init free_initrd_mem(unsigned long start, unsigned long end)
387{ 416{
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 27b863c14941..9a445f64accd 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -177,3 +177,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
177 flush_range(vma->vm_mm, start, end); 177 flush_range(vma->vm_mm, start, end);
178} 178}
179EXPORT_SYMBOL(flush_tlb_range); 179EXPORT_SYMBOL(flush_tlb_range);
180
181void __init early_init_mmu(void)
182{
183}
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index af0892209417..4ebb34bc01d6 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -30,6 +30,212 @@
30#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE) 30#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
31#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE) 31#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
32 32
33/**********************************************************************
34 * *
35 * TLB miss handling for Book3E with a bolted linear mapping *
36 * No virtual page table, no nested TLB misses *
37 * *
38 **********************************************************************/
39
40.macro tlb_prolog_bolted addr
41 mtspr SPRN_SPRG_TLB_SCRATCH,r13
42 mfspr r13,SPRN_SPRG_PACA
43 std r10,PACA_EXTLB+EX_TLB_R10(r13)
44 mfcr r10
45 std r11,PACA_EXTLB+EX_TLB_R11(r13)
46 std r16,PACA_EXTLB+EX_TLB_R16(r13)
47 mfspr r16,\addr /* get faulting address */
48 std r14,PACA_EXTLB+EX_TLB_R14(r13)
49 ld r14,PACAPGD(r13)
50 std r15,PACA_EXTLB+EX_TLB_R15(r13)
51 std r10,PACA_EXTLB+EX_TLB_CR(r13)
52 TLB_MISS_PROLOG_STATS_BOLTED
53.endm
54
55.macro tlb_epilog_bolted
56 ld r14,PACA_EXTLB+EX_TLB_CR(r13)
57 ld r10,PACA_EXTLB+EX_TLB_R10(r13)
58 ld r11,PACA_EXTLB+EX_TLB_R11(r13)
59 mtcr r14
60 ld r14,PACA_EXTLB+EX_TLB_R14(r13)
61 ld r15,PACA_EXTLB+EX_TLB_R15(r13)
62 TLB_MISS_RESTORE_STATS_BOLTED
63 ld r16,PACA_EXTLB+EX_TLB_R16(r13)
64 mfspr r13,SPRN_SPRG_TLB_SCRATCH
65.endm
66
67/* Data TLB miss */
68 START_EXCEPTION(data_tlb_miss_bolted)
69 tlb_prolog_bolted SPRN_DEAR
70
71 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
72
73 /* We do the user/kernel test for the PID here along with the RW test
74 */
75 /* We pre-test some combination of permissions to avoid double
76 * faults:
77 *
78 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
79 * ESR_ST is 0x00800000
80 * _PAGE_BAP_SW is 0x00000010
81 * So the shift is >> 19. This tests for supervisor writeability.
82 * If the page happens to be supervisor writeable and not user
83 * writeable, we will take a new fault later, but that should be
84 * a rare enough case.
85 *
86 * We also move ESR_ST in _PAGE_DIRTY position
87 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
88 *
89 * MAS1 is preset for all we need except for TID that needs to
90 * be cleared for kernel translations
91 */
92
93 mfspr r11,SPRN_ESR
94
95 srdi r15,r16,60 /* get region */
96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
97 bne- dtlb_miss_fault_bolted
98
99 rlwinm r10,r11,32-19,27,27
100 rlwimi r10,r11,32-16,19,19
101 cmpwi r15,0
102 ori r10,r10,_PAGE_PRESENT
103 oris r11,r10,_PAGE_ACCESSED@h
104
105 TLB_MISS_STATS_SAVE_INFO_BOLTED
106 bne tlb_miss_kernel_bolted
107
108tlb_miss_common_bolted:
109/*
110 * This is the guts of the TLB miss handler for bolted-linear.
111 * We are entered with:
112 *
113 * r16 = faulting address
114 * r15 = crap (free to use)
115 * r14 = page table base
116 * r13 = PACA
117 * r11 = PTE permission mask
118 * r10 = crap (free to use)
119 */
120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
121 cmpldi cr0,r14,0
122 clrrdi r15,r15,3
123 beq tlb_miss_fault_bolted
124
125BEGIN_MMU_FTR_SECTION
126 /* Set the TLB reservation and search for existing entry. Then load
127 * the entry.
128 */
129 PPC_TLBSRX_DOT(0,r16)
130 ldx r14,r14,r15
131 beq normal_tlb_miss_done
132MMU_FTR_SECTION_ELSE
133 ldx r14,r14,r15
134ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
135
136#ifndef CONFIG_PPC_64K_PAGES
137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
138 clrrdi r15,r15,3
139
140 cmpldi cr0,r14,0
141 beq tlb_miss_fault_bolted
142
143 ldx r14,r14,r15
144#endif /* CONFIG_PPC_64K_PAGES */
145
146 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
147 clrrdi r15,r15,3
148
149 cmpldi cr0,r14,0
150 beq tlb_miss_fault_bolted
151
152 ldx r14,r14,r15
153
154 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
155 clrrdi r15,r15,3
156
157 cmpldi cr0,r14,0
158 beq tlb_miss_fault_bolted
159
160 ldx r14,r14,r15
161
162 /* Check if required permissions are met */
163 andc. r15,r11,r14
164 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
165 bne- tlb_miss_fault_bolted
166
167 /* Now we build the MAS:
168 *
169 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
170 * MAS 1 : Almost fully setup
171 * - PID already updated by caller if necessary
172 * - TSIZE need change if !base page size, not
173 * yet implemented for now
174 * MAS 2 : Defaults not useful, need to be redone
175 * MAS 3+7 : Needs to be done
176 */
177 clrrdi r11,r16,12 /* Clear low crap in EA */
178 clrldi r15,r15,12 /* Clear crap at the top */
179 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
180 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
181 mtspr SPRN_MAS2,r11
182 andi. r11,r14,_PAGE_DIRTY
183 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
184
185 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
186 bne 1f
187 li r11,MAS3_SW|MAS3_UW
188 andc r15,r15,r11
1891:
190 mtspr SPRN_MAS7_MAS3,r15
191 tlbwe
192
193 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
194 tlb_epilog_bolted
195 rfi
196
197itlb_miss_kernel_bolted:
198 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
199 oris r11,r11,_PAGE_ACCESSED@h
200tlb_miss_kernel_bolted:
201 mfspr r10,SPRN_MAS1
202 ld r14,PACA_KERNELPGD(r13)
203 cmpldi cr0,r15,8 /* Check for vmalloc region */
204 rlwinm r10,r10,0,16,1 /* Clear TID */
205 mtspr SPRN_MAS1,r10
206 beq+ tlb_miss_common_bolted
207
208tlb_miss_fault_bolted:
209 /* We need to check if it was an instruction miss */
210 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
211 bne itlb_miss_fault_bolted
212dtlb_miss_fault_bolted:
213 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
214 tlb_epilog_bolted
215 b exc_data_storage_book3e
216itlb_miss_fault_bolted:
217 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
218 tlb_epilog_bolted
219 b exc_instruction_storage_book3e
220
221/* Instruction TLB miss */
222 START_EXCEPTION(instruction_tlb_miss_bolted)
223 tlb_prolog_bolted SPRN_SRR0
224
225 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
226 srdi r15,r16,60 /* get region */
227 TLB_MISS_STATS_SAVE_INFO_BOLTED
228 bne- itlb_miss_fault_bolted
229
230 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
231
232 /* We do the user/kernel test for the PID here along with the RW test
233 */
234
235 cmpldi cr0,r15,0 /* Check for user region */
236 oris r11,r11,_PAGE_ACCESSED@h
237 beq tlb_miss_common_bolted
238 b itlb_miss_kernel_bolted
33 239
34/********************************************************************** 240/**********************************************************************
35 * * 241 * *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 0bdad3aecc67..d32ec643c231 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -35,6 +35,7 @@
35#include <linux/preempt.h> 35#include <linux/preempt.h>
36#include <linux/spinlock.h> 36#include <linux/spinlock.h>
37#include <linux/memblock.h> 37#include <linux/memblock.h>
38#include <linux/of_fdt.h>
38 39
39#include <asm/tlbflush.h> 40#include <asm/tlbflush.h>
40#include <asm/tlb.h> 41#include <asm/tlb.h>
@@ -102,6 +103,12 @@ unsigned long linear_map_top; /* Top of linear mapping */
102 103
103#endif /* CONFIG_PPC64 */ 104#endif /* CONFIG_PPC64 */
104 105
106#ifdef CONFIG_PPC_FSL_BOOK3E
107/* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
108DEFINE_PER_CPU(int, next_tlbcam_idx);
109EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
110#endif
111
105/* 112/*
106 * Base TLB flushing operations: 113 * Base TLB flushing operations:
107 * 114 *
@@ -266,6 +273,17 @@ EXPORT_SYMBOL(flush_tlb_page);
266 273
267#endif /* CONFIG_SMP */ 274#endif /* CONFIG_SMP */
268 275
276#ifdef CONFIG_PPC_47x
277void __init early_init_mmu_47x(void)
278{
279#ifdef CONFIG_SMP
280 unsigned long root = of_get_flat_dt_root();
281 if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
282 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
283#endif /* CONFIG_SMP */
284}
285#endif /* CONFIG_PPC_47x */
286
269/* 287/*
270 * Flush kernel TLB entries in the given range 288 * Flush kernel TLB entries in the given range
271 */ 289 */
@@ -443,14 +461,27 @@ static void setup_page_sizes(void)
443 } 461 }
444} 462}
445 463
446static void setup_mmu_htw(void) 464static void __patch_exception(int exc, unsigned long addr)
447{ 465{
448 extern unsigned int interrupt_base_book3e; 466 extern unsigned int interrupt_base_book3e;
449 extern unsigned int exc_data_tlb_miss_htw_book3e; 467 unsigned int *ibase = &interrupt_base_book3e;
450 extern unsigned int exc_instruction_tlb_miss_htw_book3e; 468
469 /* Our exceptions vectors start with a NOP and -then- a branch
470 * to deal with single stepping from userspace which stops on
471 * the second instruction. Thus we need to patch the second
472 * instruction of the exception, not the first one
473 */
451 474
452 unsigned int *ibase = &interrupt_base_book3e; 475 patch_branch(ibase + (exc / 4) + 1, addr, 0);
476}
477
478#define patch_exception(exc, name) do { \
479 extern unsigned int name; \
480 __patch_exception((exc), (unsigned long)&name); \
481} while (0)
453 482
483static void setup_mmu_htw(void)
484{
454 /* Check if HW tablewalk is present, and if yes, enable it by: 485 /* Check if HW tablewalk is present, and if yes, enable it by:
455 * 486 *
456 * - patching the TLB miss handlers to branch to the 487 * - patching the TLB miss handlers to branch to the
@@ -462,19 +493,12 @@ static void setup_mmu_htw(void)
462 493
463 if ((tlb0cfg & TLBnCFG_IND) && 494 if ((tlb0cfg & TLBnCFG_IND) &&
464 (tlb0cfg & TLBnCFG_PT)) { 495 (tlb0cfg & TLBnCFG_PT)) {
465 /* Our exceptions vectors start with a NOP and -then- a branch 496 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
466 * to deal with single stepping from userspace which stops on 497 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
467 * the second instruction. Thus we need to patch the second
468 * instruction of the exception, not the first one
469 */
470 patch_branch(ibase + (0x1c0 / 4) + 1,
471 (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
472 patch_branch(ibase + (0x1e0 / 4) + 1,
473 (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
474 book3e_htw_enabled = 1; 498 book3e_htw_enabled = 1;
475 } 499 }
476 pr_info("MMU: Book3E Page Tables %s\n", 500 pr_info("MMU: Book3E HW tablewalk %s\n",
477 book3e_htw_enabled ? "Enabled" : "Disabled"); 501 book3e_htw_enabled ? "enabled" : "not supported");
478} 502}
479 503
480/* 504/*
@@ -549,6 +573,9 @@ static void __early_init_mmu(int boot_cpu)
549 /* limit memory so we dont have linear faults */ 573 /* limit memory so we dont have linear faults */
550 memblock_enforce_memory_limit(linear_map_top); 574 memblock_enforce_memory_limit(linear_map_top);
551 memblock_analyze(); 575 memblock_analyze();
576
577 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
578 patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
552 } 579 }
553#endif 580#endif
554 581
@@ -584,4 +611,11 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
584 /* Finally limit subsequent allocations */ 611 /* Finally limit subsequent allocations */
585 memblock_set_current_limit(first_memblock_base + ppc64_rma_size); 612 memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
586} 613}
614#else /* ! CONFIG_PPC64 */
615void __init early_init_mmu(void)
616{
617#ifdef CONFIG_PPC_47x
618 early_init_mmu_47x();
619#endif
620}
587#endif /* CONFIG_PPC64 */ 621#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index b6976e1726e4..498534cd5265 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -67,6 +67,16 @@ config MPC85xx_RDB
67 help 67 help
68 This option enables support for the MPC85xx RDB (P2020 RDB) board 68 This option enables support for the MPC85xx RDB (P2020 RDB) board
69 69
70config P1010_RDB
71 bool "Freescale P1010RDB"
72 select DEFAULT_UIMAGE
73 help
74 This option enables support for the MPC85xx RDB (P1010 RDB) board
75
76 P1010RDB contains P1010Si, which provides CPU performance up to 800
77 MHz and 1600 DMIPS, additional functionality and faster interfaces
78 (DDR3/3L, SATA II, and PCI Express).
79
70config P1022_DS 80config P1022_DS
71 bool "Freescale P1022 DS" 81 bool "Freescale P1022 DS"
72 select DEFAULT_UIMAGE 82 select DEFAULT_UIMAGE
@@ -75,6 +85,12 @@ config P1022_DS
75 help 85 help
76 This option enables support for the Freescale P1022DS reference board. 86 This option enables support for the Freescale P1022DS reference board.
77 87
88config P1023_RDS
89 bool "Freescale P1023 RDS"
90 select DEFAULT_UIMAGE
91 help
92 This option enables support for the P1023 RDS board
93
78config SOCRATES 94config SOCRATES
79 bool "Socrates" 95 bool "Socrates"
80 select DEFAULT_UIMAGE 96 select DEFAULT_UIMAGE
@@ -155,6 +171,18 @@ config SBC8560
155 help 171 help
156 This option enables support for the Wind River SBC8560 board 172 This option enables support for the Wind River SBC8560 board
157 173
174config P2040_RDB
175 bool "Freescale P2040 RDB"
176 select DEFAULT_UIMAGE
177 select PPC_E500MC
178 select PHYS_64BIT
179 select SWIOTLB
180 select MPC8xxx_GPIO
181 select HAS_RAPIDIO
182 select PPC_EPAPR_HV_PIC
183 help
184 This option enables support for the P2040 RDB board
185
158config P3041_DS 186config P3041_DS
159 bool "Freescale P3041 DS" 187 bool "Freescale P3041 DS"
160 select DEFAULT_UIMAGE 188 select DEFAULT_UIMAGE
@@ -163,6 +191,7 @@ config P3041_DS
163 select SWIOTLB 191 select SWIOTLB
164 select MPC8xxx_GPIO 192 select MPC8xxx_GPIO
165 select HAS_RAPIDIO 193 select HAS_RAPIDIO
194 select PPC_EPAPR_HV_PIC
166 help 195 help
167 This option enables support for the P3041 DS board 196 This option enables support for the P3041 DS board
168 197
@@ -174,6 +203,7 @@ config P4080_DS
174 select SWIOTLB 203 select SWIOTLB
175 select MPC8xxx_GPIO 204 select MPC8xxx_GPIO
176 select HAS_RAPIDIO 205 select HAS_RAPIDIO
206 select PPC_EPAPR_HV_PIC
177 help 207 help
178 This option enables support for the P4080 DS board 208 This option enables support for the P4080 DS board
179 209
@@ -188,6 +218,7 @@ config P5020_DS
188 select SWIOTLB 218 select SWIOTLB
189 select MPC8xxx_GPIO 219 select MPC8xxx_GPIO
190 select HAS_RAPIDIO 220 select HAS_RAPIDIO
221 select PPC_EPAPR_HV_PIC
191 help 222 help
192 This option enables support for the P5020 DS board 223 This option enables support for the P5020 DS board
193 224
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index dd70db77d63e..a971b32c5c0a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,7 +10,10 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
10obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o 10obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o 11obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o 12obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
13obj-$(CONFIG_P1010_RDB) += p1010rdb.o
13obj-$(CONFIG_P1022_DS) += p1022_ds.o 14obj-$(CONFIG_P1022_DS) += p1022_ds.o
15obj-$(CONFIG_P1023_RDS) += p1023_rds.o
16obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
14obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 17obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
15obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 18obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
16obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 19obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 2ab338c9ac37..802ad110b757 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information) 4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 * 5 *
6 * Copyright 2009 Freescale Semiconductor Inc. 6 * Copyright 2009-2011 Freescale Semiconductor Inc.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -22,6 +22,7 @@
22#include <asm/time.h> 22#include <asm/time.h>
23#include <asm/machdep.h> 23#include <asm/machdep.h>
24#include <asm/pci-bridge.h> 24#include <asm/pci-bridge.h>
25#include <asm/ppc-pci.h>
25#include <mm/mmu_decl.h> 26#include <mm/mmu_decl.h>
26#include <asm/prom.h> 27#include <asm/prom.h>
27#include <asm/udbg.h> 28#include <asm/udbg.h>
@@ -61,10 +62,6 @@ void __init corenet_ds_pic_init(void)
61 mpic_init(mpic); 62 mpic_init(mpic);
62} 63}
63 64
64#ifdef CONFIG_PCI
65static int primary_phb_addr;
66#endif
67
68/* 65/*
69 * Setup the architecture 66 * Setup the architecture
70 */ 67 */
@@ -85,18 +82,19 @@ void __init corenet_ds_setup_arch(void)
85#endif 82#endif
86 83
87#ifdef CONFIG_PCI 84#ifdef CONFIG_PCI
88 for_each_compatible_node(np, "pci", "fsl,p4080-pcie") { 85 for_each_node_by_type(np, "pci") {
89 struct resource rsrc; 86 if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
90 of_address_to_resource(np, 0, &rsrc); 87 of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
91 if ((rsrc.start & 0xfffff) == primary_phb_addr)
92 fsl_add_bridge(np, 1);
93 else
94 fsl_add_bridge(np, 0); 88 fsl_add_bridge(np, 0);
95 89 hose = pci_find_hose_for_OF_device(np);
96 hose = pci_find_hose_for_OF_device(np); 90 max = min(max, hose->dma_window_base_cur +
97 max = min(max, hose->dma_window_base_cur + 91 hose->dma_window_size);
98 hose->dma_window_size); 92 }
99 } 93 }
94
95#ifdef CONFIG_PPC64
96 pci_devs_phb_init();
97#endif
100#endif 98#endif
101 99
102#ifdef CONFIG_SWIOTLB 100#ifdef CONFIG_SWIOTLB
@@ -116,6 +114,19 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
116 { 114 {
117 .compatible = "fsl,rapidio-delta", 115 .compatible = "fsl,rapidio-delta",
118 }, 116 },
117 {
118 .compatible = "fsl,p4080-pcie",
119 },
120 {
121 .compatible = "fsl,qoriq-pcie-v2.2",
122 },
123 /* The following two are for the Freescale hypervisor */
124 {
125 .name = "hypervisor",
126 },
127 {
128 .name = "handles",
129 },
119 {} 130 {}
120}; 131};
121 132
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index c7b97f70312e..1b9a8cf1873a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -83,7 +83,8 @@ void __init mpc85xx_ds_pic_init(void)
83 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) { 83 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
84 mpic = mpic_alloc(np, r.start, 84 mpic = mpic_alloc(np, r.start,
85 MPIC_PRIMARY | 85 MPIC_PRIMARY |
86 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, 86 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
87 MPIC_SINGLE_DEST_CPU,
87 0, 256, " OpenPIC "); 88 0, 256, " OpenPIC ");
88 } else { 89 } else {
89 mpic = mpic_alloc(np, r.start, 90 mpic = mpic_alloc(np, r.start,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 088f30b0c088..f5ff9110c97e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -58,10 +58,11 @@ void __init mpc85xx_rdb_pic_init(void)
58 return; 58 return;
59 } 59 }
60 60
61 if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) { 61 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
62 mpic = mpic_alloc(np, r.start, 62 mpic = mpic_alloc(np, r.start,
63 MPIC_PRIMARY | 63 MPIC_PRIMARY |
64 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, 64 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
65 MPIC_SINGLE_DEST_CPU,
65 0, 256, " OpenPIC "); 66 0, 256, " OpenPIC ");
66 } else { 67 } else {
67 mpic = mpic_alloc(np, r.start, 68 mpic = mpic_alloc(np, r.start,
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
new file mode 100644
index 000000000000..d7387fa7f534
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -0,0 +1,122 @@
1/*
2 * P1010RDB Board Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/of_platform.h>
18
19#include <asm/system.h>
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30
31void __init p1010_rdb_pic_init(void)
32{
33 struct mpic *mpic;
34 struct resource r;
35 struct device_node *np;
36
37 np = of_find_node_by_type(NULL, "open-pic");
38 if (np == NULL) {
39 printk(KERN_ERR "Could not find open-pic node\n");
40 return;
41 }
42
43 if (of_address_to_resource(np, 0, &r)) {
44 printk(KERN_ERR "Failed to map mpic register space\n");
45 of_node_put(np);
46 return;
47 }
48
49 mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET |
50 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
51 0, 256, " OpenPIC ");
52
53 BUG_ON(mpic == NULL);
54 of_node_put(np);
55
56 mpic_init(mpic);
57
58}
59
60
61/*
62 * Setup the architecture
63 */
64static void __init p1010_rdb_setup_arch(void)
65{
66#ifdef CONFIG_PCI
67 struct device_node *np;
68#endif
69
70 if (ppc_md.progress)
71 ppc_md.progress("p1010_rdb_setup_arch()", 0);
72
73#ifdef CONFIG_PCI
74 for_each_node_by_type(np, "pci") {
75 if (of_device_is_compatible(np, "fsl,p1010-pcie"))
76 fsl_add_bridge(np, 0);
77 }
78
79#endif
80
81 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
82}
83
84static struct of_device_id __initdata p1010rdb_ids[] = {
85 { .type = "soc", },
86 { .compatible = "soc", },
87 { .compatible = "simple-bus", },
88 {},
89};
90
91static int __init p1010rdb_publish_devices(void)
92{
93 return of_platform_bus_probe(NULL, p1010rdb_ids, NULL);
94}
95machine_device_initcall(p1010_rdb, p1010rdb_publish_devices);
96machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
97
98/*
99 * Called very early, device-tree isn't unflattened
100 */
101static int __init p1010_rdb_probe(void)
102{
103 unsigned long root = of_get_flat_dt_root();
104
105 if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
106 return 1;
107 return 0;
108}
109
110define_machine(p1010_rdb) {
111 .name = "P1010 RDB",
112 .probe = p1010_rdb_probe,
113 .setup_arch = p1010_rdb_setup_arch,
114 .init_IRQ = p1010_rdb_pic_init,
115#ifdef CONFIG_PCI
116 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
117#endif
118 .get_irq = mpic_get_irq,
119 .restart = fsl_rstcr_restart,
120 .calibrate_decr = generic_calibrate_decr,
121 .progress = udbg_progress,
122};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 7eb5c40c069f..266b3aadfe5e 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -129,6 +129,7 @@ static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
129static void p1022ds_set_monitor_port(int monitor_port) 129static void p1022ds_set_monitor_port(int monitor_port)
130{ 130{
131 struct device_node *pixis_node; 131 struct device_node *pixis_node;
132 void __iomem *pixis;
132 u8 __iomem *brdcfg1; 133 u8 __iomem *brdcfg1;
133 134
134 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); 135 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
@@ -137,12 +138,12 @@ static void p1022ds_set_monitor_port(int monitor_port)
137 return; 138 return;
138 } 139 }
139 140
140 brdcfg1 = of_iomap(pixis_node, 0); 141 pixis = of_iomap(pixis_node, 0);
141 if (!brdcfg1) { 142 if (!pixis) {
142 pr_err("p1022ds: could not map ngPIXIS registers\n"); 143 pr_err("p1022ds: could not map ngPIXIS registers\n");
143 return; 144 return;
144 } 145 }
145 brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ 146 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
146 147
147 switch (monitor_port) { 148 switch (monitor_port) {
148 case 0: /* DVI */ 149 case 0: /* DVI */
@@ -158,6 +159,8 @@ static void p1022ds_set_monitor_port(int monitor_port)
158 default: 159 default:
159 pr_err("p1022ds: unsupported monitor port %i\n", monitor_port); 160 pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
160 } 161 }
162
163 iounmap(pixis);
161} 164}
162 165
163/** 166/**
@@ -192,8 +195,13 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
192 do_div(temp, pixclock); 195 do_div(temp, pixclock);
193 freq = temp; 196 freq = temp;
194 197
195 /* pixclk is the ratio of the platform clock to the pixel clock */ 198 /*
199 * 'pxclk' is the ratio of the platform clock to the pixel clock.
200 * This number is programmed into the CLKDVDR register, and the valid
201 * range of values is 2-255.
202 */
196 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); 203 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
204 pxclk = clamp_t(u32, pxclk, 2, 255);
197 205
198 /* Disable the pixel clock, and set it to non-inverted and no delay */ 206 /* Disable the pixel clock, and set it to non-inverted and no delay */
199 clrbits32(&guts->clkdvdr, 207 clrbits32(&guts->clkdvdr,
@@ -201,6 +209,8 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
201 209
202 /* Enable the clock and set the pxclk */ 210 /* Enable the clock and set the pxclk */
203 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); 211 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
212
213 iounmap(guts);
204} 214}
205 215
206/** 216/**
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
new file mode 100644
index 000000000000..835e0b335bfa
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -0,0 +1,162 @@
1/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * Author: Roy Zang <tie-fei.zang@freescale.com>
5 *
6 * Description:
7 * P1023 RDS Board Setup
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/module.h>
21#include <linux/fsl_devices.h>
22#include <linux/of_platform.h>
23#include <linux/of_device.h>
24
25#include <asm/system.h>
26#include <asm/time.h>
27#include <asm/machdep.h>
28#include <asm/pci-bridge.h>
29#include <mm/mmu_decl.h>
30#include <asm/prom.h>
31#include <asm/udbg.h>
32#include <asm/mpic.h>
33
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37/* ************************************************************************
38 *
39 * Setup the architecture
40 *
41 */
42#ifdef CONFIG_SMP
43void __init mpc85xx_smp_init(void);
44#endif
45
46static void __init mpc85xx_rds_setup_arch(void)
47{
48 struct device_node *np;
49
50 if (ppc_md.progress)
51 ppc_md.progress("p1023_rds_setup_arch()", 0);
52
53 /* Map BCSR area */
54 np = of_find_node_by_name(NULL, "bcsr");
55 if (np != NULL) {
56 static u8 __iomem *bcsr_regs;
57
58 bcsr_regs = of_iomap(np, 0);
59 of_node_put(np);
60
61 if (!bcsr_regs) {
62 printk(KERN_ERR
63 "BCSR: Failed to map bcsr register space\n");
64 return;
65 } else {
66#define BCSR15_I2C_BUS0_SEG_CLR 0x07
67#define BCSR15_I2C_BUS0_SEG2 0x02
68/*
69 * Note: Accessing exclusively i2c devices.
70 *
71 * The i2c controller selects initially ID EEPROM in the u-boot;
72 * but if menu configuration selects RTC support in the kernel,
73 * the i2c controller switches to select RTC chip in the kernel.
74 */
75#ifdef CONFIG_RTC_CLASS
76 /* Enable RTC chip on the segment #2 of i2c */
77 clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
78 setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
79#endif
80
81 iounmap(bcsr_regs);
82 }
83 }
84
85#ifdef CONFIG_PCI
86 for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
87 fsl_add_bridge(np, 0);
88#endif
89
90#ifdef CONFIG_SMP
91 mpc85xx_smp_init();
92#endif
93}
94
95static struct of_device_id p1023_ids[] = {
96 { .type = "soc", },
97 { .compatible = "soc", },
98 { .compatible = "simple-bus", },
99 {},
100};
101
102
103static int __init p1023_publish_devices(void)
104{
105 of_platform_bus_probe(NULL, p1023_ids, NULL);
106
107 return 0;
108}
109
110machine_device_initcall(p1023_rds, p1023_publish_devices);
111
112static void __init mpc85xx_rds_pic_init(void)
113{
114 struct mpic *mpic;
115 struct resource r;
116 struct device_node *np = NULL;
117
118 np = of_find_node_by_type(NULL, "open-pic");
119 if (!np) {
120 printk(KERN_ERR "Could not find open-pic node\n");
121 return;
122 }
123
124 if (of_address_to_resource(np, 0, &r)) {
125 printk(KERN_ERR "Failed to map mpic register space\n");
126 of_node_put(np);
127 return;
128 }
129
130 mpic = mpic_alloc(np, r.start,
131 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
132 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
133 0, 256, " OpenPIC ");
134
135 BUG_ON(mpic == NULL);
136 of_node_put(np);
137
138 mpic_init(mpic);
139}
140
141static int __init p1023_rds_probe(void)
142{
143 unsigned long root = of_get_flat_dt_root();
144
145 return of_flat_dt_is_compatible(root, "fsl,P1023RDS");
146
147}
148
149define_machine(p1023_rds) {
150 .name = "P1023 RDS",
151 .probe = p1023_rds_probe,
152 .setup_arch = mpc85xx_rds_setup_arch,
153 .init_IRQ = mpc85xx_rds_pic_init,
154 .get_irq = mpic_get_irq,
155 .restart = fsl_rstcr_restart,
156 .calibrate_decr = generic_calibrate_decr,
157 .progress = udbg_progress,
158#ifdef CONFIG_PCI
159 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
160#endif
161};
162
diff --git a/arch/powerpc/platforms/85xx/p2040_rdb.c b/arch/powerpc/platforms/85xx/p2040_rdb.c
new file mode 100644
index 000000000000..32b56ac73dfb
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p2040_rdb.c
@@ -0,0 +1,88 @@
1/*
2 * P2040 RDB Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/kdev_t.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/phy.h>
18
19#include <asm/system.h>
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <linux/of_platform.h>
29#include <sysdev/fsl_soc.h>
30#include <sysdev/fsl_pci.h>
31#include <asm/ehv_pic.h>
32
33#include "corenet_ds.h"
34
35/*
36 * Called very early, device-tree isn't unflattened
37 */
38static int __init p2040_rdb_probe(void)
39{
40 unsigned long root = of_get_flat_dt_root();
41#ifdef CONFIG_SMP
42 extern struct smp_ops_t smp_85xx_ops;
43#endif
44
45 if (of_flat_dt_is_compatible(root, "fsl,P2040RDB"))
46 return 1;
47
48 /* Check if we're running under the Freescale hypervisor */
49 if (of_flat_dt_is_compatible(root, "fsl,P2040RDB-hv")) {
50 ppc_md.init_IRQ = ehv_pic_init;
51 ppc_md.get_irq = ehv_pic_get_irq;
52 ppc_md.restart = fsl_hv_restart;
53 ppc_md.power_off = fsl_hv_halt;
54 ppc_md.halt = fsl_hv_halt;
55#ifdef CONFIG_SMP
56 /*
57 * Disable the timebase sync operations because we can't write
58 * to the timebase registers under the hypervisor.
59 */
60 smp_85xx_ops.give_timebase = NULL;
61 smp_85xx_ops.take_timebase = NULL;
62#endif
63 return 1;
64 }
65
66 return 0;
67}
68
69define_machine(p2040_rdb) {
70 .name = "P2040 RDB",
71 .probe = p2040_rdb_probe,
72 .setup_arch = corenet_ds_setup_arch,
73 .init_IRQ = corenet_ds_pic_init,
74#ifdef CONFIG_PCI
75 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
76#endif
77 .get_irq = mpic_get_coreint_irq,
78 .restart = fsl_rstcr_restart,
79 .calibrate_decr = generic_calibrate_decr,
80 .progress = udbg_progress,
81 .power_save = e500_idle,
82};
83
84machine_device_initcall(p2040_rdb, corenet_ds_publish_devices);
85
86#ifdef CONFIG_SWIOTLB
87machine_arch_initcall(p2040_rdb, swiotlb_setup_bus_notifier);
88#endif
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
index 0ed52e18298c..96d99a374dcf 100644
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ b/arch/powerpc/platforms/85xx/p3041_ds.c
@@ -30,6 +30,7 @@
30#include <linux/of_platform.h> 30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h> 31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h> 32#include <sysdev/fsl_pci.h>
33#include <asm/ehv_pic.h>
33 34
34#include "corenet_ds.h" 35#include "corenet_ds.h"
35 36
@@ -39,8 +40,32 @@
39static int __init p3041_ds_probe(void) 40static int __init p3041_ds_probe(void)
40{ 41{
41 unsigned long root = of_get_flat_dt_root(); 42 unsigned long root = of_get_flat_dt_root();
43#ifdef CONFIG_SMP
44 extern struct smp_ops_t smp_85xx_ops;
45#endif
46
47 if (of_flat_dt_is_compatible(root, "fsl,P3041DS"))
48 return 1;
49
50 /* Check if we're running under the Freescale hypervisor */
51 if (of_flat_dt_is_compatible(root, "fsl,P3041DS-hv")) {
52 ppc_md.init_IRQ = ehv_pic_init;
53 ppc_md.get_irq = ehv_pic_get_irq;
54 ppc_md.restart = fsl_hv_restart;
55 ppc_md.power_off = fsl_hv_halt;
56 ppc_md.halt = fsl_hv_halt;
57#ifdef CONFIG_SMP
58 /*
59 * Disable the timebase sync operations because we can't write
60 * to the timebase registers under the hypervisor.
61 */
62 smp_85xx_ops.give_timebase = NULL;
63 smp_85xx_ops.take_timebase = NULL;
64#endif
65 return 1;
66 }
42 67
43 return of_flat_dt_is_compatible(root, "fsl,P3041DS"); 68 return 0;
44} 69}
45 70
46define_machine(p3041_ds) { 71define_machine(p3041_ds) {
@@ -55,6 +80,7 @@ define_machine(p3041_ds) {
55 .restart = fsl_rstcr_restart, 80 .restart = fsl_rstcr_restart,
56 .calibrate_decr = generic_calibrate_decr, 81 .calibrate_decr = generic_calibrate_decr,
57 .progress = udbg_progress, 82 .progress = udbg_progress,
83 .power_save = e500_idle,
58}; 84};
59 85
60machine_device_initcall(p3041_ds, corenet_ds_publish_devices); 86machine_device_initcall(p3041_ds, corenet_ds_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
index 84170460497b..d1b21d7663e3 100644
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ b/arch/powerpc/platforms/85xx/p4080_ds.c
@@ -29,31 +29,42 @@
29#include <linux/of_platform.h> 29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h> 30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h> 31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
32 33
33#include "corenet_ds.h" 34#include "corenet_ds.h"
34 35
35#ifdef CONFIG_PCI
36static int primary_phb_addr;
37#endif
38
39/* 36/*
40 * Called very early, device-tree isn't unflattened 37 * Called very early, device-tree isn't unflattened
41 */ 38 */
42static int __init p4080_ds_probe(void) 39static int __init p4080_ds_probe(void)
43{ 40{
44 unsigned long root = of_get_flat_dt_root(); 41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45 45
46 if (of_flat_dt_is_compatible(root, "fsl,P4080DS")) { 46 if (of_flat_dt_is_compatible(root, "fsl,P4080DS"))
47#ifdef CONFIG_PCI 47 return 1;
48 /* treat PCIe1 as primary, 48
49 * shouldn't matter as we have no ISA on the board 49 /* Check if we're running under the Freescale hypervisor */
50 */ 50 if (of_flat_dt_is_compatible(root, "fsl,P4080DS-hv")) {
51 primary_phb_addr = 0x0000; 51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
52#endif 63#endif
53 return 1; 64 return 1;
54 } else {
55 return 0;
56 } 65 }
66
67 return 0;
57} 68}
58 69
59define_machine(p4080_ds) { 70define_machine(p4080_ds) {
@@ -68,7 +79,10 @@ define_machine(p4080_ds) {
68 .restart = fsl_rstcr_restart, 79 .restart = fsl_rstcr_restart,
69 .calibrate_decr = generic_calibrate_decr, 80 .calibrate_decr = generic_calibrate_decr,
70 .progress = udbg_progress, 81 .progress = udbg_progress,
82 .power_save = e500_idle,
71}; 83};
72 84
73machine_device_initcall(p4080_ds, corenet_ds_publish_devices); 85machine_device_initcall(p4080_ds, corenet_ds_publish_devices);
86#ifdef CONFIG_SWIOTLB
74machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier); 87machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
88#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
index 7467b712ee00..e8cba5004fd8 100644
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -30,6 +30,7 @@
30#include <linux/of_platform.h> 30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h> 31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h> 32#include <sysdev/fsl_pci.h>
33#include <asm/ehv_pic.h>
33 34
34#include "corenet_ds.h" 35#include "corenet_ds.h"
35 36
@@ -39,8 +40,32 @@
39static int __init p5020_ds_probe(void) 40static int __init p5020_ds_probe(void)
40{ 41{
41 unsigned long root = of_get_flat_dt_root(); 42 unsigned long root = of_get_flat_dt_root();
43#ifdef CONFIG_SMP
44 extern struct smp_ops_t smp_85xx_ops;
45#endif
46
47 if (of_flat_dt_is_compatible(root, "fsl,P5020DS"))
48 return 1;
49
50 /* Check if we're running under the Freescale hypervisor */
51 if (of_flat_dt_is_compatible(root, "fsl,P5020DS-hv")) {
52 ppc_md.init_IRQ = ehv_pic_init;
53 ppc_md.get_irq = ehv_pic_get_irq;
54 ppc_md.restart = fsl_hv_restart;
55 ppc_md.power_off = fsl_hv_halt;
56 ppc_md.halt = fsl_hv_halt;
57#ifdef CONFIG_SMP
58 /*
59 * Disable the timebase sync operations because we can't write
60 * to the timebase registers under the hypervisor.
61 */
62 smp_85xx_ops.give_timebase = NULL;
63 smp_85xx_ops.take_timebase = NULL;
64#endif
65 return 1;
66 }
42 67
43 return of_flat_dt_is_compatible(root, "fsl,P5020DS"); 68 return 0;
44} 69}
45 70
46define_machine(p5020_ds) { 71define_machine(p5020_ds) {
@@ -60,6 +85,11 @@ define_machine(p5020_ds) {
60 .restart = fsl_rstcr_restart, 85 .restart = fsl_rstcr_restart,
61 .calibrate_decr = generic_calibrate_decr, 86 .calibrate_decr = generic_calibrate_decr,
62 .progress = udbg_progress, 87 .progress = udbg_progress,
88#ifdef CONFIG_PPC64
89 .power_save = book3e_idle,
90#else
91 .power_save = e500_idle,
92#endif
63}; 93};
64 94
65machine_device_initcall(p5020_ds, corenet_ds_publish_devices); 95machine_device_initcall(p5020_ds, corenet_ds_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index d6a93a10c0f5..5b9b901f6443 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -2,7 +2,7 @@
2 * Author: Andy Fleming <afleming@freescale.com> 2 * Author: Andy Fleming <afleming@freescale.com>
3 * Kumar Gala <galak@kernel.crashing.org> 3 * Kumar Gala <galak@kernel.crashing.org>
4 * 4 *
5 * Copyright 2006-2008 Freescale Semiconductor Inc. 5 * Copyright 2006-2008, 2011 Freescale Semiconductor Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -111,14 +111,6 @@ smp_85xx_kick_cpu(int nr)
111 return 0; 111 return 0;
112} 112}
113 113
114static void __init
115smp_85xx_setup_cpu(int cpu_nr)
116{
117 mpic_setup_this_cpu();
118 if (cpu_has_feature(CPU_FTR_DBELL))
119 doorbell_setup_this_cpu();
120}
121
122struct smp_ops_t smp_85xx_ops = { 114struct smp_ops_t smp_85xx_ops = {
123 .kick_cpu = smp_85xx_kick_cpu, 115 .kick_cpu = smp_85xx_kick_cpu,
124#ifdef CONFIG_KEXEC 116#ifdef CONFIG_KEXEC
@@ -224,24 +216,36 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
224} 216}
225#endif /* CONFIG_KEXEC */ 217#endif /* CONFIG_KEXEC */
226 218
219static void __init
220smp_85xx_setup_cpu(int cpu_nr)
221{
222 if (smp_85xx_ops.probe == smp_mpic_probe)
223 mpic_setup_this_cpu();
224
225 if (cpu_has_feature(CPU_FTR_DBELL))
226 doorbell_setup_this_cpu();
227}
228
227void __init mpc85xx_smp_init(void) 229void __init mpc85xx_smp_init(void)
228{ 230{
229 struct device_node *np; 231 struct device_node *np;
230 232
233 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
234
231 np = of_find_node_by_type(NULL, "open-pic"); 235 np = of_find_node_by_type(NULL, "open-pic");
232 if (np) { 236 if (np) {
233 smp_85xx_ops.probe = smp_mpic_probe; 237 smp_85xx_ops.probe = smp_mpic_probe;
234 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
235 smp_85xx_ops.message_pass = smp_mpic_message_pass; 238 smp_85xx_ops.message_pass = smp_mpic_message_pass;
236 } 239 }
237 240
238 if (cpu_has_feature(CPU_FTR_DBELL)) { 241 if (cpu_has_feature(CPU_FTR_DBELL)) {
239 smp_85xx_ops.message_pass = smp_muxed_ipi_message_pass; 242 /*
243 * If left NULL, .message_pass defaults to
244 * smp_muxed_ipi_message_pass
245 */
240 smp_85xx_ops.cause_ipi = doorbell_cause_ipi; 246 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
241 } 247 }
242 248
243 BUG_ON(!smp_85xx_ops.message_pass);
244
245 smp_ops = &smp_85xx_ops; 249 smp_ops = &smp_85xx_ops;
246 250
247#ifdef CONFIG_KEXEC 251#ifdef CONFIG_KEXEC
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index a896511690c2..74e018ef724b 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -39,12 +39,19 @@
39#include <sysdev/fsl_pci.h> 39#include <sysdev/fsl_pci.h>
40#include <sysdev/fsl_soc.h> 40#include <sysdev/fsl_soc.h>
41#include <sysdev/simple_gpio.h> 41#include <sysdev/simple_gpio.h>
42#include <asm/fsl_guts.h>
42 43
43#include "mpc86xx.h" 44#include "mpc86xx.h"
44 45
45static struct device_node *pixis_node; 46static struct device_node *pixis_node;
46static unsigned char *pixis_bdcfg0, *pixis_arch; 47static unsigned char *pixis_bdcfg0, *pixis_arch;
47 48
49/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
50#define CLKDVDR_PXCKEN 0x80000000
51#define CLKDVDR_PXCKINV 0x10000000
52#define CLKDVDR_PXCKDLY 0x06000000
53#define CLKDVDR_PXCLK_MASK 0x001F0000
54
48#ifdef CONFIG_SUSPEND 55#ifdef CONFIG_SUSPEND
49static irqreturn_t mpc8610_sw9_irq(int irq, void *data) 56static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
50{ 57{
@@ -205,72 +212,54 @@ void mpc8610hpcd_set_monitor_port(int monitor_port)
205 bdcfg[monitor_port]); 212 bdcfg[monitor_port]);
206} 213}
207 214
215/**
216 * mpc8610hpcd_set_pixel_clock: program the DIU's clock
217 *
218 * @pixclock: the wavelength, in picoseconds, of the clock
219 */
208void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) 220void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
209{ 221{
210 u32 __iomem *clkdvdr; 222 struct device_node *guts_np = NULL;
211 u32 temp; 223 struct ccsr_guts_86xx __iomem *guts;
212 /* variables for pixel clock calcs */ 224 unsigned long freq;
213 ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock; 225 u64 temp;
214 ulong pixval; 226 u32 pxclk;
215 long err; 227
216 int i; 228 /* Map the global utilities registers. */
217 229 guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
218 clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32)); 230 if (!guts_np) {
219 if (!clkdvdr) { 231 pr_err("mpc8610hpcd: missing global utilties device node\n");
220 printk(KERN_ERR "Err: can't map clock divider register!\n");
221 return; 232 return;
222 } 233 }
223 234
224 /* Pixel Clock configuration */ 235 guts = of_iomap(guts_np, 0);
225 speed_ccb = fsl_get_sys_freq(); 236 of_node_put(guts_np);
226 237 if (!guts) {
227 /* Calculate the pixel clock with the smallest error */ 238 pr_err("mpc8610hpcd: could not map global utilties device\n");
228 /* calculate the following in steps to avoid overflow */ 239 return;
229 pr_debug("DIU pixclock in ps - %d\n", pixclock);
230 temp = 1000000000/pixclock;
231 temp *= 1000;
232 pixclock = temp;
233 pr_debug("DIU pixclock freq - %u\n", pixclock);
234
235 temp = pixclock * 5 / 100;
236 pr_debug("deviation = %d\n", temp);
237 minpixclock = pixclock - temp;
238 maxpixclock = pixclock + temp;
239 pr_debug("DIU minpixclock - %lu\n", minpixclock);
240 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
241 pixval = speed_ccb/pixclock;
242 pr_debug("DIU pixval = %lu\n", pixval);
243
244 err = 100000000;
245 bestval = pixval;
246 pr_debug("DIU bestval = %lu\n", bestval);
247
248 bestfreq = 0;
249 for (i = -1; i <= 1; i++) {
250 temp = speed_ccb / ((pixval+i) + 1);
251 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
252 i, pixval, temp);
253 if ((temp < minpixclock) || (temp > maxpixclock))
254 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
255 minpixclock, maxpixclock);
256 else if (abs(temp - pixclock) < err) {
257 pr_debug("Entered the else if block %d\n", i);
258 err = abs(temp - pixclock);
259 bestval = pixval+i;
260 bestfreq = temp;
261 }
262 } 240 }
263 241
264 pr_debug("DIU chose = %lx\n", bestval); 242 /* Convert pixclock from a wavelength to a frequency */
265 pr_debug("DIU error = %ld\n NomPixClk ", err); 243 temp = 1000000000000ULL;
266 pr_debug("DIU: Best Freq = %lx\n", bestfreq); 244 do_div(temp, pixclock);
267 /* Modify PXCLK in GUTS CLKDVDR */ 245 freq = temp;
268 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr)); 246
269 temp = (*clkdvdr) & 0x2000FFFF; 247 /*
270 *clkdvdr = temp; /* turn off clock */ 248 * 'pxclk' is the ratio of the platform clock to the pixel clock.
271 *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16); 249 * On the MPC8610, the value programmed into CLKDVDR is the ratio
272 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr)); 250 * minus one. The valid range of values is 2-31.
273 iounmap(clkdvdr); 251 */
252 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
253 pxclk = clamp_t(u32, pxclk, 2, 31);
254
255 /* Disable the pixel clock, and set it to non-inverted and no delay */
256 clrbits32(&guts->clkdvdr,
257 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
258
259 /* Enable the clock and set the pxclk */
260 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
261
262 iounmap(guts);
274} 263}
275 264
276ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf) 265ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index f970ca2b180c..d0af7fb2f344 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -78,6 +78,10 @@ config MPIC
78 bool 78 bool
79 default n 79 default n
80 80
81config PPC_EPAPR_HV_PIC
82 bool
83 default n
84
81config MPIC_WEIRD 85config MPIC_WEIRD
82 bool 86 bool
83 default n 87 default n
@@ -266,7 +270,7 @@ config TAU_AVERAGE
266 270
267config QUICC_ENGINE 271config QUICC_ENGINE
268 bool "Freescale QUICC Engine (QE) Support" 272 bool "Freescale QUICC Engine (QE) Support"
269 depends on FSL_SOC 273 depends on FSL_SOC && PPC32
270 select PPC_LIB_RHEAP 274 select PPC_LIB_RHEAP
271 select CRC32 275 select CRC32
272 help 276 help
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 2165b65876f9..e06e39589a09 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -1,7 +1,6 @@
1config PPC64 1config PPC64
2 bool "64-bit kernel" 2 bool "64-bit kernel"
3 default n 3 default n
4 select PPC_HAVE_PMU_SUPPORT
5 help 4 help
6 This option selects whether a 32-bit or a 64-bit kernel 5 This option selects whether a 32-bit or a 64-bit kernel
7 will be built. 6 will be built.
@@ -69,6 +68,7 @@ choice
69config PPC_BOOK3S_64 68config PPC_BOOK3S_64
70 bool "Server processors" 69 bool "Server processors"
71 select PPC_FPU 70 select PPC_FPU
71 select PPC_HAVE_PMU_SUPPORT
72 72
73config PPC_BOOK3E_64 73config PPC_BOOK3E_64
74 bool "Embedded processors" 74 bool "Embedded processors"
diff --git a/arch/powerpc/platforms/iseries/smp.c b/arch/powerpc/platforms/iseries/smp.c
index e3265adde5d3..2df48c2287bd 100644
--- a/arch/powerpc/platforms/iseries/smp.c
+++ b/arch/powerpc/platforms/iseries/smp.c
@@ -75,7 +75,7 @@ static void __devinit smp_iSeries_setup_cpu(int nr)
75} 75}
76 76
77static struct smp_ops_t iSeries_smp_ops = { 77static struct smp_ops_t iSeries_smp_ops = {
78 .message_pass = smp_muxed_ipi_message_pass, 78 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
79 .cause_ipi = smp_iSeries_cause_ipi, 79 .cause_ipi = smp_iSeries_cause_ipi,
80 .probe = smp_iSeries_probe, 80 .probe = smp_iSeries_probe,
81 .kick_cpu = smp_iSeries_kick_cpu, 81 .kick_cpu = smp_iSeries_kick_cpu,
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index fe34c3d9bb74..5b3388b9f911 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -338,35 +338,16 @@ define_machine(maple) {
338#ifdef CONFIG_EDAC 338#ifdef CONFIG_EDAC
339/* 339/*
340 * Register a platform device for CPC925 memory controller on 340 * Register a platform device for CPC925 memory controller on
341 * Motorola ATCA-6101 blade. 341 * all boards with U3H (CPC925) bridge.
342 */ 342 */
343#define MAPLE_CPC925_MODEL "Motorola,ATCA-6101"
344static int __init maple_cpc925_edac_setup(void) 343static int __init maple_cpc925_edac_setup(void)
345{ 344{
346 struct platform_device *pdev; 345 struct platform_device *pdev;
347 struct device_node *np = NULL; 346 struct device_node *np = NULL;
348 struct resource r; 347 struct resource r;
349 const unsigned char *model;
350 int ret; 348 int ret;
351 349 volatile void __iomem *mem;
352 np = of_find_node_by_path("/"); 350 u32 rev;
353 if (!np) {
354 printk(KERN_ERR "%s: Unable to get root node\n", __func__);
355 return -ENODEV;
356 }
357
358 model = (const unsigned char *)of_get_property(np, "model", NULL);
359 if (!model) {
360 printk(KERN_ERR "%s: Unabel to get model info\n", __func__);
361 of_node_put(np);
362 return -ENODEV;
363 }
364
365 ret = strcmp(model, MAPLE_CPC925_MODEL);
366 of_node_put(np);
367
368 if (ret != 0)
369 return 0;
370 351
371 np = of_find_node_by_type(NULL, "memory-controller"); 352 np = of_find_node_by_type(NULL, "memory-controller");
372 if (!np) { 353 if (!np) {
@@ -384,6 +365,22 @@ static int __init maple_cpc925_edac_setup(void)
384 return -ENODEV; 365 return -ENODEV;
385 } 366 }
386 367
368 mem = ioremap(r.start, resource_size(&r));
369 if (!mem) {
370 printk(KERN_ERR "%s: Unable to map memory-controller memory\n",
371 __func__);
372 return -ENOMEM;
373 }
374
375 rev = __raw_readl(mem);
376 iounmap(mem);
377
378 if (rev < 0x34 || rev > 0x3f) { /* U3H */
379 printk(KERN_ERR "%s: Non-CPC925(U3H) bridge revision: %02x\n",
380 __func__, rev);
381 return 0;
382 }
383
387 pdev = platform_device_register_simple("cpc925_edac", 0, &r, 1); 384 pdev = platform_device_register_simple("cpc925_edac", 0, &r, 1);
388 if (IS_ERR(pdev)) 385 if (IS_ERR(pdev))
389 return PTR_ERR(pdev); 386 return PTR_ERR(pdev);
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index aa45281bd296..a028f08309d6 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -355,9 +355,6 @@ static int initializing = 1;
355static int pmac_late_init(void) 355static int pmac_late_init(void)
356{ 356{
357 initializing = 0; 357 initializing = 0;
358 /* this is udbg (which is __init) and we can later use it during
359 * cpu hotplug (in smp_core99_kick_cpu) */
360 ppc_md.progress = NULL;
361 return 0; 358 return 0;
362} 359}
363machine_late_initcall(powermac, pmac_late_init); 360machine_late_initcall(powermac, pmac_late_init);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index db092d7c4c5b..d15fca322978 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -447,7 +447,7 @@ void __init smp_psurge_give_timebase(void)
447 447
448/* PowerSurge-style Macs */ 448/* PowerSurge-style Macs */
449struct smp_ops_t psurge_smp_ops = { 449struct smp_ops_t psurge_smp_ops = {
450 .message_pass = smp_muxed_ipi_message_pass, 450 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
451 .cause_ipi = smp_psurge_cause_ipi, 451 .cause_ipi = smp_psurge_cause_ipi,
452 .probe = smp_psurge_probe, 452 .probe = smp_psurge_probe,
453 .kick_cpu = smp_psurge_kick_cpu, 453 .kick_cpu = smp_psurge_kick_cpu,
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index 57ceb92b2288..e9be25bc571b 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -262,12 +262,11 @@ int dlpar_attach_node(struct device_node *dn)
262 if (!dn->parent) 262 if (!dn->parent)
263 return -ENOMEM; 263 return -ENOMEM;
264 264
265 rc = blocking_notifier_call_chain(&pSeries_reconfig_chain, 265 rc = pSeries_reconfig_notify(PSERIES_RECONFIG_ADD, dn);
266 PSERIES_RECONFIG_ADD, dn); 266 if (rc) {
267 if (rc == NOTIFY_BAD) {
268 printk(KERN_ERR "Failed to add device node %s\n", 267 printk(KERN_ERR "Failed to add device node %s\n",
269 dn->full_name); 268 dn->full_name);
270 return -ENOMEM; /* For now, safe to assume kmalloc failure */ 269 return rc;
271 } 270 }
272 271
273 of_attach_node(dn); 272 of_attach_node(dn);
@@ -297,8 +296,7 @@ int dlpar_detach_node(struct device_node *dn)
297 remove_proc_entry(dn->pde->name, parent->pde); 296 remove_proc_entry(dn->pde->name, parent->pde);
298#endif 297#endif
299 298
300 blocking_notifier_call_chain(&pSeries_reconfig_chain, 299 pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, dn);
301 PSERIES_RECONFIG_REMOVE, dn);
302 of_detach_node(dn); 300 of_detach_node(dn);
303 of_node_put(dn); /* Must decrement the refcount */ 301 of_node_put(dn); /* Must decrement the refcount */
304 302
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 46f13a3c5d09..bc0288501f17 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -330,21 +330,17 @@ static void pseries_remove_processor(struct device_node *np)
330static int pseries_smp_notifier(struct notifier_block *nb, 330static int pseries_smp_notifier(struct notifier_block *nb,
331 unsigned long action, void *node) 331 unsigned long action, void *node)
332{ 332{
333 int err = NOTIFY_OK; 333 int err = 0;
334 334
335 switch (action) { 335 switch (action) {
336 case PSERIES_RECONFIG_ADD: 336 case PSERIES_RECONFIG_ADD:
337 if (pseries_add_processor(node)) 337 err = pseries_add_processor(node);
338 err = NOTIFY_BAD;
339 break; 338 break;
340 case PSERIES_RECONFIG_REMOVE: 339 case PSERIES_RECONFIG_REMOVE:
341 pseries_remove_processor(node); 340 pseries_remove_processor(node);
342 break; 341 break;
343 default:
344 err = NOTIFY_DONE;
345 break;
346 } 342 }
347 return err; 343 return notifier_from_errno(err);
348} 344}
349 345
350static struct notifier_block pseries_smp_nb = { 346static struct notifier_block pseries_smp_nb = {
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 9d6a8effeda2..11d8e0544ac0 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -205,27 +205,21 @@ static int pseries_drconf_memory(unsigned long *base, unsigned int action)
205static int pseries_memory_notifier(struct notifier_block *nb, 205static int pseries_memory_notifier(struct notifier_block *nb,
206 unsigned long action, void *node) 206 unsigned long action, void *node)
207{ 207{
208 int err = NOTIFY_OK; 208 int err = 0;
209 209
210 switch (action) { 210 switch (action) {
211 case PSERIES_RECONFIG_ADD: 211 case PSERIES_RECONFIG_ADD:
212 if (pseries_add_memory(node)) 212 err = pseries_add_memory(node);
213 err = NOTIFY_BAD;
214 break; 213 break;
215 case PSERIES_RECONFIG_REMOVE: 214 case PSERIES_RECONFIG_REMOVE:
216 if (pseries_remove_memory(node)) 215 err = pseries_remove_memory(node);
217 err = NOTIFY_BAD;
218 break; 216 break;
219 case PSERIES_DRCONF_MEM_ADD: 217 case PSERIES_DRCONF_MEM_ADD:
220 case PSERIES_DRCONF_MEM_REMOVE: 218 case PSERIES_DRCONF_MEM_REMOVE:
221 if (pseries_drconf_memory(node, action)) 219 err = pseries_drconf_memory(node, action);
222 err = NOTIFY_BAD;
223 break;
224 default:
225 err = NOTIFY_DONE;
226 break; 220 break;
227 } 221 }
228 return err; 222 return notifier_from_errno(err);
229} 223}
230 224
231static struct notifier_block pseries_mem_nb = { 225static struct notifier_block pseries_mem_nb = {
diff --git a/arch/powerpc/platforms/pseries/hvconsole.c b/arch/powerpc/platforms/pseries/hvconsole.c
index 3f6a89b09816..041e87ca1893 100644
--- a/arch/powerpc/platforms/pseries/hvconsole.c
+++ b/arch/powerpc/platforms/pseries/hvconsole.c
@@ -73,7 +73,7 @@ int hvc_put_chars(uint32_t vtermno, const char *buf, int count)
73 if (ret == H_SUCCESS) 73 if (ret == H_SUCCESS)
74 return count; 74 return count;
75 if (ret == H_BUSY) 75 if (ret == H_BUSY)
76 return 0; 76 return -EAGAIN;
77 return -EIO; 77 return -EIO;
78} 78}
79 79
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 39e6e0a7b2fa..f7205d344efd 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -52,197 +52,6 @@ EXPORT_SYMBOL(plpar_hcall_norets);
52 52
53extern void pSeries_find_serial_port(void); 53extern void pSeries_find_serial_port(void);
54 54
55
56static int vtermno; /* virtual terminal# for udbg */
57
58#define __ALIGNED__ __attribute__((__aligned__(sizeof(long))))
59static void udbg_hvsi_putc(char c)
60{
61 /* packet's seqno isn't used anyways */
62 uint8_t packet[] __ALIGNED__ = { 0xff, 5, 0, 0, c };
63 int rc;
64
65 if (c == '\n')
66 udbg_hvsi_putc('\r');
67
68 do {
69 rc = plpar_put_term_char(vtermno, sizeof(packet), packet);
70 } while (rc == H_BUSY);
71}
72
73static long hvsi_udbg_buf_len;
74static uint8_t hvsi_udbg_buf[256];
75
76static int udbg_hvsi_getc_poll(void)
77{
78 unsigned char ch;
79 int rc, i;
80
81 if (hvsi_udbg_buf_len == 0) {
82 rc = plpar_get_term_char(vtermno, &hvsi_udbg_buf_len, hvsi_udbg_buf);
83 if (rc != H_SUCCESS || hvsi_udbg_buf[0] != 0xff) {
84 /* bad read or non-data packet */
85 hvsi_udbg_buf_len = 0;
86 } else {
87 /* remove the packet header */
88 for (i = 4; i < hvsi_udbg_buf_len; i++)
89 hvsi_udbg_buf[i-4] = hvsi_udbg_buf[i];
90 hvsi_udbg_buf_len -= 4;
91 }
92 }
93
94 if (hvsi_udbg_buf_len <= 0 || hvsi_udbg_buf_len > 256) {
95 /* no data ready */
96 hvsi_udbg_buf_len = 0;
97 return -1;
98 }
99
100 ch = hvsi_udbg_buf[0];
101 /* shift remaining data down */
102 for (i = 1; i < hvsi_udbg_buf_len; i++) {
103 hvsi_udbg_buf[i-1] = hvsi_udbg_buf[i];
104 }
105 hvsi_udbg_buf_len--;
106
107 return ch;
108}
109
110static int udbg_hvsi_getc(void)
111{
112 int ch;
113 for (;;) {
114 ch = udbg_hvsi_getc_poll();
115 if (ch == -1) {
116 /* This shouldn't be needed...but... */
117 volatile unsigned long delay;
118 for (delay=0; delay < 2000000; delay++)
119 ;
120 } else {
121 return ch;
122 }
123 }
124}
125
126static void udbg_putcLP(char c)
127{
128 char buf[16];
129 unsigned long rc;
130
131 if (c == '\n')
132 udbg_putcLP('\r');
133
134 buf[0] = c;
135 do {
136 rc = plpar_put_term_char(vtermno, 1, buf);
137 } while(rc == H_BUSY);
138}
139
140/* Buffered chars getc */
141static long inbuflen;
142static long inbuf[2]; /* must be 2 longs */
143
144static int udbg_getc_pollLP(void)
145{
146 /* The interface is tricky because it may return up to 16 chars.
147 * We save them statically for future calls to udbg_getc().
148 */
149 char ch, *buf = (char *)inbuf;
150 int i;
151 long rc;
152 if (inbuflen == 0) {
153 /* get some more chars. */
154 inbuflen = 0;
155 rc = plpar_get_term_char(vtermno, &inbuflen, buf);
156 if (rc != H_SUCCESS)
157 inbuflen = 0; /* otherwise inbuflen is garbage */
158 }
159 if (inbuflen <= 0 || inbuflen > 16) {
160 /* Catch error case as well as other oddities (corruption) */
161 inbuflen = 0;
162 return -1;
163 }
164 ch = buf[0];
165 for (i = 1; i < inbuflen; i++) /* shuffle them down. */
166 buf[i-1] = buf[i];
167 inbuflen--;
168 return ch;
169}
170
171static int udbg_getcLP(void)
172{
173 int ch;
174 for (;;) {
175 ch = udbg_getc_pollLP();
176 if (ch == -1) {
177 /* This shouldn't be needed...but... */
178 volatile unsigned long delay;
179 for (delay=0; delay < 2000000; delay++)
180 ;
181 } else {
182 return ch;
183 }
184 }
185}
186
187/* call this from early_init() for a working debug console on
188 * vterm capable LPAR machines
189 */
190void __init udbg_init_debug_lpar(void)
191{
192 vtermno = 0;
193 udbg_putc = udbg_putcLP;
194 udbg_getc = udbg_getcLP;
195 udbg_getc_poll = udbg_getc_pollLP;
196
197 register_early_udbg_console();
198}
199
200/* returns 0 if couldn't find or use /chosen/stdout as console */
201void __init find_udbg_vterm(void)
202{
203 struct device_node *stdout_node;
204 const u32 *termno;
205 const char *name;
206
207 /* find the boot console from /chosen/stdout */
208 if (!of_chosen)
209 return;
210 name = of_get_property(of_chosen, "linux,stdout-path", NULL);
211 if (name == NULL)
212 return;
213 stdout_node = of_find_node_by_path(name);
214 if (!stdout_node)
215 return;
216 name = of_get_property(stdout_node, "name", NULL);
217 if (!name) {
218 printk(KERN_WARNING "stdout node missing 'name' property!\n");
219 goto out;
220 }
221
222 /* Check if it's a virtual terminal */
223 if (strncmp(name, "vty", 3) != 0)
224 goto out;
225 termno = of_get_property(stdout_node, "reg", NULL);
226 if (termno == NULL)
227 goto out;
228 vtermno = termno[0];
229
230 if (of_device_is_compatible(stdout_node, "hvterm1")) {
231 udbg_putc = udbg_putcLP;
232 udbg_getc = udbg_getcLP;
233 udbg_getc_poll = udbg_getc_pollLP;
234 add_preferred_console("hvc", termno[0] & 0xff, NULL);
235 } else if (of_device_is_compatible(stdout_node, "hvterm-protocol")) {
236 vtermno = termno[0];
237 udbg_putc = udbg_hvsi_putc;
238 udbg_getc = udbg_hvsi_getc;
239 udbg_getc_poll = udbg_hvsi_getc_poll;
240 add_preferred_console("hvsi", termno[0] & 0xff, NULL);
241 }
242out:
243 of_node_put(stdout_node);
244}
245
246void vpa_init(int cpu) 55void vpa_init(int cpu)
247{ 56{
248 int hwcpu = get_hard_smp_processor_id(cpu); 57 int hwcpu = get_hard_smp_processor_id(cpu);
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index e9f6d2859c3c..24c7162f11d9 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -47,7 +47,8 @@ extern void pSeries_final_fixup(void);
47/* Poweron flag used for enabling auto ups restart */ 47/* Poweron flag used for enabling auto ups restart */
48extern unsigned long rtas_poweron_auto; 48extern unsigned long rtas_poweron_auto;
49 49
50extern void find_udbg_vterm(void); 50/* Provided by HVC VIO */
51extern void hvc_vio_init_early(void);
51 52
52/* Dynamic logical Partitioning/Mobility */ 53/* Dynamic logical Partitioning/Mobility */
53extern void dlpar_free_cc_nodes(struct device_node *); 54extern void dlpar_free_cc_nodes(struct device_node *);
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 1de2cbb92303..168651acdd83 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -97,7 +97,7 @@ static struct device_node *derive_parent(const char *path)
97 return parent; 97 return parent;
98} 98}
99 99
100BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain); 100static BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain);
101 101
102int pSeries_reconfig_notifier_register(struct notifier_block *nb) 102int pSeries_reconfig_notifier_register(struct notifier_block *nb)
103{ 103{
@@ -109,6 +109,14 @@ void pSeries_reconfig_notifier_unregister(struct notifier_block *nb)
109 blocking_notifier_chain_unregister(&pSeries_reconfig_chain, nb); 109 blocking_notifier_chain_unregister(&pSeries_reconfig_chain, nb);
110} 110}
111 111
112int pSeries_reconfig_notify(unsigned long action, void *p)
113{
114 int err = blocking_notifier_call_chain(&pSeries_reconfig_chain,
115 action, p);
116
117 return notifier_to_errno(err);
118}
119
112static int pSeries_reconfig_add_node(const char *path, struct property *proplist) 120static int pSeries_reconfig_add_node(const char *path, struct property *proplist)
113{ 121{
114 struct device_node *np; 122 struct device_node *np;
@@ -132,11 +140,9 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist
132 goto out_err; 140 goto out_err;
133 } 141 }
134 142
135 err = blocking_notifier_call_chain(&pSeries_reconfig_chain, 143 err = pSeries_reconfig_notify(PSERIES_RECONFIG_ADD, np);
136 PSERIES_RECONFIG_ADD, np); 144 if (err) {
137 if (err == NOTIFY_BAD) {
138 printk(KERN_ERR "Failed to add device node %s\n", path); 145 printk(KERN_ERR "Failed to add device node %s\n", path);
139 err = -ENOMEM; /* For now, safe to assume kmalloc failure */
140 goto out_err; 146 goto out_err;
141 } 147 }
142 148
@@ -173,8 +179,7 @@ static int pSeries_reconfig_remove_node(struct device_node *np)
173 179
174 remove_node_proc_entries(np); 180 remove_node_proc_entries(np);
175 181
176 blocking_notifier_call_chain(&pSeries_reconfig_chain, 182 pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, np);
177 PSERIES_RECONFIG_REMOVE, np);
178 of_detach_node(np); 183 of_detach_node(np);
179 184
180 of_node_put(parent); 185 of_node_put(parent);
@@ -472,11 +477,10 @@ static int do_update_property(char *buf, size_t bufsize)
472 else 477 else
473 action = PSERIES_DRCONF_MEM_REMOVE; 478 action = PSERIES_DRCONF_MEM_REMOVE;
474 479
475 rc = blocking_notifier_call_chain(&pSeries_reconfig_chain, 480 rc = pSeries_reconfig_notify(action, value);
476 action, value); 481 if (rc) {
477 if (rc == NOTIFY_BAD) { 482 prom_update_property(np, oldprop, newprop);
478 rc = prom_update_property(np, oldprop, newprop); 483 return rc;
479 return -ENOMEM;
480 } 484 }
481 } 485 }
482 486
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 593acceeff96..d00e52926b71 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -512,9 +512,10 @@ static void __init pSeries_init_early(void)
512{ 512{
513 pr_debug(" -> pSeries_init_early()\n"); 513 pr_debug(" -> pSeries_init_early()\n");
514 514
515#ifdef CONFIG_HVC_CONSOLE
515 if (firmware_has_feature(FW_FEATURE_LPAR)) 516 if (firmware_has_feature(FW_FEATURE_LPAR))
516 find_udbg_vterm(); 517 hvc_vio_init_early();
517 518#endif
518 if (firmware_has_feature(FW_FEATURE_DABR)) 519 if (firmware_has_feature(FW_FEATURE_DABR))
519 ppc_md.set_dabr = pseries_set_dabr; 520 ppc_md.set_dabr = pseries_set_dabr;
520 else if (firmware_has_feature(FW_FEATURE_XDABR)) 521 else if (firmware_has_feature(FW_FEATURE_XDABR))
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index cd70be5ff27e..1672db2d1b0e 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -206,7 +206,7 @@ static struct smp_ops_t pSeries_mpic_smp_ops = {
206}; 206};
207 207
208static struct smp_ops_t pSeries_xics_smp_ops = { 208static struct smp_ops_t pSeries_xics_smp_ops = {
209 .message_pass = smp_muxed_ipi_message_pass, 209 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
210 .cause_ipi = NULL, /* Filled at runtime by xics_smp_probe() */ 210 .cause_ipi = NULL, /* Filled at runtime by xics_smp_probe() */
211 .probe = xics_smp_probe, 211 .probe = xics_smp_probe,
212 .kick_cpu = smp_pSeries_kick_cpu, 212 .kick_cpu = smp_pSeries_kick_cpu,
diff --git a/arch/powerpc/platforms/wsp/smp.c b/arch/powerpc/platforms/wsp/smp.c
index 9d20fa9d3710..71bd105f3863 100644
--- a/arch/powerpc/platforms/wsp/smp.c
+++ b/arch/powerpc/platforms/wsp/smp.c
@@ -75,7 +75,7 @@ static int __init smp_a2_probe(void)
75} 75}
76 76
77static struct smp_ops_t a2_smp_ops = { 77static struct smp_ops_t a2_smp_ops = {
78 .message_pass = smp_muxed_ipi_message_pass, 78 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
79 .cause_ipi = doorbell_cause_ipi, 79 .cause_ipi = doorbell_cause_ipi,
80 .probe = smp_a2_probe, 80 .probe = smp_a2_probe,
81 .kick_cpu = smp_a2_kick_cpu, 81 .kick_cpu = smp_a2_kick_cpu,
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 0efa990e3344..cf736ca0cf05 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
4 4
5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o 5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) 6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
7obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
7fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o 8fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
8obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o 9obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
9 10
diff --git a/arch/powerpc/sysdev/ehv_pic.c b/arch/powerpc/sysdev/ehv_pic.c
new file mode 100644
index 000000000000..af1a5df46b3e
--- /dev/null
+++ b/arch/powerpc/sysdev/ehv_pic.c
@@ -0,0 +1,302 @@
1/*
2 * Driver for ePAPR Embedded Hypervisor PIC
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/smp.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/of.h>
22
23#include <asm/io.h>
24#include <asm/irq.h>
25#include <asm/smp.h>
26#include <asm/machdep.h>
27#include <asm/ehv_pic.h>
28#include <asm/fsl_hcalls.h>
29
30#include "../../../kernel/irq/settings.h"
31
32static struct ehv_pic *global_ehv_pic;
33static DEFINE_SPINLOCK(ehv_pic_lock);
34
35static u32 hwirq_intspec[NR_EHV_PIC_INTS];
36static u32 __iomem *mpic_percpu_base_vaddr;
37
38#define IRQ_TYPE_MPIC_DIRECT 4
39#define MPIC_EOI 0x00B0
40
41/*
42 * Linux descriptor level callbacks
43 */
44
45void ehv_pic_unmask_irq(struct irq_data *d)
46{
47 unsigned int src = virq_to_hw(d->irq);
48
49 ev_int_set_mask(src, 0);
50}
51
52void ehv_pic_mask_irq(struct irq_data *d)
53{
54 unsigned int src = virq_to_hw(d->irq);
55
56 ev_int_set_mask(src, 1);
57}
58
59void ehv_pic_end_irq(struct irq_data *d)
60{
61 unsigned int src = virq_to_hw(d->irq);
62
63 ev_int_eoi(src);
64}
65
66void ehv_pic_direct_end_irq(struct irq_data *d)
67{
68 out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
69}
70
71int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
72 bool force)
73{
74 unsigned int src = virq_to_hw(d->irq);
75 unsigned int config, prio, cpu_dest;
76 int cpuid = irq_choose_cpu(dest);
77 unsigned long flags;
78
79 spin_lock_irqsave(&ehv_pic_lock, flags);
80 ev_int_get_config(src, &config, &prio, &cpu_dest);
81 ev_int_set_config(src, config, prio, cpuid);
82 spin_unlock_irqrestore(&ehv_pic_lock, flags);
83
84 return 0;
85}
86
87static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
88{
89 /* Now convert sense value */
90
91 switch (type & IRQ_TYPE_SENSE_MASK) {
92 case IRQ_TYPE_EDGE_RISING:
93 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
94 EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
95
96 case IRQ_TYPE_EDGE_FALLING:
97 case IRQ_TYPE_EDGE_BOTH:
98 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
99 EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
100
101 case IRQ_TYPE_LEVEL_HIGH:
102 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
103 EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
104
105 case IRQ_TYPE_LEVEL_LOW:
106 default:
107 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
108 EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
109 }
110}
111
112int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
113{
114 unsigned int src = virq_to_hw(d->irq);
115 struct irq_desc *desc = irq_to_desc(d->irq);
116 unsigned int vecpri, vold, vnew, prio, cpu_dest;
117 unsigned long flags;
118
119 if (flow_type == IRQ_TYPE_NONE)
120 flow_type = IRQ_TYPE_LEVEL_LOW;
121
122 irq_settings_clr_level(desc);
123 irq_settings_set_trigger_mask(desc, flow_type);
124 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
125 irq_settings_set_level(desc);
126
127 vecpri = ehv_pic_type_to_vecpri(flow_type);
128
129 spin_lock_irqsave(&ehv_pic_lock, flags);
130 ev_int_get_config(src, &vold, &prio, &cpu_dest);
131 vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
132 EHV_PIC_INFO(VECPRI_SENSE_MASK));
133 vnew |= vecpri;
134
135 /*
136 * TODO : Add specific interface call for platform to set
137 * individual interrupt priorities.
138 * platform currently using static/default priority for all ints
139 */
140
141 prio = 8;
142
143 ev_int_set_config(src, vecpri, prio, cpu_dest);
144
145 spin_unlock_irqrestore(&ehv_pic_lock, flags);
146 return 0;
147}
148
149static struct irq_chip ehv_pic_irq_chip = {
150 .irq_mask = ehv_pic_mask_irq,
151 .irq_unmask = ehv_pic_unmask_irq,
152 .irq_eoi = ehv_pic_end_irq,
153 .irq_set_type = ehv_pic_set_irq_type,
154};
155
156static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
157 .irq_mask = ehv_pic_mask_irq,
158 .irq_unmask = ehv_pic_unmask_irq,
159 .irq_eoi = ehv_pic_direct_end_irq,
160 .irq_set_type = ehv_pic_set_irq_type,
161};
162
163/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
164unsigned int ehv_pic_get_irq(void)
165{
166 int irq;
167
168 BUG_ON(global_ehv_pic == NULL);
169
170 if (global_ehv_pic->coreint_flag)
171 irq = mfspr(SPRN_EPR); /* if core int mode */
172 else
173 ev_int_iack(0, &irq); /* legacy mode */
174
175 if (irq == 0xFFFF) /* 0xFFFF --> no irq is pending */
176 return NO_IRQ;
177
178 /*
179 * this will also setup revmap[] in the slow path for the first
180 * time, next calls will always use fast path by indexing revmap
181 */
182 return irq_linear_revmap(global_ehv_pic->irqhost, irq);
183}
184
185static int ehv_pic_host_match(struct irq_host *h, struct device_node *node)
186{
187 /* Exact match, unless ehv_pic node is NULL */
188 return h->of_node == NULL || h->of_node == node;
189}
190
191static int ehv_pic_host_map(struct irq_host *h, unsigned int virq,
192 irq_hw_number_t hw)
193{
194 struct ehv_pic *ehv_pic = h->host_data;
195 struct irq_chip *chip;
196
197 /* Default chip */
198 chip = &ehv_pic->hc_irq;
199
200 if (mpic_percpu_base_vaddr)
201 if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
202 chip = &ehv_pic_direct_eoi_irq_chip;
203
204 irq_set_chip_data(virq, chip);
205 /*
206 * using handle_fasteoi_irq as our irq handler, this will
207 * only call the eoi callback and suitable for the MPIC
208 * controller which set ISR/IPR automatically and clear the
209 * highest priority active interrupt in ISR/IPR when we do
210 * a specific eoi
211 */
212 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
213
214 /* Set default irq type */
215 irq_set_irq_type(virq, IRQ_TYPE_NONE);
216
217 return 0;
218}
219
220static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct,
221 const u32 *intspec, unsigned int intsize,
222 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
223
224{
225 /*
226 * interrupt sense values coming from the guest device tree
227 * interrupt specifiers can have four possible sense and
228 * level encoding information and they need to
229 * be translated between firmware type & linux type.
230 */
231
232 static unsigned char map_of_senses_to_linux_irqtype[4] = {
233 IRQ_TYPE_EDGE_FALLING,
234 IRQ_TYPE_EDGE_RISING,
235 IRQ_TYPE_LEVEL_LOW,
236 IRQ_TYPE_LEVEL_HIGH,
237 };
238
239 *out_hwirq = intspec[0];
240 if (intsize > 1) {
241 hwirq_intspec[intspec[0]] = intspec[1];
242 *out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
243 ~IRQ_TYPE_MPIC_DIRECT];
244 } else {
245 *out_flags = IRQ_TYPE_NONE;
246 }
247
248 return 0;
249}
250
251static struct irq_host_ops ehv_pic_host_ops = {
252 .match = ehv_pic_host_match,
253 .map = ehv_pic_host_map,
254 .xlate = ehv_pic_host_xlate,
255};
256
257void __init ehv_pic_init(void)
258{
259 struct device_node *np, *np2;
260 struct ehv_pic *ehv_pic;
261 int coreint_flag = 1;
262
263 np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
264 if (!np) {
265 pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
266 return;
267 }
268
269 if (!of_find_property(np, "has-external-proxy", NULL))
270 coreint_flag = 0;
271
272 ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
273 if (!ehv_pic) {
274 of_node_put(np);
275 return;
276 }
277
278 ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
279 NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0);
280
281 if (!ehv_pic->irqhost) {
282 of_node_put(np);
283 return;
284 }
285
286 np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
287 if (np2) {
288 mpic_percpu_base_vaddr = of_iomap(np2, 0);
289 if (!mpic_percpu_base_vaddr)
290 pr_err("ehv_pic_init: of_iomap failed\n");
291
292 of_node_put(np2);
293 }
294
295 ehv_pic->irqhost->host_data = ehv_pic;
296 ehv_pic->hc_irq = ehv_pic_irq_chip;
297 ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
298 ehv_pic->coreint_flag = coreint_flag;
299
300 global_ehv_pic = ehv_pic;
301 irq_set_default_host(global_ehv_pic->irqhost);
302}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ba5cb3fa7074..3bba8bdb58b0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -38,10 +38,17 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{ 40{
41 u8 progif;
42
41 /* if we aren't a PCIe don't bother */ 43 /* if we aren't a PCIe don't bother */
42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
43 return; 45 return;
44 46
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
45 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
46 fsl_pcie_bus_fixup = 1; 53 fsl_pcie_bus_fixup = 1;
47 return; 54 return;
@@ -323,6 +330,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
323 struct pci_controller *hose; 330 struct pci_controller *hose;
324 struct resource rsrc; 331 struct resource rsrc;
325 const int *bus_range; 332 const int *bus_range;
333 u8 progif;
326 334
327 if (!of_device_is_available(dev)) { 335 if (!of_device_is_available(dev)) {
328 pr_warning("%s: disabled\n", dev->full_name); 336 pr_warning("%s: disabled\n", dev->full_name);
@@ -353,6 +361,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
353 361
354 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 362 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
355 PPC_INDIRECT_TYPE_BIG_ENDIAN); 363 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364
365 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366 if ((progif & 1) == 1) {
367 /* unmap cfg_data & cfg_addr separately if not on same page */
368 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369 ((unsigned long)hose->cfg_addr & PAGE_MASK))
370 iounmap(hose->cfg_data);
371 iounmap(hose->cfg_addr);
372 pcibios_free_controller(hose);
373 return 0;
374 }
375
356 setup_pci_cmd(hose); 376 setup_pci_cmd(hose);
357 377
358 /* check PCI express link status */ 378 /* check PCI express link status */
@@ -380,70 +400,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
380 400
381 return 0; 401 return 0;
382} 402}
383
384DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
385DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
386DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
387DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
388DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
389DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
390DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
391DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
392DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
393DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
394DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
395DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
396DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
397DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
398DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
399DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
400DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
401DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
402DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
403DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
404DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
405DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
406DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
414DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
415DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
416DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
417DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
418DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
419DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
420DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
421DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
422DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
423DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
424DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
425DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
426DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
427DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
428DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
429DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
430DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
431DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
432DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
433DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
434#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 403#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
435 404
436#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 405DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
437DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
438DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
439DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
440DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
441DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
442DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
443DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
444DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
445DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
446 406
407#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
447struct mpc83xx_pcie_priv { 408struct mpc83xx_pcie_priv {
448 void __iomem *cfg_type0; 409 void __iomem *cfg_type0;
449 void __iomem *cfg_type1; 410 void __iomem *cfg_type1;
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 19e5015e039b..265313e8396b 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -41,6 +41,7 @@
41#include <sysdev/fsl_soc.h> 41#include <sysdev/fsl_soc.h>
42#include <mm/mmu_decl.h> 42#include <mm/mmu_decl.h>
43#include <asm/cpm2.h> 43#include <asm/cpm2.h>
44#include <asm/fsl_hcalls.h> /* For the Freescale hypervisor */
44 45
45extern void init_fcc_ioports(struct fs_platform_info*); 46extern void init_fcc_ioports(struct fs_platform_info*);
46extern void init_fec_ioports(struct fs_platform_info*); 47extern void init_fec_ioports(struct fs_platform_info*);
@@ -252,3 +253,29 @@ void fsl_rstcr_restart(char *cmd)
252struct platform_diu_data_ops diu_ops; 253struct platform_diu_data_ops diu_ops;
253EXPORT_SYMBOL(diu_ops); 254EXPORT_SYMBOL(diu_ops);
254#endif 255#endif
256
257/*
258 * Restart the current partition
259 *
260 * This function should be assigned to the ppc_md.restart function pointer,
261 * to initiate a partition restart when we're running under the Freescale
262 * hypervisor.
263 */
264void fsl_hv_restart(char *cmd)
265{
266 pr_info("hv restart\n");
267 fh_partition_restart(-1);
268}
269
270/*
271 * Halt the current partition
272 *
273 * This function should be assigned to the ppc_md.power_off and ppc_md.halt
274 * function pointers, to shut down the partition when we're running under
275 * the Freescale hypervisor.
276 */
277void fsl_hv_halt(void)
278{
279 pr_info("hv exit\n");
280 fh_partition_stop(-1);
281}
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 53609489a62b..2ece02beb8ff 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -36,5 +36,8 @@ struct platform_diu_data_ops {
36extern struct platform_diu_data_ops diu_ops; 36extern struct platform_diu_data_ops diu_ops;
37#endif 37#endif
38 38
39void fsl_hv_restart(char *cmd);
40void fsl_hv_halt(void);
41
39#endif 42#endif
40#endif 43#endif
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 58d7a534f877..d5d3ff3d757e 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -598,42 +598,6 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
598 598
599#endif /* CONFIG_MPIC_U3_HT_IRQS */ 599#endif /* CONFIG_MPIC_U3_HT_IRQS */
600 600
601#ifdef CONFIG_SMP
602static int irq_choose_cpu(const struct cpumask *mask)
603{
604 int cpuid;
605
606 if (cpumask_equal(mask, cpu_all_mask)) {
607 static int irq_rover = 0;
608 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
609 unsigned long flags;
610
611 /* Round-robin distribution... */
612 do_round_robin:
613 raw_spin_lock_irqsave(&irq_rover_lock, flags);
614
615 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
616 if (irq_rover >= nr_cpu_ids)
617 irq_rover = cpumask_first(cpu_online_mask);
618
619 cpuid = irq_rover;
620
621 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
622 } else {
623 cpuid = cpumask_first_and(mask, cpu_online_mask);
624 if (cpuid >= nr_cpu_ids)
625 goto do_round_robin;
626 }
627
628 return get_hard_smp_processor_id(cpuid);
629}
630#else
631static int irq_choose_cpu(const struct cpumask *mask)
632{
633 return hard_smp_processor_id();
634}
635#endif
636
637/* Find an mpic associated with a given linux interrupt */ 601/* Find an mpic associated with a given linux interrupt */
638static struct mpic *mpic_find(unsigned int irq) 602static struct mpic *mpic_find(unsigned int irq)
639{ 603{
@@ -849,7 +813,7 @@ static void mpic_unmask_tm(struct irq_data *d)
849 struct mpic *mpic = mpic_from_irq_data(d); 813 struct mpic *mpic = mpic_from_irq_data(d);
850 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 814 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
851 815
852 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src); 816 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
853 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); 817 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
854 mpic_tm_read(src); 818 mpic_tm_read(src);
855} 819}
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index deda60a7f996..2ec4f3bb8160 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -650,12 +650,74 @@ struct ppc4xx_pciex_hwops
650 int (*core_init)(struct device_node *np); 650 int (*core_init)(struct device_node *np);
651 int (*port_init_hw)(struct ppc4xx_pciex_port *port); 651 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
652 int (*setup_utl)(struct ppc4xx_pciex_port *port); 652 int (*setup_utl)(struct ppc4xx_pciex_port *port);
653 void (*check_link)(struct ppc4xx_pciex_port *port);
653}; 654};
654 655
655static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; 656static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
656 657
657#ifdef CONFIG_44x 658#ifdef CONFIG_44x
658 659
660static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
661 unsigned int sdr_offset,
662 unsigned int mask,
663 unsigned int value,
664 int timeout_ms)
665{
666 u32 val;
667
668 while(timeout_ms--) {
669 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
670 if ((val & mask) == value) {
671 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
672 port->index, sdr_offset, timeout_ms, val);
673 return 0;
674 }
675 msleep(1);
676 }
677 return -1;
678}
679
680static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
681{
682 /* Wait for reset to complete */
683 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
684 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
685 port->index);
686 return -1;
687 }
688 return 0;
689}
690
691static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
692{
693 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
694
695 /* Check for card presence detect if supported, if not, just wait for
696 * link unconditionally.
697 *
698 * note that we don't fail if there is no link, we just filter out
699 * config space accesses. That way, it will be easier to implement
700 * hotplug later on.
701 */
702 if (!port->has_ibpre ||
703 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
704 1 << 28, 1 << 28, 100)) {
705 printk(KERN_INFO
706 "PCIE%d: Device detected, waiting for link...\n",
707 port->index);
708 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
709 0x1000, 0x1000, 2000))
710 printk(KERN_WARNING
711 "PCIE%d: Link up failed\n", port->index);
712 else {
713 printk(KERN_INFO
714 "PCIE%d: link is up !\n", port->index);
715 port->link = 1;
716 }
717 } else
718 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
719}
720
659/* Check various reset bits of the 440SPe PCIe core */ 721/* Check various reset bits of the 440SPe PCIe core */
660static int __init ppc440spe_pciex_check_reset(struct device_node *np) 722static int __init ppc440spe_pciex_check_reset(struct device_node *np)
661{ 723{
@@ -806,7 +868,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
806 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 868 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
807 (1 << 24) | (1 << 16), 1 << 12); 869 (1 << 24) | (1 << 16), 1 << 12);
808 870
809 return 0; 871 return ppc4xx_pciex_port_reset_sdr(port);
810} 872}
811 873
812static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 874static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
@@ -856,6 +918,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
856 .core_init = ppc440spe_pciex_core_init, 918 .core_init = ppc440spe_pciex_core_init,
857 .port_init_hw = ppc440speA_pciex_init_port_hw, 919 .port_init_hw = ppc440speA_pciex_init_port_hw,
858 .setup_utl = ppc440speA_pciex_init_utl, 920 .setup_utl = ppc440speA_pciex_init_utl,
921 .check_link = ppc4xx_pciex_check_link_sdr,
859}; 922};
860 923
861static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 924static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
@@ -863,6 +926,7 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
863 .core_init = ppc440spe_pciex_core_init, 926 .core_init = ppc440spe_pciex_core_init,
864 .port_init_hw = ppc440speB_pciex_init_port_hw, 927 .port_init_hw = ppc440speB_pciex_init_port_hw,
865 .setup_utl = ppc440speB_pciex_init_utl, 928 .setup_utl = ppc440speB_pciex_init_utl,
929 .check_link = ppc4xx_pciex_check_link_sdr,
866}; 930};
867 931
868static int __init ppc460ex_pciex_core_init(struct device_node *np) 932static int __init ppc460ex_pciex_core_init(struct device_node *np)
@@ -944,7 +1008,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
944 1008
945 port->has_ibpre = 1; 1009 port->has_ibpre = 1;
946 1010
947 return 0; 1011 return ppc4xx_pciex_port_reset_sdr(port);
948} 1012}
949 1013
950static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1014static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -972,6 +1036,7 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
972 .core_init = ppc460ex_pciex_core_init, 1036 .core_init = ppc460ex_pciex_core_init,
973 .port_init_hw = ppc460ex_pciex_init_port_hw, 1037 .port_init_hw = ppc460ex_pciex_init_port_hw,
974 .setup_utl = ppc460ex_pciex_init_utl, 1038 .setup_utl = ppc460ex_pciex_init_utl,
1039 .check_link = ppc4xx_pciex_check_link_sdr,
975}; 1040};
976 1041
977static int __init ppc460sx_pciex_core_init(struct device_node *np) 1042static int __init ppc460sx_pciex_core_init(struct device_node *np)
@@ -1075,7 +1140,7 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1075 1140
1076 port->has_ibpre = 1; 1141 port->has_ibpre = 1;
1077 1142
1078 return 0; 1143 return ppc4xx_pciex_port_reset_sdr(port);
1079} 1144}
1080 1145
1081static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) 1146static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1089,6 +1154,7 @@ static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1089 .core_init = ppc460sx_pciex_core_init, 1154 .core_init = ppc460sx_pciex_core_init,
1090 .port_init_hw = ppc460sx_pciex_init_port_hw, 1155 .port_init_hw = ppc460sx_pciex_init_port_hw,
1091 .setup_utl = ppc460sx_pciex_init_utl, 1156 .setup_utl = ppc460sx_pciex_init_utl,
1157 .check_link = ppc4xx_pciex_check_link_sdr,
1092}; 1158};
1093 1159
1094#endif /* CONFIG_44x */ 1160#endif /* CONFIG_44x */
@@ -1154,7 +1220,7 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1154 1220
1155 port->has_ibpre = 1; 1221 port->has_ibpre = 1;
1156 1222
1157 return 0; 1223 return ppc4xx_pciex_port_reset_sdr(port);
1158} 1224}
1159 1225
1160static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1226static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1183,11 +1249,11 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1183 .core_init = ppc405ex_pciex_core_init, 1249 .core_init = ppc405ex_pciex_core_init,
1184 .port_init_hw = ppc405ex_pciex_init_port_hw, 1250 .port_init_hw = ppc405ex_pciex_init_port_hw,
1185 .setup_utl = ppc405ex_pciex_init_utl, 1251 .setup_utl = ppc405ex_pciex_init_utl,
1252 .check_link = ppc4xx_pciex_check_link_sdr,
1186}; 1253};
1187 1254
1188#endif /* CONFIG_40x */ 1255#endif /* CONFIG_40x */
1189 1256
1190
1191/* Check that the core has been initied and if not, do it */ 1257/* Check that the core has been initied and if not, do it */
1192static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 1258static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1193{ 1259{
@@ -1261,26 +1327,6 @@ static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port
1261 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); 1327 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1262} 1328}
1263 1329
1264static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1265 unsigned int sdr_offset,
1266 unsigned int mask,
1267 unsigned int value,
1268 int timeout_ms)
1269{
1270 u32 val;
1271
1272 while(timeout_ms--) {
1273 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1274 if ((val & mask) == value) {
1275 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1276 port->index, sdr_offset, timeout_ms, val);
1277 return 0;
1278 }
1279 msleep(1);
1280 }
1281 return -1;
1282}
1283
1284static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) 1330static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1285{ 1331{
1286 int rc = 0; 1332 int rc = 0;
@@ -1291,40 +1337,8 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1291 if (rc != 0) 1337 if (rc != 0)
1292 return rc; 1338 return rc;
1293 1339
1294 printk(KERN_INFO "PCIE%d: Checking link...\n", 1340 if (ppc4xx_pciex_hwops->check_link)
1295 port->index); 1341 ppc4xx_pciex_hwops->check_link(port);
1296
1297 /* Wait for reset to complete */
1298 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1299 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1300 port->index);
1301 return -1;
1302 }
1303
1304 /* Check for card presence detect if supported, if not, just wait for
1305 * link unconditionally.
1306 *
1307 * note that we don't fail if there is no link, we just filter out
1308 * config space accesses. That way, it will be easier to implement
1309 * hotplug later on.
1310 */
1311 if (!port->has_ibpre ||
1312 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1313 1 << 28, 1 << 28, 100)) {
1314 printk(KERN_INFO
1315 "PCIE%d: Device detected, waiting for link...\n",
1316 port->index);
1317 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1318 0x1000, 0x1000, 2000))
1319 printk(KERN_WARNING
1320 "PCIE%d: Link up failed\n", port->index);
1321 else {
1322 printk(KERN_INFO
1323 "PCIE%d: link is up !\n", port->index);
1324 port->link = 1;
1325 }
1326 } else
1327 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1328 1342
1329 /* 1343 /*
1330 * Initialize mapping: disable all regions and configure 1344 * Initialize mapping: disable all regions and configure
@@ -1347,14 +1361,17 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1347 /* 1361 /*
1348 * Check for VC0 active and assert RDY. 1362 * Check for VC0 active and assert RDY.
1349 */ 1363 */
1350 if (port->link && 1364 if (port->sdr_base) {
1351 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1365 if (port->link &&
1352 1 << 16, 1 << 16, 5000)) { 1366 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1353 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); 1367 1 << 16, 1 << 16, 5000)) {
1354 port->link = 0; 1368 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1369 port->link = 0;
1370 }
1371
1372 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1355 } 1373 }
1356 1374
1357 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1358 msleep(100); 1375 msleep(100);
1359 1376
1360 return 0; 1377 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 08:54:43 -0500