aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2008-12-17 07:07:48 -0500
committerIngo Molnar <mingo@elte.hu>2008-12-17 07:07:48 -0500
commit1f3f424a6bee9de4d839be9951f4296333fac014 (patch)
tree95de90dfdb4a9f64fe470709b82176243537c952 /arch/powerpc
parentc8cae544bba6aee0f5cb0756dbab1a71d2c68737 (diff)
parent1bda71282ded6a2e09a2db7c8884542fb46bfd4f (diff)
Merge branch 'linus' into cpus4096
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/kernel/misc_32.S3
-rw-r--r--arch/powerpc/mm/hugetlbpage.c3
-rw-r--r--arch/powerpc/mm/numa.c16
-rw-r--r--arch/powerpc/platforms/cell/axon_msi.c3
4 files changed, 20 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index bdc8b0e860e5..d108715129e2 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -479,6 +479,8 @@ _GLOBAL(_tlbil_pid)
479 * (no broadcast) 479 * (no broadcast)
480 */ 480 */
481_GLOBAL(_tlbil_va) 481_GLOBAL(_tlbil_va)
482 mfmsr r10
483 wrteei 0
482 slwi r4,r4,16 484 slwi r4,r4,16
483 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ 485 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
484 tlbsx 0,r3 486 tlbsx 0,r3
@@ -490,6 +492,7 @@ _GLOBAL(_tlbil_va)
490 tlbwe 492 tlbwe
491 msync 493 msync
492 isync 494 isync
495 wrtee r10
493 blr 496 blr
494#endif /* CONFIG_FSL_BOOKE */ 497#endif /* CONFIG_FSL_BOOKE */
495 498
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 7bbf4e4ed430..f0c3b88d50fa 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -507,6 +507,9 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
507{ 507{
508 struct hstate *hstate = hstate_file(file); 508 struct hstate *hstate = hstate_file(file);
509 int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate)); 509 int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
510
511 if (!mmu_huge_psizes[mmu_psize])
512 return -EINVAL;
510 return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0); 513 return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
511} 514}
512 515
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index a8397bbad3d4..cf81049e1e51 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -901,10 +901,17 @@ static void mark_reserved_regions_for_nid(int nid)
901 if (end_pfn > node_ar.end_pfn) 901 if (end_pfn > node_ar.end_pfn)
902 reserve_size = (node_ar.end_pfn << PAGE_SHIFT) 902 reserve_size = (node_ar.end_pfn << PAGE_SHIFT)
903 - (start_pfn << PAGE_SHIFT); 903 - (start_pfn << PAGE_SHIFT);
904 dbg("reserve_bootmem %lx %lx nid=%d\n", physbase, 904 /*
905 reserve_size, node_ar.nid); 905 * Only worry about *this* node, others may not
906 reserve_bootmem_node(NODE_DATA(node_ar.nid), physbase, 906 * yet have valid NODE_DATA().
907 reserve_size, BOOTMEM_DEFAULT); 907 */
908 if (node_ar.nid == nid) {
909 dbg("reserve_bootmem %lx %lx nid=%d\n",
910 physbase, reserve_size, node_ar.nid);
911 reserve_bootmem_node(NODE_DATA(node_ar.nid),
912 physbase, reserve_size,
913 BOOTMEM_DEFAULT);
914 }
908 /* 915 /*
909 * if reserved region is contained in the active region 916 * if reserved region is contained in the active region
910 * then done. 917 * then done.
@@ -929,7 +936,6 @@ static void mark_reserved_regions_for_nid(int nid)
929void __init do_init_bootmem(void) 936void __init do_init_bootmem(void)
930{ 937{
931 int nid; 938 int nid;
932 unsigned int i;
933 939
934 min_low_pfn = 0; 940 min_low_pfn = 0;
935 max_low_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT; 941 max_low_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index 442cf36aa172..0ce45c2b42f8 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -413,6 +413,9 @@ static int axon_msi_probe(struct of_device *device,
413 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE | 413 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
414 MSIC_CTRL_FIFO_SIZE); 414 MSIC_CTRL_FIFO_SIZE);
415 415
416 msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
417 & MSIC_FIFO_SIZE_MASK;
418
416 device->dev.platform_data = msic; 419 device->dev.platform_data = msic;
417 420
418 ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; 421 ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;