diff options
author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2009-06-02 13:22:16 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-06-02 15:45:33 -0400 |
commit | 0d48696f87e3618b0d35bd3e4e9d7c188d51e7de (patch) | |
tree | 633d37089c368c0cc2c4f8120014d57df215bb53 /arch/powerpc | |
parent | 08247e31ca79b8f02cce47b7e8120797a8726606 (diff) |
perf_counter: Rename perf_counter_hw_event => perf_counter_attr
The structure isn't hw only and when I read event, I think about those
things that fall out the other end. Rename the thing.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Kacur <jkacur@redhat.com>
Cc: Stephane Eranian <eranian@googlemail.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/kernel/perf_counter.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c index c9633321e7a5..ea54686cb787 100644 --- a/arch/powerpc/kernel/perf_counter.c +++ b/arch/powerpc/kernel/perf_counter.c | |||
@@ -262,13 +262,13 @@ static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[], | |||
262 | } | 262 | } |
263 | counter = ctrs[i]; | 263 | counter = ctrs[i]; |
264 | if (first) { | 264 | if (first) { |
265 | eu = counter->hw_event.exclude_user; | 265 | eu = counter->attr.exclude_user; |
266 | ek = counter->hw_event.exclude_kernel; | 266 | ek = counter->attr.exclude_kernel; |
267 | eh = counter->hw_event.exclude_hv; | 267 | eh = counter->attr.exclude_hv; |
268 | first = 0; | 268 | first = 0; |
269 | } else if (counter->hw_event.exclude_user != eu || | 269 | } else if (counter->attr.exclude_user != eu || |
270 | counter->hw_event.exclude_kernel != ek || | 270 | counter->attr.exclude_kernel != ek || |
271 | counter->hw_event.exclude_hv != eh) { | 271 | counter->attr.exclude_hv != eh) { |
272 | return -EAGAIN; | 272 | return -EAGAIN; |
273 | } | 273 | } |
274 | } | 274 | } |
@@ -483,16 +483,16 @@ void hw_perf_enable(void) | |||
483 | 483 | ||
484 | /* | 484 | /* |
485 | * Add in MMCR0 freeze bits corresponding to the | 485 | * Add in MMCR0 freeze bits corresponding to the |
486 | * hw_event.exclude_* bits for the first counter. | 486 | * attr.exclude_* bits for the first counter. |
487 | * We have already checked that all counters have the | 487 | * We have already checked that all counters have the |
488 | * same values for these bits as the first counter. | 488 | * same values for these bits as the first counter. |
489 | */ | 489 | */ |
490 | counter = cpuhw->counter[0]; | 490 | counter = cpuhw->counter[0]; |
491 | if (counter->hw_event.exclude_user) | 491 | if (counter->attr.exclude_user) |
492 | cpuhw->mmcr[0] |= MMCR0_FCP; | 492 | cpuhw->mmcr[0] |= MMCR0_FCP; |
493 | if (counter->hw_event.exclude_kernel) | 493 | if (counter->attr.exclude_kernel) |
494 | cpuhw->mmcr[0] |= freeze_counters_kernel; | 494 | cpuhw->mmcr[0] |= freeze_counters_kernel; |
495 | if (counter->hw_event.exclude_hv) | 495 | if (counter->attr.exclude_hv) |
496 | cpuhw->mmcr[0] |= MMCR0_FCHV; | 496 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
497 | 497 | ||
498 | /* | 498 | /* |
@@ -786,10 +786,10 @@ static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev, | |||
786 | int n; | 786 | int n; |
787 | u64 alt[MAX_EVENT_ALTERNATIVES]; | 787 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
788 | 788 | ||
789 | if (counter->hw_event.exclude_user | 789 | if (counter->attr.exclude_user |
790 | || counter->hw_event.exclude_kernel | 790 | || counter->attr.exclude_kernel |
791 | || counter->hw_event.exclude_hv | 791 | || counter->attr.exclude_hv |
792 | || counter->hw_event.sample_period) | 792 | || counter->attr.sample_period) |
793 | return 0; | 793 | return 0; |
794 | 794 | ||
795 | if (ppmu->limited_pmc_event(ev)) | 795 | if (ppmu->limited_pmc_event(ev)) |
@@ -855,13 +855,13 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) | |||
855 | 855 | ||
856 | if (!ppmu) | 856 | if (!ppmu) |
857 | return ERR_PTR(-ENXIO); | 857 | return ERR_PTR(-ENXIO); |
858 | if (!perf_event_raw(&counter->hw_event)) { | 858 | if (!perf_event_raw(&counter->attr)) { |
859 | ev = perf_event_id(&counter->hw_event); | 859 | ev = perf_event_id(&counter->attr); |
860 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) | 860 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
861 | return ERR_PTR(-EOPNOTSUPP); | 861 | return ERR_PTR(-EOPNOTSUPP); |
862 | ev = ppmu->generic_events[ev]; | 862 | ev = ppmu->generic_events[ev]; |
863 | } else { | 863 | } else { |
864 | ev = perf_event_config(&counter->hw_event); | 864 | ev = perf_event_config(&counter->attr); |
865 | } | 865 | } |
866 | counter->hw.config_base = ev; | 866 | counter->hw.config_base = ev; |
867 | counter->hw.idx = 0; | 867 | counter->hw.idx = 0; |
@@ -872,7 +872,7 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter) | |||
872 | * the user set it to. | 872 | * the user set it to. |
873 | */ | 873 | */ |
874 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | 874 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
875 | counter->hw_event.exclude_hv = 0; | 875 | counter->attr.exclude_hv = 0; |
876 | 876 | ||
877 | /* | 877 | /* |
878 | * If this is a per-task counter, then we can use | 878 | * If this is a per-task counter, then we can use |
@@ -990,7 +990,7 @@ static void record_and_restart(struct perf_counter *counter, long val, | |||
990 | */ | 990 | */ |
991 | if (record) { | 991 | if (record) { |
992 | addr = 0; | 992 | addr = 0; |
993 | if (counter->hw_event.record_type & PERF_RECORD_ADDR) { | 993 | if (counter->attr.record_type & PERF_RECORD_ADDR) { |
994 | /* | 994 | /* |
995 | * The user wants a data address recorded. | 995 | * The user wants a data address recorded. |
996 | * If we're not doing instruction sampling, | 996 | * If we're not doing instruction sampling, |