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authorSebastian Andrzej Siewior <bigeasy@linutronix.de>2010-04-04 16:19:02 -0400
committerKumar Gala <galak@kernel.crashing.org>2010-05-24 15:01:12 -0400
commit7c08ce718fd04e373d7473918ae02f1c04d5d504 (patch)
tree27c06711526c6d8c2b49c9e5b39176036b3b4c7e /arch/powerpc
parent2289d2d1a8574a11e66b00c5a59090c6fc227751 (diff)
powerpc/fsl-booke: Move the entry setup code into a seperate file
This patch only moves the initial entry code which setups the mapping from what ever to KERNELBASE into a seperate file. No code change has been made here. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/kernel/fsl_booke_entry_mapping.S200
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S199
2 files changed, 201 insertions, 198 deletions
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
new file mode 100644
index 000000000000..cdb1296f972d
--- /dev/null
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -0,0 +1,200 @@
1
2/* 1. Find the index of the entry we're executing in */
3 bl invstr /* Find our address */
4invstr: mflr r6 /* Make it accessible */
5 mfmsr r7
6 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
7 mfspr r7, SPRN_PID0
8 slwi r7,r7,16
9 or r7,r7,r4
10 mtspr SPRN_MAS6,r7
11 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
12 mfspr r7,SPRN_MAS1
13 andis. r7,r7,MAS1_VALID@h
14 bne match_TLB
15
16 mfspr r7,SPRN_MMUCFG
17 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
18 cmpwi r7,3
19 bne match_TLB /* skip if NPIDS != 3 */
20
21 mfspr r7,SPRN_PID1
22 slwi r7,r7,16
23 or r7,r7,r4
24 mtspr SPRN_MAS6,r7
25 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
26 mfspr r7,SPRN_MAS1
27 andis. r7,r7,MAS1_VALID@h
28 bne match_TLB
29 mfspr r7, SPRN_PID2
30 slwi r7,r7,16
31 or r7,r7,r4
32 mtspr SPRN_MAS6,r7
33 tlbsx 0,r6 /* Fall through, we had to match */
34
35match_TLB:
36 mfspr r7,SPRN_MAS0
37 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
38
39 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
40 oris r7,r7,MAS1_IPROT@h
41 mtspr SPRN_MAS1,r7
42 tlbwe
43
44/* 2. Invalidate all entries except the entry we're executing in */
45 mfspr r9,SPRN_TLB1CFG
46 andi. r9,r9,0xfff
47 li r6,0 /* Set Entry counter to 0 */
481: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
49 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
50 mtspr SPRN_MAS0,r7
51 tlbre
52 mfspr r7,SPRN_MAS1
53 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
54 cmpw r3,r6
55 beq skpinv /* Dont update the current execution TLB */
56 mtspr SPRN_MAS1,r7
57 tlbwe
58 isync
59skpinv: addi r6,r6,1 /* Increment */
60 cmpw r6,r9 /* Are we done? */
61 bne 1b /* If not, repeat */
62
63 /* Invalidate TLB0 */
64 li r6,0x04
65 tlbivax 0,r6
66 TLBSYNC
67 /* Invalidate TLB1 */
68 li r6,0x0c
69 tlbivax 0,r6
70 TLBSYNC
71
72/* 3. Setup a temp mapping and jump to it */
73 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
74 addi r5, r5, 0x1
75 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
76 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
77 mtspr SPRN_MAS0,r7
78 tlbre
79
80 /* grab and fixup the RPN */
81 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
82 rlwinm r6,r6,25,27,31
83 li r8,-1
84 addi r6,r6,10
85 slw r6,r8,r6 /* convert to mask */
86
87 bl 1f /* Find our address */
881: mflr r7
89
90 mfspr r8,SPRN_MAS3
91#ifdef CONFIG_PHYS_64BIT
92 mfspr r23,SPRN_MAS7
93#endif
94 and r8,r6,r8
95 subfic r9,r6,-4096
96 and r9,r9,r7
97
98 or r25,r8,r9
99 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
100
101 /* Just modify the entry ID and EPN for the temp mapping */
102 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
103 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
104 mtspr SPRN_MAS0,r7
105 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
106 slwi r6,r6,12
107 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
108 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
109 mtspr SPRN_MAS1,r6
110 mfspr r6,SPRN_MAS2
111 li r7,0 /* temp EPN = 0 */
112 rlwimi r7,r6,0,20,31
113 mtspr SPRN_MAS2,r7
114 mtspr SPRN_MAS3,r8
115 tlbwe
116
117 xori r6,r4,1
118 slwi r6,r6,5 /* setup new context with other address space */
119 bl 1f /* Find our address */
1201: mflr r9
121 rlwimi r7,r9,0,20,31
122 addi r7,r7,(2f - 1b)
123 mtspr SPRN_SRR0,r7
124 mtspr SPRN_SRR1,r6
125 rfi
1262:
127/* 4. Clear out PIDs & Search info */
128 li r6,0
129 mtspr SPRN_MAS6,r6
130 mtspr SPRN_PID0,r6
131
132 mfspr r7,SPRN_MMUCFG
133 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
134 cmpwi r7,3
135 bne 2f /* skip if NPIDS != 3 */
136
137 mtspr SPRN_PID1,r6
138 mtspr SPRN_PID2,r6
139
140/* 5. Invalidate mapping we started in */
1412:
142 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
143 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
144 mtspr SPRN_MAS0,r7
145 tlbre
146 mfspr r6,SPRN_MAS1
147 rlwinm r6,r6,0,2,0 /* clear IPROT */
148 mtspr SPRN_MAS1,r6
149 tlbwe
150 /* Invalidate TLB1 */
151 li r9,0x0c
152 tlbivax 0,r9
153 TLBSYNC
154
155/* The mapping only needs to be cache-coherent on SMP */
156#ifdef CONFIG_SMP
157#define M_IF_SMP MAS2_M
158#else
159#define M_IF_SMP 0
160#endif
161
162/* 6. Setup KERNELBASE mapping in TLB1[0] */
163 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
164 mtspr SPRN_MAS0,r6
165 lis r6,(MAS1_VALID|MAS1_IPROT)@h
166 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
167 mtspr SPRN_MAS1,r6
168 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
169 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
170 mtspr SPRN_MAS2,r6
171 mtspr SPRN_MAS3,r8
172 tlbwe
173
174/* 7. Jump to KERNELBASE mapping */
175 lis r6,(KERNELBASE & ~0xfff)@h
176 ori r6,r6,(KERNELBASE & ~0xfff)@l
177 lis r7,MSR_KERNEL@h
178 ori r7,r7,MSR_KERNEL@l
179 bl 1f /* Find our address */
1801: mflr r9
181 rlwimi r6,r9,0,20,31
182 addi r6,r6,(2f - 1b)
183 add r6, r6, r25
184 mtspr SPRN_SRR0,r6
185 mtspr SPRN_SRR1,r7
186 rfi /* start execution out of TLB1[0] entry */
187
188/* 8. Clear out the temp mapping */
1892: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
190 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
191 mtspr SPRN_MAS0,r7
192 tlbre
193 mfspr r8,SPRN_MAS1
194 rlwinm r8,r8,0,2,0 /* clear IPROT */
195 mtspr SPRN_MAS1,r8
196 tlbwe
197 /* Invalidate TLB1 */
198 li r9,0x0c
199 tlbivax 0,r9
200 TLBSYNC
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 36ee1db5fc47..6b5b1f3b6112 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -94,205 +94,8 @@ _ENTRY(_start);
94 */ 94 */
95 95
96_ENTRY(__early_start) 96_ENTRY(__early_start)
97/* 1. Find the index of the entry we're executing in */
98 bl invstr /* Find our address */
99invstr: mflr r6 /* Make it accessible */
100 mfmsr r7
101 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
102 mfspr r7, SPRN_PID0
103 slwi r7,r7,16
104 or r7,r7,r4
105 mtspr SPRN_MAS6,r7
106 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
107 mfspr r7,SPRN_MAS1
108 andis. r7,r7,MAS1_VALID@h
109 bne match_TLB
110
111 mfspr r7,SPRN_MMUCFG
112 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
113 cmpwi r7,3
114 bne match_TLB /* skip if NPIDS != 3 */
115
116 mfspr r7,SPRN_PID1
117 slwi r7,r7,16
118 or r7,r7,r4
119 mtspr SPRN_MAS6,r7
120 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
121 mfspr r7,SPRN_MAS1
122 andis. r7,r7,MAS1_VALID@h
123 bne match_TLB
124 mfspr r7, SPRN_PID2
125 slwi r7,r7,16
126 or r7,r7,r4
127 mtspr SPRN_MAS6,r7
128 tlbsx 0,r6 /* Fall through, we had to match */
129
130match_TLB:
131 mfspr r7,SPRN_MAS0
132 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
133
134 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
135 oris r7,r7,MAS1_IPROT@h
136 mtspr SPRN_MAS1,r7
137 tlbwe
138
139/* 2. Invalidate all entries except the entry we're executing in */
140 mfspr r9,SPRN_TLB1CFG
141 andi. r9,r9,0xfff
142 li r6,0 /* Set Entry counter to 0 */
1431: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
144 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
145 mtspr SPRN_MAS0,r7
146 tlbre
147 mfspr r7,SPRN_MAS1
148 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
149 cmpw r3,r6
150 beq skpinv /* Dont update the current execution TLB */
151 mtspr SPRN_MAS1,r7
152 tlbwe
153 isync
154skpinv: addi r6,r6,1 /* Increment */
155 cmpw r6,r9 /* Are we done? */
156 bne 1b /* If not, repeat */
157
158 /* Invalidate TLB0 */
159 li r6,0x04
160 tlbivax 0,r6
161 TLBSYNC
162 /* Invalidate TLB1 */
163 li r6,0x0c
164 tlbivax 0,r6
165 TLBSYNC
166
167/* 3. Setup a temp mapping and jump to it */
168 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
169 addi r5, r5, 0x1
170 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
171 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
172 mtspr SPRN_MAS0,r7
173 tlbre
174
175 /* grab and fixup the RPN */
176 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
177 rlwinm r6,r6,25,27,31
178 li r8,-1
179 addi r6,r6,10
180 slw r6,r8,r6 /* convert to mask */
181
182 bl 1f /* Find our address */
1831: mflr r7
184
185 mfspr r8,SPRN_MAS3
186#ifdef CONFIG_PHYS_64BIT
187 mfspr r23,SPRN_MAS7
188#endif
189 and r8,r6,r8
190 subfic r9,r6,-4096
191 and r9,r9,r7
192
193 or r25,r8,r9
194 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
195
196 /* Just modify the entry ID and EPN for the temp mapping */
197 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
198 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
199 mtspr SPRN_MAS0,r7
200 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
201 slwi r6,r6,12
202 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
203 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
204 mtspr SPRN_MAS1,r6
205 mfspr r6,SPRN_MAS2
206 li r7,0 /* temp EPN = 0 */
207 rlwimi r7,r6,0,20,31
208 mtspr SPRN_MAS2,r7
209 mtspr SPRN_MAS3,r8
210 tlbwe
211
212 xori r6,r4,1
213 slwi r6,r6,5 /* setup new context with other address space */
214 bl 1f /* Find our address */
2151: mflr r9
216 rlwimi r7,r9,0,20,31
217 addi r7,r7,(2f - 1b)
218 mtspr SPRN_SRR0,r7
219 mtspr SPRN_SRR1,r6
220 rfi
2212:
222/* 4. Clear out PIDs & Search info */
223 li r6,0
224 mtspr SPRN_MAS6,r6
225 mtspr SPRN_PID0,r6
226
227 mfspr r7,SPRN_MMUCFG
228 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
229 cmpwi r7,3
230 bne 2f /* skip if NPIDS != 3 */
231 97
232 mtspr SPRN_PID1,r6 98#include "fsl_booke_entry_mapping.S"
233 mtspr SPRN_PID2,r6
234
235/* 5. Invalidate mapping we started in */
2362:
237 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
238 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
239 mtspr SPRN_MAS0,r7
240 tlbre
241 mfspr r6,SPRN_MAS1
242 rlwinm r6,r6,0,2,0 /* clear IPROT */
243 mtspr SPRN_MAS1,r6
244 tlbwe
245 /* Invalidate TLB1 */
246 li r9,0x0c
247 tlbivax 0,r9
248 TLBSYNC
249
250/* The mapping only needs to be cache-coherent on SMP */
251#ifdef CONFIG_SMP
252#define M_IF_SMP MAS2_M
253#else
254#define M_IF_SMP 0
255#endif
256
257/* 6. Setup KERNELBASE mapping in TLB1[0] */
258 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
259 mtspr SPRN_MAS0,r6
260 lis r6,(MAS1_VALID|MAS1_IPROT)@h
261 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
262 mtspr SPRN_MAS1,r6
263 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
264 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
265 mtspr SPRN_MAS2,r6
266 mtspr SPRN_MAS3,r8
267 tlbwe
268
269/* 7. Jump to KERNELBASE mapping */
270 lis r6,(KERNELBASE & ~0xfff)@h
271 ori r6,r6,(KERNELBASE & ~0xfff)@l
272 lis r7,MSR_KERNEL@h
273 ori r7,r7,MSR_KERNEL@l
274 bl 1f /* Find our address */
2751: mflr r9
276 rlwimi r6,r9,0,20,31
277 addi r6,r6,(2f - 1b)
278 add r6, r6, r25
279 mtspr SPRN_SRR0,r6
280 mtspr SPRN_SRR1,r7
281 rfi /* start execution out of TLB1[0] entry */
282
283/* 8. Clear out the temp mapping */
2842: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
285 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
286 mtspr SPRN_MAS0,r7
287 tlbre
288 mfspr r8,SPRN_MAS1
289 rlwinm r8,r8,0,2,0 /* clear IPROT */
290 mtspr SPRN_MAS1,r8
291 tlbwe
292 /* Invalidate TLB1 */
293 li r9,0x0c
294 tlbivax 0,r9
295 TLBSYNC
296 99
297 /* Establish the interrupt vector offsets */ 100 /* Establish the interrupt vector offsets */
298 SET_IVOR(0, CriticalInput); 101 SET_IVOR(0, CriticalInput);
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