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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-12-18 11:40:18 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-20 11:41:46 -0500
commit4b3073e1c53a256275f1079c0fbfbe85883d9275 (patch)
treea0fa98cb75edbbc58c43bbe38ac4c6da0913ae6d /arch/powerpc
parented42acaef1a9d51631a31b55e9ed52d400430492 (diff)
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/pgtable.h2
-rw-r--r--arch/powerpc/mm/mem.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 21207e54825b..89f158731ce3 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -209,7 +209,7 @@ extern void paging_init(void);
209 * corresponding HPTE into the hash table ahead of time, instead of 209 * corresponding HPTE into the hash table ahead of time, instead of
210 * waiting for the inevitable extra hash-table miss exception. 210 * waiting for the inevitable extra hash-table miss exception.
211 */ 211 */
212extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); 212extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
213 213
214extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr, 214extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
215 unsigned long end, int write, struct page **pages, int *nr); 215 unsigned long end, int write, struct page **pages, int *nr);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index b9b152558f9c..311224cdb7ad 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -494,13 +494,13 @@ EXPORT_SYMBOL(flush_icache_user_range);
494 * This must always be called with the pte lock held. 494 * This must always be called with the pte lock held.
495 */ 495 */
496void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 496void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
497 pte_t pte) 497 pte_t *ptep)
498{ 498{
499#ifdef CONFIG_PPC_STD_MMU 499#ifdef CONFIG_PPC_STD_MMU
500 unsigned long access = 0, trap; 500 unsigned long access = 0, trap;
501 501
502 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 502 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
503 if (!pte_young(pte) || address >= TASK_SIZE) 503 if (!pte_young(*ptep) || address >= TASK_SIZE)
504 return; 504 return;
505 505
506 /* We try to figure out if we are coming from an instruction 506 /* We try to figure out if we are coming from an instruction