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authorLinus Torvalds <torvalds@linux-foundation.org>2010-06-01 17:13:14 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-06-01 17:13:14 -0400
commitaef4b9aaae1decc775778903922bd0075cce7a88 (patch)
tree31aeace86eaaf42c63b5dbe807226285d0752a41 /arch/powerpc
parent709d015bb810a3377feaee3093d110a17e919019 (diff)
parenta7fed9f7369bfcfabed7aca1d608d286f2dfa7f6 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Don't export cvt_fd & _df when CONFIG_PPC_FPU is not set powerpc/44x: icon: select SM502 and frame buffer console support powerpc/85xx: Add P1021MDS board support powerpc/85xx: Change MPC8572DS camp dtses for MSI sharing powerpc/fsl_msi: add removal path and probe failing path powerpc/fsl_msi: enable msi sharing through AMP OSes powerpc/fsl_msi: enable msi allocation in all banks powerpc/fsl_msi: fix the conflict of virt_msir's chip_data powerpc/fsl_msi: Add multiple MSI bank support powerpc/kexec: Add support for FSL-BookE powerpc/fsl-booke: Move the entry setup code into a seperate file powerpc/fsl-booke: fix the case where we are not in the first page powerpc/85xx: Enable support for ports 3 and 4 on 8548 CDS powerpc/fsl-booke: Add hibernation support for FSL BookE processors powerpc/e500mc: Implement machine check handler. powerpc/44x: Add basic ICON PPC440SPe board support powerpc/44x: Fix UART clocks on 440SPe powerpc/44x: Add reset-type to katmai.dts powerpc/44x: Adding PCI-E support for PowerPC 460SX based SOC.
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/boot/4xx.c12
-rw-r--r--arch/powerpc/boot/dts/icon.dts447
-rw-r--r--arch/powerpc/boot/dts/katmai.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts15
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts7
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts698
-rw-r--r--arch/powerpc/boot/dts/redwood.dts122
-rw-r--r--arch/powerpc/configs/44x/icon_defconfig1451
-rw-r--r--arch/powerpc/include/asm/cputable.h1
-rw-r--r--arch/powerpc/include/asm/kexec.h13
-rw-r--r--arch/powerpc/include/asm/reg_booke.h33
-rw-r--r--arch/powerpc/kernel/Makefile8
-rw-r--r--arch/powerpc/kernel/cputable.c2
-rw-r--r--arch/powerpc/kernel/crash.c4
-rw-r--r--arch/powerpc/kernel/fsl_booke_entry_mapping.S237
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S200
-rw-r--r--arch/powerpc/kernel/misc_32.S17
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c2
-rw-r--r--arch/powerpc/kernel/swsusp_booke.S193
-rw-r--r--arch/powerpc/kernel/traps.c88
-rw-r--r--arch/powerpc/platforms/44x/Kconfig11
-rw-r--r--arch/powerpc/platforms/44x/ppc44x_simple.c3
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c102
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c117
-rw-r--r--arch/powerpc/sysdev/fsl_msi.h3
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c119
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h58
29 files changed, 3712 insertions, 258 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 66a315e06dce..328774bd41ee 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -351,7 +351,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
351 351
352config KEXEC 352config KEXEC
353 bool "kexec system call (EXPERIMENTAL)" 353 bool "kexec system call (EXPERIMENTAL)"
354 depends on PPC_BOOK3S && EXPERIMENTAL 354 depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
355 help 355 help
356 kexec is a system call that implements the ability to shutdown your 356 kexec is a system call that implements the ability to shutdown your
357 current kernel, and to start another kernel. It is like a reboot 357 current kernel, and to start another kernel. It is like a reboot
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 27db8938827a..9d3bd4c45a24 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -519,7 +519,7 @@ void ibm440ep_fixup_clocks(unsigned int sys_clk,
519{ 519{
520 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); 520 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
521 521
522 /* serial clocks beed fixup based on int/ext */ 522 /* serial clocks need fixup based on int/ext */
523 eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); 523 eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
524 eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk); 524 eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
525 eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk); 525 eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
@@ -532,7 +532,7 @@ void ibm440gx_fixup_clocks(unsigned int sys_clk,
532{ 532{
533 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); 533 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
534 534
535 /* serial clocks beed fixup based on int/ext */ 535 /* serial clocks need fixup based on int/ext */
536 eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); 536 eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
537 eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk); 537 eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
538} 538}
@@ -543,10 +543,10 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk,
543{ 543{
544 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); 544 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
545 545
546 /* serial clocks beed fixup based on int/ext */ 546 /* serial clocks need fixup based on int/ext */
547 eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk); 547 eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
548 eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk); 548 eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
549 eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk); 549 eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
550} 550}
551 551
552void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) 552void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
diff --git a/arch/powerpc/boot/dts/icon.dts b/arch/powerpc/boot/dts/icon.dts
new file mode 100644
index 000000000000..abcd0caeccae
--- /dev/null
+++ b/arch/powerpc/boot/dts/icon.dts
@@ -0,0 +1,447 @@
1/*
2 * Device Tree Source for Mosaix Technologies, Inc. ICON board
3 *
4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <2>;
15 #size-cells = <2>;
16 model = "mosaixtech,icon";
17 compatible = "mosaixtech,icon";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 serial0 = &UART0;
23 serial1 = &UART1;
24 serial2 = &UART2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,440SPe";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 reset-type = <2>; /* Use chip-reset */
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440spe","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-440spe","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71 interrupt-parent = <&UIC0>;
72 };
73
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-440spe","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
84 };
85
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-440spe","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
96 };
97
98 SDR0: sdr {
99 compatible = "ibm,sdr-440spe";
100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-440spe";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 MQ0: mq {
109 compatible = "ibm,mq-440spe";
110 dcr-reg = <0x040 0x020>;
111 };
112
113 plb {
114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
115 #address-cells = <2>;
116 #size-cells = <1>;
117 /* addr-child addr-parent size */
118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
119 0x4 0x00200000 0x4 0x00200000 0x00000400
120 0x4 0xe0000000 0x4 0xe0000000 0x20000000
121 0xc 0x00000000 0xc 0x00000000 0x20000000
122 0xd 0x00000000 0xd 0x00000000 0x80000000
123 0xd 0x80000000 0xd 0x80000000 0x80000000
124 0xe 0x00000000 0xe 0x00000000 0x80000000
125 0xe 0x80000000 0xe 0x80000000 0x80000000
126 0xf 0x00000000 0xf 0x00000000 0x80000000
127 0xf 0x80000000 0xf 0x80000000 0x80000000>;
128 clock-frequency = <0>; /* Filled in by U-Boot */
129
130 SDRAM0: sdram {
131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
132 dcr-reg = <0x010 0x002>;
133 };
134
135 MAL0: mcmal {
136 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
137 dcr-reg = <0x180 0x062>;
138 num-tx-chans = <2>;
139 num-rx-chans = <1>;
140 interrupt-parent = <&MAL0>;
141 interrupts = <0x0 0x1 0x2 0x3 0x4>;
142 #interrupt-cells = <1>;
143 #address-cells = <0>;
144 #size-cells = <0>;
145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
146 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
147 /*SERR*/ 0x2 &UIC1 0x1 0x4
148 /*TXDE*/ 0x3 &UIC1 0x2 0x4
149 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
150 };
151
152 POB0: opb {
153 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
158
159 EBC0: ebc {
160 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
161 dcr-reg = <0x012 0x002>;
162 #address-cells = <2>;
163 #size-cells = <1>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
165 /* ranges property is supplied by U-Boot */
166 interrupts = <0x5 0x1>;
167 interrupt-parent = <&UIC1>;
168
169 nor_flash@0,0 {
170 compatible = "cfi-flash";
171 bank-width = <2>;
172 reg = <0x00000000 0x00000000 0x01000000>;
173 #address-cells = <1>;
174 #size-cells = <1>;
175 partition@0 {
176 label = "kernel";
177 reg = <0x00000000 0x001e0000>;
178 };
179 partition@1e0000 {
180 label = "dtb";
181 reg = <0x001e0000 0x00020000>;
182 };
183 partition@200000 {
184 label = "root";
185 reg = <0x00200000 0x00200000>;
186 };
187 partition@400000 {
188 label = "user";
189 reg = <0x00400000 0x00b60000>;
190 };
191 partition@f60000 {
192 label = "env";
193 reg = <0x00f60000 0x00040000>;
194 };
195 partition@fa0000 {
196 label = "u-boot";
197 reg = <0x00fa0000 0x00060000>;
198 };
199 };
200
201 SysACE_CompactFlash: sysace@1,0 {
202 compatible = "xlnx,sysace";
203 interrupt-parent = <&UIC2>;
204 interrupts = <24 0x4>;
205 reg = <0x00000001 0x00000000 0x10000>;
206 };
207 };
208
209 UART0: serial@f0000200 {
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0xf0000200 0x00000008>;
213 virtual-reg = <0xa0000200>;
214 clock-frequency = <0>; /* Filled in by U-Boot */
215 current-speed = <115200>;
216 interrupt-parent = <&UIC0>;
217 interrupts = <0x0 0x4>;
218 };
219
220 UART1: serial@f0000300 {
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0xf0000300 0x00000008>;
224 virtual-reg = <0xa0000300>;
225 clock-frequency = <0>;
226 current-speed = <0>;
227 interrupt-parent = <&UIC0>;
228 interrupts = <0x1 0x4>;
229 };
230
231
232 UART2: serial@f0000600 {
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0xf0000600 0x00000008>;
236 virtual-reg = <0xa0000600>;
237 clock-frequency = <0>;
238 current-speed = <0>;
239 interrupt-parent = <&UIC1>;
240 interrupts = <0x5 0x4>;
241 };
242
243 IIC0: i2c@f0000400 {
244 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
245 reg = <0xf0000400 0x00000014>;
246 interrupt-parent = <&UIC0>;
247 interrupts = <0x2 0x4>;
248 };
249
250 IIC1: i2c@f0000500 {
251 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
252 reg = <0xf0000500 0x00000014>;
253 interrupt-parent = <&UIC0>;
254 interrupts = <0x3 0x4>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 rtc@68 {
259 compatible = "stm,m41t00";
260 reg = <0x68>;
261 };
262 };
263
264 EMAC0: ethernet@f0000800 {
265 linux,network-index = <0x0>;
266 device_type = "network";
267 compatible = "ibm,emac-440spe", "ibm,emac4";
268 interrupt-parent = <&UIC1>;
269 interrupts = <0x1c 0x4 0x1d 0x4>;
270 reg = <0xf0000800 0x00000074>;
271 local-mac-address = [000000000000];
272 mal-device = <&MAL0>;
273 mal-tx-channel = <0>;
274 mal-rx-channel = <0>;
275 cell-index = <0>;
276 max-frame-size = <9000>;
277 rx-fifo-size = <4096>;
278 tx-fifo-size = <2048>;
279 phy-mode = "gmii";
280 phy-map = <0x00000000>;
281 has-inverted-stacr-oc;
282 has-new-stacr-staopc;
283 };
284 };
285
286 PCIX0: pci@c0ec00000 {
287 device_type = "pci";
288 #interrupt-cells = <1>;
289 #size-cells = <2>;
290 #address-cells = <3>;
291 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
292 primary;
293 large-inbound-windows;
294 enable-msi-hole;
295 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
296 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
297 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
298 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
299 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
300
301 /* Outbound ranges, one memory and one IO,
302 * later cannot be changed
303 */
304 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
305 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
306
307 /* Inbound 4GB range starting at 0 */
308 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
309
310 /* This drives busses 0 to 0xf */
311 bus-range = <0x0 0xf>;
312
313 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
314 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
315 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
316 };
317
318 PCIE0: pciex@d00000000 {
319 device_type = "pci";
320 #interrupt-cells = <1>;
321 #size-cells = <2>;
322 #address-cells = <3>;
323 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
324 primary;
325 port = <0x0>; /* port number */
326 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
327 0x0000000c 0x10000000 0x00001000>; /* Registers */
328 dcr-reg = <0x100 0x020>;
329 sdr-base = <0x300>;
330
331 /* Outbound ranges, one memory and one IO,
332 * later cannot be changed
333 */
334 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
335 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
336
337 /* Inbound 4GB range starting at 0 */
338 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
339
340 /* This drives busses 0x10 to 0x1f */
341 bus-range = <0x10 0x1f>;
342
343 /* Legacy interrupts (note the weird polarity, the bridge seems
344 * to invert PCIe legacy interrupts).
345 * We are de-swizzling here because the numbers are actually for
346 * port of the root complex virtual P2P bridge. But I want
347 * to avoid putting a node for it in the tree, so the numbers
348 * below are basically de-swizzled numbers.
349 * The real slot is on idsel 0, so the swizzling is 1:1
350 */
351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <
353 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
354 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
355 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
356 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
357 };
358
359 PCIE1: pciex@d20000000 {
360 device_type = "pci";
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
365 primary;
366 port = <0x1>; /* port number */
367 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
368 0x0000000c 0x10001000 0x00001000>; /* Registers */
369 dcr-reg = <0x120 0x020>;
370 sdr-base = <0x340>;
371
372 /* Outbound ranges, one memory and one IO,
373 * later cannot be changed
374 */
375 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
376 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
377
378 /* Inbound 4GB range starting at 0 */
379 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
380
381 /* This drives busses 0x20 to 0x2f */
382 bus-range = <0x20 0x2f>;
383
384 /* Legacy interrupts (note the weird polarity, the bridge seems
385 * to invert PCIe legacy interrupts).
386 * We are de-swizzling here because the numbers are actually for
387 * port of the root complex virtual P2P bridge. But I want
388 * to avoid putting a node for it in the tree, so the numbers
389 * below are basically de-swizzled numbers.
390 * The real slot is on idsel 0, so the swizzling is 1:1
391 */
392 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
393 interrupt-map = <
394 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
395 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
396 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
397 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
398 };
399
400 I2O: i2o@400100000 {
401 compatible = "ibm,i2o-440spe";
402 reg = <0x00000004 0x00100000 0x100>;
403 dcr-reg = <0x060 0x020>;
404 };
405
406 DMA0: dma0@400100100 {
407 compatible = "ibm,dma-440spe";
408 cell-index = <0>;
409 reg = <0x00000004 0x00100100 0x100>;
410 dcr-reg = <0x060 0x020>;
411 interrupt-parent = <&DMA0>;
412 interrupts = <0 1>;
413 #interrupt-cells = <1>;
414 #address-cells = <0>;
415 #size-cells = <0>;
416 interrupt-map = <
417 0 &UIC0 0x14 4
418 1 &UIC1 0x16 4>;
419 };
420
421 DMA1: dma1@400100200 {
422 compatible = "ibm,dma-440spe";
423 cell-index = <1>;
424 reg = <0x00000004 0x00100200 0x100>;
425 dcr-reg = <0x060 0x020>;
426 interrupt-parent = <&DMA1>;
427 interrupts = <0 1>;
428 #interrupt-cells = <1>;
429 #address-cells = <0>;
430 #size-cells = <0>;
431 interrupt-map = <
432 0 &UIC0 0x16 4
433 1 &UIC1 0x16 4>;
434 };
435
436 xor-accel@400200000 {
437 compatible = "amcc,xor-accelerator";
438 reg = <0x00000004 0x00200000 0x400>;
439 interrupt-parent = <&UIC1>;
440 interrupts = <0x1f 4>;
441 };
442 };
443
444 chosen {
445 linux,stdout-path = "/plb/opb/serial@f0000200";
446 };
447};
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 8cf2c0c88c05..7c3be5e45748 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -44,6 +44,7 @@
44 d-cache-size = <32768>; 44 d-cache-size = <32768>;
45 dcr-controller; 45 dcr-controller;
46 dcr-access-method = "native"; 46 dcr-access-method = "native";
47 reset-type = <2>; /* Use chip-reset */
47 }; 48 };
48 }; 49 };
49 50
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4173af387c63..0f5262452682 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -20,10 +20,8 @@
20 aliases { 20 aliases {
21 ethernet0 = &enet0; 21 ethernet0 = &enet0;
22 ethernet1 = &enet1; 22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2; 23 ethernet2 = &enet2;
25 ethernet3 = &enet3; 24 ethernet3 = &enet3;
26*/
27 serial0 = &serial0; 25 serial0 = &serial0;
28 serial1 = &serial1; 26 serial1 = &serial1;
29 pci0 = &pci0; 27 pci0 = &pci0;
@@ -254,7 +252,6 @@
254 }; 252 };
255 }; 253 };
256 254
257/* eTSEC 3/4 are currently broken
258 enet2: ethernet@26000 { 255 enet2: ethernet@26000 {
259 #address-cells = <1>; 256 #address-cells = <1>;
260 #size-cells = <1>; 257 #size-cells = <1>;
@@ -310,7 +307,6 @@
310 }; 307 };
311 }; 308 };
312 }; 309 };
313 */
314 310
315 serial0: serial@4500 { 311 serial0: serial@4500 {
316 cell-index = <0>; 312 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 5bd1011fde96..3375c2ab0c32 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -215,6 +215,18 @@
215 clock-frequency = <0>; 215 clock-frequency = <0>;
216 }; 216 };
217 217
218 msi@41600 {
219 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
220 reg = <0x41600 0x80>;
221 msi-available-ranges = <0 0x80>;
222 interrupts = <
223 0xe0 0
224 0xe1 0
225 0xe2 0
226 0xe3 0>;
227 interrupt-parent = <&mpic>;
228 };
229
218 global-utilities@e0000 { //global utilities block 230 global-utilities@e0000 { //global utilities block
219 compatible = "fsl,mpc8572-guts"; 231 compatible = "fsl,mpc8572-guts";
220 reg = <0xe0000 0x1000>; 232 reg = <0xe0000 0x1000>;
@@ -243,8 +255,7 @@
243 protected-sources = < 255 protected-sources = <
244 31 32 33 37 38 39 /* enet2 enet3 */ 256 31 32 33 37 38 39 /* enet2 enet3 */
245 76 77 78 79 26 42 /* dma2 pci2 serial*/ 257 76 77 78 79 26 42 /* dma2 pci2 serial*/
246 0xe0 0xe1 0xe2 0xe3 /* msi */ 258 0xe4 0xe5 0xe6 0xe7 /* msi */
247 0xe4 0xe5 0xe6 0xe7
248 >; 259 >;
249 }; 260 };
250 }; 261 };
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 0efc3456e297..e7b477f6a3fe 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -154,12 +154,8 @@
154 msi@41600 { 154 msi@41600 {
155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
156 reg = <0x41600 0x80>; 156 reg = <0x41600 0x80>;
157 msi-available-ranges = <0 0x100>; 157 msi-available-ranges = <0x80 0x80>;
158 interrupts = < 158 interrupts = <
159 0xe0 0
160 0xe1 0
161 0xe2 0
162 0xe3 0
163 0xe4 0 159 0xe4 0
164 0xe5 0 160 0xe5 0
165 0xe6 0 161 0xe6 0
@@ -190,6 +186,7 @@
190 0x1 0x2 0x3 0x4 /* pci slot */ 186 0x1 0x2 0x3 0x4 /* pci slot */
191 0x9 0xa 0xb 0xc /* usb */ 187 0x9 0xa 0xb 0xc /* usb */
192 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */ 188 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
189 0xe0 0xe1 0xe2 0xe3 /* msi */
193 >; 190 >;
194 }; 191 };
195 }; 192 };
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
new file mode 100644
index 000000000000..7fad2df25981
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -0,0 +1,698 @@
1/*
2 * P1021 MDS Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@ffe05000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59
60 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
62 0x1 0x0 0x0 0xf8000000 0x00008000
63 0x2 0x0 0x0 0xf8010000 0x00020000
64 0x3 0x0 0x0 0xf8020000 0x00020000>;
65
66 nand@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "fsl,p1021-fcm-nand",
70 "fsl,elbc-fcm-nand";
71 reg = <0x0 0x0 0x40000>;
72
73 partition@0 {
74 /* This location must not be altered */
75 /* 1MB for u-boot Bootloader Image */
76 reg = <0x0 0x00100000>;
77 label = "NAND (RO) U-Boot Image";
78 read-only;
79 };
80
81 partition@100000 {
82 /* 1MB for DTB Image */
83 reg = <0x00100000 0x00100000>;
84 label = "NAND (RO) DTB Image";
85 read-only;
86 };
87
88 partition@200000 {
89 /* 4MB for Linux Kernel Image */
90 reg = <0x00200000 0x00400000>;
91 label = "NAND (RO) Linux Kernel Image";
92 read-only;
93 };
94
95 partition@600000 {
96 /* 5MB for Compressed Root file System Image */
97 reg = <0x00600000 0x00500000>;
98 label = "NAND (RO) Compressed RFS Image";
99 read-only;
100 };
101
102 partition@b00000 {
103 /* 6MB for JFFS2 based Root file System */
104 reg = <0x00a00000 0x00600000>;
105 label = "NAND (RW) JFFS2 Root File System";
106 };
107
108 partition@1100000 {
109 /* 14MB for JFFS2 based Root file System */
110 reg = <0x01100000 0x00e00000>;
111 label = "NAND (RW) Writable User area";
112 };
113
114 partition@1f00000 {
115 /* 1MB for microcode */
116 reg = <0x01f00000 0x00100000>;
117 label = "NAND (RO) QE Ucode";
118 read-only;
119 };
120 };
121
122 bcsr@1,0 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,p1021mds-bcsr";
126 reg = <1 0 0x8000>;
127 ranges = <0 1 0 0x8000>;
128 };
129
130 pib@2,0 {
131 compatible = "fsl,p1021mds-pib";
132 reg = <2 0 0x10000>;
133 };
134
135 pib@3,0 {
136 compatible = "fsl,p1021mds-pib";
137 reg = <3 0 0x10000>;
138 };
139 };
140
141 soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169
170 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 {
180 compatible = "dallas,ds1374";
181 reg = <0x68>;
182 };
183 };
184
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 {
217 cell-index = <0>;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "fsl,espi-flash";
231 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */
234 partition@u-boot {
235 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>;
237 read-only;
238 };
239 partition@kernel {
240 label = "kernel-spi";
241 reg = <0x00100000 0x00500000>;
242 read-only;
243 };
244 partition@dtb {
245 label = "dtb-spi";
246 reg = <0x00600000 0x00100000>;
247 read-only;
248 };
249 partition@fs {
250 label = "file system-spi";
251 reg = <0x00700000 0x00900000>;
252 };
253 };
254 };
255
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi";
319 };
320
321 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>;
329 interrupts = <1 1>;
330 reg = <0x0>;
331 };
332 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>;
334 interrupts = <2 1>;
335 reg = <0x1>;
336 };
337 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>;
340 };
341 };
342
343 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 {
349 reg = <0x11>;
350 device_type = "tbi-phy";
351 };
352 };
353
354 enet0: ethernet@B0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 };
380
381 enet1: ethernet@B1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 };
408
409 enet2: ethernet@B2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 };
488
489 par_io@e0100 {
490 #address-cells = <1>;
491 #size-cells = <1>;
492 reg = <0xe0100 0x60>;
493 ranges = <0x0 0xe0100 0x60>;
494 device_type = "par_io";
495 num-ports = <3>;
496 pio1: ucc_pin@01 {
497 pio-map = <
498 /* port pin dir open_drain assignment has_irq */
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
507 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
508 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
509 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
510 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
511 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
512 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
513 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
514 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
515 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
516 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
517 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
518 };
519
520 pio2: ucc_pin@02 {
521 pio-map = <
522 /* port pin dir open_drain assignment has_irq */
523 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
524 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
525 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
526 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
527 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
528 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
529 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
530 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
531 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
532 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
533 };
534 };
535 };
536
537 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000
565 0x0 0x20000000
566
567 0x1000000 0x0 0x0
568 0x1000000 0x0 0x0
569 0x0 0x100000>;
570 };
571 };
572
573 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000
601 0x0 0x20000000
602
603 0x1000000 0x0 0x0
604 0x1000000 0x0 0x0
605 0x0 0x100000>;
606 };
607 };
608
609 qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>;
617 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620
621 qeic: interrupt-controller@80 {
622 interrupt-controller;
623 compatible = "fsl,qe-ic";
624 #address-cells = <0>;
625 #interrupt-cells = <1>;
626 reg = <0x80 0x80>;
627 interrupts = <63 2 60 2>; //high:47 low:44
628 interrupt-parent = <&mpic>;
629 };
630
631 enet3: ucc@2000 {
632 device_type = "network";
633 compatible = "ucc_geth";
634 cell-index = <1>;
635 reg = <0x2000 0x200>;
636 interrupts = <32>;
637 interrupt-parent = <&qeic>;
638 local-mac-address = [ 00 00 00 00 00 00 ];
639 rx-clock-name = "clk12";
640 tx-clock-name = "clk9";
641 pio-handle = <&pio1>;
642 phy-handle = <&qe_phy0>;
643 phy-connection-type = "mii";
644 };
645
646 mdio@2120 {
647 #address-cells = <1>;
648 #size-cells = <0>;
649 reg = <0x2120 0x18>;
650 compatible = "fsl,ucc-mdio";
651
652 qe_phy0: ethernet-phy@0 {
653 interrupt-parent = <&mpic>;
654 interrupts = <4 1>;
655 reg = <0x0>;
656 device_type = "ethernet-phy";
657 };
658 qe_phy1: ethernet-phy@03 {
659 interrupt-parent = <&mpic>;
660 interrupts = <5 1>;
661 reg = <0x3>;
662 device_type = "ethernet-phy";
663 };
664 tbi-phy@11 {
665 reg = <0x11>;
666 device_type = "tbi-phy";
667 };
668 };
669
670 enet4: ucc@2400 {
671 device_type = "network";
672 compatible = "ucc_geth";
673 cell-index = <5>;
674 reg = <0x2400 0x200>;
675 interrupts = <40>;
676 interrupt-parent = <&qeic>;
677 local-mac-address = [ 00 00 00 00 00 00 ];
678 rx-clock-name = "none";
679 tx-clock-name = "clk13";
680 pio-handle = <&pio2>;
681 phy-handle = <&qe_phy1>;
682 phy-connection-type = "rmii";
683 };
684
685 muram@10000 {
686 #address-cells = <1>;
687 #size-cells = <1>;
688 compatible = "fsl,qe-muram", "fsl,cpm-muram";
689 ranges = <0x0 0x10000 0x6000>;
690
691 data-only@0 {
692 compatible = "fsl,qe-muram-data",
693 "fsl,cpm-muram-data";
694 reg = <0x0 0x6000>;
695 };
696 };
697 };
698};
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index d2af32e2bf7a..81636c01d906 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -234,10 +234,132 @@
234 has-inverted-stacr-oc; 234 has-inverted-stacr-oc;
235 has-new-stacr-staopc; 235 has-new-stacr-staopc;
236 }; 236 };
237 };
238 PCIE0: pciex@d00000000 {
239 device_type = "pci";
240 #interrupt-cells = <1>;
241 #size-cells = <2>;
242 #address-cells = <3>;
243 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
244 primary;
245 port = <0x0>; /* port number */
246 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
247 0x0000000c 0x10000000 0x00001000>; /* Registers */
248 dcr-reg = <0x100 0x020>;
249 sdr-base = <0x300>;
250
251 /* Outbound ranges, one memory and one IO,
252 * later cannot be changed
253 */
254 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
255 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
256
257 /* Inbound 2GB range starting at 0 */
258 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
237 259
260 /* This drives busses 10 to 0x1f */
261 bus-range = <0x10 0x1f>;
262
263 /* Legacy interrupts (note the weird polarity, the bridge seems
264 * to invert PCIe legacy interrupts).
265 * We are de-swizzling here because the numbers are actually for
266 * port of the root complex virtual P2P bridge. But I want
267 * to avoid putting a node for it in the tree, so the numbers
268 * below are basically de-swizzled numbers.
269 * The real slot is on idsel 0, so the swizzling is 1:1
270 */
271 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
272 interrupt-map = <
273 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
274 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
275 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
276 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
277 };
278
279 PCIE1: pciex@d20000000 {
280 device_type = "pci";
281 #interrupt-cells = <1>;
282 #size-cells = <2>;
283 #address-cells = <3>;
284 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
285 primary;
286 port = <0x1>; /* port number */
287 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
288 0x0000000c 0x10001000 0x00001000>; /* Registers */
289 dcr-reg = <0x120 0x020>;
290 sdr-base = <0x340>;
291
292 /* Outbound ranges, one memory and one IO,
293 * later cannot be changed
294 */
295 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
296 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
297
298 /* Inbound 2GB range starting at 0 */
299 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
300
301 /* This drives busses 10 to 0x1f */
302 bus-range = <0x20 0x2f>;
303
304 /* Legacy interrupts (note the weird polarity, the bridge seems
305 * to invert PCIe legacy interrupts).
306 * We are de-swizzling here because the numbers are actually for
307 * port of the root complex virtual P2P bridge. But I want
308 * to avoid putting a node for it in the tree, so the numbers
309 * below are basically de-swizzled numbers.
310 * The real slot is on idsel 0, so the swizzling is 1:1
311 */
312 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
313 interrupt-map = <
314 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
315 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
316 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
317 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
318 };
319
320 PCIE2: pciex@d40000000 {
321 device_type = "pci";
322 #interrupt-cells = <1>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
326 primary;
327 port = <0x2>; /* port number */
328 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
329 0x0000000c 0x10002000 0x00001000>; /* Registers */
330 dcr-reg = <0x140 0x020>;
331 sdr-base = <0x370>;
332
333 /* Outbound ranges, one memory and one IO,
334 * later cannot be changed
335 */
336 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
337 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
338
339 /* Inbound 2GB range starting at 0 */
340 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
341
342 /* This drives busses 10 to 0x1f */
343 bus-range = <0x30 0x3f>;
344
345 /* Legacy interrupts (note the weird polarity, the bridge seems
346 * to invert PCIe legacy interrupts).
347 * We are de-swizzling here because the numbers are actually for
348 * port of the root complex virtual P2P bridge. But I want
349 * to avoid putting a node for it in the tree, so the numbers
350 * below are basically de-swizzled numbers.
351 * The real slot is on idsel 0, so the swizzling is 1:1
352 */
353 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
354 interrupt-map = <
355 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
356 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
357 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
358 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
238 }; 359 };
239 360
240 }; 361 };
362
241 chosen { 363 chosen {
242 linux,stdout-path = "/plb/opb/serial@ef600200"; 364 linux,stdout-path = "/plb/opb/serial@ef600200";
243 }; 365 };
diff --git a/arch/powerpc/configs/44x/icon_defconfig b/arch/powerpc/configs/44x/icon_defconfig
new file mode 100644
index 000000000000..277f88c2750f
--- /dev/null
+++ b/arch/powerpc/configs/44x/icon_defconfig
@@ -0,0 +1,1451 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.34-rc7
4# Fri May 21 17:40:22 2010
5#
6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11# CONFIG_PPC_BOOK3S_32 is not set
12# CONFIG_PPC_85xx is not set
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15CONFIG_44x=y
16# CONFIG_E200 is not set
17CONFIG_4xx=y
18CONFIG_BOOKE=y
19CONFIG_PTE_64BIT=y
20CONFIG_PHYS_64BIT=y
21CONFIG_PPC_MMU_NOHASH=y
22CONFIG_PPC_MMU_NOHASH_32=y
23# CONFIG_PPC_MM_SLICES is not set
24CONFIG_NOT_COHERENT_CACHE=y
25CONFIG_PPC32=y
26CONFIG_WORD_SIZE=32
27CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
28CONFIG_MMU=y
29CONFIG_GENERIC_CMOS_UPDATE=y
30CONFIG_GENERIC_TIME=y
31CONFIG_GENERIC_TIME_VSYSCALL=y
32CONFIG_GENERIC_CLOCKEVENTS=y
33CONFIG_GENERIC_HARDIRQS=y
34CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
35# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
36# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
37CONFIG_IRQ_PER_CPU=y
38CONFIG_NR_IRQS=512
39CONFIG_STACKTRACE_SUPPORT=y
40CONFIG_HAVE_LATENCYTOP_SUPPORT=y
41CONFIG_TRACE_IRQFLAGS_SUPPORT=y
42CONFIG_LOCKDEP_SUPPORT=y
43CONFIG_RWSEM_XCHGADD_ALGORITHM=y
44CONFIG_ARCH_HAS_ILOG2_U32=y
45CONFIG_GENERIC_HWEIGHT=y
46CONFIG_GENERIC_FIND_NEXT_BIT=y
47# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
48CONFIG_PPC=y
49CONFIG_EARLY_PRINTK=y
50CONFIG_GENERIC_NVRAM=y
51CONFIG_SCHED_OMIT_FRAME_POINTER=y
52CONFIG_ARCH_MAY_HAVE_PC_FDC=y
53CONFIG_PPC_OF=y
54CONFIG_OF=y
55CONFIG_PPC_UDBG_16550=y
56# CONFIG_GENERIC_TBSYNC is not set
57CONFIG_AUDIT_ARCH=y
58CONFIG_GENERIC_BUG=y
59CONFIG_DTC=y
60# CONFIG_DEFAULT_UIMAGE is not set
61CONFIG_ARCH_HIBERNATION_POSSIBLE=y
62CONFIG_PPC_DCR_NATIVE=y
63# CONFIG_PPC_DCR_MMIO is not set
64CONFIG_PPC_DCR=y
65CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
66CONFIG_PPC_ADV_DEBUG_REGS=y
67CONFIG_PPC_ADV_DEBUG_IACS=4
68CONFIG_PPC_ADV_DEBUG_DACS=2
69CONFIG_PPC_ADV_DEBUG_DVCS=2
70CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
71CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
72CONFIG_CONSTRUCTORS=y
73
74#
75# General setup
76#
77CONFIG_EXPERIMENTAL=y
78CONFIG_BROKEN_ON_SMP=y
79CONFIG_INIT_ENV_ARG_LIMIT=32
80CONFIG_LOCALVERSION=""
81CONFIG_LOCALVERSION_AUTO=y
82CONFIG_SWAP=y
83CONFIG_SYSVIPC=y
84CONFIG_SYSVIPC_SYSCTL=y
85CONFIG_POSIX_MQUEUE=y
86CONFIG_POSIX_MQUEUE_SYSCTL=y
87# CONFIG_BSD_PROCESS_ACCT is not set
88# CONFIG_TASKSTATS is not set
89# CONFIG_AUDIT is not set
90
91#
92# RCU Subsystem
93#
94CONFIG_TREE_RCU=y
95# CONFIG_TREE_PREEMPT_RCU is not set
96# CONFIG_TINY_RCU is not set
97# CONFIG_RCU_TRACE is not set
98CONFIG_RCU_FANOUT=32
99# CONFIG_RCU_FANOUT_EXACT is not set
100# CONFIG_TREE_RCU_TRACE is not set
101# CONFIG_IKCONFIG is not set
102CONFIG_LOG_BUF_SHIFT=14
103# CONFIG_CGROUPS is not set
104CONFIG_SYSFS_DEPRECATED=y
105CONFIG_SYSFS_DEPRECATED_V2=y
106# CONFIG_RELAY is not set
107# CONFIG_NAMESPACES is not set
108CONFIG_BLK_DEV_INITRD=y
109CONFIG_INITRAMFS_SOURCE=""
110CONFIG_RD_GZIP=y
111# CONFIG_RD_BZIP2 is not set
112# CONFIG_RD_LZMA is not set
113# CONFIG_RD_LZO is not set
114# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
115CONFIG_SYSCTL=y
116CONFIG_ANON_INODES=y
117CONFIG_EMBEDDED=y
118CONFIG_SYSCTL_SYSCALL=y
119CONFIG_KALLSYMS=y
120# CONFIG_KALLSYMS_ALL is not set
121# CONFIG_KALLSYMS_EXTRA_PASS is not set
122CONFIG_HOTPLUG=y
123CONFIG_PRINTK=y
124# CONFIG_LOGBUFFER is not set
125CONFIG_BUG=y
126CONFIG_ELF_CORE=y
127CONFIG_BASE_FULL=y
128CONFIG_FUTEX=y
129CONFIG_EPOLL=y
130CONFIG_SIGNALFD=y
131CONFIG_TIMERFD=y
132CONFIG_EVENTFD=y
133CONFIG_SHMEM=y
134CONFIG_AIO=y
135CONFIG_HAVE_PERF_EVENTS=y
136
137#
138# Kernel Performance Events And Counters
139#
140# CONFIG_PERF_EVENTS is not set
141# CONFIG_PERF_COUNTERS is not set
142CONFIG_VM_EVENT_COUNTERS=y
143CONFIG_PCI_QUIRKS=y
144CONFIG_SLUB_DEBUG=y
145CONFIG_COMPAT_BRK=y
146# CONFIG_SLAB is not set
147CONFIG_SLUB=y
148# CONFIG_SLOB is not set
149# CONFIG_PROFILING is not set
150CONFIG_HAVE_OPROFILE=y
151# CONFIG_KPROBES is not set
152CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
153CONFIG_HAVE_IOREMAP_PROT=y
154CONFIG_HAVE_KPROBES=y
155CONFIG_HAVE_KRETPROBES=y
156CONFIG_HAVE_ARCH_TRACEHOOK=y
157CONFIG_HAVE_DMA_ATTRS=y
158CONFIG_HAVE_DMA_API_DEBUG=y
159
160#
161# GCOV-based kernel profiling
162#
163# CONFIG_SLOW_WORK is not set
164# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
165CONFIG_SLABINFO=y
166CONFIG_RT_MUTEXES=y
167CONFIG_BASE_SMALL=0
168CONFIG_MODULES=y
169# CONFIG_MODULE_FORCE_LOAD is not set
170CONFIG_MODULE_UNLOAD=y
171# CONFIG_MODULE_FORCE_UNLOAD is not set
172# CONFIG_MODVERSIONS is not set
173# CONFIG_MODULE_SRCVERSION_ALL is not set
174CONFIG_BLOCK=y
175CONFIG_LBDAF=y
176# CONFIG_BLK_DEV_BSG is not set
177# CONFIG_BLK_DEV_INTEGRITY is not set
178
179#
180# IO Schedulers
181#
182CONFIG_IOSCHED_NOOP=y
183CONFIG_IOSCHED_DEADLINE=y
184CONFIG_IOSCHED_CFQ=y
185# CONFIG_DEFAULT_DEADLINE is not set
186CONFIG_DEFAULT_CFQ=y
187# CONFIG_DEFAULT_NOOP is not set
188CONFIG_DEFAULT_IOSCHED="cfq"
189# CONFIG_INLINE_SPIN_TRYLOCK is not set
190# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
191# CONFIG_INLINE_SPIN_LOCK is not set
192# CONFIG_INLINE_SPIN_LOCK_BH is not set
193# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
194# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
195CONFIG_INLINE_SPIN_UNLOCK=y
196# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
197CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
198# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
199# CONFIG_INLINE_READ_TRYLOCK is not set
200# CONFIG_INLINE_READ_LOCK is not set
201# CONFIG_INLINE_READ_LOCK_BH is not set
202# CONFIG_INLINE_READ_LOCK_IRQ is not set
203# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
204CONFIG_INLINE_READ_UNLOCK=y
205# CONFIG_INLINE_READ_UNLOCK_BH is not set
206CONFIG_INLINE_READ_UNLOCK_IRQ=y
207# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
208# CONFIG_INLINE_WRITE_TRYLOCK is not set
209# CONFIG_INLINE_WRITE_LOCK is not set
210# CONFIG_INLINE_WRITE_LOCK_BH is not set
211# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
212# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
213CONFIG_INLINE_WRITE_UNLOCK=y
214# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
215CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
216# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
217# CONFIG_MUTEX_SPIN_ON_OWNER is not set
218# CONFIG_FREEZER is not set
219CONFIG_PPC4xx_PCI_EXPRESS=y
220
221#
222# Platform support
223#
224# CONFIG_PPC_CELL is not set
225# CONFIG_PPC_CELL_NATIVE is not set
226# CONFIG_PQ2ADS is not set
227# CONFIG_BAMBOO is not set
228# CONFIG_EBONY is not set
229# CONFIG_SAM440EP is not set
230# CONFIG_SEQUOIA is not set
231# CONFIG_TAISHAN is not set
232# CONFIG_KATMAI is not set
233# CONFIG_RAINIER is not set
234# CONFIG_WARP is not set
235# CONFIG_ARCHES is not set
236# CONFIG_CANYONLANDS is not set
237# CONFIG_GLACIER is not set
238# CONFIG_REDWOOD is not set
239# CONFIG_EIGER is not set
240# CONFIG_YOSEMITE is not set
241CONFIG_ICON=y
242# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
243CONFIG_PPC44x_SIMPLE=y
244# CONFIG_PPC4xx_GPIO is not set
245CONFIG_440SPe=y
246CONFIG_STDBINUTILS=y
247# CONFIG_IPIC is not set
248# CONFIG_MPIC is not set
249# CONFIG_MPIC_WEIRD is not set
250# CONFIG_PPC_I8259 is not set
251# CONFIG_PPC_RTAS is not set
252# CONFIG_MMIO_NVRAM is not set
253# CONFIG_PPC_MPC106 is not set
254# CONFIG_PPC_970_NAP is not set
255# CONFIG_PPC_INDIRECT_IO is not set
256# CONFIG_GENERIC_IOMAP is not set
257# CONFIG_CPU_FREQ is not set
258# CONFIG_FSL_ULI1575 is not set
259# CONFIG_SIMPLE_GPIO is not set
260
261#
262# Kernel options
263#
264CONFIG_HIGHMEM=y
265# CONFIG_NO_HZ is not set
266# CONFIG_HIGH_RES_TIMERS is not set
267CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
268# CONFIG_HZ_100 is not set
269CONFIG_HZ_250=y
270# CONFIG_HZ_300 is not set
271# CONFIG_HZ_1000 is not set
272CONFIG_HZ=250
273# CONFIG_SCHED_HRTICK is not set
274CONFIG_PREEMPT_NONE=y
275# CONFIG_PREEMPT_VOLUNTARY is not set
276# CONFIG_PREEMPT is not set
277CONFIG_BINFMT_ELF=y
278# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
279# CONFIG_HAVE_AOUT is not set
280# CONFIG_BINFMT_MISC is not set
281# CONFIG_MATH_EMULATION is not set
282# CONFIG_IOMMU_HELPER is not set
283# CONFIG_SWIOTLB is not set
284CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
285CONFIG_ARCH_HAS_WALK_MEMORY=y
286CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
287CONFIG_SPARSE_IRQ=y
288CONFIG_MAX_ACTIVE_REGIONS=32
289CONFIG_ARCH_FLATMEM_ENABLE=y
290CONFIG_ARCH_POPULATES_NODE_MAP=y
291CONFIG_SELECT_MEMORY_MODEL=y
292CONFIG_FLATMEM_MANUAL=y
293# CONFIG_DISCONTIGMEM_MANUAL is not set
294# CONFIG_SPARSEMEM_MANUAL is not set
295CONFIG_FLATMEM=y
296CONFIG_FLAT_NODE_MEM_MAP=y
297CONFIG_PAGEFLAGS_EXTENDED=y
298CONFIG_SPLIT_PTLOCK_CPUS=4
299CONFIG_MIGRATION=y
300CONFIG_PHYS_ADDR_T_64BIT=y
301CONFIG_ZONE_DMA_FLAG=1
302CONFIG_BOUNCE=y
303CONFIG_VIRT_TO_BUS=y
304# CONFIG_KSM is not set
305CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
306CONFIG_PPC_4K_PAGES=y
307# CONFIG_PPC_16K_PAGES is not set
308# CONFIG_PPC_64K_PAGES is not set
309# CONFIG_PPC_256K_PAGES is not set
310CONFIG_FORCE_MAX_ZONEORDER=11
311CONFIG_PROC_DEVICETREE=y
312CONFIG_CMDLINE_BOOL=y
313CONFIG_CMDLINE=""
314CONFIG_EXTRA_TARGETS=""
315# CONFIG_ARCH_HAS_NMI_WATCHDOG is not set
316CONFIG_SECCOMP=y
317CONFIG_ISA_DMA_API=y
318
319#
320# Bus options
321#
322CONFIG_ZONE_DMA=y
323CONFIG_NEED_DMA_MAP_STATE=y
324CONFIG_PPC_INDIRECT_PCI=y
325CONFIG_4xx_SOC=y
326CONFIG_PPC_PCI_CHOICE=y
327CONFIG_PCI=y
328CONFIG_PCI_DOMAINS=y
329CONFIG_PCI_SYSCALL=y
330CONFIG_PCIEPORTBUS=y
331CONFIG_PCIEAER=y
332# CONFIG_PCIE_ECRC is not set
333# CONFIG_PCIEAER_INJECT is not set
334# CONFIG_PCIEASPM is not set
335CONFIG_ARCH_SUPPORTS_MSI=y
336# CONFIG_PCI_MSI is not set
337# CONFIG_PCI_DEBUG is not set
338# CONFIG_PCI_STUB is not set
339# CONFIG_PCI_IOV is not set
340# CONFIG_PCCARD is not set
341# CONFIG_HOTPLUG_PCI is not set
342# CONFIG_HAS_RAPIDIO is not set
343
344#
345# Advanced setup
346#
347# CONFIG_ADVANCED_OPTIONS is not set
348
349#
350# Default settings for advanced configuration options are used
351#
352CONFIG_LOWMEM_SIZE=0x30000000
353CONFIG_PAGE_OFFSET=0xc0000000
354CONFIG_KERNEL_START=0xc0000000
355CONFIG_PHYSICAL_START=0x00000000
356CONFIG_TASK_SIZE=0xc0000000
357CONFIG_CONSISTENT_SIZE=0x00200000
358CONFIG_NET=y
359
360#
361# Networking options
362#
363CONFIG_PACKET=y
364CONFIG_UNIX=y
365# CONFIG_NET_KEY is not set
366CONFIG_INET=y
367# CONFIG_IP_MULTICAST is not set
368# CONFIG_IP_ADVANCED_ROUTER is not set
369CONFIG_IP_FIB_HASH=y
370CONFIG_IP_PNP=y
371CONFIG_IP_PNP_DHCP=y
372CONFIG_IP_PNP_BOOTP=y
373# CONFIG_IP_PNP_RARP is not set
374# CONFIG_NET_IPIP is not set
375# CONFIG_NET_IPGRE is not set
376# CONFIG_ARPD is not set
377# CONFIG_SYN_COOKIES is not set
378# CONFIG_INET_AH is not set
379# CONFIG_INET_ESP is not set
380# CONFIG_INET_IPCOMP is not set
381# CONFIG_INET_XFRM_TUNNEL is not set
382# CONFIG_INET_TUNNEL is not set
383# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
384# CONFIG_INET_XFRM_MODE_TUNNEL is not set
385# CONFIG_INET_XFRM_MODE_BEET is not set
386# CONFIG_INET_LRO is not set
387CONFIG_INET_DIAG=y
388CONFIG_INET_TCP_DIAG=y
389# CONFIG_TCP_CONG_ADVANCED is not set
390CONFIG_TCP_CONG_CUBIC=y
391CONFIG_DEFAULT_TCP_CONG="cubic"
392# CONFIG_TCP_MD5SIG is not set
393# CONFIG_IPV6 is not set
394# CONFIG_NETWORK_SECMARK is not set
395# CONFIG_NETFILTER is not set
396# CONFIG_IP_DCCP is not set
397# CONFIG_IP_SCTP is not set
398# CONFIG_RDS is not set
399# CONFIG_TIPC is not set
400# CONFIG_ATM is not set
401# CONFIG_BRIDGE is not set
402# CONFIG_NET_DSA is not set
403# CONFIG_VLAN_8021Q is not set
404# CONFIG_DECNET is not set
405# CONFIG_LLC2 is not set
406# CONFIG_IPX is not set
407# CONFIG_ATALK is not set
408# CONFIG_X25 is not set
409# CONFIG_LAPB is not set
410# CONFIG_ECONET is not set
411# CONFIG_WAN_ROUTER is not set
412# CONFIG_PHONET is not set
413# CONFIG_IEEE802154 is not set
414# CONFIG_NET_SCHED is not set
415# CONFIG_DCB is not set
416
417#
418# Network testing
419#
420# CONFIG_NET_PKTGEN is not set
421# CONFIG_HAMRADIO is not set
422# CONFIG_CAN is not set
423# CONFIG_IRDA is not set
424# CONFIG_BT is not set
425# CONFIG_AF_RXRPC is not set
426CONFIG_WIRELESS=y
427# CONFIG_CFG80211 is not set
428# CONFIG_LIB80211 is not set
429
430#
431# CFG80211 needs to be enabled for MAC80211
432#
433# CONFIG_WIMAX is not set
434# CONFIG_RFKILL is not set
435# CONFIG_NET_9P is not set
436
437#
438# Device Drivers
439#
440
441#
442# Generic Driver Options
443#
444CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
445# CONFIG_DEVTMPFS is not set
446CONFIG_STANDALONE=y
447CONFIG_PREVENT_FIRMWARE_BUILD=y
448CONFIG_FW_LOADER=y
449CONFIG_FIRMWARE_IN_KERNEL=y
450CONFIG_EXTRA_FIRMWARE=""
451# CONFIG_DEBUG_DRIVER is not set
452# CONFIG_DEBUG_DEVRES is not set
453# CONFIG_SYS_HYPERVISOR is not set
454CONFIG_CONNECTOR=y
455CONFIG_PROC_EVENTS=y
456CONFIG_MTD=y
457# CONFIG_MTD_DEBUG is not set
458# CONFIG_MTD_TESTS is not set
459# CONFIG_MTD_CONCAT is not set
460CONFIG_MTD_PARTITIONS=y
461# CONFIG_MTD_REDBOOT_PARTS is not set
462CONFIG_MTD_CMDLINE_PARTS=y
463CONFIG_MTD_OF_PARTS=y
464# CONFIG_MTD_AR7_PARTS is not set
465
466#
467# User Modules And Translation Layers
468#
469CONFIG_MTD_CHAR=y
470CONFIG_MTD_BLKDEVS=y
471CONFIG_MTD_BLOCK=y
472# CONFIG_FTL is not set
473# CONFIG_NFTL is not set
474# CONFIG_INFTL is not set
475# CONFIG_RFD_FTL is not set
476# CONFIG_SSFDC is not set
477# CONFIG_MTD_OOPS is not set
478
479#
480# RAM/ROM/Flash chip drivers
481#
482CONFIG_MTD_CFI=y
483# CONFIG_MTD_JEDECPROBE is not set
484CONFIG_MTD_GEN_PROBE=y
485# CONFIG_MTD_CFI_ADV_OPTIONS is not set
486CONFIG_MTD_MAP_BANK_WIDTH_1=y
487CONFIG_MTD_MAP_BANK_WIDTH_2=y
488CONFIG_MTD_MAP_BANK_WIDTH_4=y
489# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
490# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
491# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
492CONFIG_MTD_CFI_I1=y
493CONFIG_MTD_CFI_I2=y
494# CONFIG_MTD_CFI_I4 is not set
495# CONFIG_MTD_CFI_I8 is not set
496# CONFIG_MTD_CFI_INTELEXT is not set
497CONFIG_MTD_CFI_AMDSTD=y
498# CONFIG_MTD_CFI_STAA is not set
499CONFIG_MTD_CFI_UTIL=y
500# CONFIG_MTD_RAM is not set
501# CONFIG_MTD_ROM is not set
502# CONFIG_MTD_ABSENT is not set
503
504#
505# Mapping drivers for chip access
506#
507# CONFIG_MTD_COMPLEX_MAPPINGS is not set
508# CONFIG_MTD_PHYSMAP is not set
509CONFIG_MTD_PHYSMAP_OF=y
510# CONFIG_MTD_INTEL_VR_NOR is not set
511# CONFIG_MTD_PLATRAM is not set
512
513#
514# Self-contained MTD device drivers
515#
516# CONFIG_MTD_PMC551 is not set
517# CONFIG_MTD_SLRAM is not set
518# CONFIG_MTD_PHRAM is not set
519# CONFIG_MTD_MTDRAM is not set
520# CONFIG_MTD_BLOCK2MTD is not set
521
522#
523# Disk-On-Chip Device Drivers
524#
525# CONFIG_MTD_DOC2000 is not set
526# CONFIG_MTD_DOC2001 is not set
527# CONFIG_MTD_DOC2001PLUS is not set
528# CONFIG_MTD_NAND is not set
529# CONFIG_MTD_ONENAND is not set
530
531#
532# LPDDR flash memory drivers
533#
534# CONFIG_MTD_LPDDR is not set
535
536#
537# UBI - Unsorted block images
538#
539# CONFIG_MTD_UBI is not set
540CONFIG_OF_FLATTREE=y
541CONFIG_OF_DYNAMIC=y
542CONFIG_OF_DEVICE=y
543CONFIG_OF_I2C=y
544# CONFIG_PARPORT is not set
545CONFIG_BLK_DEV=y
546# CONFIG_BLK_DEV_FD is not set
547# CONFIG_BLK_CPQ_DA is not set
548# CONFIG_BLK_CPQ_CISS_DA is not set
549# CONFIG_BLK_DEV_DAC960 is not set
550# CONFIG_BLK_DEV_UMEM is not set
551# CONFIG_BLK_DEV_COW_COMMON is not set
552# CONFIG_BLK_DEV_LOOP is not set
553# CONFIG_BLK_DEV_DRBD is not set
554# CONFIG_BLK_DEV_NBD is not set
555# CONFIG_BLK_DEV_SX8 is not set
556CONFIG_BLK_DEV_RAM=y
557CONFIG_BLK_DEV_RAM_COUNT=16
558CONFIG_BLK_DEV_RAM_SIZE=35000
559# CONFIG_BLK_DEV_XIP is not set
560# CONFIG_CDROM_PKTCDVD is not set
561# CONFIG_ATA_OVER_ETH is not set
562CONFIG_XILINX_SYSACE=y
563# CONFIG_BLK_DEV_HD is not set
564# CONFIG_MISC_DEVICES is not set
565CONFIG_HAVE_IDE=y
566# CONFIG_IDE is not set
567
568#
569# SCSI device support
570#
571CONFIG_SCSI_MOD=y
572# CONFIG_RAID_ATTRS is not set
573CONFIG_SCSI=y
574CONFIG_SCSI_DMA=y
575# CONFIG_SCSI_TGT is not set
576# CONFIG_SCSI_NETLINK is not set
577CONFIG_SCSI_PROC_FS=y
578
579#
580# SCSI support type (disk, tape, CD-ROM)
581#
582CONFIG_BLK_DEV_SD=y
583# CONFIG_CHR_DEV_ST is not set
584# CONFIG_CHR_DEV_OSST is not set
585# CONFIG_BLK_DEV_SR is not set
586# CONFIG_CHR_DEV_SG is not set
587# CONFIG_CHR_DEV_SCH is not set
588# CONFIG_SCSI_MULTI_LUN is not set
589CONFIG_SCSI_CONSTANTS=y
590CONFIG_SCSI_LOGGING=y
591# CONFIG_SCSI_SCAN_ASYNC is not set
592CONFIG_SCSI_WAIT_SCAN=m
593
594#
595# SCSI Transports
596#
597# CONFIG_SCSI_SPI_ATTRS is not set
598# CONFIG_SCSI_FC_ATTRS is not set
599# CONFIG_SCSI_ISCSI_ATTRS is not set
600CONFIG_SCSI_SAS_ATTRS=y
601# CONFIG_SCSI_SAS_LIBSAS is not set
602# CONFIG_SCSI_SRP_ATTRS is not set
603# CONFIG_SCSI_LOWLEVEL is not set
604# CONFIG_SCSI_DH is not set
605# CONFIG_SCSI_OSD_INITIATOR is not set
606# CONFIG_ATA is not set
607# CONFIG_MD is not set
608CONFIG_FUSION=y
609# CONFIG_FUSION_SPI is not set
610# CONFIG_FUSION_FC is not set
611CONFIG_FUSION_SAS=y
612CONFIG_FUSION_MAX_SGE=128
613CONFIG_FUSION_CTL=y
614CONFIG_FUSION_LOGGING=y
615
616#
617# IEEE 1394 (FireWire) support
618#
619
620#
621# You can enable one or both FireWire driver stacks.
622#
623
624#
625# The newer stack is recommended.
626#
627# CONFIG_FIREWIRE is not set
628# CONFIG_IEEE1394 is not set
629# CONFIG_I2O is not set
630# CONFIG_MACINTOSH_DRIVERS is not set
631CONFIG_NETDEVICES=y
632# CONFIG_DUMMY is not set
633# CONFIG_BONDING is not set
634# CONFIG_MACVLAN is not set
635# CONFIG_EQUALIZER is not set
636# CONFIG_TUN is not set
637# CONFIG_VETH is not set
638# CONFIG_ARCNET is not set
639# CONFIG_PHYLIB is not set
640CONFIG_NET_ETHERNET=y
641# CONFIG_MII is not set
642# CONFIG_HAPPYMEAL is not set
643# CONFIG_SUNGEM is not set
644# CONFIG_CASSINI is not set
645# CONFIG_NET_VENDOR_3COM is not set
646# CONFIG_ETHOC is not set
647# CONFIG_DNET is not set
648# CONFIG_NET_TULIP is not set
649# CONFIG_HP100 is not set
650CONFIG_IBM_NEW_EMAC=y
651CONFIG_IBM_NEW_EMAC_RXB=128
652CONFIG_IBM_NEW_EMAC_TXB=64
653CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
654CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
655CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
656# CONFIG_IBM_NEW_EMAC_DEBUG is not set
657# CONFIG_IBM_NEW_EMAC_ZMII is not set
658# CONFIG_IBM_NEW_EMAC_RGMII is not set
659# CONFIG_IBM_NEW_EMAC_TAH is not set
660CONFIG_IBM_NEW_EMAC_EMAC4=y
661# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
662# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
663# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
664# CONFIG_NET_PCI is not set
665# CONFIG_B44 is not set
666# CONFIG_KS8842 is not set
667# CONFIG_KS8851_MLL is not set
668# CONFIG_ATL2 is not set
669# CONFIG_XILINX_EMACLITE is not set
670# CONFIG_NETDEV_1000 is not set
671# CONFIG_NETDEV_10000 is not set
672# CONFIG_TR is not set
673# CONFIG_WLAN is not set
674
675#
676# Enable WiMAX (Networking options) to see the WiMAX drivers
677#
678# CONFIG_WAN is not set
679# CONFIG_FDDI is not set
680# CONFIG_HIPPI is not set
681# CONFIG_PPP is not set
682# CONFIG_SLIP is not set
683# CONFIG_NET_FC is not set
684# CONFIG_NETCONSOLE is not set
685# CONFIG_NETPOLL is not set
686# CONFIG_NET_POLL_CONTROLLER is not set
687# CONFIG_VMXNET3 is not set
688# CONFIG_ISDN is not set
689# CONFIG_PHONE is not set
690
691#
692# Input device support
693#
694CONFIG_INPUT=y
695# CONFIG_INPUT_FF_MEMLESS is not set
696# CONFIG_INPUT_POLLDEV is not set
697# CONFIG_INPUT_SPARSEKMAP is not set
698
699#
700# Userland interfaces
701#
702CONFIG_INPUT_MOUSEDEV=y
703CONFIG_INPUT_MOUSEDEV_PSAUX=y
704CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
705CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
706# CONFIG_INPUT_JOYDEV is not set
707# CONFIG_INPUT_EVDEV is not set
708# CONFIG_INPUT_EVBUG is not set
709
710#
711# Input Device Drivers
712#
713CONFIG_INPUT_KEYBOARD=y
714# CONFIG_KEYBOARD_ADP5588 is not set
715CONFIG_KEYBOARD_ATKBD=y
716# CONFIG_QT2160 is not set
717# CONFIG_KEYBOARD_LKKBD is not set
718# CONFIG_KEYBOARD_MAX7359 is not set
719# CONFIG_KEYBOARD_NEWTON is not set
720# CONFIG_KEYBOARD_OPENCORES is not set
721# CONFIG_KEYBOARD_STOWAWAY is not set
722# CONFIG_KEYBOARD_SUNKBD is not set
723# CONFIG_KEYBOARD_XTKBD is not set
724CONFIG_INPUT_MOUSE=y
725CONFIG_MOUSE_PS2=y
726# CONFIG_MOUSE_PS2_ALPS is not set
727# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
728# CONFIG_MOUSE_PS2_SYNAPTICS is not set
729# CONFIG_MOUSE_PS2_TRACKPOINT is not set
730# CONFIG_MOUSE_PS2_ELANTECH is not set
731# CONFIG_MOUSE_PS2_SENTELIC is not set
732# CONFIG_MOUSE_PS2_TOUCHKIT is not set
733# CONFIG_MOUSE_SERIAL is not set
734# CONFIG_MOUSE_VSXXXAA is not set
735# CONFIG_MOUSE_SYNAPTICS_I2C is not set
736# CONFIG_INPUT_JOYSTICK is not set
737# CONFIG_INPUT_TABLET is not set
738# CONFIG_INPUT_TOUCHSCREEN is not set
739# CONFIG_INPUT_MISC is not set
740
741#
742# Hardware I/O ports
743#
744CONFIG_SERIO=y
745CONFIG_SERIO_I8042=y
746CONFIG_SERIO_SERPORT=y
747# CONFIG_SERIO_PCIPS2 is not set
748CONFIG_SERIO_LIBPS2=y
749# CONFIG_SERIO_RAW is not set
750# CONFIG_SERIO_XILINX_XPS_PS2 is not set
751# CONFIG_SERIO_ALTERA_PS2 is not set
752# CONFIG_GAMEPORT is not set
753
754#
755# Character devices
756#
757CONFIG_VT=y
758CONFIG_CONSOLE_TRANSLATIONS=y
759CONFIG_VT_CONSOLE=y
760CONFIG_HW_CONSOLE=y
761# CONFIG_VT_HW_CONSOLE_BINDING is not set
762CONFIG_DEVKMEM=y
763# CONFIG_SERIAL_NONSTANDARD is not set
764# CONFIG_NOZOMI is not set
765
766#
767# Serial drivers
768#
769CONFIG_SERIAL_8250=y
770CONFIG_SERIAL_8250_CONSOLE=y
771# CONFIG_SERIAL_8250_PCI is not set
772CONFIG_SERIAL_8250_NR_UARTS=4
773CONFIG_SERIAL_8250_RUNTIME_UARTS=4
774CONFIG_SERIAL_8250_EXTENDED=y
775# CONFIG_SERIAL_8250_MANY_PORTS is not set
776CONFIG_SERIAL_8250_SHARE_IRQ=y
777# CONFIG_SERIAL_8250_DETECT_IRQ is not set
778# CONFIG_SERIAL_8250_RSA is not set
779
780#
781# Non-8250 serial port support
782#
783# CONFIG_SERIAL_UARTLITE is not set
784CONFIG_SERIAL_CORE=y
785CONFIG_SERIAL_CORE_CONSOLE=y
786# CONFIG_SERIAL_JSM is not set
787CONFIG_SERIAL_OF_PLATFORM=y
788# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
789# CONFIG_SERIAL_TIMBERDALE is not set
790# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
791CONFIG_UNIX98_PTYS=y
792# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
793CONFIG_LEGACY_PTYS=y
794CONFIG_LEGACY_PTY_COUNT=256
795# CONFIG_HVC_UDBG is not set
796# CONFIG_IPMI_HANDLER is not set
797# CONFIG_HW_RANDOM is not set
798# CONFIG_NVRAM is not set
799# CONFIG_R3964 is not set
800# CONFIG_APPLICOM is not set
801# CONFIG_RAW_DRIVER is not set
802# CONFIG_BOOTCOUNT is not set
803# CONFIG_DISPLAY_PDSP1880 is not set
804# CONFIG_MUCMC52_IO is not set
805# CONFIG_UC101_IO is not set
806# CONFIG_SRAM is not set
807# CONFIG_TCG_TPM is not set
808CONFIG_DEVPORT=y
809CONFIG_I2C=y
810CONFIG_I2C_BOARDINFO=y
811CONFIG_I2C_COMPAT=y
812CONFIG_I2C_CHARDEV=y
813CONFIG_I2C_HELPER_AUTO=y
814
815#
816# I2C Hardware Bus support
817#
818
819#
820# PC SMBus host controller drivers
821#
822# CONFIG_I2C_ALI1535 is not set
823# CONFIG_I2C_ALI1563 is not set
824# CONFIG_I2C_ALI15X3 is not set
825# CONFIG_I2C_AMD756 is not set
826# CONFIG_I2C_AMD8111 is not set
827# CONFIG_I2C_I801 is not set
828# CONFIG_I2C_ISCH is not set
829# CONFIG_I2C_PIIX4 is not set
830# CONFIG_I2C_NFORCE2 is not set
831# CONFIG_I2C_SIS5595 is not set
832# CONFIG_I2C_SIS630 is not set
833# CONFIG_I2C_SIS96X is not set
834# CONFIG_I2C_VIA is not set
835# CONFIG_I2C_VIAPRO is not set
836
837#
838# I2C system bus drivers (mostly embedded / system-on-chip)
839#
840CONFIG_I2C_IBM_IIC=y
841# CONFIG_I2C_MPC is not set
842# CONFIG_I2C_OCORES is not set
843# CONFIG_I2C_SIMTEC is not set
844# CONFIG_I2C_XILINX is not set
845
846#
847# External I2C/SMBus adapter drivers
848#
849# CONFIG_I2C_PARPORT_LIGHT is not set
850# CONFIG_I2C_TAOS_EVM is not set
851
852#
853# Other I2C/SMBus bus drivers
854#
855# CONFIG_I2C_PCA_PLATFORM is not set
856# CONFIG_I2C_STUB is not set
857# CONFIG_I2C_DEBUG_CORE is not set
858# CONFIG_I2C_DEBUG_ALGO is not set
859# CONFIG_I2C_DEBUG_BUS is not set
860# CONFIG_SPI is not set
861
862#
863# PPS support
864#
865# CONFIG_PPS is not set
866CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
867# CONFIG_GPIOLIB is not set
868# CONFIG_W1 is not set
869# CONFIG_POWER_SUPPLY is not set
870# CONFIG_HWMON is not set
871# CONFIG_THERMAL is not set
872# CONFIG_WATCHDOG is not set
873CONFIG_SSB_POSSIBLE=y
874
875#
876# Sonics Silicon Backplane
877#
878# CONFIG_SSB is not set
879
880#
881# Multifunction device drivers
882#
883# CONFIG_MFD_CORE is not set
884# CONFIG_MFD_88PM860X is not set
885CONFIG_MFD_SM501=y
886# CONFIG_HTC_PASIC3 is not set
887# CONFIG_TWL4030_CORE is not set
888# CONFIG_MFD_TMIO is not set
889# CONFIG_PMIC_DA903X is not set
890# CONFIG_PMIC_ADP5520 is not set
891# CONFIG_MFD_MAX8925 is not set
892# CONFIG_MFD_WM8400 is not set
893# CONFIG_MFD_WM831X is not set
894# CONFIG_MFD_WM8350_I2C is not set
895# CONFIG_MFD_WM8994 is not set
896# CONFIG_MFD_PCF50633 is not set
897# CONFIG_AB3100_CORE is not set
898# CONFIG_LPC_SCH is not set
899# CONFIG_REGULATOR is not set
900# CONFIG_MEDIA_SUPPORT is not set
901
902#
903# Graphics support
904#
905# CONFIG_AGP is not set
906CONFIG_VGA_ARB=y
907CONFIG_VGA_ARB_MAX_GPUS=16
908# CONFIG_DRM is not set
909# CONFIG_VGASTATE is not set
910CONFIG_VIDEO_OUTPUT_CONTROL=m
911CONFIG_FB=y
912# CONFIG_FIRMWARE_EDID is not set
913# CONFIG_FB_DDC is not set
914# CONFIG_FB_BOOT_VESA_SUPPORT is not set
915CONFIG_FB_CFB_FILLRECT=y
916CONFIG_FB_CFB_COPYAREA=y
917CONFIG_FB_CFB_IMAGEBLIT=y
918# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
919# CONFIG_FB_SYS_FILLRECT is not set
920# CONFIG_FB_SYS_COPYAREA is not set
921# CONFIG_FB_SYS_IMAGEBLIT is not set
922# CONFIG_FB_FOREIGN_ENDIAN is not set
923# CONFIG_FB_SYS_FOPS is not set
924# CONFIG_FB_SVGALIB is not set
925# CONFIG_FB_MACMODES is not set
926# CONFIG_FB_BACKLIGHT is not set
927# CONFIG_FB_MODE_HELPERS is not set
928# CONFIG_FB_TILEBLITTING is not set
929
930#
931# Frame buffer hardware drivers
932#
933# CONFIG_FB_CIRRUS is not set
934# CONFIG_FB_PM2 is not set
935# CONFIG_FB_CYBER2000 is not set
936# CONFIG_FB_OF is not set
937# CONFIG_FB_CT65550 is not set
938# CONFIG_FB_ASILIANT is not set
939# CONFIG_FB_IMSTT is not set
940# CONFIG_FB_VGA16 is not set
941# CONFIG_FB_UVESA is not set
942# CONFIG_FB_S1D13XXX is not set
943# CONFIG_FB_NVIDIA is not set
944# CONFIG_FB_RIVA is not set
945# CONFIG_FB_MATROX is not set
946# CONFIG_FB_RADEON is not set
947# CONFIG_FB_ATY128 is not set
948# CONFIG_FB_ATY is not set
949# CONFIG_FB_S3 is not set
950# CONFIG_FB_SAVAGE is not set
951# CONFIG_FB_SIS is not set
952# CONFIG_FB_VIA is not set
953# CONFIG_FB_NEOMAGIC is not set
954# CONFIG_FB_KYRO is not set
955# CONFIG_FB_3DFX is not set
956# CONFIG_FB_VOODOO1 is not set
957# CONFIG_FB_VT8623 is not set
958# CONFIG_FB_TRIDENT is not set
959# CONFIG_FB_ARK is not set
960# CONFIG_FB_PM3 is not set
961# CONFIG_FB_CARMINE is not set
962CONFIG_FB_SM501=y
963# CONFIG_FB_IBM_GXT4500 is not set
964# CONFIG_FB_VIRTUAL is not set
965# CONFIG_FB_METRONOME is not set
966# CONFIG_FB_MB862XX is not set
967# CONFIG_FB_BROADSHEET is not set
968# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
969
970#
971# Display device support
972#
973# CONFIG_DISPLAY_SUPPORT is not set
974
975#
976# Console display driver support
977#
978CONFIG_DUMMY_CONSOLE=y
979CONFIG_FRAMEBUFFER_CONSOLE=y
980# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
981# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
982# CONFIG_FONTS is not set
983CONFIG_FONT_8x8=y
984CONFIG_FONT_8x16=y
985CONFIG_LOGO=y
986# CONFIG_LOGO_LINUX_MONO is not set
987# CONFIG_LOGO_LINUX_VGA16 is not set
988CONFIG_LOGO_LINUX_CLUT224=y
989# CONFIG_SOUND is not set
990CONFIG_HID_SUPPORT=y
991CONFIG_HID=y
992# CONFIG_HIDRAW is not set
993# CONFIG_HID_PID is not set
994
995#
996# Special HID drivers
997#
998# CONFIG_USB_SUPPORT is not set
999# CONFIG_UWB is not set
1000# CONFIG_MMC is not set
1001# CONFIG_MEMSTICK is not set
1002# CONFIG_NEW_LEDS is not set
1003# CONFIG_ACCESSIBILITY is not set
1004# CONFIG_INFINIBAND is not set
1005# CONFIG_EDAC is not set
1006CONFIG_RTC_LIB=y
1007CONFIG_RTC_CLASS=y
1008CONFIG_RTC_HCTOSYS=y
1009CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1010# CONFIG_RTC_DEBUG is not set
1011
1012#
1013# RTC interfaces
1014#
1015CONFIG_RTC_INTF_SYSFS=y
1016CONFIG_RTC_INTF_PROC=y
1017CONFIG_RTC_INTF_DEV=y
1018# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1019# CONFIG_RTC_DRV_TEST is not set
1020
1021#
1022# I2C RTC drivers
1023#
1024CONFIG_RTC_DRV_DS1307=y
1025# CONFIG_RTC_DRV_DS1374 is not set
1026# CONFIG_RTC_DRV_DS1672 is not set
1027# CONFIG_RTC_DRV_MAX6900 is not set
1028# CONFIG_RTC_DRV_RS5C372 is not set
1029# CONFIG_RTC_DRV_ISL1208 is not set
1030# CONFIG_RTC_DRV_X1205 is not set
1031# CONFIG_RTC_DRV_PCF8563 is not set
1032# CONFIG_RTC_DRV_PCF8583 is not set
1033# CONFIG_RTC_DRV_M41T80 is not set
1034# CONFIG_RTC_DRV_BQ32K is not set
1035# CONFIG_RTC_DRV_S35390A is not set
1036# CONFIG_RTC_DRV_FM3130 is not set
1037# CONFIG_RTC_DRV_RX8581 is not set
1038# CONFIG_RTC_DRV_RX8025 is not set
1039
1040#
1041# SPI RTC drivers
1042#
1043
1044#
1045# Platform RTC drivers
1046#
1047# CONFIG_RTC_DRV_CMOS is not set
1048# CONFIG_RTC_DRV_DS1286 is not set
1049# CONFIG_RTC_DRV_DS1511 is not set
1050# CONFIG_RTC_DRV_DS1553 is not set
1051# CONFIG_RTC_DRV_DS1742 is not set
1052# CONFIG_RTC_DRV_STK17TA8 is not set
1053# CONFIG_RTC_DRV_M48T86 is not set
1054# CONFIG_RTC_DRV_M48T35 is not set
1055# CONFIG_RTC_DRV_M48T59 is not set
1056# CONFIG_RTC_DRV_MSM6242 is not set
1057# CONFIG_RTC_DRV_BQ4802 is not set
1058# CONFIG_RTC_DRV_RP5C01 is not set
1059# CONFIG_RTC_DRV_V3020 is not set
1060
1061#
1062# on-CPU RTC drivers
1063#
1064# CONFIG_RTC_DRV_GENERIC is not set
1065# CONFIG_DMADEVICES is not set
1066# CONFIG_AUXDISPLAY is not set
1067# CONFIG_UIO is not set
1068
1069#
1070# TI VLYNQ
1071#
1072# CONFIG_STAGING is not set
1073
1074#
1075# File systems
1076#
1077CONFIG_EXT2_FS=y
1078# CONFIG_EXT2_FS_XATTR is not set
1079# CONFIG_EXT2_FS_XIP is not set
1080CONFIG_EXT3_FS=y
1081# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1082CONFIG_EXT3_FS_XATTR=y
1083# CONFIG_EXT3_FS_POSIX_ACL is not set
1084# CONFIG_EXT3_FS_SECURITY is not set
1085# CONFIG_EXT4_FS is not set
1086CONFIG_JBD=y
1087CONFIG_FS_MBCACHE=y
1088# CONFIG_REISERFS_FS is not set
1089# CONFIG_JFS_FS is not set
1090# CONFIG_FS_POSIX_ACL is not set
1091# CONFIG_XFS_FS is not set
1092# CONFIG_GFS2_FS is not set
1093# CONFIG_OCFS2_FS is not set
1094# CONFIG_BTRFS_FS is not set
1095# CONFIG_NILFS2_FS is not set
1096CONFIG_FILE_LOCKING=y
1097CONFIG_FSNOTIFY=y
1098CONFIG_DNOTIFY=y
1099CONFIG_INOTIFY=y
1100CONFIG_INOTIFY_USER=y
1101# CONFIG_QUOTA is not set
1102# CONFIG_AUTOFS_FS is not set
1103# CONFIG_AUTOFS4_FS is not set
1104# CONFIG_FUSE_FS is not set
1105
1106#
1107# Caches
1108#
1109# CONFIG_FSCACHE is not set
1110
1111#
1112# CD-ROM/DVD Filesystems
1113#
1114# CONFIG_ISO9660_FS is not set
1115# CONFIG_UDF_FS is not set
1116
1117#
1118# DOS/FAT/NT Filesystems
1119#
1120CONFIG_FAT_FS=y
1121# CONFIG_MSDOS_FS is not set
1122CONFIG_VFAT_FS=y
1123CONFIG_FAT_DEFAULT_CODEPAGE=437
1124CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1125# CONFIG_NTFS_FS is not set
1126
1127#
1128# Pseudo filesystems
1129#
1130CONFIG_PROC_FS=y
1131CONFIG_PROC_KCORE=y
1132CONFIG_PROC_SYSCTL=y
1133CONFIG_PROC_PAGE_MONITOR=y
1134CONFIG_SYSFS=y
1135CONFIG_TMPFS=y
1136# CONFIG_TMPFS_POSIX_ACL is not set
1137# CONFIG_HUGETLB_PAGE is not set
1138# CONFIG_CONFIGFS_FS is not set
1139CONFIG_MISC_FILESYSTEMS=y
1140# CONFIG_ADFS_FS is not set
1141# CONFIG_AFFS_FS is not set
1142# CONFIG_HFS_FS is not set
1143# CONFIG_HFSPLUS_FS is not set
1144# CONFIG_BEFS_FS is not set
1145# CONFIG_BFS_FS is not set
1146# CONFIG_EFS_FS is not set
1147# CONFIG_JFFS2_FS is not set
1148# CONFIG_YAFFS_FS is not set
1149# CONFIG_LOGFS is not set
1150CONFIG_CRAMFS=y
1151# CONFIG_SQUASHFS is not set
1152# CONFIG_VXFS_FS is not set
1153# CONFIG_MINIX_FS is not set
1154# CONFIG_OMFS_FS is not set
1155# CONFIG_HPFS_FS is not set
1156# CONFIG_QNX4FS_FS is not set
1157# CONFIG_ROMFS_FS is not set
1158# CONFIG_SYSV_FS is not set
1159# CONFIG_UFS_FS is not set
1160CONFIG_NETWORK_FILESYSTEMS=y
1161CONFIG_NFS_FS=y
1162CONFIG_NFS_V3=y
1163# CONFIG_NFS_V3_ACL is not set
1164# CONFIG_NFS_V4 is not set
1165CONFIG_ROOT_NFS=y
1166# CONFIG_NFSD is not set
1167CONFIG_LOCKD=y
1168CONFIG_LOCKD_V4=y
1169CONFIG_NFS_COMMON=y
1170CONFIG_SUNRPC=y
1171# CONFIG_RPCSEC_GSS_KRB5 is not set
1172# CONFIG_RPCSEC_GSS_SPKM3 is not set
1173# CONFIG_SMB_FS is not set
1174# CONFIG_CEPH_FS is not set
1175# CONFIG_CIFS is not set
1176# CONFIG_NCP_FS is not set
1177# CONFIG_CODA_FS is not set
1178# CONFIG_AFS_FS is not set
1179
1180#
1181# Partition Types
1182#
1183# CONFIG_PARTITION_ADVANCED is not set
1184CONFIG_MSDOS_PARTITION=y
1185CONFIG_NLS=y
1186CONFIG_NLS_DEFAULT="iso8859-1"
1187CONFIG_NLS_CODEPAGE_437=y
1188# CONFIG_NLS_CODEPAGE_737 is not set
1189# CONFIG_NLS_CODEPAGE_775 is not set
1190CONFIG_NLS_CODEPAGE_850=y
1191# CONFIG_NLS_CODEPAGE_852 is not set
1192# CONFIG_NLS_CODEPAGE_855 is not set
1193# CONFIG_NLS_CODEPAGE_857 is not set
1194# CONFIG_NLS_CODEPAGE_860 is not set
1195# CONFIG_NLS_CODEPAGE_861 is not set
1196# CONFIG_NLS_CODEPAGE_862 is not set
1197# CONFIG_NLS_CODEPAGE_863 is not set
1198# CONFIG_NLS_CODEPAGE_864 is not set
1199# CONFIG_NLS_CODEPAGE_865 is not set
1200# CONFIG_NLS_CODEPAGE_866 is not set
1201# CONFIG_NLS_CODEPAGE_869 is not set
1202# CONFIG_NLS_CODEPAGE_936 is not set
1203# CONFIG_NLS_CODEPAGE_950 is not set
1204# CONFIG_NLS_CODEPAGE_932 is not set
1205# CONFIG_NLS_CODEPAGE_949 is not set
1206# CONFIG_NLS_CODEPAGE_874 is not set
1207# CONFIG_NLS_ISO8859_8 is not set
1208# CONFIG_NLS_CODEPAGE_1250 is not set
1209# CONFIG_NLS_CODEPAGE_1251 is not set
1210# CONFIG_NLS_ASCII is not set
1211CONFIG_NLS_ISO8859_1=y
1212# CONFIG_NLS_ISO8859_2 is not set
1213# CONFIG_NLS_ISO8859_3 is not set
1214# CONFIG_NLS_ISO8859_4 is not set
1215# CONFIG_NLS_ISO8859_5 is not set
1216# CONFIG_NLS_ISO8859_6 is not set
1217# CONFIG_NLS_ISO8859_7 is not set
1218# CONFIG_NLS_ISO8859_9 is not set
1219# CONFIG_NLS_ISO8859_13 is not set
1220# CONFIG_NLS_ISO8859_14 is not set
1221CONFIG_NLS_ISO8859_15=y
1222# CONFIG_NLS_KOI8_R is not set
1223# CONFIG_NLS_KOI8_U is not set
1224# CONFIG_NLS_UTF8 is not set
1225# CONFIG_DLM is not set
1226# CONFIG_BINARY_PRINTF is not set
1227
1228#
1229# Library routines
1230#
1231CONFIG_BITREVERSE=y
1232CONFIG_GENERIC_FIND_LAST_BIT=y
1233# CONFIG_CRC_CCITT is not set
1234# CONFIG_CRC16 is not set
1235# CONFIG_CRC_T10DIF is not set
1236# CONFIG_CRC_ITU_T is not set
1237CONFIG_CRC32=y
1238# CONFIG_CRC7 is not set
1239# CONFIG_LIBCRC32C is not set
1240CONFIG_ZLIB_INFLATE=y
1241CONFIG_DECOMPRESS_GZIP=y
1242CONFIG_HAS_IOMEM=y
1243CONFIG_HAS_IOPORT=y
1244CONFIG_HAS_DMA=y
1245CONFIG_HAVE_LMB=y
1246CONFIG_NLATTR=y
1247CONFIG_GENERIC_ATOMIC64=y
1248
1249#
1250# Kernel hacking
1251#
1252# CONFIG_PRINTK_TIME is not set
1253CONFIG_ENABLE_WARN_DEPRECATED=y
1254CONFIG_ENABLE_MUST_CHECK=y
1255CONFIG_FRAME_WARN=1024
1256CONFIG_MAGIC_SYSRQ=y
1257# CONFIG_STRIP_ASM_SYMS is not set
1258# CONFIG_UNUSED_SYMBOLS is not set
1259# CONFIG_DEBUG_FS is not set
1260# CONFIG_HEADERS_CHECK is not set
1261CONFIG_DEBUG_KERNEL=y
1262# CONFIG_DEBUG_SHIRQ is not set
1263CONFIG_DETECT_SOFTLOCKUP=y
1264# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1265CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1266CONFIG_DETECT_HUNG_TASK=y
1267# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1268CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1269CONFIG_SCHED_DEBUG=y
1270# CONFIG_SCHEDSTATS is not set
1271# CONFIG_TIMER_STATS is not set
1272# CONFIG_DEBUG_OBJECTS is not set
1273# CONFIG_SLUB_DEBUG_ON is not set
1274# CONFIG_SLUB_STATS is not set
1275# CONFIG_DEBUG_KMEMLEAK is not set
1276# CONFIG_DEBUG_RT_MUTEXES is not set
1277# CONFIG_RT_MUTEX_TESTER is not set
1278# CONFIG_DEBUG_SPINLOCK is not set
1279# CONFIG_DEBUG_MUTEXES is not set
1280# CONFIG_DEBUG_LOCK_ALLOC is not set
1281# CONFIG_PROVE_LOCKING is not set
1282# CONFIG_LOCK_STAT is not set
1283# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1284# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1285# CONFIG_DEBUG_KOBJECT is not set
1286# CONFIG_DEBUG_HIGHMEM is not set
1287# CONFIG_DEBUG_BUGVERBOSE is not set
1288# CONFIG_DEBUG_INFO is not set
1289# CONFIG_DEBUG_VM is not set
1290# CONFIG_DEBUG_WRITECOUNT is not set
1291# CONFIG_DEBUG_MEMORY_INIT is not set
1292# CONFIG_DEBUG_LIST is not set
1293# CONFIG_DEBUG_SG is not set
1294# CONFIG_DEBUG_NOTIFIERS is not set
1295# CONFIG_DEBUG_CREDENTIALS is not set
1296# CONFIG_RCU_TORTURE_TEST is not set
1297# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1298# CONFIG_BACKTRACE_SELF_TEST is not set
1299# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1300# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1301# CONFIG_FAULT_INJECTION is not set
1302# CONFIG_LATENCYTOP is not set
1303CONFIG_SYSCTL_SYSCALL_CHECK=y
1304# CONFIG_DEBUG_PAGEALLOC is not set
1305CONFIG_HAVE_FUNCTION_TRACER=y
1306CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1307CONFIG_HAVE_DYNAMIC_FTRACE=y
1308CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1309CONFIG_TRACING_SUPPORT=y
1310CONFIG_FTRACE=y
1311# CONFIG_FUNCTION_TRACER is not set
1312# CONFIG_IRQSOFF_TRACER is not set
1313# CONFIG_SCHED_TRACER is not set
1314# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1315# CONFIG_BOOT_TRACER is not set
1316CONFIG_BRANCH_PROFILE_NONE=y
1317# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1318# CONFIG_PROFILE_ALL_BRANCHES is not set
1319# CONFIG_STACK_TRACER is not set
1320# CONFIG_KMEMTRACE is not set
1321# CONFIG_WORKQUEUE_TRACER is not set
1322# CONFIG_BLK_DEV_IO_TRACE is not set
1323# CONFIG_DMA_API_DEBUG is not set
1324# CONFIG_SAMPLES is not set
1325CONFIG_HAVE_ARCH_KGDB=y
1326# CONFIG_KGDB is not set
1327# CONFIG_PPC_DISABLE_WERROR is not set
1328CONFIG_PPC_WERROR=y
1329CONFIG_PRINT_STACK_DEPTH=64
1330# CONFIG_DEBUG_STACKOVERFLOW is not set
1331# CONFIG_DEBUG_STACK_USAGE is not set
1332# CONFIG_CODE_PATCHING_SELFTEST is not set
1333# CONFIG_FTR_FIXUP_SELFTEST is not set
1334# CONFIG_MSI_BITMAP_SELFTEST is not set
1335# CONFIG_XMON is not set
1336# CONFIG_IRQSTACKS is not set
1337# CONFIG_BDI_SWITCH is not set
1338# CONFIG_PPC_EARLY_DEBUG is not set
1339
1340#
1341# Security options
1342#
1343# CONFIG_KEYS is not set
1344# CONFIG_SECURITY is not set
1345# CONFIG_SECURITYFS is not set
1346# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1347# CONFIG_DEFAULT_SECURITY_SMACK is not set
1348# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1349CONFIG_DEFAULT_SECURITY_DAC=y
1350CONFIG_DEFAULT_SECURITY=""
1351CONFIG_CRYPTO=y
1352
1353#
1354# Crypto core or helper
1355#
1356CONFIG_CRYPTO_ALGAPI=y
1357CONFIG_CRYPTO_ALGAPI2=y
1358CONFIG_CRYPTO_AEAD2=y
1359CONFIG_CRYPTO_BLKCIPHER=y
1360CONFIG_CRYPTO_BLKCIPHER2=y
1361CONFIG_CRYPTO_HASH=y
1362CONFIG_CRYPTO_HASH2=y
1363CONFIG_CRYPTO_RNG2=y
1364CONFIG_CRYPTO_PCOMP=y
1365CONFIG_CRYPTO_MANAGER=y
1366CONFIG_CRYPTO_MANAGER2=y
1367# CONFIG_CRYPTO_GF128MUL is not set
1368# CONFIG_CRYPTO_NULL is not set
1369CONFIG_CRYPTO_WORKQUEUE=y
1370# CONFIG_CRYPTO_CRYPTD is not set
1371# CONFIG_CRYPTO_AUTHENC is not set
1372# CONFIG_CRYPTO_TEST is not set
1373
1374#
1375# Authenticated Encryption with Associated Data
1376#
1377# CONFIG_CRYPTO_CCM is not set
1378# CONFIG_CRYPTO_GCM is not set
1379# CONFIG_CRYPTO_SEQIV is not set
1380
1381#
1382# Block modes
1383#
1384CONFIG_CRYPTO_CBC=y
1385# CONFIG_CRYPTO_CTR is not set
1386# CONFIG_CRYPTO_CTS is not set
1387CONFIG_CRYPTO_ECB=y
1388# CONFIG_CRYPTO_LRW is not set
1389CONFIG_CRYPTO_PCBC=y
1390# CONFIG_CRYPTO_XTS is not set
1391
1392#
1393# Hash modes
1394#
1395# CONFIG_CRYPTO_HMAC is not set
1396# CONFIG_CRYPTO_XCBC is not set
1397# CONFIG_CRYPTO_VMAC is not set
1398
1399#
1400# Digest
1401#
1402# CONFIG_CRYPTO_CRC32C is not set
1403# CONFIG_CRYPTO_GHASH is not set
1404# CONFIG_CRYPTO_MD4 is not set
1405CONFIG_CRYPTO_MD5=y
1406# CONFIG_CRYPTO_MICHAEL_MIC is not set
1407# CONFIG_CRYPTO_RMD128 is not set
1408# CONFIG_CRYPTO_RMD160 is not set
1409# CONFIG_CRYPTO_RMD256 is not set
1410# CONFIG_CRYPTO_RMD320 is not set
1411# CONFIG_CRYPTO_SHA1 is not set
1412# CONFIG_CRYPTO_SHA256 is not set
1413# CONFIG_CRYPTO_SHA512 is not set
1414# CONFIG_CRYPTO_TGR192 is not set
1415# CONFIG_CRYPTO_WP512 is not set
1416
1417#
1418# Ciphers
1419#
1420# CONFIG_CRYPTO_AES is not set
1421# CONFIG_CRYPTO_ANUBIS is not set
1422# CONFIG_CRYPTO_ARC4 is not set
1423# CONFIG_CRYPTO_BLOWFISH is not set
1424# CONFIG_CRYPTO_CAMELLIA is not set
1425# CONFIG_CRYPTO_CAST5 is not set
1426# CONFIG_CRYPTO_CAST6 is not set
1427CONFIG_CRYPTO_DES=y
1428# CONFIG_CRYPTO_FCRYPT is not set
1429# CONFIG_CRYPTO_KHAZAD is not set
1430# CONFIG_CRYPTO_SALSA20 is not set
1431# CONFIG_CRYPTO_SEED is not set
1432# CONFIG_CRYPTO_SERPENT is not set
1433# CONFIG_CRYPTO_TEA is not set
1434# CONFIG_CRYPTO_TWOFISH is not set
1435
1436#
1437# Compression
1438#
1439# CONFIG_CRYPTO_DEFLATE is not set
1440# CONFIG_CRYPTO_ZLIB is not set
1441# CONFIG_CRYPTO_LZO is not set
1442
1443#
1444# Random Number Generation
1445#
1446# CONFIG_CRYPTO_ANSI_CPRNG is not set
1447CONFIG_CRYPTO_HW=y
1448# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1449# CONFIG_CRYPTO_DEV_PPC4XX is not set
1450# CONFIG_PPC_CLOCK is not set
1451# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e3cba4e1eb34..b0b21134f61a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -70,6 +70,7 @@ struct pt_regs;
70extern int machine_check_generic(struct pt_regs *regs); 70extern int machine_check_generic(struct pt_regs *regs);
71extern int machine_check_4xx(struct pt_regs *regs); 71extern int machine_check_4xx(struct pt_regs *regs);
72extern int machine_check_440A(struct pt_regs *regs); 72extern int machine_check_440A(struct pt_regs *regs);
73extern int machine_check_e500mc(struct pt_regs *regs);
73extern int machine_check_e500(struct pt_regs *regs); 74extern int machine_check_e500(struct pt_regs *regs);
74extern int machine_check_e200(struct pt_regs *regs); 75extern int machine_check_e200(struct pt_regs *regs);
75extern int machine_check_47x(struct pt_regs *regs); 76extern int machine_check_47x(struct pt_regs *regs);
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index a6ca6da1430b..2a9cd74a841e 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -2,6 +2,18 @@
2#define _ASM_POWERPC_KEXEC_H 2#define _ASM_POWERPC_KEXEC_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifdef CONFIG_FSL_BOOKE
6
7/*
8 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
9 * and therefore we can only deal with memory within this range
10 */
11#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
12#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
13#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
14
15#else
16
5/* 17/*
6 * Maximum page that is mapped directly into kernel memory. 18 * Maximum page that is mapped directly into kernel memory.
7 * XXX: Since we copy virt we can use any page we allocate 19 * XXX: Since we copy virt we can use any page we allocate
@@ -21,6 +33,7 @@
21/* TASK_SIZE, probably left over from use_mm ?? */ 33/* TASK_SIZE, probably left over from use_mm ?? */
22#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE 34#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
23#endif 35#endif
36#endif
24 37
25#define KEXEC_CONTROL_PAGE_SIZE 4096 38#define KEXEC_CONTROL_PAGE_SIZE 4096
26 39
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 5304a37ba425..2360317179a9 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -4,6 +4,12 @@
4 * are not true Book E PowerPCs, they borrowed a number of features 4 * are not true Book E PowerPCs, they borrowed a number of features
5 * before Book E was finalized, and are included here as well. Unfortunatly, 5 * before Book E was finalized, and are included here as well. Unfortunatly,
6 * they sometimes used different locations than true Book E CPUs did. 6 * they sometimes used different locations than true Book E CPUs did.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
11 *
12 * Copyright 2009-2010 Freescale Semiconductor, Inc.
7 */ 13 */
8#ifdef __KERNEL__ 14#ifdef __KERNEL__
9#ifndef __ASM_POWERPC_REG_BOOKE_H__ 15#ifndef __ASM_POWERPC_REG_BOOKE_H__
@@ -88,6 +94,7 @@
88#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 94#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
89#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ 95#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
90#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ 96#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
97#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
91#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 98#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
92#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 99#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
93#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 100#define SPRN_MCSR 0x23C /* Machine Check Status Register */
@@ -196,8 +203,11 @@
196#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ 203#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
197 204
198#ifdef CONFIG_E500 205#ifdef CONFIG_E500
206/* All e500 */
199#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 207#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
200#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 208#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
209
210/* e500v1/v2 */
201#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 211#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
202#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 212#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
203#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 213#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
@@ -209,12 +219,20 @@
209#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 219#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
210#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 220#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
211 221
212/* e500 parts may set unused bits in MCSR; mask these off */ 222/* e500mc */
213#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \ 223#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
214 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \ 224#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */
215 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \ 225#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
216 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR) 226#define MCSR_MAV 0x00080000UL /* MCAR address valid */
227#define MCSR_MEA 0x00040000UL /* MCAR is effective address */
228#define MCSR_IF 0x00010000UL /* Instruction Fetch */
229#define MCSR_LD 0x00008000UL /* Load */
230#define MCSR_ST 0x00004000UL /* Store */
231#define MCSR_LDG 0x00002000UL /* Guarded Load */
232#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
233#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
217#endif 234#endif
235
218#ifdef CONFIG_E200 236#ifdef CONFIG_E200
219#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 237#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
220#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ 238#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
@@ -225,11 +243,6 @@
225#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 243#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
226#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 244#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
227 store or cache line push */ 245 store or cache line push */
228
229/* e200 parts may set unused bits in MCSR; mask these off */
230#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
231 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
232 MCSR_BUS_WRERR)
233#endif 246#endif
234 247
235/* Bit definitions for the DBSR. */ 248/* Bit definitions for the DBSR. */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 877326320e74..58d0572de6f9 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -57,8 +57,12 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
57obj-$(CONFIG_E500) += idle_e500.o 57obj-$(CONFIG_E500) += idle_e500.o
58obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o 58obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
59obj-$(CONFIG_TAU) += tau_6xx.o 59obj-$(CONFIG_TAU) += tau_6xx.o
60obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \ 60obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o
61 swsusp_$(CONFIG_WORD_SIZE).o 61ifeq ($(CONFIG_FSL_BOOKE),y)
62obj-$(CONFIG_HIBERNATION) += swsusp_booke.o
63else
64obj-$(CONFIG_HIBERNATION) += swsusp_$(CONFIG_WORD_SIZE).o
65endif
62obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o 66obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
63obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o 67obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
64obj-$(CONFIG_44x) += cpu_setup_44x.o 68obj-$(CONFIG_44x) += cpu_setup_44x.o
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 9556be903e96..87aa0f3c6047 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1840,7 +1840,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1840 .oprofile_cpu_type = "ppc/e500mc", 1840 .oprofile_cpu_type = "ppc/e500mc",
1841 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1841 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1842 .cpu_setup = __setup_cpu_e500mc, 1842 .cpu_setup = __setup_cpu_e500mc,
1843 .machine_check = machine_check_e500, 1843 .machine_check = machine_check_e500mc,
1844 .platform = "ppce500mc", 1844 .platform = "ppce500mc",
1845 }, 1845 },
1846 { /* default match */ 1846 { /* default match */
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 8c066d6a8e4b..b46f2e09bd81 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -163,6 +163,7 @@ static void crash_kexec_prepare_cpus(int cpu)
163} 163}
164 164
165/* wait for all the CPUs to hit real mode but timeout if they don't come in */ 165/* wait for all the CPUs to hit real mode but timeout if they don't come in */
166#ifdef CONFIG_PPC_STD_MMU_64
166static void crash_kexec_wait_realmode(int cpu) 167static void crash_kexec_wait_realmode(int cpu)
167{ 168{
168 unsigned int msecs; 169 unsigned int msecs;
@@ -187,6 +188,7 @@ static void crash_kexec_wait_realmode(int cpu)
187 } 188 }
188 mb(); 189 mb();
189} 190}
191#endif
190 192
191/* 193/*
192 * This function will be called by secondary cpus or by kexec cpu 194 * This function will be called by secondary cpus or by kexec cpu
@@ -445,7 +447,9 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
445 crash_kexec_prepare_cpus(crashing_cpu); 447 crash_kexec_prepare_cpus(crashing_cpu);
446 cpu_set(crashing_cpu, cpus_in_crash); 448 cpu_set(crashing_cpu, cpus_in_crash);
447 crash_kexec_stop_spus(); 449 crash_kexec_stop_spus();
450#ifdef CONFIG_PPC_STD_MMU_64
448 crash_kexec_wait_realmode(crashing_cpu); 451 crash_kexec_wait_realmode(crashing_cpu);
452#endif
449 if (ppc_md.kexec_cpu_down) 453 if (ppc_md.kexec_cpu_down)
450 ppc_md.kexec_cpu_down(1, 0); 454 ppc_md.kexec_cpu_down(1, 0);
451} 455}
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
new file mode 100644
index 000000000000..beb4d78a2304
--- /dev/null
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -0,0 +1,237 @@
1
2/* 1. Find the index of the entry we're executing in */
3 bl invstr /* Find our address */
4invstr: mflr r6 /* Make it accessible */
5 mfmsr r7
6 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
7 mfspr r7, SPRN_PID0
8 slwi r7,r7,16
9 or r7,r7,r4
10 mtspr SPRN_MAS6,r7
11 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
12 mfspr r7,SPRN_MAS1
13 andis. r7,r7,MAS1_VALID@h
14 bne match_TLB
15
16 mfspr r7,SPRN_MMUCFG
17 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
18 cmpwi r7,3
19 bne match_TLB /* skip if NPIDS != 3 */
20
21 mfspr r7,SPRN_PID1
22 slwi r7,r7,16
23 or r7,r7,r4
24 mtspr SPRN_MAS6,r7
25 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
26 mfspr r7,SPRN_MAS1
27 andis. r7,r7,MAS1_VALID@h
28 bne match_TLB
29 mfspr r7, SPRN_PID2
30 slwi r7,r7,16
31 or r7,r7,r4
32 mtspr SPRN_MAS6,r7
33 tlbsx 0,r6 /* Fall through, we had to match */
34
35match_TLB:
36 mfspr r7,SPRN_MAS0
37 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
38
39 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
40 oris r7,r7,MAS1_IPROT@h
41 mtspr SPRN_MAS1,r7
42 tlbwe
43
44/* 2. Invalidate all entries except the entry we're executing in */
45 mfspr r9,SPRN_TLB1CFG
46 andi. r9,r9,0xfff
47 li r6,0 /* Set Entry counter to 0 */
481: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
49 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
50 mtspr SPRN_MAS0,r7
51 tlbre
52 mfspr r7,SPRN_MAS1
53 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
54 cmpw r3,r6
55 beq skpinv /* Dont update the current execution TLB */
56 mtspr SPRN_MAS1,r7
57 tlbwe
58 isync
59skpinv: addi r6,r6,1 /* Increment */
60 cmpw r6,r9 /* Are we done? */
61 bne 1b /* If not, repeat */
62
63 /* Invalidate TLB0 */
64 li r6,0x04
65 tlbivax 0,r6
66 TLBSYNC
67 /* Invalidate TLB1 */
68 li r6,0x0c
69 tlbivax 0,r6
70 TLBSYNC
71
72/* 3. Setup a temp mapping and jump to it */
73 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
74 addi r5, r5, 0x1
75 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
76 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
77 mtspr SPRN_MAS0,r7
78 tlbre
79
80 /* grab and fixup the RPN */
81 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
82 rlwinm r6,r6,25,27,31
83 li r8,-1
84 addi r6,r6,10
85 slw r6,r8,r6 /* convert to mask */
86
87 bl 1f /* Find our address */
881: mflr r7
89
90 mfspr r8,SPRN_MAS3
91#ifdef CONFIG_PHYS_64BIT
92 mfspr r23,SPRN_MAS7
93#endif
94 and r8,r6,r8
95 subfic r9,r6,-4096
96 and r9,r9,r7
97
98 or r25,r8,r9
99 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
100
101 /* Just modify the entry ID and EPN for the temp mapping */
102 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
103 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
104 mtspr SPRN_MAS0,r7
105 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
106 slwi r6,r6,12
107 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
108 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
109 mtspr SPRN_MAS1,r6
110 mfspr r6,SPRN_MAS2
111 li r7,0 /* temp EPN = 0 */
112 rlwimi r7,r6,0,20,31
113 mtspr SPRN_MAS2,r7
114 mtspr SPRN_MAS3,r8
115 tlbwe
116
117 xori r6,r4,1
118 slwi r6,r6,5 /* setup new context with other address space */
119 bl 1f /* Find our address */
1201: mflr r9
121 rlwimi r7,r9,0,20,31
122 addi r7,r7,(2f - 1b)
123 mtspr SPRN_SRR0,r7
124 mtspr SPRN_SRR1,r6
125 rfi
1262:
127/* 4. Clear out PIDs & Search info */
128 li r6,0
129 mtspr SPRN_MAS6,r6
130 mtspr SPRN_PID0,r6
131
132 mfspr r7,SPRN_MMUCFG
133 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
134 cmpwi r7,3
135 bne 2f /* skip if NPIDS != 3 */
136
137 mtspr SPRN_PID1,r6
138 mtspr SPRN_PID2,r6
139
140/* 5. Invalidate mapping we started in */
1412:
142 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
143 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
144 mtspr SPRN_MAS0,r7
145 tlbre
146 mfspr r6,SPRN_MAS1
147 rlwinm r6,r6,0,2,0 /* clear IPROT */
148 mtspr SPRN_MAS1,r6
149 tlbwe
150 /* Invalidate TLB1 */
151 li r9,0x0c
152 tlbivax 0,r9
153 TLBSYNC
154
155/* The mapping only needs to be cache-coherent on SMP */
156#ifdef CONFIG_SMP
157#define M_IF_SMP MAS2_M
158#else
159#define M_IF_SMP 0
160#endif
161
162#if defined(ENTRY_MAPPING_BOOT_SETUP)
163
164/* 6. Setup KERNELBASE mapping in TLB1[0] */
165 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
166 mtspr SPRN_MAS0,r6
167 lis r6,(MAS1_VALID|MAS1_IPROT)@h
168 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
169 mtspr SPRN_MAS1,r6
170 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
171 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
172 mtspr SPRN_MAS2,r6
173 mtspr SPRN_MAS3,r8
174 tlbwe
175
176/* 7. Jump to KERNELBASE mapping */
177 lis r6,(KERNELBASE & ~0xfff)@h
178 ori r6,r6,(KERNELBASE & ~0xfff)@l
179
180#elif defined(ENTRY_MAPPING_KEXEC_SETUP)
181/*
182 * 6. Setup a 1:1 mapping in TLB1. Esel 0 is unsued, 1 or 2 contains the tmp
183 * mapping so we start at 3. We setup 8 mappings, each 256MiB in size. This
184 * will cover the first 2GiB of memory.
185 */
186
187 lis r10, (MAS1_VALID|MAS1_IPROT)@h
188 ori r10,r10, (MAS1_TSIZE(BOOK3E_PAGESZ_256M))@l
189 li r11, 0
190 li r0, 8
191 mtctr r0
192
193next_tlb_setup:
194 addi r0, r11, 3
195 rlwinm r0, r0, 16, 4, 15 // Compute esel
196 rlwinm r9, r11, 28, 0, 3 // Compute [ER]PN
197 oris r0, r0, (MAS0_TLBSEL(1))@h
198 mtspr SPRN_MAS0,r0
199 mtspr SPRN_MAS1,r10
200 mtspr SPRN_MAS2,r9
201 ori r9, r9, (MAS3_SX|MAS3_SW|MAS3_SR)
202 mtspr SPRN_MAS3,r9
203 tlbwe
204 addi r11, r11, 1
205 bdnz+ next_tlb_setup
206
207/* 7. Jump to our 1:1 mapping */
208 li r6, 0
209
210#else
211 #error You need to specify the mapping or not use this at all.
212#endif
213
214 lis r7,MSR_KERNEL@h
215 ori r7,r7,MSR_KERNEL@l
216 bl 1f /* Find our address */
2171: mflr r9
218 rlwimi r6,r9,0,20,31
219 addi r6,r6,(2f - 1b)
220 add r6, r6, r25
221 mtspr SPRN_SRR0,r6
222 mtspr SPRN_SRR1,r7
223 rfi /* start execution out of TLB1[0] entry */
224
225/* 8. Clear out the temp mapping */
2262: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
227 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
228 mtspr SPRN_MAS0,r7
229 tlbre
230 mfspr r8,SPRN_MAS1
231 rlwinm r8,r8,0,2,0 /* clear IPROT */
232 mtspr SPRN_MAS1,r8
233 tlbwe
234 /* Invalidate TLB1 */
235 li r9,0x0c
236 tlbivax 0,r9
237 TLBSYNC
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index edd4a57fd29e..4faeba247854 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -94,204 +94,10 @@ _ENTRY(_start);
94 */ 94 */
95 95
96_ENTRY(__early_start) 96_ENTRY(__early_start)
97/* 1. Find the index of the entry we're executing in */
98 bl invstr /* Find our address */
99invstr: mflr r6 /* Make it accessible */
100 mfmsr r7
101 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
102 mfspr r7, SPRN_PID0
103 slwi r7,r7,16
104 or r7,r7,r4
105 mtspr SPRN_MAS6,r7
106 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
107 mfspr r7,SPRN_MAS1
108 andis. r7,r7,MAS1_VALID@h
109 bne match_TLB
110
111 mfspr r7,SPRN_MMUCFG
112 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
113 cmpwi r7,3
114 bne match_TLB /* skip if NPIDS != 3 */
115
116 mfspr r7,SPRN_PID1
117 slwi r7,r7,16
118 or r7,r7,r4
119 mtspr SPRN_MAS6,r7
120 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
121 mfspr r7,SPRN_MAS1
122 andis. r7,r7,MAS1_VALID@h
123 bne match_TLB
124 mfspr r7, SPRN_PID2
125 slwi r7,r7,16
126 or r7,r7,r4
127 mtspr SPRN_MAS6,r7
128 tlbsx 0,r6 /* Fall through, we had to match */
129
130match_TLB:
131 mfspr r7,SPRN_MAS0
132 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
133
134 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
135 oris r7,r7,MAS1_IPROT@h
136 mtspr SPRN_MAS1,r7
137 tlbwe
138
139/* 2. Invalidate all entries except the entry we're executing in */
140 mfspr r9,SPRN_TLB1CFG
141 andi. r9,r9,0xfff
142 li r6,0 /* Set Entry counter to 0 */
1431: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
144 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
145 mtspr SPRN_MAS0,r7
146 tlbre
147 mfspr r7,SPRN_MAS1
148 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
149 cmpw r3,r6
150 beq skpinv /* Dont update the current execution TLB */
151 mtspr SPRN_MAS1,r7
152 tlbwe
153 isync
154skpinv: addi r6,r6,1 /* Increment */
155 cmpw r6,r9 /* Are we done? */
156 bne 1b /* If not, repeat */
157
158 /* Invalidate TLB0 */
159 li r6,0x04
160 tlbivax 0,r6
161 TLBSYNC
162 /* Invalidate TLB1 */
163 li r6,0x0c
164 tlbivax 0,r6
165 TLBSYNC
166
167/* 3. Setup a temp mapping and jump to it */
168 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
169 addi r5, r5, 0x1
170 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
171 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
172 mtspr SPRN_MAS0,r7
173 tlbre
174
175 /* grab and fixup the RPN */
176 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
177 rlwinm r6,r6,25,27,31
178 li r8,-1
179 addi r6,r6,10
180 slw r6,r8,r6 /* convert to mask */
181
182 bl 1f /* Find our address */
1831: mflr r7
184
185 mfspr r8,SPRN_MAS3
186#ifdef CONFIG_PHYS_64BIT
187 mfspr r23,SPRN_MAS7
188#endif
189 and r8,r6,r8
190 subfic r9,r6,-4096
191 and r9,r9,r7
192
193 or r25,r8,r9
194 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
195
196 /* Just modify the entry ID and EPN for the temp mapping */
197 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
198 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
199 mtspr SPRN_MAS0,r7
200 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
201 slwi r6,r6,12
202 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
203 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
204 mtspr SPRN_MAS1,r6
205 mfspr r6,SPRN_MAS2
206 li r7,0 /* temp EPN = 0 */
207 rlwimi r7,r6,0,20,31
208 mtspr SPRN_MAS2,r7
209 mtspr SPRN_MAS3,r8
210 tlbwe
211
212 xori r6,r4,1
213 slwi r6,r6,5 /* setup new context with other address space */
214 bl 1f /* Find our address */
2151: mflr r9
216 rlwimi r7,r9,0,20,31
217 addi r7,r7,(2f - 1b)
218 mtspr SPRN_SRR0,r7
219 mtspr SPRN_SRR1,r6
220 rfi
2212:
222/* 4. Clear out PIDs & Search info */
223 li r6,0
224 mtspr SPRN_MAS6,r6
225 mtspr SPRN_PID0,r6
226
227 mfspr r7,SPRN_MMUCFG
228 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
229 cmpwi r7,3
230 bne 2f /* skip if NPIDS != 3 */
231 97
232 mtspr SPRN_PID1,r6 98#define ENTRY_MAPPING_BOOT_SETUP
233 mtspr SPRN_PID2,r6 99#include "fsl_booke_entry_mapping.S"
234 100#undef ENTRY_MAPPING_BOOT_SETUP
235/* 5. Invalidate mapping we started in */
2362:
237 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
238 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
239 mtspr SPRN_MAS0,r7
240 tlbre
241 mfspr r6,SPRN_MAS1
242 rlwinm r6,r6,0,2,0 /* clear IPROT */
243 mtspr SPRN_MAS1,r6
244 tlbwe
245 /* Invalidate TLB1 */
246 li r9,0x0c
247 tlbivax 0,r9
248 TLBSYNC
249
250/* The mapping only needs to be cache-coherent on SMP */
251#ifdef CONFIG_SMP
252#define M_IF_SMP MAS2_M
253#else
254#define M_IF_SMP 0
255#endif
256
257/* 6. Setup KERNELBASE mapping in TLB1[0] */
258 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
259 mtspr SPRN_MAS0,r6
260 lis r6,(MAS1_VALID|MAS1_IPROT)@h
261 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
262 mtspr SPRN_MAS1,r6
263 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
264 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
265 mtspr SPRN_MAS2,r6
266 mtspr SPRN_MAS3,r8
267 tlbwe
268
269/* 7. Jump to KERNELBASE mapping */
270 lis r6,(KERNELBASE & ~0xfff)@h
271 ori r6,r6,(KERNELBASE & ~0xfff)@l
272 lis r7,MSR_KERNEL@h
273 ori r7,r7,MSR_KERNEL@l
274 bl 1f /* Find our address */
2751: mflr r9
276 rlwimi r6,r9,0,20,31
277 addi r6,r6,(2f - 1b)
278 mtspr SPRN_SRR0,r6
279 mtspr SPRN_SRR1,r7
280 rfi /* start execution out of TLB1[0] entry */
281
282/* 8. Clear out the temp mapping */
2832: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
284 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
285 mtspr SPRN_MAS0,r7
286 tlbre
287 mfspr r8,SPRN_MAS1
288 rlwinm r8,r8,0,2,0 /* clear IPROT */
289 mtspr SPRN_MAS1,r8
290 tlbwe
291 /* Invalidate TLB1 */
292 li r9,0x0c
293 tlbivax 0,r9
294 TLBSYNC
295 101
296 /* Establish the interrupt vector offsets */ 102 /* Establish the interrupt vector offsets */
297 SET_IVOR(0, CriticalInput); 103 SET_IVOR(0, CriticalInput);
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 8043d1b73cf0..dc66d52dcff5 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -711,6 +711,22 @@ relocate_new_kernel:
711 /* r4 = reboot_code_buffer */ 711 /* r4 = reboot_code_buffer */
712 /* r5 = start_address */ 712 /* r5 = start_address */
713 713
714#ifdef CONFIG_FSL_BOOKE
715
716 mr r29, r3
717 mr r30, r4
718 mr r31, r5
719
720#define ENTRY_MAPPING_KEXEC_SETUP
721#include "fsl_booke_entry_mapping.S"
722#undef ENTRY_MAPPING_KEXEC_SETUP
723
724 mr r3, r29
725 mr r4, r30
726 mr r5, r31
727
728 li r0, 0
729#else
714 li r0, 0 730 li r0, 0
715 731
716 /* 732 /*
@@ -727,6 +743,7 @@ relocate_new_kernel:
727 rfi 743 rfi
728 744
7291: 7451:
746#endif
730 /* from this point address translation is turned off */ 747 /* from this point address translation is turned off */
731 /* and interrupts are disabled */ 748 /* and interrupts are disabled */
732 749
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index bc9f39d2598b..3b4dcc82a4c1 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -101,7 +101,7 @@ EXPORT_SYMBOL(pci_dram_offset);
101EXPORT_SYMBOL(start_thread); 101EXPORT_SYMBOL(start_thread);
102EXPORT_SYMBOL(kernel_thread); 102EXPORT_SYMBOL(kernel_thread);
103 103
104#ifndef CONFIG_BOOKE 104#ifdef CONFIG_PPC_FPU
105EXPORT_SYMBOL_GPL(cvt_df); 105EXPORT_SYMBOL_GPL(cvt_df);
106EXPORT_SYMBOL_GPL(cvt_fd); 106EXPORT_SYMBOL_GPL(cvt_fd);
107#endif 107#endif
diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S
new file mode 100644
index 000000000000..11a39307dd71
--- /dev/null
+++ b/arch/powerpc/kernel/swsusp_booke.S
@@ -0,0 +1,193 @@
1/*
2 * Based on swsusp_32.S, modified for FSL BookE by
3 * Anton Vorontsov <avorontsov@ru.mvista.com>
4 * Copyright (c) 2009-2010 MontaVista Software, LLC.
5 */
6
7#include <linux/threads.h>
8#include <asm/processor.h>
9#include <asm/page.h>
10#include <asm/cputable.h>
11#include <asm/thread_info.h>
12#include <asm/ppc_asm.h>
13#include <asm/asm-offsets.h>
14#include <asm/mmu.h>
15
16/*
17 * Structure for storing CPU registers on the save area.
18 */
19#define SL_SP 0
20#define SL_PC 4
21#define SL_MSR 8
22#define SL_TCR 0xc
23#define SL_SPRG0 0x10
24#define SL_SPRG1 0x14
25#define SL_SPRG2 0x18
26#define SL_SPRG3 0x1c
27#define SL_SPRG4 0x20
28#define SL_SPRG5 0x24
29#define SL_SPRG6 0x28
30#define SL_SPRG7 0x2c
31#define SL_TBU 0x30
32#define SL_TBL 0x34
33#define SL_R2 0x38
34#define SL_CR 0x3c
35#define SL_LR 0x40
36#define SL_R12 0x44 /* r12 to r31 */
37#define SL_SIZE (SL_R12 + 80)
38
39 .section .data
40 .align 5
41
42_GLOBAL(swsusp_save_area)
43 .space SL_SIZE
44
45
46 .section .text
47 .align 5
48
49_GLOBAL(swsusp_arch_suspend)
50 lis r11,swsusp_save_area@h
51 ori r11,r11,swsusp_save_area@l
52
53 mflr r0
54 stw r0,SL_LR(r11)
55 mfcr r0
56 stw r0,SL_CR(r11)
57 stw r1,SL_SP(r11)
58 stw r2,SL_R2(r11)
59 stmw r12,SL_R12(r11)
60
61 /* Save MSR & TCR */
62 mfmsr r4
63 stw r4,SL_MSR(r11)
64 mfspr r4,SPRN_TCR
65 stw r4,SL_TCR(r11)
66
67 /* Get a stable timebase and save it */
681: mfspr r4,SPRN_TBRU
69 stw r4,SL_TBU(r11)
70 mfspr r5,SPRN_TBRL
71 stw r5,SL_TBL(r11)
72 mfspr r3,SPRN_TBRU
73 cmpw r3,r4
74 bne 1b
75
76 /* Save SPRGs */
77 mfsprg r4,0
78 stw r4,SL_SPRG0(r11)
79 mfsprg r4,1
80 stw r4,SL_SPRG1(r11)
81 mfsprg r4,2
82 stw r4,SL_SPRG2(r11)
83 mfsprg r4,3
84 stw r4,SL_SPRG3(r11)
85 mfsprg r4,4
86 stw r4,SL_SPRG4(r11)
87 mfsprg r4,5
88 stw r4,SL_SPRG5(r11)
89 mfsprg r4,6
90 stw r4,SL_SPRG6(r11)
91 mfsprg r4,7
92 stw r4,SL_SPRG7(r11)
93
94 /* Call the low level suspend stuff (we should probably have made
95 * a stackframe...
96 */
97 bl swsusp_save
98
99 /* Restore LR from the save area */
100 lis r11,swsusp_save_area@h
101 ori r11,r11,swsusp_save_area@l
102 lwz r0,SL_LR(r11)
103 mtlr r0
104
105 blr
106
107_GLOBAL(swsusp_arch_resume)
108 sync
109
110 /* Load ptr the list of pages to copy in r3 */
111 lis r11,(restore_pblist)@h
112 ori r11,r11,restore_pblist@l
113 lwz r3,0(r11)
114
115 /* Copy the pages. This is a very basic implementation, to
116 * be replaced by something more cache efficient */
1171:
118 li r0,256
119 mtctr r0
120 lwz r5,pbe_address(r3) /* source */
121 lwz r6,pbe_orig_address(r3) /* destination */
1222:
123 lwz r8,0(r5)
124 lwz r9,4(r5)
125 lwz r10,8(r5)
126 lwz r11,12(r5)
127 addi r5,r5,16
128 stw r8,0(r6)
129 stw r9,4(r6)
130 stw r10,8(r6)
131 stw r11,12(r6)
132 addi r6,r6,16
133 bdnz 2b
134 lwz r3,pbe_next(r3)
135 cmpwi 0,r3,0
136 bne 1b
137
138 bl flush_dcache_L1
139 bl flush_instruction_cache
140
141 lis r11,swsusp_save_area@h
142 ori r11,r11,swsusp_save_area@l
143
144 lwz r4,SL_SPRG0(r11)
145 mtsprg 0,r4
146 lwz r4,SL_SPRG1(r11)
147 mtsprg 1,r4
148 lwz r4,SL_SPRG2(r11)
149 mtsprg 2,r4
150 lwz r4,SL_SPRG3(r11)
151 mtsprg 3,r4
152 lwz r4,SL_SPRG4(r11)
153 mtsprg 4,r4
154 lwz r4,SL_SPRG5(r11)
155 mtsprg 5,r4
156 lwz r4,SL_SPRG6(r11)
157 mtsprg 6,r4
158 lwz r4,SL_SPRG7(r11)
159 mtsprg 7,r4
160
161 /* restore the MSR */
162 lwz r3,SL_MSR(r11)
163 mtmsr r3
164
165 /* Restore TB */
166 li r3,0
167 mtspr SPRN_TBWL,r3
168 lwz r3,SL_TBU(r11)
169 lwz r4,SL_TBL(r11)
170 mtspr SPRN_TBWU,r3
171 mtspr SPRN_TBWL,r4
172
173 /* Restore TCR and clear any pending bits in TSR. */
174 lwz r4,SL_TCR(r11)
175 mtspr SPRN_TCR,r4
176 lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
177 mtspr SPRN_TSR,r4
178
179 /* Kick decrementer */
180 li r0,1
181 mtdec r0
182
183 /* Restore the callee-saved registers and return */
184 lwz r0,SL_CR(r11)
185 mtcr r0
186 lwz r2,SL_R2(r11)
187 lmw r12,SL_R12(r11)
188 lwz r1,SL_SP(r11)
189 lwz r0,SL_LR(r11)
190 mtlr r0
191
192 li r3,0
193 blr
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 3031fc712ad0..25fc33984c2b 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
@@ -305,7 +306,7 @@ static inline int check_io_access(struct pt_regs *regs)
305#ifndef CONFIG_FSL_BOOKE 306#ifndef CONFIG_FSL_BOOKE
306#define get_mc_reason(regs) ((regs)->dsisr) 307#define get_mc_reason(regs) ((regs)->dsisr)
307#else 308#else
308#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) 309#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
309#endif 310#endif
310#define REASON_FP ESR_FP 311#define REASON_FP ESR_FP
311#define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 312#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
@@ -421,6 +422,91 @@ int machine_check_47x(struct pt_regs *regs)
421 return 0; 422 return 0;
422} 423}
423#elif defined(CONFIG_E500) 424#elif defined(CONFIG_E500)
425int machine_check_e500mc(struct pt_regs *regs)
426{
427 unsigned long mcsr = mfspr(SPRN_MCSR);
428 unsigned long reason = mcsr;
429 int recoverable = 1;
430
431 printk("Machine check in kernel mode.\n");
432 printk("Caused by (from MCSR=%lx): ", reason);
433
434 if (reason & MCSR_MCP)
435 printk("Machine Check Signal\n");
436
437 if (reason & MCSR_ICPERR) {
438 printk("Instruction Cache Parity Error\n");
439
440 /*
441 * This is recoverable by invalidating the i-cache.
442 */
443 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
444 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
445 ;
446
447 /*
448 * This will generally be accompanied by an instruction
449 * fetch error report -- only treat MCSR_IF as fatal
450 * if it wasn't due to an L1 parity error.
451 */
452 reason &= ~MCSR_IF;
453 }
454
455 if (reason & MCSR_DCPERR_MC) {
456 printk("Data Cache Parity Error\n");
457 recoverable = 0;
458 }
459
460 if (reason & MCSR_L2MMU_MHIT) {
461 printk("Hit on multiple TLB entries\n");
462 recoverable = 0;
463 }
464
465 if (reason & MCSR_NMI)
466 printk("Non-maskable interrupt\n");
467
468 if (reason & MCSR_IF) {
469 printk("Instruction Fetch Error Report\n");
470 recoverable = 0;
471 }
472
473 if (reason & MCSR_LD) {
474 printk("Load Error Report\n");
475 recoverable = 0;
476 }
477
478 if (reason & MCSR_ST) {
479 printk("Store Error Report\n");
480 recoverable = 0;
481 }
482
483 if (reason & MCSR_LDG) {
484 printk("Guarded Load Error Report\n");
485 recoverable = 0;
486 }
487
488 if (reason & MCSR_TLBSYNC)
489 printk("Simultaneous tlbsync operations\n");
490
491 if (reason & MCSR_BSL2_ERR) {
492 printk("Level 2 Cache Error\n");
493 recoverable = 0;
494 }
495
496 if (reason & MCSR_MAV) {
497 u64 addr;
498
499 addr = mfspr(SPRN_MCAR);
500 addr |= (u64)mfspr(SPRN_MCARU) << 32;
501
502 printk("Machine Check %s Address: %#llx\n",
503 reason & MCSR_MEA ? "Effective" : "Physical", addr);
504 }
505
506 mtspr(SPRN_MCSR, mcsr);
507 return mfspr(SPRN_MCSR) == 0 && recoverable;
508}
509
424int machine_check_e500(struct pt_regs *regs) 510int machine_check_e500(struct pt_regs *regs)
425{ 511{
426 unsigned long reason = get_mc_reason(regs); 512 unsigned long reason = get_mc_reason(regs);
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index eeba0a70e466..69d668c072ae 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -171,6 +171,17 @@ config ISS4xx
171 help 171 help
172 This option enables support for the IBM ISS simulation environment 172 This option enables support for the IBM ISS simulation environment
173 173
174config ICON
175 bool "Icon"
176 depends on 44x
177 default n
178 select PPC44x_SIMPLE
179 select 440SPe
180 select PCI
181 select PPC4xx_PCI_EXPRESS
182 help
183 This option enables support for the AMCC PPC440SPe evaluation board.
184
174#config LUAN 185#config LUAN
175# bool "Luan" 186# bool "Luan"
176# depends on 44x 187# depends on 44x
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index e8c23ccaa1fc..5f7a29d7f590 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -61,7 +61,8 @@ static char *board[] __initdata = {
61 "amcc,redwood", 61 "amcc,redwood",
62 "amcc,sequoia", 62 "amcc,sequoia",
63 "amcc,taishan", 63 "amcc,taishan",
64 "amcc,yosemite" 64 "amcc,yosemite",
65 "mosaixtech,icon"
65}; 66};
66 67
67static int __init ppc44x_probe(void) 68static int __init ppc44x_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index f0684c8ac960..8fe87fc61485 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
3 * 3 *
4 * Author: Andy Fleming <afleming@freescale.com> 4 * Author: Andy Fleming <afleming@freescale.com>
5 * 5 *
@@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
154 * Setup the architecture 154 * Setup the architecture
155 * 155 *
156 */ 156 */
157#ifdef CONFIG_SMP
158extern void __init mpc85xx_smp_init(void);
159#endif
160
157static void __init mpc85xx_mds_setup_arch(void) 161static void __init mpc85xx_mds_setup_arch(void)
158{ 162{
159 struct device_node *np; 163 struct device_node *np;
@@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void)
194 } 198 }
195#endif 199#endif
196 200
201#ifdef CONFIG_SMP
202 mpc85xx_smp_init();
203#endif
204
197#ifdef CONFIG_QUICC_ENGINE 205#ifdef CONFIG_QUICC_ENGINE
198 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 206 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
199 if (!np) { 207 if (!np) {
@@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void)
271 BCSR_UCC_RGMII, BCSR_UCC_RTBI); 279 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
272 } 280 }
273 281
282 } else if (machine_is(p1021_mds)) {
283#define BCSR11_ENET_MICRST (0x1 << 5)
284 /* Reset Micrel PHY */
285 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
286 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
274 } 287 }
288
275 iounmap(bcsr_regs); 289 iounmap(bcsr_regs);
276 } 290 }
291
292 if (machine_is(p1021_mds)) {
293#define MPC85xx_PMUXCR_OFFSET 0x60
294#define MPC85xx_PMUXCR_QE0 0x00008000
295#define MPC85xx_PMUXCR_QE3 0x00001000
296#define MPC85xx_PMUXCR_QE9 0x00000040
297#define MPC85xx_PMUXCR_QE12 0x00000008
298 static __be32 __iomem *pmuxcr;
299
300 np = of_find_node_by_name(NULL, "global-utilities");
301
302 if (np) {
303 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
304
305 if (!pmuxcr)
306 printk(KERN_EMERG "Error: Alternate function"
307 " signal multiplex control register not"
308 " mapped!\n");
309 else
310 /* P1021 has pins muxed for QE and other functions. To
311 * enable QE UEC mode, we need to set bit QE0 for UCC1
312 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
313 * and QE12 for QE MII management singals in PMUXCR
314 * register.
315 */
316 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
317 MPC85xx_PMUXCR_QE3 |
318 MPC85xx_PMUXCR_QE9 |
319 MPC85xx_PMUXCR_QE12);
320
321 of_node_put(np);
322 }
323
324 }
277#endif /* CONFIG_QUICC_ENGINE */ 325#endif /* CONFIG_QUICC_ENGINE */
278 326
279#ifdef CONFIG_SWIOTLB 327#ifdef CONFIG_SWIOTLB
@@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = {
330 {}, 378 {},
331}; 379};
332 380
381static struct of_device_id p1021_ids[] = {
382 { .type = "soc", },
383 { .compatible = "soc", },
384 { .compatible = "simple-bus", },
385 { .type = "qe", },
386 { .compatible = "fsl,qe", },
387 { .compatible = "gianfar", },
388 {},
389};
390
333static int __init mpc85xx_publish_devices(void) 391static int __init mpc85xx_publish_devices(void)
334{ 392{
335 if (machine_is(mpc8568_mds)) 393 if (machine_is(mpc8568_mds))
@@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void)
342 400
343 return 0; 401 return 0;
344} 402}
403
404static int __init p1021_publish_devices(void)
405{
406 /* Publish the QE devices */
407 of_platform_bus_probe(NULL, p1021_ids, NULL);
408
409 return 0;
410}
411
345machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 412machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
346machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 413machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
414machine_device_initcall(p1021_mds, p1021_publish_devices);
347 415
348machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 416machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
349machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 417machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
418machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
350 419
351static void __init mpc85xx_mds_pic_init(void) 420static void __init mpc85xx_mds_pic_init(void)
352{ 421{
@@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void)
366 435
367 mpic = mpic_alloc(np, r.start, 436 mpic = mpic_alloc(np, r.start,
368 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | 437 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
369 MPIC_BROKEN_FRR_NIRQS, 438 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
370 0, 256, " OpenPIC "); 439 0, 256, " OpenPIC ");
371 BUG_ON(mpic == NULL); 440 BUG_ON(mpic == NULL);
372 of_node_put(np); 441 of_node_put(np);
@@ -380,7 +449,11 @@ static void __init mpc85xx_mds_pic_init(void)
380 if (!np) 449 if (!np)
381 return; 450 return;
382 } 451 }
383 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); 452 if (machine_is(p1021_mds))
453 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
454 qe_ic_cascade_high_mpic);
455 else
456 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
384 of_node_put(np); 457 of_node_put(np);
385#endif /* CONFIG_QUICC_ENGINE */ 458#endif /* CONFIG_QUICC_ENGINE */
386} 459}
@@ -426,3 +499,26 @@ define_machine(mpc8569_mds) {
426 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 499 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
427#endif 500#endif
428}; 501};
502
503static int __init p1021_mds_probe(void)
504{
505 unsigned long root = of_get_flat_dt_root();
506
507 return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
508
509}
510
511define_machine(p1021_mds) {
512 .name = "P1021 MDS",
513 .probe = p1021_mds_probe,
514 .setup_arch = mpc85xx_mds_setup_arch,
515 .init_IRQ = mpc85xx_mds_pic_init,
516 .get_irq = mpic_get_irq,
517 .restart = fsl_rstcr_restart,
518 .calibrate_decr = generic_calibrate_decr,
519 .progress = udbg_progress,
520#ifdef CONFIG_PCI
521 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
522#endif
523};
524
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index a7be144f5874..0f5bee90ee4e 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. 2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Tony Li <tony.li@freescale.com> 4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com> 5 * Jason Jin <Jason.jin@freescale.com>
@@ -22,14 +22,20 @@
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/hw_irq.h> 23#include <asm/hw_irq.h>
24#include <asm/ppc-pci.h> 24#include <asm/ppc-pci.h>
25#include <asm/mpic.h>
25#include "fsl_msi.h" 26#include "fsl_msi.h"
26 27
28LIST_HEAD(msi_head);
29
27struct fsl_msi_feature { 30struct fsl_msi_feature {
28 u32 fsl_pic_ip; 31 u32 fsl_pic_ip;
29 u32 msiir_offset; 32 u32 msiir_offset;
30}; 33};
31 34
32static struct fsl_msi *fsl_msi; 35struct fsl_msi_cascade_data {
36 struct fsl_msi *msi_data;
37 int index;
38};
33 39
34static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) 40static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
35{ 41{
@@ -54,10 +60,12 @@ static struct irq_chip fsl_msi_chip = {
54static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, 60static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
55 irq_hw_number_t hw) 61 irq_hw_number_t hw)
56{ 62{
63 struct fsl_msi *msi_data = h->host_data;
57 struct irq_chip *chip = &fsl_msi_chip; 64 struct irq_chip *chip = &fsl_msi_chip;
58 65
59 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; 66 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
60 67
68 set_irq_chip_data(virq, msi_data);
61 set_irq_chip_and_handler(virq, chip, handle_edge_irq); 69 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
62 70
63 return 0; 71 return 0;
@@ -96,11 +104,12 @@ static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
96static void fsl_teardown_msi_irqs(struct pci_dev *pdev) 104static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
97{ 105{
98 struct msi_desc *entry; 106 struct msi_desc *entry;
99 struct fsl_msi *msi_data = fsl_msi; 107 struct fsl_msi *msi_data;
100 108
101 list_for_each_entry(entry, &pdev->msi_list, list) { 109 list_for_each_entry(entry, &pdev->msi_list, list) {
102 if (entry->irq == NO_IRQ) 110 if (entry->irq == NO_IRQ)
103 continue; 111 continue;
112 msi_data = get_irq_data(entry->irq);
104 set_irq_msi(entry->irq, NULL); 113 set_irq_msi(entry->irq, NULL);
105 msi_bitmap_free_hwirqs(&msi_data->bitmap, 114 msi_bitmap_free_hwirqs(&msi_data->bitmap,
106 virq_to_hw(entry->irq), 1); 115 virq_to_hw(entry->irq), 1);
@@ -111,9 +120,10 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
111} 120}
112 121
113static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, 122static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
114 struct msi_msg *msg) 123 struct msi_msg *msg,
124 struct fsl_msi *fsl_msi_data)
115{ 125{
116 struct fsl_msi *msi_data = fsl_msi; 126 struct fsl_msi *msi_data = fsl_msi_data;
117 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 127 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
118 u32 base = 0; 128 u32 base = 0;
119 129
@@ -130,14 +140,19 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
130 140
131static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 141static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
132{ 142{
133 int rc, hwirq; 143 int rc, hwirq = -ENOMEM;
134 unsigned int virq; 144 unsigned int virq;
135 struct msi_desc *entry; 145 struct msi_desc *entry;
136 struct msi_msg msg; 146 struct msi_msg msg;
137 struct fsl_msi *msi_data = fsl_msi; 147 struct fsl_msi *msi_data;
138 148
139 list_for_each_entry(entry, &pdev->msi_list, list) { 149 list_for_each_entry(entry, &pdev->msi_list, list) {
140 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); 150 list_for_each_entry(msi_data, &msi_head, list) {
151 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
152 if (hwirq >= 0)
153 break;
154 }
155
141 if (hwirq < 0) { 156 if (hwirq < 0) {
142 rc = hwirq; 157 rc = hwirq;
143 pr_debug("%s: fail allocating msi interrupt\n", 158 pr_debug("%s: fail allocating msi interrupt\n",
@@ -154,25 +169,31 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
154 rc = -ENOSPC; 169 rc = -ENOSPC;
155 goto out_free; 170 goto out_free;
156 } 171 }
172 set_irq_data(virq, msi_data);
157 set_irq_msi(virq, entry); 173 set_irq_msi(virq, entry);
158 174
159 fsl_compose_msi_msg(pdev, hwirq, &msg); 175 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
160 write_msi_msg(virq, &msg); 176 write_msi_msg(virq, &msg);
161 } 177 }
162 return 0; 178 return 0;
163 179
164out_free: 180out_free:
181 /* free by the caller of this function */
165 return rc; 182 return rc;
166} 183}
167 184
168static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) 185static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
169{ 186{
170 unsigned int cascade_irq; 187 unsigned int cascade_irq;
171 struct fsl_msi *msi_data = fsl_msi; 188 struct fsl_msi *msi_data;
172 int msir_index = -1; 189 int msir_index = -1;
173 u32 msir_value = 0; 190 u32 msir_value = 0;
174 u32 intr_index; 191 u32 intr_index;
175 u32 have_shift = 0; 192 u32 have_shift = 0;
193 struct fsl_msi_cascade_data *cascade_data;
194
195 cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
196 msi_data = cascade_data->msi_data;
176 197
177 raw_spin_lock(&desc->lock); 198 raw_spin_lock(&desc->lock);
178 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { 199 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
@@ -187,13 +208,13 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
187 if (unlikely(desc->status & IRQ_INPROGRESS)) 208 if (unlikely(desc->status & IRQ_INPROGRESS))
188 goto unlock; 209 goto unlock;
189 210
190 msir_index = (int)desc->handler_data; 211 msir_index = cascade_data->index;
191 212
192 if (msir_index >= NR_MSI_REG) 213 if (msir_index >= NR_MSI_REG)
193 cascade_irq = NO_IRQ; 214 cascade_irq = NO_IRQ;
194 215
195 desc->status |= IRQ_INPROGRESS; 216 desc->status |= IRQ_INPROGRESS;
196 switch (fsl_msi->feature & FSL_PIC_IP_MASK) { 217 switch (msi_data->feature & FSL_PIC_IP_MASK) {
197 case FSL_PIC_IP_MPIC: 218 case FSL_PIC_IP_MPIC:
198 msir_value = fsl_msi_read(msi_data->msi_regs, 219 msir_value = fsl_msi_read(msi_data->msi_regs,
199 msir_index * 0x10); 220 msir_index * 0x10);
@@ -229,6 +250,30 @@ unlock:
229 raw_spin_unlock(&desc->lock); 250 raw_spin_unlock(&desc->lock);
230} 251}
231 252
253static int fsl_of_msi_remove(struct of_device *ofdev)
254{
255 struct fsl_msi *msi = ofdev->dev.platform_data;
256 int virq, i;
257 struct fsl_msi_cascade_data *cascade_data;
258
259 if (msi->list.prev != NULL)
260 list_del(&msi->list);
261 for (i = 0; i < NR_MSI_REG; i++) {
262 virq = msi->msi_virqs[i];
263 if (virq != NO_IRQ) {
264 cascade_data = get_irq_data(virq);
265 kfree(cascade_data);
266 irq_dispose_mapping(virq);
267 }
268 }
269 if (msi->bitmap.bitmap)
270 msi_bitmap_free(&msi->bitmap);
271 iounmap(msi->msi_regs);
272 kfree(msi);
273
274 return 0;
275}
276
232static int __devinit fsl_of_msi_probe(struct of_device *dev, 277static int __devinit fsl_of_msi_probe(struct of_device *dev,
233 const struct of_device_id *match) 278 const struct of_device_id *match)
234{ 279{
@@ -239,15 +284,18 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
239 int virt_msir; 284 int virt_msir;
240 const u32 *p; 285 const u32 *p;
241 struct fsl_msi_feature *features = match->data; 286 struct fsl_msi_feature *features = match->data;
287 struct fsl_msi_cascade_data *cascade_data = NULL;
288 int len;
289 u32 offset;
242 290
243 printk(KERN_DEBUG "Setting up Freescale MSI support\n"); 291 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
244 292
245 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); 293 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
246 if (!msi) { 294 if (!msi) {
247 dev_err(&dev->dev, "No memory for MSI structure\n"); 295 dev_err(&dev->dev, "No memory for MSI structure\n");
248 err = -ENOMEM; 296 return -ENOMEM;
249 goto error_out;
250 } 297 }
298 dev->dev.platform_data = msi;
251 299
252 msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR, 300 msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
253 NR_MSI_IRQS, &fsl_msi_host_ops, 0); 301 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
@@ -298,27 +346,47 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
298 err = -EINVAL; 346 err = -EINVAL;
299 goto error_out; 347 goto error_out;
300 } 348 }
349 offset = 0;
350 p = of_get_property(dev->node, "msi-available-ranges", &len);
351 if (p)
352 offset = *p / IRQS_PER_MSI_REG;
301 353
302 count /= sizeof(u32); 354 count /= sizeof(u32);
303 for (i = 0; i < count / 2; i++) { 355 for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
304 if (i > NR_MSI_REG)
305 break;
306 virt_msir = irq_of_parse_and_map(dev->dev.of_node, i); 356 virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
307 if (virt_msir != NO_IRQ) { 357 if (virt_msir != NO_IRQ) {
308 set_irq_data(virt_msir, (void *)i); 358 cascade_data = kzalloc(
359 sizeof(struct fsl_msi_cascade_data),
360 GFP_KERNEL);
361 if (!cascade_data) {
362 dev_err(&dev->dev,
363 "No memory for MSI cascade data\n");
364 err = -ENOMEM;
365 goto error_out;
366 }
367 msi->msi_virqs[i] = virt_msir;
368 cascade_data->index = i + offset;
369 cascade_data->msi_data = msi;
370 set_irq_data(virt_msir, (void *)cascade_data);
309 set_irq_chained_handler(virt_msir, fsl_msi_cascade); 371 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
310 } 372 }
311 } 373 }
312 374
313 fsl_msi = msi; 375 list_add_tail(&msi->list, &msi_head);
314 376
315 WARN_ON(ppc_md.setup_msi_irqs); 377 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
316 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; 378 if (!ppc_md.setup_msi_irqs) {
317 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; 379 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
318 ppc_md.msi_check_device = fsl_msi_check_device; 380 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
381 ppc_md.msi_check_device = fsl_msi_check_device;
382 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
383 dev_err(&dev->dev, "Different MSI driver already installed!\n");
384 err = -ENODEV;
385 goto error_out;
386 }
319 return 0; 387 return 0;
320error_out: 388error_out:
321 kfree(msi); 389 fsl_of_msi_remove(dev);
322 return err; 390 return err;
323} 391}
324 392
@@ -351,6 +419,7 @@ static struct of_platform_driver fsl_of_msi_driver = {
351 .of_match_table = fsl_of_msi_ids, 419 .of_match_table = fsl_of_msi_ids,
352 }, 420 },
353 .probe = fsl_of_msi_probe, 421 .probe = fsl_of_msi_probe,
422 .remove = fsl_of_msi_remove,
354}; 423};
355 424
356static __init int fsl_of_msi_init(void) 425static __init int fsl_of_msi_init(void)
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 331c7e7025b7..624580c252d7 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -32,8 +32,11 @@ struct fsl_msi {
32 u32 msi_addr_hi; 32 u32 msi_addr_hi;
33 void __iomem *msi_regs; 33 void __iomem *msi_regs;
34 u32 feature; 34 u32 feature;
35 int msi_virqs[NR_MSI_REG];
35 36
36 struct msi_bitmap bitmap; 37 struct msi_bitmap bitmap;
38
39 struct list_head list; /* support multiple MSI banks */
37}; 40};
38 41
39#endif /* _POWERPC_SYSDEV_FSL_MSI_H */ 42#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 106d767bf65b..156aa7d36258 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
974 .setup_utl = ppc460ex_pciex_init_utl, 974 .setup_utl = ppc460ex_pciex_init_utl,
975}; 975};
976 976
977static int __init ppc460sx_pciex_core_init(struct device_node *np)
978{
979 /* HSS drive amplitude */
980 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
981 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
982 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
983 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
984 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
985 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
986 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
987 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
988
989 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
990 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
991 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
992 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
993
994 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
995 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
996 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
997 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
998
999 /* HSS TX pre-emphasis */
1000 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1001 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1002 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1003 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1004 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1005 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1006 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1007 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1008
1009 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1010 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1011 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1012 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1013
1014 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1015 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1016 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1017 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1018
1019 /* HSS TX calibration control */
1020 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1021 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1022 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1023
1024 /* HSS TX slew control */
1025 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1026 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1027 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1028
1029 udelay(100);
1030
1031 /* De-assert PLLRESET */
1032 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1033
1034 /* Reset DL, UTL, GPL before configuration */
1035 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1036 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1037 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1038 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1039 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1040 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1041
1042 udelay(100);
1043
1044 /*
1045 * If bifurcation is not enabled, u-boot would have disabled the
1046 * third PCIe port
1047 */
1048 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1049 0x00000001)) {
1050 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1051 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1052 return 3;
1053 }
1054
1055 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1056 return 2;
1057}
1058
1059static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1060{
1061
1062 if (port->endpoint)
1063 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1064 0x01000000, 0);
1065 else
1066 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1067 0, 0x01000000);
1068
1069 /*Gen-1*/
1070 mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
1071
1072 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1073 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1074 PESDRx_RCSSET_RSTPYN);
1075
1076 port->has_ibpre = 1;
1077
1078 return 0;
1079}
1080
1081static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1082{
1083 /* Max 128 Bytes */
1084 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1085 return 0;
1086}
1087
1088static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1089 .core_init = ppc460sx_pciex_core_init,
1090 .port_init_hw = ppc460sx_pciex_init_port_hw,
1091 .setup_utl = ppc460sx_pciex_init_utl,
1092};
1093
977#endif /* CONFIG_44x */ 1094#endif /* CONFIG_44x */
978 1095
979#ifdef CONFIG_40x 1096#ifdef CONFIG_40x
@@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1089 } 1206 }
1090 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) 1207 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1091 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; 1208 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1209 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1210 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1092#endif /* CONFIG_44x */ 1211#endif /* CONFIG_44x */
1093#ifdef CONFIG_40x 1212#ifdef CONFIG_40x
1094 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1213 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index d04e40b306fb..56d9e5deccbf 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -324,6 +324,64 @@
324#define PESDR0_460EX_IHS2 0x036D 324#define PESDR0_460EX_IHS2 0x036D
325 325
326/* 326/*
327 * 460SX addtional DCRs
328 */
329#define PESDRn_460SX_RCEI 0x02
330
331#define PESDR0_460SX_HSSL0DAMP 0x320
332#define PESDR0_460SX_HSSL1DAMP 0x321
333#define PESDR0_460SX_HSSL2DAMP 0x322
334#define PESDR0_460SX_HSSL3DAMP 0x323
335#define PESDR0_460SX_HSSL4DAMP 0x324
336#define PESDR0_460SX_HSSL5DAMP 0x325
337#define PESDR0_460SX_HSSL6DAMP 0x326
338#define PESDR0_460SX_HSSL7DAMP 0x327
339
340#define PESDR1_460SX_HSSL0DAMP 0x354
341#define PESDR1_460SX_HSSL1DAMP 0x355
342#define PESDR1_460SX_HSSL2DAMP 0x356
343#define PESDR1_460SX_HSSL3DAMP 0x357
344
345#define PESDR2_460SX_HSSL0DAMP 0x384
346#define PESDR2_460SX_HSSL1DAMP 0x385
347#define PESDR2_460SX_HSSL2DAMP 0x386
348#define PESDR2_460SX_HSSL3DAMP 0x387
349
350#define PESDR0_460SX_HSSL0COEFA 0x328
351#define PESDR0_460SX_HSSL1COEFA 0x329
352#define PESDR0_460SX_HSSL2COEFA 0x32A
353#define PESDR0_460SX_HSSL3COEFA 0x32B
354#define PESDR0_460SX_HSSL4COEFA 0x32C
355#define PESDR0_460SX_HSSL5COEFA 0x32D
356#define PESDR0_460SX_HSSL6COEFA 0x32E
357#define PESDR0_460SX_HSSL7COEFA 0x32F
358
359#define PESDR1_460SX_HSSL0COEFA 0x358
360#define PESDR1_460SX_HSSL1COEFA 0x359
361#define PESDR1_460SX_HSSL2COEFA 0x35A
362#define PESDR1_460SX_HSSL3COEFA 0x35B
363
364#define PESDR2_460SX_HSSL0COEFA 0x388
365#define PESDR2_460SX_HSSL1COEFA 0x389
366#define PESDR2_460SX_HSSL2COEFA 0x38A
367#define PESDR2_460SX_HSSL3COEFA 0x38B
368
369#define PESDR0_460SX_HSSL1CALDRV 0x339
370#define PESDR1_460SX_HSSL1CALDRV 0x361
371#define PESDR2_460SX_HSSL1CALDRV 0x391
372
373#define PESDR0_460SX_HSSSLEW 0x338
374#define PESDR1_460SX_HSSSLEW 0x360
375#define PESDR2_460SX_HSSSLEW 0x390
376
377#define PESDR0_460SX_HSSCTLSET 0x31E
378#define PESDR1_460SX_HSSCTLSET 0x352
379#define PESDR2_460SX_HSSCTLSET 0x382
380
381#define PESDR0_460SX_RCSSET 0x304
382#define PESDR1_460SX_RCSSET 0x344
383#define PESDR2_460SX_RCSSET 0x374
384/*
327 * Of the above, some are common offsets from the base 385 * Of the above, some are common offsets from the base
328 */ 386 */
329#define PESDRn_UTLSET1 0x00 387#define PESDRn_UTLSET1 0x00
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 23:59:51 -0500