Merge commit 'origin/master' into next

Manual merge of: arch/powerpc/kernel/asm-offsets.c
author: Benjamin Herrenschmidt <benh@kernel.crashing.org> 2009-06-12 02:53:38 -0400
committer: Benjamin Herrenschmidt <benh@kernel.crashing.org> 2009-06-12 02:53:38 -0400
commit: bc47ab0241c7c86da4f5e5f82fbca7d45387c18d (patch)
tree: b9c33ae8b6de43e44cc5fcbaa3e4a15f18a5ed42 /arch/powerpc
parent: 37f9ef553bed630957e025504cdcbc76f5de49d5 (diff)
parent: 8ebf975608aaebd7feb33d77f07ba21a6380e086 (diff)
25 files changed, 4895 insertions, 93 deletions
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 5339bb44cce9..ea8870a34482 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc3
+# Linux kernel version: 2.6.30-rc7
-# Tue Nov 11 19:36:51 2008
+# Mon May 25 14:53:25 2009
 #
 # CONFIG_PPC64 is not set
@@ -14,6 +14,7 @@ CONFIG_6xx=y
 # CONFIG_40x is not set
 # CONFIG_44x is not set
 # CONFIG_E200 is not set
+CONFIG_PPC_BOOK3S=y
 CONFIG_PPC_FPU=y
 CONFIG_ALTIVEC=y
 CONFIG_PPC_STD_MMU=y
@@ -43,7 +44,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_PPC=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_GENERIC_NVRAM=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_ARCH_MAY_HAVE_PC_FDC=y
 CONFIG_PPC_OF=y
 CONFIG_OF=y
@@ -52,12 +53,14 @@ CONFIG_OF=y
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_HIBERNATE_32=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PPC_DCR_NATIVE is not set
 # CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@@ -72,14 +75,24 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -88,23 +101,27 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -114,10 +131,12 @@ CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
@@ -127,10 +146,10 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -138,11 +157,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-CONFIG_LSF=y
 CONFIG_BLK_DEV_BSG=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -158,14 +174,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
 CONFIG_FREEZER=y
 #
 # Platform support
 #
-CONFIG_PPC_MULTIPLATFORM=y
-CONFIG_CLASSIC32=y
 # CONFIG_PPC_CHRP is not set
 # CONFIG_MPC5121_ADS is not set
 # CONFIG_MPC5121_GENERIC is not set
@@ -178,7 +191,9 @@ CONFIG_PPC_PMAC=y
 # CONFIG_PPC_83xx is not set
 # CONFIG_PPC_86xx is not set
 # CONFIG_EMBEDDED6xx is not set
+# CONFIG_AMIGAONE is not set
 CONFIG_PPC_NATIVE=y
+CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
 # CONFIG_IPIC is not set
 CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
@@ -212,11 +227,12 @@ CONFIG_CPU_FREQ_PMAC=y
 CONFIG_PPC601_SYNC_FIX=y
 # CONFIG_TAU is not set
 # CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
 #
 # Kernel options
 #
-# CONFIG_HIGHMEM is not set
+CONFIG_HIGHMEM=y
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -239,6 +255,7 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
 # CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -250,12 +267,17 @@ CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_MIGRATION is not set
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
@@ -288,6 +310,8 @@ CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
 # CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 CONFIG_PCCARD=m
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=m
@@ -397,6 +421,8 @@ CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
 # CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
@@ -405,6 +431,7 @@ CONFIG_NETFILTER_XT_TARGET_RATEEST=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
@@ -415,6 +442,7 @@ CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
 CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
 CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
 CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@@ -478,17 +506,15 @@ CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_IP_DCCP=m
 CONFIG_INET_DCCP_DIAG=m
-CONFIG_IP_DCCP_ACKVEC=y
 #
 # DCCP CCIDs Configuration (EXPERIMENTAL)
 #
-CONFIG_IP_DCCP_CCID2=m
 # CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=m
+CONFIG_IP_DCCP_CCID3=y
 # CONFIG_IP_DCCP_CCID3_DEBUG is not set
 CONFIG_IP_DCCP_CCID3_RTO=100
-CONFIG_IP_DCCP_TFRC_LIB=m
+CONFIG_IP_DCCP_TFRC_LIB=y
 #
 # DCCP Kernel Hacking
@@ -508,13 +534,16 @@ CONFIG_IP_DCCP_TFRC_LIB=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 CONFIG_IRDA=m
@@ -577,8 +606,6 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
 # CONFIG_BT_HCIBTUSB is not set
 # CONFIG_BT_HCIUART is not set
 CONFIG_BT_HCIBCM203X=m
@@ -590,31 +617,27 @@ CONFIG_BT_HCIBFUSB=m
 # CONFIG_BT_HCIBTUART is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 CONFIG_WIRELESS=y
 CONFIG_CFG80211=m
-CONFIG_NL80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
 CONFIG_MAC80211=m
 #
 # Rate control algorithm selection
 #
-CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
-# CONFIG_MAC80211_RC_MINSTREL is not set
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
-CONFIG_MAC80211_RC_DEFAULT_PID=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
-CONFIG_MAC80211_RC_DEFAULT="pid"
 # CONFIG_MAC80211_MESH is not set
 CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
 # CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_IEEE80211=m
+# CONFIG_WIMAX is not set
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -662,17 +685,27 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
 CONFIG_IDE_TIMINGS=y
 CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
@@ -684,7 +717,6 @@ CONFIG_BLK_DEV_IDECS=m
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDESCSI=y
 # CONFIG_IDE_TASK_IOCTL is not set
 CONFIG_IDE_PROC_FS=y
@@ -714,6 +746,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8172 is not set
 # CONFIG_BLK_DEV_IT8213 is not set
 # CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
@@ -728,7 +761,6 @@ CONFIG_BLK_DEV_SL82C105=y
 # CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_BLK_DEV_IDE_PMAC=y
 CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
-CONFIG_BLK_DEV_IDEDMA_PMAC=y
 CONFIG_BLK_DEV_IDEDMA=y
 #
@@ -772,6 +804,7 @@ CONFIG_SCSI_FC_ATTRS=y
 # CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_ACARD is not set
@@ -791,8 +824,12 @@ CONFIG_SCSI_AIC7XXX_OLD=m
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
 # CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
 # CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_EATA is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -822,6 +859,7 @@ CONFIG_SCSI_MAC53C94=y
 # CONFIG_SCSI_SRP is not set
 # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
@@ -881,6 +919,7 @@ CONFIG_THERM_ADT746X=m
 # CONFIG_ANSLCD is not set
 CONFIG_PMAC_RACKMETER=m
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -898,6 +937,8 @@ CONFIG_BMAC=y
 CONFIG_SUNGEM=y
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -913,7 +954,6 @@ CONFIG_PCNET32=y
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
@@ -923,6 +963,7 @@ CONFIG_PCNET32=y
 # CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
@@ -935,6 +976,7 @@ CONFIG_NETDEV_1000=y
 # CONFIG_E1000E is not set
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
@@ -945,18 +987,20 @@ CONFIG_NETDEV_1000=y
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
-# CONFIG_MV643XX_ETH is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
 # CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
 # CONFIG_JME is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_CHELSIO_T3 is not set
 # CONFIG_ENIC is not set
 # CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
 # CONFIG_NIU is not set
@@ -966,6 +1010,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
 # CONFIG_TR is not set
 #
@@ -974,20 +1019,11 @@ CONFIG_NETDEV_10000=y
 # CONFIG_WLAN_PRE80211 is not set
 CONFIG_WLAN_80211=y
 # CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_IPW2100 is not set
-# CONFIG_IPW2200 is not set
 # CONFIG_LIBERTAS is not set
 # CONFIG_LIBERTAS_THINFIRM is not set
 # CONFIG_AIRO is not set
-CONFIG_HERMES=m
-CONFIG_APPLE_AIRPORT=m
-# CONFIG_PLX_HERMES is not set
-# CONFIG_TMD_HERMES is not set
-# CONFIG_NORTEL_HERMES is not set
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-# CONFIG_PCMCIA_SPECTRUM is not set
 # CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
 # CONFIG_AIRO_CS is not set
 # CONFIG_PCMCIA_WL3501 is not set
 CONFIG_PRISM54=m
@@ -997,15 +1033,17 @@ CONFIG_PRISM54=m
 # CONFIG_RTL8187 is not set
 # CONFIG_ADM8211 is not set
 # CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
 CONFIG_P54_COMMON=m
 # CONFIG_P54_USB is not set
 # CONFIG_P54_PCI is not set
+CONFIG_P54_LEDS=y
 # CONFIG_ATH5K is not set
 # CONFIG_ATH9K is not set
-# CONFIG_IWLCORE is not set
+# CONFIG_AR9170_USB is not set
-# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_IPW2100 is not set
-# CONFIG_IWLAGN is not set
+# CONFIG_IPW2200 is not set
-# CONFIG_IWL3945 is not set
+# CONFIG_IWLWIFI is not set
 # CONFIG_HOSTAP is not set
 CONFIG_B43=m
 CONFIG_B43_PCI_AUTOSELECT=y
@@ -1025,6 +1063,19 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
 # CONFIG_B43LEGACY_PIO_MODE is not set
 # CONFIG_ZD1211RW is not set
 # CONFIG_RT2X00 is not set
+CONFIG_HERMES=m
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_APPLE_AIRPORT=m
+# CONFIG_PLX_HERMES is not set
+# CONFIG_TMD_HERMES is not set
+# CONFIG_NORTEL_HERMES is not set
+CONFIG_PCI_HERMES=m
+CONFIG_PCMCIA_HERMES=m
+# CONFIG_PCMCIA_SPECTRUM is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 #
 # USB Network Adapters
@@ -1036,6 +1087,7 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
 CONFIG_USB_USBNET=m
 CONFIG_USB_NET_AX8817X=m
 CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_CDC_EEM is not set
 # CONFIG_USB_NET_DM9601 is not set
 # CONFIG_USB_NET_SMSC95XX is not set
 # CONFIG_USB_NET_GL620A is not set
@@ -1099,7 +1151,7 @@ CONFIG_INPUT_KEYBOARD=y
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
+CONFIG_MOUSE_APPLETOUCH=y
 # CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
@@ -1150,10 +1202,13 @@ CONFIG_SERIAL_PMACZILOG_TTYS=y
 # CONFIG_SERIAL_JSM is not set
 # CONFIG_SERIAL_OF_PLATFORM is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_HVC_UDBG is not set
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 CONFIG_NVRAM=y
 CONFIG_GEN_RTC=y
 # CONFIG_GEN_RTC_X is not set
@@ -1232,12 +1287,9 @@ CONFIG_I2C_POWERMAC=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@@ -1259,11 +1311,11 @@ CONFIG_BATTERY_PMU=y
 # CONFIG_THERMAL is not set
 # CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 CONFIG_SSB=m
 CONFIG_SSB_SPROM=y
 CONFIG_SSB_PCIHOST_POSSIBLE=y
@@ -1281,18 +1333,13 @@ CONFIG_SSB_DRIVER_PCICORE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
-#
-# Voltage and Current regulators
-#
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 #
 # Multimedia devices
@@ -1390,6 +1437,7 @@ CONFIG_FB_ATY_BACKLIGHT=y
 # CONFIG_FB_KYRO is not set
 CONFIG_FB_3DFX=y
 # CONFIG_FB_3DFX_ACCEL is not set
+CONFIG_FB_3DFX_I2C=y
 # CONFIG_FB_VOODOO1 is not set
 # CONFIG_FB_VT8623 is not set
 # CONFIG_FB_TRIDENT is not set
@@ -1399,12 +1447,14 @@ CONFIG_FB_3DFX=y
 # CONFIG_FB_IBM_GXT4500 is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=m
 # CONFIG_LCD_ILI9320 is not set
 # CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_GENERIC=y
 #
 # Display device support
@@ -1444,11 +1494,13 @@ CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
 CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
 CONFIG_SND_DRIVERS=y
 CONFIG_SND_DUMMY=m
 # CONFIG_SND_VIRMIDI is not set
@@ -1486,6 +1538,8 @@ CONFIG_SND_PCI=y
 # CONFIG_SND_INDIGO is not set
 # CONFIG_SND_INDIGOIO is not set
 # CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
 # CONFIG_SND_EMU10K1 is not set
 # CONFIG_SND_EMU10K1X is not set
 # CONFIG_SND_ENS1370 is not set
@@ -1551,28 +1605,31 @@ CONFIG_USB_HID=y
 #
 # Special HID drivers
 #
-CONFIG_HID_COMPAT=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
-CONFIG_HID_BRIGHT=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
-CONFIG_HID_DELL=y
+# CONFIG_DRAGONRISE_FF is not set
 CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
 CONFIG_HID_GYRATION=y
+CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LOGITECH=y
 # CONFIG_LOGITECH_FF is not set
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
 CONFIG_HID_PANTHERLORD=y
 # CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_TOPSEED=y
 # CONFIG_THRUSTMASTER_FF is not set
 # CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
@@ -1603,6 +1660,7 @@ CONFIG_USB_EHCI_HCD=m
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_EHCI_HCD_PPC_OF is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
@@ -1625,24 +1683,23 @@ CONFIG_USB_PRINTER=m
 # CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
-CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_ONETOUCH=m
 # CONFIG_USB_STORAGE_KARMA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
@@ -1665,7 +1722,7 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CP210X is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
@@ -1701,15 +1758,19 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
 # CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
 # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 #
@@ -1726,7 +1787,6 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 CONFIG_USB_APPLEDISPLAY=m
@@ -1738,6 +1798,11 @@ CONFIG_USB_APPLEDISPLAY=m
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_UWB is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -1748,7 +1813,9 @@ CONFIG_LEDS_CLASS=y
 # LED drivers
 #
 # CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP5521 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
 #
 # LED Triggers
@@ -1759,11 +1826,16 @@ CONFIG_LEDS_TRIGGER_IDE_DISK=y
 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
 # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@@ -1774,6 +1846,7 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 # CONFIG_EXT3_FS_SECURITY is not set
@@ -1783,7 +1856,9 @@ CONFIG_EXT4_FS_XATTR=y
 # CONFIG_EXT4_FS_POSIX_ACL is not set
 # CONFIG_EXT4_FS_SECURITY is not set
 CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
 CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
@@ -1792,6 +1867,7 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1801,6 +1877,11 @@ CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 CONFIG_ISO9660_FS=y
@@ -1831,10 +1912,7 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 CONFIG_HFS_FS=m
@@ -1843,6 +1921,7 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1851,6 +1930,7 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1868,7 +1948,6 @@ CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1940,11 +2019,13 @@ CONFIG_NLS_ISO8859_1=m
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
+CONFIG_BINARY_PRINTF=y
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
@@ -1954,15 +2035,18 @@ CONFIG_CRC32=y
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_TEXTSEARCH=y
 CONFIG_TEXTSEARCH_KMP=m
 CONFIG_TEXTSEARCH_BM=m
 CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
 #
 # Kernel hacking
@@ -1973,13 +2057,16 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 CONFIG_SCHEDSTATS=y
 # CONFIG_TIMER_STATS is not set
@@ -1994,6 +2081,7 @@ CONFIG_SCHEDSTATS=y
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
@@ -2001,6 +2089,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -2009,7 +2098,14 @@ CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_LATENCYTOP=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
@@ -2017,12 +2113,19 @@ CONFIG_HAVE_FUNCTION_TRACER=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
@@ -2033,6 +2136,7 @@ CONFIG_XMON_DEFAULT=y
 CONFIG_XMON_DISASSEMBLY=y
 CONFIG_DEBUGGER=y
 CONFIG_IRQSTACKS=y
+# CONFIG_VIRQ_DEBUG is not set
 # CONFIG_BDI_SWITCH is not set
 CONFIG_BOOTX_TEXT=y
 # CONFIG_PPC_EARLY_DEBUG is not set
@@ -2051,13 +2155,20 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_AUTHENC=y
 # CONFIG_CRYPTO_TEST is not set
@@ -2127,6 +2238,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
 # Compression
 #
 CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index b7e034b0a6dd..53512374e1c9 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -131,5 +131,41 @@ static inline int irqs_disabled_flags(unsigned long flags)
 */
 struct irq_chip;
+#ifdef CONFIG_PERF_COUNTERS
+static inline unsigned long test_perf_counter_pending(void)
+{
+        unsigned long x;
+        asm volatile("lbz %0,%1(13)"
+                : "=r" (x)
+                : "i" (offsetof(struct paca_struct, perf_counter_pending)));
+        return x;
+}
+static inline void set_perf_counter_pending(void)
+{
+        asm volatile("stb %0,%1(13)" : :
+                "r" (1),
+                "i" (offsetof(struct paca_struct, perf_counter_pending)));
+}
+static inline void clear_perf_counter_pending(void)
+{
+        asm volatile("stb %0,%1(13)" : :
+                "r" (0),
+                "i" (offsetof(struct paca_struct, perf_counter_pending)));
+}
+#else
+static inline unsigned long test_perf_counter_pending(void)
+{
+        return 0;
+}
+static inline void set_perf_counter_pending(void) {}
+static inline void clear_perf_counter_pending(void) {}
+#endif /* CONFIG_PERF_COUNTERS */
 #endif  /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 0ea1985bdb8b..c8a3cbfe02ff 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -105,6 +105,7 @@ struct paca_struct {
        u8 soft_enabled;                /* irq soft-enable flag */
        u8 hard_enabled;                /* set if irqs are enabled in MSR */
        u8 io_sync;                     /* writel() needs spin_unlock sync */
+        u8 perf_counter_pending;        /* PM interrupt while soft-disabled */
        /* Stuff for accurate time accounting */
        u64 user_time;                  /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h
new file mode 100644
index 000000000000..cc7c887705b8
--- /dev/null
+++ b/arch/powerpc/include/asm/perf_counter.h
@@ -0,0 +1,98 @@
+/*
+ * Performance counter support - PowerPC-specific definitions.
+ *
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#define MAX_HWCOUNTERS          8
+#define MAX_EVENT_ALTERNATIVES  8
+#define MAX_LIMITED_HWCOUNTERS  2
+/*
+ * This struct provides the constants and functions needed to
+ * describe the PMU on a particular POWER-family CPU.
+ */
+struct power_pmu {
+        int     n_counter;
+        int     max_alternatives;
+        u64     add_fields;
+        u64     test_adder;
+        int     (*compute_mmcr)(u64 events[], int n_ev,
+                                unsigned int hwc[], u64 mmcr[]);
+        int     (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
+        int     (*get_alternatives)(u64 event, unsigned int flags,
+                                    u64 alt[]);
+        void    (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
+        int     (*limited_pmc_event)(u64 event);
+        u32     flags;
+        int     n_generic;
+        int     *generic_events;
+        int     (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX];
+};
+extern struct power_pmu *ppmu;
+/*
+ * Values for power_pmu.flags
+ */
+#define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
+#define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
+/*
+ * Values for flags to get_alternatives()
+ */
+#define PPMU_LIMITED_PMC_OK     1       /* can put this on a limited PMC */
+#define PPMU_LIMITED_PMC_REQD   2       /* have to put this on a limited PMC */
+#define PPMU_ONLY_COUNT_RUN     4       /* only counting in run state */
+struct pt_regs;
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs)   perf_misc_flags(regs)
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+/*
+ * The power_pmu.get_constraint function returns a 64-bit value and
+ * a 64-bit mask that express the constraints between this event and
+ * other events.
+ *
+ * The value and mask are divided up into (non-overlapping) bitfields
+ * of three different types:
+ *
+ * Select field: this expresses the constraint that some set of bits
+ * in MMCR* needs to be set to a specific value for this event.  For a
+ * select field, the mask contains 1s in every bit of the field, and
+ * the value contains a unique value for each possible setting of the
+ * MMCR* bits.  The constraint checking code will ensure that two events
+ * that set the same field in their masks have the same value in their
+ * value dwords.
+ *
+ * Add field: this expresses the constraint that there can be at most
+ * N events in a particular class.  A field of k bits can be used for
+ * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
+ * set (and the other bits 0), and the value has only the least significant
+ * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
+ * in the struct power_pmu for this processor come into play.  The
+ * add_fields value contains 1 in the LSB of the field, and the
+ * test_adder contains 2^(k-1) - 1 - N in the field.
+ *
+ * NAND field: this expresses the constraint that you may not have events
+ * in all of a set of classes.  (For example, on PPC970, you can't select
+ * events from the FPU, ISU and IDU simultaneously, although any two are
+ * possible.)  For N classes, the field is N+1 bits wide, and each class
+ * is assigned one bit from the least-significant N bits.  The mask has
+ * only the most-significant bit set, and the value has only the bit
+ * for the event's class set.  The test_adder has the least significant
+ * bit set in the field.
+ *
+ * If an event is not subject to the constraint expressed by a particular
+ * field, then it will have 0 in both the mask and value for that field.
+ */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index e8018d540e87..fb359b0a6937 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -492,11 +492,13 @@
 #define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1      798
 #define SPRN_MMCRA      0x312
+#define   MMCRA_SDSYNC  0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
 #define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
 #define   MMCRA_SLOT    0x07000000UL /* SLOT bits (37-39) */
 #define   MMCRA_SLOT_SHIFT      24
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL     /* SDAR/SIAR synced */
 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
 #define   POWER6_MMCRA_THRM     0x00000020UL
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index d98a30dfd41c..a0b92de51c7e 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -322,6 +322,6 @@ SYSCALL_SPU(epoll_create1)
 SYSCALL_SPU(dup3)
 SYSCALL_SPU(pipe2)
 SYSCALL(inotify_init1)
-SYSCALL(ni_syscall)
+SYSCALL_SPU(perf_counter_open)
 COMPAT_SYS_SPU(preadv)
 COMPAT_SYS_SPU(pwritev)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3f06f8ec81c5..4badac2d11d1 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -341,6 +341,7 @@
 #define __NR_dup3               316
 #define __NR_pipe2              317
 #define __NR_inotify_init1      318
+#define __NR_perf_counter_open  319
 #define __NR_preadv             320
 #define __NR_pwritev            321
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 65cf36502aa6..a7def5f90cad 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -95,6 +95,9 @@ obj64-$(CONFIG_AUDIT)		+= compat_audit.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
+obj-$(CONFIG_PERF_COUNTERS)     += perf_counter.o power4-pmu.o ppc970-pmu.o \
+                                   power5-pmu.o power5+-pmu.o power6-pmu.o \
+                                   power7-pmu.o
 obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index ce90c570cd8e..561b64652311 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -129,6 +129,7 @@ int main(void)
        DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
        DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
        DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
+        DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_counter_pending));
        DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
 #ifdef CONFIG_PPC_MM_SLICES
        DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index abfc32330479..43e073477c34 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -526,6 +526,15 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
 2:
        TRACE_AND_RESTORE_IRQ(r5);
+#ifdef CONFIG_PERF_COUNTERS
+        /* check paca->perf_counter_pending if we're enabling ints */
+        lbz     r3,PACAPERFPEND(r13)
+        and.    r3,r3,r5
+        beq     27f
+        bl      .perf_counter_do_pending
+27:
+#endif /* CONFIG_PERF_COUNTERS */
        /* extract EE bit and use it to restore paca->hard_enabled */
        ld      r3,_MSR(r1)
        rldicl  r4,r3,49,63             /* r0 = (r3 >> 15) & 1 */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 8564a412e7a6..f7f376ea7b17 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -53,6 +53,7 @@
 #include <linux/bootmem.h>
 #include <linux/pci.h>
 #include <linux/debugfs.h>
+#include <linux/perf_counter.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -137,6 +138,11 @@ notrace void raw_local_irq_restore(unsigned long en)
        }
 #endif /* CONFIG_PPC_STD_MMU_64 */
+        if (test_perf_counter_pending()) {
+                clear_perf_counter_pending();
+                perf_counter_do_pending();
+        }
        /*
         * if (get_paca()->hard_enabled) return;
         * But again we need to take care that gcc gets hard_enabled directly
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
new file mode 100644
index 000000000000..bb202388170e
--- /dev/null
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -0,0 +1,1263 @@
+/*
+ * Performance counter support - powerpc architecture code
+ *
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/perf_counter.h>
+#include <linux/percpu.h>
+#include <linux/hardirq.h>
+#include <asm/reg.h>
+#include <asm/pmc.h>
+#include <asm/machdep.h>
+#include <asm/firmware.h>
+#include <asm/ptrace.h>
+struct cpu_hw_counters {
+        int n_counters;
+        int n_percpu;
+        int disabled;
+        int n_added;
+        int n_limited;
+        u8  pmcs_enabled;
+        struct perf_counter *counter[MAX_HWCOUNTERS];
+        u64 events[MAX_HWCOUNTERS];
+        unsigned int flags[MAX_HWCOUNTERS];
+        u64 mmcr[3];
+        struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
+        u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
+};
+DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
+struct power_pmu *ppmu;
+/*
+ * Normally, to ignore kernel events we set the FCS (freeze counters
+ * in supervisor mode) bit in MMCR0, but if the kernel runs with the
+ * hypervisor bit set in the MSR, or if we are running on a processor
+ * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
+ * then we need to use the FCHV bit to ignore kernel events.
+ */
+static unsigned int freeze_counters_kernel = MMCR0_FCS;
+static void perf_counter_interrupt(struct pt_regs *regs);
+void perf_counter_print_debug(void)
+{
+}
+/*
+ * Read one performance monitor counter (PMC).
+ */
+static unsigned long read_pmc(int idx)
+{
+        unsigned long val;
+        switch (idx) {
+        case 1:
+                val = mfspr(SPRN_PMC1);
+                break;
+        case 2:
+                val = mfspr(SPRN_PMC2);
+                break;
+        case 3:
+                val = mfspr(SPRN_PMC3);
+                break;
+        case 4:
+                val = mfspr(SPRN_PMC4);
+                break;
+        case 5:
+                val = mfspr(SPRN_PMC5);
+                break;
+        case 6:
+                val = mfspr(SPRN_PMC6);
+                break;
+        case 7:
+                val = mfspr(SPRN_PMC7);
+                break;
+        case 8:
+                val = mfspr(SPRN_PMC8);
+                break;
+        default:
+                printk(KERN_ERR "oops trying to read PMC%d\n", idx);
+                val = 0;
+        }
+        return val;
+}
+/*
+ * Write one PMC.
+ */
+static void write_pmc(int idx, unsigned long val)
+{
+        switch (idx) {
+        case 1:
+                mtspr(SPRN_PMC1, val);
+                break;
+        case 2:
+                mtspr(SPRN_PMC2, val);
+                break;
+        case 3:
+                mtspr(SPRN_PMC3, val);
+                break;
+        case 4:
+                mtspr(SPRN_PMC4, val);
+                break;
+        case 5:
+                mtspr(SPRN_PMC5, val);
+                break;
+        case 6:
+                mtspr(SPRN_PMC6, val);
+                break;
+        case 7:
+                mtspr(SPRN_PMC7, val);
+                break;
+        case 8:
+                mtspr(SPRN_PMC8, val);
+                break;
+        default:
+                printk(KERN_ERR "oops trying to write PMC%d\n", idx);
+        }
+}
+/*
+ * Check if a set of events can all go on the PMU at once.
+ * If they can't, this will look at alternative codes for the events
+ * and see if any combination of alternative codes is feasible.
+ * The feasible set is returned in event[].
+ */
+static int power_check_constraints(u64 event[], unsigned int cflags[],
+                                   int n_ev)
+{
+        u64 mask, value, nv;
+        u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+        u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+        u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+        u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
+        int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
+        int i, j;
+        u64 addf = ppmu->add_fields;
+        u64 tadd = ppmu->test_adder;
+        if (n_ev > ppmu->n_counter)
+                return -1;
+        /* First see if the events will go on as-is */
+        for (i = 0; i < n_ev; ++i) {
+                if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
+                    && !ppmu->limited_pmc_event(event[i])) {
+                        ppmu->get_alternatives(event[i], cflags[i],
+                                               alternatives[i]);
+                        event[i] = alternatives[i][0];
+                }
+                if (ppmu->get_constraint(event[i], &amasks[i][0],
+                                         &avalues[i][0]))
+                        return -1;
+        }
+        value = mask = 0;
+        for (i = 0; i < n_ev; ++i) {
+                nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
+                if ((((nv + tadd) ^ value) & mask) != 0 ||
+                    (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
+                        break;
+                value = nv;
+                mask |= amasks[i][0];
+        }
+        if (i == n_ev)
+                return 0;       /* all OK */
+        /* doesn't work, gather alternatives... */
+        if (!ppmu->get_alternatives)
+                return -1;
+        for (i = 0; i < n_ev; ++i) {
+                choice[i] = 0;
+                n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
+                                                  alternatives[i]);
+                for (j = 1; j < n_alt[i]; ++j)
+                        ppmu->get_constraint(alternatives[i][j],
+                                             &amasks[i][j], &avalues[i][j]);
+        }
+        /* enumerate all possibilities and see if any will work */
+        i = 0;
+        j = -1;
+        value = mask = nv = 0;
+        while (i < n_ev) {
+                if (j >= 0) {
+                        /* we're backtracking, restore context */
+                        value = svalues[i];
+                        mask = smasks[i];
+                        j = choice[i];
+                }
+                /*
+                 * See if any alternative k for event i,
+                 * where k > j, will satisfy the constraints.
+                 */
+                while (++j < n_alt[i]) {
+                        nv = (value | avalues[i][j]) +
+                                (value & avalues[i][j] & addf);
+                        if ((((nv + tadd) ^ value) & mask) == 0 &&
+                            (((nv + tadd) ^ avalues[i][j])
+                             & amasks[i][j]) == 0)
+                                break;
+                }
+                if (j >= n_alt[i]) {
+                        /*
+                         * No feasible alternative, backtrack
+                         * to event i-1 and continue enumerating its
+                         * alternatives from where we got up to.
+                         */
+                        if (--i < 0)
+                                return -1;
+                } else {
+                        /*
+                         * Found a feasible alternative for event i,
+                         * remember where we got up to with this event,
+                         * go on to the next event, and start with
+                         * the first alternative for it.
+                         */
+                        choice[i] = j;
+                        svalues[i] = value;
+                        smasks[i] = mask;
+                        value = nv;
+                        mask |= amasks[i][j];
+                        ++i;
+                        j = -1;
+                }
+        }
+        /* OK, we have a feasible combination, tell the caller the solution */
+        for (i = 0; i < n_ev; ++i)
+                event[i] = alternatives[i][choice[i]];
+        return 0;
+}
+/*
+ * Check if newly-added counters have consistent settings for
+ * exclude_{user,kernel,hv} with each other and any previously
+ * added counters.
+ */
+static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
+                          int n_prev, int n_new)
+{
+        int eu = 0, ek = 0, eh = 0;
+        int i, n, first;
+        struct perf_counter *counter;
+        n = n_prev + n_new;
+        if (n <= 1)
+                return 0;
+        first = 1;
+        for (i = 0; i < n; ++i) {
+                if (cflags[i] & PPMU_LIMITED_PMC_OK) {
+                        cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
+                        continue;
+                }
+                counter = ctrs[i];
+                if (first) {
+                        eu = counter->attr.exclude_user;
+                        ek = counter->attr.exclude_kernel;
+                        eh = counter->attr.exclude_hv;
+                        first = 0;
+                } else if (counter->attr.exclude_user != eu ||
+                           counter->attr.exclude_kernel != ek ||
+                           counter->attr.exclude_hv != eh) {
+                        return -EAGAIN;
+                }
+        }
+        if (eu || ek || eh)
+                for (i = 0; i < n; ++i)
+                        if (cflags[i] & PPMU_LIMITED_PMC_OK)
+                                cflags[i] |= PPMU_LIMITED_PMC_REQD;
+        return 0;
+}
+static void power_pmu_read(struct perf_counter *counter)
+{
+        long val, delta, prev;
+        if (!counter->hw.idx)
+                return;
+        /*
+         * Performance monitor interrupts come even when interrupts
+         * are soft-disabled, as long as interrupts are hard-enabled.
+         * Therefore we treat them like NMIs.
+         */
+        do {
+                prev = atomic64_read(&counter->hw.prev_count);
+                barrier();
+                val = read_pmc(counter->hw.idx);
+        } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev);
+        /* The counters are only 32 bits wide */
+        delta = (val - prev) & 0xfffffffful;
+        atomic64_add(delta, &counter->count);
+        atomic64_sub(delta, &counter->hw.period_left);
+}
+/*
+ * On some machines, PMC5 and PMC6 can't be written, don't respect
+ * the freeze conditions, and don't generate interrupts.  This tells
+ * us if `counter' is using such a PMC.
+ */
+static int is_limited_pmc(int pmcnum)
+{
+        return (ppmu->flags & PPMU_LIMITED_PMC5_6)
+                && (pmcnum == 5 || pmcnum == 6);
+}
+static void freeze_limited_counters(struct cpu_hw_counters *cpuhw,
+                                    unsigned long pmc5, unsigned long pmc6)
+{
+        struct perf_counter *counter;
+        u64 val, prev, delta;
+        int i;
+        for (i = 0; i < cpuhw->n_limited; ++i) {
+                counter = cpuhw->limited_counter[i];
+                if (!counter->hw.idx)
+                        continue;
+                val = (counter->hw.idx == 5) ? pmc5 : pmc6;
+                prev = atomic64_read(&counter->hw.prev_count);
+                counter->hw.idx = 0;
+                delta = (val - prev) & 0xfffffffful;
+                atomic64_add(delta, &counter->count);
+        }
+}
+static void thaw_limited_counters(struct cpu_hw_counters *cpuhw,
+                                  unsigned long pmc5, unsigned long pmc6)
+{
+        struct perf_counter *counter;
+        u64 val;
+        int i;
+        for (i = 0; i < cpuhw->n_limited; ++i) {
+                counter = cpuhw->limited_counter[i];
+                counter->hw.idx = cpuhw->limited_hwidx[i];
+                val = (counter->hw.idx == 5) ? pmc5 : pmc6;
+                atomic64_set(&counter->hw.prev_count, val);
+                perf_counter_update_userpage(counter);
+        }
+}
+/*
+ * Since limited counters don't respect the freeze conditions, we
+ * have to read them immediately after freezing or unfreezing the
+ * other counters.  We try to keep the values from the limited
+ * counters as consistent as possible by keeping the delay (in
+ * cycles and instructions) between freezing/unfreezing and reading
+ * the limited counters as small and consistent as possible.
+ * Therefore, if any limited counters are in use, we read them
+ * both, and always in the same order, to minimize variability,
+ * and do it inside the same asm that writes MMCR0.
+ */
+static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
+{
+        unsigned long pmc5, pmc6;
+        if (!cpuhw->n_limited) {
+                mtspr(SPRN_MMCR0, mmcr0);
+                return;
+        }
+        /*
+         * Write MMCR0, then read PMC5 and PMC6 immediately.
+         * To ensure we don't get a performance monitor interrupt
+         * between writing MMCR0 and freezing/thawing the limited
+         * counters, we first write MMCR0 with the counter overflow
+         * interrupt enable bits turned off.
+         */
+        asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
+                     : "=&r" (pmc5), "=&r" (pmc6)
+                     : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
+                       "i" (SPRN_MMCR0),
+                       "i" (SPRN_PMC5), "i" (SPRN_PMC6));
+        if (mmcr0 & MMCR0_FC)
+                freeze_limited_counters(cpuhw, pmc5, pmc6);
+        else
+                thaw_limited_counters(cpuhw, pmc5, pmc6);
+        /*
+         * Write the full MMCR0 including the counter overflow interrupt
+         * enable bits, if necessary.
+         */
+        if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
+                mtspr(SPRN_MMCR0, mmcr0);
+}
+/*
+ * Disable all counters to prevent PMU interrupts and to allow
+ * counters to be added or removed.
+ */
+void hw_perf_disable(void)
+{
+        struct cpu_hw_counters *cpuhw;
+        unsigned long ret;
+        unsigned long flags;
+        local_irq_save(flags);
+        cpuhw = &__get_cpu_var(cpu_hw_counters);
+        ret = cpuhw->disabled;
+        if (!ret) {
+                cpuhw->disabled = 1;
+                cpuhw->n_added = 0;
+                /*
+                 * Check if we ever enabled the PMU on this cpu.
+                 */
+                if (!cpuhw->pmcs_enabled) {
+                        if (ppc_md.enable_pmcs)
+                                ppc_md.enable_pmcs();
+                        cpuhw->pmcs_enabled = 1;
+                }
+                /*
+                 * Disable instruction sampling if it was enabled
+                 */
+                if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
+                        mtspr(SPRN_MMCRA,
+                              cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
+                        mb();
+                }
+                /*
+                 * Set the 'freeze counters' bit.
+                 * The barrier is to make sure the mtspr has been
+                 * executed and the PMU has frozen the counters
+                 * before we return.
+                 */
+                write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
+                mb();
+        }
+        local_irq_restore(flags);
+}
+/*
+ * Re-enable all counters if disable == 0.
+ * If we were previously disabled and counters were added, then
+ * put the new config on the PMU.
+ */
+void hw_perf_enable(void)
+{
+        struct perf_counter *counter;
+        struct cpu_hw_counters *cpuhw;
+        unsigned long flags;
+        long i;
+        unsigned long val;
+        s64 left;
+        unsigned int hwc_index[MAX_HWCOUNTERS];
+        int n_lim;
+        int idx;
+        local_irq_save(flags);
+        cpuhw = &__get_cpu_var(cpu_hw_counters);
+        if (!cpuhw->disabled) {
+                local_irq_restore(flags);
+                return;
+        }
+        cpuhw->disabled = 0;
+        /*
+         * If we didn't change anything, or only removed counters,
+         * no need to recalculate MMCR* settings and reset the PMCs.
+         * Just reenable the PMU with the current MMCR* settings
+         * (possibly updated for removal of counters).
+         */
+        if (!cpuhw->n_added) {
+                mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
+                mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
+                if (cpuhw->n_counters == 0)
+                        get_lppaca()->pmcregs_in_use = 0;
+                goto out_enable;
+        }
+        /*
+         * Compute MMCR* values for the new set of counters
+         */
+        if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index,
+                               cpuhw->mmcr)) {
+                /* shouldn't ever get here */
+                printk(KERN_ERR "oops compute_mmcr failed\n");
+                goto out;
+        }
+        /*
+         * Add in MMCR0 freeze bits corresponding to the
+         * attr.exclude_* bits for the first counter.
+         * We have already checked that all counters have the
+         * same values for these bits as the first counter.
+         */
+        counter = cpuhw->counter[0];
+        if (counter->attr.exclude_user)
+                cpuhw->mmcr[0] |= MMCR0_FCP;
+        if (counter->attr.exclude_kernel)
+                cpuhw->mmcr[0] |= freeze_counters_kernel;
+        if (counter->attr.exclude_hv)
+                cpuhw->mmcr[0] |= MMCR0_FCHV;
+        /*
+         * Write the new configuration to MMCR* with the freeze
+         * bit set and set the hardware counters to their initial values.
+         * Then unfreeze the counters.
+         */
+        get_lppaca()->pmcregs_in_use = 1;
+        mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
+        mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
+        mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
+                                | MMCR0_FC);
+        /*
+         * Read off any pre-existing counters that need to move
+         * to another PMC.
+         */
+        for (i = 0; i < cpuhw->n_counters; ++i) {
+                counter = cpuhw->counter[i];
+                if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) {
+                        power_pmu_read(counter);
+                        write_pmc(counter->hw.idx, 0);
+                        counter->hw.idx = 0;
+                }
+        }
+        /*
+         * Initialize the PMCs for all the new and moved counters.
+         */
+        cpuhw->n_limited = n_lim = 0;
+        for (i = 0; i < cpuhw->n_counters; ++i) {
+                counter = cpuhw->counter[i];
+                if (counter->hw.idx)
+                        continue;
+                idx = hwc_index[i] + 1;
+                if (is_limited_pmc(idx)) {
+                        cpuhw->limited_counter[n_lim] = counter;
+                        cpuhw->limited_hwidx[n_lim] = idx;
+                        ++n_lim;
+                        continue;
+                }
+                val = 0;
+                if (counter->hw.sample_period) {
+                        left = atomic64_read(&counter->hw.period_left);
+                        if (left < 0x80000000L)
+                                val = 0x80000000L - left;
+                }
+                atomic64_set(&counter->hw.prev_count, val);
+                counter->hw.idx = idx;
+                write_pmc(idx, val);
+                perf_counter_update_userpage(counter);
+        }
+        cpuhw->n_limited = n_lim;
+        cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
+ out_enable:
+        mb();
+        write_mmcr0(cpuhw, cpuhw->mmcr[0]);
+        /*
+         * Enable instruction sampling if necessary
+         */
+        if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
+                mb();
+                mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
+        }
+ out:
+        local_irq_restore(flags);
+}
+static int collect_events(struct perf_counter *group, int max_count,
+                          struct perf_counter *ctrs[], u64 *events,
+                          unsigned int *flags)
+{
+        int n = 0;
+        struct perf_counter *counter;
+        if (!is_software_counter(group)) {
+                if (n >= max_count)
+                        return -1;
+                ctrs[n] = group;
+                flags[n] = group->hw.counter_base;
+                events[n++] = group->hw.config;
+        }
+        list_for_each_entry(counter, &group->sibling_list, list_entry) {
+                if (!is_software_counter(counter) &&
+                    counter->state != PERF_COUNTER_STATE_OFF) {
+                        if (n >= max_count)
+                                return -1;
+                        ctrs[n] = counter;
+                        flags[n] = counter->hw.counter_base;
+                        events[n++] = counter->hw.config;
+                }
+        }
+        return n;
+}
+static void counter_sched_in(struct perf_counter *counter, int cpu)
+{
+        counter->state = PERF_COUNTER_STATE_ACTIVE;
+        counter->oncpu = cpu;
+        counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped;
+        if (is_software_counter(counter))
+                counter->pmu->enable(counter);
+}
+/*
+ * Called to enable a whole group of counters.
+ * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
+ * Assumes the caller has disabled interrupts and has
+ * frozen the PMU with hw_perf_save_disable.
+ */
+int hw_perf_group_sched_in(struct perf_counter *group_leader,
+               struct perf_cpu_context *cpuctx,
+               struct perf_counter_context *ctx, int cpu)
+{
+        struct cpu_hw_counters *cpuhw;
+        long i, n, n0;
+        struct perf_counter *sub;
+        cpuhw = &__get_cpu_var(cpu_hw_counters);
+        n0 = cpuhw->n_counters;
+        n = collect_events(group_leader, ppmu->n_counter - n0,
+                           &cpuhw->counter[n0], &cpuhw->events[n0],
+                           &cpuhw->flags[n0]);
+        if (n < 0)
+                return -EAGAIN;
+        if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
+                return -EAGAIN;
+        i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
+        if (i < 0)
+                return -EAGAIN;
+        cpuhw->n_counters = n0 + n;
+        cpuhw->n_added += n;
+        /*
+         * OK, this group can go on; update counter states etc.,
+         * and enable any software counters
+         */
+        for (i = n0; i < n0 + n; ++i)
+                cpuhw->counter[i]->hw.config = cpuhw->events[i];
+        cpuctx->active_oncpu += n;
+        n = 1;
+        counter_sched_in(group_leader, cpu);
+        list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
+                if (sub->state != PERF_COUNTER_STATE_OFF) {
+                        counter_sched_in(sub, cpu);
+                        ++n;
+                }
+        }
+        ctx->nr_active += n;
+        return 1;
+}
+/*
+ * Add a counter to the PMU.
+ * If all counters are not already frozen, then we disable and
+ * re-enable the PMU in order to get hw_perf_enable to do the
+ * actual work of reconfiguring the PMU.
+ */
+static int power_pmu_enable(struct perf_counter *counter)
+{
+        struct cpu_hw_counters *cpuhw;
+        unsigned long flags;
+        int n0;
+        int ret = -EAGAIN;
+        local_irq_save(flags);
+        perf_disable();
+        /*
+         * Add the counter to the list (if there is room)
+         * and check whether the total set is still feasible.
+         */
+        cpuhw = &__get_cpu_var(cpu_hw_counters);
+        n0 = cpuhw->n_counters;
+        if (n0 >= ppmu->n_counter)
+                goto out;
+        cpuhw->counter[n0] = counter;
+        cpuhw->events[n0] = counter->hw.config;
+        cpuhw->flags[n0] = counter->hw.counter_base;
+        if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
+                goto out;
+        if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
+                goto out;
+        counter->hw.config = cpuhw->events[n0];
+        ++cpuhw->n_counters;
+        ++cpuhw->n_added;
+        ret = 0;
+ out:
+        perf_enable();
+        local_irq_restore(flags);
+        return ret;
+}
+/*
+ * Remove a counter from the PMU.
+ */
+static void power_pmu_disable(struct perf_counter *counter)
+{
+        struct cpu_hw_counters *cpuhw;
+        long i;
+        unsigned long flags;
+        local_irq_save(flags);
+        perf_disable();
+        power_pmu_read(counter);
+        cpuhw = &__get_cpu_var(cpu_hw_counters);
+        for (i = 0; i < cpuhw->n_counters; ++i) {
+                if (counter == cpuhw->counter[i]) {
+                        while (++i < cpuhw->n_counters)
+                                cpuhw->counter[i-1] = cpuhw->counter[i];
+                        --cpuhw->n_counters;
+                        ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr);
+                        if (counter->hw.idx) {
+                                write_pmc(counter->hw.idx, 0);
+                                counter->hw.idx = 0;
+                        }
+                        perf_counter_update_userpage(counter);
+                        break;
+                }
+        }
+        for (i = 0; i < cpuhw->n_limited; ++i)
+                if (counter == cpuhw->limited_counter[i])
+                        break;
+        if (i < cpuhw->n_limited) {
+                while (++i < cpuhw->n_limited) {
+                        cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
+                        cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
+                }
+                --cpuhw->n_limited;
+        }
+        if (cpuhw->n_counters == 0) {
+                /* disable exceptions if no counters are running */
+                cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
+        }
+        perf_enable();
+        local_irq_restore(flags);
+}
+/*
+ * Re-enable interrupts on a counter after they were throttled
+ * because they were coming too fast.
+ */
+static void power_pmu_unthrottle(struct perf_counter *counter)
+{
+        s64 val, left;
+        unsigned long flags;
+        if (!counter->hw.idx || !counter->hw.sample_period)
+                return;
+        local_irq_save(flags);
+        perf_disable();
+        power_pmu_read(counter);
+        left = counter->hw.sample_period;
+        counter->hw.last_period = left;
+        val = 0;
+        if (left < 0x80000000L)
+                val = 0x80000000L - left;
+        write_pmc(counter->hw.idx, val);
+        atomic64_set(&counter->hw.prev_count, val);
+        atomic64_set(&counter->hw.period_left, left);
+        perf_counter_update_userpage(counter);
+        perf_enable();
+        local_irq_restore(flags);
+}
+struct pmu power_pmu = {
+        .enable         = power_pmu_enable,
+        .disable        = power_pmu_disable,
+        .read           = power_pmu_read,
+        .unthrottle     = power_pmu_unthrottle,
+};
+/*
+ * Return 1 if we might be able to put counter on a limited PMC,
+ * or 0 if not.
+ * A counter can only go on a limited PMC if it counts something
+ * that a limited PMC can count, doesn't require interrupts, and
+ * doesn't exclude any processor mode.
+ */
+static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev,
+                                 unsigned int flags)
+{
+        int n;
+        u64 alt[MAX_EVENT_ALTERNATIVES];
+        if (counter->attr.exclude_user
+            || counter->attr.exclude_kernel
+            || counter->attr.exclude_hv
+            || counter->attr.sample_period)
+                return 0;
+        if (ppmu->limited_pmc_event(ev))
+                return 1;
+        /*
+         * The requested event isn't on a limited PMC already;
+         * see if any alternative code goes on a limited PMC.
+         */
+        if (!ppmu->get_alternatives)
+                return 0;
+        flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
+        n = ppmu->get_alternatives(ev, flags, alt);
+        return n > 0;
+}
+/*
+ * Find an alternative event that goes on a normal PMC, if possible,
+ * and return the event code, or 0 if there is no such alternative.
+ * (Note: event code 0 is "don't count" on all machines.)
+ */
+static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
+{
+        u64 alt[MAX_EVENT_ALTERNATIVES];
+        int n;
+        flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
+        n = ppmu->get_alternatives(ev, flags, alt);
+        if (!n)
+                return 0;
+        return alt[0];
+}
+/* Number of perf_counters counting hardware events */
+static atomic_t num_counters;
+/* Used to avoid races in calling reserve/release_pmc_hardware */
+static DEFINE_MUTEX(pmc_reserve_mutex);
+/*
+ * Release the PMU if this is the last perf_counter.
+ */
+static void hw_perf_counter_destroy(struct perf_counter *counter)
+{
+        if (!atomic_add_unless(&num_counters, -1, 1)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_dec_return(&num_counters) == 0)
+                        release_pmc_hardware();
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+}
+/*
+ * Translate a generic cache event config to a raw event code.
+ */
+static int hw_perf_cache_event(u64 config, u64 *eventp)
+{
+        unsigned long type, op, result;
+        int ev;
+        if (!ppmu->cache_events)
+                return -EINVAL;
+        /* unpack config */
+        type = config & 0xff;
+        op = (config >> 8) & 0xff;
+        result = (config >> 16) & 0xff;
+        if (type >= PERF_COUNT_HW_CACHE_MAX ||
+            op >= PERF_COUNT_HW_CACHE_OP_MAX ||
+            result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+        ev = (*ppmu->cache_events)[type][op][result];
+        if (ev == 0)
+                return -EOPNOTSUPP;
+        if (ev == -1)
+                return -EINVAL;
+        *eventp = ev;
+        return 0;
+}
+const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
+{
+        u64 ev;
+        unsigned long flags;
+        struct perf_counter *ctrs[MAX_HWCOUNTERS];
+        u64 events[MAX_HWCOUNTERS];
+        unsigned int cflags[MAX_HWCOUNTERS];
+        int n;
+        int err;
+        if (!ppmu)
+                return ERR_PTR(-ENXIO);
+        switch (counter->attr.type) {
+        case PERF_TYPE_HARDWARE:
+                ev = counter->attr.config;
+                if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
+                        return ERR_PTR(-EOPNOTSUPP);
+                ev = ppmu->generic_events[ev];
+                break;
+        case PERF_TYPE_HW_CACHE:
+                err = hw_perf_cache_event(counter->attr.config, &ev);
+                if (err)
+                        return ERR_PTR(err);
+                break;
+        case PERF_TYPE_RAW:
+                ev = counter->attr.config;
+                break;
+        }
+        counter->hw.config_base = ev;
+        counter->hw.idx = 0;
+        /*
+         * If we are not running on a hypervisor, force the
+         * exclude_hv bit to 0 so that we don't care what
+         * the user set it to.
+         */
+        if (!firmware_has_feature(FW_FEATURE_LPAR))
+                counter->attr.exclude_hv = 0;
+        /*
+         * If this is a per-task counter, then we can use
+         * PM_RUN_* events interchangeably with their non RUN_*
+         * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
+         * XXX we should check if the task is an idle task.
+         */
+        flags = 0;
+        if (counter->ctx->task)
+                flags |= PPMU_ONLY_COUNT_RUN;
+        /*
+         * If this machine has limited counters, check whether this
+         * event could go on a limited counter.
+         */
+        if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
+                if (can_go_on_limited_pmc(counter, ev, flags)) {
+                        flags |= PPMU_LIMITED_PMC_OK;
+                } else if (ppmu->limited_pmc_event(ev)) {
+                        /*
+                         * The requested event is on a limited PMC,
+                         * but we can't use a limited PMC; see if any
+                         * alternative goes on a normal PMC.
+                         */
+                        ev = normal_pmc_alternative(ev, flags);
+                        if (!ev)
+                                return ERR_PTR(-EINVAL);
+                }
+        }
+        /*
+         * If this is in a group, check if it can go on with all the
+         * other hardware counters in the group.  We assume the counter
+         * hasn't been linked into its leader's sibling list at this point.
+         */
+        n = 0;
+        if (counter->group_leader != counter) {
+                n = collect_events(counter->group_leader, ppmu->n_counter - 1,
+                                   ctrs, events, cflags);
+                if (n < 0)
+                        return ERR_PTR(-EINVAL);
+        }
+        events[n] = ev;
+        ctrs[n] = counter;
+        cflags[n] = flags;
+        if (check_excludes(ctrs, cflags, n, 1))
+                return ERR_PTR(-EINVAL);
+        if (power_check_constraints(events, cflags, n + 1))
+                return ERR_PTR(-EINVAL);
+        counter->hw.config = events[n];
+        counter->hw.counter_base = cflags[n];
+        counter->hw.last_period = counter->hw.sample_period;
+        atomic64_set(&counter->hw.period_left, counter->hw.last_period);
+        /*
+         * See if we need to reserve the PMU.
+         * If no counters are currently in use, then we have to take a
+         * mutex to ensure that we don't race with another task doing
+         * reserve_pmc_hardware or release_pmc_hardware.
+         */
+        err = 0;
+        if (!atomic_inc_not_zero(&num_counters)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_read(&num_counters) == 0 &&
+                    reserve_pmc_hardware(perf_counter_interrupt))
+                        err = -EBUSY;
+                else
+                        atomic_inc(&num_counters);
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+        counter->destroy = hw_perf_counter_destroy;
+        if (err)
+                return ERR_PTR(err);
+        return &power_pmu;
+}
+/*
+ * A counter has overflowed; update its count and record
+ * things if requested.  Note that interrupts are hard-disabled
+ * here so there is no possibility of being interrupted.
+ */
+static void record_and_restart(struct perf_counter *counter, long val,
+                               struct pt_regs *regs, int nmi)
+{
+        u64 period = counter->hw.sample_period;
+        s64 prev, delta, left;
+        int record = 0;
+        u64 addr, mmcra, sdsync;
+        /* we don't have to worry about interrupts here */
+        prev = atomic64_read(&counter->hw.prev_count);
+        delta = (val - prev) & 0xfffffffful;
+        atomic64_add(delta, &counter->count);
+        /*
+         * See if the total period for this counter has expired,
+         * and update for the next period.
+         */
+        val = 0;
+        left = atomic64_read(&counter->hw.period_left) - delta;
+        if (period) {
+                if (left <= 0) {
+                        left += period;
+                        if (left <= 0)
+                                left = period;
+                        record = 1;
+                }
+                if (left < 0x80000000L)
+                        val = 0x80000000L - left;
+        }
+        /*
+         * Finally record data if requested.
+         */
+        if (record) {
+                struct perf_sample_data data = {
+                        .regs   = regs,
+                        .addr   = 0,
+                        .period = counter->hw.last_period,
+                };
+                if (counter->attr.sample_type & PERF_SAMPLE_ADDR) {
+                        /*
+                         * The user wants a data address recorded.
+                         * If we're not doing instruction sampling,
+                         * give them the SDAR (sampled data address).
+                         * If we are doing instruction sampling, then only
+                         * give them the SDAR if it corresponds to the
+                         * instruction pointed to by SIAR; this is indicated
+                         * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA.
+                         */
+                        mmcra = regs->dsisr;
+                        sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
+                                POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
+                        if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
+                                data.addr = mfspr(SPRN_SDAR);
+                }
+                if (perf_counter_overflow(counter, nmi, &data)) {
+                        /*
+                         * Interrupts are coming too fast - throttle them
+                         * by setting the counter to 0, so it will be
+                         * at least 2^30 cycles until the next interrupt
+                         * (assuming each counter counts at most 2 counts
+                         * per cycle).
+                         */
+                        val = 0;
+                        left = ~0ULL >> 1;
+                }
+        }
+        write_pmc(counter->hw.idx, val);
+        atomic64_set(&counter->hw.prev_count, val);
+        atomic64_set(&counter->hw.period_left, left);
+        perf_counter_update_userpage(counter);
+}
+/*
+ * Called from generic code to get the misc flags (i.e. processor mode)
+ * for an event.
+ */
+unsigned long perf_misc_flags(struct pt_regs *regs)
+{
+        unsigned long mmcra;
+        if (TRAP(regs) != 0xf00) {
+                /* not a PMU interrupt */
+                return user_mode(regs) ? PERF_EVENT_MISC_USER :
+                        PERF_EVENT_MISC_KERNEL;
+        }
+        mmcra = regs->dsisr;
+        if (ppmu->flags & PPMU_ALT_SIPR) {
+                if (mmcra & POWER6_MMCRA_SIHV)
+                        return PERF_EVENT_MISC_HYPERVISOR;
+                return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
+                        PERF_EVENT_MISC_KERNEL;
+        }
+        if (mmcra & MMCRA_SIHV)
+                return PERF_EVENT_MISC_HYPERVISOR;
+        return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
+                        PERF_EVENT_MISC_KERNEL;
+}
+/*
+ * Called from generic code to get the instruction pointer
+ * for an event.
+ */
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
+        unsigned long mmcra;
+        unsigned long ip;
+        unsigned long slot;
+        if (TRAP(regs) != 0xf00)
+                return regs->nip;       /* not a PMU interrupt */
+        ip = mfspr(SPRN_SIAR);
+        mmcra = regs->dsisr;
+        if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
+                slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
+                if (slot > 1)
+                        ip += 4 * (slot - 1);
+        }
+        return ip;
+}
+/*
+ * Performance monitor interrupt stuff
+ */
+static void perf_counter_interrupt(struct pt_regs *regs)
+{
+        int i;
+        struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
+        struct perf_counter *counter;
+        long val;
+        int found = 0;
+        int nmi;
+        if (cpuhw->n_limited)
+                freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
+                                        mfspr(SPRN_PMC6));
+        /*
+         * Overload regs->dsisr to store MMCRA so we only need to read it once.
+         */
+        regs->dsisr = mfspr(SPRN_MMCRA);
+        /*
+         * If interrupts were soft-disabled when this PMU interrupt
+         * occurred, treat it as an NMI.
+         */
+        nmi = !regs->softe;
+        if (nmi)
+                nmi_enter();
+        else
+                irq_enter();
+        for (i = 0; i < cpuhw->n_counters; ++i) {
+                counter = cpuhw->counter[i];
+                if (!counter->hw.idx || is_limited_pmc(counter->hw.idx))
+                        continue;
+                val = read_pmc(counter->hw.idx);
+                if ((int)val < 0) {
+                        /* counter has overflowed */
+                        found = 1;
+                        record_and_restart(counter, val, regs, nmi);
+                }
+        }
+        /*
+         * In case we didn't find and reset the counter that caused
+         * the interrupt, scan all counters and reset any that are
+         * negative, to avoid getting continual interrupts.
+         * Any that we processed in the previous loop will not be negative.
+         */
+        if (!found) {
+                for (i = 0; i < ppmu->n_counter; ++i) {
+                        if (is_limited_pmc(i + 1))
+                                continue;
+                        val = read_pmc(i + 1);
+                        if ((int)val < 0)
+                                write_pmc(i + 1, 0);
+                }
+        }
+        /*
+         * Reset MMCR0 to its normal value.  This will set PMXE and
+         * clear FC (freeze counters) and PMAO (perf mon alert occurred)
+         * and thus allow interrupts to occur again.
+         * XXX might want to use MSR.PM to keep the counters frozen until
+         * we get back out of this interrupt.
+         */
+        write_mmcr0(cpuhw, cpuhw->mmcr[0]);
+        if (nmi)
+                nmi_exit();
+        else
+                irq_exit();
+}
+void hw_perf_counter_setup(int cpu)
+{
+        struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu);
+        memset(cpuhw, 0, sizeof(*cpuhw));
+        cpuhw->mmcr[0] = MMCR0_FC;
+}
+extern struct power_pmu power4_pmu;
+extern struct power_pmu ppc970_pmu;
+extern struct power_pmu power5_pmu;
+extern struct power_pmu power5p_pmu;
+extern struct power_pmu power6_pmu;
+extern struct power_pmu power7_pmu;
+static int init_perf_counters(void)
+{
+        unsigned long pvr;
+        /* XXX should get this from cputable */
+        pvr = mfspr(SPRN_PVR);
+        switch (PVR_VER(pvr)) {
+        case PV_POWER4:
+        case PV_POWER4p:
+                ppmu = &power4_pmu;
+                break;
+        case PV_970:
+        case PV_970FX:
+        case PV_970MP:
+                ppmu = &ppc970_pmu;
+                break;
+        case PV_POWER5:
+                ppmu = &power5_pmu;
+                break;
+        case PV_POWER5p:
+                ppmu = &power5p_pmu;
+                break;
+        case 0x3e:
+                ppmu = &power6_pmu;
+                break;
+        case 0x3f:
+                ppmu = &power7_pmu;
+                break;
+        }
+        /*
+         * Use FCHV to ignore kernel events if MSR.HV is set.
+         */
+        if (mfmsr() & MSR_HV)
+                freeze_counters_kernel = MMCR0_FCHV;
+        return 0;
+}
+arch_initcall(init_perf_counters);
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
new file mode 100644
index 000000000000..07bd308a5fa7
--- /dev/null
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -0,0 +1,598 @@
+/*
+ * Performance counter support for POWER4 (GP) and POWER4+ (GQ) processors.
+ *
+ * Copyright 2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for POWER4
+ */
+#define PM_PMC_SH       12      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0xf
+#define PM_UNIT_SH      8       /* TTMMUX number and setting - unit select */
+#define PM_UNIT_MSK     0xf
+#define PM_LOWER_SH     6
+#define PM_LOWER_MSK    1
+#define PM_LOWER_MSKS   0x40
+#define PM_BYTE_SH      4       /* Byte number of event bus to use */
+#define PM_BYTE_MSK     3
+#define PM_PMCSEL_MSK   7
+/*
+ * Unit code values
+ */
+#define PM_FPU          1
+#define PM_ISU1         2
+#define PM_IFU          3
+#define PM_IDU0         4
+#define PM_ISU1_ALT     6
+#define PM_ISU2         7
+#define PM_IFU_ALT      8
+#define PM_LSU0         9
+#define PM_LSU1         0xc
+#define PM_GPS          0xf
+/*
+ * Bits in MMCR0 for POWER4
+ */
+#define MMCR0_PMC1SEL_SH        8
+#define MMCR0_PMC2SEL_SH        1
+#define MMCR_PMCSEL_MSK         0x1f
+/*
+ * Bits in MMCR1 for POWER4
+ */
+#define MMCR1_TTM0SEL_SH        62
+#define MMCR1_TTC0SEL_SH        61
+#define MMCR1_TTM1SEL_SH        59
+#define MMCR1_TTC1SEL_SH        58
+#define MMCR1_TTM2SEL_SH        56
+#define MMCR1_TTC2SEL_SH        55
+#define MMCR1_TTM3SEL_SH        53
+#define MMCR1_TTC3SEL_SH        52
+#define MMCR1_TTMSEL_MSK        3
+#define MMCR1_TD_CP_DBG0SEL_SH  50
+#define MMCR1_TD_CP_DBG1SEL_SH  48
+#define MMCR1_TD_CP_DBG2SEL_SH  46
+#define MMCR1_TD_CP_DBG3SEL_SH  44
+#define MMCR1_DEBUG0SEL_SH      43
+#define MMCR1_DEBUG1SEL_SH      42
+#define MMCR1_DEBUG2SEL_SH      41
+#define MMCR1_DEBUG3SEL_SH      40
+#define MMCR1_PMC1_ADDER_SEL_SH 39
+#define MMCR1_PMC2_ADDER_SEL_SH 38
+#define MMCR1_PMC6_ADDER_SEL_SH 37
+#define MMCR1_PMC5_ADDER_SEL_SH 36
+#define MMCR1_PMC8_ADDER_SEL_SH 35
+#define MMCR1_PMC7_ADDER_SEL_SH 34
+#define MMCR1_PMC3_ADDER_SEL_SH 33
+#define MMCR1_PMC4_ADDER_SEL_SH 32
+#define MMCR1_PMC3SEL_SH        27
+#define MMCR1_PMC4SEL_SH        22
+#define MMCR1_PMC5SEL_SH        17
+#define MMCR1_PMC6SEL_SH        12
+#define MMCR1_PMC7SEL_SH        7
+#define MMCR1_PMC8SEL_SH        2       /* note bit 0 is in MMCRA for GP */
+static short mmcr1_adder_bits[8] = {
+        MMCR1_PMC1_ADDER_SEL_SH,
+        MMCR1_PMC2_ADDER_SEL_SH,
+        MMCR1_PMC3_ADDER_SEL_SH,
+        MMCR1_PMC4_ADDER_SEL_SH,
+        MMCR1_PMC5_ADDER_SEL_SH,
+        MMCR1_PMC6_ADDER_SEL_SH,
+        MMCR1_PMC7_ADDER_SEL_SH,
+        MMCR1_PMC8_ADDER_SEL_SH
+};
+/*
+ * Bits in MMCRA
+ */
+#define MMCRA_PMC8SEL0_SH       17      /* PMC8SEL bit 0 for GP */
+/*
+ * Layout of constraint bits:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ *        |[  >[  >[   >|||[  >[  ><  ><  ><  ><  ><><><><><><><><>
+ *        | UC1 UC2 UC3 ||| PS1 PS2 B0  B1  B2  B3 P1P2P3P4P5P6P7P8
+ *        \SMPL         ||\TTC3SEL
+ *                      |\TTC_IFU_SEL
+ *                      \TTM2SEL0
+ *
+ * SMPL - SAMPLE_ENABLE constraint
+ *     56: SAMPLE_ENABLE value 0x0100_0000_0000_0000
+ *
+ * UC1 - unit constraint 1: can't have all three of FPU/ISU1/IDU0|ISU2
+ *     55: UC1 error 0x0080_0000_0000_0000
+ *     54: FPU events needed 0x0040_0000_0000_0000
+ *     53: ISU1 events needed 0x0020_0000_0000_0000
+ *     52: IDU0|ISU2 events needed 0x0010_0000_0000_0000
+ *
+ * UC2 - unit constraint 2: can't have all three of FPU/IFU/LSU0
+ *     51: UC2 error 0x0008_0000_0000_0000
+ *     50: FPU events needed 0x0004_0000_0000_0000
+ *     49: IFU events needed 0x0002_0000_0000_0000
+ *     48: LSU0 events needed 0x0001_0000_0000_0000
+ *
+ * UC3 - unit constraint 3: can't have all four of LSU0/IFU/IDU0|ISU2/ISU1
+ *     47: UC3 error 0x8000_0000_0000
+ *     46: LSU0 events needed 0x4000_0000_0000
+ *     45: IFU events needed 0x2000_0000_0000
+ *     44: IDU0|ISU2 events needed 0x1000_0000_0000
+ *     43: ISU1 events needed 0x0800_0000_0000
+ *
+ * TTM2SEL0
+ *     42: 0 = IDU0 events needed
+ *         1 = ISU2 events needed 0x0400_0000_0000
+ *
+ * TTC_IFU_SEL
+ *     41: 0 = IFU.U events needed
+ *         1 = IFU.L events needed 0x0200_0000_0000
+ *
+ * TTC3SEL
+ *     40: 0 = LSU1.U events needed
+ *         1 = LSU1.L events needed 0x0100_0000_0000
+ *
+ * PS1
+ *     39: PS1 error 0x0080_0000_0000
+ *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
+ *
+ * PS2
+ *     35: PS2 error 0x0008_0000_0000
+ *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
+ *
+ * B0
+ *     28-31: Byte 0 event source 0xf000_0000
+ *         1 = FPU
+ *         2 = ISU1
+ *         3 = IFU
+ *         4 = IDU0
+ *         7 = ISU2
+ *         9 = LSU0
+ *         c = LSU1
+ *         f = GPS
+ *
+ * B1, B2, B3
+ *     24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
+ *
+ * P8
+ *     15: P8 error 0x8000
+ *     14-15: Count of events needing PMC8
+ *
+ * P1..P7
+ *     0-13: Count of events needing PMC1..PMC7
+ *
+ * Note: this doesn't allow events using IFU.U to be combined with events
+ * using IFU.L, though that is feasible (using TTM0 and TTM2).  However
+ * there are no listed events for IFU.L (they are debug events not
+ * verified for performance monitoring) so this shouldn't cause a
+ * problem.
+ */
+static struct unitinfo {
+        u64     value, mask;
+        int     unit;
+        int     lowerbit;
+} p4_unitinfo[16] = {
+        [PM_FPU]  = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 },
+        [PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },
+        [PM_ISU1_ALT] =
+                    { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },
+        [PM_IFU]  = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },
+        [PM_IFU_ALT] =
+                    { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },
+        [PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 },
+        [PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 },
+        [PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 },
+        [PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 },
+        [PM_GPS]  = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 }
+};
+static unsigned char direct_marked_event[8] = {
+        (1<<2) | (1<<3),        /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
+        (1<<3) | (1<<5),        /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
+        (1<<3),                 /* PMC3: PM_MRK_ST_CMPL_INT */
+        (1<<4) | (1<<5),        /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
+        (1<<4) | (1<<5),        /* PMC5: PM_MRK_GRP_TIMEO */
+        (1<<3) | (1<<4) | (1<<5),
+                /* PMC6: PM_MRK_ST_GPS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
+        (1<<4) | (1<<5),        /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
+        (1<<4),                 /* PMC8: PM_MRK_LSU_FIN */
+};
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int p4_marked_instr_event(u64 event)
+{
+        int pmc, psel, unit, byte, bit;
+        unsigned int mask;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = event & PM_PMCSEL_MSK;
+        if (pmc) {
+                if (direct_marked_event[pmc - 1] & (1 << psel))
+                        return 1;
+                if (psel == 0)          /* add events */
+                        bit = (pmc <= 4)? pmc - 1: 8 - pmc;
+                else if (psel == 6)     /* decode events */
+                        bit = 4;
+                else
+                        return 0;
+        } else
+                bit = psel;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        mask = 0;
+        switch (unit) {
+        case PM_LSU1:
+                if (event & PM_LOWER_MSKS)
+                        mask = 1 << 28;         /* byte 7 bit 4 */
+                else
+                        mask = 6 << 24;         /* byte 3 bits 1 and 2 */
+                break;
+        case PM_LSU0:
+                /* byte 3, bit 3; byte 2 bits 0,2,3,4,5; byte 1 */
+                mask = 0x083dff00;
+        }
+        return (mask >> (byte * 8 + bit)) & 1;
+}
+static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, byte, unit, lower, sh;
+        u64 mask = 0, value = 0;
+        int grp = -1;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 8)
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+                grp = ((pmc - 1) >> 1) & 1;
+        }
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        if (unit) {
+                lower = (event >> PM_LOWER_SH) & PM_LOWER_MSK;
+                /*
+                 * Bus events on bytes 0 and 2 can be counted
+                 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
+                 */
+                if (!pmc)
+                        grp = byte & 1;
+                if (!p4_unitinfo[unit].unit)
+                        return -1;
+                mask  |= p4_unitinfo[unit].mask;
+                value |= p4_unitinfo[unit].value;
+                sh = p4_unitinfo[unit].lowerbit;
+                if (sh > 1)
+                        value |= (u64)lower << sh;
+                else if (lower != sh)
+                        return -1;
+                unit = p4_unitinfo[unit].unit;
+                /* Set byte lane select field */
+                mask  |= 0xfULL << (28 - 4 * byte);
+                value |= (u64)unit << (28 - 4 * byte);
+        }
+        if (grp == 0) {
+                /* increment PMC1/2/5/6 field */
+                mask  |= 0x8000000000ull;
+                value |= 0x1000000000ull;
+        } else {
+                /* increment PMC3/4/7/8 field */
+                mask  |= 0x800000000ull;
+                value |= 0x100000000ull;
+        }
+        /* Marked instruction events need sample_enable set */
+        if (p4_marked_instr_event(event)) {
+                mask  |= 1ull << 56;
+                value |= 1ull << 56;
+        }
+        /* PMCSEL=6 decode events on byte 2 need sample_enable clear */
+        if (pmc && (event & PM_PMCSEL_MSK) == 6 && byte == 2)
+                mask  |= 1ull << 56;
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+static unsigned int ppc_inst_cmpl[] = {
+        0x1001, 0x4001, 0x6001, 0x7001, 0x8001
+};
+static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, na;
+        alt[0] = event;
+        na = 1;
+        /* 2 possibilities for PM_GRP_DISP_REJECT */
+        if (event == 0x8003 || event == 0x0224) {
+                alt[1] = event ^ (0x8003 ^ 0x0224);
+                return 2;
+        }
+        /* 2 possibilities for PM_ST_MISS_L1 */
+        if (event == 0x0c13 || event == 0x0c23) {
+                alt[1] = event ^ (0x0c13 ^ 0x0c23);
+                return 2;
+        }
+        /* several possibilities for PM_INST_CMPL */
+        for (i = 0; i < ARRAY_SIZE(ppc_inst_cmpl); ++i) {
+                if (event == ppc_inst_cmpl[i]) {
+                        for (j = 0; j < ARRAY_SIZE(ppc_inst_cmpl); ++j)
+                                if (j != i)
+                                        alt[na++] = ppc_inst_cmpl[j];
+                        break;
+                }
+        }
+        return na;
+}
+static int p4_compute_mmcr(u64 event[], int n_ev,
+                           unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;
+        unsigned int pmc, unit, byte, psel, lower;
+        unsigned int ttm, grp;
+        unsigned int pmc_inuse = 0;
+        unsigned int pmc_grp_use[2];
+        unsigned char busbyte[4];
+        unsigned char unituse[16];
+        unsigned int unitlower = 0;
+        int i;
+        if (n_ev > 8)
+                return -1;
+        /* First pass to count resource use */
+        pmc_grp_use[0] = pmc_grp_use[1] = 0;
+        memset(busbyte, 0, sizeof(busbyte));
+        memset(unituse, 0, sizeof(unituse));
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;
+                        pmc_inuse |= 1 << (pmc - 1);
+                        /* count 1/2/5/6 vs 3/4/7/8 use */
+                        ++pmc_grp_use[((pmc - 1) >> 1) & 1];
+                }
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                lower = (event[i] >> PM_LOWER_SH) & PM_LOWER_MSK;
+                if (unit) {
+                        if (!pmc)
+                                ++pmc_grp_use[byte & 1];
+                        if (unit == 6 || unit == 8)
+                                /* map alt ISU1/IFU codes: 6->2, 8->3 */
+                                unit = (unit >> 1) - 1;
+                        if (busbyte[byte] && busbyte[byte] != unit)
+                                return -1;
+                        busbyte[byte] = unit;
+                        lower <<= unit;
+                        if (unituse[unit] && lower != (unitlower & lower))
+                                return -1;
+                        unituse[unit] = 1;
+                        unitlower |= lower;
+                }
+        }
+        if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
+                return -1;
+        /*
+         * Assign resources and set multiplexer selects.
+         *
+         * Units 1,2,3 are on TTM0, 4,6,7 on TTM1, 8,10 on TTM2.
+         * Each TTMx can only select one unit, but since
+         * units 2 and 6 are both ISU1, and 3 and 8 are both IFU,
+         * we have some choices.
+         */
+        if (unituse[2] & (unituse[1] | (unituse[3] & unituse[9]))) {
+                unituse[6] = 1;         /* Move 2 to 6 */
+                unituse[2] = 0;
+        }
+        if (unituse[3] & (unituse[1] | unituse[2])) {
+                unituse[8] = 1;         /* Move 3 to 8 */
+                unituse[3] = 0;
+                unitlower = (unitlower & ~8) | ((unitlower & 8) << 5);
+        }
+        /* Check only one unit per TTMx */
+        if (unituse[1] + unituse[2] + unituse[3] > 1 ||
+            unituse[4] + unituse[6] + unituse[7] > 1 ||
+            unituse[8] + unituse[9] > 1 ||
+            (unituse[5] | unituse[10] | unituse[11] |
+             unituse[13] | unituse[14]))
+                return -1;
+        /* Set TTMxSEL fields.  Note, units 1-3 => TTM0SEL codes 0-2 */
+        mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH;
+        mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH;
+        mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH;
+        /* Set TTCxSEL fields. */
+        if (unitlower & 0xe)
+                mmcr1 |= 1ull << MMCR1_TTC0SEL_SH;
+        if (unitlower & 0xf0)
+                mmcr1 |= 1ull << MMCR1_TTC1SEL_SH;
+        if (unitlower & 0xf00)
+                mmcr1 |= 1ull << MMCR1_TTC2SEL_SH;
+        if (unitlower & 0x7000)
+                mmcr1 |= 1ull << MMCR1_TTC3SEL_SH;
+        /* Set byte lane select fields. */
+        for (byte = 0; byte < 4; ++byte) {
+                unit = busbyte[byte];
+                if (!unit)
+                        continue;
+                if (unit == 0xf) {
+                        /* special case for GPS */
+                        mmcr1 |= 1ull << (MMCR1_DEBUG0SEL_SH - byte);
+                } else {
+                        if (!unituse[unit])
+                                ttm = unit - 1;         /* 2->1, 3->2 */
+                        else
+                                ttm = unit >> 2;
+                        mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte);
+                }
+        }
+        /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                psel = event[i] & PM_PMCSEL_MSK;
+                if (!pmc) {
+                        /* Bus event or 00xxx direct event (off or cycles) */
+                        if (unit)
+                                psel |= 0x10 | ((byte & 2) << 2);
+                        for (pmc = 0; pmc < 8; ++pmc) {
+                                if (pmc_inuse & (1 << pmc))
+                                        continue;
+                                grp = (pmc >> 1) & 1;
+                                if (unit) {
+                                        if (grp == (byte & 1))
+                                                break;
+                                } else if (pmc_grp_use[grp] < 4) {
+                                        ++pmc_grp_use[grp];
+                                        break;
+                                }
+                        }
+                        pmc_inuse |= 1 << pmc;
+                } else {
+                        /* Direct event */
+                        --pmc;
+                        if (psel == 0 && (byte & 2))
+                                /* add events on higher-numbered bus */
+                                mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
+                        else if (psel == 6 && byte == 3)
+                                /* seem to need to set sample_enable here */
+                                mmcra |= MMCRA_SAMPLE_ENABLE;
+                        psel |= 8;
+                }
+                if (pmc <= 1)
+                        mmcr0 |= psel << (MMCR0_PMC1SEL_SH - 7 * pmc);
+                else
+                        mmcr1 |= psel << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
+                if (pmc == 7)   /* PMC8 */
+                        mmcra |= (psel & 1) << MMCRA_PMC8SEL0_SH;
+                hwc[i] = pmc;
+                if (p4_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+        }
+        if (pmc_inuse & 1)
+                mmcr0 |= MMCR0_PMC1CE;
+        if (pmc_inuse & 0xfe)
+                mmcr0 |= MMCR0_PMCjCE;
+        mmcra |= 0x2000;        /* mark only one IOP per PPC instruction */
+        /* Return MMCRx values */
+        mmcr[0] = mmcr0;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+static void p4_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        /*
+         * Setting the PMCxSEL field to 0 disables PMC x.
+         * (Note that pmc is 0-based here, not 1-based.)
+         */
+        if (pmc <= 1) {
+                mmcr[0] &= ~(0x1fUL << (MMCR0_PMC1SEL_SH - 7 * pmc));
+        } else {
+                mmcr[1] &= ~(0x1fUL << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)));
+                if (pmc == 7)
+                        mmcr[2] &= ~(1UL << MMCRA_PMC8SEL0_SH);
+        }
+}
+static int p4_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 7,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x1001,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x8c10, /* PM_LD_REF_L1 */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x3c10, /* PM_LD_MISS_L1 */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x330,  /* PM_BR_ISSUED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x331,  /* PM_BR_MPRED_CR */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x8c10,         0x3c10  },
+                [C(OP_WRITE)] = {       0x7c10,         0xc13   },
+                [C(OP_PREFETCH)] = {    0xc35,          0       },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0       },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    0,              0       },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0       },
+                [C(OP_WRITE)] = {       0,              0       },
+                [C(OP_PREFETCH)] = {    0xc34,          0       },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x904   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x900   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x330,          0x331   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+};
+struct power_pmu power4_pmu = {
+        .n_counter = 8,
+        .max_alternatives = 5,
+        .add_fields = 0x0000001100005555ull,
+        .test_adder = 0x0011083300000000ull,
+        .compute_mmcr = p4_compute_mmcr,
+        .get_constraint = p4_get_constraint,
+        .get_alternatives = p4_get_alternatives,
+        .disable_pmc = p4_disable_pmc,
+        .n_generic = ARRAY_SIZE(p4_generic_events),
+        .generic_events = p4_generic_events,
+        .cache_events = &power4_cache_events,
+};
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
new file mode 100644
index 000000000000..41e5d2d958d4
--- /dev/null
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -0,0 +1,671 @@
+/*
+ * Performance counter support for POWER5+/++ (not POWER5) processors.
+ *
+ * Copyright 2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
+ */
+#define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0xf
+#define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
+#define PM_UNIT_SH      16      /* TTMMUX number and setting - unit select */
+#define PM_UNIT_MSK     0xf
+#define PM_BYTE_SH      12      /* Byte number of event bus to use */
+#define PM_BYTE_MSK     7
+#define PM_GRS_SH       8       /* Storage subsystem mux select */
+#define PM_GRS_MSK      7
+#define PM_BUSEVENT_MSK 0x80    /* Set if event uses event bus */
+#define PM_PMCSEL_MSK   0x7f
+/* Values in PM_UNIT field */
+#define PM_FPU          0
+#define PM_ISU0         1
+#define PM_IFU          2
+#define PM_ISU1         3
+#define PM_IDU          4
+#define PM_ISU0_ALT     6
+#define PM_GRS          7
+#define PM_LSU0         8
+#define PM_LSU1         0xc
+#define PM_LASTUNIT     0xc
+/*
+ * Bits in MMCR1 for POWER5+
+ */
+#define MMCR1_TTM0SEL_SH        62
+#define MMCR1_TTM1SEL_SH        60
+#define MMCR1_TTM2SEL_SH        58
+#define MMCR1_TTM3SEL_SH        56
+#define MMCR1_TTMSEL_MSK        3
+#define MMCR1_TD_CP_DBG0SEL_SH  54
+#define MMCR1_TD_CP_DBG1SEL_SH  52
+#define MMCR1_TD_CP_DBG2SEL_SH  50
+#define MMCR1_TD_CP_DBG3SEL_SH  48
+#define MMCR1_GRS_L2SEL_SH      46
+#define MMCR1_GRS_L2SEL_MSK     3
+#define MMCR1_GRS_L3SEL_SH      44
+#define MMCR1_GRS_L3SEL_MSK     3
+#define MMCR1_GRS_MCSEL_SH      41
+#define MMCR1_GRS_MCSEL_MSK     7
+#define MMCR1_GRS_FABSEL_SH     39
+#define MMCR1_GRS_FABSEL_MSK    3
+#define MMCR1_PMC1_ADDER_SEL_SH 35
+#define MMCR1_PMC2_ADDER_SEL_SH 34
+#define MMCR1_PMC3_ADDER_SEL_SH 33
+#define MMCR1_PMC4_ADDER_SEL_SH 32
+#define MMCR1_PMC1SEL_SH        25
+#define MMCR1_PMC2SEL_SH        17
+#define MMCR1_PMC3SEL_SH        9
+#define MMCR1_PMC4SEL_SH        1
+#define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
+#define MMCR1_PMCSEL_MSK        0x7f
+/*
+ * Bits in MMCRA
+ */
+/*
+ * Layout of constraint bits:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ *             [  ><><>< ><> <><>[  >  <  ><  ><  ><  ><><><><><><>
+ *             NC  G0G1G2 G3 T0T1 UC    B0  B1  B2  B3 P6P5P4P3P2P1
+ *
+ * NC - number of counters
+ *     51: NC error 0x0008_0000_0000_0000
+ *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
+ *
+ * G0..G3 - GRS mux constraints
+ *     46-47: GRS_L2SEL value
+ *     44-45: GRS_L3SEL value
+ *     41-44: GRS_MCSEL value
+ *     39-40: GRS_FABSEL value
+ *      Note that these match up with their bit positions in MMCR1
+ *
+ * T0 - TTM0 constraint
+ *     36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
+ *
+ * T1 - TTM1 constraint
+ *     34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
+ *
+ * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
+ *     33: UC3 error 0x02_0000_0000
+ *     32: FPU|IFU|ISU1 events needed 0x01_0000_0000
+ *     31: ISU0 events needed 0x01_8000_0000
+ *     30: IDU|GRS events needed 0x00_4000_0000
+ *
+ * B0
+ *     24-27: Byte 0 event source 0x0f00_0000
+ *            Encoding as for the event code
+ *
+ * B1, B2, B3
+ *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
+ *
+ * P6
+ *     11: P6 error 0x800
+ *     10-11: Count of events needing PMC6
+ *
+ * P1..P5
+ *     0-9: Count of events needing PMC1..PMC5
+ */
+static const int grsel_shift[8] = {
+        MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
+        MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
+        MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
+};
+/* Masks and values for using events from the various units */
+static u64 unit_cons[PM_LASTUNIT+1][2] = {
+        [PM_FPU] =   { 0x3200000000ull, 0x0100000000ull },
+        [PM_ISU0] =  { 0x0200000000ull, 0x0080000000ull },
+        [PM_ISU1] =  { 0x3200000000ull, 0x3100000000ull },
+        [PM_IFU] =   { 0x3200000000ull, 0x2100000000ull },
+        [PM_IDU] =   { 0x0e00000000ull, 0x0040000000ull },
+        [PM_GRS] =   { 0x0e00000000ull, 0x0c40000000ull },
+};
+static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, byte, unit, sh;
+        int bit, fmask;
+        u64 mask = 0, value = 0;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 6)
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+                if (pmc >= 5 && !(event == 0x500009 || event == 0x600005))
+                        return -1;
+        }
+        if (event & PM_BUSEVENT_MSK) {
+                unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+                if (unit > PM_LASTUNIT)
+                        return -1;
+                if (unit == PM_ISU0_ALT)
+                        unit = PM_ISU0;
+                mask |= unit_cons[unit][0];
+                value |= unit_cons[unit][1];
+                byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+                if (byte >= 4) {
+                        if (unit != PM_LSU1)
+                                return -1;
+                        /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
+                        ++unit;
+                        byte &= 3;
+                }
+                if (unit == PM_GRS) {
+                        bit = event & 7;
+                        fmask = (bit == 6)? 7: 3;
+                        sh = grsel_shift[bit];
+                        mask |= (u64)fmask << sh;
+                        value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
+                }
+                /* Set byte lane select field */
+                mask  |= 0xfULL << (24 - 4 * byte);
+                value |= (u64)unit << (24 - 4 * byte);
+        }
+        if (pmc < 5) {
+                /* need a counter from PMC1-4 set */
+                mask  |= 0x8000000000000ull;
+                value |= 0x1000000000000ull;
+        }
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+static int power5p_limited_pmc_event(u64 event)
+{
+        int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        return pmc == 5 || pmc == 6;
+}
+#define MAX_ALT 3       /* at most 3 alternatives for any event */
+static const unsigned int event_alternatives[][MAX_ALT] = {
+        { 0x100c0,  0x40001f },                 /* PM_GCT_FULL_CYC */
+        { 0x120e4,  0x400002 },                 /* PM_GRP_DISP_REJECT */
+        { 0x230e2,  0x323087 },                 /* PM_BR_PRED_CR */
+        { 0x230e3,  0x223087, 0x3230a0 },       /* PM_BR_PRED_TA */
+        { 0x410c7,  0x441084 },                 /* PM_THRD_L2MISS_BOTH_CYC */
+        { 0x800c4,  0xc20e0 },                  /* PM_DTLB_MISS */
+        { 0xc50c6,  0xc60e0 },                  /* PM_MRK_DTLB_MISS */
+        { 0x100005, 0x600005 },                 /* PM_RUN_CYC */
+        { 0x100009, 0x200009 },                 /* PM_INST_CMPL */
+        { 0x200015, 0x300015 },                 /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
+        { 0x300009, 0x400009 },                 /* PM_INST_DISP */
+};
+/*
+ * Scan the alternatives table for a match and return the
+ * index into the alternatives table if found, else -1.
+ */
+static int find_alternative(unsigned int event)
+{
+        int i, j;
+        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
+                if (event < event_alternatives[i][0])
+                        break;
+                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
+                        if (event == event_alternatives[i][j])
+                                return i;
+        }
+        return -1;
+}
+static const unsigned char bytedecode_alternatives[4][4] = {
+        /* PMC 1 */     { 0x21, 0x23, 0x25, 0x27 },
+        /* PMC 2 */     { 0x07, 0x17, 0x0e, 0x1e },
+        /* PMC 3 */     { 0x20, 0x22, 0x24, 0x26 },
+        /* PMC 4 */     { 0x07, 0x17, 0x0e, 0x1e }
+};
+/*
+ * Some direct events for decodes of event bus byte 3 have alternative
+ * PMCSEL values on other counters.  This returns the alternative
+ * event code for those that do, or -1 otherwise.  This also handles
+ * alternative PCMSEL values for add events.
+ */
+static s64 find_alternative_bdecode(u64 event)
+{
+        int pmc, altpmc, pp, j;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc == 0 || pmc > 4)
+                return -1;
+        altpmc = 5 - pmc;       /* 1 <-> 4, 2 <-> 3 */
+        pp = event & PM_PMCSEL_MSK;
+        for (j = 0; j < 4; ++j) {
+                if (bytedecode_alternatives[pmc - 1][j] == pp) {
+                        return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
+                                (altpmc << PM_PMC_SH) |
+                                bytedecode_alternatives[altpmc - 1][j];
+                }
+        }
+        /* new decode alternatives for power5+ */
+        if (pmc == 1 && (pp == 0x0d || pp == 0x0e))
+                return event + (2 << PM_PMC_SH) + (0x2e - 0x0d);
+        if (pmc == 3 && (pp == 0x2e || pp == 0x2f))
+                return event - (2 << PM_PMC_SH) - (0x2e - 0x0d);
+        /* alternative add event encodings */
+        if (pp == 0x10 || pp == 0x28)
+                return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) |
+                        (altpmc << PM_PMC_SH);
+        return -1;
+}
+static int power5p_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, nalt = 1;
+        int nlim;
+        s64 ae;
+        alt[0] = event;
+        nalt = 1;
+        nlim = power5p_limited_pmc_event(event);
+        i = find_alternative(event);
+        if (i >= 0) {
+                for (j = 0; j < MAX_ALT; ++j) {
+                        ae = event_alternatives[i][j];
+                        if (ae && ae != event)
+                                alt[nalt++] = ae;
+                        nlim += power5p_limited_pmc_event(ae);
+                }
+        } else {
+                ae = find_alternative_bdecode(event);
+                if (ae > 0)
+                        alt[nalt++] = ae;
+        }
+        if (flags & PPMU_ONLY_COUNT_RUN) {
+                /*
+                 * We're only counting in RUN state,
+                 * so PM_CYC is equivalent to PM_RUN_CYC
+                 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
+                 * This doesn't include alternatives that don't provide
+                 * any extra flexibility in assigning PMCs (e.g.
+                 * 0x100005 for PM_RUN_CYC vs. 0xf for PM_CYC).
+                 * Note that even with these additional alternatives
+                 * we never end up with more than 3 alternatives for any event.
+                 */
+                j = nalt;
+                for (i = 0; i < nalt; ++i) {
+                        switch (alt[i]) {
+                        case 0xf:       /* PM_CYC */
+                                alt[j++] = 0x600005;    /* PM_RUN_CYC */
+                                ++nlim;
+                                break;
+                        case 0x600005:  /* PM_RUN_CYC */
+                                alt[j++] = 0xf;
+                                break;
+                        case 0x100009:  /* PM_INST_CMPL */
+                                alt[j++] = 0x500009;    /* PM_RUN_INST_CMPL */
+                                ++nlim;
+                                break;
+                        case 0x500009:  /* PM_RUN_INST_CMPL */
+                                alt[j++] = 0x100009;    /* PM_INST_CMPL */
+                                alt[j++] = 0x200009;
+                                break;
+                        }
+                }
+                nalt = j;
+        }
+        if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
+                /* remove the limited PMC events */
+                j = 0;
+                for (i = 0; i < nalt; ++i) {
+                        if (!power5p_limited_pmc_event(alt[i])) {
+                                alt[j] = alt[i];
+                                ++j;
+                        }
+                }
+                nalt = j;
+        } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
+                /* remove all but the limited PMC events */
+                j = 0;
+                for (i = 0; i < nalt; ++i) {
+                        if (power5p_limited_pmc_event(alt[i])) {
+                                alt[j] = alt[i];
+                                ++j;
+                        }
+                }
+                nalt = j;
+        }
+        return nalt;
+}
+/*
+ * Map of which direct events on which PMCs are marked instruction events.
+ * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
+ * Bit 0 is set if it is marked for all PMCs.
+ * The 0x80 bit indicates a byte decode PMCSEL value.
+ */
+static unsigned char direct_event_is_marked[0x28] = {
+        0,      /* 00 */
+        0x1f,   /* 01 PM_IOPS_CMPL */
+        0x2,    /* 02 PM_MRK_GRP_DISP */
+        0xe,    /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
+        0,      /* 04 */
+        0x1c,   /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
+        0x80,   /* 06 */
+        0x80,   /* 07 */
+        0, 0, 0,/* 08 - 0a */
+        0x18,   /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
+        0,      /* 0c */
+        0x80,   /* 0d */
+        0x80,   /* 0e */
+        0,      /* 0f */
+        0,      /* 10 */
+        0x14,   /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
+        0,      /* 12 */
+        0x10,   /* 13 PM_MRK_GRP_CMPL */
+        0x1f,   /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
+        0x2,    /* 15 PM_MRK_GRP_ISSUED */
+        0x80,   /* 16 */
+        0x80,   /* 17 */
+        0, 0, 0, 0, 0,
+        0x80,   /* 1d */
+        0x80,   /* 1e */
+        0,      /* 1f */
+        0x80,   /* 20 */
+        0x80,   /* 21 */
+        0x80,   /* 22 */
+        0x80,   /* 23 */
+        0x80,   /* 24 */
+        0x80,   /* 25 */
+        0x80,   /* 26 */
+        0x80,   /* 27 */
+};
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int power5p_marked_instr_event(u64 event)
+{
+        int pmc, psel;
+        int bit, byte, unit;
+        u32 mask;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = event & PM_PMCSEL_MSK;
+        if (pmc >= 5)
+                return 0;
+        bit = -1;
+        if (psel < sizeof(direct_event_is_marked)) {
+                if (direct_event_is_marked[psel] & (1 << pmc))
+                        return 1;
+                if (direct_event_is_marked[psel] & 0x80)
+                        bit = 4;
+                else if (psel == 0x08)
+                        bit = pmc - 1;
+                else if (psel == 0x10)
+                        bit = 4 - pmc;
+                else if (psel == 0x1b && (pmc == 1 || pmc == 3))
+                        bit = 4;
+        } else if ((psel & 0x48) == 0x40) {
+                bit = psel & 7;
+        } else if (psel == 0x28) {
+                bit = pmc - 1;
+        } else if (pmc == 3 && (psel == 0x2e || psel == 0x2f)) {
+                bit = 4;
+        }
+        if (!(event & PM_BUSEVENT_MSK) || bit == -1)
+                return 0;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        if (unit == PM_LSU0) {
+                /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
+                mask = 0x5dff00;
+        } else if (unit == PM_LSU1 && byte >= 4) {
+                byte -= 4;
+                /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */
+                mask = 0x5f11c000;
+        } else
+                return 0;
+        return (mask >> (byte * 8 + bit)) & 1;
+}
+static int power5p_compute_mmcr(u64 event[], int n_ev,
+                                unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr1 = 0;
+        u64 mmcra = 0;
+        unsigned int pmc, unit, byte, psel;
+        unsigned int ttm;
+        int i, isbus, bit, grsel;
+        unsigned int pmc_inuse = 0;
+        unsigned char busbyte[4];
+        unsigned char unituse[16];
+        int ttmuse;
+        if (n_ev > 6)
+                return -1;
+        /* First pass to count resource use */
+        memset(busbyte, 0, sizeof(busbyte));
+        memset(unituse, 0, sizeof(unituse));
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc > 6)
+                                return -1;
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;
+                        pmc_inuse |= 1 << (pmc - 1);
+                }
+                if (event[i] & PM_BUSEVENT_MSK) {
+                        unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                        byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                        if (unit > PM_LASTUNIT)
+                                return -1;
+                        if (unit == PM_ISU0_ALT)
+                                unit = PM_ISU0;
+                        if (byte >= 4) {
+                                if (unit != PM_LSU1)
+                                        return -1;
+                                ++unit;
+                                byte &= 3;
+                        }
+                        if (busbyte[byte] && busbyte[byte] != unit)
+                                return -1;
+                        busbyte[byte] = unit;
+                        unituse[unit] = 1;
+                }
+        }
+        /*
+         * Assign resources and set multiplexer selects.
+         *
+         * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
+         * choice we have to deal with.
+         */
+        if (unituse[PM_ISU0] &
+            (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
+                unituse[PM_ISU0_ALT] = 1;       /* move ISU to TTM1 */
+                unituse[PM_ISU0] = 0;
+        }
+        /* Set TTM[01]SEL fields. */
+        ttmuse = 0;
+        for (i = PM_FPU; i <= PM_ISU1; ++i) {
+                if (!unituse[i])
+                        continue;
+                if (ttmuse++)
+                        return -1;
+                mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
+        }
+        ttmuse = 0;
+        for (; i <= PM_GRS; ++i) {
+                if (!unituse[i])
+                        continue;
+                if (ttmuse++)
+                        return -1;
+                mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
+        }
+        if (ttmuse > 1)
+                return -1;
+        /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
+        for (byte = 0; byte < 4; ++byte) {
+                unit = busbyte[byte];
+                if (!unit)
+                        continue;
+                if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
+                        /* get ISU0 through TTM1 rather than TTM0 */
+                        unit = PM_ISU0_ALT;
+                } else if (unit == PM_LSU1 + 1) {
+                        /* select lower word of LSU1 for this byte */
+                        mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
+                }
+                ttm = unit >> 2;
+                mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
+        }
+        /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                psel = event[i] & PM_PMCSEL_MSK;
+                isbus = event[i] & PM_BUSEVENT_MSK;
+                if (!pmc) {
+                        /* Bus event or any-PMC direct event */
+                        for (pmc = 0; pmc < 4; ++pmc) {
+                                if (!(pmc_inuse & (1 << pmc)))
+                                        break;
+                        }
+                        if (pmc >= 4)
+                                return -1;
+                        pmc_inuse |= 1 << pmc;
+                } else if (pmc <= 4) {
+                        /* Direct event */
+                        --pmc;
+                        if (isbus && (byte & 2) &&
+                            (psel == 8 || psel == 0x10 || psel == 0x28))
+                                /* add events on higher-numbered bus */
+                                mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
+                } else {
+                        /* Instructions or run cycles on PMC5/6 */
+                        --pmc;
+                }
+                if (isbus && unit == PM_GRS) {
+                        bit = psel & 7;
+                        grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
+                        mmcr1 |= (u64)grsel << grsel_shift[bit];
+                }
+                if (power5p_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+                if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1))
+                        /* select alternate byte lane */
+                        psel |= 0x10;
+                if (pmc <= 3)
+                        mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
+                hwc[i] = pmc;
+        }
+        /* Return MMCRx values */
+        mmcr[0] = 0;
+        if (pmc_inuse & 1)
+                mmcr[0] = MMCR0_PMC1CE;
+        if (pmc_inuse & 0x3e)
+                mmcr[0] |= MMCR0_PMCjCE;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        if (pmc <= 3)
+                mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
+}
+static int power5p_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0xf,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x100009,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x1c10a8, /* LD_REF_L1 */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x3c1088, /* LD_MISS_L1 */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x230e4,  /* BR_ISSUED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x230e5,  /* BR_MPRED_CR */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x1c10a8,       0x3c1088        },
+                [C(OP_WRITE)] = {       0x2c10a8,       0xc10c3         },
+                [C(OP_PREFETCH)] = {    0xc70e7,        -1              },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0               },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    0,              0               },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0               },
+                [C(OP_WRITE)] = {       0,              0               },
+                [C(OP_PREFETCH)] = {    0xc50c3,        0               },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0xc20e4,        0x800c4         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x800c0         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x230e4,        0x230e5         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+};
+struct power_pmu power5p_pmu = {
+        .n_counter = 6,
+        .max_alternatives = MAX_ALT,
+        .add_fields = 0x7000000000055ull,
+        .test_adder = 0x3000040000000ull,
+        .compute_mmcr = power5p_compute_mmcr,
+        .get_constraint = power5p_get_constraint,
+        .get_alternatives = power5p_get_alternatives,
+        .disable_pmc = power5p_disable_pmc,
+        .limited_pmc_event = power5p_limited_pmc_event,
+        .flags = PPMU_LIMITED_PMC5_6,
+        .n_generic = ARRAY_SIZE(power5p_generic_events),
+        .generic_events = power5p_generic_events,
+        .cache_events = &power5p_cache_events,
+};
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
new file mode 100644
index 000000000000..05600b66221a
--- /dev/null
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -0,0 +1,611 @@
+/*
+ * Performance counter support for POWER5 (not POWER5++) processors.
+ *
+ * Copyright 2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for POWER5 (not POWER5++)
+ */
+#define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0xf
+#define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
+#define PM_UNIT_SH      16      /* TTMMUX number and setting - unit select */
+#define PM_UNIT_MSK     0xf
+#define PM_BYTE_SH      12      /* Byte number of event bus to use */
+#define PM_BYTE_MSK     7
+#define PM_GRS_SH       8       /* Storage subsystem mux select */
+#define PM_GRS_MSK      7
+#define PM_BUSEVENT_MSK 0x80    /* Set if event uses event bus */
+#define PM_PMCSEL_MSK   0x7f
+/* Values in PM_UNIT field */
+#define PM_FPU          0
+#define PM_ISU0         1
+#define PM_IFU          2
+#define PM_ISU1         3
+#define PM_IDU          4
+#define PM_ISU0_ALT     6
+#define PM_GRS          7
+#define PM_LSU0         8
+#define PM_LSU1         0xc
+#define PM_LASTUNIT     0xc
+/*
+ * Bits in MMCR1 for POWER5
+ */
+#define MMCR1_TTM0SEL_SH        62
+#define MMCR1_TTM1SEL_SH        60
+#define MMCR1_TTM2SEL_SH        58
+#define MMCR1_TTM3SEL_SH        56
+#define MMCR1_TTMSEL_MSK        3
+#define MMCR1_TD_CP_DBG0SEL_SH  54
+#define MMCR1_TD_CP_DBG1SEL_SH  52
+#define MMCR1_TD_CP_DBG2SEL_SH  50
+#define MMCR1_TD_CP_DBG3SEL_SH  48
+#define MMCR1_GRS_L2SEL_SH      46
+#define MMCR1_GRS_L2SEL_MSK     3
+#define MMCR1_GRS_L3SEL_SH      44
+#define MMCR1_GRS_L3SEL_MSK     3
+#define MMCR1_GRS_MCSEL_SH      41
+#define MMCR1_GRS_MCSEL_MSK     7
+#define MMCR1_GRS_FABSEL_SH     39
+#define MMCR1_GRS_FABSEL_MSK    3
+#define MMCR1_PMC1_ADDER_SEL_SH 35
+#define MMCR1_PMC2_ADDER_SEL_SH 34
+#define MMCR1_PMC3_ADDER_SEL_SH 33
+#define MMCR1_PMC4_ADDER_SEL_SH 32
+#define MMCR1_PMC1SEL_SH        25
+#define MMCR1_PMC2SEL_SH        17
+#define MMCR1_PMC3SEL_SH        9
+#define MMCR1_PMC4SEL_SH        1
+#define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
+#define MMCR1_PMCSEL_MSK        0x7f
+/*
+ * Bits in MMCRA
+ */
+/*
+ * Layout of constraint bits:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ *         <><>[  ><><>< ><> [  >[ >[ ><  ><  ><  ><  ><><><><><><>
+ *         T0T1 NC G0G1G2 G3  UC PS1PS2 B0  B1  B2  B3 P6P5P4P3P2P1
+ *
+ * T0 - TTM0 constraint
+ *     54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
+ *
+ * T1 - TTM1 constraint
+ *     52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
+ *
+ * NC - number of counters
+ *     51: NC error 0x0008_0000_0000_0000
+ *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
+ *
+ * G0..G3 - GRS mux constraints
+ *     46-47: GRS_L2SEL value
+ *     44-45: GRS_L3SEL value
+ *     41-44: GRS_MCSEL value
+ *     39-40: GRS_FABSEL value
+ *      Note that these match up with their bit positions in MMCR1
+ *
+ * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
+ *     37: UC3 error 0x20_0000_0000
+ *     36: FPU|IFU|ISU1 events needed 0x10_0000_0000
+ *     35: ISU0 events needed 0x08_0000_0000
+ *     34: IDU|GRS events needed 0x04_0000_0000
+ *
+ * PS1
+ *     33: PS1 error 0x2_0000_0000
+ *     31-32: count of events needing PMC1/2 0x1_8000_0000
+ *
+ * PS2
+ *     30: PS2 error 0x4000_0000
+ *     28-29: count of events needing PMC3/4 0x3000_0000
+ *
+ * B0
+ *     24-27: Byte 0 event source 0x0f00_0000
+ *            Encoding as for the event code
+ *
+ * B1, B2, B3
+ *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
+ *
+ * P1..P6
+ *     0-11: Count of events needing PMC1..PMC6
+ */
+static const int grsel_shift[8] = {
+        MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
+        MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
+        MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
+};
+/* Masks and values for using events from the various units */
+static u64 unit_cons[PM_LASTUNIT+1][2] = {
+        [PM_FPU] =   { 0xc0002000000000ull, 0x00001000000000ull },
+        [PM_ISU0] =  { 0x00002000000000ull, 0x00000800000000ull },
+        [PM_ISU1] =  { 0xc0002000000000ull, 0xc0001000000000ull },
+        [PM_IFU] =   { 0xc0002000000000ull, 0x80001000000000ull },
+        [PM_IDU] =   { 0x30002000000000ull, 0x00000400000000ull },
+        [PM_GRS] =   { 0x30002000000000ull, 0x30000400000000ull },
+};
+static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, byte, unit, sh;
+        int bit, fmask;
+        u64 mask = 0, value = 0;
+        int grp = -1;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 6)
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+                if (pmc <= 4)
+                        grp = (pmc - 1) >> 1;
+                else if (event != 0x500009 && event != 0x600005)
+                        return -1;
+        }
+        if (event & PM_BUSEVENT_MSK) {
+                unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+                if (unit > PM_LASTUNIT)
+                        return -1;
+                if (unit == PM_ISU0_ALT)
+                        unit = PM_ISU0;
+                mask |= unit_cons[unit][0];
+                value |= unit_cons[unit][1];
+                byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+                if (byte >= 4) {
+                        if (unit != PM_LSU1)
+                                return -1;
+                        /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
+                        ++unit;
+                        byte &= 3;
+                }
+                if (unit == PM_GRS) {
+                        bit = event & 7;
+                        fmask = (bit == 6)? 7: 3;
+                        sh = grsel_shift[bit];
+                        mask |= (u64)fmask << sh;
+                        value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
+                }
+                /*
+                 * Bus events on bytes 0 and 2 can be counted
+                 * on PMC1/2; bytes 1 and 3 on PMC3/4.
+                 */
+                if (!pmc)
+                        grp = byte & 1;
+                /* Set byte lane select field */
+                mask  |= 0xfULL << (24 - 4 * byte);
+                value |= (u64)unit << (24 - 4 * byte);
+        }
+        if (grp == 0) {
+                /* increment PMC1/2 field */
+                mask  |= 0x200000000ull;
+                value |= 0x080000000ull;
+        } else if (grp == 1) {
+                /* increment PMC3/4 field */
+                mask  |= 0x40000000ull;
+                value |= 0x10000000ull;
+        }
+        if (pmc < 5) {
+                /* need a counter from PMC1-4 set */
+                mask  |= 0x8000000000000ull;
+                value |= 0x1000000000000ull;
+        }
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+#define MAX_ALT 3       /* at most 3 alternatives for any event */
+static const unsigned int event_alternatives[][MAX_ALT] = {
+        { 0x120e4,  0x400002 },                 /* PM_GRP_DISP_REJECT */
+        { 0x410c7,  0x441084 },                 /* PM_THRD_L2MISS_BOTH_CYC */
+        { 0x100005, 0x600005 },                 /* PM_RUN_CYC */
+        { 0x100009, 0x200009, 0x500009 },       /* PM_INST_CMPL */
+        { 0x300009, 0x400009 },                 /* PM_INST_DISP */
+};
+/*
+ * Scan the alternatives table for a match and return the
+ * index into the alternatives table if found, else -1.
+ */
+static int find_alternative(u64 event)
+{
+        int i, j;
+        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
+                if (event < event_alternatives[i][0])
+                        break;
+                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
+                        if (event == event_alternatives[i][j])
+                                return i;
+        }
+        return -1;
+}
+static const unsigned char bytedecode_alternatives[4][4] = {
+        /* PMC 1 */     { 0x21, 0x23, 0x25, 0x27 },
+        /* PMC 2 */     { 0x07, 0x17, 0x0e, 0x1e },
+        /* PMC 3 */     { 0x20, 0x22, 0x24, 0x26 },
+        /* PMC 4 */     { 0x07, 0x17, 0x0e, 0x1e }
+};
+/*
+ * Some direct events for decodes of event bus byte 3 have alternative
+ * PMCSEL values on other counters.  This returns the alternative
+ * event code for those that do, or -1 otherwise.
+ */
+static s64 find_alternative_bdecode(u64 event)
+{
+        int pmc, altpmc, pp, j;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc == 0 || pmc > 4)
+                return -1;
+        altpmc = 5 - pmc;       /* 1 <-> 4, 2 <-> 3 */
+        pp = event & PM_PMCSEL_MSK;
+        for (j = 0; j < 4; ++j) {
+                if (bytedecode_alternatives[pmc - 1][j] == pp) {
+                        return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
+                                (altpmc << PM_PMC_SH) |
+                                bytedecode_alternatives[altpmc - 1][j];
+                }
+        }
+        return -1;
+}
+static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, nalt = 1;
+        s64 ae;
+        alt[0] = event;
+        nalt = 1;
+        i = find_alternative(event);
+        if (i >= 0) {
+                for (j = 0; j < MAX_ALT; ++j) {
+                        ae = event_alternatives[i][j];
+                        if (ae && ae != event)
+                                alt[nalt++] = ae;
+                }
+        } else {
+                ae = find_alternative_bdecode(event);
+                if (ae > 0)
+                        alt[nalt++] = ae;
+        }
+        return nalt;
+}
+/*
+ * Map of which direct events on which PMCs are marked instruction events.
+ * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
+ * Bit 0 is set if it is marked for all PMCs.
+ * The 0x80 bit indicates a byte decode PMCSEL value.
+ */
+static unsigned char direct_event_is_marked[0x28] = {
+        0,      /* 00 */
+        0x1f,   /* 01 PM_IOPS_CMPL */
+        0x2,    /* 02 PM_MRK_GRP_DISP */
+        0xe,    /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
+        0,      /* 04 */
+        0x1c,   /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
+        0x80,   /* 06 */
+        0x80,   /* 07 */
+        0, 0, 0,/* 08 - 0a */
+        0x18,   /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
+        0,      /* 0c */
+        0x80,   /* 0d */
+        0x80,   /* 0e */
+        0,      /* 0f */
+        0,      /* 10 */
+        0x14,   /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
+        0,      /* 12 */
+        0x10,   /* 13 PM_MRK_GRP_CMPL */
+        0x1f,   /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
+        0x2,    /* 15 PM_MRK_GRP_ISSUED */
+        0x80,   /* 16 */
+        0x80,   /* 17 */
+        0, 0, 0, 0, 0,
+        0x80,   /* 1d */
+        0x80,   /* 1e */
+        0,      /* 1f */
+        0x80,   /* 20 */
+        0x80,   /* 21 */
+        0x80,   /* 22 */
+        0x80,   /* 23 */
+        0x80,   /* 24 */
+        0x80,   /* 25 */
+        0x80,   /* 26 */
+        0x80,   /* 27 */
+};
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int power5_marked_instr_event(u64 event)
+{
+        int pmc, psel;
+        int bit, byte, unit;
+        u32 mask;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = event & PM_PMCSEL_MSK;
+        if (pmc >= 5)
+                return 0;
+        bit = -1;
+        if (psel < sizeof(direct_event_is_marked)) {
+                if (direct_event_is_marked[psel] & (1 << pmc))
+                        return 1;
+                if (direct_event_is_marked[psel] & 0x80)
+                        bit = 4;
+                else if (psel == 0x08)
+                        bit = pmc - 1;
+                else if (psel == 0x10)
+                        bit = 4 - pmc;
+                else if (psel == 0x1b && (pmc == 1 || pmc == 3))
+                        bit = 4;
+        } else if ((psel & 0x58) == 0x40)
+                bit = psel & 7;
+        if (!(event & PM_BUSEVENT_MSK))
+                return 0;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        if (unit == PM_LSU0) {
+                /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
+                mask = 0x5dff00;
+        } else if (unit == PM_LSU1 && byte >= 4) {
+                byte -= 4;
+                /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
+                mask = 0x5f00c0aa;
+        } else
+                return 0;
+        return (mask >> (byte * 8 + bit)) & 1;
+}
+static int power5_compute_mmcr(u64 event[], int n_ev,
+                               unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr1 = 0;
+        u64 mmcra = 0;
+        unsigned int pmc, unit, byte, psel;
+        unsigned int ttm, grp;
+        int i, isbus, bit, grsel;
+        unsigned int pmc_inuse = 0;
+        unsigned int pmc_grp_use[2];
+        unsigned char busbyte[4];
+        unsigned char unituse[16];
+        int ttmuse;
+        if (n_ev > 6)
+                return -1;
+        /* First pass to count resource use */
+        pmc_grp_use[0] = pmc_grp_use[1] = 0;
+        memset(busbyte, 0, sizeof(busbyte));
+        memset(unituse, 0, sizeof(unituse));
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc > 6)
+                                return -1;
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;
+                        pmc_inuse |= 1 << (pmc - 1);
+                        /* count 1/2 vs 3/4 use */
+                        if (pmc <= 4)
+                                ++pmc_grp_use[(pmc - 1) >> 1];
+                }
+                if (event[i] & PM_BUSEVENT_MSK) {
+                        unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                        byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                        if (unit > PM_LASTUNIT)
+                                return -1;
+                        if (unit == PM_ISU0_ALT)
+                                unit = PM_ISU0;
+                        if (byte >= 4) {
+                                if (unit != PM_LSU1)
+                                        return -1;
+                                ++unit;
+                                byte &= 3;
+                        }
+                        if (!pmc)
+                                ++pmc_grp_use[byte & 1];
+                        if (busbyte[byte] && busbyte[byte] != unit)
+                                return -1;
+                        busbyte[byte] = unit;
+                        unituse[unit] = 1;
+                }
+        }
+        if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
+                return -1;
+        /*
+         * Assign resources and set multiplexer selects.
+         *
+         * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
+         * choice we have to deal with.
+         */
+        if (unituse[PM_ISU0] &
+            (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
+                unituse[PM_ISU0_ALT] = 1;       /* move ISU to TTM1 */
+                unituse[PM_ISU0] = 0;
+        }
+        /* Set TTM[01]SEL fields. */
+        ttmuse = 0;
+        for (i = PM_FPU; i <= PM_ISU1; ++i) {
+                if (!unituse[i])
+                        continue;
+                if (ttmuse++)
+                        return -1;
+                mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
+        }
+        ttmuse = 0;
+        for (; i <= PM_GRS; ++i) {
+                if (!unituse[i])
+                        continue;
+                if (ttmuse++)
+                        return -1;
+                mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
+        }
+        if (ttmuse > 1)
+                return -1;
+        /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
+        for (byte = 0; byte < 4; ++byte) {
+                unit = busbyte[byte];
+                if (!unit)
+                        continue;
+                if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
+                        /* get ISU0 through TTM1 rather than TTM0 */
+                        unit = PM_ISU0_ALT;
+                } else if (unit == PM_LSU1 + 1) {
+                        /* select lower word of LSU1 for this byte */
+                        mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
+                }
+                ttm = unit >> 2;
+                mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
+        }
+        /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                psel = event[i] & PM_PMCSEL_MSK;
+                isbus = event[i] & PM_BUSEVENT_MSK;
+                if (!pmc) {
+                        /* Bus event or any-PMC direct event */
+                        for (pmc = 0; pmc < 4; ++pmc) {
+                                if (pmc_inuse & (1 << pmc))
+                                        continue;
+                                grp = (pmc >> 1) & 1;
+                                if (isbus) {
+                                        if (grp == (byte & 1))
+                                                break;
+                                } else if (pmc_grp_use[grp] < 2) {
+                                        ++pmc_grp_use[grp];
+                                        break;
+                                }
+                        }
+                        pmc_inuse |= 1 << pmc;
+                } else if (pmc <= 4) {
+                        /* Direct event */
+                        --pmc;
+                        if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
+                                /* add events on higher-numbered bus */
+                                mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
+                } else {
+                        /* Instructions or run cycles on PMC5/6 */
+                        --pmc;
+                }
+                if (isbus && unit == PM_GRS) {
+                        bit = psel & 7;
+                        grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
+                        mmcr1 |= (u64)grsel << grsel_shift[bit];
+                }
+                if (power5_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+                if (pmc <= 3)
+                        mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
+                hwc[i] = pmc;
+        }
+        /* Return MMCRx values */
+        mmcr[0] = 0;
+        if (pmc_inuse & 1)
+                mmcr[0] = MMCR0_PMC1CE;
+        if (pmc_inuse & 0x3e)
+                mmcr[0] |= MMCR0_PMCjCE;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+static void power5_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        if (pmc <= 3)
+                mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
+}
+static int power5_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0xf,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x100009,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4c1090, /* LD_REF_L1 */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x3c1088, /* LD_MISS_L1 */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x230e4,  /* BR_ISSUED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x230e5,  /* BR_MPRED_CR */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x4c1090,       0x3c1088        },
+                [C(OP_WRITE)] = {       0x3c1090,       0xc10c3         },
+                [C(OP_PREFETCH)] = {    0xc70e7,        0               },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0               },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    0,              0               },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x3c309b        },
+                [C(OP_WRITE)] = {       0,              0               },
+                [C(OP_PREFETCH)] = {    0xc50c3,        0               },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x2c4090,       0x800c4         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x800c0         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x230e4,        0x230e5         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+};
+struct power_pmu power5_pmu = {
+        .n_counter = 6,
+        .max_alternatives = MAX_ALT,
+        .add_fields = 0x7000090000555ull,
+        .test_adder = 0x3000490000000ull,
+        .compute_mmcr = power5_compute_mmcr,
+        .get_constraint = power5_get_constraint,
+        .get_alternatives = power5_get_alternatives,
+        .disable_pmc = power5_disable_pmc,
+        .n_generic = ARRAY_SIZE(power5_generic_events),
+        .generic_events = power5_generic_events,
+        .cache_events = &power5_cache_events,
+};
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
new file mode 100644
index 000000000000..46f74bebcfd9
--- /dev/null
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -0,0 +1,532 @@
+/*
+ * Performance counter support for POWER6 processors.
+ *
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for POWER6
+ */
+#define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0x7
+#define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
+#define PM_UNIT_SH      16      /* Unit event comes (TTMxSEL encoding) */
+#define PM_UNIT_MSK     0xf
+#define PM_UNIT_MSKS    (PM_UNIT_MSK << PM_UNIT_SH)
+#define PM_LLAV         0x8000  /* Load lookahead match value */
+#define PM_LLA          0x4000  /* Load lookahead match enable */
+#define PM_BYTE_SH      12      /* Byte of event bus to use */
+#define PM_BYTE_MSK     3
+#define PM_SUBUNIT_SH   8       /* Subunit event comes from (NEST_SEL enc.) */
+#define PM_SUBUNIT_MSK  7
+#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
+#define PM_PMCSEL_MSK   0xff    /* PMCxSEL value */
+#define PM_BUSEVENT_MSK 0xf3700
+/*
+ * Bits in MMCR1 for POWER6
+ */
+#define MMCR1_TTM0SEL_SH        60
+#define MMCR1_TTMSEL_SH(n)      (MMCR1_TTM0SEL_SH - (n) * 4)
+#define MMCR1_TTMSEL_MSK        0xf
+#define MMCR1_TTMSEL(m, n)      (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
+#define MMCR1_NESTSEL_SH        45
+#define MMCR1_NESTSEL_MSK       0x7
+#define MMCR1_NESTSEL(m)        (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
+#define MMCR1_PMC1_LLA          ((u64)1 << 44)
+#define MMCR1_PMC1_LLA_VALUE    ((u64)1 << 39)
+#define MMCR1_PMC1_ADDR_SEL     ((u64)1 << 35)
+#define MMCR1_PMC1SEL_SH        24
+#define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
+#define MMCR1_PMCSEL_MSK        0xff
+/*
+ * Map of which direct events on which PMCs are marked instruction events.
+ * Indexed by PMCSEL value >> 1.
+ * Bottom 4 bits are a map of which PMCs are interesting,
+ * top 4 bits say what sort of event:
+ *   0 = direct marked event,
+ *   1 = byte decode event,
+ *   4 = add/and event (PMC1 -> bits 0 & 4),
+ *   5 = add/and event (PMC1 -> bits 1 & 5),
+ *   6 = add/and event (PMC1 -> bits 2 & 6),
+ *   7 = add/and event (PMC1 -> bits 3 & 7).
+ */
+static unsigned char direct_event_is_marked[0x60 >> 1] = {
+        0,      /* 00 */
+        0,      /* 02 */
+        0,      /* 04 */
+        0x07,   /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
+        0x04,   /* 08 PM_MRK_DFU_FIN */
+        0x06,   /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
+        0,      /* 0c */
+        0,      /* 0e */
+        0x02,   /* 10 PM_MRK_INST_DISP */
+        0x08,   /* 12 PM_MRK_LSU_DERAT_MISS */
+        0,      /* 14 */
+        0,      /* 16 */
+        0x0c,   /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
+        0x0f,   /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
+        0x01,   /* 1c PM_MRK_INST_ISSUED */
+        0,      /* 1e */
+        0,      /* 20 */
+        0,      /* 22 */
+        0,      /* 24 */
+        0,      /* 26 */
+        0x15,   /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
+        0,      /* 2a */
+        0,      /* 2c */
+        0,      /* 2e */
+        0x4f,   /* 30 */
+        0x7f,   /* 32 */
+        0x4f,   /* 34 */
+        0x5f,   /* 36 */
+        0x6f,   /* 38 */
+        0x4f,   /* 3a */
+        0,      /* 3c */
+        0x08,   /* 3e PM_MRK_INST_TIMEO */
+        0x1f,   /* 40 */
+        0x1f,   /* 42 */
+        0x1f,   /* 44 */
+        0x1f,   /* 46 */
+        0x1f,   /* 48 */
+        0x1f,   /* 4a */
+        0x1f,   /* 4c */
+        0x1f,   /* 4e */
+        0,      /* 50 */
+        0x05,   /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
+        0x1c,   /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
+        0x02,   /* 56 PM_MRK_LD_MISS_L1 */
+        0,      /* 58 */
+        0,      /* 5a */
+        0,      /* 5c */
+        0,      /* 5e */
+};
+/*
+ * Masks showing for each unit which bits are marked events.
+ * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
+ */
+static u32 marked_bus_events[16] = {
+        0x01000000,     /* direct events set 1: byte 3 bit 0 */
+        0x00010000,     /* direct events set 2: byte 2 bit 0 */
+        0, 0, 0, 0,     /* IDU, IFU, nest: nothing */
+        0x00000088,     /* VMX set 1: byte 0 bits 3, 7 */
+        0x000000c0,     /* VMX set 2: byte 0 bits 4-7 */
+        0x04010000,     /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
+        0xff010000u,    /* LSU set 2: byte 2 bit 0, all of byte 3 */
+        0,              /* LSU set 3 */
+        0x00000010,     /* VMX set 3: byte 0 bit 4 */
+        0,              /* BFP set 1 */
+        0x00000022,     /* BFP set 2: byte 0 bits 1, 5 */
+        0, 0
+};
+        
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int power6_marked_instr_event(u64 event)
+{
+        int pmc, psel, ptype;
+        int bit, byte, unit;
+        u32 mask;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = (event & PM_PMCSEL_MSK) >> 1;    /* drop edge/level bit */
+        if (pmc >= 5)
+                return 0;
+        bit = -1;
+        if (psel < sizeof(direct_event_is_marked)) {
+                ptype = direct_event_is_marked[psel];
+                if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
+                        return 0;
+                ptype >>= 4;
+                if (ptype == 0)
+                        return 1;
+                if (ptype == 1)
+                        bit = 0;
+                else
+                        bit = ptype ^ (pmc - 1);
+        } else if ((psel & 0x48) == 0x40)
+                bit = psel & 7;
+        if (!(event & PM_BUSEVENT_MSK) || bit == -1)
+                return 0;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        mask = marked_bus_events[unit];
+        return (mask >> (byte * 8 + bit)) & 1;
+}
+/*
+ * Assign PMC numbers and compute MMCR1 value for a set of events
+ */
+static int p6_compute_mmcr(u64 event[], int n_ev,
+                           unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr1 = 0;
+        u64 mmcra = 0;
+        int i;
+        unsigned int pmc, ev, b, u, s, psel;
+        unsigned int ttmset = 0;
+        unsigned int pmc_inuse = 0;
+        if (n_ev > 6)
+                return -1;
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;      /* collision! */
+                        pmc_inuse |= 1 << (pmc - 1);
+                }
+        }
+        for (i = 0; i < n_ev; ++i) {
+                ev = event[i];
+                pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        --pmc;
+                } else {
+                        /* can go on any PMC; find a free one */
+                        for (pmc = 0; pmc < 4; ++pmc)
+                                if (!(pmc_inuse & (1 << pmc)))
+                                        break;
+                        if (pmc >= 4)
+                                return -1;
+                        pmc_inuse |= 1 << pmc;
+                }
+                hwc[i] = pmc;
+                psel = ev & PM_PMCSEL_MSK;
+                if (ev & PM_BUSEVENT_MSK) {
+                        /* this event uses the event bus */
+                        b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
+                        u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
+                        /* check for conflict on this byte of event bus */
+                        if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
+                                return -1;
+                        mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b);
+                        ttmset |= 1 << b;
+                        if (u == 5) {
+                                /* Nest events have a further mux */
+                                s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
+                                if ((ttmset & 0x10) &&
+                                    MMCR1_NESTSEL(mmcr1) != s)
+                                        return -1;
+                                ttmset |= 0x10;
+                                mmcr1 |= (u64)s << MMCR1_NESTSEL_SH;
+                        }
+                        if (0x30 <= psel && psel <= 0x3d) {
+                                /* these need the PMCx_ADDR_SEL bits */
+                                if (b >= 2)
+                                        mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
+                        }
+                        /* bus select values are different for PMC3/4 */
+                        if (pmc >= 2 && (psel & 0x90) == 0x80)
+                                psel ^= 0x20;
+                }
+                if (ev & PM_LLA) {
+                        mmcr1 |= MMCR1_PMC1_LLA >> pmc;
+                        if (ev & PM_LLAV)
+                                mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
+                }
+                if (power6_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+                if (pmc < 4)
+                        mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc);
+        }
+        mmcr[0] = 0;
+        if (pmc_inuse & 1)
+                mmcr[0] = MMCR0_PMC1CE;
+        if (pmc_inuse & 0xe)
+                mmcr[0] |= MMCR0_PMCjCE;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+/*
+ * Layout of constraint bits:
+ *
+ *      0-1     add field: number of uses of PMC1 (max 1)
+ *      2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
+ *      12-15   add field: number of uses of PMC1-4 (max 4)
+ *      16-19   select field: unit on byte 0 of event bus
+ *      20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
+ *      32-34   select field: nest (subunit) event selector
+ */
+static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, byte, sh, subunit;
+        u64 mask = 0, value = 0;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+        }
+        if (event & PM_BUSEVENT_MSK) {
+                byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+                sh = byte * 4 + (16 - PM_UNIT_SH);
+                mask |= PM_UNIT_MSKS << sh;
+                value |= (u64)(event & PM_UNIT_MSKS) << sh;
+                if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
+                        subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
+                        mask  |= (u64)PM_SUBUNIT_MSK << 32;
+                        value |= (u64)subunit << 32;
+                }
+        }
+        if (pmc <= 4) {
+                mask  |= 0x8000;        /* add field for count of PMC1-4 uses */
+                value |= 0x1000;
+        }
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+static int p6_limited_pmc_event(u64 event)
+{
+        int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        return pmc == 5 || pmc == 6;
+}
+#define MAX_ALT 4       /* at most 4 alternatives for any event */
+static const unsigned int event_alternatives[][MAX_ALT] = {
+        { 0x0130e8, 0x2000f6, 0x3000fc },       /* PM_PTEG_RELOAD_VALID */
+        { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
+        { 0x080088, 0x200054, 0x3000f0 },       /* PM_ST_MISS_L1 */
+        { 0x10000a, 0x2000f4, 0x600005 },       /* PM_RUN_CYC */
+        { 0x10000b, 0x2000f5 },                 /* PM_RUN_COUNT */
+        { 0x10000e, 0x400010 },                 /* PM_PURR */
+        { 0x100010, 0x4000f8 },                 /* PM_FLUSH */
+        { 0x10001a, 0x200010 },                 /* PM_MRK_INST_DISP */
+        { 0x100026, 0x3000f8 },                 /* PM_TB_BIT_TRANS */
+        { 0x100054, 0x2000f0 },                 /* PM_ST_FIN */
+        { 0x100056, 0x2000fc },                 /* PM_L1_ICACHE_MISS */
+        { 0x1000f0, 0x40000a },                 /* PM_INST_IMC_MATCH_CMPL */
+        { 0x1000f8, 0x200008 },                 /* PM_GCT_EMPTY_CYC */
+        { 0x1000fc, 0x400006 },                 /* PM_LSU_DERAT_MISS_CYC */
+        { 0x20000e, 0x400007 },                 /* PM_LSU_DERAT_MISS */
+        { 0x200012, 0x300012 },                 /* PM_INST_DISP */
+        { 0x2000f2, 0x3000f2 },                 /* PM_INST_DISP */
+        { 0x2000f8, 0x300010 },                 /* PM_EXT_INT */
+        { 0x2000fe, 0x300056 },                 /* PM_DATA_FROM_L2MISS */
+        { 0x2d0030, 0x30001a },                 /* PM_MRK_FPU_FIN */
+        { 0x30000a, 0x400018 },                 /* PM_MRK_INST_FIN */
+        { 0x3000f6, 0x40000e },                 /* PM_L1_DCACHE_RELOAD_VALID */
+        { 0x3000fe, 0x400056 },                 /* PM_DATA_FROM_L3MISS */
+};
+/*
+ * This could be made more efficient with a binary search on
+ * a presorted list, if necessary
+ */
+static int find_alternatives_list(u64 event)
+{
+        int i, j;
+        unsigned int alt;
+        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
+                if (event < event_alternatives[i][0])
+                        return -1;
+                for (j = 0; j < MAX_ALT; ++j) {
+                        alt = event_alternatives[i][j];
+                        if (!alt || event < alt)
+                                break;
+                        if (event == alt)
+                                return i;
+                }
+        }
+        return -1;
+}
+static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, nlim;
+        unsigned int psel, pmc;
+        unsigned int nalt = 1;
+        u64 aevent;
+        alt[0] = event;
+        nlim = p6_limited_pmc_event(event);
+        /* check the alternatives table */
+        i = find_alternatives_list(event);
+        if (i >= 0) {
+                /* copy out alternatives from list */
+                for (j = 0; j < MAX_ALT; ++j) {
+                        aevent = event_alternatives[i][j];
+                        if (!aevent)
+                                break;
+                        if (aevent != event)
+                                alt[nalt++] = aevent;
+                        nlim += p6_limited_pmc_event(aevent);
+                }
+        } else {
+                /* Check for alternative ways of computing sum events */
+                /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
+                psel = event & (PM_PMCSEL_MSK & ~1);    /* ignore edge bit */
+                pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc && (psel == 0x32 || psel == 0x34))
+                        alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
+                                ((5 - pmc) << PM_PMC_SH);
+                /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
+                if (pmc && (psel == 0x38 || psel == 0x3a))
+                        alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
+                                ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
+        }
+        if (flags & PPMU_ONLY_COUNT_RUN) {
+                /*
+                 * We're only counting in RUN state,
+                 * so PM_CYC is equivalent to PM_RUN_CYC,
+                 * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
+                 * This doesn't include alternatives that don't provide
+                 * any extra flexibility in assigning PMCs (e.g.
+                 * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
+                 * Note that even with these additional alternatives
+                 * we never end up with more than 4 alternatives for any event.
+                 */
+                j = nalt;
+                for (i = 0; i < nalt; ++i) {
+                        switch (alt[i]) {
+                        case 0x1e:      /* PM_CYC */
+                                alt[j++] = 0x600005;    /* PM_RUN_CYC */
+                                ++nlim;
+                                break;
+                        case 0x10000a:  /* PM_RUN_CYC */
+                                alt[j++] = 0x1e;        /* PM_CYC */
+                                break;
+                        case 2:         /* PM_INST_CMPL */
+                                alt[j++] = 0x500009;    /* PM_RUN_INST_CMPL */
+                                ++nlim;
+                                break;
+                        case 0x500009:  /* PM_RUN_INST_CMPL */
+                                alt[j++] = 2;           /* PM_INST_CMPL */
+                                break;
+                        case 0x10000e:  /* PM_PURR */
+                                alt[j++] = 0x4000f4;    /* PM_RUN_PURR */
+                                break;
+                        case 0x4000f4:  /* PM_RUN_PURR */
+                                alt[j++] = 0x10000e;    /* PM_PURR */
+                                break;
+                        }
+                }
+                nalt = j;
+        }
+        if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
+                /* remove the limited PMC events */
+                j = 0;
+                for (i = 0; i < nalt; ++i) {
+                        if (!p6_limited_pmc_event(alt[i])) {
+                                alt[j] = alt[i];
+                                ++j;
+                        }
+                }
+                nalt = j;
+        } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
+                /* remove all but the limited PMC events */
+                j = 0;
+                for (i = 0; i < nalt; ++i) {
+                        if (p6_limited_pmc_event(alt[i])) {
+                                alt[j] = alt[i];
+                                ++j;
+                        }
+                }
+                nalt = j;
+        }
+        return nalt;
+}
+static void p6_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        /* Set PMCxSEL to 0 to disable PMCx */
+        if (pmc <= 3)
+                mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
+}
+static int power6_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x1e,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 2,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x280030, /* LD_REF_L1 */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x30000c, /* LD_MISS_L1 */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x410a0,  /* BR_PRED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x400052, /* BR_MPRED */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
+ */
+static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x80082,        0x80080         },
+                [C(OP_WRITE)] = {       0x80086,        0x80088         },
+                [C(OP_PREFETCH)] = {    0x810a4,        0               },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x100056        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    0x4008c,        0               },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x150730,       0x250532        },
+                [C(OP_WRITE)] = {       0x250432,       0x150432        },
+                [C(OP_PREFETCH)] = {    0x810a6,        0               },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x20000e        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x420ce         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x430e6,        0x400052        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+};
+struct power_pmu power6_pmu = {
+        .n_counter = 6,
+        .max_alternatives = MAX_ALT,
+        .add_fields = 0x1555,
+        .test_adder = 0x3000,
+        .compute_mmcr = p6_compute_mmcr,
+        .get_constraint = p6_get_constraint,
+        .get_alternatives = p6_get_alternatives,
+        .disable_pmc = p6_disable_pmc,
+        .limited_pmc_event = p6_limited_pmc_event,
+        .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
+        .n_generic = ARRAY_SIZE(power6_generic_events),
+        .generic_events = power6_generic_events,
+        .cache_events = &power6_cache_events,
+};
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
new file mode 100644
index 000000000000..b3f7d1216bae
--- /dev/null
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -0,0 +1,357 @@
+/*
+ * Performance counter support for POWER7 processors.
+ *
+ * Copyright 2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for POWER7
+ */
+#define PM_PMC_SH       16      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0xf
+#define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
+#define PM_UNIT_SH      12      /* TTMMUX number and setting - unit select */
+#define PM_UNIT_MSK     0xf
+#define PM_COMBINE_SH   11      /* Combined event bit */
+#define PM_COMBINE_MSK  1
+#define PM_COMBINE_MSKS 0x800
+#define PM_L2SEL_SH     8       /* L2 event select */
+#define PM_L2SEL_MSK    7
+#define PM_PMCSEL_MSK   0xff
+/*
+ * Bits in MMCR1 for POWER7
+ */
+#define MMCR1_TTM0SEL_SH        60
+#define MMCR1_TTM1SEL_SH        56
+#define MMCR1_TTM2SEL_SH        52
+#define MMCR1_TTM3SEL_SH        48
+#define MMCR1_TTMSEL_MSK        0xf
+#define MMCR1_L2SEL_SH          45
+#define MMCR1_L2SEL_MSK         7
+#define MMCR1_PMC1_COMBINE_SH   35
+#define MMCR1_PMC2_COMBINE_SH   34
+#define MMCR1_PMC3_COMBINE_SH   33
+#define MMCR1_PMC4_COMBINE_SH   32
+#define MMCR1_PMC1SEL_SH        24
+#define MMCR1_PMC2SEL_SH        16
+#define MMCR1_PMC3SEL_SH        8
+#define MMCR1_PMC4SEL_SH        0
+#define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
+#define MMCR1_PMCSEL_MSK        0xff
+/*
+ * Bits in MMCRA
+ */
+/*
+ * Layout of constraint bits:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ *                                                 [  ><><><><><><>
+ *                                                  NC P6P5P4P3P2P1
+ *
+ * NC - number of counters
+ *     15: NC error 0x8000
+ *     12-14: number of events needing PMC1-4 0x7000
+ *
+ * P6
+ *     11: P6 error 0x800
+ *     10-11: Count of events needing PMC6
+ *
+ * P1..P5
+ *     0-9: Count of events needing PMC1..PMC5
+ */
+static int power7_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, sh;
+        u64 mask = 0, value = 0;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 6)
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+                if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
+                        return -1;
+        }
+        if (pmc < 5) {
+                /* need a counter from PMC1-4 set */
+                mask  |= 0x8000;
+                value |= 0x1000;
+        }
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+#define MAX_ALT 2       /* at most 2 alternatives for any event */
+static const unsigned int event_alternatives[][MAX_ALT] = {
+        { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
+        { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
+        { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
+};
+/*
+ * Scan the alternatives table for a match and return the
+ * index into the alternatives table if found, else -1.
+ */
+static int find_alternative(u64 event)
+{
+        int i, j;
+        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
+                if (event < event_alternatives[i][0])
+                        break;
+                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
+                        if (event == event_alternatives[i][j])
+                                return i;
+        }
+        return -1;
+}
+static s64 find_alternative_decode(u64 event)
+{
+        int pmc, psel;
+        /* this only handles the 4x decode events */
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = event & PM_PMCSEL_MSK;
+        if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
+                return event - (1 << PM_PMC_SH) + 8;
+        if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
+                return event + (1 << PM_PMC_SH) - 8;
+        return -1;
+}
+static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, nalt = 1;
+        s64 ae;
+        alt[0] = event;
+        nalt = 1;
+        i = find_alternative(event);
+        if (i >= 0) {
+                for (j = 0; j < MAX_ALT; ++j) {
+                        ae = event_alternatives[i][j];
+                        if (ae && ae != event)
+                                alt[nalt++] = ae;
+                }
+        } else {
+                ae = find_alternative_decode(event);
+                if (ae > 0)
+                        alt[nalt++] = ae;
+        }
+        if (flags & PPMU_ONLY_COUNT_RUN) {
+                /*
+                 * We're only counting in RUN state,
+                 * so PM_CYC is equivalent to PM_RUN_CYC
+                 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
+                 * This doesn't include alternatives that don't provide
+                 * any extra flexibility in assigning PMCs.
+                 */
+                j = nalt;
+                for (i = 0; i < nalt; ++i) {
+                        switch (alt[i]) {
+                        case 0x1e:      /* PM_CYC */
+                                alt[j++] = 0x600f4;     /* PM_RUN_CYC */
+                                break;
+                        case 0x600f4:   /* PM_RUN_CYC */
+                                alt[j++] = 0x1e;
+                                break;
+                        case 0x2:       /* PM_PPC_CMPL */
+                                alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
+                                break;
+                        case 0x500fa:   /* PM_RUN_INST_CMPL */
+                                alt[j++] = 0x2; /* PM_PPC_CMPL */
+                                break;
+                        }
+                }
+                nalt = j;
+        }
+        return nalt;
+}
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int power7_marked_instr_event(u64 event)
+{
+        int pmc, psel;
+        int unit;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        psel = event & PM_PMCSEL_MSK & ~1;      /* trim off edge/level bit */
+        if (pmc >= 5)
+                return 0;
+        switch (psel >> 4) {
+        case 2:
+                return pmc == 2 || pmc == 4;
+        case 3:
+                if (psel == 0x3c)
+                        return pmc == 1;
+                if (psel == 0x3e)
+                        return pmc != 2;
+                return 1;
+        case 4:
+        case 5:
+                return unit == 0xd;
+        case 6:
+                if (psel == 0x64)
+                        return pmc >= 3;
+        case 8:
+                return unit == 0xd;
+        }
+        return 0;
+}
+static int power7_compute_mmcr(u64 event[], int n_ev,
+                               unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr1 = 0;
+        u64 mmcra = 0;
+        unsigned int pmc, unit, combine, l2sel, psel;
+        unsigned int pmc_inuse = 0;
+        int i;
+        /* First pass to count resource use */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc > 6)
+                                return -1;
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;
+                        pmc_inuse |= 1 << (pmc - 1);
+                }
+        }
+        /* Second pass: assign PMCs, set all MMCR1 fields */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
+                l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
+                psel = event[i] & PM_PMCSEL_MSK;
+                if (!pmc) {
+                        /* Bus event or any-PMC direct event */
+                        for (pmc = 0; pmc < 4; ++pmc) {
+                                if (!(pmc_inuse & (1 << pmc)))
+                                        break;
+                        }
+                        if (pmc >= 4)
+                                return -1;
+                        pmc_inuse |= 1 << pmc;
+                } else {
+                        /* Direct or decoded event */
+                        --pmc;
+                }
+                if (pmc <= 3) {
+                        mmcr1 |= (u64) unit << (MMCR1_TTM0SEL_SH - 4 * pmc);
+                        mmcr1 |= (u64) combine << (MMCR1_PMC1_COMBINE_SH - pmc);
+                        mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
+                        if (unit == 6)  /* L2 events */
+                                mmcr1 |= (u64) l2sel << MMCR1_L2SEL_SH;
+                }
+                if (power7_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+                hwc[i] = pmc;
+        }
+        /* Return MMCRx values */
+        mmcr[0] = 0;
+        if (pmc_inuse & 1)
+                mmcr[0] = MMCR0_PMC1CE;
+        if (pmc_inuse & 0x3e)
+                mmcr[0] |= MMCR0_PMCjCE;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+static void power7_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        if (pmc <= 3)
+                mmcr[1] &= ~(0xffULL << MMCR1_PMCSEL_SH(pmc));
+}
+static int power7_generic_events[] = {
+        [PERF_COUNT_CPU_CYCLES] = 0x1e,
+        [PERF_COUNT_INSTRUCTIONS] = 2,
+        [PERF_COUNT_CACHE_REFERENCES] = 0xc880,         /* LD_REF_L1_LSU */
+        [PERF_COUNT_CACHE_MISSES] = 0x400f0,            /* LD_MISS_L1 */
+        [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x10068,     /* BRU_FIN */
+        [PERF_COUNT_BRANCH_MISSES] = 0x400f6,           /* BR_MPRED */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x400f0,        0xc880  },
+                [C(OP_WRITE)] = {       0,              0x300f0 },
+                [C(OP_PREFETCH)] = {    0xd8b8,         0       },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x200fc },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    0x408a,         0       },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x6080,         0x6084  },
+                [C(OP_WRITE)] = {       0x6082,         0x6086  },
+                [C(OP_PREFETCH)] = {    0,              0       },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x300fc },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x400fc },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x10068,        0x400f6 },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+};
+struct power_pmu power7_pmu = {
+        .n_counter = 6,
+        .max_alternatives = MAX_ALT + 1,
+        .add_fields = 0x1555ull,
+        .test_adder = 0x3000ull,
+        .compute_mmcr = power7_compute_mmcr,
+        .get_constraint = power7_get_constraint,
+        .get_alternatives = power7_get_alternatives,
+        .disable_pmc = power7_disable_pmc,
+        .n_generic = ARRAY_SIZE(power7_generic_events),
+        .generic_events = power7_generic_events,
+        .cache_events = &power7_cache_events,
+};
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
new file mode 100644
index 000000000000..ba0a357a89f4
--- /dev/null
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -0,0 +1,482 @@
+/*
+ * Performance counter support for PPC970-family processors.
+ *
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/string.h>
+#include <linux/perf_counter.h>
+#include <asm/reg.h>
+/*
+ * Bits in event code for PPC970
+ */
+#define PM_PMC_SH       12      /* PMC number (1-based) for direct events */
+#define PM_PMC_MSK      0xf
+#define PM_UNIT_SH      8       /* TTMMUX number and setting - unit select */
+#define PM_UNIT_MSK     0xf
+#define PM_SPCSEL_SH    6
+#define PM_SPCSEL_MSK   3
+#define PM_BYTE_SH      4       /* Byte number of event bus to use */
+#define PM_BYTE_MSK     3
+#define PM_PMCSEL_MSK   0xf
+/* Values in PM_UNIT field */
+#define PM_NONE         0
+#define PM_FPU          1
+#define PM_VPU          2
+#define PM_ISU          3
+#define PM_IFU          4
+#define PM_IDU          5
+#define PM_STS          6
+#define PM_LSU0         7
+#define PM_LSU1U        8
+#define PM_LSU1L        9
+#define PM_LASTUNIT     9
+/*
+ * Bits in MMCR0 for PPC970
+ */
+#define MMCR0_PMC1SEL_SH        8
+#define MMCR0_PMC2SEL_SH        1
+#define MMCR_PMCSEL_MSK         0x1f
+/*
+ * Bits in MMCR1 for PPC970
+ */
+#define MMCR1_TTM0SEL_SH        62
+#define MMCR1_TTM1SEL_SH        59
+#define MMCR1_TTM3SEL_SH        53
+#define MMCR1_TTMSEL_MSK        3
+#define MMCR1_TD_CP_DBG0SEL_SH  50
+#define MMCR1_TD_CP_DBG1SEL_SH  48
+#define MMCR1_TD_CP_DBG2SEL_SH  46
+#define MMCR1_TD_CP_DBG3SEL_SH  44
+#define MMCR1_PMC1_ADDER_SEL_SH 39
+#define MMCR1_PMC2_ADDER_SEL_SH 38
+#define MMCR1_PMC6_ADDER_SEL_SH 37
+#define MMCR1_PMC5_ADDER_SEL_SH 36
+#define MMCR1_PMC8_ADDER_SEL_SH 35
+#define MMCR1_PMC7_ADDER_SEL_SH 34
+#define MMCR1_PMC3_ADDER_SEL_SH 33
+#define MMCR1_PMC4_ADDER_SEL_SH 32
+#define MMCR1_PMC3SEL_SH        27
+#define MMCR1_PMC4SEL_SH        22
+#define MMCR1_PMC5SEL_SH        17
+#define MMCR1_PMC6SEL_SH        12
+#define MMCR1_PMC7SEL_SH        7
+#define MMCR1_PMC8SEL_SH        2
+static short mmcr1_adder_bits[8] = {
+        MMCR1_PMC1_ADDER_SEL_SH,
+        MMCR1_PMC2_ADDER_SEL_SH,
+        MMCR1_PMC3_ADDER_SEL_SH,
+        MMCR1_PMC4_ADDER_SEL_SH,
+        MMCR1_PMC5_ADDER_SEL_SH,
+        MMCR1_PMC6_ADDER_SEL_SH,
+        MMCR1_PMC7_ADDER_SEL_SH,
+        MMCR1_PMC8_ADDER_SEL_SH
+};
+/*
+ * Bits in MMCRA
+ */
+/*
+ * Layout of constraint bits:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ *               <><><>[  >[  >[  ><  ><  ><  ><  ><><><><><><><><>
+ *               SPT0T1 UC  PS1 PS2 B0  B1  B2  B3 P1P2P3P4P5P6P7P8
+ *
+ * SP - SPCSEL constraint
+ *     48-49: SPCSEL value 0x3_0000_0000_0000
+ *
+ * T0 - TTM0 constraint
+ *     46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
+ *
+ * T1 - TTM1 constraint
+ *     44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
+ *
+ * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
+ *     43: UC3 error 0x0800_0000_0000
+ *     42: FPU|IFU|VPU events needed 0x0400_0000_0000
+ *     41: ISU events needed 0x0200_0000_0000
+ *     40: IDU|STS events needed 0x0100_0000_0000
+ *
+ * PS1
+ *     39: PS1 error 0x0080_0000_0000
+ *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
+ *
+ * PS2
+ *     35: PS2 error 0x0008_0000_0000
+ *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
+ *
+ * B0
+ *     28-31: Byte 0 event source 0xf000_0000
+ *            Encoding as for the event code
+ *
+ * B1, B2, B3
+ *     24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
+ *
+ * P1
+ *     15: P1 error 0x8000
+ *     14-15: Count of events needing PMC1
+ *
+ * P2..P8
+ *     0-13: Count of events needing PMC2..PMC8
+ */
+static unsigned char direct_marked_event[8] = {
+        (1<<2) | (1<<3),        /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
+        (1<<3) | (1<<5),        /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
+        (1<<3) | (1<<5),        /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
+        (1<<4) | (1<<5),        /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
+        (1<<4) | (1<<5),        /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
+        (1<<3) | (1<<4) | (1<<5),
+                /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
+        (1<<4) | (1<<5),        /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
+        (1<<4)                  /* PMC8: PM_MRK_LSU_FIN */
+};
+/*
+ * Returns 1 if event counts things relating to marked instructions
+ * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
+ */
+static int p970_marked_instr_event(u64 event)
+{
+        int pmc, psel, unit, byte, bit;
+        unsigned int mask;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        psel = event & PM_PMCSEL_MSK;
+        if (pmc) {
+                if (direct_marked_event[pmc - 1] & (1 << psel))
+                        return 1;
+                if (psel == 0)          /* add events */
+                        bit = (pmc <= 4)? pmc - 1: 8 - pmc;
+                else if (psel == 7 || psel == 13)       /* decode events */
+                        bit = 4;
+                else
+                        return 0;
+        } else
+                bit = psel;
+        byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        mask = 0;
+        switch (unit) {
+        case PM_VPU:
+                mask = 0x4c;            /* byte 0 bits 2,3,6 */
+        case PM_LSU0:
+                /* byte 2 bits 0,2,3,4,6; all of byte 1 */
+                mask = 0x085dff00;
+        case PM_LSU1L:
+                mask = 0x50 << 24;      /* byte 3 bits 4,6 */
+                break;
+        }
+        return (mask >> (byte * 8 + bit)) & 1;
+}
+/* Masks and values for using events from the various units */
+static u64 unit_cons[PM_LASTUNIT+1][2] = {
+        [PM_FPU] =   { 0xc80000000000ull, 0x040000000000ull },
+        [PM_VPU] =   { 0xc80000000000ull, 0xc40000000000ull },
+        [PM_ISU] =   { 0x080000000000ull, 0x020000000000ull },
+        [PM_IFU] =   { 0xc80000000000ull, 0x840000000000ull },
+        [PM_IDU] =   { 0x380000000000ull, 0x010000000000ull },
+        [PM_STS] =   { 0x380000000000ull, 0x310000000000ull },
+};
+static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
+{
+        int pmc, byte, unit, sh, spcsel;
+        u64 mask = 0, value = 0;
+        int grp = -1;
+        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
+        if (pmc) {
+                if (pmc > 8)
+                        return -1;
+                sh = (pmc - 1) * 2;
+                mask |= 2 << sh;
+                value |= 1 << sh;
+                grp = ((pmc - 1) >> 1) & 1;
+        }
+        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
+        if (unit) {
+                if (unit > PM_LASTUNIT)
+                        return -1;
+                mask |= unit_cons[unit][0];
+                value |= unit_cons[unit][1];
+                byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
+                /*
+                 * Bus events on bytes 0 and 2 can be counted
+                 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
+                 */
+                if (!pmc)
+                        grp = byte & 1;
+                /* Set byte lane select field */
+                mask  |= 0xfULL << (28 - 4 * byte);
+                value |= (u64)unit << (28 - 4 * byte);
+        }
+        if (grp == 0) {
+                /* increment PMC1/2/5/6 field */
+                mask  |= 0x8000000000ull;
+                value |= 0x1000000000ull;
+        } else if (grp == 1) {
+                /* increment PMC3/4/7/8 field */
+                mask  |= 0x800000000ull;
+                value |= 0x100000000ull;
+        }
+        spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
+        if (spcsel) {
+                mask  |= 3ull << 48;
+                value |= (u64)spcsel << 48;
+        }
+        *maskp = mask;
+        *valp = value;
+        return 0;
+}
+static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        alt[0] = event;
+        /* 2 alternatives for LSU empty */
+        if (event == 0x2002 || event == 0x3002) {
+                alt[1] = event ^ 0x1000;
+                return 2;
+        }
+                
+        return 1;
+}
+static int p970_compute_mmcr(u64 event[], int n_ev,
+                             unsigned int hwc[], u64 mmcr[])
+{
+        u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;
+        unsigned int pmc, unit, byte, psel;
+        unsigned int ttm, grp;
+        unsigned int pmc_inuse = 0;
+        unsigned int pmc_grp_use[2];
+        unsigned char busbyte[4];
+        unsigned char unituse[16];
+        unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
+        unsigned char ttmuse[2];
+        unsigned char pmcsel[8];
+        int i;
+        int spcsel;
+        if (n_ev > 8)
+                return -1;
+        /* First pass to count resource use */
+        pmc_grp_use[0] = pmc_grp_use[1] = 0;
+        memset(busbyte, 0, sizeof(busbyte));
+        memset(unituse, 0, sizeof(unituse));
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                if (pmc) {
+                        if (pmc_inuse & (1 << (pmc - 1)))
+                                return -1;
+                        pmc_inuse |= 1 << (pmc - 1);
+                        /* count 1/2/5/6 vs 3/4/7/8 use */
+                        ++pmc_grp_use[((pmc - 1) >> 1) & 1];
+                }
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                if (unit) {
+                        if (unit > PM_LASTUNIT)
+                                return -1;
+                        if (!pmc)
+                                ++pmc_grp_use[byte & 1];
+                        if (busbyte[byte] && busbyte[byte] != unit)
+                                return -1;
+                        busbyte[byte] = unit;
+                        unituse[unit] = 1;
+                }
+        }
+        if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
+                return -1;
+        /*
+         * Assign resources and set multiplexer selects.
+         *
+         * PM_ISU can go either on TTM0 or TTM1, but that's the only
+         * choice we have to deal with.
+         */
+        if (unituse[PM_ISU] &
+            (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
+                unitmap[PM_ISU] = 2 | 4;        /* move ISU to TTM1 */
+        /* Set TTM[01]SEL fields. */
+        ttmuse[0] = ttmuse[1] = 0;
+        for (i = PM_FPU; i <= PM_STS; ++i) {
+                if (!unituse[i])
+                        continue;
+                ttm = unitmap[i];
+                ++ttmuse[(ttm >> 2) & 1];
+                mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH;
+        }
+        /* Check only one unit per TTMx */
+        if (ttmuse[0] > 1 || ttmuse[1] > 1)
+                return -1;
+        /* Set byte lane select fields and TTM3SEL. */
+        for (byte = 0; byte < 4; ++byte) {
+                unit = busbyte[byte];
+                if (!unit)
+                        continue;
+                if (unit <= PM_STS)
+                        ttm = (unitmap[unit] >> 2) & 1;
+                else if (unit == PM_LSU0)
+                        ttm = 2;
+                else {
+                        ttm = 3;
+                        if (unit == PM_LSU1L && byte >= 2)
+                                mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
+                }
+                mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
+        }
+        /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
+        memset(pmcsel, 0x8, sizeof(pmcsel));    /* 8 means don't count */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
+                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
+                byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
+                psel = event[i] & PM_PMCSEL_MSK;
+                if (!pmc) {
+                        /* Bus event or any-PMC direct event */
+                        if (unit)
+                                psel |= 0x10 | ((byte & 2) << 2);
+                        else
+                                psel |= 8;
+                        for (pmc = 0; pmc < 8; ++pmc) {
+                                if (pmc_inuse & (1 << pmc))
+                                        continue;
+                                grp = (pmc >> 1) & 1;
+                                if (unit) {
+                                        if (grp == (byte & 1))
+                                                break;
+                                } else if (pmc_grp_use[grp] < 4) {
+                                        ++pmc_grp_use[grp];
+                                        break;
+                                }
+                        }
+                        pmc_inuse |= 1 << pmc;
+                } else {
+                        /* Direct event */
+                        --pmc;
+                        if (psel == 0 && (byte & 2))
+                                /* add events on higher-numbered bus */
+                                mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
+                }
+                pmcsel[pmc] = psel;
+                hwc[i] = pmc;
+                spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
+                mmcr1 |= spcsel;
+                if (p970_marked_instr_event(event[i]))
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+        }
+        for (pmc = 0; pmc < 2; ++pmc)
+                mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
+        for (; pmc < 8; ++pmc)
+                mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
+        if (pmc_inuse & 1)
+                mmcr0 |= MMCR0_PMC1CE;
+        if (pmc_inuse & 0xfe)
+                mmcr0 |= MMCR0_PMCjCE;
+        mmcra |= 0x2000;        /* mark only one IOP per PPC instruction */
+        /* Return MMCRx values */
+        mmcr[0] = mmcr0;
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+        return 0;
+}
+static void p970_disable_pmc(unsigned int pmc, u64 mmcr[])
+{
+        int shift, i;
+        if (pmc <= 1) {
+                shift = MMCR0_PMC1SEL_SH - 7 * pmc;
+                i = 0;
+        } else {
+                shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
+                i = 1;
+        }
+        /*
+         * Setting the PMCxSEL field to 0x08 disables PMC x.
+         */
+        mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
+}
+static int ppc970_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 7,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 1,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x8810, /* PM_LD_REF_L1 */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x3810, /* PM_LD_MISS_L1 */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x431,  /* PM_BR_ISSUED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x327,  /* PM_GRP_BR_MPRED */
+};
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x8810,         0x3810  },
+                [C(OP_WRITE)] = {       0x7810,         0x813   },
+                [C(OP_PREFETCH)] = {    0x731,          0       },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0       },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    0,              0       },
+        },
+        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0       },
+                [C(OP_WRITE)] = {       0,              0       },
+                [C(OP_PREFETCH)] = {    0x733,          0       },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x704   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x700   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x431,          0x327   },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
+};
+struct power_pmu ppc970_pmu = {
+        .n_counter = 8,
+        .max_alternatives = 2,
+        .add_fields = 0x001100005555ull,
+        .test_adder = 0x013300000000ull,
+        .compute_mmcr = p970_compute_mmcr,
+        .get_constraint = p970_get_constraint,
+        .get_alternatives = p970_get_alternatives,
+        .disable_pmc = p970_disable_pmc,
+        .n_generic = ARRAY_SIZE(ppc970_generic_events),
+        .generic_events = ppc970_generic_events,
+        .cache_events = &ppc970_cache_events,
+};
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 9057335fdc61..2cf915e51e7e 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -41,6 +41,12 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
        return !!(v->arch.pending_exceptions);
 }
+int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
+{
+        /* do real check here */
+        return 1;
+}
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
 {
        return !(v->arch.msr & MSR_WE);
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 76993941cac9..5beffc8f481e 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -29,6 +29,7 @@
 #include <linux/module.h>
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
+#include <linux/perf_counter.h>
 #include <asm/firmware.h>
 #include <asm/page.h>
@@ -170,6 +171,8 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
                die("Weird page fault", regs, SIGSEGV);
        }
+        perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
        /* When running in the kernel we expect faults to occur only to
         * addresses in user space.  All other faults represent errors in the
         * kernel and should generate an OOPS.  Unfortunately, in the case of an
@@ -309,6 +312,8 @@ good_area:
        }
        if (ret & VM_FAULT_MAJOR) {
                current->maj_flt++;
+                perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                                     regs, address);
 #ifdef CONFIG_PPC_SMLPAR
                if (firmware_has_feature(FW_FEATURE_CMO)) {
                        preempt_disable();
@@ -316,8 +321,11 @@ good_area:
                        preempt_enable();
                }
 #endif
-        } else
+        } else {
                current->min_flt++;
+                perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                                     regs, address);
+        }
        up_read(&mm->mmap_sem);
        return 0;
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 25f8a9c2ba1a..cca6b4fc719a 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -1,6 +1,7 @@
 config PPC64
        bool "64-bit kernel"
        default n
+        select HAVE_PERF_COUNTERS
        help
          This option selects whether a 32-bit or a 64-bit kernel
          will be built.
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 80b513449f4c..be3581a8c294 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -333,7 +333,7 @@ static void xics_eoi_lpar(unsigned int virq)
        lpar_xirr_info_set((0xff << 24) | irq);
 }
-static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
+static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
 {
        unsigned int irq;
        int status;
@@ -342,14 +342,14 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
        irq = (unsigned int)irq_map[virq].hwirq;
        if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
-                return;
+                return -1;
        status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
        if (status) {
                printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
                        __func__, irq, status);
-                return;
+                return -1;
        }
        /*
@@ -363,7 +363,7 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
                printk(KERN_WARNING
                        "%s: No online cpus in the mask %s for irq %d\n",
                        __func__, cpulist, virq);
-                return;
+                return -1;
        }
        status = rtas_call(ibm_set_xive, 3, 1, NULL,
@@ -372,8 +372,10 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
        if (status) {
                printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
                        __func__, irq, status);
-                return;
+                return -1;
        }
+        return 0;
 }
 static struct irq_chip xics_pic_direct = {
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index 9e105cbc5e5f..a4779912a5ca 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -250,7 +250,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id)
        set_capacity(bank->disk, bank->size >> AXON_RAM_SECTOR_SHIFT);
        blk_queue_make_request(bank->disk->queue, axon_ram_make_request);
-        blk_queue_hardsect_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE);
+        blk_queue_logical_block_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE);
        add_disk(bank->disk);
        bank->irq_id = irq_of_parse_and_map(device->node, 0);
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index bbee441ae867..9c3af5045495 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -807,7 +807,7 @@ static void mpic_end_ipi(unsigned int irq)
 #endif /* CONFIG_SMP */
-void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
+int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 {
        struct mpic *mpic = mpic_from_irq(irq);
        unsigned int src = mpic_irq_to_hw(irq);
@@ -824,6 +824,8 @@ void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
                mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
                               mpic_physmask(cpus_addr(tmp)[0]));
        }
+        return 0;
 }
 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index 3cef2af10f42..eff433c322a0 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -36,6 +36,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
 extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
 extern void mpic_set_vector(unsigned int virq, unsigned int vector);
-extern void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
+extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
 #endif /* _POWERPC_SYSDEV_MPIC_H */
author	Benjamin Herrenschmidt <benh@kernel.crashing.org>	2009-06-12 02:53:38 -0400
committer	Benjamin Herrenschmidt <benh@kernel.crashing.org>	2009-06-12 02:53:38 -0400
commit	bc47ab0241c7c86da4f5e5f82fbca7d45387c18d (patch)
tree	b9c33ae8b6de43e44cc5fcbaa3e4a15f18a5ed42 /arch/powerpc
parent	37f9ef553bed630957e025504cdcbc76f5de49d5 (diff)
parent	8ebf975608aaebd7feb33d77f07ba21a6380e086 (diff)