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authorAndy Fleming <afleming@freescale.com>2006-08-18 19:03:08 -0400
committerPaul Mackerras <paulus@samba.org>2006-08-23 01:51:18 -0400
commit4c86cd9c59428a40233fb707f5de18caa5ab5cb7 (patch)
treeb0ad76cbfdb48041e2f393cc2886c0c79e83ccbc /arch/powerpc
parent9e8a9bc2d2c3ac3b8542cc5c2544248df6f3f1c5 (diff)
[POWERPC] Fix interrupts on 8540 ADS board
* Fixed 8540 ADS support for the new irq layer * Fixed 8540 ADS support for mapping PCI interrupts * Updated 8540 ADS to use device tree for interrupt assignment and sense values Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c162
1 files changed, 55 insertions, 107 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 06a497676c99..9d2acfbbeccd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -37,79 +37,7 @@ unsigned long isa_io_base = 0;
37unsigned long isa_mem_base = 0; 37unsigned long isa_mem_base = 0;
38#endif 38#endif
39 39
40/*
41 * Internal interrupts are all Level Sensitive, and Positive Polarity
42 *
43 * Note: Likely, this table and the following function should be
44 * obtained and derived from the OF Device Tree.
45 */
46static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
47 MPC85XX_INTERNAL_IRQ_SENSES,
48 0x0, /* External 0: */
49#if defined(CONFIG_PCI)
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
54#else
55 0x0, /* External 1: */
56 0x0, /* External 2: */
57 0x0, /* External 3: */
58 0x0, /* External 4: */
59#endif
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
61 0x0, /* External 6: */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
63 0x0, /* External 8: */
64 0x0, /* External 9: */
65 0x0, /* External 10: */
66 0x0, /* External 11: */
67};
68
69#ifdef CONFIG_PCI 40#ifdef CONFIG_PCI
70/*
71 * interrupt routing
72 */
73
74int
75mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
76{
77 static char pci_irq_table[][4] =
78 /*
79 * This is little evil, but works around the fact
80 * that revA boards have IDSEL starting at 18
81 * and others boards (older) start at 12
82 *
83 * PCI IDSEL/INTPIN->INTLINE
84 * A B C D
85 */
86 {
87 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
88 {PIRQD, PIRQA, PIRQB, PIRQC},
89 {PIRQC, PIRQD, PIRQA, PIRQB},
90 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
91 {0, 0, 0, 0}, /* -- */
92 {0, 0, 0, 0}, /* -- */
93 {0, 0, 0, 0}, /* -- */
94 {0, 0, 0, 0}, /* -- */
95 {0, 0, 0, 0}, /* -- */
96 {0, 0, 0, 0}, /* -- */
97 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
98 {PIRQD, PIRQA, PIRQB, PIRQC},
99 {PIRQC, PIRQD, PIRQA, PIRQB},
100 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
101 {0, 0, 0, 0}, /* -- */
102 {0, 0, 0, 0}, /* -- */
103 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
104 {PIRQD, PIRQA, PIRQB, PIRQC},
105 {PIRQC, PIRQD, PIRQA, PIRQB},
106 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
107 };
108
109 const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111}
112
113int 41int
114mpc85xx_exclude_device(u_char bus, u_char devfn) 42mpc85xx_exclude_device(u_char bus, u_char devfn)
115{ 43{
@@ -119,44 +47,63 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
119 return PCIBIOS_SUCCESSFUL; 47 return PCIBIOS_SUCCESSFUL;
120} 48}
121 49
50void __init
51mpc85xx_pcibios_fixup(void)
52{
53 struct pci_dev *dev = NULL;
54
55 for_each_pci_dev(dev)
56 pci_read_irq_line(dev);
57}
122#endif /* CONFIG_PCI */ 58#endif /* CONFIG_PCI */
123 59
124 60
125void __init mpc85xx_ads_pic_init(void) 61void __init mpc85xx_ads_pic_init(void)
126{ 62{
127 struct mpic *mpic1; 63 struct mpic *mpic;
128 phys_addr_t OpenPIC_PAddr; 64 struct resource r;
129 65 struct device_node *np = NULL;
130 /* Determine the Physical Address of the OpenPIC regs */ 66
131 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; 67 np = of_find_node_by_type(np, "open-pic");
132 68
133 mpic1 = mpic_alloc(OpenPIC_PAddr, 69 if (np == NULL) {
134 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 70 printk(KERN_ERR "Could not find open-pic node\n");
135 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, 71 return;
136 mpc85xx_ads_openpic_initsenses, 72 }
137 sizeof(mpc85xx_ads_openpic_initsenses), 73
138 " OpenPIC "); 74 if(of_address_to_resource(np, 0, &r)) {
139 BUG_ON(mpic1 == NULL); 75 printk(KERN_ERR "Could not map mpic register space\n");
140 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); 76 of_node_put(np);
141 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); 77 return;
142 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); 78 }
143 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); 79
144 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); 80 mpic = mpic_alloc(np, r.start,
145 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); 81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
146 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); 82 4, 0, " OpenPIC ");
147 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); 83 BUG_ON(mpic == NULL);
148 84 of_node_put(np);
149 /* dummy mappings to get to 48 */ 85
150 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); 86 mpic_assign_isu(mpic, 0, r.start + 0x10200);
151 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); 87 mpic_assign_isu(mpic, 1, r.start + 0x10280);
152 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); 88 mpic_assign_isu(mpic, 2, r.start + 0x10300);
153 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); 89 mpic_assign_isu(mpic, 3, r.start + 0x10380);
154 90 mpic_assign_isu(mpic, 4, r.start + 0x10400);
155 /* External ints */ 91 mpic_assign_isu(mpic, 5, r.start + 0x10480);
156 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); 92 mpic_assign_isu(mpic, 6, r.start + 0x10500);
157 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); 93 mpic_assign_isu(mpic, 7, r.start + 0x10580);
158 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); 94
159 mpic_init(mpic1); 95 /* Unused on this platform (leave room for 8548) */
96 mpic_assign_isu(mpic, 8, r.start + 0x10600);
97 mpic_assign_isu(mpic, 9, r.start + 0x10680);
98 mpic_assign_isu(mpic, 10, r.start + 0x10700);
99 mpic_assign_isu(mpic, 11, r.start + 0x10780);
100
101 /* External Interrupts */
102 mpic_assign_isu(mpic, 12, r.start + 0x10000);
103 mpic_assign_isu(mpic, 13, r.start + 0x10080);
104 mpic_assign_isu(mpic, 14, r.start + 0x10100);
105
106 mpic_init(mpic);
160} 107}
161 108
162/* 109/*
@@ -165,7 +112,9 @@ void __init mpc85xx_ads_pic_init(void)
165static void __init mpc85xx_ads_setup_arch(void) 112static void __init mpc85xx_ads_setup_arch(void)
166{ 113{
167 struct device_node *cpu; 114 struct device_node *cpu;
115#ifdef CONFIG_PCI
168 struct device_node *np; 116 struct device_node *np;
117#endif
169 118
170 if (ppc_md.progress) 119 if (ppc_md.progress)
171 ppc_md.progress("mpc85xx_ads_setup_arch()", 0); 120 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
@@ -186,8 +135,7 @@ static void __init mpc85xx_ads_setup_arch(void)
186 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 135 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
187 add_bridge(np); 136 add_bridge(np);
188 137
189 ppc_md.pci_swizzle = common_swizzle; 138 ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup;
190 ppc_md.pci_map_irq = mpc85xx_map_irq;
191 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 139 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
192#endif 140#endif
193 141
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 04:11:42 -0500