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authorDavid S. Miller <davem@davemloft.net>2009-06-15 06:02:23 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-15 06:02:23 -0400
commit9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb (patch)
tree8d104ec2a459346b99413b0b77421ca7b9936c1a /arch/powerpc
parentca44d6e60f9de26281fda203f58b570e1748c015 (diff)
parent45e3e1935e2857c54783291107d33323b3ef33c8 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: Documentation/feature-removal-schedule.txt drivers/scsi/fcoe/fcoe.c net/core/drop_monitor.c net/core/net-traces.c
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig12
-rw-r--r--arch/powerpc/configs/pmac32_defconfig278
-rw-r--r--arch/powerpc/configs/ps3_defconfig105
-rw-r--r--arch/powerpc/include/asm/atomic.h2
-rw-r--r--arch/powerpc/include/asm/bitsperlong.h12
-rw-r--r--arch/powerpc/include/asm/dma-mapping.h6
-rw-r--r--arch/powerpc/include/asm/fixmap.h4
-rw-r--r--arch/powerpc/include/asm/hw_irq.h36
-rw-r--r--arch/powerpc/include/asm/mman.h2
-rw-r--r--arch/powerpc/include/asm/mpc52xx_psc.h11
-rw-r--r--arch/powerpc/include/asm/paca.h1
-rw-r--r--arch/powerpc/include/asm/page_32.h2
-rw-r--r--arch/powerpc/include/asm/page_64.h2
-rw-r--r--arch/powerpc/include/asm/perf_counter.h98
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h26
-rw-r--r--arch/powerpc/include/asm/reg.h2
-rw-r--r--arch/powerpc/include/asm/signal.h2
-rw-r--r--arch/powerpc/include/asm/systbl.h2
-rw-r--r--arch/powerpc/include/asm/termios.h2
-rw-r--r--arch/powerpc/include/asm/types.h9
-rw-r--r--arch/powerpc/include/asm/unistd.h1
-rw-r--r--arch/powerpc/kernel/Makefile3
-rw-r--r--arch/powerpc/kernel/asm-offsets.c1
-rw-r--r--arch/powerpc/kernel/dma.c2
-rw-r--r--arch/powerpc/kernel/entry_64.S9
-rw-r--r--arch/powerpc/kernel/ftrace.c22
-rw-r--r--arch/powerpc/kernel/irq.c6
-rw-r--r--arch/powerpc/kernel/module.c2
-rw-r--r--arch/powerpc/kernel/perf_counter.c1263
-rw-r--r--arch/powerpc/kernel/power4-pmu.c598
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c671
-rw-r--r--arch/powerpc/kernel/power5-pmu.c611
-rw-r--r--arch/powerpc/kernel/power6-pmu.c532
-rw-r--r--arch/powerpc/kernel/power7-pmu.c357
-rw-r--r--arch/powerpc/kernel/ppc970-pmu.c482
-rw-r--r--arch/powerpc/kernel/vmlinux.lds.S1
-rw-r--r--arch/powerpc/kvm/powerpc.c6
-rw-r--r--arch/powerpc/lib/Makefile1
-rw-r--r--arch/powerpc/lib/dma-noncoherent.c237
-rw-r--r--arch/powerpc/mm/Makefile1
-rw-r--r--arch/powerpc/mm/dma-noncoherent.c400
-rw-r--r--arch/powerpc/mm/fault.c10
-rw-r--r--arch/powerpc/mm/init_32.c8
-rw-r--r--arch/powerpc/mm/mem.c17
-rw-r--r--arch/powerpc/mm/mmu_context_nohash.c6
-rw-r--r--arch/powerpc/mm/pgtable.c3
-rw-r--r--arch/powerpc/mm/pgtable_32.c2
-rw-r--r--arch/powerpc/mm/slb.c2
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype1
-rw-r--r--arch/powerpc/platforms/maple/pci.c14
-rw-r--r--arch/powerpc/platforms/pseries/xics.c12
-rw-r--r--arch/powerpc/sysdev/axonram.c2
-rw-r--r--arch/powerpc/sysdev/mpic.c4
-rw-r--r--arch/powerpc/sysdev/mpic.h2
54 files changed, 5481 insertions, 422 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a0d1146a0578..cdc9a6ff4be8 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -868,6 +868,18 @@ config TASK_SIZE
868 default "0x80000000" if PPC_PREP || PPC_8xx 868 default "0x80000000" if PPC_PREP || PPC_8xx
869 default "0xc0000000" 869 default "0xc0000000"
870 870
871config CONSISTENT_SIZE_BOOL
872 bool "Set custom consistent memory pool size"
873 depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
874 help
875 This option allows you to set the size of the
876 consistent memory pool. This pool of virtual memory
877 is used to make consistent memory allocations.
878
879config CONSISTENT_SIZE
880 hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
881 default "0x00200000" if NOT_COHERENT_CACHE
882
871config PIN_TLB 883config PIN_TLB
872 bool "Pinned Kernel TLBs (860 ONLY)" 884 bool "Pinned Kernel TLBs (860 ONLY)"
873 depends on ADVANCED_OPTIONS && 8xx 885 depends on ADVANCED_OPTIONS && 8xx
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 5339bb44cce9..ea8870a34482 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc3 3# Linux kernel version: 2.6.30-rc7
4# Tue Nov 11 19:36:51 2008 4# Mon May 25 14:53:25 2009
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -14,6 +14,7 @@ CONFIG_6xx=y
14# CONFIG_40x is not set 14# CONFIG_40x is not set
15# CONFIG_44x is not set 15# CONFIG_44x is not set
16# CONFIG_E200 is not set 16# CONFIG_E200 is not set
17CONFIG_PPC_BOOK3S=y
17CONFIG_PPC_FPU=y 18CONFIG_PPC_FPU=y
18CONFIG_ALTIVEC=y 19CONFIG_ALTIVEC=y
19CONFIG_PPC_STD_MMU=y 20CONFIG_PPC_STD_MMU=y
@@ -43,7 +44,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y
43CONFIG_PPC=y 44CONFIG_PPC=y
44CONFIG_EARLY_PRINTK=y 45CONFIG_EARLY_PRINTK=y
45CONFIG_GENERIC_NVRAM=y 46CONFIG_GENERIC_NVRAM=y
46CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 47CONFIG_SCHED_OMIT_FRAME_POINTER=y
47CONFIG_ARCH_MAY_HAVE_PC_FDC=y 48CONFIG_ARCH_MAY_HAVE_PC_FDC=y
48CONFIG_PPC_OF=y 49CONFIG_PPC_OF=y
49CONFIG_OF=y 50CONFIG_OF=y
@@ -52,12 +53,14 @@ CONFIG_OF=y
52CONFIG_AUDIT_ARCH=y 53CONFIG_AUDIT_ARCH=y
53CONFIG_GENERIC_BUG=y 54CONFIG_GENERIC_BUG=y
54CONFIG_SYS_SUPPORTS_APM_EMULATION=y 55CONFIG_SYS_SUPPORTS_APM_EMULATION=y
56CONFIG_DTC=y
55# CONFIG_DEFAULT_UIMAGE is not set 57# CONFIG_DEFAULT_UIMAGE is not set
56CONFIG_HIBERNATE_32=y 58CONFIG_HIBERNATE_32=y
57CONFIG_ARCH_HIBERNATION_POSSIBLE=y 59CONFIG_ARCH_HIBERNATION_POSSIBLE=y
58CONFIG_ARCH_SUSPEND_POSSIBLE=y 60CONFIG_ARCH_SUSPEND_POSSIBLE=y
59# CONFIG_PPC_DCR_NATIVE is not set 61# CONFIG_PPC_DCR_NATIVE is not set
60# CONFIG_PPC_DCR_MMIO is not set 62# CONFIG_PPC_DCR_MMIO is not set
63CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 64CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
62 65
63# 66#
@@ -72,14 +75,24 @@ CONFIG_SWAP=y
72CONFIG_SYSVIPC=y 75CONFIG_SYSVIPC=y
73CONFIG_SYSVIPC_SYSCTL=y 76CONFIG_SYSVIPC_SYSCTL=y
74CONFIG_POSIX_MQUEUE=y 77CONFIG_POSIX_MQUEUE=y
78CONFIG_POSIX_MQUEUE_SYSCTL=y
75# CONFIG_BSD_PROCESS_ACCT is not set 79# CONFIG_BSD_PROCESS_ACCT is not set
76# CONFIG_TASKSTATS is not set 80# CONFIG_TASKSTATS is not set
77# CONFIG_AUDIT is not set 81# CONFIG_AUDIT is not set
82
83#
84# RCU Subsystem
85#
86CONFIG_CLASSIC_RCU=y
87# CONFIG_TREE_RCU is not set
88# CONFIG_PREEMPT_RCU is not set
89# CONFIG_TREE_RCU_TRACE is not set
90# CONFIG_PREEMPT_RCU_TRACE is not set
78CONFIG_IKCONFIG=y 91CONFIG_IKCONFIG=y
79CONFIG_IKCONFIG_PROC=y 92CONFIG_IKCONFIG_PROC=y
80CONFIG_LOG_BUF_SHIFT=14 93CONFIG_LOG_BUF_SHIFT=14
81# CONFIG_CGROUPS is not set
82# CONFIG_GROUP_SCHED is not set 94# CONFIG_GROUP_SCHED is not set
95# CONFIG_CGROUPS is not set
83CONFIG_SYSFS_DEPRECATED=y 96CONFIG_SYSFS_DEPRECATED=y
84CONFIG_SYSFS_DEPRECATED_V2=y 97CONFIG_SYSFS_DEPRECATED_V2=y
85# CONFIG_RELAY is not set 98# CONFIG_RELAY is not set
@@ -88,23 +101,27 @@ CONFIG_NAMESPACES=y
88# CONFIG_IPC_NS is not set 101# CONFIG_IPC_NS is not set
89# CONFIG_USER_NS is not set 102# CONFIG_USER_NS is not set
90# CONFIG_PID_NS is not set 103# CONFIG_PID_NS is not set
104# CONFIG_NET_NS is not set
91CONFIG_BLK_DEV_INITRD=y 105CONFIG_BLK_DEV_INITRD=y
92CONFIG_INITRAMFS_SOURCE="" 106CONFIG_INITRAMFS_SOURCE=""
107CONFIG_RD_GZIP=y
108CONFIG_RD_BZIP2=y
109CONFIG_RD_LZMA=y
93# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 110# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
94CONFIG_SYSCTL=y 111CONFIG_SYSCTL=y
112CONFIG_ANON_INODES=y
95# CONFIG_EMBEDDED is not set 113# CONFIG_EMBEDDED is not set
96CONFIG_SYSCTL_SYSCALL=y 114CONFIG_SYSCTL_SYSCALL=y
97CONFIG_KALLSYMS=y 115CONFIG_KALLSYMS=y
98CONFIG_KALLSYMS_ALL=y 116CONFIG_KALLSYMS_ALL=y
99# CONFIG_KALLSYMS_EXTRA_PASS is not set 117# CONFIG_KALLSYMS_EXTRA_PASS is not set
118# CONFIG_STRIP_ASM_SYMS is not set
100CONFIG_HOTPLUG=y 119CONFIG_HOTPLUG=y
101CONFIG_PRINTK=y 120CONFIG_PRINTK=y
102CONFIG_BUG=y 121CONFIG_BUG=y
103CONFIG_ELF_CORE=y 122CONFIG_ELF_CORE=y
104# CONFIG_COMPAT_BRK is not set
105CONFIG_BASE_FULL=y 123CONFIG_BASE_FULL=y
106CONFIG_FUTEX=y 124CONFIG_FUTEX=y
107CONFIG_ANON_INODES=y
108CONFIG_EPOLL=y 125CONFIG_EPOLL=y
109CONFIG_SIGNALFD=y 126CONFIG_SIGNALFD=y
110CONFIG_TIMERFD=y 127CONFIG_TIMERFD=y
@@ -114,10 +131,12 @@ CONFIG_AIO=y
114CONFIG_VM_EVENT_COUNTERS=y 131CONFIG_VM_EVENT_COUNTERS=y
115CONFIG_PCI_QUIRKS=y 132CONFIG_PCI_QUIRKS=y
116CONFIG_SLUB_DEBUG=y 133CONFIG_SLUB_DEBUG=y
134# CONFIG_COMPAT_BRK is not set
117# CONFIG_SLAB is not set 135# CONFIG_SLAB is not set
118CONFIG_SLUB=y 136CONFIG_SLUB=y
119# CONFIG_SLOB is not set 137# CONFIG_SLOB is not set
120CONFIG_PROFILING=y 138CONFIG_PROFILING=y
139CONFIG_TRACEPOINTS=y
121# CONFIG_MARKERS is not set 140# CONFIG_MARKERS is not set
122CONFIG_OPROFILE=y 141CONFIG_OPROFILE=y
123CONFIG_HAVE_OPROFILE=y 142CONFIG_HAVE_OPROFILE=y
@@ -127,10 +146,10 @@ CONFIG_HAVE_IOREMAP_PROT=y
127CONFIG_HAVE_KPROBES=y 146CONFIG_HAVE_KPROBES=y
128CONFIG_HAVE_KRETPROBES=y 147CONFIG_HAVE_KRETPROBES=y
129CONFIG_HAVE_ARCH_TRACEHOOK=y 148CONFIG_HAVE_ARCH_TRACEHOOK=y
149# CONFIG_SLOW_WORK is not set
130# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 150# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
131CONFIG_SLABINFO=y 151CONFIG_SLABINFO=y
132CONFIG_RT_MUTEXES=y 152CONFIG_RT_MUTEXES=y
133# CONFIG_TINY_SHMEM is not set
134CONFIG_BASE_SMALL=0 153CONFIG_BASE_SMALL=0
135CONFIG_MODULES=y 154CONFIG_MODULES=y
136# CONFIG_MODULE_FORCE_LOAD is not set 155# CONFIG_MODULE_FORCE_LOAD is not set
@@ -138,11 +157,8 @@ CONFIG_MODULE_UNLOAD=y
138CONFIG_MODULE_FORCE_UNLOAD=y 157CONFIG_MODULE_FORCE_UNLOAD=y
139# CONFIG_MODVERSIONS is not set 158# CONFIG_MODVERSIONS is not set
140# CONFIG_MODULE_SRCVERSION_ALL is not set 159# CONFIG_MODULE_SRCVERSION_ALL is not set
141CONFIG_KMOD=y
142CONFIG_BLOCK=y 160CONFIG_BLOCK=y
143CONFIG_LBD=y 161CONFIG_LBD=y
144# CONFIG_BLK_DEV_IO_TRACE is not set
145CONFIG_LSF=y
146CONFIG_BLK_DEV_BSG=y 162CONFIG_BLK_DEV_BSG=y
147# CONFIG_BLK_DEV_INTEGRITY is not set 163# CONFIG_BLK_DEV_INTEGRITY is not set
148 164
@@ -158,14 +174,11 @@ CONFIG_DEFAULT_AS=y
158# CONFIG_DEFAULT_CFQ is not set 174# CONFIG_DEFAULT_CFQ is not set
159# CONFIG_DEFAULT_NOOP is not set 175# CONFIG_DEFAULT_NOOP is not set
160CONFIG_DEFAULT_IOSCHED="anticipatory" 176CONFIG_DEFAULT_IOSCHED="anticipatory"
161CONFIG_CLASSIC_RCU=y
162CONFIG_FREEZER=y 177CONFIG_FREEZER=y
163 178
164# 179#
165# Platform support 180# Platform support
166# 181#
167CONFIG_PPC_MULTIPLATFORM=y
168CONFIG_CLASSIC32=y
169# CONFIG_PPC_CHRP is not set 182# CONFIG_PPC_CHRP is not set
170# CONFIG_MPC5121_ADS is not set 183# CONFIG_MPC5121_ADS is not set
171# CONFIG_MPC5121_GENERIC is not set 184# CONFIG_MPC5121_GENERIC is not set
@@ -178,7 +191,9 @@ CONFIG_PPC_PMAC=y
178# CONFIG_PPC_83xx is not set 191# CONFIG_PPC_83xx is not set
179# CONFIG_PPC_86xx is not set 192# CONFIG_PPC_86xx is not set
180# CONFIG_EMBEDDED6xx is not set 193# CONFIG_EMBEDDED6xx is not set
194# CONFIG_AMIGAONE is not set
181CONFIG_PPC_NATIVE=y 195CONFIG_PPC_NATIVE=y
196CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
182# CONFIG_IPIC is not set 197# CONFIG_IPIC is not set
183CONFIG_MPIC=y 198CONFIG_MPIC=y
184# CONFIG_MPIC_WEIRD is not set 199# CONFIG_MPIC_WEIRD is not set
@@ -212,11 +227,12 @@ CONFIG_CPU_FREQ_PMAC=y
212CONFIG_PPC601_SYNC_FIX=y 227CONFIG_PPC601_SYNC_FIX=y
213# CONFIG_TAU is not set 228# CONFIG_TAU is not set
214# CONFIG_FSL_ULI1575 is not set 229# CONFIG_FSL_ULI1575 is not set
230# CONFIG_SIMPLE_GPIO is not set
215 231
216# 232#
217# Kernel options 233# Kernel options
218# 234#
219# CONFIG_HIGHMEM is not set 235CONFIG_HIGHMEM=y
220CONFIG_TICK_ONESHOT=y 236CONFIG_TICK_ONESHOT=y
221CONFIG_NO_HZ=y 237CONFIG_NO_HZ=y
222CONFIG_HIGH_RES_TIMERS=y 238CONFIG_HIGH_RES_TIMERS=y
@@ -239,6 +255,7 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
239CONFIG_ARCH_HAS_WALK_MEMORY=y 255CONFIG_ARCH_HAS_WALK_MEMORY=y
240CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 256CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
241# CONFIG_KEXEC is not set 257# CONFIG_KEXEC is not set
258# CONFIG_CRASH_DUMP is not set
242CONFIG_ARCH_FLATMEM_ENABLE=y 259CONFIG_ARCH_FLATMEM_ENABLE=y
243CONFIG_ARCH_POPULATES_NODE_MAP=y 260CONFIG_ARCH_POPULATES_NODE_MAP=y
244CONFIG_SELECT_MEMORY_MODEL=y 261CONFIG_SELECT_MEMORY_MODEL=y
@@ -250,12 +267,17 @@ CONFIG_FLAT_NODE_MEM_MAP=y
250CONFIG_PAGEFLAGS_EXTENDED=y 267CONFIG_PAGEFLAGS_EXTENDED=y
251CONFIG_SPLIT_PTLOCK_CPUS=4 268CONFIG_SPLIT_PTLOCK_CPUS=4
252# CONFIG_MIGRATION is not set 269# CONFIG_MIGRATION is not set
253# CONFIG_RESOURCES_64BIT is not set
254# CONFIG_PHYS_ADDR_T_64BIT is not set 270# CONFIG_PHYS_ADDR_T_64BIT is not set
255CONFIG_ZONE_DMA_FLAG=1 271CONFIG_ZONE_DMA_FLAG=1
256CONFIG_BOUNCE=y 272CONFIG_BOUNCE=y
257CONFIG_VIRT_TO_BUS=y 273CONFIG_VIRT_TO_BUS=y
258CONFIG_UNEVICTABLE_LRU=y 274CONFIG_UNEVICTABLE_LRU=y
275CONFIG_HAVE_MLOCK=y
276CONFIG_HAVE_MLOCKED_PAGE_BIT=y
277CONFIG_PPC_4K_PAGES=y
278# CONFIG_PPC_16K_PAGES is not set
279# CONFIG_PPC_64K_PAGES is not set
280# CONFIG_PPC_256K_PAGES is not set
259CONFIG_FORCE_MAX_ZONEORDER=11 281CONFIG_FORCE_MAX_ZONEORDER=11
260CONFIG_PROC_DEVICETREE=y 282CONFIG_PROC_DEVICETREE=y
261# CONFIG_CMDLINE_BOOL is not set 283# CONFIG_CMDLINE_BOOL is not set
@@ -288,6 +310,8 @@ CONFIG_ARCH_SUPPORTS_MSI=y
288# CONFIG_PCI_MSI is not set 310# CONFIG_PCI_MSI is not set
289# CONFIG_PCI_LEGACY is not set 311# CONFIG_PCI_LEGACY is not set
290# CONFIG_PCI_DEBUG is not set 312# CONFIG_PCI_DEBUG is not set
313# CONFIG_PCI_STUB is not set
314# CONFIG_PCI_IOV is not set
291CONFIG_PCCARD=m 315CONFIG_PCCARD=m
292# CONFIG_PCMCIA_DEBUG is not set 316# CONFIG_PCMCIA_DEBUG is not set
293CONFIG_PCMCIA=m 317CONFIG_PCMCIA=m
@@ -397,6 +421,8 @@ CONFIG_NETFILTER_XTABLES=m
397CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 421CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
398# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set 422# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
399# CONFIG_NETFILTER_XT_TARGET_DSCP is not set 423# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
424CONFIG_NETFILTER_XT_TARGET_HL=m
425# CONFIG_NETFILTER_XT_TARGET_LED is not set
400CONFIG_NETFILTER_XT_TARGET_MARK=m 426CONFIG_NETFILTER_XT_TARGET_MARK=m
401CONFIG_NETFILTER_XT_TARGET_NFLOG=m 427CONFIG_NETFILTER_XT_TARGET_NFLOG=m
402CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 428CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
@@ -405,6 +431,7 @@ CONFIG_NETFILTER_XT_TARGET_RATEEST=m
405CONFIG_NETFILTER_XT_TARGET_TRACE=m 431CONFIG_NETFILTER_XT_TARGET_TRACE=m
406CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 432CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
407CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 433CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
434# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
408CONFIG_NETFILTER_XT_MATCH_COMMENT=m 435CONFIG_NETFILTER_XT_MATCH_COMMENT=m
409# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set 436# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
410CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m 437CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
@@ -415,6 +442,7 @@ CONFIG_NETFILTER_XT_MATCH_DSCP=m
415CONFIG_NETFILTER_XT_MATCH_ESP=m 442CONFIG_NETFILTER_XT_MATCH_ESP=m
416# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set 443# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
417CONFIG_NETFILTER_XT_MATCH_HELPER=m 444CONFIG_NETFILTER_XT_MATCH_HELPER=m
445CONFIG_NETFILTER_XT_MATCH_HL=m
418CONFIG_NETFILTER_XT_MATCH_IPRANGE=m 446CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
419CONFIG_NETFILTER_XT_MATCH_LENGTH=m 447CONFIG_NETFILTER_XT_MATCH_LENGTH=m
420CONFIG_NETFILTER_XT_MATCH_LIMIT=m 448CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@@ -478,17 +506,15 @@ CONFIG_IP_NF_ARPFILTER=m
478CONFIG_IP_NF_ARP_MANGLE=m 506CONFIG_IP_NF_ARP_MANGLE=m
479CONFIG_IP_DCCP=m 507CONFIG_IP_DCCP=m
480CONFIG_INET_DCCP_DIAG=m 508CONFIG_INET_DCCP_DIAG=m
481CONFIG_IP_DCCP_ACKVEC=y
482 509
483# 510#
484# DCCP CCIDs Configuration (EXPERIMENTAL) 511# DCCP CCIDs Configuration (EXPERIMENTAL)
485# 512#
486CONFIG_IP_DCCP_CCID2=m
487# CONFIG_IP_DCCP_CCID2_DEBUG is not set 513# CONFIG_IP_DCCP_CCID2_DEBUG is not set
488CONFIG_IP_DCCP_CCID3=m 514CONFIG_IP_DCCP_CCID3=y
489# CONFIG_IP_DCCP_CCID3_DEBUG is not set 515# CONFIG_IP_DCCP_CCID3_DEBUG is not set
490CONFIG_IP_DCCP_CCID3_RTO=100 516CONFIG_IP_DCCP_CCID3_RTO=100
491CONFIG_IP_DCCP_TFRC_LIB=m 517CONFIG_IP_DCCP_TFRC_LIB=y
492 518
493# 519#
494# DCCP Kernel Hacking 520# DCCP Kernel Hacking
@@ -508,13 +534,16 @@ CONFIG_IP_DCCP_TFRC_LIB=m
508# CONFIG_LAPB is not set 534# CONFIG_LAPB is not set
509# CONFIG_ECONET is not set 535# CONFIG_ECONET is not set
510# CONFIG_WAN_ROUTER is not set 536# CONFIG_WAN_ROUTER is not set
537# CONFIG_PHONET is not set
511# CONFIG_NET_SCHED is not set 538# CONFIG_NET_SCHED is not set
512CONFIG_NET_CLS_ROUTE=y 539CONFIG_NET_CLS_ROUTE=y
540# CONFIG_DCB is not set
513 541
514# 542#
515# Network testing 543# Network testing
516# 544#
517# CONFIG_NET_PKTGEN is not set 545# CONFIG_NET_PKTGEN is not set
546# CONFIG_NET_DROP_MONITOR is not set
518# CONFIG_HAMRADIO is not set 547# CONFIG_HAMRADIO is not set
519# CONFIG_CAN is not set 548# CONFIG_CAN is not set
520CONFIG_IRDA=m 549CONFIG_IRDA=m
@@ -577,8 +606,6 @@ CONFIG_BT_HIDP=m
577# 606#
578# Bluetooth device drivers 607# Bluetooth device drivers
579# 608#
580CONFIG_BT_HCIUSB=m
581# CONFIG_BT_HCIUSB_SCO is not set
582# CONFIG_BT_HCIBTUSB is not set 609# CONFIG_BT_HCIBTUSB is not set
583# CONFIG_BT_HCIUART is not set 610# CONFIG_BT_HCIUART is not set
584CONFIG_BT_HCIBCM203X=m 611CONFIG_BT_HCIBCM203X=m
@@ -590,31 +617,27 @@ CONFIG_BT_HCIBFUSB=m
590# CONFIG_BT_HCIBTUART is not set 617# CONFIG_BT_HCIBTUART is not set
591# CONFIG_BT_HCIVHCI is not set 618# CONFIG_BT_HCIVHCI is not set
592# CONFIG_AF_RXRPC is not set 619# CONFIG_AF_RXRPC is not set
593# CONFIG_PHONET is not set
594CONFIG_WIRELESS=y 620CONFIG_WIRELESS=y
595CONFIG_CFG80211=m 621CONFIG_CFG80211=m
596CONFIG_NL80211=y 622# CONFIG_CFG80211_REG_DEBUG is not set
597CONFIG_WIRELESS_OLD_REGULATORY=y 623CONFIG_WIRELESS_OLD_REGULATORY=y
598CONFIG_WIRELESS_EXT=y 624CONFIG_WIRELESS_EXT=y
599CONFIG_WIRELESS_EXT_SYSFS=y 625CONFIG_WIRELESS_EXT_SYSFS=y
626# CONFIG_LIB80211 is not set
600CONFIG_MAC80211=m 627CONFIG_MAC80211=m
601 628
602# 629#
603# Rate control algorithm selection 630# Rate control algorithm selection
604# 631#
605CONFIG_MAC80211_RC_PID=y 632CONFIG_MAC80211_RC_MINSTREL=y
606# CONFIG_MAC80211_RC_MINSTREL is not set 633# CONFIG_MAC80211_RC_DEFAULT_PID is not set
607CONFIG_MAC80211_RC_DEFAULT_PID=y 634CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
608# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set 635CONFIG_MAC80211_RC_DEFAULT="minstrel"
609CONFIG_MAC80211_RC_DEFAULT="pid"
610# CONFIG_MAC80211_MESH is not set 636# CONFIG_MAC80211_MESH is not set
611CONFIG_MAC80211_LEDS=y 637CONFIG_MAC80211_LEDS=y
638# CONFIG_MAC80211_DEBUGFS is not set
612# CONFIG_MAC80211_DEBUG_MENU is not set 639# CONFIG_MAC80211_DEBUG_MENU is not set
613CONFIG_IEEE80211=m 640# CONFIG_WIMAX is not set
614# CONFIG_IEEE80211_DEBUG is not set
615CONFIG_IEEE80211_CRYPT_WEP=m
616CONFIG_IEEE80211_CRYPT_CCMP=m
617CONFIG_IEEE80211_CRYPT_TKIP=m
618# CONFIG_RFKILL is not set 641# CONFIG_RFKILL is not set
619# CONFIG_NET_9P is not set 642# CONFIG_NET_9P is not set
620 643
@@ -662,17 +685,27 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
662# CONFIG_BLK_DEV_HD is not set 685# CONFIG_BLK_DEV_HD is not set
663CONFIG_MISC_DEVICES=y 686CONFIG_MISC_DEVICES=y
664# CONFIG_PHANTOM is not set 687# CONFIG_PHANTOM is not set
665# CONFIG_EEPROM_93CX6 is not set
666# CONFIG_SGI_IOC4 is not set 688# CONFIG_SGI_IOC4 is not set
667# CONFIG_TIFM_CORE is not set 689# CONFIG_TIFM_CORE is not set
690# CONFIG_ICS932S401 is not set
668# CONFIG_ENCLOSURE_SERVICES is not set 691# CONFIG_ENCLOSURE_SERVICES is not set
669# CONFIG_HP_ILO is not set 692# CONFIG_HP_ILO is not set
693# CONFIG_ISL29003 is not set
694# CONFIG_C2PORT is not set
695
696#
697# EEPROM support
698#
699# CONFIG_EEPROM_AT24 is not set
700# CONFIG_EEPROM_LEGACY is not set
701# CONFIG_EEPROM_93CX6 is not set
670CONFIG_HAVE_IDE=y 702CONFIG_HAVE_IDE=y
671CONFIG_IDE=y 703CONFIG_IDE=y
672 704
673# 705#
674# Please see Documentation/ide/ide.txt for help/info on IDE drives 706# Please see Documentation/ide/ide.txt for help/info on IDE drives
675# 707#
708CONFIG_IDE_XFER_MODE=y
676CONFIG_IDE_TIMINGS=y 709CONFIG_IDE_TIMINGS=y
677CONFIG_IDE_ATAPI=y 710CONFIG_IDE_ATAPI=y
678# CONFIG_BLK_DEV_IDE_SATA is not set 711# CONFIG_BLK_DEV_IDE_SATA is not set
@@ -684,7 +717,6 @@ CONFIG_BLK_DEV_IDECS=m
684CONFIG_BLK_DEV_IDECD=y 717CONFIG_BLK_DEV_IDECD=y
685CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y 718CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
686# CONFIG_BLK_DEV_IDETAPE is not set 719# CONFIG_BLK_DEV_IDETAPE is not set
687CONFIG_BLK_DEV_IDESCSI=y
688# CONFIG_IDE_TASK_IOCTL is not set 720# CONFIG_IDE_TASK_IOCTL is not set
689CONFIG_IDE_PROC_FS=y 721CONFIG_IDE_PROC_FS=y
690 722
@@ -714,6 +746,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
714# CONFIG_BLK_DEV_JMICRON is not set 746# CONFIG_BLK_DEV_JMICRON is not set
715# CONFIG_BLK_DEV_SC1200 is not set 747# CONFIG_BLK_DEV_SC1200 is not set
716# CONFIG_BLK_DEV_PIIX is not set 748# CONFIG_BLK_DEV_PIIX is not set
749# CONFIG_BLK_DEV_IT8172 is not set
717# CONFIG_BLK_DEV_IT8213 is not set 750# CONFIG_BLK_DEV_IT8213 is not set
718# CONFIG_BLK_DEV_IT821X is not set 751# CONFIG_BLK_DEV_IT821X is not set
719# CONFIG_BLK_DEV_NS87415 is not set 752# CONFIG_BLK_DEV_NS87415 is not set
@@ -728,7 +761,6 @@ CONFIG_BLK_DEV_SL82C105=y
728# CONFIG_BLK_DEV_TC86C001 is not set 761# CONFIG_BLK_DEV_TC86C001 is not set
729CONFIG_BLK_DEV_IDE_PMAC=y 762CONFIG_BLK_DEV_IDE_PMAC=y
730CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y 763CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
731CONFIG_BLK_DEV_IDEDMA_PMAC=y
732CONFIG_BLK_DEV_IDEDMA=y 764CONFIG_BLK_DEV_IDEDMA=y
733 765
734# 766#
@@ -772,6 +804,7 @@ CONFIG_SCSI_FC_ATTRS=y
772# CONFIG_SCSI_SRP_ATTRS is not set 804# CONFIG_SCSI_SRP_ATTRS is not set
773CONFIG_SCSI_LOWLEVEL=y 805CONFIG_SCSI_LOWLEVEL=y
774# CONFIG_ISCSI_TCP is not set 806# CONFIG_ISCSI_TCP is not set
807# CONFIG_SCSI_CXGB3_ISCSI is not set
775# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 808# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
776# CONFIG_SCSI_3W_9XXX is not set 809# CONFIG_SCSI_3W_9XXX is not set
777# CONFIG_SCSI_ACARD is not set 810# CONFIG_SCSI_ACARD is not set
@@ -791,8 +824,12 @@ CONFIG_SCSI_AIC7XXX_OLD=m
791# CONFIG_MEGARAID_NEWGEN is not set 824# CONFIG_MEGARAID_NEWGEN is not set
792# CONFIG_MEGARAID_LEGACY is not set 825# CONFIG_MEGARAID_LEGACY is not set
793# CONFIG_MEGARAID_SAS is not set 826# CONFIG_MEGARAID_SAS is not set
827# CONFIG_SCSI_MPT2SAS is not set
794# CONFIG_SCSI_HPTIOP is not set 828# CONFIG_SCSI_HPTIOP is not set
795# CONFIG_SCSI_BUSLOGIC is not set 829# CONFIG_SCSI_BUSLOGIC is not set
830# CONFIG_LIBFC is not set
831# CONFIG_LIBFCOE is not set
832# CONFIG_FCOE is not set
796# CONFIG_SCSI_DMX3191D is not set 833# CONFIG_SCSI_DMX3191D is not set
797# CONFIG_SCSI_EATA is not set 834# CONFIG_SCSI_EATA is not set
798# CONFIG_SCSI_FUTURE_DOMAIN is not set 835# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -822,6 +859,7 @@ CONFIG_SCSI_MAC53C94=y
822# CONFIG_SCSI_SRP is not set 859# CONFIG_SCSI_SRP is not set
823# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 860# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
824# CONFIG_SCSI_DH is not set 861# CONFIG_SCSI_DH is not set
862# CONFIG_SCSI_OSD_INITIATOR is not set
825# CONFIG_ATA is not set 863# CONFIG_ATA is not set
826CONFIG_MD=y 864CONFIG_MD=y
827CONFIG_BLK_DEV_MD=m 865CONFIG_BLK_DEV_MD=m
@@ -881,6 +919,7 @@ CONFIG_THERM_ADT746X=m
881# CONFIG_ANSLCD is not set 919# CONFIG_ANSLCD is not set
882CONFIG_PMAC_RACKMETER=m 920CONFIG_PMAC_RACKMETER=m
883CONFIG_NETDEVICES=y 921CONFIG_NETDEVICES=y
922CONFIG_COMPAT_NET_DEV_OPS=y
884CONFIG_DUMMY=m 923CONFIG_DUMMY=m
885# CONFIG_BONDING is not set 924# CONFIG_BONDING is not set
886# CONFIG_MACVLAN is not set 925# CONFIG_MACVLAN is not set
@@ -898,6 +937,8 @@ CONFIG_BMAC=y
898CONFIG_SUNGEM=y 937CONFIG_SUNGEM=y
899# CONFIG_CASSINI is not set 938# CONFIG_CASSINI is not set
900# CONFIG_NET_VENDOR_3COM is not set 939# CONFIG_NET_VENDOR_3COM is not set
940# CONFIG_ETHOC is not set
941# CONFIG_DNET is not set
901# CONFIG_NET_TULIP is not set 942# CONFIG_NET_TULIP is not set
902# CONFIG_HP100 is not set 943# CONFIG_HP100 is not set
903# CONFIG_IBM_NEW_EMAC_ZMII is not set 944# CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -913,7 +954,6 @@ CONFIG_PCNET32=y
913# CONFIG_ADAPTEC_STARFIRE is not set 954# CONFIG_ADAPTEC_STARFIRE is not set
914# CONFIG_B44 is not set 955# CONFIG_B44 is not set
915# CONFIG_FORCEDETH is not set 956# CONFIG_FORCEDETH is not set
916# CONFIG_EEPRO100 is not set
917# CONFIG_E100 is not set 957# CONFIG_E100 is not set
918# CONFIG_FEALNX is not set 958# CONFIG_FEALNX is not set
919# CONFIG_NATSEMI is not set 959# CONFIG_NATSEMI is not set
@@ -923,6 +963,7 @@ CONFIG_PCNET32=y
923# CONFIG_R6040 is not set 963# CONFIG_R6040 is not set
924# CONFIG_SIS900 is not set 964# CONFIG_SIS900 is not set
925# CONFIG_EPIC100 is not set 965# CONFIG_EPIC100 is not set
966# CONFIG_SMSC9420 is not set
926# CONFIG_SUNDANCE is not set 967# CONFIG_SUNDANCE is not set
927# CONFIG_TLAN is not set 968# CONFIG_TLAN is not set
928# CONFIG_VIA_RHINE is not set 969# CONFIG_VIA_RHINE is not set
@@ -935,6 +976,7 @@ CONFIG_NETDEV_1000=y
935# CONFIG_E1000E is not set 976# CONFIG_E1000E is not set
936# CONFIG_IP1000 is not set 977# CONFIG_IP1000 is not set
937# CONFIG_IGB is not set 978# CONFIG_IGB is not set
979# CONFIG_IGBVF is not set
938# CONFIG_NS83820 is not set 980# CONFIG_NS83820 is not set
939# CONFIG_HAMACHI is not set 981# CONFIG_HAMACHI is not set
940# CONFIG_YELLOWFIN is not set 982# CONFIG_YELLOWFIN is not set
@@ -945,18 +987,20 @@ CONFIG_NETDEV_1000=y
945# CONFIG_VIA_VELOCITY is not set 987# CONFIG_VIA_VELOCITY is not set
946# CONFIG_TIGON3 is not set 988# CONFIG_TIGON3 is not set
947# CONFIG_BNX2 is not set 989# CONFIG_BNX2 is not set
948# CONFIG_MV643XX_ETH is not set
949# CONFIG_QLA3XXX is not set 990# CONFIG_QLA3XXX is not set
950# CONFIG_ATL1 is not set 991# CONFIG_ATL1 is not set
951# CONFIG_ATL1E is not set 992# CONFIG_ATL1E is not set
993# CONFIG_ATL1C is not set
952# CONFIG_JME is not set 994# CONFIG_JME is not set
953CONFIG_NETDEV_10000=y 995CONFIG_NETDEV_10000=y
954# CONFIG_CHELSIO_T1 is not set 996# CONFIG_CHELSIO_T1 is not set
997CONFIG_CHELSIO_T3_DEPENDS=y
955# CONFIG_CHELSIO_T3 is not set 998# CONFIG_CHELSIO_T3 is not set
956# CONFIG_ENIC is not set 999# CONFIG_ENIC is not set
957# CONFIG_IXGBE is not set 1000# CONFIG_IXGBE is not set
958# CONFIG_IXGB is not set 1001# CONFIG_IXGB is not set
959# CONFIG_S2IO is not set 1002# CONFIG_S2IO is not set
1003# CONFIG_VXGE is not set
960# CONFIG_MYRI10GE is not set 1004# CONFIG_MYRI10GE is not set
961# CONFIG_NETXEN_NIC is not set 1005# CONFIG_NETXEN_NIC is not set
962# CONFIG_NIU is not set 1006# CONFIG_NIU is not set
@@ -966,6 +1010,7 @@ CONFIG_NETDEV_10000=y
966# CONFIG_BNX2X is not set 1010# CONFIG_BNX2X is not set
967# CONFIG_QLGE is not set 1011# CONFIG_QLGE is not set
968# CONFIG_SFC is not set 1012# CONFIG_SFC is not set
1013# CONFIG_BE2NET is not set
969# CONFIG_TR is not set 1014# CONFIG_TR is not set
970 1015
971# 1016#
@@ -974,20 +1019,11 @@ CONFIG_NETDEV_10000=y
974# CONFIG_WLAN_PRE80211 is not set 1019# CONFIG_WLAN_PRE80211 is not set
975CONFIG_WLAN_80211=y 1020CONFIG_WLAN_80211=y
976# CONFIG_PCMCIA_RAYCS is not set 1021# CONFIG_PCMCIA_RAYCS is not set
977# CONFIG_IPW2100 is not set
978# CONFIG_IPW2200 is not set
979# CONFIG_LIBERTAS is not set 1022# CONFIG_LIBERTAS is not set
980# CONFIG_LIBERTAS_THINFIRM is not set 1023# CONFIG_LIBERTAS_THINFIRM is not set
981# CONFIG_AIRO is not set 1024# CONFIG_AIRO is not set
982CONFIG_HERMES=m
983CONFIG_APPLE_AIRPORT=m
984# CONFIG_PLX_HERMES is not set
985# CONFIG_TMD_HERMES is not set
986# CONFIG_NORTEL_HERMES is not set
987CONFIG_PCI_HERMES=m
988CONFIG_PCMCIA_HERMES=m
989# CONFIG_PCMCIA_SPECTRUM is not set
990# CONFIG_ATMEL is not set 1025# CONFIG_ATMEL is not set
1026# CONFIG_AT76C50X_USB is not set
991# CONFIG_AIRO_CS is not set 1027# CONFIG_AIRO_CS is not set
992# CONFIG_PCMCIA_WL3501 is not set 1028# CONFIG_PCMCIA_WL3501 is not set
993CONFIG_PRISM54=m 1029CONFIG_PRISM54=m
@@ -997,15 +1033,17 @@ CONFIG_PRISM54=m
997# CONFIG_RTL8187 is not set 1033# CONFIG_RTL8187 is not set
998# CONFIG_ADM8211 is not set 1034# CONFIG_ADM8211 is not set
999# CONFIG_MAC80211_HWSIM is not set 1035# CONFIG_MAC80211_HWSIM is not set
1036# CONFIG_MWL8K is not set
1000CONFIG_P54_COMMON=m 1037CONFIG_P54_COMMON=m
1001# CONFIG_P54_USB is not set 1038# CONFIG_P54_USB is not set
1002# CONFIG_P54_PCI is not set 1039# CONFIG_P54_PCI is not set
1040CONFIG_P54_LEDS=y
1003# CONFIG_ATH5K is not set 1041# CONFIG_ATH5K is not set
1004# CONFIG_ATH9K is not set 1042# CONFIG_ATH9K is not set
1005# CONFIG_IWLCORE is not set 1043# CONFIG_AR9170_USB is not set
1006# CONFIG_IWLWIFI_LEDS is not set 1044# CONFIG_IPW2100 is not set
1007# CONFIG_IWLAGN is not set 1045# CONFIG_IPW2200 is not set
1008# CONFIG_IWL3945 is not set 1046# CONFIG_IWLWIFI is not set
1009# CONFIG_HOSTAP is not set 1047# CONFIG_HOSTAP is not set
1010CONFIG_B43=m 1048CONFIG_B43=m
1011CONFIG_B43_PCI_AUTOSELECT=y 1049CONFIG_B43_PCI_AUTOSELECT=y
@@ -1025,6 +1063,19 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
1025# CONFIG_B43LEGACY_PIO_MODE is not set 1063# CONFIG_B43LEGACY_PIO_MODE is not set
1026# CONFIG_ZD1211RW is not set 1064# CONFIG_ZD1211RW is not set
1027# CONFIG_RT2X00 is not set 1065# CONFIG_RT2X00 is not set
1066CONFIG_HERMES=m
1067CONFIG_HERMES_CACHE_FW_ON_INIT=y
1068CONFIG_APPLE_AIRPORT=m
1069# CONFIG_PLX_HERMES is not set
1070# CONFIG_TMD_HERMES is not set
1071# CONFIG_NORTEL_HERMES is not set
1072CONFIG_PCI_HERMES=m
1073CONFIG_PCMCIA_HERMES=m
1074# CONFIG_PCMCIA_SPECTRUM is not set
1075
1076#
1077# Enable WiMAX (Networking options) to see the WiMAX drivers
1078#
1028 1079
1029# 1080#
1030# USB Network Adapters 1081# USB Network Adapters
@@ -1036,6 +1087,7 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
1036CONFIG_USB_USBNET=m 1087CONFIG_USB_USBNET=m
1037CONFIG_USB_NET_AX8817X=m 1088CONFIG_USB_NET_AX8817X=m
1038CONFIG_USB_NET_CDCETHER=m 1089CONFIG_USB_NET_CDCETHER=m
1090# CONFIG_USB_NET_CDC_EEM is not set
1039# CONFIG_USB_NET_DM9601 is not set 1091# CONFIG_USB_NET_DM9601 is not set
1040# CONFIG_USB_NET_SMSC95XX is not set 1092# CONFIG_USB_NET_SMSC95XX is not set
1041# CONFIG_USB_NET_GL620A is not set 1093# CONFIG_USB_NET_GL620A is not set
@@ -1099,7 +1151,7 @@ CONFIG_INPUT_KEYBOARD=y
1099CONFIG_INPUT_MOUSE=y 1151CONFIG_INPUT_MOUSE=y
1100# CONFIG_MOUSE_PS2 is not set 1152# CONFIG_MOUSE_PS2 is not set
1101# CONFIG_MOUSE_SERIAL is not set 1153# CONFIG_MOUSE_SERIAL is not set
1102# CONFIG_MOUSE_APPLETOUCH is not set 1154CONFIG_MOUSE_APPLETOUCH=y
1103# CONFIG_MOUSE_BCM5974 is not set 1155# CONFIG_MOUSE_BCM5974 is not set
1104# CONFIG_MOUSE_VSXXXAA is not set 1156# CONFIG_MOUSE_VSXXXAA is not set
1105# CONFIG_INPUT_JOYSTICK is not set 1157# CONFIG_INPUT_JOYSTICK is not set
@@ -1150,10 +1202,13 @@ CONFIG_SERIAL_PMACZILOG_TTYS=y
1150# CONFIG_SERIAL_JSM is not set 1202# CONFIG_SERIAL_JSM is not set
1151# CONFIG_SERIAL_OF_PLATFORM is not set 1203# CONFIG_SERIAL_OF_PLATFORM is not set
1152CONFIG_UNIX98_PTYS=y 1204CONFIG_UNIX98_PTYS=y
1205# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1153CONFIG_LEGACY_PTYS=y 1206CONFIG_LEGACY_PTYS=y
1154CONFIG_LEGACY_PTY_COUNT=256 1207CONFIG_LEGACY_PTY_COUNT=256
1208# CONFIG_HVC_UDBG is not set
1155# CONFIG_IPMI_HANDLER is not set 1209# CONFIG_IPMI_HANDLER is not set
1156CONFIG_HW_RANDOM=m 1210CONFIG_HW_RANDOM=m
1211# CONFIG_HW_RANDOM_TIMERIOMEM is not set
1157CONFIG_NVRAM=y 1212CONFIG_NVRAM=y
1158CONFIG_GEN_RTC=y 1213CONFIG_GEN_RTC=y
1159# CONFIG_GEN_RTC_X is not set 1214# CONFIG_GEN_RTC_X is not set
@@ -1232,12 +1287,9 @@ CONFIG_I2C_POWERMAC=y
1232# Miscellaneous I2C Chip support 1287# Miscellaneous I2C Chip support
1233# 1288#
1234# CONFIG_DS1682 is not set 1289# CONFIG_DS1682 is not set
1235# CONFIG_EEPROM_AT24 is not set
1236# CONFIG_EEPROM_LEGACY is not set
1237# CONFIG_SENSORS_PCF8574 is not set 1290# CONFIG_SENSORS_PCF8574 is not set
1238# CONFIG_PCF8575 is not set 1291# CONFIG_PCF8575 is not set
1239# CONFIG_SENSORS_PCA9539 is not set 1292# CONFIG_SENSORS_PCA9539 is not set
1240# CONFIG_SENSORS_PCF8591 is not set
1241# CONFIG_SENSORS_MAX6875 is not set 1293# CONFIG_SENSORS_MAX6875 is not set
1242# CONFIG_SENSORS_TSL2550 is not set 1294# CONFIG_SENSORS_TSL2550 is not set
1243# CONFIG_I2C_DEBUG_CORE is not set 1295# CONFIG_I2C_DEBUG_CORE is not set
@@ -1259,11 +1311,11 @@ CONFIG_BATTERY_PMU=y
1259# CONFIG_THERMAL is not set 1311# CONFIG_THERMAL is not set
1260# CONFIG_THERMAL_HWMON is not set 1312# CONFIG_THERMAL_HWMON is not set
1261# CONFIG_WATCHDOG is not set 1313# CONFIG_WATCHDOG is not set
1314CONFIG_SSB_POSSIBLE=y
1262 1315
1263# 1316#
1264# Sonics Silicon Backplane 1317# Sonics Silicon Backplane
1265# 1318#
1266CONFIG_SSB_POSSIBLE=y
1267CONFIG_SSB=m 1319CONFIG_SSB=m
1268CONFIG_SSB_SPROM=y 1320CONFIG_SSB_SPROM=y
1269CONFIG_SSB_PCIHOST_POSSIBLE=y 1321CONFIG_SSB_PCIHOST_POSSIBLE=y
@@ -1281,18 +1333,13 @@ CONFIG_SSB_DRIVER_PCICORE=y
1281# CONFIG_MFD_CORE is not set 1333# CONFIG_MFD_CORE is not set
1282# CONFIG_MFD_SM501 is not set 1334# CONFIG_MFD_SM501 is not set
1283# CONFIG_HTC_PASIC3 is not set 1335# CONFIG_HTC_PASIC3 is not set
1336# CONFIG_TWL4030_CORE is not set
1284# CONFIG_MFD_TMIO is not set 1337# CONFIG_MFD_TMIO is not set
1285# CONFIG_PMIC_DA903X is not set 1338# CONFIG_PMIC_DA903X is not set
1286# CONFIG_MFD_WM8400 is not set 1339# CONFIG_MFD_WM8400 is not set
1287# CONFIG_MFD_WM8350_I2C is not set 1340# CONFIG_MFD_WM8350_I2C is not set
1288 1341# CONFIG_MFD_PCF50633 is not set
1289#
1290# Voltage and Current regulators
1291#
1292# CONFIG_REGULATOR is not set 1342# CONFIG_REGULATOR is not set
1293# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1294# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1295# CONFIG_REGULATOR_BQ24022 is not set
1296 1343
1297# 1344#
1298# Multimedia devices 1345# Multimedia devices
@@ -1390,6 +1437,7 @@ CONFIG_FB_ATY_BACKLIGHT=y
1390# CONFIG_FB_KYRO is not set 1437# CONFIG_FB_KYRO is not set
1391CONFIG_FB_3DFX=y 1438CONFIG_FB_3DFX=y
1392# CONFIG_FB_3DFX_ACCEL is not set 1439# CONFIG_FB_3DFX_ACCEL is not set
1440CONFIG_FB_3DFX_I2C=y
1393# CONFIG_FB_VOODOO1 is not set 1441# CONFIG_FB_VOODOO1 is not set
1394# CONFIG_FB_VT8623 is not set 1442# CONFIG_FB_VT8623 is not set
1395# CONFIG_FB_TRIDENT is not set 1443# CONFIG_FB_TRIDENT is not set
@@ -1399,12 +1447,14 @@ CONFIG_FB_3DFX=y
1399# CONFIG_FB_IBM_GXT4500 is not set 1447# CONFIG_FB_IBM_GXT4500 is not set
1400# CONFIG_FB_VIRTUAL is not set 1448# CONFIG_FB_VIRTUAL is not set
1401# CONFIG_FB_METRONOME is not set 1449# CONFIG_FB_METRONOME is not set
1450# CONFIG_FB_MB862XX is not set
1451# CONFIG_FB_BROADSHEET is not set
1402CONFIG_BACKLIGHT_LCD_SUPPORT=y 1452CONFIG_BACKLIGHT_LCD_SUPPORT=y
1403CONFIG_LCD_CLASS_DEVICE=m 1453CONFIG_LCD_CLASS_DEVICE=m
1404# CONFIG_LCD_ILI9320 is not set 1454# CONFIG_LCD_ILI9320 is not set
1405# CONFIG_LCD_PLATFORM is not set 1455# CONFIG_LCD_PLATFORM is not set
1406CONFIG_BACKLIGHT_CLASS_DEVICE=y 1456CONFIG_BACKLIGHT_CLASS_DEVICE=y
1407# CONFIG_BACKLIGHT_CORGI is not set 1457CONFIG_BACKLIGHT_GENERIC=y
1408 1458
1409# 1459#
1410# Display device support 1460# Display device support
@@ -1444,11 +1494,13 @@ CONFIG_SND_MIXER_OSS=m
1444CONFIG_SND_PCM_OSS=m 1494CONFIG_SND_PCM_OSS=m
1445CONFIG_SND_PCM_OSS_PLUGINS=y 1495CONFIG_SND_PCM_OSS_PLUGINS=y
1446CONFIG_SND_SEQUENCER_OSS=y 1496CONFIG_SND_SEQUENCER_OSS=y
1497# CONFIG_SND_HRTIMER is not set
1447# CONFIG_SND_DYNAMIC_MINORS is not set 1498# CONFIG_SND_DYNAMIC_MINORS is not set
1448CONFIG_SND_SUPPORT_OLD_API=y 1499CONFIG_SND_SUPPORT_OLD_API=y
1449CONFIG_SND_VERBOSE_PROCFS=y 1500CONFIG_SND_VERBOSE_PROCFS=y
1450# CONFIG_SND_VERBOSE_PRINTK is not set 1501# CONFIG_SND_VERBOSE_PRINTK is not set
1451# CONFIG_SND_DEBUG is not set 1502# CONFIG_SND_DEBUG is not set
1503CONFIG_SND_VMASTER=y
1452CONFIG_SND_DRIVERS=y 1504CONFIG_SND_DRIVERS=y
1453CONFIG_SND_DUMMY=m 1505CONFIG_SND_DUMMY=m
1454# CONFIG_SND_VIRMIDI is not set 1506# CONFIG_SND_VIRMIDI is not set
@@ -1486,6 +1538,8 @@ CONFIG_SND_PCI=y
1486# CONFIG_SND_INDIGO is not set 1538# CONFIG_SND_INDIGO is not set
1487# CONFIG_SND_INDIGOIO is not set 1539# CONFIG_SND_INDIGOIO is not set
1488# CONFIG_SND_INDIGODJ is not set 1540# CONFIG_SND_INDIGODJ is not set
1541# CONFIG_SND_INDIGOIOX is not set
1542# CONFIG_SND_INDIGODJX is not set
1489# CONFIG_SND_EMU10K1 is not set 1543# CONFIG_SND_EMU10K1 is not set
1490# CONFIG_SND_EMU10K1X is not set 1544# CONFIG_SND_EMU10K1X is not set
1491# CONFIG_SND_ENS1370 is not set 1545# CONFIG_SND_ENS1370 is not set
@@ -1551,28 +1605,31 @@ CONFIG_USB_HID=y
1551# 1605#
1552# Special HID drivers 1606# Special HID drivers
1553# 1607#
1554CONFIG_HID_COMPAT=y
1555CONFIG_HID_A4TECH=y 1608CONFIG_HID_A4TECH=y
1556CONFIG_HID_APPLE=y 1609CONFIG_HID_APPLE=y
1557CONFIG_HID_BELKIN=y 1610CONFIG_HID_BELKIN=y
1558CONFIG_HID_BRIGHT=y
1559CONFIG_HID_CHERRY=y 1611CONFIG_HID_CHERRY=y
1560CONFIG_HID_CHICONY=y 1612CONFIG_HID_CHICONY=y
1561CONFIG_HID_CYPRESS=y 1613CONFIG_HID_CYPRESS=y
1562CONFIG_HID_DELL=y 1614# CONFIG_DRAGONRISE_FF is not set
1563CONFIG_HID_EZKEY=y 1615CONFIG_HID_EZKEY=y
1616CONFIG_HID_KYE=y
1564CONFIG_HID_GYRATION=y 1617CONFIG_HID_GYRATION=y
1618CONFIG_HID_KENSINGTON=y
1565CONFIG_HID_LOGITECH=y 1619CONFIG_HID_LOGITECH=y
1566# CONFIG_LOGITECH_FF is not set 1620# CONFIG_LOGITECH_FF is not set
1567# CONFIG_LOGIRUMBLEPAD2_FF is not set 1621# CONFIG_LOGIRUMBLEPAD2_FF is not set
1568CONFIG_HID_MICROSOFT=y 1622CONFIG_HID_MICROSOFT=y
1569CONFIG_HID_MONTEREY=y 1623CONFIG_HID_MONTEREY=y
1624CONFIG_HID_NTRIG=y
1570CONFIG_HID_PANTHERLORD=y 1625CONFIG_HID_PANTHERLORD=y
1571# CONFIG_PANTHERLORD_FF is not set 1626# CONFIG_PANTHERLORD_FF is not set
1572CONFIG_HID_PETALYNX=y 1627CONFIG_HID_PETALYNX=y
1573CONFIG_HID_SAMSUNG=y 1628CONFIG_HID_SAMSUNG=y
1574CONFIG_HID_SONY=y 1629CONFIG_HID_SONY=y
1575CONFIG_HID_SUNPLUS=y 1630CONFIG_HID_SUNPLUS=y
1631# CONFIG_GREENASIA_FF is not set
1632CONFIG_HID_TOPSEED=y
1576# CONFIG_THRUSTMASTER_FF is not set 1633# CONFIG_THRUSTMASTER_FF is not set
1577# CONFIG_ZEROPLUS_FF is not set 1634# CONFIG_ZEROPLUS_FF is not set
1578CONFIG_USB_SUPPORT=y 1635CONFIG_USB_SUPPORT=y
@@ -1603,6 +1660,7 @@ CONFIG_USB_EHCI_HCD=m
1603CONFIG_USB_EHCI_ROOT_HUB_TT=y 1660CONFIG_USB_EHCI_ROOT_HUB_TT=y
1604# CONFIG_USB_EHCI_TT_NEWSCHED is not set 1661# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1605# CONFIG_USB_EHCI_HCD_PPC_OF is not set 1662# CONFIG_USB_EHCI_HCD_PPC_OF is not set
1663# CONFIG_USB_OXU210HP_HCD is not set
1606# CONFIG_USB_ISP116X_HCD is not set 1664# CONFIG_USB_ISP116X_HCD is not set
1607# CONFIG_USB_ISP1760_HCD is not set 1665# CONFIG_USB_ISP1760_HCD is not set
1608CONFIG_USB_OHCI_HCD=y 1666CONFIG_USB_OHCI_HCD=y
@@ -1625,24 +1683,23 @@ CONFIG_USB_PRINTER=m
1625# CONFIG_USB_TMC is not set 1683# CONFIG_USB_TMC is not set
1626 1684
1627# 1685#
1628# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1686# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1629# 1687#
1630 1688
1631# 1689#
1632# may also be needed; see USB_STORAGE Help for more information 1690# also be needed; see USB_STORAGE Help for more info
1633# 1691#
1634CONFIG_USB_STORAGE=m 1692CONFIG_USB_STORAGE=m
1635# CONFIG_USB_STORAGE_DEBUG is not set 1693# CONFIG_USB_STORAGE_DEBUG is not set
1636# CONFIG_USB_STORAGE_DATAFAB is not set 1694# CONFIG_USB_STORAGE_DATAFAB is not set
1637# CONFIG_USB_STORAGE_FREECOM is not set 1695# CONFIG_USB_STORAGE_FREECOM is not set
1638# CONFIG_USB_STORAGE_ISD200 is not set 1696# CONFIG_USB_STORAGE_ISD200 is not set
1639# CONFIG_USB_STORAGE_DPCM is not set
1640# CONFIG_USB_STORAGE_USBAT is not set 1697# CONFIG_USB_STORAGE_USBAT is not set
1641# CONFIG_USB_STORAGE_SDDR09 is not set 1698# CONFIG_USB_STORAGE_SDDR09 is not set
1642# CONFIG_USB_STORAGE_SDDR55 is not set 1699# CONFIG_USB_STORAGE_SDDR55 is not set
1643# CONFIG_USB_STORAGE_JUMPSHOT is not set 1700# CONFIG_USB_STORAGE_JUMPSHOT is not set
1644# CONFIG_USB_STORAGE_ALAUDA is not set 1701# CONFIG_USB_STORAGE_ALAUDA is not set
1645CONFIG_USB_STORAGE_ONETOUCH=y 1702CONFIG_USB_STORAGE_ONETOUCH=m
1646# CONFIG_USB_STORAGE_KARMA is not set 1703# CONFIG_USB_STORAGE_KARMA is not set
1647# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1704# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1648# CONFIG_USB_LIBUSUAL is not set 1705# CONFIG_USB_LIBUSUAL is not set
@@ -1665,7 +1722,7 @@ CONFIG_USB_EZUSB=y
1665# CONFIG_USB_SERIAL_CH341 is not set 1722# CONFIG_USB_SERIAL_CH341 is not set
1666# CONFIG_USB_SERIAL_WHITEHEAT is not set 1723# CONFIG_USB_SERIAL_WHITEHEAT is not set
1667# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set 1724# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1668# CONFIG_USB_SERIAL_CP2101 is not set 1725# CONFIG_USB_SERIAL_CP210X is not set
1669# CONFIG_USB_SERIAL_CYPRESS_M8 is not set 1726# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1670# CONFIG_USB_SERIAL_EMPEG is not set 1727# CONFIG_USB_SERIAL_EMPEG is not set
1671# CONFIG_USB_SERIAL_FTDI_SIO is not set 1728# CONFIG_USB_SERIAL_FTDI_SIO is not set
@@ -1701,15 +1758,19 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
1701# CONFIG_USB_SERIAL_NAVMAN is not set 1758# CONFIG_USB_SERIAL_NAVMAN is not set
1702# CONFIG_USB_SERIAL_PL2303 is not set 1759# CONFIG_USB_SERIAL_PL2303 is not set
1703# CONFIG_USB_SERIAL_OTI6858 is not set 1760# CONFIG_USB_SERIAL_OTI6858 is not set
1761# CONFIG_USB_SERIAL_QUALCOMM is not set
1704# CONFIG_USB_SERIAL_SPCP8X5 is not set 1762# CONFIG_USB_SERIAL_SPCP8X5 is not set
1705# CONFIG_USB_SERIAL_HP4X is not set 1763# CONFIG_USB_SERIAL_HP4X is not set
1706# CONFIG_USB_SERIAL_SAFE is not set 1764# CONFIG_USB_SERIAL_SAFE is not set
1765# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1707# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set 1766# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1767# CONFIG_USB_SERIAL_SYMBOL is not set
1708# CONFIG_USB_SERIAL_TI is not set 1768# CONFIG_USB_SERIAL_TI is not set
1709# CONFIG_USB_SERIAL_CYBERJACK is not set 1769# CONFIG_USB_SERIAL_CYBERJACK is not set
1710# CONFIG_USB_SERIAL_XIRCOM is not set 1770# CONFIG_USB_SERIAL_XIRCOM is not set
1711# CONFIG_USB_SERIAL_OPTION is not set 1771# CONFIG_USB_SERIAL_OPTION is not set
1712# CONFIG_USB_SERIAL_OMNINET is not set 1772# CONFIG_USB_SERIAL_OMNINET is not set
1773# CONFIG_USB_SERIAL_OPTICON is not set
1713# CONFIG_USB_SERIAL_DEBUG is not set 1774# CONFIG_USB_SERIAL_DEBUG is not set
1714 1775
1715# 1776#
@@ -1726,7 +1787,6 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
1726# CONFIG_USB_LED is not set 1787# CONFIG_USB_LED is not set
1727# CONFIG_USB_CYPRESS_CY7C63 is not set 1788# CONFIG_USB_CYPRESS_CY7C63 is not set
1728# CONFIG_USB_CYTHERM is not set 1789# CONFIG_USB_CYTHERM is not set
1729# CONFIG_USB_PHIDGET is not set
1730# CONFIG_USB_IDMOUSE is not set 1790# CONFIG_USB_IDMOUSE is not set
1731# CONFIG_USB_FTDI_ELAN is not set 1791# CONFIG_USB_FTDI_ELAN is not set
1732CONFIG_USB_APPLEDISPLAY=m 1792CONFIG_USB_APPLEDISPLAY=m
@@ -1738,6 +1798,11 @@ CONFIG_USB_APPLEDISPLAY=m
1738# CONFIG_USB_ISIGHTFW is not set 1798# CONFIG_USB_ISIGHTFW is not set
1739# CONFIG_USB_VST is not set 1799# CONFIG_USB_VST is not set
1740# CONFIG_USB_GADGET is not set 1800# CONFIG_USB_GADGET is not set
1801
1802#
1803# OTG and related infrastructure
1804#
1805# CONFIG_NOP_USB_XCEIV is not set
1741# CONFIG_UWB is not set 1806# CONFIG_UWB is not set
1742# CONFIG_MMC is not set 1807# CONFIG_MMC is not set
1743# CONFIG_MEMSTICK is not set 1808# CONFIG_MEMSTICK is not set
@@ -1748,7 +1813,9 @@ CONFIG_LEDS_CLASS=y
1748# LED drivers 1813# LED drivers
1749# 1814#
1750# CONFIG_LEDS_PCA9532 is not set 1815# CONFIG_LEDS_PCA9532 is not set
1816# CONFIG_LEDS_LP5521 is not set
1751# CONFIG_LEDS_PCA955X is not set 1817# CONFIG_LEDS_PCA955X is not set
1818# CONFIG_LEDS_BD2802 is not set
1752 1819
1753# 1820#
1754# LED Triggers 1821# LED Triggers
@@ -1759,11 +1826,16 @@ CONFIG_LEDS_TRIGGER_IDE_DISK=y
1759# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set 1826# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
1760# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 1827# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1761CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 1828CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1829
1830#
1831# iptables trigger is under Netfilter config (LED target)
1832#
1762# CONFIG_ACCESSIBILITY is not set 1833# CONFIG_ACCESSIBILITY is not set
1763# CONFIG_INFINIBAND is not set 1834# CONFIG_INFINIBAND is not set
1764# CONFIG_EDAC is not set 1835# CONFIG_EDAC is not set
1765# CONFIG_RTC_CLASS is not set 1836# CONFIG_RTC_CLASS is not set
1766# CONFIG_DMADEVICES is not set 1837# CONFIG_DMADEVICES is not set
1838# CONFIG_AUXDISPLAY is not set
1767# CONFIG_UIO is not set 1839# CONFIG_UIO is not set
1768# CONFIG_STAGING is not set 1840# CONFIG_STAGING is not set
1769 1841
@@ -1774,6 +1846,7 @@ CONFIG_EXT2_FS=y
1774# CONFIG_EXT2_FS_XATTR is not set 1846# CONFIG_EXT2_FS_XATTR is not set
1775# CONFIG_EXT2_FS_XIP is not set 1847# CONFIG_EXT2_FS_XIP is not set
1776CONFIG_EXT3_FS=y 1848CONFIG_EXT3_FS=y
1849# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1777CONFIG_EXT3_FS_XATTR=y 1850CONFIG_EXT3_FS_XATTR=y
1778CONFIG_EXT3_FS_POSIX_ACL=y 1851CONFIG_EXT3_FS_POSIX_ACL=y
1779# CONFIG_EXT3_FS_SECURITY is not set 1852# CONFIG_EXT3_FS_SECURITY is not set
@@ -1783,7 +1856,9 @@ CONFIG_EXT4_FS_XATTR=y
1783# CONFIG_EXT4_FS_POSIX_ACL is not set 1856# CONFIG_EXT4_FS_POSIX_ACL is not set
1784# CONFIG_EXT4_FS_SECURITY is not set 1857# CONFIG_EXT4_FS_SECURITY is not set
1785CONFIG_JBD=y 1858CONFIG_JBD=y
1859# CONFIG_JBD_DEBUG is not set
1786CONFIG_JBD2=y 1860CONFIG_JBD2=y
1861# CONFIG_JBD2_DEBUG is not set
1787CONFIG_FS_MBCACHE=y 1862CONFIG_FS_MBCACHE=y
1788# CONFIG_REISERFS_FS is not set 1863# CONFIG_REISERFS_FS is not set
1789# CONFIG_JFS_FS is not set 1864# CONFIG_JFS_FS is not set
@@ -1792,6 +1867,7 @@ CONFIG_FILE_LOCKING=y
1792# CONFIG_XFS_FS is not set 1867# CONFIG_XFS_FS is not set
1793# CONFIG_GFS2_FS is not set 1868# CONFIG_GFS2_FS is not set
1794# CONFIG_OCFS2_FS is not set 1869# CONFIG_OCFS2_FS is not set
1870# CONFIG_BTRFS_FS is not set
1795CONFIG_DNOTIFY=y 1871CONFIG_DNOTIFY=y
1796CONFIG_INOTIFY=y 1872CONFIG_INOTIFY=y
1797CONFIG_INOTIFY_USER=y 1873CONFIG_INOTIFY_USER=y
@@ -1801,6 +1877,11 @@ CONFIG_AUTOFS4_FS=m
1801CONFIG_FUSE_FS=m 1877CONFIG_FUSE_FS=m
1802 1878
1803# 1879#
1880# Caches
1881#
1882# CONFIG_FSCACHE is not set
1883
1884#
1804# CD-ROM/DVD Filesystems 1885# CD-ROM/DVD Filesystems
1805# 1886#
1806CONFIG_ISO9660_FS=y 1887CONFIG_ISO9660_FS=y
@@ -1831,10 +1912,7 @@ CONFIG_TMPFS=y
1831# CONFIG_TMPFS_POSIX_ACL is not set 1912# CONFIG_TMPFS_POSIX_ACL is not set
1832# CONFIG_HUGETLB_PAGE is not set 1913# CONFIG_HUGETLB_PAGE is not set
1833# CONFIG_CONFIGFS_FS is not set 1914# CONFIG_CONFIGFS_FS is not set
1834 1915CONFIG_MISC_FILESYSTEMS=y
1835#
1836# Miscellaneous filesystems
1837#
1838# CONFIG_ADFS_FS is not set 1916# CONFIG_ADFS_FS is not set
1839# CONFIG_AFFS_FS is not set 1917# CONFIG_AFFS_FS is not set
1840CONFIG_HFS_FS=m 1918CONFIG_HFS_FS=m
@@ -1843,6 +1921,7 @@ CONFIG_HFSPLUS_FS=m
1843# CONFIG_BFS_FS is not set 1921# CONFIG_BFS_FS is not set
1844# CONFIG_EFS_FS is not set 1922# CONFIG_EFS_FS is not set
1845# CONFIG_CRAMFS is not set 1923# CONFIG_CRAMFS is not set
1924# CONFIG_SQUASHFS is not set
1846# CONFIG_VXFS_FS is not set 1925# CONFIG_VXFS_FS is not set
1847# CONFIG_MINIX_FS is not set 1926# CONFIG_MINIX_FS is not set
1848# CONFIG_OMFS_FS is not set 1927# CONFIG_OMFS_FS is not set
@@ -1851,6 +1930,7 @@ CONFIG_HFSPLUS_FS=m
1851# CONFIG_ROMFS_FS is not set 1930# CONFIG_ROMFS_FS is not set
1852# CONFIG_SYSV_FS is not set 1931# CONFIG_SYSV_FS is not set
1853# CONFIG_UFS_FS is not set 1932# CONFIG_UFS_FS is not set
1933# CONFIG_NILFS2_FS is not set
1854CONFIG_NETWORK_FILESYSTEMS=y 1934CONFIG_NETWORK_FILESYSTEMS=y
1855CONFIG_NFS_FS=y 1935CONFIG_NFS_FS=y
1856CONFIG_NFS_V3=y 1936CONFIG_NFS_V3=y
@@ -1868,7 +1948,6 @@ CONFIG_NFS_ACL_SUPPORT=y
1868CONFIG_NFS_COMMON=y 1948CONFIG_NFS_COMMON=y
1869CONFIG_SUNRPC=y 1949CONFIG_SUNRPC=y
1870CONFIG_SUNRPC_GSS=y 1950CONFIG_SUNRPC_GSS=y
1871# CONFIG_SUNRPC_REGISTER_V4 is not set
1872CONFIG_RPCSEC_GSS_KRB5=y 1951CONFIG_RPCSEC_GSS_KRB5=y
1873# CONFIG_RPCSEC_GSS_SPKM3 is not set 1952# CONFIG_RPCSEC_GSS_SPKM3 is not set
1874CONFIG_SMB_FS=m 1953CONFIG_SMB_FS=m
@@ -1940,11 +2019,13 @@ CONFIG_NLS_ISO8859_1=m
1940# CONFIG_NLS_KOI8_U is not set 2019# CONFIG_NLS_KOI8_U is not set
1941CONFIG_NLS_UTF8=m 2020CONFIG_NLS_UTF8=m
1942# CONFIG_DLM is not set 2021# CONFIG_DLM is not set
2022CONFIG_BINARY_PRINTF=y
1943 2023
1944# 2024#
1945# Library routines 2025# Library routines
1946# 2026#
1947CONFIG_BITREVERSE=y 2027CONFIG_BITREVERSE=y
2028CONFIG_GENERIC_FIND_LAST_BIT=y
1948CONFIG_CRC_CCITT=y 2029CONFIG_CRC_CCITT=y
1949CONFIG_CRC16=y 2030CONFIG_CRC16=y
1950CONFIG_CRC_T10DIF=y 2031CONFIG_CRC_T10DIF=y
@@ -1954,15 +2035,18 @@ CONFIG_CRC32=y
1954CONFIG_LIBCRC32C=m 2035CONFIG_LIBCRC32C=m
1955CONFIG_ZLIB_INFLATE=y 2036CONFIG_ZLIB_INFLATE=y
1956CONFIG_ZLIB_DEFLATE=y 2037CONFIG_ZLIB_DEFLATE=y
2038CONFIG_DECOMPRESS_GZIP=y
2039CONFIG_DECOMPRESS_BZIP2=y
2040CONFIG_DECOMPRESS_LZMA=y
1957CONFIG_TEXTSEARCH=y 2041CONFIG_TEXTSEARCH=y
1958CONFIG_TEXTSEARCH_KMP=m 2042CONFIG_TEXTSEARCH_KMP=m
1959CONFIG_TEXTSEARCH_BM=m 2043CONFIG_TEXTSEARCH_BM=m
1960CONFIG_TEXTSEARCH_FSM=m 2044CONFIG_TEXTSEARCH_FSM=m
1961CONFIG_PLIST=y
1962CONFIG_HAS_IOMEM=y 2045CONFIG_HAS_IOMEM=y
1963CONFIG_HAS_IOPORT=y 2046CONFIG_HAS_IOPORT=y
1964CONFIG_HAS_DMA=y 2047CONFIG_HAS_DMA=y
1965CONFIG_HAVE_LMB=y 2048CONFIG_HAVE_LMB=y
2049CONFIG_NLATTR=y
1966 2050
1967# 2051#
1968# Kernel hacking 2052# Kernel hacking
@@ -1973,13 +2057,16 @@ CONFIG_ENABLE_MUST_CHECK=y
1973CONFIG_FRAME_WARN=1024 2057CONFIG_FRAME_WARN=1024
1974CONFIG_MAGIC_SYSRQ=y 2058CONFIG_MAGIC_SYSRQ=y
1975# CONFIG_UNUSED_SYMBOLS is not set 2059# CONFIG_UNUSED_SYMBOLS is not set
1976# CONFIG_DEBUG_FS is not set 2060CONFIG_DEBUG_FS=y
1977# CONFIG_HEADERS_CHECK is not set 2061# CONFIG_HEADERS_CHECK is not set
1978CONFIG_DEBUG_KERNEL=y 2062CONFIG_DEBUG_KERNEL=y
1979# CONFIG_DEBUG_SHIRQ is not set 2063# CONFIG_DEBUG_SHIRQ is not set
1980CONFIG_DETECT_SOFTLOCKUP=y 2064CONFIG_DETECT_SOFTLOCKUP=y
1981# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 2065# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1982CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 2066CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
2067CONFIG_DETECT_HUNG_TASK=y
2068# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
2069CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1983CONFIG_SCHED_DEBUG=y 2070CONFIG_SCHED_DEBUG=y
1984CONFIG_SCHEDSTATS=y 2071CONFIG_SCHEDSTATS=y
1985# CONFIG_TIMER_STATS is not set 2072# CONFIG_TIMER_STATS is not set
@@ -1994,6 +2081,7 @@ CONFIG_SCHEDSTATS=y
1994# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 2081# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1995CONFIG_STACKTRACE=y 2082CONFIG_STACKTRACE=y
1996# CONFIG_DEBUG_KOBJECT is not set 2083# CONFIG_DEBUG_KOBJECT is not set
2084# CONFIG_DEBUG_HIGHMEM is not set
1997CONFIG_DEBUG_BUGVERBOSE=y 2085CONFIG_DEBUG_BUGVERBOSE=y
1998# CONFIG_DEBUG_INFO is not set 2086# CONFIG_DEBUG_INFO is not set
1999# CONFIG_DEBUG_VM is not set 2087# CONFIG_DEBUG_VM is not set
@@ -2001,6 +2089,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
2001CONFIG_DEBUG_MEMORY_INIT=y 2089CONFIG_DEBUG_MEMORY_INIT=y
2002# CONFIG_DEBUG_LIST is not set 2090# CONFIG_DEBUG_LIST is not set
2003# CONFIG_DEBUG_SG is not set 2091# CONFIG_DEBUG_SG is not set
2092# CONFIG_DEBUG_NOTIFIERS is not set
2004# CONFIG_BOOT_PRINTK_DELAY is not set 2093# CONFIG_BOOT_PRINTK_DELAY is not set
2005# CONFIG_RCU_TORTURE_TEST is not set 2094# CONFIG_RCU_TORTURE_TEST is not set
2006# CONFIG_RCU_CPU_STALL_DETECTOR is not set 2095# CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -2009,7 +2098,14 @@ CONFIG_DEBUG_MEMORY_INIT=y
2009# CONFIG_FAULT_INJECTION is not set 2098# CONFIG_FAULT_INJECTION is not set
2010CONFIG_LATENCYTOP=y 2099CONFIG_LATENCYTOP=y
2011CONFIG_SYSCTL_SYSCALL_CHECK=y 2100CONFIG_SYSCTL_SYSCALL_CHECK=y
2101CONFIG_NOP_TRACER=y
2012CONFIG_HAVE_FUNCTION_TRACER=y 2102CONFIG_HAVE_FUNCTION_TRACER=y
2103CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
2104CONFIG_HAVE_DYNAMIC_FTRACE=y
2105CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
2106CONFIG_RING_BUFFER=y
2107CONFIG_TRACING=y
2108CONFIG_TRACING_SUPPORT=y
2013 2109
2014# 2110#
2015# Tracers 2111# Tracers
@@ -2017,12 +2113,19 @@ CONFIG_HAVE_FUNCTION_TRACER=y
2017# CONFIG_FUNCTION_TRACER is not set 2113# CONFIG_FUNCTION_TRACER is not set
2018# CONFIG_SCHED_TRACER is not set 2114# CONFIG_SCHED_TRACER is not set
2019# CONFIG_CONTEXT_SWITCH_TRACER is not set 2115# CONFIG_CONTEXT_SWITCH_TRACER is not set
2116# CONFIG_EVENT_TRACER is not set
2020# CONFIG_BOOT_TRACER is not set 2117# CONFIG_BOOT_TRACER is not set
2118# CONFIG_TRACE_BRANCH_PROFILING is not set
2021# CONFIG_STACK_TRACER is not set 2119# CONFIG_STACK_TRACER is not set
2022# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 2120# CONFIG_KMEMTRACE is not set
2121# CONFIG_WORKQUEUE_TRACER is not set
2122# CONFIG_BLK_DEV_IO_TRACE is not set
2123# CONFIG_FTRACE_STARTUP_TEST is not set
2124# CONFIG_DYNAMIC_DEBUG is not set
2023# CONFIG_SAMPLES is not set 2125# CONFIG_SAMPLES is not set
2024CONFIG_HAVE_ARCH_KGDB=y 2126CONFIG_HAVE_ARCH_KGDB=y
2025# CONFIG_KGDB is not set 2127# CONFIG_KGDB is not set
2128CONFIG_PRINT_STACK_DEPTH=64
2026# CONFIG_DEBUG_STACKOVERFLOW is not set 2129# CONFIG_DEBUG_STACKOVERFLOW is not set
2027# CONFIG_DEBUG_STACK_USAGE is not set 2130# CONFIG_DEBUG_STACK_USAGE is not set
2028# CONFIG_CODE_PATCHING_SELFTEST is not set 2131# CONFIG_CODE_PATCHING_SELFTEST is not set
@@ -2033,6 +2136,7 @@ CONFIG_XMON_DEFAULT=y
2033CONFIG_XMON_DISASSEMBLY=y 2136CONFIG_XMON_DISASSEMBLY=y
2034CONFIG_DEBUGGER=y 2137CONFIG_DEBUGGER=y
2035CONFIG_IRQSTACKS=y 2138CONFIG_IRQSTACKS=y
2139# CONFIG_VIRQ_DEBUG is not set
2036# CONFIG_BDI_SWITCH is not set 2140# CONFIG_BDI_SWITCH is not set
2037CONFIG_BOOTX_TEXT=y 2141CONFIG_BOOTX_TEXT=y
2038# CONFIG_PPC_EARLY_DEBUG is not set 2142# CONFIG_PPC_EARLY_DEBUG is not set
@@ -2051,13 +2155,20 @@ CONFIG_CRYPTO=y
2051# 2155#
2052# CONFIG_CRYPTO_FIPS is not set 2156# CONFIG_CRYPTO_FIPS is not set
2053CONFIG_CRYPTO_ALGAPI=y 2157CONFIG_CRYPTO_ALGAPI=y
2158CONFIG_CRYPTO_ALGAPI2=y
2054CONFIG_CRYPTO_AEAD=y 2159CONFIG_CRYPTO_AEAD=y
2160CONFIG_CRYPTO_AEAD2=y
2055CONFIG_CRYPTO_BLKCIPHER=y 2161CONFIG_CRYPTO_BLKCIPHER=y
2162CONFIG_CRYPTO_BLKCIPHER2=y
2056CONFIG_CRYPTO_HASH=y 2163CONFIG_CRYPTO_HASH=y
2057CONFIG_CRYPTO_RNG=y 2164CONFIG_CRYPTO_HASH2=y
2165CONFIG_CRYPTO_RNG2=y
2166CONFIG_CRYPTO_PCOMP=y
2058CONFIG_CRYPTO_MANAGER=y 2167CONFIG_CRYPTO_MANAGER=y
2168CONFIG_CRYPTO_MANAGER2=y
2059# CONFIG_CRYPTO_GF128MUL is not set 2169# CONFIG_CRYPTO_GF128MUL is not set
2060CONFIG_CRYPTO_NULL=m 2170CONFIG_CRYPTO_NULL=m
2171CONFIG_CRYPTO_WORKQUEUE=y
2061# CONFIG_CRYPTO_CRYPTD is not set 2172# CONFIG_CRYPTO_CRYPTD is not set
2062CONFIG_CRYPTO_AUTHENC=y 2173CONFIG_CRYPTO_AUTHENC=y
2063# CONFIG_CRYPTO_TEST is not set 2174# CONFIG_CRYPTO_TEST is not set
@@ -2127,6 +2238,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
2127# Compression 2238# Compression
2128# 2239#
2129CONFIG_CRYPTO_DEFLATE=m 2240CONFIG_CRYPTO_DEFLATE=m
2241# CONFIG_CRYPTO_ZLIB is not set
2130# CONFIG_CRYPTO_LZO is not set 2242# CONFIG_CRYPTO_LZO is not set
2131 2243
2132# 2244#
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index ac14f5245d2a..e28e65e7a0e1 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -1,13 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc8 3# Linux kernel version: 2.6.30-rc5
4# Fri Mar 13 09:28:45 2009 4# Fri May 15 10:37:00 2009
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
8# 8#
9# Processor support 9# Processor support
10# 10#
11CONFIG_PPC_BOOK3S=y
11# CONFIG_POWER4_ONLY is not set 12# CONFIG_POWER4_ONLY is not set
12CONFIG_POWER3=y 13CONFIG_POWER3=y
13CONFIG_POWER4=y 14CONFIG_POWER4=y
@@ -55,9 +56,11 @@ CONFIG_OF=y
55# CONFIG_GENERIC_TBSYNC is not set 56# CONFIG_GENERIC_TBSYNC is not set
56CONFIG_AUDIT_ARCH=y 57CONFIG_AUDIT_ARCH=y
57CONFIG_GENERIC_BUG=y 58CONFIG_GENERIC_BUG=y
59CONFIG_DTC=y
58# CONFIG_DEFAULT_UIMAGE is not set 60# CONFIG_DEFAULT_UIMAGE is not set
59# CONFIG_PPC_DCR_NATIVE is not set 61# CONFIG_PPC_DCR_NATIVE is not set
60# CONFIG_PPC_DCR_MMIO is not set 62# CONFIG_PPC_DCR_MMIO is not set
63CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 64CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
62 65
63# 66#
@@ -72,6 +75,7 @@ CONFIG_SWAP=y
72CONFIG_SYSVIPC=y 75CONFIG_SYSVIPC=y
73CONFIG_SYSVIPC_SYSCTL=y 76CONFIG_SYSVIPC_SYSCTL=y
74CONFIG_POSIX_MQUEUE=y 77CONFIG_POSIX_MQUEUE=y
78CONFIG_POSIX_MQUEUE_SYSCTL=y
75# CONFIG_BSD_PROCESS_ACCT is not set 79# CONFIG_BSD_PROCESS_ACCT is not set
76# CONFIG_TASKSTATS is not set 80# CONFIG_TASKSTATS is not set
77# CONFIG_AUDIT is not set 81# CONFIG_AUDIT is not set
@@ -88,8 +92,7 @@ CONFIG_CLASSIC_RCU=y
88CONFIG_LOG_BUF_SHIFT=17 92CONFIG_LOG_BUF_SHIFT=17
89# CONFIG_GROUP_SCHED is not set 93# CONFIG_GROUP_SCHED is not set
90# CONFIG_CGROUPS is not set 94# CONFIG_CGROUPS is not set
91CONFIG_SYSFS_DEPRECATED=y 95# CONFIG_SYSFS_DEPRECATED_V2 is not set
92CONFIG_SYSFS_DEPRECATED_V2=y
93# CONFIG_RELAY is not set 96# CONFIG_RELAY is not set
94CONFIG_NAMESPACES=y 97CONFIG_NAMESPACES=y
95# CONFIG_UTS_NS is not set 98# CONFIG_UTS_NS is not set
@@ -99,6 +102,9 @@ CONFIG_NAMESPACES=y
99# CONFIG_NET_NS is not set 102# CONFIG_NET_NS is not set
100CONFIG_BLK_DEV_INITRD=y 103CONFIG_BLK_DEV_INITRD=y
101CONFIG_INITRAMFS_SOURCE="" 104CONFIG_INITRAMFS_SOURCE=""
105CONFIG_RD_GZIP=y
106# CONFIG_RD_BZIP2 is not set
107# CONFIG_RD_LZMA is not set
102CONFIG_CC_OPTIMIZE_FOR_SIZE=y 108CONFIG_CC_OPTIMIZE_FOR_SIZE=y
103CONFIG_SYSCTL=y 109CONFIG_SYSCTL=y
104CONFIG_ANON_INODES=y 110CONFIG_ANON_INODES=y
@@ -107,6 +113,7 @@ CONFIG_SYSCTL_SYSCALL=y
107CONFIG_KALLSYMS=y 113CONFIG_KALLSYMS=y
108CONFIG_KALLSYMS_ALL=y 114CONFIG_KALLSYMS_ALL=y
109CONFIG_KALLSYMS_EXTRA_PASS=y 115CONFIG_KALLSYMS_EXTRA_PASS=y
116# CONFIG_STRIP_ASM_SYMS is not set
110CONFIG_HOTPLUG=y 117CONFIG_HOTPLUG=y
111CONFIG_PRINTK=y 118CONFIG_PRINTK=y
112CONFIG_BUG=y 119CONFIG_BUG=y
@@ -138,6 +145,7 @@ CONFIG_HAVE_KRETPROBES=y
138CONFIG_HAVE_ARCH_TRACEHOOK=y 145CONFIG_HAVE_ARCH_TRACEHOOK=y
139CONFIG_HAVE_DMA_ATTRS=y 146CONFIG_HAVE_DMA_ATTRS=y
140CONFIG_USE_GENERIC_SMP_HELPERS=y 147CONFIG_USE_GENERIC_SMP_HELPERS=y
148# CONFIG_SLOW_WORK is not set
141# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 149# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
142CONFIG_SLABINFO=y 150CONFIG_SLABINFO=y
143CONFIG_RT_MUTEXES=y 151CONFIG_RT_MUTEXES=y
@@ -150,7 +158,6 @@ CONFIG_MODULE_UNLOAD=y
150# CONFIG_MODULE_SRCVERSION_ALL is not set 158# CONFIG_MODULE_SRCVERSION_ALL is not set
151CONFIG_STOP_MACHINE=y 159CONFIG_STOP_MACHINE=y
152CONFIG_BLOCK=y 160CONFIG_BLOCK=y
153# CONFIG_BLK_DEV_IO_TRACE is not set
154CONFIG_BLK_DEV_BSG=y 161CONFIG_BLK_DEV_BSG=y
155# CONFIG_BLK_DEV_INTEGRITY is not set 162# CONFIG_BLK_DEV_INTEGRITY is not set
156CONFIG_BLOCK_COMPAT=y 163CONFIG_BLOCK_COMPAT=y
@@ -172,7 +179,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
172# 179#
173# Platform support 180# Platform support
174# 181#
175CONFIG_PPC_MULTIPLATFORM=y
176# CONFIG_PPC_PSERIES is not set 182# CONFIG_PPC_PSERIES is not set
177# CONFIG_PPC_ISERIES is not set 183# CONFIG_PPC_ISERIES is not set
178# CONFIG_PPC_PMAC is not set 184# CONFIG_PPC_PMAC is not set
@@ -209,6 +215,7 @@ CONFIG_SPU_FS_64K_LS=y
209# CONFIG_SPU_TRACE is not set 215# CONFIG_SPU_TRACE is not set
210CONFIG_SPU_BASE=y 216CONFIG_SPU_BASE=y
211# CONFIG_PQ2ADS is not set 217# CONFIG_PQ2ADS is not set
218# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
212# CONFIG_IPIC is not set 219# CONFIG_IPIC is not set
213# CONFIG_MPIC is not set 220# CONFIG_MPIC is not set
214# CONFIG_MPIC_WEIRD is not set 221# CONFIG_MPIC_WEIRD is not set
@@ -279,11 +286,14 @@ CONFIG_PHYS_ADDR_T_64BIT=y
279CONFIG_ZONE_DMA_FLAG=1 286CONFIG_ZONE_DMA_FLAG=1
280CONFIG_BOUNCE=y 287CONFIG_BOUNCE=y
281CONFIG_UNEVICTABLE_LRU=y 288CONFIG_UNEVICTABLE_LRU=y
289CONFIG_HAVE_MLOCK=y
290CONFIG_HAVE_MLOCKED_PAGE_BIT=y
282CONFIG_ARCH_MEMORY_PROBE=y 291CONFIG_ARCH_MEMORY_PROBE=y
283CONFIG_PPC_HAS_HASH_64K=y 292CONFIG_PPC_HAS_HASH_64K=y
284CONFIG_PPC_4K_PAGES=y 293CONFIG_PPC_4K_PAGES=y
285# CONFIG_PPC_16K_PAGES is not set 294# CONFIG_PPC_16K_PAGES is not set
286# CONFIG_PPC_64K_PAGES is not set 295# CONFIG_PPC_64K_PAGES is not set
296# CONFIG_PPC_256K_PAGES is not set
287CONFIG_FORCE_MAX_ZONEORDER=13 297CONFIG_FORCE_MAX_ZONEORDER=13
288CONFIG_SCHED_SMT=y 298CONFIG_SCHED_SMT=y
289CONFIG_PROC_DEVICETREE=y 299CONFIG_PROC_DEVICETREE=y
@@ -316,7 +326,6 @@ CONFIG_NET=y
316# 326#
317# Networking options 327# Networking options
318# 328#
319CONFIG_COMPAT_NET_DEV_OPS=y
320CONFIG_PACKET=y 329CONFIG_PACKET=y
321CONFIG_PACKET_MMAP=y 330CONFIG_PACKET_MMAP=y
322CONFIG_UNIX=y 331CONFIG_UNIX=y
@@ -389,6 +398,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y
389# CONFIG_LAPB is not set 398# CONFIG_LAPB is not set
390# CONFIG_ECONET is not set 399# CONFIG_ECONET is not set
391# CONFIG_WAN_ROUTER is not set 400# CONFIG_WAN_ROUTER is not set
401# CONFIG_PHONET is not set
392# CONFIG_NET_SCHED is not set 402# CONFIG_NET_SCHED is not set
393# CONFIG_DCB is not set 403# CONFIG_DCB is not set
394 404
@@ -396,6 +406,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y
396# Network testing 406# Network testing
397# 407#
398# CONFIG_NET_PKTGEN is not set 408# CONFIG_NET_PKTGEN is not set
409# CONFIG_NET_DROP_MONITOR is not set
399# CONFIG_HAMRADIO is not set 410# CONFIG_HAMRADIO is not set
400# CONFIG_CAN is not set 411# CONFIG_CAN is not set
401# CONFIG_IRDA is not set 412# CONFIG_IRDA is not set
@@ -419,11 +430,9 @@ CONFIG_BT_HCIBTUSB=m
419# CONFIG_BT_HCIBFUSB is not set 430# CONFIG_BT_HCIBFUSB is not set
420# CONFIG_BT_HCIVHCI is not set 431# CONFIG_BT_HCIVHCI is not set
421# CONFIG_AF_RXRPC is not set 432# CONFIG_AF_RXRPC is not set
422# CONFIG_PHONET is not set
423CONFIG_WIRELESS=y 433CONFIG_WIRELESS=y
424CONFIG_CFG80211=m 434CONFIG_CFG80211=m
425# CONFIG_CFG80211_REG_DEBUG is not set 435# CONFIG_CFG80211_REG_DEBUG is not set
426CONFIG_NL80211=y
427# CONFIG_WIRELESS_OLD_REGULATORY is not set 436# CONFIG_WIRELESS_OLD_REGULATORY is not set
428CONFIG_WIRELESS_EXT=y 437CONFIG_WIRELESS_EXT=y
429# CONFIG_WIRELESS_EXT_SYSFS is not set 438# CONFIG_WIRELESS_EXT_SYSFS is not set
@@ -602,6 +611,7 @@ CONFIG_SCSI_WAIT_SCAN=m
602# CONFIG_SCSI_SRP_ATTRS is not set 611# CONFIG_SCSI_SRP_ATTRS is not set
603# CONFIG_SCSI_LOWLEVEL is not set 612# CONFIG_SCSI_LOWLEVEL is not set
604# CONFIG_SCSI_DH is not set 613# CONFIG_SCSI_DH is not set
614# CONFIG_SCSI_OSD_INITIATOR is not set
605# CONFIG_ATA is not set 615# CONFIG_ATA is not set
606CONFIG_MD=y 616CONFIG_MD=y
607# CONFIG_BLK_DEV_MD is not set 617# CONFIG_BLK_DEV_MD is not set
@@ -616,6 +626,7 @@ CONFIG_BLK_DEV_DM=m
616# CONFIG_DM_UEVENT is not set 626# CONFIG_DM_UEVENT is not set
617# CONFIG_MACINTOSH_DRIVERS is not set 627# CONFIG_MACINTOSH_DRIVERS is not set
618CONFIG_NETDEVICES=y 628CONFIG_NETDEVICES=y
629CONFIG_COMPAT_NET_DEV_OPS=y
619# CONFIG_DUMMY is not set 630# CONFIG_DUMMY is not set
620# CONFIG_BONDING is not set 631# CONFIG_BONDING is not set
621# CONFIG_MACVLAN is not set 632# CONFIG_MACVLAN is not set
@@ -625,6 +636,8 @@ CONFIG_NETDEVICES=y
625# CONFIG_PHYLIB is not set 636# CONFIG_PHYLIB is not set
626CONFIG_NET_ETHERNET=y 637CONFIG_NET_ETHERNET=y
627CONFIG_MII=m 638CONFIG_MII=m
639# CONFIG_ETHOC is not set
640# CONFIG_DNET is not set
628# CONFIG_IBM_NEW_EMAC_ZMII is not set 641# CONFIG_IBM_NEW_EMAC_ZMII is not set
629# CONFIG_IBM_NEW_EMAC_RGMII is not set 642# CONFIG_IBM_NEW_EMAC_RGMII is not set
630# CONFIG_IBM_NEW_EMAC_TAH is not set 643# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -646,12 +659,13 @@ CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE=y
646CONFIG_WLAN_80211=y 659CONFIG_WLAN_80211=y
647# CONFIG_LIBERTAS is not set 660# CONFIG_LIBERTAS is not set
648# CONFIG_LIBERTAS_THINFIRM is not set 661# CONFIG_LIBERTAS_THINFIRM is not set
662# CONFIG_AT76C50X_USB is not set
649# CONFIG_USB_ZD1201 is not set 663# CONFIG_USB_ZD1201 is not set
650# CONFIG_USB_NET_RNDIS_WLAN is not set 664# CONFIG_USB_NET_RNDIS_WLAN is not set
651# CONFIG_RTL8187 is not set 665# CONFIG_RTL8187 is not set
652# CONFIG_MAC80211_HWSIM is not set 666# CONFIG_MAC80211_HWSIM is not set
653# CONFIG_P54_COMMON is not set 667# CONFIG_P54_COMMON is not set
654# CONFIG_IWLWIFI_LEDS is not set 668# CONFIG_AR9170_USB is not set
655# CONFIG_HOSTAP is not set 669# CONFIG_HOSTAP is not set
656# CONFIG_B43 is not set 670# CONFIG_B43 is not set
657# CONFIG_B43LEGACY is not set 671# CONFIG_B43LEGACY is not set
@@ -673,6 +687,7 @@ CONFIG_USB_PEGASUS=m
673CONFIG_USB_USBNET=m 687CONFIG_USB_USBNET=m
674CONFIG_USB_NET_AX8817X=m 688CONFIG_USB_NET_AX8817X=m
675# CONFIG_USB_NET_CDCETHER is not set 689# CONFIG_USB_NET_CDCETHER is not set
690# CONFIG_USB_NET_CDC_EEM is not set
676# CONFIG_USB_NET_DM9601 is not set 691# CONFIG_USB_NET_DM9601 is not set
677# CONFIG_USB_NET_SMSC95XX is not set 692# CONFIG_USB_NET_SMSC95XX is not set
678# CONFIG_USB_NET_GL620A is not set 693# CONFIG_USB_NET_GL620A is not set
@@ -724,28 +739,7 @@ CONFIG_INPUT_EVDEV=m
724# 739#
725# CONFIG_INPUT_KEYBOARD is not set 740# CONFIG_INPUT_KEYBOARD is not set
726# CONFIG_INPUT_MOUSE is not set 741# CONFIG_INPUT_MOUSE is not set
727CONFIG_INPUT_JOYSTICK=y 742# CONFIG_INPUT_JOYSTICK is not set
728# CONFIG_JOYSTICK_ANALOG is not set
729# CONFIG_JOYSTICK_A3D is not set
730# CONFIG_JOYSTICK_ADI is not set
731# CONFIG_JOYSTICK_COBRA is not set
732# CONFIG_JOYSTICK_GF2K is not set
733# CONFIG_JOYSTICK_GRIP is not set
734# CONFIG_JOYSTICK_GRIP_MP is not set
735# CONFIG_JOYSTICK_GUILLEMOT is not set
736# CONFIG_JOYSTICK_INTERACT is not set
737# CONFIG_JOYSTICK_SIDEWINDER is not set
738# CONFIG_JOYSTICK_TMDC is not set
739# CONFIG_JOYSTICK_IFORCE is not set
740# CONFIG_JOYSTICK_WARRIOR is not set
741# CONFIG_JOYSTICK_MAGELLAN is not set
742# CONFIG_JOYSTICK_SPACEORB is not set
743# CONFIG_JOYSTICK_SPACEBALL is not set
744# CONFIG_JOYSTICK_STINGER is not set
745# CONFIG_JOYSTICK_TWIDJOY is not set
746# CONFIG_JOYSTICK_ZHENHUA is not set
747# CONFIG_JOYSTICK_JOYDUMP is not set
748# CONFIG_JOYSTICK_XPAD is not set
749# CONFIG_INPUT_TABLET is not set 743# CONFIG_INPUT_TABLET is not set
750# CONFIG_INPUT_TOUCHSCREEN is not set 744# CONFIG_INPUT_TOUCHSCREEN is not set
751# CONFIG_INPUT_MISC is not set 745# CONFIG_INPUT_MISC is not set
@@ -864,6 +858,7 @@ CONFIG_FB_PS3_DEFAULT_SIZE_M=9
864# CONFIG_FB_VIRTUAL is not set 858# CONFIG_FB_VIRTUAL is not set
865# CONFIG_FB_METRONOME is not set 859# CONFIG_FB_METRONOME is not set
866# CONFIG_FB_MB862XX is not set 860# CONFIG_FB_MB862XX is not set
861# CONFIG_FB_BROADSHEET is not set
867# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 862# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
868 863
869# 864#
@@ -934,15 +929,17 @@ CONFIG_USB_HIDDEV=y
934# 929#
935# Special HID drivers 930# Special HID drivers
936# 931#
937# CONFIG_HID_COMPAT is not set
938# CONFIG_HID_A4TECH is not set 932# CONFIG_HID_A4TECH is not set
939# CONFIG_HID_APPLE is not set 933# CONFIG_HID_APPLE is not set
940# CONFIG_HID_BELKIN is not set 934# CONFIG_HID_BELKIN is not set
941# CONFIG_HID_CHERRY is not set 935# CONFIG_HID_CHERRY is not set
942# CONFIG_HID_CHICONY is not set 936# CONFIG_HID_CHICONY is not set
943# CONFIG_HID_CYPRESS is not set 937# CONFIG_HID_CYPRESS is not set
938# CONFIG_DRAGONRISE_FF is not set
944# CONFIG_HID_EZKEY is not set 939# CONFIG_HID_EZKEY is not set
940# CONFIG_HID_KYE is not set
945# CONFIG_HID_GYRATION is not set 941# CONFIG_HID_GYRATION is not set
942# CONFIG_HID_KENSINGTON is not set
946# CONFIG_HID_LOGITECH is not set 943# CONFIG_HID_LOGITECH is not set
947# CONFIG_HID_MICROSOFT is not set 944# CONFIG_HID_MICROSOFT is not set
948# CONFIG_HID_MONTEREY is not set 945# CONFIG_HID_MONTEREY is not set
@@ -950,7 +947,7 @@ CONFIG_USB_HIDDEV=y
950# CONFIG_HID_PANTHERLORD is not set 947# CONFIG_HID_PANTHERLORD is not set
951# CONFIG_HID_PETALYNX is not set 948# CONFIG_HID_PETALYNX is not set
952# CONFIG_HID_SAMSUNG is not set 949# CONFIG_HID_SAMSUNG is not set
953# CONFIG_HID_SONY is not set 950CONFIG_HID_SONY=m
954# CONFIG_HID_SUNPLUS is not set 951# CONFIG_HID_SUNPLUS is not set
955# CONFIG_GREENASIA_FF is not set 952# CONFIG_GREENASIA_FF is not set
956# CONFIG_HID_TOPSEED is not set 953# CONFIG_HID_TOPSEED is not set
@@ -1012,11 +1009,11 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1012# CONFIG_USB_TMC is not set 1009# CONFIG_USB_TMC is not set
1013 1010
1014# 1011#
1015# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 1012# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1016# 1013#
1017 1014
1018# 1015#
1019# see USB_STORAGE Help for more information 1016# also be needed; see USB_STORAGE Help for more info
1020# 1017#
1021CONFIG_USB_STORAGE=m 1018CONFIG_USB_STORAGE=m
1022# CONFIG_USB_STORAGE_DEBUG is not set 1019# CONFIG_USB_STORAGE_DEBUG is not set
@@ -1058,7 +1055,6 @@ CONFIG_USB_STORAGE=m
1058# CONFIG_USB_LED is not set 1055# CONFIG_USB_LED is not set
1059# CONFIG_USB_CYPRESS_CY7C63 is not set 1056# CONFIG_USB_CYPRESS_CY7C63 is not set
1060# CONFIG_USB_CYTHERM is not set 1057# CONFIG_USB_CYTHERM is not set
1061# CONFIG_USB_PHIDGET is not set
1062# CONFIG_USB_IDMOUSE is not set 1058# CONFIG_USB_IDMOUSE is not set
1063# CONFIG_USB_FTDI_ELAN is not set 1059# CONFIG_USB_FTDI_ELAN is not set
1064# CONFIG_USB_APPLEDISPLAY is not set 1060# CONFIG_USB_APPLEDISPLAY is not set
@@ -1074,6 +1070,7 @@ CONFIG_USB_STORAGE=m
1074# 1070#
1075# OTG and related infrastructure 1071# OTG and related infrastructure
1076# 1072#
1073# CONFIG_NOP_USB_XCEIV is not set
1077# CONFIG_MMC is not set 1074# CONFIG_MMC is not set
1078# CONFIG_MEMSTICK is not set 1075# CONFIG_MEMSTICK is not set
1079# CONFIG_NEW_LEDS is not set 1076# CONFIG_NEW_LEDS is not set
@@ -1113,8 +1110,10 @@ CONFIG_RTC_INTF_DEV=y
1113# 1110#
1114# on-CPU RTC drivers 1111# on-CPU RTC drivers
1115# 1112#
1116CONFIG_RTC_DRV_PPC=m 1113# CONFIG_RTC_DRV_GENERIC is not set
1114CONFIG_RTC_DRV_PS3=m
1117# CONFIG_DMADEVICES is not set 1115# CONFIG_DMADEVICES is not set
1116# CONFIG_AUXDISPLAY is not set
1118# CONFIG_UIO is not set 1117# CONFIG_UIO is not set
1119# CONFIG_STAGING is not set 1118# CONFIG_STAGING is not set
1120 1119
@@ -1125,6 +1124,7 @@ CONFIG_EXT2_FS=m
1125# CONFIG_EXT2_FS_XATTR is not set 1124# CONFIG_EXT2_FS_XATTR is not set
1126# CONFIG_EXT2_FS_XIP is not set 1125# CONFIG_EXT2_FS_XIP is not set
1127CONFIG_EXT3_FS=m 1126CONFIG_EXT3_FS=m
1127# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1128CONFIG_EXT3_FS_XATTR=y 1128CONFIG_EXT3_FS_XATTR=y
1129# CONFIG_EXT3_FS_POSIX_ACL is not set 1129# CONFIG_EXT3_FS_POSIX_ACL is not set
1130# CONFIG_EXT3_FS_SECURITY is not set 1130# CONFIG_EXT3_FS_SECURITY is not set
@@ -1161,6 +1161,11 @@ CONFIG_AUTOFS4_FS=m
1161# CONFIG_FUSE_FS is not set 1161# CONFIG_FUSE_FS is not set
1162 1162
1163# 1163#
1164# Caches
1165#
1166# CONFIG_FSCACHE is not set
1167
1168#
1164# CD-ROM/DVD Filesystems 1169# CD-ROM/DVD Filesystems
1165# 1170#
1166CONFIG_ISO9660_FS=m 1171CONFIG_ISO9660_FS=m
@@ -1211,6 +1216,7 @@ CONFIG_MISC_FILESYSTEMS=y
1211# CONFIG_ROMFS_FS is not set 1216# CONFIG_ROMFS_FS is not set
1212# CONFIG_SYSV_FS is not set 1217# CONFIG_SYSV_FS is not set
1213# CONFIG_UFS_FS is not set 1218# CONFIG_UFS_FS is not set
1219# CONFIG_NILFS2_FS is not set
1214CONFIG_NETWORK_FILESYSTEMS=y 1220CONFIG_NETWORK_FILESYSTEMS=y
1215CONFIG_NFS_FS=y 1221CONFIG_NFS_FS=y
1216CONFIG_NFS_V3=y 1222CONFIG_NFS_V3=y
@@ -1223,7 +1229,6 @@ CONFIG_LOCKD_V4=y
1223CONFIG_NFS_COMMON=y 1229CONFIG_NFS_COMMON=y
1224CONFIG_SUNRPC=y 1230CONFIG_SUNRPC=y
1225CONFIG_SUNRPC_GSS=y 1231CONFIG_SUNRPC_GSS=y
1226# CONFIG_SUNRPC_REGISTER_V4 is not set
1227CONFIG_RPCSEC_GSS_KRB5=y 1232CONFIG_RPCSEC_GSS_KRB5=y
1228# CONFIG_RPCSEC_GSS_SPKM3 is not set 1233# CONFIG_RPCSEC_GSS_SPKM3 is not set
1229# CONFIG_SMB_FS is not set 1234# CONFIG_SMB_FS is not set
@@ -1283,6 +1288,7 @@ CONFIG_NLS_ISO8859_1=y
1283# CONFIG_NLS_KOI8_U is not set 1288# CONFIG_NLS_KOI8_U is not set
1284# CONFIG_NLS_UTF8 is not set 1289# CONFIG_NLS_UTF8 is not set
1285# CONFIG_DLM is not set 1290# CONFIG_DLM is not set
1291CONFIG_BINARY_PRINTF=y
1286 1292
1287# 1293#
1288# Library routines 1294# Library routines
@@ -1296,15 +1302,16 @@ CONFIG_CRC_ITU_T=m
1296CONFIG_CRC32=y 1302CONFIG_CRC32=y
1297# CONFIG_CRC7 is not set 1303# CONFIG_CRC7 is not set
1298# CONFIG_LIBCRC32C is not set 1304# CONFIG_LIBCRC32C is not set
1299CONFIG_ZLIB_INFLATE=m 1305CONFIG_ZLIB_INFLATE=y
1300CONFIG_ZLIB_DEFLATE=m 1306CONFIG_ZLIB_DEFLATE=m
1301CONFIG_LZO_COMPRESS=m 1307CONFIG_LZO_COMPRESS=m
1302CONFIG_LZO_DECOMPRESS=m 1308CONFIG_LZO_DECOMPRESS=m
1303CONFIG_PLIST=y 1309CONFIG_DECOMPRESS_GZIP=y
1304CONFIG_HAS_IOMEM=y 1310CONFIG_HAS_IOMEM=y
1305CONFIG_HAS_IOPORT=y 1311CONFIG_HAS_IOPORT=y
1306CONFIG_HAS_DMA=y 1312CONFIG_HAS_DMA=y
1307CONFIG_HAVE_LMB=y 1313CONFIG_HAVE_LMB=y
1314CONFIG_NLATTR=y
1308 1315
1309# 1316#
1310# Kernel hacking 1317# Kernel hacking
@@ -1322,6 +1329,9 @@ CONFIG_DEBUG_KERNEL=y
1322CONFIG_DETECT_SOFTLOCKUP=y 1329CONFIG_DETECT_SOFTLOCKUP=y
1323# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1330# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1324CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1331CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1332CONFIG_DETECT_HUNG_TASK=y
1333# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1334CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1325CONFIG_SCHED_DEBUG=y 1335CONFIG_SCHED_DEBUG=y
1326# CONFIG_SCHEDSTATS is not set 1336# CONFIG_SCHEDSTATS is not set
1327# CONFIG_TIMER_STATS is not set 1337# CONFIG_TIMER_STATS is not set
@@ -1357,12 +1367,15 @@ CONFIG_DEBUG_LIST=y
1357# CONFIG_FAULT_INJECTION is not set 1367# CONFIG_FAULT_INJECTION is not set
1358# CONFIG_LATENCYTOP is not set 1368# CONFIG_LATENCYTOP is not set
1359CONFIG_SYSCTL_SYSCALL_CHECK=y 1369CONFIG_SYSCTL_SYSCALL_CHECK=y
1370# CONFIG_DEBUG_PAGEALLOC is not set
1360CONFIG_NOP_TRACER=y 1371CONFIG_NOP_TRACER=y
1361CONFIG_HAVE_FUNCTION_TRACER=y 1372CONFIG_HAVE_FUNCTION_TRACER=y
1373CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1362CONFIG_HAVE_DYNAMIC_FTRACE=y 1374CONFIG_HAVE_DYNAMIC_FTRACE=y
1363CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1375CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1364CONFIG_RING_BUFFER=y 1376CONFIG_RING_BUFFER=y
1365CONFIG_TRACING=y 1377CONFIG_TRACING=y
1378CONFIG_TRACING_SUPPORT=y
1366 1379
1367# 1380#
1368# Tracers 1381# Tracers
@@ -1371,18 +1384,21 @@ CONFIG_TRACING=y
1371# CONFIG_IRQSOFF_TRACER is not set 1384# CONFIG_IRQSOFF_TRACER is not set
1372# CONFIG_SCHED_TRACER is not set 1385# CONFIG_SCHED_TRACER is not set
1373# CONFIG_CONTEXT_SWITCH_TRACER is not set 1386# CONFIG_CONTEXT_SWITCH_TRACER is not set
1387# CONFIG_EVENT_TRACER is not set
1374# CONFIG_BOOT_TRACER is not set 1388# CONFIG_BOOT_TRACER is not set
1375# CONFIG_TRACE_BRANCH_PROFILING is not set 1389# CONFIG_TRACE_BRANCH_PROFILING is not set
1376# CONFIG_STACK_TRACER is not set 1390# CONFIG_STACK_TRACER is not set
1391# CONFIG_KMEMTRACE is not set
1392# CONFIG_WORKQUEUE_TRACER is not set
1393# CONFIG_BLK_DEV_IO_TRACE is not set
1377# CONFIG_FTRACE_STARTUP_TEST is not set 1394# CONFIG_FTRACE_STARTUP_TEST is not set
1378# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1395# CONFIG_DYNAMIC_DEBUG is not set
1379# CONFIG_SAMPLES is not set 1396# CONFIG_SAMPLES is not set
1380CONFIG_HAVE_ARCH_KGDB=y 1397CONFIG_HAVE_ARCH_KGDB=y
1381# CONFIG_KGDB is not set 1398# CONFIG_KGDB is not set
1382CONFIG_PRINT_STACK_DEPTH=64 1399CONFIG_PRINT_STACK_DEPTH=64
1383CONFIG_DEBUG_STACKOVERFLOW=y 1400CONFIG_DEBUG_STACKOVERFLOW=y
1384# CONFIG_DEBUG_STACK_USAGE is not set 1401# CONFIG_DEBUG_STACK_USAGE is not set
1385# CONFIG_DEBUG_PAGEALLOC is not set
1386# CONFIG_CODE_PATCHING_SELFTEST is not set 1402# CONFIG_CODE_PATCHING_SELFTEST is not set
1387# CONFIG_FTR_FIXUP_SELFTEST is not set 1403# CONFIG_FTR_FIXUP_SELFTEST is not set
1388# CONFIG_MSI_BITMAP_SELFTEST is not set 1404# CONFIG_MSI_BITMAP_SELFTEST is not set
@@ -1415,10 +1431,12 @@ CONFIG_CRYPTO_HASH=y
1415CONFIG_CRYPTO_HASH2=y 1431CONFIG_CRYPTO_HASH2=y
1416CONFIG_CRYPTO_RNG=m 1432CONFIG_CRYPTO_RNG=m
1417CONFIG_CRYPTO_RNG2=y 1433CONFIG_CRYPTO_RNG2=y
1434CONFIG_CRYPTO_PCOMP=y
1418CONFIG_CRYPTO_MANAGER=y 1435CONFIG_CRYPTO_MANAGER=y
1419CONFIG_CRYPTO_MANAGER2=y 1436CONFIG_CRYPTO_MANAGER2=y
1420CONFIG_CRYPTO_GF128MUL=m 1437CONFIG_CRYPTO_GF128MUL=m
1421# CONFIG_CRYPTO_NULL is not set 1438# CONFIG_CRYPTO_NULL is not set
1439CONFIG_CRYPTO_WORKQUEUE=y
1422# CONFIG_CRYPTO_CRYPTD is not set 1440# CONFIG_CRYPTO_CRYPTD is not set
1423# CONFIG_CRYPTO_AUTHENC is not set 1441# CONFIG_CRYPTO_AUTHENC is not set
1424# CONFIG_CRYPTO_TEST is not set 1442# CONFIG_CRYPTO_TEST is not set
@@ -1487,6 +1505,7 @@ CONFIG_CRYPTO_SALSA20=m
1487# Compression 1505# Compression
1488# 1506#
1489# CONFIG_CRYPTO_DEFLATE is not set 1507# CONFIG_CRYPTO_DEFLATE is not set
1508# CONFIG_CRYPTO_ZLIB is not set
1490CONFIG_CRYPTO_LZO=m 1509CONFIG_CRYPTO_LZO=m
1491 1510
1492# 1511#
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index b401950f5259..b7d2d07b6f96 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -472,6 +472,6 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
472 472
473#endif /* __powerpc64__ */ 473#endif /* __powerpc64__ */
474 474
475#include <asm-generic/atomic.h> 475#include <asm-generic/atomic-long.h>
476#endif /* __KERNEL__ */ 476#endif /* __KERNEL__ */
477#endif /* _ASM_POWERPC_ATOMIC_H_ */ 477#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/arch/powerpc/include/asm/bitsperlong.h b/arch/powerpc/include/asm/bitsperlong.h
new file mode 100644
index 000000000000..5f1659032c40
--- /dev/null
+++ b/arch/powerpc/include/asm/bitsperlong.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_POWERPC_BITSPERLONG_H
2#define __ASM_POWERPC_BITSPERLONG_H
3
4#if defined(__powerpc64__)
5# define __BITS_PER_LONG 64
6#else
7# define __BITS_PER_LONG 32
8#endif
9
10#include <asm-generic/bitsperlong.h>
11
12#endif /* __ASM_POWERPC_BITSPERLONG_H */
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index c69f2b5f0cc4..cb448d68452c 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -26,7 +26,9 @@
26 * allocate the space "normally" and use the cache management functions 26 * allocate the space "normally" and use the cache management functions
27 * to ensure it is consistent. 27 * to ensure it is consistent.
28 */ 28 */
29extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp); 29struct device;
30extern void *__dma_alloc_coherent(struct device *dev, size_t size,
31 dma_addr_t *handle, gfp_t gfp);
30extern void __dma_free_coherent(size_t size, void *vaddr); 32extern void __dma_free_coherent(size_t size, void *vaddr);
31extern void __dma_sync(void *vaddr, size_t size, int direction); 33extern void __dma_sync(void *vaddr, size_t size, int direction);
32extern void __dma_sync_page(struct page *page, unsigned long offset, 34extern void __dma_sync_page(struct page *page, unsigned long offset,
@@ -37,7 +39,7 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
37 * Cache coherent cores. 39 * Cache coherent cores.
38 */ 40 */
39 41
40#define __dma_alloc_coherent(gfp, size, handle) NULL 42#define __dma_alloc_coherent(dev, gfp, size, handle) NULL
41#define __dma_free_coherent(size, addr) ((void)0) 43#define __dma_free_coherent(size, addr) ((void)0)
42#define __dma_sync(addr, size, rw) ((void)0) 44#define __dma_sync(addr, size, rw) ((void)0)
43#define __dma_sync_page(pg, off, sz, rw) ((void)0) 45#define __dma_sync_page(pg, off, sz, rw) ((void)0)
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index d60fd18f428c..f1f4e23a84e9 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -14,8 +14,6 @@
14#ifndef _ASM_FIXMAP_H 14#ifndef _ASM_FIXMAP_H
15#define _ASM_FIXMAP_H 15#define _ASM_FIXMAP_H
16 16
17extern unsigned long FIXADDR_TOP;
18
19#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
20#include <linux/kernel.h> 18#include <linux/kernel.h>
21#include <asm/page.h> 19#include <asm/page.h>
@@ -24,6 +22,8 @@ extern unsigned long FIXADDR_TOP;
24#include <asm/kmap_types.h> 22#include <asm/kmap_types.h>
25#endif 23#endif
26 24
25#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE))
26
27/* 27/*
28 * Here we define all the compile-time 'special' virtual 28 * Here we define all the compile-time 'special' virtual
29 * addresses. The point is to have a constant address at 29 * addresses. The point is to have a constant address at
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index b7e034b0a6dd..53512374e1c9 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -131,5 +131,41 @@ static inline int irqs_disabled_flags(unsigned long flags)
131 */ 131 */
132struct irq_chip; 132struct irq_chip;
133 133
134#ifdef CONFIG_PERF_COUNTERS
135static inline unsigned long test_perf_counter_pending(void)
136{
137 unsigned long x;
138
139 asm volatile("lbz %0,%1(13)"
140 : "=r" (x)
141 : "i" (offsetof(struct paca_struct, perf_counter_pending)));
142 return x;
143}
144
145static inline void set_perf_counter_pending(void)
146{
147 asm volatile("stb %0,%1(13)" : :
148 "r" (1),
149 "i" (offsetof(struct paca_struct, perf_counter_pending)));
150}
151
152static inline void clear_perf_counter_pending(void)
153{
154 asm volatile("stb %0,%1(13)" : :
155 "r" (0),
156 "i" (offsetof(struct paca_struct, perf_counter_pending)));
157}
158
159#else
160
161static inline unsigned long test_perf_counter_pending(void)
162{
163 return 0;
164}
165
166static inline void set_perf_counter_pending(void) {}
167static inline void clear_perf_counter_pending(void) {}
168#endif /* CONFIG_PERF_COUNTERS */
169
134#endif /* __KERNEL__ */ 170#endif /* __KERNEL__ */
135#endif /* _ASM_POWERPC_HW_IRQ_H */ 171#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h
index e7b99bac9f48..7b1c49811a24 100644
--- a/arch/powerpc/include/asm/mman.h
+++ b/arch/powerpc/include/asm/mman.h
@@ -1,7 +1,7 @@
1#ifndef _ASM_POWERPC_MMAN_H 1#ifndef _ASM_POWERPC_MMAN_H
2#define _ASM_POWERPC_MMAN_H 2#define _ASM_POWERPC_MMAN_H
3 3
4#include <asm-generic/mman.h> 4#include <asm-generic/mman-common.h>
5 5
6/* 6/*
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index a218da6bec7c..fb8412057450 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -28,6 +28,10 @@
28#define MPC52xx_PSC_MAXNUM 6 28#define MPC52xx_PSC_MAXNUM 6
29 29
30/* Programmable Serial Controller (PSC) status register bits */ 30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_UNEX_RX 0x0001
32#define MPC52xx_PSC_SR_DATA_VAL 0x0002
33#define MPC52xx_PSC_SR_DATA_OVR 0x0004
34#define MPC52xx_PSC_SR_CMDSEND 0x0008
31#define MPC52xx_PSC_SR_CDE 0x0080 35#define MPC52xx_PSC_SR_CDE 0x0080
32#define MPC52xx_PSC_SR_RXRDY 0x0100 36#define MPC52xx_PSC_SR_RXRDY 0x0100
33#define MPC52xx_PSC_SR_RXFULL 0x0200 37#define MPC52xx_PSC_SR_RXFULL 0x0200
@@ -61,6 +65,12 @@
61#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 65#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
62 66
63/* PSC interrupt status/mask bits */ 67/* PSC interrupt status/mask bits */
68#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
69#define MPC52xx_PSC_IMR_DATA_VALID 0x0002
70#define MPC52xx_PSC_IMR_DATA_OVR 0x0004
71#define MPC52xx_PSC_IMR_CMD_SEND 0x0008
72#define MPC52xx_PSC_IMR_ERROR 0x0040
73#define MPC52xx_PSC_IMR_DEOF 0x0080
64#define MPC52xx_PSC_IMR_TXRDY 0x0100 74#define MPC52xx_PSC_IMR_TXRDY 0x0100
65#define MPC52xx_PSC_IMR_RXRDY 0x0200 75#define MPC52xx_PSC_IMR_RXRDY 0x0200
66#define MPC52xx_PSC_IMR_DB 0x0400 76#define MPC52xx_PSC_IMR_DB 0x0400
@@ -117,6 +127,7 @@
117#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) 127#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
118#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) 128#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
119#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) 129#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
130#define MPC52xx_PSC_SICR_AWR (1 << 30)
120#define MPC52xx_PSC_SICR_GENCLK (1 << 23) 131#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
121#define MPC52xx_PSC_SICR_I2S (1 << 22) 132#define MPC52xx_PSC_SICR_I2S (1 << 22)
122#define MPC52xx_PSC_SICR_CLKPOL (1 << 21) 133#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 082b3aedf145..6ef055723019 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -99,6 +99,7 @@ struct paca_struct {
99 u8 soft_enabled; /* irq soft-enable flag */ 99 u8 soft_enabled; /* irq soft-enable flag */
100 u8 hard_enabled; /* set if irqs are enabled in MSR */ 100 u8 hard_enabled; /* set if irqs are enabled in MSR */
101 u8 io_sync; /* writel() needs spin_unlock sync */ 101 u8 io_sync; /* writel() needs spin_unlock sync */
102 u8 perf_counter_pending; /* PM interrupt while soft-disabled */
102 103
103 /* Stuff for accurate time accounting */ 104 /* Stuff for accurate time accounting */
104 u64 user_time; /* accumulated usermode TB ticks */ 105 u64 user_time; /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h
index a0e3f6e6b4ee..bd0849dbcaaa 100644
--- a/arch/powerpc/include/asm/page_32.h
+++ b/arch/powerpc/include/asm/page_32.h
@@ -41,7 +41,7 @@ extern void clear_pages(void *page, int order);
41static inline void clear_page(void *page) { clear_pages(page, 0); } 41static inline void clear_page(void *page) { clear_pages(page, 0); }
42extern void copy_page(void *to, void *from); 42extern void copy_page(void *to, void *from);
43 43
44#include <asm-generic/page.h> 44#include <asm-generic/getorder.h>
45 45
46#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) 46#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
47#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) 47#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 043bfdfe4f73..5817a3b747e5 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -180,6 +180,6 @@ do { \
180 (test_thread_flag(TIF_32BIT) ? \ 180 (test_thread_flag(TIF_32BIT) ? \
181 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) 181 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
182 182
183#include <asm-generic/page.h> 183#include <asm-generic/getorder.h>
184 184
185#endif /* _ASM_POWERPC_PAGE_64_H */ 185#endif /* _ASM_POWERPC_PAGE_64_H */
diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h
new file mode 100644
index 000000000000..cc7c887705b8
--- /dev/null
+++ b/arch/powerpc/include/asm/perf_counter.h
@@ -0,0 +1,98 @@
1/*
2 * Performance counter support - PowerPC-specific definitions.
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/types.h>
12
13#define MAX_HWCOUNTERS 8
14#define MAX_EVENT_ALTERNATIVES 8
15#define MAX_LIMITED_HWCOUNTERS 2
16
17/*
18 * This struct provides the constants and functions needed to
19 * describe the PMU on a particular POWER-family CPU.
20 */
21struct power_pmu {
22 int n_counter;
23 int max_alternatives;
24 u64 add_fields;
25 u64 test_adder;
26 int (*compute_mmcr)(u64 events[], int n_ev,
27 unsigned int hwc[], u64 mmcr[]);
28 int (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
29 int (*get_alternatives)(u64 event, unsigned int flags,
30 u64 alt[]);
31 void (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
32 int (*limited_pmc_event)(u64 event);
33 u32 flags;
34 int n_generic;
35 int *generic_events;
36 int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
37 [PERF_COUNT_HW_CACHE_OP_MAX]
38 [PERF_COUNT_HW_CACHE_RESULT_MAX];
39};
40
41extern struct power_pmu *ppmu;
42
43/*
44 * Values for power_pmu.flags
45 */
46#define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */
47#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */
48
49/*
50 * Values for flags to get_alternatives()
51 */
52#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
53#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
54#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
55
56struct pt_regs;
57extern unsigned long perf_misc_flags(struct pt_regs *regs);
58#define perf_misc_flags(regs) perf_misc_flags(regs)
59
60extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
61
62/*
63 * The power_pmu.get_constraint function returns a 64-bit value and
64 * a 64-bit mask that express the constraints between this event and
65 * other events.
66 *
67 * The value and mask are divided up into (non-overlapping) bitfields
68 * of three different types:
69 *
70 * Select field: this expresses the constraint that some set of bits
71 * in MMCR* needs to be set to a specific value for this event. For a
72 * select field, the mask contains 1s in every bit of the field, and
73 * the value contains a unique value for each possible setting of the
74 * MMCR* bits. The constraint checking code will ensure that two events
75 * that set the same field in their masks have the same value in their
76 * value dwords.
77 *
78 * Add field: this expresses the constraint that there can be at most
79 * N events in a particular class. A field of k bits can be used for
80 * N <= 2^(k-1) - 1. The mask has the most significant bit of the field
81 * set (and the other bits 0), and the value has only the least significant
82 * bit of the field set. In addition, the 'add_fields' and 'test_adder'
83 * in the struct power_pmu for this processor come into play. The
84 * add_fields value contains 1 in the LSB of the field, and the
85 * test_adder contains 2^(k-1) - 1 - N in the field.
86 *
87 * NAND field: this expresses the constraint that you may not have events
88 * in all of a set of classes. (For example, on PPC970, you can't select
89 * events from the FPU, ISU and IDU simultaneously, although any two are
90 * possible.) For N classes, the field is N+1 bits wide, and each class
91 * is assigned one bit from the least-significant N bits. The mask has
92 * only the most-significant bit set, and the value has only the bit
93 * for the event's class set. The test_adder has the least significant
94 * bit set in the field.
95 *
96 * If an event is not subject to the constraint expressed by a particular
97 * field, then it will have 0 in both the mask and value for that field.
98 */
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index ba45c997830f..c9ff9d75990e 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -10,7 +10,7 @@
10 10
11extern unsigned long va_to_phys(unsigned long address); 11extern unsigned long va_to_phys(unsigned long address);
12extern pte_t *va_to_pte(unsigned long address); 12extern pte_t *va_to_pte(unsigned long address);
13extern unsigned long ioremap_bot, ioremap_base; 13extern unsigned long ioremap_bot;
14 14
15#ifdef CONFIG_44x 15#ifdef CONFIG_44x
16extern int icache_44x_need_flush; 16extern int icache_44x_need_flush;
@@ -56,8 +56,30 @@ extern int icache_44x_need_flush;
56 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 56 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
57 57
58/* 58/*
59 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
60 * value (for now) on others, from where we can start layout kernel
61 * virtual space that goes below PKMAP and FIXMAP
62 */
63#ifdef CONFIG_HIGHMEM
64#define KVIRT_TOP PKMAP_BASE
65#else
66#define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
67#endif
68
69/*
70 * ioremap_bot starts at that address. Early ioremaps move down from there,
71 * until mem_init() at which point this becomes the top of the vmalloc
72 * and ioremap space
73 */
74#ifdef CONFIG_NOT_COHERENT_CACHE
75#define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
76#else
77#define IOREMAP_TOP KVIRT_TOP
78#endif
79
80/*
59 * Just any arbitrary offset to the start of the vmalloc VM area: the 81 * Just any arbitrary offset to the start of the vmalloc VM area: the
60 * current 64MB value just means that there will be a 64MB "hole" after the 82 * current 16MB value just means that there will be a 64MB "hole" after the
61 * physical memory until the kernel virtual memory starts. That means that 83 * physical memory until the kernel virtual memory starts. That means that
62 * any out-of-bounds memory accesses will hopefully be caught. 84 * any out-of-bounds memory accesses will hopefully be caught.
63 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 85 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index e8018d540e87..fb359b0a6937 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -492,11 +492,13 @@
492#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 492#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
493#define SPRN_MMCR1 798 493#define SPRN_MMCR1 798
494#define SPRN_MMCRA 0x312 494#define SPRN_MMCRA 0x312
495#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
495#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 496#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
496#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 497#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
497#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 498#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
498#define MMCRA_SLOT_SHIFT 24 499#define MMCRA_SLOT_SHIFT 24
499#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 500#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
501#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
500#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 502#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
501#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 503#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
502#define POWER6_MMCRA_THRM 0x00000020UL 504#define POWER6_MMCRA_THRM 0x00000020UL
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
index 69f709d8e8e7..3eb13be11d8f 100644
--- a/arch/powerpc/include/asm/signal.h
+++ b/arch/powerpc/include/asm/signal.h
@@ -94,7 +94,7 @@ typedef struct {
94#define MINSIGSTKSZ 2048 94#define MINSIGSTKSZ 2048
95#define SIGSTKSZ 8192 95#define SIGSTKSZ 8192
96 96
97#include <asm-generic/signal.h> 97#include <asm-generic/signal-defs.h>
98 98
99struct old_sigaction { 99struct old_sigaction {
100 __sighandler_t sa_handler; 100 __sighandler_t sa_handler;
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index d98a30dfd41c..a0b92de51c7e 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -322,6 +322,6 @@ SYSCALL_SPU(epoll_create1)
322SYSCALL_SPU(dup3) 322SYSCALL_SPU(dup3)
323SYSCALL_SPU(pipe2) 323SYSCALL_SPU(pipe2)
324SYSCALL(inotify_init1) 324SYSCALL(inotify_init1)
325SYSCALL(ni_syscall) 325SYSCALL_SPU(perf_counter_open)
326COMPAT_SYS_SPU(preadv) 326COMPAT_SYS_SPU(preadv)
327COMPAT_SYS_SPU(pwritev) 327COMPAT_SYS_SPU(pwritev)
diff --git a/arch/powerpc/include/asm/termios.h b/arch/powerpc/include/asm/termios.h
index 2c14fea07c8a..a24f48704a34 100644
--- a/arch/powerpc/include/asm/termios.h
+++ b/arch/powerpc/include/asm/termios.h
@@ -78,7 +78,7 @@ struct termio {
78 78
79#ifdef __KERNEL__ 79#ifdef __KERNEL__
80 80
81#include <asm-generic/termios.h> 81#include <asm-generic/termios-base.h>
82 82
83#endif /* __KERNEL__ */ 83#endif /* __KERNEL__ */
84 84
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 7ce27a52bb34..a5aea0ca34e9 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -40,15 +40,6 @@ typedef struct {
40#endif /* __ASSEMBLY__ */ 40#endif /* __ASSEMBLY__ */
41 41
42#ifdef __KERNEL__ 42#ifdef __KERNEL__
43/*
44 * These aren't exported outside the kernel to avoid name space clashes
45 */
46#ifdef __powerpc64__
47#define BITS_PER_LONG 64
48#else
49#define BITS_PER_LONG 32
50#endif
51
52#ifndef __ASSEMBLY__ 43#ifndef __ASSEMBLY__
53 44
54typedef __vector128 vector128; 45typedef __vector128 vector128;
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3f06f8ec81c5..4badac2d11d1 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -341,6 +341,7 @@
341#define __NR_dup3 316 341#define __NR_dup3 316
342#define __NR_pipe2 317 342#define __NR_pipe2 317
343#define __NR_inotify_init1 318 343#define __NR_inotify_init1 318
344#define __NR_perf_counter_open 319
344#define __NR_preadv 320 345#define __NR_preadv 320
345#define __NR_pwritev 321 346#define __NR_pwritev 321
346 347
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 71901fbda4a5..a2c683403c2b 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -94,6 +94,9 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o
94 94
95obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 95obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
96obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 96obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
97obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o power4-pmu.o ppc970-pmu.o \
98 power5-pmu.o power5+-pmu.o power6-pmu.o \
99 power7-pmu.o
97 100
98obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o 101obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
99 102
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 1e40bc053946..e981d1ce1914 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -131,6 +131,7 @@ int main(void)
131 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); 131 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
132 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); 132 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
133 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled)); 133 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
134 DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_counter_pending));
134 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); 135 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
135 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); 136 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
136 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); 137 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 53c7788cba78..6b02793dc75b 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -32,7 +32,7 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
32{ 32{
33 void *ret; 33 void *ret;
34#ifdef CONFIG_NOT_COHERENT_CACHE 34#ifdef CONFIG_NOT_COHERENT_CACHE
35 ret = __dma_alloc_coherent(size, dma_handle, flag); 35 ret = __dma_alloc_coherent(dev, size, dma_handle, flag);
36 if (ret == NULL) 36 if (ret == NULL)
37 return NULL; 37 return NULL;
38 *dma_handle += get_dma_direct_offset(dev); 38 *dma_handle += get_dma_direct_offset(dev);
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index abfc32330479..43e073477c34 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -526,6 +526,15 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
5262: 5262:
527 TRACE_AND_RESTORE_IRQ(r5); 527 TRACE_AND_RESTORE_IRQ(r5);
528 528
529#ifdef CONFIG_PERF_COUNTERS
530 /* check paca->perf_counter_pending if we're enabling ints */
531 lbz r3,PACAPERFPEND(r13)
532 and. r3,r3,r5
533 beq 27f
534 bl .perf_counter_do_pending
53527:
536#endif /* CONFIG_PERF_COUNTERS */
537
529 /* extract EE bit and use it to restore paca->hard_enabled */ 538 /* extract EE bit and use it to restore paca->hard_enabled */
530 ld r3,_MSR(r1) 539 ld r3,_MSR(r1)
531 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ 540 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 70e2a736be1f..2d182f119d1d 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -157,7 +157,7 @@ __ftrace_make_nop(struct module *mod,
157 * 0xe8, 0x4c, 0x00, 0x28, ld r2,40(r12) 157 * 0xe8, 0x4c, 0x00, 0x28, ld r2,40(r12)
158 */ 158 */
159 159
160 pr_debug("ip:%lx jumps to %lx r2: %lx", ip, tramp, mod->arch.toc); 160 pr_devel("ip:%lx jumps to %lx r2: %lx", ip, tramp, mod->arch.toc);
161 161
162 /* Find where the trampoline jumps to */ 162 /* Find where the trampoline jumps to */
163 if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) { 163 if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) {
@@ -165,7 +165,7 @@ __ftrace_make_nop(struct module *mod,
165 return -EFAULT; 165 return -EFAULT;
166 } 166 }
167 167
168 pr_debug(" %08x %08x", jmp[0], jmp[1]); 168 pr_devel(" %08x %08x", jmp[0], jmp[1]);
169 169
170 /* verify that this is what we expect it to be */ 170 /* verify that this is what we expect it to be */
171 if (((jmp[0] & 0xffff0000) != 0x3d820000) || 171 if (((jmp[0] & 0xffff0000) != 0x3d820000) ||
@@ -181,18 +181,18 @@ __ftrace_make_nop(struct module *mod,
181 offset = ((unsigned)((unsigned short)jmp[0]) << 16) + 181 offset = ((unsigned)((unsigned short)jmp[0]) << 16) +
182 (int)((short)jmp[1]); 182 (int)((short)jmp[1]);
183 183
184 pr_debug(" %x ", offset); 184 pr_devel(" %x ", offset);
185 185
186 /* get the address this jumps too */ 186 /* get the address this jumps too */
187 tramp = mod->arch.toc + offset + 32; 187 tramp = mod->arch.toc + offset + 32;
188 pr_debug("toc: %lx", tramp); 188 pr_devel("toc: %lx", tramp);
189 189
190 if (probe_kernel_read(jmp, (void *)tramp, 8)) { 190 if (probe_kernel_read(jmp, (void *)tramp, 8)) {
191 printk(KERN_ERR "Failed to read %lx\n", tramp); 191 printk(KERN_ERR "Failed to read %lx\n", tramp);
192 return -EFAULT; 192 return -EFAULT;
193 } 193 }
194 194
195 pr_debug(" %08x %08x\n", jmp[0], jmp[1]); 195 pr_devel(" %08x %08x\n", jmp[0], jmp[1]);
196 196
197 ptr = ((unsigned long)jmp[0] << 32) + jmp[1]; 197 ptr = ((unsigned long)jmp[0] << 32) + jmp[1];
198 198
@@ -269,7 +269,7 @@ __ftrace_make_nop(struct module *mod,
269 * 0x4e, 0x80, 0x04, 0x20 bctr 269 * 0x4e, 0x80, 0x04, 0x20 bctr
270 */ 270 */
271 271
272 pr_debug("ip:%lx jumps to %lx", ip, tramp); 272 pr_devel("ip:%lx jumps to %lx", ip, tramp);
273 273
274 /* Find where the trampoline jumps to */ 274 /* Find where the trampoline jumps to */
275 if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) { 275 if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) {
@@ -277,7 +277,7 @@ __ftrace_make_nop(struct module *mod,
277 return -EFAULT; 277 return -EFAULT;
278 } 278 }
279 279
280 pr_debug(" %08x %08x ", jmp[0], jmp[1]); 280 pr_devel(" %08x %08x ", jmp[0], jmp[1]);
281 281
282 /* verify that this is what we expect it to be */ 282 /* verify that this is what we expect it to be */
283 if (((jmp[0] & 0xffff0000) != 0x3d600000) || 283 if (((jmp[0] & 0xffff0000) != 0x3d600000) ||
@@ -293,7 +293,7 @@ __ftrace_make_nop(struct module *mod,
293 if (tramp & 0x8000) 293 if (tramp & 0x8000)
294 tramp -= 0x10000; 294 tramp -= 0x10000;
295 295
296 pr_debug(" %lx ", tramp); 296 pr_devel(" %lx ", tramp);
297 297
298 if (tramp != addr) { 298 if (tramp != addr) {
299 printk(KERN_ERR 299 printk(KERN_ERR
@@ -402,7 +402,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
402 /* ld r2,40(r1) */ 402 /* ld r2,40(r1) */
403 op[1] = 0xe8410028; 403 op[1] = 0xe8410028;
404 404
405 pr_debug("write to %lx\n", rec->ip); 405 pr_devel("write to %lx\n", rec->ip);
406 406
407 if (probe_kernel_write((void *)ip, op, MCOUNT_INSN_SIZE * 2)) 407 if (probe_kernel_write((void *)ip, op, MCOUNT_INSN_SIZE * 2))
408 return -EPERM; 408 return -EPERM;
@@ -442,7 +442,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
442 return -EINVAL; 442 return -EINVAL;
443 } 443 }
444 444
445 pr_debug("write to %lx\n", rec->ip); 445 pr_devel("write to %lx\n", rec->ip);
446 446
447 if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE)) 447 if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE))
448 return -EPERM; 448 return -EPERM;
@@ -594,7 +594,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
594 PPC_LONG "2b,4b\n" 594 PPC_LONG "2b,4b\n"
595 ".previous" 595 ".previous"
596 596
597 : [old] "=r" (old), [faulted] "=r" (faulted) 597 : [old] "=&r" (old), [faulted] "=r" (faulted)
598 : [parent] "r" (parent), [return_hooker] "r" (return_hooker) 598 : [parent] "r" (parent), [return_hooker] "r" (return_hooker)
599 : "memory" 599 : "memory"
600 ); 600 );
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 8c1a4966867e..844d3f882a15 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -53,6 +53,7 @@
53#include <linux/bootmem.h> 53#include <linux/bootmem.h>
54#include <linux/pci.h> 54#include <linux/pci.h>
55#include <linux/debugfs.h> 55#include <linux/debugfs.h>
56#include <linux/perf_counter.h>
56 57
57#include <asm/uaccess.h> 58#include <asm/uaccess.h>
58#include <asm/system.h> 59#include <asm/system.h>
@@ -135,6 +136,11 @@ notrace void raw_local_irq_restore(unsigned long en)
135 iseries_handle_interrupts(); 136 iseries_handle_interrupts();
136 } 137 }
137 138
139 if (test_perf_counter_pending()) {
140 clear_perf_counter_pending();
141 perf_counter_do_pending();
142 }
143
138 /* 144 /*
139 * if (get_paca()->hard_enabled) return; 145 * if (get_paca()->hard_enabled) return;
140 * But again we need to take care that gcc gets hard_enabled directly 146 * But again we need to take care that gcc gets hard_enabled directly
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 43e7e3a7f130..477c663e0140 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -43,8 +43,6 @@ void *module_alloc(unsigned long size)
43void module_free(struct module *mod, void *module_region) 43void module_free(struct module *mod, void *module_region)
44{ 44{
45 vfree(module_region); 45 vfree(module_region);
46 /* FIXME: If module_region == mod->init_region, trim exception
47 table entries. */
48} 46}
49 47
50static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, 48static const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
new file mode 100644
index 000000000000..bb202388170e
--- /dev/null
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -0,0 +1,1263 @@
1/*
2 * Performance counter support - powerpc architecture code
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/sched.h>
13#include <linux/perf_counter.h>
14#include <linux/percpu.h>
15#include <linux/hardirq.h>
16#include <asm/reg.h>
17#include <asm/pmc.h>
18#include <asm/machdep.h>
19#include <asm/firmware.h>
20#include <asm/ptrace.h>
21
22struct cpu_hw_counters {
23 int n_counters;
24 int n_percpu;
25 int disabled;
26 int n_added;
27 int n_limited;
28 u8 pmcs_enabled;
29 struct perf_counter *counter[MAX_HWCOUNTERS];
30 u64 events[MAX_HWCOUNTERS];
31 unsigned int flags[MAX_HWCOUNTERS];
32 u64 mmcr[3];
33 struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
34 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
35};
36DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
37
38struct power_pmu *ppmu;
39
40/*
41 * Normally, to ignore kernel events we set the FCS (freeze counters
42 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
43 * hypervisor bit set in the MSR, or if we are running on a processor
44 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
45 * then we need to use the FCHV bit to ignore kernel events.
46 */
47static unsigned int freeze_counters_kernel = MMCR0_FCS;
48
49static void perf_counter_interrupt(struct pt_regs *regs);
50
51void perf_counter_print_debug(void)
52{
53}
54
55/*
56 * Read one performance monitor counter (PMC).
57 */
58static unsigned long read_pmc(int idx)
59{
60 unsigned long val;
61
62 switch (idx) {
63 case 1:
64 val = mfspr(SPRN_PMC1);
65 break;
66 case 2:
67 val = mfspr(SPRN_PMC2);
68 break;
69 case 3:
70 val = mfspr(SPRN_PMC3);
71 break;
72 case 4:
73 val = mfspr(SPRN_PMC4);
74 break;
75 case 5:
76 val = mfspr(SPRN_PMC5);
77 break;
78 case 6:
79 val = mfspr(SPRN_PMC6);
80 break;
81 case 7:
82 val = mfspr(SPRN_PMC7);
83 break;
84 case 8:
85 val = mfspr(SPRN_PMC8);
86 break;
87 default:
88 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
89 val = 0;
90 }
91 return val;
92}
93
94/*
95 * Write one PMC.
96 */
97static void write_pmc(int idx, unsigned long val)
98{
99 switch (idx) {
100 case 1:
101 mtspr(SPRN_PMC1, val);
102 break;
103 case 2:
104 mtspr(SPRN_PMC2, val);
105 break;
106 case 3:
107 mtspr(SPRN_PMC3, val);
108 break;
109 case 4:
110 mtspr(SPRN_PMC4, val);
111 break;
112 case 5:
113 mtspr(SPRN_PMC5, val);
114 break;
115 case 6:
116 mtspr(SPRN_PMC6, val);
117 break;
118 case 7:
119 mtspr(SPRN_PMC7, val);
120 break;
121 case 8:
122 mtspr(SPRN_PMC8, val);
123 break;
124 default:
125 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
126 }
127}
128
129/*
130 * Check if a set of events can all go on the PMU at once.
131 * If they can't, this will look at alternative codes for the events
132 * and see if any combination of alternative codes is feasible.
133 * The feasible set is returned in event[].
134 */
135static int power_check_constraints(u64 event[], unsigned int cflags[],
136 int n_ev)
137{
138 u64 mask, value, nv;
139 u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
140 u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
141 u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
142 u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
143 int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
144 int i, j;
145 u64 addf = ppmu->add_fields;
146 u64 tadd = ppmu->test_adder;
147
148 if (n_ev > ppmu->n_counter)
149 return -1;
150
151 /* First see if the events will go on as-is */
152 for (i = 0; i < n_ev; ++i) {
153 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
154 && !ppmu->limited_pmc_event(event[i])) {
155 ppmu->get_alternatives(event[i], cflags[i],
156 alternatives[i]);
157 event[i] = alternatives[i][0];
158 }
159 if (ppmu->get_constraint(event[i], &amasks[i][0],
160 &avalues[i][0]))
161 return -1;
162 }
163 value = mask = 0;
164 for (i = 0; i < n_ev; ++i) {
165 nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
166 if ((((nv + tadd) ^ value) & mask) != 0 ||
167 (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
168 break;
169 value = nv;
170 mask |= amasks[i][0];
171 }
172 if (i == n_ev)
173 return 0; /* all OK */
174
175 /* doesn't work, gather alternatives... */
176 if (!ppmu->get_alternatives)
177 return -1;
178 for (i = 0; i < n_ev; ++i) {
179 choice[i] = 0;
180 n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
181 alternatives[i]);
182 for (j = 1; j < n_alt[i]; ++j)
183 ppmu->get_constraint(alternatives[i][j],
184 &amasks[i][j], &avalues[i][j]);
185 }
186
187 /* enumerate all possibilities and see if any will work */
188 i = 0;
189 j = -1;
190 value = mask = nv = 0;
191 while (i < n_ev) {
192 if (j >= 0) {
193 /* we're backtracking, restore context */
194 value = svalues[i];
195 mask = smasks[i];
196 j = choice[i];
197 }
198 /*
199 * See if any alternative k for event i,
200 * where k > j, will satisfy the constraints.
201 */
202 while (++j < n_alt[i]) {
203 nv = (value | avalues[i][j]) +
204 (value & avalues[i][j] & addf);
205 if ((((nv + tadd) ^ value) & mask) == 0 &&
206 (((nv + tadd) ^ avalues[i][j])
207 & amasks[i][j]) == 0)
208 break;
209 }
210 if (j >= n_alt[i]) {
211 /*
212 * No feasible alternative, backtrack
213 * to event i-1 and continue enumerating its
214 * alternatives from where we got up to.
215 */
216 if (--i < 0)
217 return -1;
218 } else {
219 /*
220 * Found a feasible alternative for event i,
221 * remember where we got up to with this event,
222 * go on to the next event, and start with
223 * the first alternative for it.
224 */
225 choice[i] = j;
226 svalues[i] = value;
227 smasks[i] = mask;
228 value = nv;
229 mask |= amasks[i][j];
230 ++i;
231 j = -1;
232 }
233 }
234
235 /* OK, we have a feasible combination, tell the caller the solution */
236 for (i = 0; i < n_ev; ++i)
237 event[i] = alternatives[i][choice[i]];
238 return 0;
239}
240
241/*
242 * Check if newly-added counters have consistent settings for
243 * exclude_{user,kernel,hv} with each other and any previously
244 * added counters.
245 */
246static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
247 int n_prev, int n_new)
248{
249 int eu = 0, ek = 0, eh = 0;
250 int i, n, first;
251 struct perf_counter *counter;
252
253 n = n_prev + n_new;
254 if (n <= 1)
255 return 0;
256
257 first = 1;
258 for (i = 0; i < n; ++i) {
259 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
260 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
261 continue;
262 }
263 counter = ctrs[i];
264 if (first) {
265 eu = counter->attr.exclude_user;
266 ek = counter->attr.exclude_kernel;
267 eh = counter->attr.exclude_hv;
268 first = 0;
269 } else if (counter->attr.exclude_user != eu ||
270 counter->attr.exclude_kernel != ek ||
271 counter->attr.exclude_hv != eh) {
272 return -EAGAIN;
273 }
274 }
275
276 if (eu || ek || eh)
277 for (i = 0; i < n; ++i)
278 if (cflags[i] & PPMU_LIMITED_PMC_OK)
279 cflags[i] |= PPMU_LIMITED_PMC_REQD;
280
281 return 0;
282}
283
284static void power_pmu_read(struct perf_counter *counter)
285{
286 long val, delta, prev;
287
288 if (!counter->hw.idx)
289 return;
290 /*
291 * Performance monitor interrupts come even when interrupts
292 * are soft-disabled, as long as interrupts are hard-enabled.
293 * Therefore we treat them like NMIs.
294 */
295 do {
296 prev = atomic64_read(&counter->hw.prev_count);
297 barrier();
298 val = read_pmc(counter->hw.idx);
299 } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev);
300
301 /* The counters are only 32 bits wide */
302 delta = (val - prev) & 0xfffffffful;
303 atomic64_add(delta, &counter->count);
304 atomic64_sub(delta, &counter->hw.period_left);
305}
306
307/*
308 * On some machines, PMC5 and PMC6 can't be written, don't respect
309 * the freeze conditions, and don't generate interrupts. This tells
310 * us if `counter' is using such a PMC.
311 */
312static int is_limited_pmc(int pmcnum)
313{
314 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
315 && (pmcnum == 5 || pmcnum == 6);
316}
317
318static void freeze_limited_counters(struct cpu_hw_counters *cpuhw,
319 unsigned long pmc5, unsigned long pmc6)
320{
321 struct perf_counter *counter;
322 u64 val, prev, delta;
323 int i;
324
325 for (i = 0; i < cpuhw->n_limited; ++i) {
326 counter = cpuhw->limited_counter[i];
327 if (!counter->hw.idx)
328 continue;
329 val = (counter->hw.idx == 5) ? pmc5 : pmc6;
330 prev = atomic64_read(&counter->hw.prev_count);
331 counter->hw.idx = 0;
332 delta = (val - prev) & 0xfffffffful;
333 atomic64_add(delta, &counter->count);
334 }
335}
336
337static void thaw_limited_counters(struct cpu_hw_counters *cpuhw,
338 unsigned long pmc5, unsigned long pmc6)
339{
340 struct perf_counter *counter;
341 u64 val;
342 int i;
343
344 for (i = 0; i < cpuhw->n_limited; ++i) {
345 counter = cpuhw->limited_counter[i];
346 counter->hw.idx = cpuhw->limited_hwidx[i];
347 val = (counter->hw.idx == 5) ? pmc5 : pmc6;
348 atomic64_set(&counter->hw.prev_count, val);
349 perf_counter_update_userpage(counter);
350 }
351}
352
353/*
354 * Since limited counters don't respect the freeze conditions, we
355 * have to read them immediately after freezing or unfreezing the
356 * other counters. We try to keep the values from the limited
357 * counters as consistent as possible by keeping the delay (in
358 * cycles and instructions) between freezing/unfreezing and reading
359 * the limited counters as small and consistent as possible.
360 * Therefore, if any limited counters are in use, we read them
361 * both, and always in the same order, to minimize variability,
362 * and do it inside the same asm that writes MMCR0.
363 */
364static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
365{
366 unsigned long pmc5, pmc6;
367
368 if (!cpuhw->n_limited) {
369 mtspr(SPRN_MMCR0, mmcr0);
370 return;
371 }
372
373 /*
374 * Write MMCR0, then read PMC5 and PMC6 immediately.
375 * To ensure we don't get a performance monitor interrupt
376 * between writing MMCR0 and freezing/thawing the limited
377 * counters, we first write MMCR0 with the counter overflow
378 * interrupt enable bits turned off.
379 */
380 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
381 : "=&r" (pmc5), "=&r" (pmc6)
382 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
383 "i" (SPRN_MMCR0),
384 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
385
386 if (mmcr0 & MMCR0_FC)
387 freeze_limited_counters(cpuhw, pmc5, pmc6);
388 else
389 thaw_limited_counters(cpuhw, pmc5, pmc6);
390
391 /*
392 * Write the full MMCR0 including the counter overflow interrupt
393 * enable bits, if necessary.
394 */
395 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
396 mtspr(SPRN_MMCR0, mmcr0);
397}
398
399/*
400 * Disable all counters to prevent PMU interrupts and to allow
401 * counters to be added or removed.
402 */
403void hw_perf_disable(void)
404{
405 struct cpu_hw_counters *cpuhw;
406 unsigned long ret;
407 unsigned long flags;
408
409 local_irq_save(flags);
410 cpuhw = &__get_cpu_var(cpu_hw_counters);
411
412 ret = cpuhw->disabled;
413 if (!ret) {
414 cpuhw->disabled = 1;
415 cpuhw->n_added = 0;
416
417 /*
418 * Check if we ever enabled the PMU on this cpu.
419 */
420 if (!cpuhw->pmcs_enabled) {
421 if (ppc_md.enable_pmcs)
422 ppc_md.enable_pmcs();
423 cpuhw->pmcs_enabled = 1;
424 }
425
426 /*
427 * Disable instruction sampling if it was enabled
428 */
429 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
430 mtspr(SPRN_MMCRA,
431 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
432 mb();
433 }
434
435 /*
436 * Set the 'freeze counters' bit.
437 * The barrier is to make sure the mtspr has been
438 * executed and the PMU has frozen the counters
439 * before we return.
440 */
441 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
442 mb();
443 }
444 local_irq_restore(flags);
445}
446
447/*
448 * Re-enable all counters if disable == 0.
449 * If we were previously disabled and counters were added, then
450 * put the new config on the PMU.
451 */
452void hw_perf_enable(void)
453{
454 struct perf_counter *counter;
455 struct cpu_hw_counters *cpuhw;
456 unsigned long flags;
457 long i;
458 unsigned long val;
459 s64 left;
460 unsigned int hwc_index[MAX_HWCOUNTERS];
461 int n_lim;
462 int idx;
463
464 local_irq_save(flags);
465 cpuhw = &__get_cpu_var(cpu_hw_counters);
466 if (!cpuhw->disabled) {
467 local_irq_restore(flags);
468 return;
469 }
470 cpuhw->disabled = 0;
471
472 /*
473 * If we didn't change anything, or only removed counters,
474 * no need to recalculate MMCR* settings and reset the PMCs.
475 * Just reenable the PMU with the current MMCR* settings
476 * (possibly updated for removal of counters).
477 */
478 if (!cpuhw->n_added) {
479 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
480 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
481 if (cpuhw->n_counters == 0)
482 get_lppaca()->pmcregs_in_use = 0;
483 goto out_enable;
484 }
485
486 /*
487 * Compute MMCR* values for the new set of counters
488 */
489 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index,
490 cpuhw->mmcr)) {
491 /* shouldn't ever get here */
492 printk(KERN_ERR "oops compute_mmcr failed\n");
493 goto out;
494 }
495
496 /*
497 * Add in MMCR0 freeze bits corresponding to the
498 * attr.exclude_* bits for the first counter.
499 * We have already checked that all counters have the
500 * same values for these bits as the first counter.
501 */
502 counter = cpuhw->counter[0];
503 if (counter->attr.exclude_user)
504 cpuhw->mmcr[0] |= MMCR0_FCP;
505 if (counter->attr.exclude_kernel)
506 cpuhw->mmcr[0] |= freeze_counters_kernel;
507 if (counter->attr.exclude_hv)
508 cpuhw->mmcr[0] |= MMCR0_FCHV;
509
510 /*
511 * Write the new configuration to MMCR* with the freeze
512 * bit set and set the hardware counters to their initial values.
513 * Then unfreeze the counters.
514 */
515 get_lppaca()->pmcregs_in_use = 1;
516 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
517 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
518 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
519 | MMCR0_FC);
520
521 /*
522 * Read off any pre-existing counters that need to move
523 * to another PMC.
524 */
525 for (i = 0; i < cpuhw->n_counters; ++i) {
526 counter = cpuhw->counter[i];
527 if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) {
528 power_pmu_read(counter);
529 write_pmc(counter->hw.idx, 0);
530 counter->hw.idx = 0;
531 }
532 }
533
534 /*
535 * Initialize the PMCs for all the new and moved counters.
536 */
537 cpuhw->n_limited = n_lim = 0;
538 for (i = 0; i < cpuhw->n_counters; ++i) {
539 counter = cpuhw->counter[i];
540 if (counter->hw.idx)
541 continue;
542 idx = hwc_index[i] + 1;
543 if (is_limited_pmc(idx)) {
544 cpuhw->limited_counter[n_lim] = counter;
545 cpuhw->limited_hwidx[n_lim] = idx;
546 ++n_lim;
547 continue;
548 }
549 val = 0;
550 if (counter->hw.sample_period) {
551 left = atomic64_read(&counter->hw.period_left);
552 if (left < 0x80000000L)
553 val = 0x80000000L - left;
554 }
555 atomic64_set(&counter->hw.prev_count, val);
556 counter->hw.idx = idx;
557 write_pmc(idx, val);
558 perf_counter_update_userpage(counter);
559 }
560 cpuhw->n_limited = n_lim;
561 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
562
563 out_enable:
564 mb();
565 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
566
567 /*
568 * Enable instruction sampling if necessary
569 */
570 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
571 mb();
572 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
573 }
574
575 out:
576 local_irq_restore(flags);
577}
578
579static int collect_events(struct perf_counter *group, int max_count,
580 struct perf_counter *ctrs[], u64 *events,
581 unsigned int *flags)
582{
583 int n = 0;
584 struct perf_counter *counter;
585
586 if (!is_software_counter(group)) {
587 if (n >= max_count)
588 return -1;
589 ctrs[n] = group;
590 flags[n] = group->hw.counter_base;
591 events[n++] = group->hw.config;
592 }
593 list_for_each_entry(counter, &group->sibling_list, list_entry) {
594 if (!is_software_counter(counter) &&
595 counter->state != PERF_COUNTER_STATE_OFF) {
596 if (n >= max_count)
597 return -1;
598 ctrs[n] = counter;
599 flags[n] = counter->hw.counter_base;
600 events[n++] = counter->hw.config;
601 }
602 }
603 return n;
604}
605
606static void counter_sched_in(struct perf_counter *counter, int cpu)
607{
608 counter->state = PERF_COUNTER_STATE_ACTIVE;
609 counter->oncpu = cpu;
610 counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped;
611 if (is_software_counter(counter))
612 counter->pmu->enable(counter);
613}
614
615/*
616 * Called to enable a whole group of counters.
617 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
618 * Assumes the caller has disabled interrupts and has
619 * frozen the PMU with hw_perf_save_disable.
620 */
621int hw_perf_group_sched_in(struct perf_counter *group_leader,
622 struct perf_cpu_context *cpuctx,
623 struct perf_counter_context *ctx, int cpu)
624{
625 struct cpu_hw_counters *cpuhw;
626 long i, n, n0;
627 struct perf_counter *sub;
628
629 cpuhw = &__get_cpu_var(cpu_hw_counters);
630 n0 = cpuhw->n_counters;
631 n = collect_events(group_leader, ppmu->n_counter - n0,
632 &cpuhw->counter[n0], &cpuhw->events[n0],
633 &cpuhw->flags[n0]);
634 if (n < 0)
635 return -EAGAIN;
636 if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
637 return -EAGAIN;
638 i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
639 if (i < 0)
640 return -EAGAIN;
641 cpuhw->n_counters = n0 + n;
642 cpuhw->n_added += n;
643
644 /*
645 * OK, this group can go on; update counter states etc.,
646 * and enable any software counters
647 */
648 for (i = n0; i < n0 + n; ++i)
649 cpuhw->counter[i]->hw.config = cpuhw->events[i];
650 cpuctx->active_oncpu += n;
651 n = 1;
652 counter_sched_in(group_leader, cpu);
653 list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
654 if (sub->state != PERF_COUNTER_STATE_OFF) {
655 counter_sched_in(sub, cpu);
656 ++n;
657 }
658 }
659 ctx->nr_active += n;
660
661 return 1;
662}
663
664/*
665 * Add a counter to the PMU.
666 * If all counters are not already frozen, then we disable and
667 * re-enable the PMU in order to get hw_perf_enable to do the
668 * actual work of reconfiguring the PMU.
669 */
670static int power_pmu_enable(struct perf_counter *counter)
671{
672 struct cpu_hw_counters *cpuhw;
673 unsigned long flags;
674 int n0;
675 int ret = -EAGAIN;
676
677 local_irq_save(flags);
678 perf_disable();
679
680 /*
681 * Add the counter to the list (if there is room)
682 * and check whether the total set is still feasible.
683 */
684 cpuhw = &__get_cpu_var(cpu_hw_counters);
685 n0 = cpuhw->n_counters;
686 if (n0 >= ppmu->n_counter)
687 goto out;
688 cpuhw->counter[n0] = counter;
689 cpuhw->events[n0] = counter->hw.config;
690 cpuhw->flags[n0] = counter->hw.counter_base;
691 if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
692 goto out;
693 if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
694 goto out;
695
696 counter->hw.config = cpuhw->events[n0];
697 ++cpuhw->n_counters;
698 ++cpuhw->n_added;
699
700 ret = 0;
701 out:
702 perf_enable();
703 local_irq_restore(flags);
704 return ret;
705}
706
707/*
708 * Remove a counter from the PMU.
709 */
710static void power_pmu_disable(struct perf_counter *counter)
711{
712 struct cpu_hw_counters *cpuhw;
713 long i;
714 unsigned long flags;
715
716 local_irq_save(flags);
717 perf_disable();
718
719 power_pmu_read(counter);
720
721 cpuhw = &__get_cpu_var(cpu_hw_counters);
722 for (i = 0; i < cpuhw->n_counters; ++i) {
723 if (counter == cpuhw->counter[i]) {
724 while (++i < cpuhw->n_counters)
725 cpuhw->counter[i-1] = cpuhw->counter[i];
726 --cpuhw->n_counters;
727 ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr);
728 if (counter->hw.idx) {
729 write_pmc(counter->hw.idx, 0);
730 counter->hw.idx = 0;
731 }
732 perf_counter_update_userpage(counter);
733 break;
734 }
735 }
736 for (i = 0; i < cpuhw->n_limited; ++i)
737 if (counter == cpuhw->limited_counter[i])
738 break;
739 if (i < cpuhw->n_limited) {
740 while (++i < cpuhw->n_limited) {
741 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
742 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
743 }
744 --cpuhw->n_limited;
745 }
746 if (cpuhw->n_counters == 0) {
747 /* disable exceptions if no counters are running */
748 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
749 }
750
751 perf_enable();
752 local_irq_restore(flags);
753}
754
755/*
756 * Re-enable interrupts on a counter after they were throttled
757 * because they were coming too fast.
758 */
759static void power_pmu_unthrottle(struct perf_counter *counter)
760{
761 s64 val, left;
762 unsigned long flags;
763
764 if (!counter->hw.idx || !counter->hw.sample_period)
765 return;
766 local_irq_save(flags);
767 perf_disable();
768 power_pmu_read(counter);
769 left = counter->hw.sample_period;
770 counter->hw.last_period = left;
771 val = 0;
772 if (left < 0x80000000L)
773 val = 0x80000000L - left;
774 write_pmc(counter->hw.idx, val);
775 atomic64_set(&counter->hw.prev_count, val);
776 atomic64_set(&counter->hw.period_left, left);
777 perf_counter_update_userpage(counter);
778 perf_enable();
779 local_irq_restore(flags);
780}
781
782struct pmu power_pmu = {
783 .enable = power_pmu_enable,
784 .disable = power_pmu_disable,
785 .read = power_pmu_read,
786 .unthrottle = power_pmu_unthrottle,
787};
788
789/*
790 * Return 1 if we might be able to put counter on a limited PMC,
791 * or 0 if not.
792 * A counter can only go on a limited PMC if it counts something
793 * that a limited PMC can count, doesn't require interrupts, and
794 * doesn't exclude any processor mode.
795 */
796static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev,
797 unsigned int flags)
798{
799 int n;
800 u64 alt[MAX_EVENT_ALTERNATIVES];
801
802 if (counter->attr.exclude_user
803 || counter->attr.exclude_kernel
804 || counter->attr.exclude_hv
805 || counter->attr.sample_period)
806 return 0;
807
808 if (ppmu->limited_pmc_event(ev))
809 return 1;
810
811 /*
812 * The requested event isn't on a limited PMC already;
813 * see if any alternative code goes on a limited PMC.
814 */
815 if (!ppmu->get_alternatives)
816 return 0;
817
818 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
819 n = ppmu->get_alternatives(ev, flags, alt);
820
821 return n > 0;
822}
823
824/*
825 * Find an alternative event that goes on a normal PMC, if possible,
826 * and return the event code, or 0 if there is no such alternative.
827 * (Note: event code 0 is "don't count" on all machines.)
828 */
829static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
830{
831 u64 alt[MAX_EVENT_ALTERNATIVES];
832 int n;
833
834 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
835 n = ppmu->get_alternatives(ev, flags, alt);
836 if (!n)
837 return 0;
838 return alt[0];
839}
840
841/* Number of perf_counters counting hardware events */
842static atomic_t num_counters;
843/* Used to avoid races in calling reserve/release_pmc_hardware */
844static DEFINE_MUTEX(pmc_reserve_mutex);
845
846/*
847 * Release the PMU if this is the last perf_counter.
848 */
849static void hw_perf_counter_destroy(struct perf_counter *counter)
850{
851 if (!atomic_add_unless(&num_counters, -1, 1)) {
852 mutex_lock(&pmc_reserve_mutex);
853 if (atomic_dec_return(&num_counters) == 0)
854 release_pmc_hardware();
855 mutex_unlock(&pmc_reserve_mutex);
856 }
857}
858
859/*
860 * Translate a generic cache event config to a raw event code.
861 */
862static int hw_perf_cache_event(u64 config, u64 *eventp)
863{
864 unsigned long type, op, result;
865 int ev;
866
867 if (!ppmu->cache_events)
868 return -EINVAL;
869
870 /* unpack config */
871 type = config & 0xff;
872 op = (config >> 8) & 0xff;
873 result = (config >> 16) & 0xff;
874
875 if (type >= PERF_COUNT_HW_CACHE_MAX ||
876 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
877 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
878 return -EINVAL;
879
880 ev = (*ppmu->cache_events)[type][op][result];
881 if (ev == 0)
882 return -EOPNOTSUPP;
883 if (ev == -1)
884 return -EINVAL;
885 *eventp = ev;
886 return 0;
887}
888
889const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
890{
891 u64 ev;
892 unsigned long flags;
893 struct perf_counter *ctrs[MAX_HWCOUNTERS];
894 u64 events[MAX_HWCOUNTERS];
895 unsigned int cflags[MAX_HWCOUNTERS];
896 int n;
897 int err;
898
899 if (!ppmu)
900 return ERR_PTR(-ENXIO);
901 switch (counter->attr.type) {
902 case PERF_TYPE_HARDWARE:
903 ev = counter->attr.config;
904 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
905 return ERR_PTR(-EOPNOTSUPP);
906 ev = ppmu->generic_events[ev];
907 break;
908 case PERF_TYPE_HW_CACHE:
909 err = hw_perf_cache_event(counter->attr.config, &ev);
910 if (err)
911 return ERR_PTR(err);
912 break;
913 case PERF_TYPE_RAW:
914 ev = counter->attr.config;
915 break;
916 }
917 counter->hw.config_base = ev;
918 counter->hw.idx = 0;
919
920 /*
921 * If we are not running on a hypervisor, force the
922 * exclude_hv bit to 0 so that we don't care what
923 * the user set it to.
924 */
925 if (!firmware_has_feature(FW_FEATURE_LPAR))
926 counter->attr.exclude_hv = 0;
927
928 /*
929 * If this is a per-task counter, then we can use
930 * PM_RUN_* events interchangeably with their non RUN_*
931 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
932 * XXX we should check if the task is an idle task.
933 */
934 flags = 0;
935 if (counter->ctx->task)
936 flags |= PPMU_ONLY_COUNT_RUN;
937
938 /*
939 * If this machine has limited counters, check whether this
940 * event could go on a limited counter.
941 */
942 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
943 if (can_go_on_limited_pmc(counter, ev, flags)) {
944 flags |= PPMU_LIMITED_PMC_OK;
945 } else if (ppmu->limited_pmc_event(ev)) {
946 /*
947 * The requested event is on a limited PMC,
948 * but we can't use a limited PMC; see if any
949 * alternative goes on a normal PMC.
950 */
951 ev = normal_pmc_alternative(ev, flags);
952 if (!ev)
953 return ERR_PTR(-EINVAL);
954 }
955 }
956
957 /*
958 * If this is in a group, check if it can go on with all the
959 * other hardware counters in the group. We assume the counter
960 * hasn't been linked into its leader's sibling list at this point.
961 */
962 n = 0;
963 if (counter->group_leader != counter) {
964 n = collect_events(counter->group_leader, ppmu->n_counter - 1,
965 ctrs, events, cflags);
966 if (n < 0)
967 return ERR_PTR(-EINVAL);
968 }
969 events[n] = ev;
970 ctrs[n] = counter;
971 cflags[n] = flags;
972 if (check_excludes(ctrs, cflags, n, 1))
973 return ERR_PTR(-EINVAL);
974 if (power_check_constraints(events, cflags, n + 1))
975 return ERR_PTR(-EINVAL);
976
977 counter->hw.config = events[n];
978 counter->hw.counter_base = cflags[n];
979 counter->hw.last_period = counter->hw.sample_period;
980 atomic64_set(&counter->hw.period_left, counter->hw.last_period);
981
982 /*
983 * See if we need to reserve the PMU.
984 * If no counters are currently in use, then we have to take a
985 * mutex to ensure that we don't race with another task doing
986 * reserve_pmc_hardware or release_pmc_hardware.
987 */
988 err = 0;
989 if (!atomic_inc_not_zero(&num_counters)) {
990 mutex_lock(&pmc_reserve_mutex);
991 if (atomic_read(&num_counters) == 0 &&
992 reserve_pmc_hardware(perf_counter_interrupt))
993 err = -EBUSY;
994 else
995 atomic_inc(&num_counters);
996 mutex_unlock(&pmc_reserve_mutex);
997 }
998 counter->destroy = hw_perf_counter_destroy;
999
1000 if (err)
1001 return ERR_PTR(err);
1002 return &power_pmu;
1003}
1004
1005/*
1006 * A counter has overflowed; update its count and record
1007 * things if requested. Note that interrupts are hard-disabled
1008 * here so there is no possibility of being interrupted.
1009 */
1010static void record_and_restart(struct perf_counter *counter, long val,
1011 struct pt_regs *regs, int nmi)
1012{
1013 u64 period = counter->hw.sample_period;
1014 s64 prev, delta, left;
1015 int record = 0;
1016 u64 addr, mmcra, sdsync;
1017
1018 /* we don't have to worry about interrupts here */
1019 prev = atomic64_read(&counter->hw.prev_count);
1020 delta = (val - prev) & 0xfffffffful;
1021 atomic64_add(delta, &counter->count);
1022
1023 /*
1024 * See if the total period for this counter has expired,
1025 * and update for the next period.
1026 */
1027 val = 0;
1028 left = atomic64_read(&counter->hw.period_left) - delta;
1029 if (period) {
1030 if (left <= 0) {
1031 left += period;
1032 if (left <= 0)
1033 left = period;
1034 record = 1;
1035 }
1036 if (left < 0x80000000L)
1037 val = 0x80000000L - left;
1038 }
1039
1040 /*
1041 * Finally record data if requested.
1042 */
1043 if (record) {
1044 struct perf_sample_data data = {
1045 .regs = regs,
1046 .addr = 0,
1047 .period = counter->hw.last_period,
1048 };
1049
1050 if (counter->attr.sample_type & PERF_SAMPLE_ADDR) {
1051 /*
1052 * The user wants a data address recorded.
1053 * If we're not doing instruction sampling,
1054 * give them the SDAR (sampled data address).
1055 * If we are doing instruction sampling, then only
1056 * give them the SDAR if it corresponds to the
1057 * instruction pointed to by SIAR; this is indicated
1058 * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA.
1059 */
1060 mmcra = regs->dsisr;
1061 sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
1062 POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
1063 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
1064 data.addr = mfspr(SPRN_SDAR);
1065 }
1066 if (perf_counter_overflow(counter, nmi, &data)) {
1067 /*
1068 * Interrupts are coming too fast - throttle them
1069 * by setting the counter to 0, so it will be
1070 * at least 2^30 cycles until the next interrupt
1071 * (assuming each counter counts at most 2 counts
1072 * per cycle).
1073 */
1074 val = 0;
1075 left = ~0ULL >> 1;
1076 }
1077 }
1078
1079 write_pmc(counter->hw.idx, val);
1080 atomic64_set(&counter->hw.prev_count, val);
1081 atomic64_set(&counter->hw.period_left, left);
1082 perf_counter_update_userpage(counter);
1083}
1084
1085/*
1086 * Called from generic code to get the misc flags (i.e. processor mode)
1087 * for an event.
1088 */
1089unsigned long perf_misc_flags(struct pt_regs *regs)
1090{
1091 unsigned long mmcra;
1092
1093 if (TRAP(regs) != 0xf00) {
1094 /* not a PMU interrupt */
1095 return user_mode(regs) ? PERF_EVENT_MISC_USER :
1096 PERF_EVENT_MISC_KERNEL;
1097 }
1098
1099 mmcra = regs->dsisr;
1100 if (ppmu->flags & PPMU_ALT_SIPR) {
1101 if (mmcra & POWER6_MMCRA_SIHV)
1102 return PERF_EVENT_MISC_HYPERVISOR;
1103 return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
1104 PERF_EVENT_MISC_KERNEL;
1105 }
1106 if (mmcra & MMCRA_SIHV)
1107 return PERF_EVENT_MISC_HYPERVISOR;
1108 return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
1109 PERF_EVENT_MISC_KERNEL;
1110}
1111
1112/*
1113 * Called from generic code to get the instruction pointer
1114 * for an event.
1115 */
1116unsigned long perf_instruction_pointer(struct pt_regs *regs)
1117{
1118 unsigned long mmcra;
1119 unsigned long ip;
1120 unsigned long slot;
1121
1122 if (TRAP(regs) != 0xf00)
1123 return regs->nip; /* not a PMU interrupt */
1124
1125 ip = mfspr(SPRN_SIAR);
1126 mmcra = regs->dsisr;
1127 if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
1128 slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
1129 if (slot > 1)
1130 ip += 4 * (slot - 1);
1131 }
1132 return ip;
1133}
1134
1135/*
1136 * Performance monitor interrupt stuff
1137 */
1138static void perf_counter_interrupt(struct pt_regs *regs)
1139{
1140 int i;
1141 struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
1142 struct perf_counter *counter;
1143 long val;
1144 int found = 0;
1145 int nmi;
1146
1147 if (cpuhw->n_limited)
1148 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1149 mfspr(SPRN_PMC6));
1150
1151 /*
1152 * Overload regs->dsisr to store MMCRA so we only need to read it once.
1153 */
1154 regs->dsisr = mfspr(SPRN_MMCRA);
1155
1156 /*
1157 * If interrupts were soft-disabled when this PMU interrupt
1158 * occurred, treat it as an NMI.
1159 */
1160 nmi = !regs->softe;
1161 if (nmi)
1162 nmi_enter();
1163 else
1164 irq_enter();
1165
1166 for (i = 0; i < cpuhw->n_counters; ++i) {
1167 counter = cpuhw->counter[i];
1168 if (!counter->hw.idx || is_limited_pmc(counter->hw.idx))
1169 continue;
1170 val = read_pmc(counter->hw.idx);
1171 if ((int)val < 0) {
1172 /* counter has overflowed */
1173 found = 1;
1174 record_and_restart(counter, val, regs, nmi);
1175 }
1176 }
1177
1178 /*
1179 * In case we didn't find and reset the counter that caused
1180 * the interrupt, scan all counters and reset any that are
1181 * negative, to avoid getting continual interrupts.
1182 * Any that we processed in the previous loop will not be negative.
1183 */
1184 if (!found) {
1185 for (i = 0; i < ppmu->n_counter; ++i) {
1186 if (is_limited_pmc(i + 1))
1187 continue;
1188 val = read_pmc(i + 1);
1189 if ((int)val < 0)
1190 write_pmc(i + 1, 0);
1191 }
1192 }
1193
1194 /*
1195 * Reset MMCR0 to its normal value. This will set PMXE and
1196 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1197 * and thus allow interrupts to occur again.
1198 * XXX might want to use MSR.PM to keep the counters frozen until
1199 * we get back out of this interrupt.
1200 */
1201 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1202
1203 if (nmi)
1204 nmi_exit();
1205 else
1206 irq_exit();
1207}
1208
1209void hw_perf_counter_setup(int cpu)
1210{
1211 struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu);
1212
1213 memset(cpuhw, 0, sizeof(*cpuhw));
1214 cpuhw->mmcr[0] = MMCR0_FC;
1215}
1216
1217extern struct power_pmu power4_pmu;
1218extern struct power_pmu ppc970_pmu;
1219extern struct power_pmu power5_pmu;
1220extern struct power_pmu power5p_pmu;
1221extern struct power_pmu power6_pmu;
1222extern struct power_pmu power7_pmu;
1223
1224static int init_perf_counters(void)
1225{
1226 unsigned long pvr;
1227
1228 /* XXX should get this from cputable */
1229 pvr = mfspr(SPRN_PVR);
1230 switch (PVR_VER(pvr)) {
1231 case PV_POWER4:
1232 case PV_POWER4p:
1233 ppmu = &power4_pmu;
1234 break;
1235 case PV_970:
1236 case PV_970FX:
1237 case PV_970MP:
1238 ppmu = &ppc970_pmu;
1239 break;
1240 case PV_POWER5:
1241 ppmu = &power5_pmu;
1242 break;
1243 case PV_POWER5p:
1244 ppmu = &power5p_pmu;
1245 break;
1246 case 0x3e:
1247 ppmu = &power6_pmu;
1248 break;
1249 case 0x3f:
1250 ppmu = &power7_pmu;
1251 break;
1252 }
1253
1254 /*
1255 * Use FCHV to ignore kernel events if MSR.HV is set.
1256 */
1257 if (mfmsr() & MSR_HV)
1258 freeze_counters_kernel = MMCR0_FCHV;
1259
1260 return 0;
1261}
1262
1263arch_initcall(init_perf_counters);
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
new file mode 100644
index 000000000000..07bd308a5fa7
--- /dev/null
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -0,0 +1,598 @@
1/*
2 * Performance counter support for POWER4 (GP) and POWER4+ (GQ) processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER4
17 */
18#define PM_PMC_SH 12 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */
21#define PM_UNIT_MSK 0xf
22#define PM_LOWER_SH 6
23#define PM_LOWER_MSK 1
24#define PM_LOWER_MSKS 0x40
25#define PM_BYTE_SH 4 /* Byte number of event bus to use */
26#define PM_BYTE_MSK 3
27#define PM_PMCSEL_MSK 7
28
29/*
30 * Unit code values
31 */
32#define PM_FPU 1
33#define PM_ISU1 2
34#define PM_IFU 3
35#define PM_IDU0 4
36#define PM_ISU1_ALT 6
37#define PM_ISU2 7
38#define PM_IFU_ALT 8
39#define PM_LSU0 9
40#define PM_LSU1 0xc
41#define PM_GPS 0xf
42
43/*
44 * Bits in MMCR0 for POWER4
45 */
46#define MMCR0_PMC1SEL_SH 8
47#define MMCR0_PMC2SEL_SH 1
48#define MMCR_PMCSEL_MSK 0x1f
49
50/*
51 * Bits in MMCR1 for POWER4
52 */
53#define MMCR1_TTM0SEL_SH 62
54#define MMCR1_TTC0SEL_SH 61
55#define MMCR1_TTM1SEL_SH 59
56#define MMCR1_TTC1SEL_SH 58
57#define MMCR1_TTM2SEL_SH 56
58#define MMCR1_TTC2SEL_SH 55
59#define MMCR1_TTM3SEL_SH 53
60#define MMCR1_TTC3SEL_SH 52
61#define MMCR1_TTMSEL_MSK 3
62#define MMCR1_TD_CP_DBG0SEL_SH 50
63#define MMCR1_TD_CP_DBG1SEL_SH 48
64#define MMCR1_TD_CP_DBG2SEL_SH 46
65#define MMCR1_TD_CP_DBG3SEL_SH 44
66#define MMCR1_DEBUG0SEL_SH 43
67#define MMCR1_DEBUG1SEL_SH 42
68#define MMCR1_DEBUG2SEL_SH 41
69#define MMCR1_DEBUG3SEL_SH 40
70#define MMCR1_PMC1_ADDER_SEL_SH 39
71#define MMCR1_PMC2_ADDER_SEL_SH 38
72#define MMCR1_PMC6_ADDER_SEL_SH 37
73#define MMCR1_PMC5_ADDER_SEL_SH 36
74#define MMCR1_PMC8_ADDER_SEL_SH 35
75#define MMCR1_PMC7_ADDER_SEL_SH 34
76#define MMCR1_PMC3_ADDER_SEL_SH 33
77#define MMCR1_PMC4_ADDER_SEL_SH 32
78#define MMCR1_PMC3SEL_SH 27
79#define MMCR1_PMC4SEL_SH 22
80#define MMCR1_PMC5SEL_SH 17
81#define MMCR1_PMC6SEL_SH 12
82#define MMCR1_PMC7SEL_SH 7
83#define MMCR1_PMC8SEL_SH 2 /* note bit 0 is in MMCRA for GP */
84
85static short mmcr1_adder_bits[8] = {
86 MMCR1_PMC1_ADDER_SEL_SH,
87 MMCR1_PMC2_ADDER_SEL_SH,
88 MMCR1_PMC3_ADDER_SEL_SH,
89 MMCR1_PMC4_ADDER_SEL_SH,
90 MMCR1_PMC5_ADDER_SEL_SH,
91 MMCR1_PMC6_ADDER_SEL_SH,
92 MMCR1_PMC7_ADDER_SEL_SH,
93 MMCR1_PMC8_ADDER_SEL_SH
94};
95
96/*
97 * Bits in MMCRA
98 */
99#define MMCRA_PMC8SEL0_SH 17 /* PMC8SEL bit 0 for GP */
100
101/*
102 * Layout of constraint bits:
103 * 6666555555555544444444443333333333222222222211111111110000000000
104 * 3210987654321098765432109876543210987654321098765432109876543210
105 * |[ >[ >[ >|||[ >[ >< >< >< >< ><><><><><><><><>
106 * | UC1 UC2 UC3 ||| PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
107 * \SMPL ||\TTC3SEL
108 * |\TTC_IFU_SEL
109 * \TTM2SEL0
110 *
111 * SMPL - SAMPLE_ENABLE constraint
112 * 56: SAMPLE_ENABLE value 0x0100_0000_0000_0000
113 *
114 * UC1 - unit constraint 1: can't have all three of FPU/ISU1/IDU0|ISU2
115 * 55: UC1 error 0x0080_0000_0000_0000
116 * 54: FPU events needed 0x0040_0000_0000_0000
117 * 53: ISU1 events needed 0x0020_0000_0000_0000
118 * 52: IDU0|ISU2 events needed 0x0010_0000_0000_0000
119 *
120 * UC2 - unit constraint 2: can't have all three of FPU/IFU/LSU0
121 * 51: UC2 error 0x0008_0000_0000_0000
122 * 50: FPU events needed 0x0004_0000_0000_0000
123 * 49: IFU events needed 0x0002_0000_0000_0000
124 * 48: LSU0 events needed 0x0001_0000_0000_0000
125 *
126 * UC3 - unit constraint 3: can't have all four of LSU0/IFU/IDU0|ISU2/ISU1
127 * 47: UC3 error 0x8000_0000_0000
128 * 46: LSU0 events needed 0x4000_0000_0000
129 * 45: IFU events needed 0x2000_0000_0000
130 * 44: IDU0|ISU2 events needed 0x1000_0000_0000
131 * 43: ISU1 events needed 0x0800_0000_0000
132 *
133 * TTM2SEL0
134 * 42: 0 = IDU0 events needed
135 * 1 = ISU2 events needed 0x0400_0000_0000
136 *
137 * TTC_IFU_SEL
138 * 41: 0 = IFU.U events needed
139 * 1 = IFU.L events needed 0x0200_0000_0000
140 *
141 * TTC3SEL
142 * 40: 0 = LSU1.U events needed
143 * 1 = LSU1.L events needed 0x0100_0000_0000
144 *
145 * PS1
146 * 39: PS1 error 0x0080_0000_0000
147 * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
148 *
149 * PS2
150 * 35: PS2 error 0x0008_0000_0000
151 * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
152 *
153 * B0
154 * 28-31: Byte 0 event source 0xf000_0000
155 * 1 = FPU
156 * 2 = ISU1
157 * 3 = IFU
158 * 4 = IDU0
159 * 7 = ISU2
160 * 9 = LSU0
161 * c = LSU1
162 * f = GPS
163 *
164 * B1, B2, B3
165 * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
166 *
167 * P8
168 * 15: P8 error 0x8000
169 * 14-15: Count of events needing PMC8
170 *
171 * P1..P7
172 * 0-13: Count of events needing PMC1..PMC7
173 *
174 * Note: this doesn't allow events using IFU.U to be combined with events
175 * using IFU.L, though that is feasible (using TTM0 and TTM2). However
176 * there are no listed events for IFU.L (they are debug events not
177 * verified for performance monitoring) so this shouldn't cause a
178 * problem.
179 */
180
181static struct unitinfo {
182 u64 value, mask;
183 int unit;
184 int lowerbit;
185} p4_unitinfo[16] = {
186 [PM_FPU] = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 },
187 [PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },
188 [PM_ISU1_ALT] =
189 { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 },
190 [PM_IFU] = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },
191 [PM_IFU_ALT] =
192 { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 },
193 [PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 },
194 [PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 },
195 [PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 },
196 [PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 },
197 [PM_GPS] = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 }
198};
199
200static unsigned char direct_marked_event[8] = {
201 (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
202 (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
203 (1<<3), /* PMC3: PM_MRK_ST_CMPL_INT */
204 (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
205 (1<<4) | (1<<5), /* PMC5: PM_MRK_GRP_TIMEO */
206 (1<<3) | (1<<4) | (1<<5),
207 /* PMC6: PM_MRK_ST_GPS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
208 (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
209 (1<<4), /* PMC8: PM_MRK_LSU_FIN */
210};
211
212/*
213 * Returns 1 if event counts things relating to marked instructions
214 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
215 */
216static int p4_marked_instr_event(u64 event)
217{
218 int pmc, psel, unit, byte, bit;
219 unsigned int mask;
220
221 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
222 psel = event & PM_PMCSEL_MSK;
223 if (pmc) {
224 if (direct_marked_event[pmc - 1] & (1 << psel))
225 return 1;
226 if (psel == 0) /* add events */
227 bit = (pmc <= 4)? pmc - 1: 8 - pmc;
228 else if (psel == 6) /* decode events */
229 bit = 4;
230 else
231 return 0;
232 } else
233 bit = psel;
234
235 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
236 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
237 mask = 0;
238 switch (unit) {
239 case PM_LSU1:
240 if (event & PM_LOWER_MSKS)
241 mask = 1 << 28; /* byte 7 bit 4 */
242 else
243 mask = 6 << 24; /* byte 3 bits 1 and 2 */
244 break;
245 case PM_LSU0:
246 /* byte 3, bit 3; byte 2 bits 0,2,3,4,5; byte 1 */
247 mask = 0x083dff00;
248 }
249 return (mask >> (byte * 8 + bit)) & 1;
250}
251
252static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp)
253{
254 int pmc, byte, unit, lower, sh;
255 u64 mask = 0, value = 0;
256 int grp = -1;
257
258 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
259 if (pmc) {
260 if (pmc > 8)
261 return -1;
262 sh = (pmc - 1) * 2;
263 mask |= 2 << sh;
264 value |= 1 << sh;
265 grp = ((pmc - 1) >> 1) & 1;
266 }
267 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
268 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
269 if (unit) {
270 lower = (event >> PM_LOWER_SH) & PM_LOWER_MSK;
271
272 /*
273 * Bus events on bytes 0 and 2 can be counted
274 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
275 */
276 if (!pmc)
277 grp = byte & 1;
278
279 if (!p4_unitinfo[unit].unit)
280 return -1;
281 mask |= p4_unitinfo[unit].mask;
282 value |= p4_unitinfo[unit].value;
283 sh = p4_unitinfo[unit].lowerbit;
284 if (sh > 1)
285 value |= (u64)lower << sh;
286 else if (lower != sh)
287 return -1;
288 unit = p4_unitinfo[unit].unit;
289
290 /* Set byte lane select field */
291 mask |= 0xfULL << (28 - 4 * byte);
292 value |= (u64)unit << (28 - 4 * byte);
293 }
294 if (grp == 0) {
295 /* increment PMC1/2/5/6 field */
296 mask |= 0x8000000000ull;
297 value |= 0x1000000000ull;
298 } else {
299 /* increment PMC3/4/7/8 field */
300 mask |= 0x800000000ull;
301 value |= 0x100000000ull;
302 }
303
304 /* Marked instruction events need sample_enable set */
305 if (p4_marked_instr_event(event)) {
306 mask |= 1ull << 56;
307 value |= 1ull << 56;
308 }
309
310 /* PMCSEL=6 decode events on byte 2 need sample_enable clear */
311 if (pmc && (event & PM_PMCSEL_MSK) == 6 && byte == 2)
312 mask |= 1ull << 56;
313
314 *maskp = mask;
315 *valp = value;
316 return 0;
317}
318
319static unsigned int ppc_inst_cmpl[] = {
320 0x1001, 0x4001, 0x6001, 0x7001, 0x8001
321};
322
323static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[])
324{
325 int i, j, na;
326
327 alt[0] = event;
328 na = 1;
329
330 /* 2 possibilities for PM_GRP_DISP_REJECT */
331 if (event == 0x8003 || event == 0x0224) {
332 alt[1] = event ^ (0x8003 ^ 0x0224);
333 return 2;
334 }
335
336 /* 2 possibilities for PM_ST_MISS_L1 */
337 if (event == 0x0c13 || event == 0x0c23) {
338 alt[1] = event ^ (0x0c13 ^ 0x0c23);
339 return 2;
340 }
341
342 /* several possibilities for PM_INST_CMPL */
343 for (i = 0; i < ARRAY_SIZE(ppc_inst_cmpl); ++i) {
344 if (event == ppc_inst_cmpl[i]) {
345 for (j = 0; j < ARRAY_SIZE(ppc_inst_cmpl); ++j)
346 if (j != i)
347 alt[na++] = ppc_inst_cmpl[j];
348 break;
349 }
350 }
351
352 return na;
353}
354
355static int p4_compute_mmcr(u64 event[], int n_ev,
356 unsigned int hwc[], u64 mmcr[])
357{
358 u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;
359 unsigned int pmc, unit, byte, psel, lower;
360 unsigned int ttm, grp;
361 unsigned int pmc_inuse = 0;
362 unsigned int pmc_grp_use[2];
363 unsigned char busbyte[4];
364 unsigned char unituse[16];
365 unsigned int unitlower = 0;
366 int i;
367
368 if (n_ev > 8)
369 return -1;
370
371 /* First pass to count resource use */
372 pmc_grp_use[0] = pmc_grp_use[1] = 0;
373 memset(busbyte, 0, sizeof(busbyte));
374 memset(unituse, 0, sizeof(unituse));
375 for (i = 0; i < n_ev; ++i) {
376 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
377 if (pmc) {
378 if (pmc_inuse & (1 << (pmc - 1)))
379 return -1;
380 pmc_inuse |= 1 << (pmc - 1);
381 /* count 1/2/5/6 vs 3/4/7/8 use */
382 ++pmc_grp_use[((pmc - 1) >> 1) & 1];
383 }
384 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
385 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
386 lower = (event[i] >> PM_LOWER_SH) & PM_LOWER_MSK;
387 if (unit) {
388 if (!pmc)
389 ++pmc_grp_use[byte & 1];
390 if (unit == 6 || unit == 8)
391 /* map alt ISU1/IFU codes: 6->2, 8->3 */
392 unit = (unit >> 1) - 1;
393 if (busbyte[byte] && busbyte[byte] != unit)
394 return -1;
395 busbyte[byte] = unit;
396 lower <<= unit;
397 if (unituse[unit] && lower != (unitlower & lower))
398 return -1;
399 unituse[unit] = 1;
400 unitlower |= lower;
401 }
402 }
403 if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
404 return -1;
405
406 /*
407 * Assign resources and set multiplexer selects.
408 *
409 * Units 1,2,3 are on TTM0, 4,6,7 on TTM1, 8,10 on TTM2.
410 * Each TTMx can only select one unit, but since
411 * units 2 and 6 are both ISU1, and 3 and 8 are both IFU,
412 * we have some choices.
413 */
414 if (unituse[2] & (unituse[1] | (unituse[3] & unituse[9]))) {
415 unituse[6] = 1; /* Move 2 to 6 */
416 unituse[2] = 0;
417 }
418 if (unituse[3] & (unituse[1] | unituse[2])) {
419 unituse[8] = 1; /* Move 3 to 8 */
420 unituse[3] = 0;
421 unitlower = (unitlower & ~8) | ((unitlower & 8) << 5);
422 }
423 /* Check only one unit per TTMx */
424 if (unituse[1] + unituse[2] + unituse[3] > 1 ||
425 unituse[4] + unituse[6] + unituse[7] > 1 ||
426 unituse[8] + unituse[9] > 1 ||
427 (unituse[5] | unituse[10] | unituse[11] |
428 unituse[13] | unituse[14]))
429 return -1;
430
431 /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */
432 mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH;
433 mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH;
434 mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH;
435
436 /* Set TTCxSEL fields. */
437 if (unitlower & 0xe)
438 mmcr1 |= 1ull << MMCR1_TTC0SEL_SH;
439 if (unitlower & 0xf0)
440 mmcr1 |= 1ull << MMCR1_TTC1SEL_SH;
441 if (unitlower & 0xf00)
442 mmcr1 |= 1ull << MMCR1_TTC2SEL_SH;
443 if (unitlower & 0x7000)
444 mmcr1 |= 1ull << MMCR1_TTC3SEL_SH;
445
446 /* Set byte lane select fields. */
447 for (byte = 0; byte < 4; ++byte) {
448 unit = busbyte[byte];
449 if (!unit)
450 continue;
451 if (unit == 0xf) {
452 /* special case for GPS */
453 mmcr1 |= 1ull << (MMCR1_DEBUG0SEL_SH - byte);
454 } else {
455 if (!unituse[unit])
456 ttm = unit - 1; /* 2->1, 3->2 */
457 else
458 ttm = unit >> 2;
459 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte);
460 }
461 }
462
463 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
464 for (i = 0; i < n_ev; ++i) {
465 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
466 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
467 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
468 psel = event[i] & PM_PMCSEL_MSK;
469 if (!pmc) {
470 /* Bus event or 00xxx direct event (off or cycles) */
471 if (unit)
472 psel |= 0x10 | ((byte & 2) << 2);
473 for (pmc = 0; pmc < 8; ++pmc) {
474 if (pmc_inuse & (1 << pmc))
475 continue;
476 grp = (pmc >> 1) & 1;
477 if (unit) {
478 if (grp == (byte & 1))
479 break;
480 } else if (pmc_grp_use[grp] < 4) {
481 ++pmc_grp_use[grp];
482 break;
483 }
484 }
485 pmc_inuse |= 1 << pmc;
486 } else {
487 /* Direct event */
488 --pmc;
489 if (psel == 0 && (byte & 2))
490 /* add events on higher-numbered bus */
491 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
492 else if (psel == 6 && byte == 3)
493 /* seem to need to set sample_enable here */
494 mmcra |= MMCRA_SAMPLE_ENABLE;
495 psel |= 8;
496 }
497 if (pmc <= 1)
498 mmcr0 |= psel << (MMCR0_PMC1SEL_SH - 7 * pmc);
499 else
500 mmcr1 |= psel << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
501 if (pmc == 7) /* PMC8 */
502 mmcra |= (psel & 1) << MMCRA_PMC8SEL0_SH;
503 hwc[i] = pmc;
504 if (p4_marked_instr_event(event[i]))
505 mmcra |= MMCRA_SAMPLE_ENABLE;
506 }
507
508 if (pmc_inuse & 1)
509 mmcr0 |= MMCR0_PMC1CE;
510 if (pmc_inuse & 0xfe)
511 mmcr0 |= MMCR0_PMCjCE;
512
513 mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
514
515 /* Return MMCRx values */
516 mmcr[0] = mmcr0;
517 mmcr[1] = mmcr1;
518 mmcr[2] = mmcra;
519 return 0;
520}
521
522static void p4_disable_pmc(unsigned int pmc, u64 mmcr[])
523{
524 /*
525 * Setting the PMCxSEL field to 0 disables PMC x.
526 * (Note that pmc is 0-based here, not 1-based.)
527 */
528 if (pmc <= 1) {
529 mmcr[0] &= ~(0x1fUL << (MMCR0_PMC1SEL_SH - 7 * pmc));
530 } else {
531 mmcr[1] &= ~(0x1fUL << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)));
532 if (pmc == 7)
533 mmcr[2] &= ~(1UL << MMCRA_PMC8SEL0_SH);
534 }
535}
536
537static int p4_generic_events[] = {
538 [PERF_COUNT_HW_CPU_CYCLES] = 7,
539 [PERF_COUNT_HW_INSTRUCTIONS] = 0x1001,
540 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8c10, /* PM_LD_REF_L1 */
541 [PERF_COUNT_HW_CACHE_MISSES] = 0x3c10, /* PM_LD_MISS_L1 */
542 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x330, /* PM_BR_ISSUED */
543 [PERF_COUNT_HW_BRANCH_MISSES] = 0x331, /* PM_BR_MPRED_CR */
544};
545
546#define C(x) PERF_COUNT_HW_CACHE_##x
547
548/*
549 * Table of generalized cache-related events.
550 * 0 means not supported, -1 means nonsensical, other values
551 * are event codes.
552 */
553static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
554 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
555 [C(OP_READ)] = { 0x8c10, 0x3c10 },
556 [C(OP_WRITE)] = { 0x7c10, 0xc13 },
557 [C(OP_PREFETCH)] = { 0xc35, 0 },
558 },
559 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
560 [C(OP_READ)] = { 0, 0 },
561 [C(OP_WRITE)] = { -1, -1 },
562 [C(OP_PREFETCH)] = { 0, 0 },
563 },
564 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
565 [C(OP_READ)] = { 0, 0 },
566 [C(OP_WRITE)] = { 0, 0 },
567 [C(OP_PREFETCH)] = { 0xc34, 0 },
568 },
569 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
570 [C(OP_READ)] = { 0, 0x904 },
571 [C(OP_WRITE)] = { -1, -1 },
572 [C(OP_PREFETCH)] = { -1, -1 },
573 },
574 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
575 [C(OP_READ)] = { 0, 0x900 },
576 [C(OP_WRITE)] = { -1, -1 },
577 [C(OP_PREFETCH)] = { -1, -1 },
578 },
579 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
580 [C(OP_READ)] = { 0x330, 0x331 },
581 [C(OP_WRITE)] = { -1, -1 },
582 [C(OP_PREFETCH)] = { -1, -1 },
583 },
584};
585
586struct power_pmu power4_pmu = {
587 .n_counter = 8,
588 .max_alternatives = 5,
589 .add_fields = 0x0000001100005555ull,
590 .test_adder = 0x0011083300000000ull,
591 .compute_mmcr = p4_compute_mmcr,
592 .get_constraint = p4_get_constraint,
593 .get_alternatives = p4_get_alternatives,
594 .disable_pmc = p4_disable_pmc,
595 .n_generic = ARRAY_SIZE(p4_generic_events),
596 .generic_events = p4_generic_events,
597 .cache_events = &power4_cache_events,
598};
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
new file mode 100644
index 000000000000..41e5d2d958d4
--- /dev/null
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -0,0 +1,671 @@
1/*
2 * Performance counter support for POWER5+/++ (not POWER5) processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
17 */
18#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
22#define PM_UNIT_MSK 0xf
23#define PM_BYTE_SH 12 /* Byte number of event bus to use */
24#define PM_BYTE_MSK 7
25#define PM_GRS_SH 8 /* Storage subsystem mux select */
26#define PM_GRS_MSK 7
27#define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
28#define PM_PMCSEL_MSK 0x7f
29
30/* Values in PM_UNIT field */
31#define PM_FPU 0
32#define PM_ISU0 1
33#define PM_IFU 2
34#define PM_ISU1 3
35#define PM_IDU 4
36#define PM_ISU0_ALT 6
37#define PM_GRS 7
38#define PM_LSU0 8
39#define PM_LSU1 0xc
40#define PM_LASTUNIT 0xc
41
42/*
43 * Bits in MMCR1 for POWER5+
44 */
45#define MMCR1_TTM0SEL_SH 62
46#define MMCR1_TTM1SEL_SH 60
47#define MMCR1_TTM2SEL_SH 58
48#define MMCR1_TTM3SEL_SH 56
49#define MMCR1_TTMSEL_MSK 3
50#define MMCR1_TD_CP_DBG0SEL_SH 54
51#define MMCR1_TD_CP_DBG1SEL_SH 52
52#define MMCR1_TD_CP_DBG2SEL_SH 50
53#define MMCR1_TD_CP_DBG3SEL_SH 48
54#define MMCR1_GRS_L2SEL_SH 46
55#define MMCR1_GRS_L2SEL_MSK 3
56#define MMCR1_GRS_L3SEL_SH 44
57#define MMCR1_GRS_L3SEL_MSK 3
58#define MMCR1_GRS_MCSEL_SH 41
59#define MMCR1_GRS_MCSEL_MSK 7
60#define MMCR1_GRS_FABSEL_SH 39
61#define MMCR1_GRS_FABSEL_MSK 3
62#define MMCR1_PMC1_ADDER_SEL_SH 35
63#define MMCR1_PMC2_ADDER_SEL_SH 34
64#define MMCR1_PMC3_ADDER_SEL_SH 33
65#define MMCR1_PMC4_ADDER_SEL_SH 32
66#define MMCR1_PMC1SEL_SH 25
67#define MMCR1_PMC2SEL_SH 17
68#define MMCR1_PMC3SEL_SH 9
69#define MMCR1_PMC4SEL_SH 1
70#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
71#define MMCR1_PMCSEL_MSK 0x7f
72
73/*
74 * Bits in MMCRA
75 */
76
77/*
78 * Layout of constraint bits:
79 * 6666555555555544444444443333333333222222222211111111110000000000
80 * 3210987654321098765432109876543210987654321098765432109876543210
81 * [ ><><>< ><> <><>[ > < >< >< >< ><><><><><><>
82 * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P6P5P4P3P2P1
83 *
84 * NC - number of counters
85 * 51: NC error 0x0008_0000_0000_0000
86 * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
87 *
88 * G0..G3 - GRS mux constraints
89 * 46-47: GRS_L2SEL value
90 * 44-45: GRS_L3SEL value
91 * 41-44: GRS_MCSEL value
92 * 39-40: GRS_FABSEL value
93 * Note that these match up with their bit positions in MMCR1
94 *
95 * T0 - TTM0 constraint
96 * 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
97 *
98 * T1 - TTM1 constraint
99 * 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
100 *
101 * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
102 * 33: UC3 error 0x02_0000_0000
103 * 32: FPU|IFU|ISU1 events needed 0x01_0000_0000
104 * 31: ISU0 events needed 0x01_8000_0000
105 * 30: IDU|GRS events needed 0x00_4000_0000
106 *
107 * B0
108 * 24-27: Byte 0 event source 0x0f00_0000
109 * Encoding as for the event code
110 *
111 * B1, B2, B3
112 * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
113 *
114 * P6
115 * 11: P6 error 0x800
116 * 10-11: Count of events needing PMC6
117 *
118 * P1..P5
119 * 0-9: Count of events needing PMC1..PMC5
120 */
121
122static const int grsel_shift[8] = {
123 MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
124 MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
125 MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
126};
127
128/* Masks and values for using events from the various units */
129static u64 unit_cons[PM_LASTUNIT+1][2] = {
130 [PM_FPU] = { 0x3200000000ull, 0x0100000000ull },
131 [PM_ISU0] = { 0x0200000000ull, 0x0080000000ull },
132 [PM_ISU1] = { 0x3200000000ull, 0x3100000000ull },
133 [PM_IFU] = { 0x3200000000ull, 0x2100000000ull },
134 [PM_IDU] = { 0x0e00000000ull, 0x0040000000ull },
135 [PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull },
136};
137
138static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
139{
140 int pmc, byte, unit, sh;
141 int bit, fmask;
142 u64 mask = 0, value = 0;
143
144 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
145 if (pmc) {
146 if (pmc > 6)
147 return -1;
148 sh = (pmc - 1) * 2;
149 mask |= 2 << sh;
150 value |= 1 << sh;
151 if (pmc >= 5 && !(event == 0x500009 || event == 0x600005))
152 return -1;
153 }
154 if (event & PM_BUSEVENT_MSK) {
155 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
156 if (unit > PM_LASTUNIT)
157 return -1;
158 if (unit == PM_ISU0_ALT)
159 unit = PM_ISU0;
160 mask |= unit_cons[unit][0];
161 value |= unit_cons[unit][1];
162 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
163 if (byte >= 4) {
164 if (unit != PM_LSU1)
165 return -1;
166 /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
167 ++unit;
168 byte &= 3;
169 }
170 if (unit == PM_GRS) {
171 bit = event & 7;
172 fmask = (bit == 6)? 7: 3;
173 sh = grsel_shift[bit];
174 mask |= (u64)fmask << sh;
175 value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
176 }
177 /* Set byte lane select field */
178 mask |= 0xfULL << (24 - 4 * byte);
179 value |= (u64)unit << (24 - 4 * byte);
180 }
181 if (pmc < 5) {
182 /* need a counter from PMC1-4 set */
183 mask |= 0x8000000000000ull;
184 value |= 0x1000000000000ull;
185 }
186 *maskp = mask;
187 *valp = value;
188 return 0;
189}
190
191static int power5p_limited_pmc_event(u64 event)
192{
193 int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
194
195 return pmc == 5 || pmc == 6;
196}
197
198#define MAX_ALT 3 /* at most 3 alternatives for any event */
199
200static const unsigned int event_alternatives[][MAX_ALT] = {
201 { 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */
202 { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
203 { 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */
204 { 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */
205 { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
206 { 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */
207 { 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */
208 { 0x100005, 0x600005 }, /* PM_RUN_CYC */
209 { 0x100009, 0x200009 }, /* PM_INST_CMPL */
210 { 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
211 { 0x300009, 0x400009 }, /* PM_INST_DISP */
212};
213
214/*
215 * Scan the alternatives table for a match and return the
216 * index into the alternatives table if found, else -1.
217 */
218static int find_alternative(unsigned int event)
219{
220 int i, j;
221
222 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
223 if (event < event_alternatives[i][0])
224 break;
225 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
226 if (event == event_alternatives[i][j])
227 return i;
228 }
229 return -1;
230}
231
232static const unsigned char bytedecode_alternatives[4][4] = {
233 /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
234 /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
235 /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
236 /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
237};
238
239/*
240 * Some direct events for decodes of event bus byte 3 have alternative
241 * PMCSEL values on other counters. This returns the alternative
242 * event code for those that do, or -1 otherwise. This also handles
243 * alternative PCMSEL values for add events.
244 */
245static s64 find_alternative_bdecode(u64 event)
246{
247 int pmc, altpmc, pp, j;
248
249 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
250 if (pmc == 0 || pmc > 4)
251 return -1;
252 altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
253 pp = event & PM_PMCSEL_MSK;
254 for (j = 0; j < 4; ++j) {
255 if (bytedecode_alternatives[pmc - 1][j] == pp) {
256 return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
257 (altpmc << PM_PMC_SH) |
258 bytedecode_alternatives[altpmc - 1][j];
259 }
260 }
261
262 /* new decode alternatives for power5+ */
263 if (pmc == 1 && (pp == 0x0d || pp == 0x0e))
264 return event + (2 << PM_PMC_SH) + (0x2e - 0x0d);
265 if (pmc == 3 && (pp == 0x2e || pp == 0x2f))
266 return event - (2 << PM_PMC_SH) - (0x2e - 0x0d);
267
268 /* alternative add event encodings */
269 if (pp == 0x10 || pp == 0x28)
270 return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) |
271 (altpmc << PM_PMC_SH);
272
273 return -1;
274}
275
276static int power5p_get_alternatives(u64 event, unsigned int flags, u64 alt[])
277{
278 int i, j, nalt = 1;
279 int nlim;
280 s64 ae;
281
282 alt[0] = event;
283 nalt = 1;
284 nlim = power5p_limited_pmc_event(event);
285 i = find_alternative(event);
286 if (i >= 0) {
287 for (j = 0; j < MAX_ALT; ++j) {
288 ae = event_alternatives[i][j];
289 if (ae && ae != event)
290 alt[nalt++] = ae;
291 nlim += power5p_limited_pmc_event(ae);
292 }
293 } else {
294 ae = find_alternative_bdecode(event);
295 if (ae > 0)
296 alt[nalt++] = ae;
297 }
298
299 if (flags & PPMU_ONLY_COUNT_RUN) {
300 /*
301 * We're only counting in RUN state,
302 * so PM_CYC is equivalent to PM_RUN_CYC
303 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
304 * This doesn't include alternatives that don't provide
305 * any extra flexibility in assigning PMCs (e.g.
306 * 0x100005 for PM_RUN_CYC vs. 0xf for PM_CYC).
307 * Note that even with these additional alternatives
308 * we never end up with more than 3 alternatives for any event.
309 */
310 j = nalt;
311 for (i = 0; i < nalt; ++i) {
312 switch (alt[i]) {
313 case 0xf: /* PM_CYC */
314 alt[j++] = 0x600005; /* PM_RUN_CYC */
315 ++nlim;
316 break;
317 case 0x600005: /* PM_RUN_CYC */
318 alt[j++] = 0xf;
319 break;
320 case 0x100009: /* PM_INST_CMPL */
321 alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */
322 ++nlim;
323 break;
324 case 0x500009: /* PM_RUN_INST_CMPL */
325 alt[j++] = 0x100009; /* PM_INST_CMPL */
326 alt[j++] = 0x200009;
327 break;
328 }
329 }
330 nalt = j;
331 }
332
333 if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
334 /* remove the limited PMC events */
335 j = 0;
336 for (i = 0; i < nalt; ++i) {
337 if (!power5p_limited_pmc_event(alt[i])) {
338 alt[j] = alt[i];
339 ++j;
340 }
341 }
342 nalt = j;
343 } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
344 /* remove all but the limited PMC events */
345 j = 0;
346 for (i = 0; i < nalt; ++i) {
347 if (power5p_limited_pmc_event(alt[i])) {
348 alt[j] = alt[i];
349 ++j;
350 }
351 }
352 nalt = j;
353 }
354
355 return nalt;
356}
357
358/*
359 * Map of which direct events on which PMCs are marked instruction events.
360 * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
361 * Bit 0 is set if it is marked for all PMCs.
362 * The 0x80 bit indicates a byte decode PMCSEL value.
363 */
364static unsigned char direct_event_is_marked[0x28] = {
365 0, /* 00 */
366 0x1f, /* 01 PM_IOPS_CMPL */
367 0x2, /* 02 PM_MRK_GRP_DISP */
368 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
369 0, /* 04 */
370 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
371 0x80, /* 06 */
372 0x80, /* 07 */
373 0, 0, 0,/* 08 - 0a */
374 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
375 0, /* 0c */
376 0x80, /* 0d */
377 0x80, /* 0e */
378 0, /* 0f */
379 0, /* 10 */
380 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
381 0, /* 12 */
382 0x10, /* 13 PM_MRK_GRP_CMPL */
383 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
384 0x2, /* 15 PM_MRK_GRP_ISSUED */
385 0x80, /* 16 */
386 0x80, /* 17 */
387 0, 0, 0, 0, 0,
388 0x80, /* 1d */
389 0x80, /* 1e */
390 0, /* 1f */
391 0x80, /* 20 */
392 0x80, /* 21 */
393 0x80, /* 22 */
394 0x80, /* 23 */
395 0x80, /* 24 */
396 0x80, /* 25 */
397 0x80, /* 26 */
398 0x80, /* 27 */
399};
400
401/*
402 * Returns 1 if event counts things relating to marked instructions
403 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
404 */
405static int power5p_marked_instr_event(u64 event)
406{
407 int pmc, psel;
408 int bit, byte, unit;
409 u32 mask;
410
411 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
412 psel = event & PM_PMCSEL_MSK;
413 if (pmc >= 5)
414 return 0;
415
416 bit = -1;
417 if (psel < sizeof(direct_event_is_marked)) {
418 if (direct_event_is_marked[psel] & (1 << pmc))
419 return 1;
420 if (direct_event_is_marked[psel] & 0x80)
421 bit = 4;
422 else if (psel == 0x08)
423 bit = pmc - 1;
424 else if (psel == 0x10)
425 bit = 4 - pmc;
426 else if (psel == 0x1b && (pmc == 1 || pmc == 3))
427 bit = 4;
428 } else if ((psel & 0x48) == 0x40) {
429 bit = psel & 7;
430 } else if (psel == 0x28) {
431 bit = pmc - 1;
432 } else if (pmc == 3 && (psel == 0x2e || psel == 0x2f)) {
433 bit = 4;
434 }
435
436 if (!(event & PM_BUSEVENT_MSK) || bit == -1)
437 return 0;
438
439 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
440 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
441 if (unit == PM_LSU0) {
442 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
443 mask = 0x5dff00;
444 } else if (unit == PM_LSU1 && byte >= 4) {
445 byte -= 4;
446 /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */
447 mask = 0x5f11c000;
448 } else
449 return 0;
450
451 return (mask >> (byte * 8 + bit)) & 1;
452}
453
454static int power5p_compute_mmcr(u64 event[], int n_ev,
455 unsigned int hwc[], u64 mmcr[])
456{
457 u64 mmcr1 = 0;
458 u64 mmcra = 0;
459 unsigned int pmc, unit, byte, psel;
460 unsigned int ttm;
461 int i, isbus, bit, grsel;
462 unsigned int pmc_inuse = 0;
463 unsigned char busbyte[4];
464 unsigned char unituse[16];
465 int ttmuse;
466
467 if (n_ev > 6)
468 return -1;
469
470 /* First pass to count resource use */
471 memset(busbyte, 0, sizeof(busbyte));
472 memset(unituse, 0, sizeof(unituse));
473 for (i = 0; i < n_ev; ++i) {
474 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
475 if (pmc) {
476 if (pmc > 6)
477 return -1;
478 if (pmc_inuse & (1 << (pmc - 1)))
479 return -1;
480 pmc_inuse |= 1 << (pmc - 1);
481 }
482 if (event[i] & PM_BUSEVENT_MSK) {
483 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
484 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
485 if (unit > PM_LASTUNIT)
486 return -1;
487 if (unit == PM_ISU0_ALT)
488 unit = PM_ISU0;
489 if (byte >= 4) {
490 if (unit != PM_LSU1)
491 return -1;
492 ++unit;
493 byte &= 3;
494 }
495 if (busbyte[byte] && busbyte[byte] != unit)
496 return -1;
497 busbyte[byte] = unit;
498 unituse[unit] = 1;
499 }
500 }
501
502 /*
503 * Assign resources and set multiplexer selects.
504 *
505 * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
506 * choice we have to deal with.
507 */
508 if (unituse[PM_ISU0] &
509 (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
510 unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
511 unituse[PM_ISU0] = 0;
512 }
513 /* Set TTM[01]SEL fields. */
514 ttmuse = 0;
515 for (i = PM_FPU; i <= PM_ISU1; ++i) {
516 if (!unituse[i])
517 continue;
518 if (ttmuse++)
519 return -1;
520 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
521 }
522 ttmuse = 0;
523 for (; i <= PM_GRS; ++i) {
524 if (!unituse[i])
525 continue;
526 if (ttmuse++)
527 return -1;
528 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
529 }
530 if (ttmuse > 1)
531 return -1;
532
533 /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
534 for (byte = 0; byte < 4; ++byte) {
535 unit = busbyte[byte];
536 if (!unit)
537 continue;
538 if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
539 /* get ISU0 through TTM1 rather than TTM0 */
540 unit = PM_ISU0_ALT;
541 } else if (unit == PM_LSU1 + 1) {
542 /* select lower word of LSU1 for this byte */
543 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
544 }
545 ttm = unit >> 2;
546 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
547 }
548
549 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
550 for (i = 0; i < n_ev; ++i) {
551 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
552 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
553 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
554 psel = event[i] & PM_PMCSEL_MSK;
555 isbus = event[i] & PM_BUSEVENT_MSK;
556 if (!pmc) {
557 /* Bus event or any-PMC direct event */
558 for (pmc = 0; pmc < 4; ++pmc) {
559 if (!(pmc_inuse & (1 << pmc)))
560 break;
561 }
562 if (pmc >= 4)
563 return -1;
564 pmc_inuse |= 1 << pmc;
565 } else if (pmc <= 4) {
566 /* Direct event */
567 --pmc;
568 if (isbus && (byte & 2) &&
569 (psel == 8 || psel == 0x10 || psel == 0x28))
570 /* add events on higher-numbered bus */
571 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
572 } else {
573 /* Instructions or run cycles on PMC5/6 */
574 --pmc;
575 }
576 if (isbus && unit == PM_GRS) {
577 bit = psel & 7;
578 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
579 mmcr1 |= (u64)grsel << grsel_shift[bit];
580 }
581 if (power5p_marked_instr_event(event[i]))
582 mmcra |= MMCRA_SAMPLE_ENABLE;
583 if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1))
584 /* select alternate byte lane */
585 psel |= 0x10;
586 if (pmc <= 3)
587 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
588 hwc[i] = pmc;
589 }
590
591 /* Return MMCRx values */
592 mmcr[0] = 0;
593 if (pmc_inuse & 1)
594 mmcr[0] = MMCR0_PMC1CE;
595 if (pmc_inuse & 0x3e)
596 mmcr[0] |= MMCR0_PMCjCE;
597 mmcr[1] = mmcr1;
598 mmcr[2] = mmcra;
599 return 0;
600}
601
602static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])
603{
604 if (pmc <= 3)
605 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
606}
607
608static int power5p_generic_events[] = {
609 [PERF_COUNT_HW_CPU_CYCLES] = 0xf,
610 [PERF_COUNT_HW_INSTRUCTIONS] = 0x100009,
611 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x1c10a8, /* LD_REF_L1 */
612 [PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
613 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
614 [PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
615};
616
617#define C(x) PERF_COUNT_HW_CACHE_##x
618
619/*
620 * Table of generalized cache-related events.
621 * 0 means not supported, -1 means nonsensical, other values
622 * are event codes.
623 */
624static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
625 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
626 [C(OP_READ)] = { 0x1c10a8, 0x3c1088 },
627 [C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 },
628 [C(OP_PREFETCH)] = { 0xc70e7, -1 },
629 },
630 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
631 [C(OP_READ)] = { 0, 0 },
632 [C(OP_WRITE)] = { -1, -1 },
633 [C(OP_PREFETCH)] = { 0, 0 },
634 },
635 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
636 [C(OP_READ)] = { 0, 0 },
637 [C(OP_WRITE)] = { 0, 0 },
638 [C(OP_PREFETCH)] = { 0xc50c3, 0 },
639 },
640 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
641 [C(OP_READ)] = { 0xc20e4, 0x800c4 },
642 [C(OP_WRITE)] = { -1, -1 },
643 [C(OP_PREFETCH)] = { -1, -1 },
644 },
645 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
646 [C(OP_READ)] = { 0, 0x800c0 },
647 [C(OP_WRITE)] = { -1, -1 },
648 [C(OP_PREFETCH)] = { -1, -1 },
649 },
650 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
651 [C(OP_READ)] = { 0x230e4, 0x230e5 },
652 [C(OP_WRITE)] = { -1, -1 },
653 [C(OP_PREFETCH)] = { -1, -1 },
654 },
655};
656
657struct power_pmu power5p_pmu = {
658 .n_counter = 6,
659 .max_alternatives = MAX_ALT,
660 .add_fields = 0x7000000000055ull,
661 .test_adder = 0x3000040000000ull,
662 .compute_mmcr = power5p_compute_mmcr,
663 .get_constraint = power5p_get_constraint,
664 .get_alternatives = power5p_get_alternatives,
665 .disable_pmc = power5p_disable_pmc,
666 .limited_pmc_event = power5p_limited_pmc_event,
667 .flags = PPMU_LIMITED_PMC5_6,
668 .n_generic = ARRAY_SIZE(power5p_generic_events),
669 .generic_events = power5p_generic_events,
670 .cache_events = &power5p_cache_events,
671};
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
new file mode 100644
index 000000000000..05600b66221a
--- /dev/null
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -0,0 +1,611 @@
1/*
2 * Performance counter support for POWER5 (not POWER5++) processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER5 (not POWER5++)
17 */
18#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
22#define PM_UNIT_MSK 0xf
23#define PM_BYTE_SH 12 /* Byte number of event bus to use */
24#define PM_BYTE_MSK 7
25#define PM_GRS_SH 8 /* Storage subsystem mux select */
26#define PM_GRS_MSK 7
27#define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
28#define PM_PMCSEL_MSK 0x7f
29
30/* Values in PM_UNIT field */
31#define PM_FPU 0
32#define PM_ISU0 1
33#define PM_IFU 2
34#define PM_ISU1 3
35#define PM_IDU 4
36#define PM_ISU0_ALT 6
37#define PM_GRS 7
38#define PM_LSU0 8
39#define PM_LSU1 0xc
40#define PM_LASTUNIT 0xc
41
42/*
43 * Bits in MMCR1 for POWER5
44 */
45#define MMCR1_TTM0SEL_SH 62
46#define MMCR1_TTM1SEL_SH 60
47#define MMCR1_TTM2SEL_SH 58
48#define MMCR1_TTM3SEL_SH 56
49#define MMCR1_TTMSEL_MSK 3
50#define MMCR1_TD_CP_DBG0SEL_SH 54
51#define MMCR1_TD_CP_DBG1SEL_SH 52
52#define MMCR1_TD_CP_DBG2SEL_SH 50
53#define MMCR1_TD_CP_DBG3SEL_SH 48
54#define MMCR1_GRS_L2SEL_SH 46
55#define MMCR1_GRS_L2SEL_MSK 3
56#define MMCR1_GRS_L3SEL_SH 44
57#define MMCR1_GRS_L3SEL_MSK 3
58#define MMCR1_GRS_MCSEL_SH 41
59#define MMCR1_GRS_MCSEL_MSK 7
60#define MMCR1_GRS_FABSEL_SH 39
61#define MMCR1_GRS_FABSEL_MSK 3
62#define MMCR1_PMC1_ADDER_SEL_SH 35
63#define MMCR1_PMC2_ADDER_SEL_SH 34
64#define MMCR1_PMC3_ADDER_SEL_SH 33
65#define MMCR1_PMC4_ADDER_SEL_SH 32
66#define MMCR1_PMC1SEL_SH 25
67#define MMCR1_PMC2SEL_SH 17
68#define MMCR1_PMC3SEL_SH 9
69#define MMCR1_PMC4SEL_SH 1
70#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
71#define MMCR1_PMCSEL_MSK 0x7f
72
73/*
74 * Bits in MMCRA
75 */
76
77/*
78 * Layout of constraint bits:
79 * 6666555555555544444444443333333333222222222211111111110000000000
80 * 3210987654321098765432109876543210987654321098765432109876543210
81 * <><>[ ><><>< ><> [ >[ >[ >< >< >< >< ><><><><><><>
82 * T0T1 NC G0G1G2 G3 UC PS1PS2 B0 B1 B2 B3 P6P5P4P3P2P1
83 *
84 * T0 - TTM0 constraint
85 * 54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
86 *
87 * T1 - TTM1 constraint
88 * 52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
89 *
90 * NC - number of counters
91 * 51: NC error 0x0008_0000_0000_0000
92 * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
93 *
94 * G0..G3 - GRS mux constraints
95 * 46-47: GRS_L2SEL value
96 * 44-45: GRS_L3SEL value
97 * 41-44: GRS_MCSEL value
98 * 39-40: GRS_FABSEL value
99 * Note that these match up with their bit positions in MMCR1
100 *
101 * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
102 * 37: UC3 error 0x20_0000_0000
103 * 36: FPU|IFU|ISU1 events needed 0x10_0000_0000
104 * 35: ISU0 events needed 0x08_0000_0000
105 * 34: IDU|GRS events needed 0x04_0000_0000
106 *
107 * PS1
108 * 33: PS1 error 0x2_0000_0000
109 * 31-32: count of events needing PMC1/2 0x1_8000_0000
110 *
111 * PS2
112 * 30: PS2 error 0x4000_0000
113 * 28-29: count of events needing PMC3/4 0x3000_0000
114 *
115 * B0
116 * 24-27: Byte 0 event source 0x0f00_0000
117 * Encoding as for the event code
118 *
119 * B1, B2, B3
120 * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
121 *
122 * P1..P6
123 * 0-11: Count of events needing PMC1..PMC6
124 */
125
126static const int grsel_shift[8] = {
127 MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
128 MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
129 MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
130};
131
132/* Masks and values for using events from the various units */
133static u64 unit_cons[PM_LASTUNIT+1][2] = {
134 [PM_FPU] = { 0xc0002000000000ull, 0x00001000000000ull },
135 [PM_ISU0] = { 0x00002000000000ull, 0x00000800000000ull },
136 [PM_ISU1] = { 0xc0002000000000ull, 0xc0001000000000ull },
137 [PM_IFU] = { 0xc0002000000000ull, 0x80001000000000ull },
138 [PM_IDU] = { 0x30002000000000ull, 0x00000400000000ull },
139 [PM_GRS] = { 0x30002000000000ull, 0x30000400000000ull },
140};
141
142static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
143{
144 int pmc, byte, unit, sh;
145 int bit, fmask;
146 u64 mask = 0, value = 0;
147 int grp = -1;
148
149 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
150 if (pmc) {
151 if (pmc > 6)
152 return -1;
153 sh = (pmc - 1) * 2;
154 mask |= 2 << sh;
155 value |= 1 << sh;
156 if (pmc <= 4)
157 grp = (pmc - 1) >> 1;
158 else if (event != 0x500009 && event != 0x600005)
159 return -1;
160 }
161 if (event & PM_BUSEVENT_MSK) {
162 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
163 if (unit > PM_LASTUNIT)
164 return -1;
165 if (unit == PM_ISU0_ALT)
166 unit = PM_ISU0;
167 mask |= unit_cons[unit][0];
168 value |= unit_cons[unit][1];
169 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
170 if (byte >= 4) {
171 if (unit != PM_LSU1)
172 return -1;
173 /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
174 ++unit;
175 byte &= 3;
176 }
177 if (unit == PM_GRS) {
178 bit = event & 7;
179 fmask = (bit == 6)? 7: 3;
180 sh = grsel_shift[bit];
181 mask |= (u64)fmask << sh;
182 value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
183 }
184 /*
185 * Bus events on bytes 0 and 2 can be counted
186 * on PMC1/2; bytes 1 and 3 on PMC3/4.
187 */
188 if (!pmc)
189 grp = byte & 1;
190 /* Set byte lane select field */
191 mask |= 0xfULL << (24 - 4 * byte);
192 value |= (u64)unit << (24 - 4 * byte);
193 }
194 if (grp == 0) {
195 /* increment PMC1/2 field */
196 mask |= 0x200000000ull;
197 value |= 0x080000000ull;
198 } else if (grp == 1) {
199 /* increment PMC3/4 field */
200 mask |= 0x40000000ull;
201 value |= 0x10000000ull;
202 }
203 if (pmc < 5) {
204 /* need a counter from PMC1-4 set */
205 mask |= 0x8000000000000ull;
206 value |= 0x1000000000000ull;
207 }
208 *maskp = mask;
209 *valp = value;
210 return 0;
211}
212
213#define MAX_ALT 3 /* at most 3 alternatives for any event */
214
215static const unsigned int event_alternatives[][MAX_ALT] = {
216 { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
217 { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
218 { 0x100005, 0x600005 }, /* PM_RUN_CYC */
219 { 0x100009, 0x200009, 0x500009 }, /* PM_INST_CMPL */
220 { 0x300009, 0x400009 }, /* PM_INST_DISP */
221};
222
223/*
224 * Scan the alternatives table for a match and return the
225 * index into the alternatives table if found, else -1.
226 */
227static int find_alternative(u64 event)
228{
229 int i, j;
230
231 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
232 if (event < event_alternatives[i][0])
233 break;
234 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
235 if (event == event_alternatives[i][j])
236 return i;
237 }
238 return -1;
239}
240
241static const unsigned char bytedecode_alternatives[4][4] = {
242 /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
243 /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
244 /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
245 /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
246};
247
248/*
249 * Some direct events for decodes of event bus byte 3 have alternative
250 * PMCSEL values on other counters. This returns the alternative
251 * event code for those that do, or -1 otherwise.
252 */
253static s64 find_alternative_bdecode(u64 event)
254{
255 int pmc, altpmc, pp, j;
256
257 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
258 if (pmc == 0 || pmc > 4)
259 return -1;
260 altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
261 pp = event & PM_PMCSEL_MSK;
262 for (j = 0; j < 4; ++j) {
263 if (bytedecode_alternatives[pmc - 1][j] == pp) {
264 return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
265 (altpmc << PM_PMC_SH) |
266 bytedecode_alternatives[altpmc - 1][j];
267 }
268 }
269 return -1;
270}
271
272static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[])
273{
274 int i, j, nalt = 1;
275 s64 ae;
276
277 alt[0] = event;
278 nalt = 1;
279 i = find_alternative(event);
280 if (i >= 0) {
281 for (j = 0; j < MAX_ALT; ++j) {
282 ae = event_alternatives[i][j];
283 if (ae && ae != event)
284 alt[nalt++] = ae;
285 }
286 } else {
287 ae = find_alternative_bdecode(event);
288 if (ae > 0)
289 alt[nalt++] = ae;
290 }
291 return nalt;
292}
293
294/*
295 * Map of which direct events on which PMCs are marked instruction events.
296 * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
297 * Bit 0 is set if it is marked for all PMCs.
298 * The 0x80 bit indicates a byte decode PMCSEL value.
299 */
300static unsigned char direct_event_is_marked[0x28] = {
301 0, /* 00 */
302 0x1f, /* 01 PM_IOPS_CMPL */
303 0x2, /* 02 PM_MRK_GRP_DISP */
304 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
305 0, /* 04 */
306 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
307 0x80, /* 06 */
308 0x80, /* 07 */
309 0, 0, 0,/* 08 - 0a */
310 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
311 0, /* 0c */
312 0x80, /* 0d */
313 0x80, /* 0e */
314 0, /* 0f */
315 0, /* 10 */
316 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
317 0, /* 12 */
318 0x10, /* 13 PM_MRK_GRP_CMPL */
319 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
320 0x2, /* 15 PM_MRK_GRP_ISSUED */
321 0x80, /* 16 */
322 0x80, /* 17 */
323 0, 0, 0, 0, 0,
324 0x80, /* 1d */
325 0x80, /* 1e */
326 0, /* 1f */
327 0x80, /* 20 */
328 0x80, /* 21 */
329 0x80, /* 22 */
330 0x80, /* 23 */
331 0x80, /* 24 */
332 0x80, /* 25 */
333 0x80, /* 26 */
334 0x80, /* 27 */
335};
336
337/*
338 * Returns 1 if event counts things relating to marked instructions
339 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
340 */
341static int power5_marked_instr_event(u64 event)
342{
343 int pmc, psel;
344 int bit, byte, unit;
345 u32 mask;
346
347 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
348 psel = event & PM_PMCSEL_MSK;
349 if (pmc >= 5)
350 return 0;
351
352 bit = -1;
353 if (psel < sizeof(direct_event_is_marked)) {
354 if (direct_event_is_marked[psel] & (1 << pmc))
355 return 1;
356 if (direct_event_is_marked[psel] & 0x80)
357 bit = 4;
358 else if (psel == 0x08)
359 bit = pmc - 1;
360 else if (psel == 0x10)
361 bit = 4 - pmc;
362 else if (psel == 0x1b && (pmc == 1 || pmc == 3))
363 bit = 4;
364 } else if ((psel & 0x58) == 0x40)
365 bit = psel & 7;
366
367 if (!(event & PM_BUSEVENT_MSK))
368 return 0;
369
370 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
371 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
372 if (unit == PM_LSU0) {
373 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
374 mask = 0x5dff00;
375 } else if (unit == PM_LSU1 && byte >= 4) {
376 byte -= 4;
377 /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
378 mask = 0x5f00c0aa;
379 } else
380 return 0;
381
382 return (mask >> (byte * 8 + bit)) & 1;
383}
384
385static int power5_compute_mmcr(u64 event[], int n_ev,
386 unsigned int hwc[], u64 mmcr[])
387{
388 u64 mmcr1 = 0;
389 u64 mmcra = 0;
390 unsigned int pmc, unit, byte, psel;
391 unsigned int ttm, grp;
392 int i, isbus, bit, grsel;
393 unsigned int pmc_inuse = 0;
394 unsigned int pmc_grp_use[2];
395 unsigned char busbyte[4];
396 unsigned char unituse[16];
397 int ttmuse;
398
399 if (n_ev > 6)
400 return -1;
401
402 /* First pass to count resource use */
403 pmc_grp_use[0] = pmc_grp_use[1] = 0;
404 memset(busbyte, 0, sizeof(busbyte));
405 memset(unituse, 0, sizeof(unituse));
406 for (i = 0; i < n_ev; ++i) {
407 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
408 if (pmc) {
409 if (pmc > 6)
410 return -1;
411 if (pmc_inuse & (1 << (pmc - 1)))
412 return -1;
413 pmc_inuse |= 1 << (pmc - 1);
414 /* count 1/2 vs 3/4 use */
415 if (pmc <= 4)
416 ++pmc_grp_use[(pmc - 1) >> 1];
417 }
418 if (event[i] & PM_BUSEVENT_MSK) {
419 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
420 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
421 if (unit > PM_LASTUNIT)
422 return -1;
423 if (unit == PM_ISU0_ALT)
424 unit = PM_ISU0;
425 if (byte >= 4) {
426 if (unit != PM_LSU1)
427 return -1;
428 ++unit;
429 byte &= 3;
430 }
431 if (!pmc)
432 ++pmc_grp_use[byte & 1];
433 if (busbyte[byte] && busbyte[byte] != unit)
434 return -1;
435 busbyte[byte] = unit;
436 unituse[unit] = 1;
437 }
438 }
439 if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
440 return -1;
441
442 /*
443 * Assign resources and set multiplexer selects.
444 *
445 * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
446 * choice we have to deal with.
447 */
448 if (unituse[PM_ISU0] &
449 (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
450 unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
451 unituse[PM_ISU0] = 0;
452 }
453 /* Set TTM[01]SEL fields. */
454 ttmuse = 0;
455 for (i = PM_FPU; i <= PM_ISU1; ++i) {
456 if (!unituse[i])
457 continue;
458 if (ttmuse++)
459 return -1;
460 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
461 }
462 ttmuse = 0;
463 for (; i <= PM_GRS; ++i) {
464 if (!unituse[i])
465 continue;
466 if (ttmuse++)
467 return -1;
468 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
469 }
470 if (ttmuse > 1)
471 return -1;
472
473 /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
474 for (byte = 0; byte < 4; ++byte) {
475 unit = busbyte[byte];
476 if (!unit)
477 continue;
478 if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
479 /* get ISU0 through TTM1 rather than TTM0 */
480 unit = PM_ISU0_ALT;
481 } else if (unit == PM_LSU1 + 1) {
482 /* select lower word of LSU1 for this byte */
483 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
484 }
485 ttm = unit >> 2;
486 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
487 }
488
489 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
490 for (i = 0; i < n_ev; ++i) {
491 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
492 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
493 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
494 psel = event[i] & PM_PMCSEL_MSK;
495 isbus = event[i] & PM_BUSEVENT_MSK;
496 if (!pmc) {
497 /* Bus event or any-PMC direct event */
498 for (pmc = 0; pmc < 4; ++pmc) {
499 if (pmc_inuse & (1 << pmc))
500 continue;
501 grp = (pmc >> 1) & 1;
502 if (isbus) {
503 if (grp == (byte & 1))
504 break;
505 } else if (pmc_grp_use[grp] < 2) {
506 ++pmc_grp_use[grp];
507 break;
508 }
509 }
510 pmc_inuse |= 1 << pmc;
511 } else if (pmc <= 4) {
512 /* Direct event */
513 --pmc;
514 if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
515 /* add events on higher-numbered bus */
516 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
517 } else {
518 /* Instructions or run cycles on PMC5/6 */
519 --pmc;
520 }
521 if (isbus && unit == PM_GRS) {
522 bit = psel & 7;
523 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
524 mmcr1 |= (u64)grsel << grsel_shift[bit];
525 }
526 if (power5_marked_instr_event(event[i]))
527 mmcra |= MMCRA_SAMPLE_ENABLE;
528 if (pmc <= 3)
529 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
530 hwc[i] = pmc;
531 }
532
533 /* Return MMCRx values */
534 mmcr[0] = 0;
535 if (pmc_inuse & 1)
536 mmcr[0] = MMCR0_PMC1CE;
537 if (pmc_inuse & 0x3e)
538 mmcr[0] |= MMCR0_PMCjCE;
539 mmcr[1] = mmcr1;
540 mmcr[2] = mmcra;
541 return 0;
542}
543
544static void power5_disable_pmc(unsigned int pmc, u64 mmcr[])
545{
546 if (pmc <= 3)
547 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
548}
549
550static int power5_generic_events[] = {
551 [PERF_COUNT_HW_CPU_CYCLES] = 0xf,
552 [PERF_COUNT_HW_INSTRUCTIONS] = 0x100009,
553 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4c1090, /* LD_REF_L1 */
554 [PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
555 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
556 [PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
557};
558
559#define C(x) PERF_COUNT_HW_CACHE_##x
560
561/*
562 * Table of generalized cache-related events.
563 * 0 means not supported, -1 means nonsensical, other values
564 * are event codes.
565 */
566static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
567 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
568 [C(OP_READ)] = { 0x4c1090, 0x3c1088 },
569 [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
570 [C(OP_PREFETCH)] = { 0xc70e7, 0 },
571 },
572 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
573 [C(OP_READ)] = { 0, 0 },
574 [C(OP_WRITE)] = { -1, -1 },
575 [C(OP_PREFETCH)] = { 0, 0 },
576 },
577 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
578 [C(OP_READ)] = { 0, 0x3c309b },
579 [C(OP_WRITE)] = { 0, 0 },
580 [C(OP_PREFETCH)] = { 0xc50c3, 0 },
581 },
582 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
583 [C(OP_READ)] = { 0x2c4090, 0x800c4 },
584 [C(OP_WRITE)] = { -1, -1 },
585 [C(OP_PREFETCH)] = { -1, -1 },
586 },
587 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
588 [C(OP_READ)] = { 0, 0x800c0 },
589 [C(OP_WRITE)] = { -1, -1 },
590 [C(OP_PREFETCH)] = { -1, -1 },
591 },
592 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
593 [C(OP_READ)] = { 0x230e4, 0x230e5 },
594 [C(OP_WRITE)] = { -1, -1 },
595 [C(OP_PREFETCH)] = { -1, -1 },
596 },
597};
598
599struct power_pmu power5_pmu = {
600 .n_counter = 6,
601 .max_alternatives = MAX_ALT,
602 .add_fields = 0x7000090000555ull,
603 .test_adder = 0x3000490000000ull,
604 .compute_mmcr = power5_compute_mmcr,
605 .get_constraint = power5_get_constraint,
606 .get_alternatives = power5_get_alternatives,
607 .disable_pmc = power5_disable_pmc,
608 .n_generic = ARRAY_SIZE(power5_generic_events),
609 .generic_events = power5_generic_events,
610 .cache_events = &power5_cache_events,
611};
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
new file mode 100644
index 000000000000..46f74bebcfd9
--- /dev/null
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -0,0 +1,532 @@
1/*
2 * Performance counter support for POWER6 processors.
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER6
17 */
18#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0x7
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */
22#define PM_UNIT_MSK 0xf
23#define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
24#define PM_LLAV 0x8000 /* Load lookahead match value */
25#define PM_LLA 0x4000 /* Load lookahead match enable */
26#define PM_BYTE_SH 12 /* Byte of event bus to use */
27#define PM_BYTE_MSK 3
28#define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */
29#define PM_SUBUNIT_MSK 7
30#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
31#define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
32#define PM_BUSEVENT_MSK 0xf3700
33
34/*
35 * Bits in MMCR1 for POWER6
36 */
37#define MMCR1_TTM0SEL_SH 60
38#define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
39#define MMCR1_TTMSEL_MSK 0xf
40#define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
41#define MMCR1_NESTSEL_SH 45
42#define MMCR1_NESTSEL_MSK 0x7
43#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
44#define MMCR1_PMC1_LLA ((u64)1 << 44)
45#define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39)
46#define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35)
47#define MMCR1_PMC1SEL_SH 24
48#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
49#define MMCR1_PMCSEL_MSK 0xff
50
51/*
52 * Map of which direct events on which PMCs are marked instruction events.
53 * Indexed by PMCSEL value >> 1.
54 * Bottom 4 bits are a map of which PMCs are interesting,
55 * top 4 bits say what sort of event:
56 * 0 = direct marked event,
57 * 1 = byte decode event,
58 * 4 = add/and event (PMC1 -> bits 0 & 4),
59 * 5 = add/and event (PMC1 -> bits 1 & 5),
60 * 6 = add/and event (PMC1 -> bits 2 & 6),
61 * 7 = add/and event (PMC1 -> bits 3 & 7).
62 */
63static unsigned char direct_event_is_marked[0x60 >> 1] = {
64 0, /* 00 */
65 0, /* 02 */
66 0, /* 04 */
67 0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
68 0x04, /* 08 PM_MRK_DFU_FIN */
69 0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
70 0, /* 0c */
71 0, /* 0e */
72 0x02, /* 10 PM_MRK_INST_DISP */
73 0x08, /* 12 PM_MRK_LSU_DERAT_MISS */
74 0, /* 14 */
75 0, /* 16 */
76 0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
77 0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
78 0x01, /* 1c PM_MRK_INST_ISSUED */
79 0, /* 1e */
80 0, /* 20 */
81 0, /* 22 */
82 0, /* 24 */
83 0, /* 26 */
84 0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
85 0, /* 2a */
86 0, /* 2c */
87 0, /* 2e */
88 0x4f, /* 30 */
89 0x7f, /* 32 */
90 0x4f, /* 34 */
91 0x5f, /* 36 */
92 0x6f, /* 38 */
93 0x4f, /* 3a */
94 0, /* 3c */
95 0x08, /* 3e PM_MRK_INST_TIMEO */
96 0x1f, /* 40 */
97 0x1f, /* 42 */
98 0x1f, /* 44 */
99 0x1f, /* 46 */
100 0x1f, /* 48 */
101 0x1f, /* 4a */
102 0x1f, /* 4c */
103 0x1f, /* 4e */
104 0, /* 50 */
105 0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
106 0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
107 0x02, /* 56 PM_MRK_LD_MISS_L1 */
108 0, /* 58 */
109 0, /* 5a */
110 0, /* 5c */
111 0, /* 5e */
112};
113
114/*
115 * Masks showing for each unit which bits are marked events.
116 * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
117 */
118static u32 marked_bus_events[16] = {
119 0x01000000, /* direct events set 1: byte 3 bit 0 */
120 0x00010000, /* direct events set 2: byte 2 bit 0 */
121 0, 0, 0, 0, /* IDU, IFU, nest: nothing */
122 0x00000088, /* VMX set 1: byte 0 bits 3, 7 */
123 0x000000c0, /* VMX set 2: byte 0 bits 4-7 */
124 0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
125 0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */
126 0, /* LSU set 3 */
127 0x00000010, /* VMX set 3: byte 0 bit 4 */
128 0, /* BFP set 1 */
129 0x00000022, /* BFP set 2: byte 0 bits 1, 5 */
130 0, 0
131};
132
133/*
134 * Returns 1 if event counts things relating to marked instructions
135 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
136 */
137static int power6_marked_instr_event(u64 event)
138{
139 int pmc, psel, ptype;
140 int bit, byte, unit;
141 u32 mask;
142
143 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
144 psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */
145 if (pmc >= 5)
146 return 0;
147
148 bit = -1;
149 if (psel < sizeof(direct_event_is_marked)) {
150 ptype = direct_event_is_marked[psel];
151 if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
152 return 0;
153 ptype >>= 4;
154 if (ptype == 0)
155 return 1;
156 if (ptype == 1)
157 bit = 0;
158 else
159 bit = ptype ^ (pmc - 1);
160 } else if ((psel & 0x48) == 0x40)
161 bit = psel & 7;
162
163 if (!(event & PM_BUSEVENT_MSK) || bit == -1)
164 return 0;
165
166 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
167 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
168 mask = marked_bus_events[unit];
169 return (mask >> (byte * 8 + bit)) & 1;
170}
171
172/*
173 * Assign PMC numbers and compute MMCR1 value for a set of events
174 */
175static int p6_compute_mmcr(u64 event[], int n_ev,
176 unsigned int hwc[], u64 mmcr[])
177{
178 u64 mmcr1 = 0;
179 u64 mmcra = 0;
180 int i;
181 unsigned int pmc, ev, b, u, s, psel;
182 unsigned int ttmset = 0;
183 unsigned int pmc_inuse = 0;
184
185 if (n_ev > 6)
186 return -1;
187 for (i = 0; i < n_ev; ++i) {
188 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
189 if (pmc) {
190 if (pmc_inuse & (1 << (pmc - 1)))
191 return -1; /* collision! */
192 pmc_inuse |= 1 << (pmc - 1);
193 }
194 }
195 for (i = 0; i < n_ev; ++i) {
196 ev = event[i];
197 pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
198 if (pmc) {
199 --pmc;
200 } else {
201 /* can go on any PMC; find a free one */
202 for (pmc = 0; pmc < 4; ++pmc)
203 if (!(pmc_inuse & (1 << pmc)))
204 break;
205 if (pmc >= 4)
206 return -1;
207 pmc_inuse |= 1 << pmc;
208 }
209 hwc[i] = pmc;
210 psel = ev & PM_PMCSEL_MSK;
211 if (ev & PM_BUSEVENT_MSK) {
212 /* this event uses the event bus */
213 b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
214 u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
215 /* check for conflict on this byte of event bus */
216 if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
217 return -1;
218 mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b);
219 ttmset |= 1 << b;
220 if (u == 5) {
221 /* Nest events have a further mux */
222 s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
223 if ((ttmset & 0x10) &&
224 MMCR1_NESTSEL(mmcr1) != s)
225 return -1;
226 ttmset |= 0x10;
227 mmcr1 |= (u64)s << MMCR1_NESTSEL_SH;
228 }
229 if (0x30 <= psel && psel <= 0x3d) {
230 /* these need the PMCx_ADDR_SEL bits */
231 if (b >= 2)
232 mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
233 }
234 /* bus select values are different for PMC3/4 */
235 if (pmc >= 2 && (psel & 0x90) == 0x80)
236 psel ^= 0x20;
237 }
238 if (ev & PM_LLA) {
239 mmcr1 |= MMCR1_PMC1_LLA >> pmc;
240 if (ev & PM_LLAV)
241 mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
242 }
243 if (power6_marked_instr_event(event[i]))
244 mmcra |= MMCRA_SAMPLE_ENABLE;
245 if (pmc < 4)
246 mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc);
247 }
248 mmcr[0] = 0;
249 if (pmc_inuse & 1)
250 mmcr[0] = MMCR0_PMC1CE;
251 if (pmc_inuse & 0xe)
252 mmcr[0] |= MMCR0_PMCjCE;
253 mmcr[1] = mmcr1;
254 mmcr[2] = mmcra;
255 return 0;
256}
257
258/*
259 * Layout of constraint bits:
260 *
261 * 0-1 add field: number of uses of PMC1 (max 1)
262 * 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
263 * 12-15 add field: number of uses of PMC1-4 (max 4)
264 * 16-19 select field: unit on byte 0 of event bus
265 * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
266 * 32-34 select field: nest (subunit) event selector
267 */
268static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp)
269{
270 int pmc, byte, sh, subunit;
271 u64 mask = 0, value = 0;
272
273 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
274 if (pmc) {
275 if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
276 return -1;
277 sh = (pmc - 1) * 2;
278 mask |= 2 << sh;
279 value |= 1 << sh;
280 }
281 if (event & PM_BUSEVENT_MSK) {
282 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
283 sh = byte * 4 + (16 - PM_UNIT_SH);
284 mask |= PM_UNIT_MSKS << sh;
285 value |= (u64)(event & PM_UNIT_MSKS) << sh;
286 if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
287 subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
288 mask |= (u64)PM_SUBUNIT_MSK << 32;
289 value |= (u64)subunit << 32;
290 }
291 }
292 if (pmc <= 4) {
293 mask |= 0x8000; /* add field for count of PMC1-4 uses */
294 value |= 0x1000;
295 }
296 *maskp = mask;
297 *valp = value;
298 return 0;
299}
300
301static int p6_limited_pmc_event(u64 event)
302{
303 int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
304
305 return pmc == 5 || pmc == 6;
306}
307
308#define MAX_ALT 4 /* at most 4 alternatives for any event */
309
310static const unsigned int event_alternatives[][MAX_ALT] = {
311 { 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */
312 { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
313 { 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */
314 { 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */
315 { 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */
316 { 0x10000e, 0x400010 }, /* PM_PURR */
317 { 0x100010, 0x4000f8 }, /* PM_FLUSH */
318 { 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */
319 { 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */
320 { 0x100054, 0x2000f0 }, /* PM_ST_FIN */
321 { 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */
322 { 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */
323 { 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */
324 { 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */
325 { 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */
326 { 0x200012, 0x300012 }, /* PM_INST_DISP */
327 { 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */
328 { 0x2000f8, 0x300010 }, /* PM_EXT_INT */
329 { 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */
330 { 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */
331 { 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */
332 { 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */
333 { 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */
334};
335
336/*
337 * This could be made more efficient with a binary search on
338 * a presorted list, if necessary
339 */
340static int find_alternatives_list(u64 event)
341{
342 int i, j;
343 unsigned int alt;
344
345 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
346 if (event < event_alternatives[i][0])
347 return -1;
348 for (j = 0; j < MAX_ALT; ++j) {
349 alt = event_alternatives[i][j];
350 if (!alt || event < alt)
351 break;
352 if (event == alt)
353 return i;
354 }
355 }
356 return -1;
357}
358
359static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
360{
361 int i, j, nlim;
362 unsigned int psel, pmc;
363 unsigned int nalt = 1;
364 u64 aevent;
365
366 alt[0] = event;
367 nlim = p6_limited_pmc_event(event);
368
369 /* check the alternatives table */
370 i = find_alternatives_list(event);
371 if (i >= 0) {
372 /* copy out alternatives from list */
373 for (j = 0; j < MAX_ALT; ++j) {
374 aevent = event_alternatives[i][j];
375 if (!aevent)
376 break;
377 if (aevent != event)
378 alt[nalt++] = aevent;
379 nlim += p6_limited_pmc_event(aevent);
380 }
381
382 } else {
383 /* Check for alternative ways of computing sum events */
384 /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
385 psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */
386 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
387 if (pmc && (psel == 0x32 || psel == 0x34))
388 alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
389 ((5 - pmc) << PM_PMC_SH);
390
391 /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
392 if (pmc && (psel == 0x38 || psel == 0x3a))
393 alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
394 ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
395 }
396
397 if (flags & PPMU_ONLY_COUNT_RUN) {
398 /*
399 * We're only counting in RUN state,
400 * so PM_CYC is equivalent to PM_RUN_CYC,
401 * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
402 * This doesn't include alternatives that don't provide
403 * any extra flexibility in assigning PMCs (e.g.
404 * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
405 * Note that even with these additional alternatives
406 * we never end up with more than 4 alternatives for any event.
407 */
408 j = nalt;
409 for (i = 0; i < nalt; ++i) {
410 switch (alt[i]) {
411 case 0x1e: /* PM_CYC */
412 alt[j++] = 0x600005; /* PM_RUN_CYC */
413 ++nlim;
414 break;
415 case 0x10000a: /* PM_RUN_CYC */
416 alt[j++] = 0x1e; /* PM_CYC */
417 break;
418 case 2: /* PM_INST_CMPL */
419 alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */
420 ++nlim;
421 break;
422 case 0x500009: /* PM_RUN_INST_CMPL */
423 alt[j++] = 2; /* PM_INST_CMPL */
424 break;
425 case 0x10000e: /* PM_PURR */
426 alt[j++] = 0x4000f4; /* PM_RUN_PURR */
427 break;
428 case 0x4000f4: /* PM_RUN_PURR */
429 alt[j++] = 0x10000e; /* PM_PURR */
430 break;
431 }
432 }
433 nalt = j;
434 }
435
436 if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
437 /* remove the limited PMC events */
438 j = 0;
439 for (i = 0; i < nalt; ++i) {
440 if (!p6_limited_pmc_event(alt[i])) {
441 alt[j] = alt[i];
442 ++j;
443 }
444 }
445 nalt = j;
446 } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
447 /* remove all but the limited PMC events */
448 j = 0;
449 for (i = 0; i < nalt; ++i) {
450 if (p6_limited_pmc_event(alt[i])) {
451 alt[j] = alt[i];
452 ++j;
453 }
454 }
455 nalt = j;
456 }
457
458 return nalt;
459}
460
461static void p6_disable_pmc(unsigned int pmc, u64 mmcr[])
462{
463 /* Set PMCxSEL to 0 to disable PMCx */
464 if (pmc <= 3)
465 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
466}
467
468static int power6_generic_events[] = {
469 [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
470 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
471 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */
472 [PERF_COUNT_HW_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */
473 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */
474 [PERF_COUNT_HW_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
475};
476
477#define C(x) PERF_COUNT_HW_CACHE_##x
478
479/*
480 * Table of generalized cache-related events.
481 * 0 means not supported, -1 means nonsensical, other values
482 * are event codes.
483 * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
484 */
485static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
486 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
487 [C(OP_READ)] = { 0x80082, 0x80080 },
488 [C(OP_WRITE)] = { 0x80086, 0x80088 },
489 [C(OP_PREFETCH)] = { 0x810a4, 0 },
490 },
491 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
492 [C(OP_READ)] = { 0, 0x100056 },
493 [C(OP_WRITE)] = { -1, -1 },
494 [C(OP_PREFETCH)] = { 0x4008c, 0 },
495 },
496 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
497 [C(OP_READ)] = { 0x150730, 0x250532 },
498 [C(OP_WRITE)] = { 0x250432, 0x150432 },
499 [C(OP_PREFETCH)] = { 0x810a6, 0 },
500 },
501 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
502 [C(OP_READ)] = { 0, 0x20000e },
503 [C(OP_WRITE)] = { -1, -1 },
504 [C(OP_PREFETCH)] = { -1, -1 },
505 },
506 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
507 [C(OP_READ)] = { 0, 0x420ce },
508 [C(OP_WRITE)] = { -1, -1 },
509 [C(OP_PREFETCH)] = { -1, -1 },
510 },
511 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
512 [C(OP_READ)] = { 0x430e6, 0x400052 },
513 [C(OP_WRITE)] = { -1, -1 },
514 [C(OP_PREFETCH)] = { -1, -1 },
515 },
516};
517
518struct power_pmu power6_pmu = {
519 .n_counter = 6,
520 .max_alternatives = MAX_ALT,
521 .add_fields = 0x1555,
522 .test_adder = 0x3000,
523 .compute_mmcr = p6_compute_mmcr,
524 .get_constraint = p6_get_constraint,
525 .get_alternatives = p6_get_alternatives,
526 .disable_pmc = p6_disable_pmc,
527 .limited_pmc_event = p6_limited_pmc_event,
528 .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
529 .n_generic = ARRAY_SIZE(power6_generic_events),
530 .generic_events = power6_generic_events,
531 .cache_events = &power6_cache_events,
532};
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
new file mode 100644
index 000000000000..b72e7a19d054
--- /dev/null
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -0,0 +1,357 @@
1/*
2 * Performance counter support for POWER7 processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER7
17 */
18#define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
22#define PM_UNIT_MSK 0xf
23#define PM_COMBINE_SH 11 /* Combined event bit */
24#define PM_COMBINE_MSK 1
25#define PM_COMBINE_MSKS 0x800
26#define PM_L2SEL_SH 8 /* L2 event select */
27#define PM_L2SEL_MSK 7
28#define PM_PMCSEL_MSK 0xff
29
30/*
31 * Bits in MMCR1 for POWER7
32 */
33#define MMCR1_TTM0SEL_SH 60
34#define MMCR1_TTM1SEL_SH 56
35#define MMCR1_TTM2SEL_SH 52
36#define MMCR1_TTM3SEL_SH 48
37#define MMCR1_TTMSEL_MSK 0xf
38#define MMCR1_L2SEL_SH 45
39#define MMCR1_L2SEL_MSK 7
40#define MMCR1_PMC1_COMBINE_SH 35
41#define MMCR1_PMC2_COMBINE_SH 34
42#define MMCR1_PMC3_COMBINE_SH 33
43#define MMCR1_PMC4_COMBINE_SH 32
44#define MMCR1_PMC1SEL_SH 24
45#define MMCR1_PMC2SEL_SH 16
46#define MMCR1_PMC3SEL_SH 8
47#define MMCR1_PMC4SEL_SH 0
48#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
49#define MMCR1_PMCSEL_MSK 0xff
50
51/*
52 * Bits in MMCRA
53 */
54
55/*
56 * Layout of constraint bits:
57 * 6666555555555544444444443333333333222222222211111111110000000000
58 * 3210987654321098765432109876543210987654321098765432109876543210
59 * [ ><><><><><><>
60 * NC P6P5P4P3P2P1
61 *
62 * NC - number of counters
63 * 15: NC error 0x8000
64 * 12-14: number of events needing PMC1-4 0x7000
65 *
66 * P6
67 * 11: P6 error 0x800
68 * 10-11: Count of events needing PMC6
69 *
70 * P1..P5
71 * 0-9: Count of events needing PMC1..PMC5
72 */
73
74static int power7_get_constraint(u64 event, u64 *maskp, u64 *valp)
75{
76 int pmc, sh;
77 u64 mask = 0, value = 0;
78
79 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
80 if (pmc) {
81 if (pmc > 6)
82 return -1;
83 sh = (pmc - 1) * 2;
84 mask |= 2 << sh;
85 value |= 1 << sh;
86 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
87 return -1;
88 }
89 if (pmc < 5) {
90 /* need a counter from PMC1-4 set */
91 mask |= 0x8000;
92 value |= 0x1000;
93 }
94 *maskp = mask;
95 *valp = value;
96 return 0;
97}
98
99#define MAX_ALT 2 /* at most 2 alternatives for any event */
100
101static const unsigned int event_alternatives[][MAX_ALT] = {
102 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */
103 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
104 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
105};
106
107/*
108 * Scan the alternatives table for a match and return the
109 * index into the alternatives table if found, else -1.
110 */
111static int find_alternative(u64 event)
112{
113 int i, j;
114
115 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
116 if (event < event_alternatives[i][0])
117 break;
118 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
119 if (event == event_alternatives[i][j])
120 return i;
121 }
122 return -1;
123}
124
125static s64 find_alternative_decode(u64 event)
126{
127 int pmc, psel;
128
129 /* this only handles the 4x decode events */
130 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
131 psel = event & PM_PMCSEL_MSK;
132 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
133 return event - (1 << PM_PMC_SH) + 8;
134 if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
135 return event + (1 << PM_PMC_SH) - 8;
136 return -1;
137}
138
139static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
140{
141 int i, j, nalt = 1;
142 s64 ae;
143
144 alt[0] = event;
145 nalt = 1;
146 i = find_alternative(event);
147 if (i >= 0) {
148 for (j = 0; j < MAX_ALT; ++j) {
149 ae = event_alternatives[i][j];
150 if (ae && ae != event)
151 alt[nalt++] = ae;
152 }
153 } else {
154 ae = find_alternative_decode(event);
155 if (ae > 0)
156 alt[nalt++] = ae;
157 }
158
159 if (flags & PPMU_ONLY_COUNT_RUN) {
160 /*
161 * We're only counting in RUN state,
162 * so PM_CYC is equivalent to PM_RUN_CYC
163 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
164 * This doesn't include alternatives that don't provide
165 * any extra flexibility in assigning PMCs.
166 */
167 j = nalt;
168 for (i = 0; i < nalt; ++i) {
169 switch (alt[i]) {
170 case 0x1e: /* PM_CYC */
171 alt[j++] = 0x600f4; /* PM_RUN_CYC */
172 break;
173 case 0x600f4: /* PM_RUN_CYC */
174 alt[j++] = 0x1e;
175 break;
176 case 0x2: /* PM_PPC_CMPL */
177 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
178 break;
179 case 0x500fa: /* PM_RUN_INST_CMPL */
180 alt[j++] = 0x2; /* PM_PPC_CMPL */
181 break;
182 }
183 }
184 nalt = j;
185 }
186
187 return nalt;
188}
189
190/*
191 * Returns 1 if event counts things relating to marked instructions
192 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
193 */
194static int power7_marked_instr_event(u64 event)
195{
196 int pmc, psel;
197 int unit;
198
199 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
200 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
201 psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
202 if (pmc >= 5)
203 return 0;
204
205 switch (psel >> 4) {
206 case 2:
207 return pmc == 2 || pmc == 4;
208 case 3:
209 if (psel == 0x3c)
210 return pmc == 1;
211 if (psel == 0x3e)
212 return pmc != 2;
213 return 1;
214 case 4:
215 case 5:
216 return unit == 0xd;
217 case 6:
218 if (psel == 0x64)
219 return pmc >= 3;
220 case 8:
221 return unit == 0xd;
222 }
223 return 0;
224}
225
226static int power7_compute_mmcr(u64 event[], int n_ev,
227 unsigned int hwc[], u64 mmcr[])
228{
229 u64 mmcr1 = 0;
230 u64 mmcra = 0;
231 unsigned int pmc, unit, combine, l2sel, psel;
232 unsigned int pmc_inuse = 0;
233 int i;
234
235 /* First pass to count resource use */
236 for (i = 0; i < n_ev; ++i) {
237 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
238 if (pmc) {
239 if (pmc > 6)
240 return -1;
241 if (pmc_inuse & (1 << (pmc - 1)))
242 return -1;
243 pmc_inuse |= 1 << (pmc - 1);
244 }
245 }
246
247 /* Second pass: assign PMCs, set all MMCR1 fields */
248 for (i = 0; i < n_ev; ++i) {
249 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
250 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
251 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
252 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
253 psel = event[i] & PM_PMCSEL_MSK;
254 if (!pmc) {
255 /* Bus event or any-PMC direct event */
256 for (pmc = 0; pmc < 4; ++pmc) {
257 if (!(pmc_inuse & (1 << pmc)))
258 break;
259 }
260 if (pmc >= 4)
261 return -1;
262 pmc_inuse |= 1 << pmc;
263 } else {
264 /* Direct or decoded event */
265 --pmc;
266 }
267 if (pmc <= 3) {
268 mmcr1 |= (u64) unit << (MMCR1_TTM0SEL_SH - 4 * pmc);
269 mmcr1 |= (u64) combine << (MMCR1_PMC1_COMBINE_SH - pmc);
270 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
271 if (unit == 6) /* L2 events */
272 mmcr1 |= (u64) l2sel << MMCR1_L2SEL_SH;
273 }
274 if (power7_marked_instr_event(event[i]))
275 mmcra |= MMCRA_SAMPLE_ENABLE;
276 hwc[i] = pmc;
277 }
278
279 /* Return MMCRx values */
280 mmcr[0] = 0;
281 if (pmc_inuse & 1)
282 mmcr[0] = MMCR0_PMC1CE;
283 if (pmc_inuse & 0x3e)
284 mmcr[0] |= MMCR0_PMCjCE;
285 mmcr[1] = mmcr1;
286 mmcr[2] = mmcra;
287 return 0;
288}
289
290static void power7_disable_pmc(unsigned int pmc, u64 mmcr[])
291{
292 if (pmc <= 3)
293 mmcr[1] &= ~(0xffULL << MMCR1_PMCSEL_SH(pmc));
294}
295
296static int power7_generic_events[] = {
297 [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
298 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
299 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/
300 [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */
301 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */
302 [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */
303};
304
305#define C(x) PERF_COUNT_HW_CACHE_##x
306
307/*
308 * Table of generalized cache-related events.
309 * 0 means not supported, -1 means nonsensical, other values
310 * are event codes.
311 */
312static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
313 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
314 [C(OP_READ)] = { 0x400f0, 0xc880 },
315 [C(OP_WRITE)] = { 0, 0x300f0 },
316 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
317 },
318 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
319 [C(OP_READ)] = { 0, 0x200fc },
320 [C(OP_WRITE)] = { -1, -1 },
321 [C(OP_PREFETCH)] = { 0x408a, 0 },
322 },
323 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
324 [C(OP_READ)] = { 0x6080, 0x6084 },
325 [C(OP_WRITE)] = { 0x6082, 0x6086 },
326 [C(OP_PREFETCH)] = { 0, 0 },
327 },
328 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
329 [C(OP_READ)] = { 0, 0x300fc },
330 [C(OP_WRITE)] = { -1, -1 },
331 [C(OP_PREFETCH)] = { -1, -1 },
332 },
333 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
334 [C(OP_READ)] = { 0, 0x400fc },
335 [C(OP_WRITE)] = { -1, -1 },
336 [C(OP_PREFETCH)] = { -1, -1 },
337 },
338 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
339 [C(OP_READ)] = { 0x10068, 0x400f6 },
340 [C(OP_WRITE)] = { -1, -1 },
341 [C(OP_PREFETCH)] = { -1, -1 },
342 },
343};
344
345struct power_pmu power7_pmu = {
346 .n_counter = 6,
347 .max_alternatives = MAX_ALT + 1,
348 .add_fields = 0x1555ull,
349 .test_adder = 0x3000ull,
350 .compute_mmcr = power7_compute_mmcr,
351 .get_constraint = power7_get_constraint,
352 .get_alternatives = power7_get_alternatives,
353 .disable_pmc = power7_disable_pmc,
354 .n_generic = ARRAY_SIZE(power7_generic_events),
355 .generic_events = power7_generic_events,
356 .cache_events = &power7_cache_events,
357};
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
new file mode 100644
index 000000000000..ba0a357a89f4
--- /dev/null
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -0,0 +1,482 @@
1/*
2 * Performance counter support for PPC970-family processors.
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/string.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for PPC970
17 */
18#define PM_PMC_SH 12 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */
21#define PM_UNIT_MSK 0xf
22#define PM_SPCSEL_SH 6
23#define PM_SPCSEL_MSK 3
24#define PM_BYTE_SH 4 /* Byte number of event bus to use */
25#define PM_BYTE_MSK 3
26#define PM_PMCSEL_MSK 0xf
27
28/* Values in PM_UNIT field */
29#define PM_NONE 0
30#define PM_FPU 1
31#define PM_VPU 2
32#define PM_ISU 3
33#define PM_IFU 4
34#define PM_IDU 5
35#define PM_STS 6
36#define PM_LSU0 7
37#define PM_LSU1U 8
38#define PM_LSU1L 9
39#define PM_LASTUNIT 9
40
41/*
42 * Bits in MMCR0 for PPC970
43 */
44#define MMCR0_PMC1SEL_SH 8
45#define MMCR0_PMC2SEL_SH 1
46#define MMCR_PMCSEL_MSK 0x1f
47
48/*
49 * Bits in MMCR1 for PPC970
50 */
51#define MMCR1_TTM0SEL_SH 62
52#define MMCR1_TTM1SEL_SH 59
53#define MMCR1_TTM3SEL_SH 53
54#define MMCR1_TTMSEL_MSK 3
55#define MMCR1_TD_CP_DBG0SEL_SH 50
56#define MMCR1_TD_CP_DBG1SEL_SH 48
57#define MMCR1_TD_CP_DBG2SEL_SH 46
58#define MMCR1_TD_CP_DBG3SEL_SH 44
59#define MMCR1_PMC1_ADDER_SEL_SH 39
60#define MMCR1_PMC2_ADDER_SEL_SH 38
61#define MMCR1_PMC6_ADDER_SEL_SH 37
62#define MMCR1_PMC5_ADDER_SEL_SH 36
63#define MMCR1_PMC8_ADDER_SEL_SH 35
64#define MMCR1_PMC7_ADDER_SEL_SH 34
65#define MMCR1_PMC3_ADDER_SEL_SH 33
66#define MMCR1_PMC4_ADDER_SEL_SH 32
67#define MMCR1_PMC3SEL_SH 27
68#define MMCR1_PMC4SEL_SH 22
69#define MMCR1_PMC5SEL_SH 17
70#define MMCR1_PMC6SEL_SH 12
71#define MMCR1_PMC7SEL_SH 7
72#define MMCR1_PMC8SEL_SH 2
73
74static short mmcr1_adder_bits[8] = {
75 MMCR1_PMC1_ADDER_SEL_SH,
76 MMCR1_PMC2_ADDER_SEL_SH,
77 MMCR1_PMC3_ADDER_SEL_SH,
78 MMCR1_PMC4_ADDER_SEL_SH,
79 MMCR1_PMC5_ADDER_SEL_SH,
80 MMCR1_PMC6_ADDER_SEL_SH,
81 MMCR1_PMC7_ADDER_SEL_SH,
82 MMCR1_PMC8_ADDER_SEL_SH
83};
84
85/*
86 * Bits in MMCRA
87 */
88
89/*
90 * Layout of constraint bits:
91 * 6666555555555544444444443333333333222222222211111111110000000000
92 * 3210987654321098765432109876543210987654321098765432109876543210
93 * <><><>[ >[ >[ >< >< >< >< ><><><><><><><><>
94 * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
95 *
96 * SP - SPCSEL constraint
97 * 48-49: SPCSEL value 0x3_0000_0000_0000
98 *
99 * T0 - TTM0 constraint
100 * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
101 *
102 * T1 - TTM1 constraint
103 * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
104 *
105 * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
106 * 43: UC3 error 0x0800_0000_0000
107 * 42: FPU|IFU|VPU events needed 0x0400_0000_0000
108 * 41: ISU events needed 0x0200_0000_0000
109 * 40: IDU|STS events needed 0x0100_0000_0000
110 *
111 * PS1
112 * 39: PS1 error 0x0080_0000_0000
113 * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
114 *
115 * PS2
116 * 35: PS2 error 0x0008_0000_0000
117 * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
118 *
119 * B0
120 * 28-31: Byte 0 event source 0xf000_0000
121 * Encoding as for the event code
122 *
123 * B1, B2, B3
124 * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
125 *
126 * P1
127 * 15: P1 error 0x8000
128 * 14-15: Count of events needing PMC1
129 *
130 * P2..P8
131 * 0-13: Count of events needing PMC2..PMC8
132 */
133
134static unsigned char direct_marked_event[8] = {
135 (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
136 (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
137 (1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
138 (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
139 (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
140 (1<<3) | (1<<4) | (1<<5),
141 /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
142 (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
143 (1<<4) /* PMC8: PM_MRK_LSU_FIN */
144};
145
146/*
147 * Returns 1 if event counts things relating to marked instructions
148 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
149 */
150static int p970_marked_instr_event(u64 event)
151{
152 int pmc, psel, unit, byte, bit;
153 unsigned int mask;
154
155 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
156 psel = event & PM_PMCSEL_MSK;
157 if (pmc) {
158 if (direct_marked_event[pmc - 1] & (1 << psel))
159 return 1;
160 if (psel == 0) /* add events */
161 bit = (pmc <= 4)? pmc - 1: 8 - pmc;
162 else if (psel == 7 || psel == 13) /* decode events */
163 bit = 4;
164 else
165 return 0;
166 } else
167 bit = psel;
168
169 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
170 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
171 mask = 0;
172 switch (unit) {
173 case PM_VPU:
174 mask = 0x4c; /* byte 0 bits 2,3,6 */
175 case PM_LSU0:
176 /* byte 2 bits 0,2,3,4,6; all of byte 1 */
177 mask = 0x085dff00;
178 case PM_LSU1L:
179 mask = 0x50 << 24; /* byte 3 bits 4,6 */
180 break;
181 }
182 return (mask >> (byte * 8 + bit)) & 1;
183}
184
185/* Masks and values for using events from the various units */
186static u64 unit_cons[PM_LASTUNIT+1][2] = {
187 [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
188 [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
189 [PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
190 [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull },
191 [PM_IDU] = { 0x380000000000ull, 0x010000000000ull },
192 [PM_STS] = { 0x380000000000ull, 0x310000000000ull },
193};
194
195static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
196{
197 int pmc, byte, unit, sh, spcsel;
198 u64 mask = 0, value = 0;
199 int grp = -1;
200
201 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
202 if (pmc) {
203 if (pmc > 8)
204 return -1;
205 sh = (pmc - 1) * 2;
206 mask |= 2 << sh;
207 value |= 1 << sh;
208 grp = ((pmc - 1) >> 1) & 1;
209 }
210 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
211 if (unit) {
212 if (unit > PM_LASTUNIT)
213 return -1;
214 mask |= unit_cons[unit][0];
215 value |= unit_cons[unit][1];
216 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
217 /*
218 * Bus events on bytes 0 and 2 can be counted
219 * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
220 */
221 if (!pmc)
222 grp = byte & 1;
223 /* Set byte lane select field */
224 mask |= 0xfULL << (28 - 4 * byte);
225 value |= (u64)unit << (28 - 4 * byte);
226 }
227 if (grp == 0) {
228 /* increment PMC1/2/5/6 field */
229 mask |= 0x8000000000ull;
230 value |= 0x1000000000ull;
231 } else if (grp == 1) {
232 /* increment PMC3/4/7/8 field */
233 mask |= 0x800000000ull;
234 value |= 0x100000000ull;
235 }
236 spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
237 if (spcsel) {
238 mask |= 3ull << 48;
239 value |= (u64)spcsel << 48;
240 }
241 *maskp = mask;
242 *valp = value;
243 return 0;
244}
245
246static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
247{
248 alt[0] = event;
249
250 /* 2 alternatives for LSU empty */
251 if (event == 0x2002 || event == 0x3002) {
252 alt[1] = event ^ 0x1000;
253 return 2;
254 }
255
256 return 1;
257}
258
259static int p970_compute_mmcr(u64 event[], int n_ev,
260 unsigned int hwc[], u64 mmcr[])
261{
262 u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;
263 unsigned int pmc, unit, byte, psel;
264 unsigned int ttm, grp;
265 unsigned int pmc_inuse = 0;
266 unsigned int pmc_grp_use[2];
267 unsigned char busbyte[4];
268 unsigned char unituse[16];
269 unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
270 unsigned char ttmuse[2];
271 unsigned char pmcsel[8];
272 int i;
273 int spcsel;
274
275 if (n_ev > 8)
276 return -1;
277
278 /* First pass to count resource use */
279 pmc_grp_use[0] = pmc_grp_use[1] = 0;
280 memset(busbyte, 0, sizeof(busbyte));
281 memset(unituse, 0, sizeof(unituse));
282 for (i = 0; i < n_ev; ++i) {
283 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
284 if (pmc) {
285 if (pmc_inuse & (1 << (pmc - 1)))
286 return -1;
287 pmc_inuse |= 1 << (pmc - 1);
288 /* count 1/2/5/6 vs 3/4/7/8 use */
289 ++pmc_grp_use[((pmc - 1) >> 1) & 1];
290 }
291 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
292 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
293 if (unit) {
294 if (unit > PM_LASTUNIT)
295 return -1;
296 if (!pmc)
297 ++pmc_grp_use[byte & 1];
298 if (busbyte[byte] && busbyte[byte] != unit)
299 return -1;
300 busbyte[byte] = unit;
301 unituse[unit] = 1;
302 }
303 }
304 if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
305 return -1;
306
307 /*
308 * Assign resources and set multiplexer selects.
309 *
310 * PM_ISU can go either on TTM0 or TTM1, but that's the only
311 * choice we have to deal with.
312 */
313 if (unituse[PM_ISU] &
314 (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
315 unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */
316 /* Set TTM[01]SEL fields. */
317 ttmuse[0] = ttmuse[1] = 0;
318 for (i = PM_FPU; i <= PM_STS; ++i) {
319 if (!unituse[i])
320 continue;
321 ttm = unitmap[i];
322 ++ttmuse[(ttm >> 2) & 1];
323 mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH;
324 }
325 /* Check only one unit per TTMx */
326 if (ttmuse[0] > 1 || ttmuse[1] > 1)
327 return -1;
328
329 /* Set byte lane select fields and TTM3SEL. */
330 for (byte = 0; byte < 4; ++byte) {
331 unit = busbyte[byte];
332 if (!unit)
333 continue;
334 if (unit <= PM_STS)
335 ttm = (unitmap[unit] >> 2) & 1;
336 else if (unit == PM_LSU0)
337 ttm = 2;
338 else {
339 ttm = 3;
340 if (unit == PM_LSU1L && byte >= 2)
341 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
342 }
343 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
344 }
345
346 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
347 memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */
348 for (i = 0; i < n_ev; ++i) {
349 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
350 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
351 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
352 psel = event[i] & PM_PMCSEL_MSK;
353 if (!pmc) {
354 /* Bus event or any-PMC direct event */
355 if (unit)
356 psel |= 0x10 | ((byte & 2) << 2);
357 else
358 psel |= 8;
359 for (pmc = 0; pmc < 8; ++pmc) {
360 if (pmc_inuse & (1 << pmc))
361 continue;
362 grp = (pmc >> 1) & 1;
363 if (unit) {
364 if (grp == (byte & 1))
365 break;
366 } else if (pmc_grp_use[grp] < 4) {
367 ++pmc_grp_use[grp];
368 break;
369 }
370 }
371 pmc_inuse |= 1 << pmc;
372 } else {
373 /* Direct event */
374 --pmc;
375 if (psel == 0 && (byte & 2))
376 /* add events on higher-numbered bus */
377 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
378 }
379 pmcsel[pmc] = psel;
380 hwc[i] = pmc;
381 spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
382 mmcr1 |= spcsel;
383 if (p970_marked_instr_event(event[i]))
384 mmcra |= MMCRA_SAMPLE_ENABLE;
385 }
386 for (pmc = 0; pmc < 2; ++pmc)
387 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
388 for (; pmc < 8; ++pmc)
389 mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
390 if (pmc_inuse & 1)
391 mmcr0 |= MMCR0_PMC1CE;
392 if (pmc_inuse & 0xfe)
393 mmcr0 |= MMCR0_PMCjCE;
394
395 mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
396
397 /* Return MMCRx values */
398 mmcr[0] = mmcr0;
399 mmcr[1] = mmcr1;
400 mmcr[2] = mmcra;
401 return 0;
402}
403
404static void p970_disable_pmc(unsigned int pmc, u64 mmcr[])
405{
406 int shift, i;
407
408 if (pmc <= 1) {
409 shift = MMCR0_PMC1SEL_SH - 7 * pmc;
410 i = 0;
411 } else {
412 shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
413 i = 1;
414 }
415 /*
416 * Setting the PMCxSEL field to 0x08 disables PMC x.
417 */
418 mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
419}
420
421static int ppc970_generic_events[] = {
422 [PERF_COUNT_HW_CPU_CYCLES] = 7,
423 [PERF_COUNT_HW_INSTRUCTIONS] = 1,
424 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */
425 [PERF_COUNT_HW_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */
426 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */
427 [PERF_COUNT_HW_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
428};
429
430#define C(x) PERF_COUNT_HW_CACHE_##x
431
432/*
433 * Table of generalized cache-related events.
434 * 0 means not supported, -1 means nonsensical, other values
435 * are event codes.
436 */
437static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
438 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
439 [C(OP_READ)] = { 0x8810, 0x3810 },
440 [C(OP_WRITE)] = { 0x7810, 0x813 },
441 [C(OP_PREFETCH)] = { 0x731, 0 },
442 },
443 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
444 [C(OP_READ)] = { 0, 0 },
445 [C(OP_WRITE)] = { -1, -1 },
446 [C(OP_PREFETCH)] = { 0, 0 },
447 },
448 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
449 [C(OP_READ)] = { 0, 0 },
450 [C(OP_WRITE)] = { 0, 0 },
451 [C(OP_PREFETCH)] = { 0x733, 0 },
452 },
453 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
454 [C(OP_READ)] = { 0, 0x704 },
455 [C(OP_WRITE)] = { -1, -1 },
456 [C(OP_PREFETCH)] = { -1, -1 },
457 },
458 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
459 [C(OP_READ)] = { 0, 0x700 },
460 [C(OP_WRITE)] = { -1, -1 },
461 [C(OP_PREFETCH)] = { -1, -1 },
462 },
463 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
464 [C(OP_READ)] = { 0x431, 0x327 },
465 [C(OP_WRITE)] = { -1, -1 },
466 [C(OP_PREFETCH)] = { -1, -1 },
467 },
468};
469
470struct power_pmu ppc970_pmu = {
471 .n_counter = 8,
472 .max_alternatives = 2,
473 .add_fields = 0x001100005555ull,
474 .test_adder = 0x013300000000ull,
475 .compute_mmcr = p970_compute_mmcr,
476 .get_constraint = p970_get_constraint,
477 .get_alternatives = p970_get_alternatives,
478 .disable_pmc = p970_disable_pmc,
479 .n_generic = ARRAY_SIZE(ppc970_generic_events),
480 .generic_events = ppc970_generic_events,
481 .cache_events = &ppc970_cache_events,
482};
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index a047a6cfca4d..8ef8a14abc95 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -264,6 +264,7 @@ SECTIONS
264 *(.data.page_aligned) 264 *(.data.page_aligned)
265 } 265 }
266 266
267 . = ALIGN(L1_CACHE_BYTES);
267 .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) { 268 .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
268 *(.data.cacheline_aligned) 269 *(.data.cacheline_aligned)
269 } 270 }
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 9057335fdc61..2cf915e51e7e 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -41,6 +41,12 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
41 return !!(v->arch.pending_exceptions); 41 return !!(v->arch.pending_exceptions);
42} 42}
43 43
44int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
45{
46 /* do real check here */
47 return 1;
48}
49
44int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) 50int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
45{ 51{
46 return !(v->arch.msr & MSR_WE); 52 return !(v->arch.msr & MSR_WE);
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 8db35278a4b4..29b742b90f1f 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
18 memcpy_64.o usercopy_64.o mem_64.o string.o 18 memcpy_64.o usercopy_64.o mem_64.o string.o
19obj-$(CONFIG_XMON) += sstep.o 19obj-$(CONFIG_XMON) += sstep.o
20obj-$(CONFIG_KPROBES) += sstep.o 20obj-$(CONFIG_KPROBES) += sstep.o
21obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
22 21
23ifeq ($(CONFIG_PPC64),y) 22ifeq ($(CONFIG_PPC64),y)
24obj-$(CONFIG_SMP) += locks.o 23obj-$(CONFIG_SMP) += locks.o
diff --git a/arch/powerpc/lib/dma-noncoherent.c b/arch/powerpc/lib/dma-noncoherent.c
deleted file mode 100644
index 005a28d380af..000000000000
--- a/arch/powerpc/lib/dma-noncoherent.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/*
2 * PowerPC version derived from arch/arm/mm/consistent.c
3 * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
4 *
5 * Copyright (C) 2000 Russell King
6 *
7 * Consistent memory allocators. Used for DMA devices that want to
8 * share uncached memory with the processor core. The function return
9 * is the virtual address and 'dma_handle' is the physical address.
10 * Mostly stolen from the ARM port, with some changes for PowerPC.
11 * -- Dan
12 *
13 * Reorganized to get rid of the arch-specific consistent_* functions
14 * and provide non-coherent implementations for the DMA API. -Matt
15 *
16 * Added in_interrupt() safe dma_alloc_coherent()/dma_free_coherent()
17 * implementation. This is pulled straight from ARM and barely
18 * modified. -Matt
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
23 */
24
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/types.h>
30#include <linux/highmem.h>
31#include <linux/dma-mapping.h>
32#include <linux/vmalloc.h>
33
34#include <asm/tlbflush.h>
35
36/*
37 * Allocate DMA-coherent memory space and return both the kernel remapped
38 * virtual and bus address for that space.
39 */
40void *
41__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp)
42{
43 struct page *page;
44 unsigned long order;
45 int i;
46 unsigned int nr_pages = PAGE_ALIGN(size)>>PAGE_SHIFT;
47 unsigned int array_size = nr_pages * sizeof(struct page *);
48 struct page **pages;
49 struct page *end;
50 u64 mask = 0x00ffffff, limit; /* ISA default */
51 struct vm_struct *area;
52
53 BUG_ON(!mem_init_done);
54 size = PAGE_ALIGN(size);
55 limit = (mask + 1) & ~mask;
56 if (limit && size >= limit) {
57 printk(KERN_WARNING "coherent allocation too big (requested "
58 "%#x mask %#Lx)\n", size, mask);
59 return NULL;
60 }
61
62 order = get_order(size);
63
64 if (mask != 0xffffffff)
65 gfp |= GFP_DMA;
66
67 page = alloc_pages(gfp, order);
68 if (!page)
69 goto no_page;
70
71 end = page + (1 << order);
72
73 /*
74 * Invalidate any data that might be lurking in the
75 * kernel direct-mapped region for device DMA.
76 */
77 {
78 unsigned long kaddr = (unsigned long)page_address(page);
79 memset(page_address(page), 0, size);
80 flush_dcache_range(kaddr, kaddr + size);
81 }
82
83 split_page(page, order);
84
85 /*
86 * Set the "dma handle"
87 */
88 *handle = page_to_phys(page);
89
90 area = get_vm_area_caller(size, VM_IOREMAP,
91 __builtin_return_address(1));
92 if (!area)
93 goto out_free_pages;
94
95 if (array_size > PAGE_SIZE) {
96 pages = vmalloc(array_size);
97 area->flags |= VM_VPAGES;
98 } else {
99 pages = kmalloc(array_size, GFP_KERNEL);
100 }
101 if (!pages)
102 goto out_free_area;
103
104 area->pages = pages;
105 area->nr_pages = nr_pages;
106
107 for (i = 0; i < nr_pages; i++)
108 pages[i] = page + i;
109
110 if (map_vm_area(area, pgprot_noncached(PAGE_KERNEL), &pages))
111 goto out_unmap;
112
113 /*
114 * Free the otherwise unused pages.
115 */
116 page += nr_pages;
117 while (page < end) {
118 __free_page(page);
119 page++;
120 }
121
122 return area->addr;
123out_unmap:
124 vunmap(area->addr);
125 if (array_size > PAGE_SIZE)
126 vfree(pages);
127 else
128 kfree(pages);
129 goto out_free_pages;
130out_free_area:
131 free_vm_area(area);
132out_free_pages:
133 if (page)
134 __free_pages(page, order);
135no_page:
136 return NULL;
137}
138EXPORT_SYMBOL(__dma_alloc_coherent);
139
140/*
141 * free a page as defined by the above mapping.
142 */
143void __dma_free_coherent(size_t size, void *vaddr)
144{
145 vfree(vaddr);
146
147}
148EXPORT_SYMBOL(__dma_free_coherent);
149
150/*
151 * make an area consistent.
152 */
153void __dma_sync(void *vaddr, size_t size, int direction)
154{
155 unsigned long start = (unsigned long)vaddr;
156 unsigned long end = start + size;
157
158 switch (direction) {
159 case DMA_NONE:
160 BUG();
161 case DMA_FROM_DEVICE:
162 /*
163 * invalidate only when cache-line aligned otherwise there is
164 * the potential for discarding uncommitted data from the cache
165 */
166 if ((start & (L1_CACHE_BYTES - 1)) || (size & (L1_CACHE_BYTES - 1)))
167 flush_dcache_range(start, end);
168 else
169 invalidate_dcache_range(start, end);
170 break;
171 case DMA_TO_DEVICE: /* writeback only */
172 clean_dcache_range(start, end);
173 break;
174 case DMA_BIDIRECTIONAL: /* writeback and invalidate */
175 flush_dcache_range(start, end);
176 break;
177 }
178}
179EXPORT_SYMBOL(__dma_sync);
180
181#ifdef CONFIG_HIGHMEM
182/*
183 * __dma_sync_page() implementation for systems using highmem.
184 * In this case, each page of a buffer must be kmapped/kunmapped
185 * in order to have a virtual address for __dma_sync(). This must
186 * not sleep so kmap_atomic()/kunmap_atomic() are used.
187 *
188 * Note: yes, it is possible and correct to have a buffer extend
189 * beyond the first page.
190 */
191static inline void __dma_sync_page_highmem(struct page *page,
192 unsigned long offset, size_t size, int direction)
193{
194 size_t seg_size = min((size_t)(PAGE_SIZE - offset), size);
195 size_t cur_size = seg_size;
196 unsigned long flags, start, seg_offset = offset;
197 int nr_segs = 1 + ((size - seg_size) + PAGE_SIZE - 1)/PAGE_SIZE;
198 int seg_nr = 0;
199
200 local_irq_save(flags);
201
202 do {
203 start = (unsigned long)kmap_atomic(page + seg_nr,
204 KM_PPC_SYNC_PAGE) + seg_offset;
205
206 /* Sync this buffer segment */
207 __dma_sync((void *)start, seg_size, direction);
208 kunmap_atomic((void *)start, KM_PPC_SYNC_PAGE);
209 seg_nr++;
210
211 /* Calculate next buffer segment size */
212 seg_size = min((size_t)PAGE_SIZE, size - cur_size);
213
214 /* Add the segment size to our running total */
215 cur_size += seg_size;
216 seg_offset = 0;
217 } while (seg_nr < nr_segs);
218
219 local_irq_restore(flags);
220}
221#endif /* CONFIG_HIGHMEM */
222
223/*
224 * __dma_sync_page makes memory consistent. identical to __dma_sync, but
225 * takes a struct page instead of a virtual address
226 */
227void __dma_sync_page(struct page *page, unsigned long offset,
228 size_t size, int direction)
229{
230#ifdef CONFIG_HIGHMEM
231 __dma_sync_page_highmem(page, offset, size, direction);
232#else
233 unsigned long start = (unsigned long)page_address(page) + offset;
234 __dma_sync((void *)start, size, direction);
235#endif
236}
237EXPORT_SYMBOL(__dma_sync_page);
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 17290bcedc5e..b746f4ca4209 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
26obj-$(CONFIG_PPC_MM_SLICES) += slice.o 26obj-$(CONFIG_PPC_MM_SLICES) += slice.o
27obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 27obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
28obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o 28obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o
29obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
new file mode 100644
index 000000000000..36692f5c9a76
--- /dev/null
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -0,0 +1,400 @@
1/*
2 * PowerPC version derived from arch/arm/mm/consistent.c
3 * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
4 *
5 * Copyright (C) 2000 Russell King
6 *
7 * Consistent memory allocators. Used for DMA devices that want to
8 * share uncached memory with the processor core. The function return
9 * is the virtual address and 'dma_handle' is the physical address.
10 * Mostly stolen from the ARM port, with some changes for PowerPC.
11 * -- Dan
12 *
13 * Reorganized to get rid of the arch-specific consistent_* functions
14 * and provide non-coherent implementations for the DMA API. -Matt
15 *
16 * Added in_interrupt() safe dma_alloc_coherent()/dma_free_coherent()
17 * implementation. This is pulled straight from ARM and barely
18 * modified. -Matt
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
23 */
24
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/types.h>
30#include <linux/highmem.h>
31#include <linux/dma-mapping.h>
32
33#include <asm/tlbflush.h>
34
35#include "mmu_decl.h"
36
37/*
38 * This address range defaults to a value that is safe for all
39 * platforms which currently set CONFIG_NOT_COHERENT_CACHE. It
40 * can be further configured for specific applications under
41 * the "Advanced Setup" menu. -Matt
42 */
43#define CONSISTENT_BASE (IOREMAP_TOP)
44#define CONSISTENT_END (CONSISTENT_BASE + CONFIG_CONSISTENT_SIZE)
45#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
46
47/*
48 * This is the page table (2MB) covering uncached, DMA consistent allocations
49 */
50static DEFINE_SPINLOCK(consistent_lock);
51
52/*
53 * VM region handling support.
54 *
55 * This should become something generic, handling VM region allocations for
56 * vmalloc and similar (ioremap, module space, etc).
57 *
58 * I envisage vmalloc()'s supporting vm_struct becoming:
59 *
60 * struct vm_struct {
61 * struct vm_region region;
62 * unsigned long flags;
63 * struct page **pages;
64 * unsigned int nr_pages;
65 * unsigned long phys_addr;
66 * };
67 *
68 * get_vm_area() would then call vm_region_alloc with an appropriate
69 * struct vm_region head (eg):
70 *
71 * struct vm_region vmalloc_head = {
72 * .vm_list = LIST_HEAD_INIT(vmalloc_head.vm_list),
73 * .vm_start = VMALLOC_START,
74 * .vm_end = VMALLOC_END,
75 * };
76 *
77 * However, vmalloc_head.vm_start is variable (typically, it is dependent on
78 * the amount of RAM found at boot time.) I would imagine that get_vm_area()
79 * would have to initialise this each time prior to calling vm_region_alloc().
80 */
81struct ppc_vm_region {
82 struct list_head vm_list;
83 unsigned long vm_start;
84 unsigned long vm_end;
85};
86
87static struct ppc_vm_region consistent_head = {
88 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
89 .vm_start = CONSISTENT_BASE,
90 .vm_end = CONSISTENT_END,
91};
92
93static struct ppc_vm_region *
94ppc_vm_region_alloc(struct ppc_vm_region *head, size_t size, gfp_t gfp)
95{
96 unsigned long addr = head->vm_start, end = head->vm_end - size;
97 unsigned long flags;
98 struct ppc_vm_region *c, *new;
99
100 new = kmalloc(sizeof(struct ppc_vm_region), gfp);
101 if (!new)
102 goto out;
103
104 spin_lock_irqsave(&consistent_lock, flags);
105
106 list_for_each_entry(c, &head->vm_list, vm_list) {
107 if ((addr + size) < addr)
108 goto nospc;
109 if ((addr + size) <= c->vm_start)
110 goto found;
111 addr = c->vm_end;
112 if (addr > end)
113 goto nospc;
114 }
115
116 found:
117 /*
118 * Insert this entry _before_ the one we found.
119 */
120 list_add_tail(&new->vm_list, &c->vm_list);
121 new->vm_start = addr;
122 new->vm_end = addr + size;
123
124 spin_unlock_irqrestore(&consistent_lock, flags);
125 return new;
126
127 nospc:
128 spin_unlock_irqrestore(&consistent_lock, flags);
129 kfree(new);
130 out:
131 return NULL;
132}
133
134static struct ppc_vm_region *ppc_vm_region_find(struct ppc_vm_region *head, unsigned long addr)
135{
136 struct ppc_vm_region *c;
137
138 list_for_each_entry(c, &head->vm_list, vm_list) {
139 if (c->vm_start == addr)
140 goto out;
141 }
142 c = NULL;
143 out:
144 return c;
145}
146
147/*
148 * Allocate DMA-coherent memory space and return both the kernel remapped
149 * virtual and bus address for that space.
150 */
151void *
152__dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
153{
154 struct page *page;
155 struct ppc_vm_region *c;
156 unsigned long order;
157 u64 mask = ISA_DMA_THRESHOLD, limit;
158
159 if (dev) {
160 mask = dev->coherent_dma_mask;
161
162 /*
163 * Sanity check the DMA mask - it must be non-zero, and
164 * must be able to be satisfied by a DMA allocation.
165 */
166 if (mask == 0) {
167 dev_warn(dev, "coherent DMA mask is unset\n");
168 goto no_page;
169 }
170
171 if ((~mask) & ISA_DMA_THRESHOLD) {
172 dev_warn(dev, "coherent DMA mask %#llx is smaller "
173 "than system GFP_DMA mask %#llx\n",
174 mask, (unsigned long long)ISA_DMA_THRESHOLD);
175 goto no_page;
176 }
177 }
178
179
180 size = PAGE_ALIGN(size);
181 limit = (mask + 1) & ~mask;
182 if ((limit && size >= limit) ||
183 size >= (CONSISTENT_END - CONSISTENT_BASE)) {
184 printk(KERN_WARNING "coherent allocation too big (requested %#x mask %#Lx)\n",
185 size, mask);
186 return NULL;
187 }
188
189 order = get_order(size);
190
191 /* Might be useful if we ever have a real legacy DMA zone... */
192 if (mask != 0xffffffff)
193 gfp |= GFP_DMA;
194
195 page = alloc_pages(gfp, order);
196 if (!page)
197 goto no_page;
198
199 /*
200 * Invalidate any data that might be lurking in the
201 * kernel direct-mapped region for device DMA.
202 */
203 {
204 unsigned long kaddr = (unsigned long)page_address(page);
205 memset(page_address(page), 0, size);
206 flush_dcache_range(kaddr, kaddr + size);
207 }
208
209 /*
210 * Allocate a virtual address in the consistent mapping region.
211 */
212 c = ppc_vm_region_alloc(&consistent_head, size,
213 gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
214 if (c) {
215 unsigned long vaddr = c->vm_start;
216 struct page *end = page + (1 << order);
217
218 split_page(page, order);
219
220 /*
221 * Set the "dma handle"
222 */
223 *handle = page_to_phys(page);
224
225 do {
226 SetPageReserved(page);
227 map_page(vaddr, page_to_phys(page),
228 pgprot_noncached(PAGE_KERNEL));
229 page++;
230 vaddr += PAGE_SIZE;
231 } while (size -= PAGE_SIZE);
232
233 /*
234 * Free the otherwise unused pages.
235 */
236 while (page < end) {
237 __free_page(page);
238 page++;
239 }
240
241 return (void *)c->vm_start;
242 }
243
244 if (page)
245 __free_pages(page, order);
246 no_page:
247 return NULL;
248}
249EXPORT_SYMBOL(__dma_alloc_coherent);
250
251/*
252 * free a page as defined by the above mapping.
253 */
254void __dma_free_coherent(size_t size, void *vaddr)
255{
256 struct ppc_vm_region *c;
257 unsigned long flags, addr;
258
259 size = PAGE_ALIGN(size);
260
261 spin_lock_irqsave(&consistent_lock, flags);
262
263 c = ppc_vm_region_find(&consistent_head, (unsigned long)vaddr);
264 if (!c)
265 goto no_area;
266
267 if ((c->vm_end - c->vm_start) != size) {
268 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
269 __func__, c->vm_end - c->vm_start, size);
270 dump_stack();
271 size = c->vm_end - c->vm_start;
272 }
273
274 addr = c->vm_start;
275 do {
276 pte_t *ptep;
277 unsigned long pfn;
278
279 ptep = pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(addr),
280 addr),
281 addr),
282 addr);
283 if (!pte_none(*ptep) && pte_present(*ptep)) {
284 pfn = pte_pfn(*ptep);
285 pte_clear(&init_mm, addr, ptep);
286 if (pfn_valid(pfn)) {
287 struct page *page = pfn_to_page(pfn);
288
289 ClearPageReserved(page);
290 __free_page(page);
291 }
292 }
293 addr += PAGE_SIZE;
294 } while (size -= PAGE_SIZE);
295
296 flush_tlb_kernel_range(c->vm_start, c->vm_end);
297
298 list_del(&c->vm_list);
299
300 spin_unlock_irqrestore(&consistent_lock, flags);
301
302 kfree(c);
303 return;
304
305 no_area:
306 spin_unlock_irqrestore(&consistent_lock, flags);
307 printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n",
308 __func__, vaddr);
309 dump_stack();
310}
311EXPORT_SYMBOL(__dma_free_coherent);
312
313/*
314 * make an area consistent.
315 */
316void __dma_sync(void *vaddr, size_t size, int direction)
317{
318 unsigned long start = (unsigned long)vaddr;
319 unsigned long end = start + size;
320
321 switch (direction) {
322 case DMA_NONE:
323 BUG();
324 case DMA_FROM_DEVICE:
325 /*
326 * invalidate only when cache-line aligned otherwise there is
327 * the potential for discarding uncommitted data from the cache
328 */
329 if ((start & (L1_CACHE_BYTES - 1)) || (size & (L1_CACHE_BYTES - 1)))
330 flush_dcache_range(start, end);
331 else
332 invalidate_dcache_range(start, end);
333 break;
334 case DMA_TO_DEVICE: /* writeback only */
335 clean_dcache_range(start, end);
336 break;
337 case DMA_BIDIRECTIONAL: /* writeback and invalidate */
338 flush_dcache_range(start, end);
339 break;
340 }
341}
342EXPORT_SYMBOL(__dma_sync);
343
344#ifdef CONFIG_HIGHMEM
345/*
346 * __dma_sync_page() implementation for systems using highmem.
347 * In this case, each page of a buffer must be kmapped/kunmapped
348 * in order to have a virtual address for __dma_sync(). This must
349 * not sleep so kmap_atomic()/kunmap_atomic() are used.
350 *
351 * Note: yes, it is possible and correct to have a buffer extend
352 * beyond the first page.
353 */
354static inline void __dma_sync_page_highmem(struct page *page,
355 unsigned long offset, size_t size, int direction)
356{
357 size_t seg_size = min((size_t)(PAGE_SIZE - offset), size);
358 size_t cur_size = seg_size;
359 unsigned long flags, start, seg_offset = offset;
360 int nr_segs = 1 + ((size - seg_size) + PAGE_SIZE - 1)/PAGE_SIZE;
361 int seg_nr = 0;
362
363 local_irq_save(flags);
364
365 do {
366 start = (unsigned long)kmap_atomic(page + seg_nr,
367 KM_PPC_SYNC_PAGE) + seg_offset;
368
369 /* Sync this buffer segment */
370 __dma_sync((void *)start, seg_size, direction);
371 kunmap_atomic((void *)start, KM_PPC_SYNC_PAGE);
372 seg_nr++;
373
374 /* Calculate next buffer segment size */
375 seg_size = min((size_t)PAGE_SIZE, size - cur_size);
376
377 /* Add the segment size to our running total */
378 cur_size += seg_size;
379 seg_offset = 0;
380 } while (seg_nr < nr_segs);
381
382 local_irq_restore(flags);
383}
384#endif /* CONFIG_HIGHMEM */
385
386/*
387 * __dma_sync_page makes memory consistent. identical to __dma_sync, but
388 * takes a struct page instead of a virtual address
389 */
390void __dma_sync_page(struct page *page, unsigned long offset,
391 size_t size, int direction)
392{
393#ifdef CONFIG_HIGHMEM
394 __dma_sync_page_highmem(page, offset, size, direction);
395#else
396 unsigned long start = (unsigned long)page_address(page) + offset;
397 __dma_sync((void *)start, size, direction);
398#endif
399}
400EXPORT_SYMBOL(__dma_sync_page);
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 76993941cac9..5beffc8f481e 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -29,6 +29,7 @@
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/kprobes.h> 30#include <linux/kprobes.h>
31#include <linux/kdebug.h> 31#include <linux/kdebug.h>
32#include <linux/perf_counter.h>
32 33
33#include <asm/firmware.h> 34#include <asm/firmware.h>
34#include <asm/page.h> 35#include <asm/page.h>
@@ -170,6 +171,8 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
170 die("Weird page fault", regs, SIGSEGV); 171 die("Weird page fault", regs, SIGSEGV);
171 } 172 }
172 173
174 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
175
173 /* When running in the kernel we expect faults to occur only to 176 /* When running in the kernel we expect faults to occur only to
174 * addresses in user space. All other faults represent errors in the 177 * addresses in user space. All other faults represent errors in the
175 * kernel and should generate an OOPS. Unfortunately, in the case of an 178 * kernel and should generate an OOPS. Unfortunately, in the case of an
@@ -309,6 +312,8 @@ good_area:
309 } 312 }
310 if (ret & VM_FAULT_MAJOR) { 313 if (ret & VM_FAULT_MAJOR) {
311 current->maj_flt++; 314 current->maj_flt++;
315 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
316 regs, address);
312#ifdef CONFIG_PPC_SMLPAR 317#ifdef CONFIG_PPC_SMLPAR
313 if (firmware_has_feature(FW_FEATURE_CMO)) { 318 if (firmware_has_feature(FW_FEATURE_CMO)) {
314 preempt_disable(); 319 preempt_disable();
@@ -316,8 +321,11 @@ good_area:
316 preempt_enable(); 321 preempt_enable();
317 } 322 }
318#endif 323#endif
319 } else 324 } else {
320 current->min_flt++; 325 current->min_flt++;
326 perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
327 regs, address);
328 }
321 up_read(&mm->mmap_sem); 329 up_read(&mm->mmap_sem);
322 return 0; 330 return 0;
323 331
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 666a5e8a5be1..3de6a0d93824 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -168,12 +168,8 @@ void __init MMU_init(void)
168 ppc_md.progress("MMU:mapin", 0x301); 168 ppc_md.progress("MMU:mapin", 0x301);
169 mapin_ram(); 169 mapin_ram();
170 170
171#ifdef CONFIG_HIGHMEM 171 /* Initialize early top-down ioremap allocator */
172 ioremap_base = PKMAP_BASE; 172 ioremap_bot = IOREMAP_TOP;
173#else
174 ioremap_base = 0xfe000000UL; /* for now, could be 0xfffff000 */
175#endif /* CONFIG_HIGHMEM */
176 ioremap_bot = ioremap_base;
177 173
178 /* Map in I/O resources */ 174 /* Map in I/O resources */
179 if (ppc_md.progress) 175 if (ppc_md.progress)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index d0602a76bf7f..579382c163a9 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -380,6 +380,23 @@ void __init mem_init(void)
380 bsssize >> 10, 380 bsssize >> 10,
381 initsize >> 10); 381 initsize >> 10);
382 382
383#ifdef CONFIG_PPC32
384 pr_info("Kernel virtual memory layout:\n");
385 pr_info(" * 0x%08lx..0x%08lx : fixmap\n", FIXADDR_START, FIXADDR_TOP);
386#ifdef CONFIG_HIGHMEM
387 pr_info(" * 0x%08lx..0x%08lx : highmem PTEs\n",
388 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP));
389#endif /* CONFIG_HIGHMEM */
390#ifdef CONFIG_NOT_COHERENT_CACHE
391 pr_info(" * 0x%08lx..0x%08lx : consistent mem\n",
392 IOREMAP_TOP, IOREMAP_TOP + CONFIG_CONSISTENT_SIZE);
393#endif /* CONFIG_NOT_COHERENT_CACHE */
394 pr_info(" * 0x%08lx..0x%08lx : early ioremap\n",
395 ioremap_bot, IOREMAP_TOP);
396 pr_info(" * 0x%08lx..0x%08lx : vmalloc & ioremap\n",
397 VMALLOC_START, VMALLOC_END);
398#endif /* CONFIG_PPC32 */
399
383 mem_init_done = 1; 400 mem_init_done = 1;
384} 401}
385 402
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index a70e311bd457..030d0005b4d2 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -127,12 +127,12 @@ static unsigned int steal_context_up(unsigned int id)
127 127
128 pr_debug("[%d] steal context %d from mm @%p\n", cpu, id, mm); 128 pr_debug("[%d] steal context %d from mm @%p\n", cpu, id, mm);
129 129
130 /* Mark this mm has having no context anymore */
131 mm->context.id = MMU_NO_CONTEXT;
132
133 /* Flush the TLB for that context */ 130 /* Flush the TLB for that context */
134 local_flush_tlb_mm(mm); 131 local_flush_tlb_mm(mm);
135 132
133 /* Mark this mm has having no context anymore */
134 mm->context.id = MMU_NO_CONTEXT;
135
136 /* XXX This clear should ultimately be part of local_flush_tlb_mm */ 136 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
137 __clear_bit(id, stale_map[cpu]); 137 __clear_bit(id, stale_map[cpu]);
138 138
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index f5c6fd42265c..ae1d67cc090c 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -219,7 +219,8 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
219 entry = do_dcache_icache_coherency(entry); 219 entry = do_dcache_icache_coherency(entry);
220 changed = !pte_same(*(ptep), entry); 220 changed = !pte_same(*(ptep), entry);
221 if (changed) { 221 if (changed) {
222 assert_pte_locked(vma->vm_mm, address); 222 if (!(vma->vm_flags & VM_HUGETLB))
223 assert_pte_locked(vma->vm_mm, address);
223 __ptep_set_access_flags(ptep, entry); 224 __ptep_set_access_flags(ptep, entry);
224 flush_tlb_page_nohash(vma, address); 225 flush_tlb_page_nohash(vma, address);
225 } 226 }
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 430d0908fa50..5422169626ba 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -399,8 +399,6 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
399#endif /* CONFIG_DEBUG_PAGEALLOC */ 399#endif /* CONFIG_DEBUG_PAGEALLOC */
400 400
401static int fixmaps; 401static int fixmaps;
402unsigned long FIXADDR_TOP = (-PAGE_SIZE);
403EXPORT_SYMBOL(FIXADDR_TOP);
404 402
405void __set_fixmap (enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags) 403void __set_fixmap (enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags)
406{ 404{
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 89497fb04280..3b52c80e5e33 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -2,7 +2,7 @@
2 * PowerPC64 SLB support. 2 * PowerPC64 SLB support.
3 * 3 *
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM 4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 * Based on earlier code writteh by: 5 * Based on earlier code written by:
6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com 6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
7 * Copyright (c) 2001 Dave Engebretsen 7 * Copyright (c) 2001 Dave Engebretsen
8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM 8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 9da795e49337..732ee93a8e98 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -1,6 +1,7 @@
1config PPC64 1config PPC64
2 bool "64-bit kernel" 2 bool "64-bit kernel"
3 default n 3 default n
4 select HAVE_PERF_COUNTERS
4 help 5 help
5 This option selects whether a 32-bit or a 64-bit kernel 6 This option selects whether a 32-bit or a 64-bit kernel
6 will be built. 7 will be built.
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index 301855263b81..04296ffff8bf 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -592,3 +592,17 @@ int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
592 } 592 }
593 return irq; 593 return irq;
594} 594}
595
596static void __devinit quirk_ipr_msi(struct pci_dev *dev)
597{
598 /* Something prevents MSIs from the IPR from working on Bimini,
599 * and the driver has no smarts to recover. So disable MSI
600 * on it for now. */
601
602 if (machine_is(maple)) {
603 dev->no_msi = 1;
604 dev_info(&dev->dev, "Quirk disabled MSI\n");
605 }
606}
607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
608 quirk_ipr_msi);
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 80b513449f4c..be3581a8c294 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -333,7 +333,7 @@ static void xics_eoi_lpar(unsigned int virq)
333 lpar_xirr_info_set((0xff << 24) | irq); 333 lpar_xirr_info_set((0xff << 24) | irq);
334} 334}
335 335
336static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) 336static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
337{ 337{
338 unsigned int irq; 338 unsigned int irq;
339 int status; 339 int status;
@@ -342,14 +342,14 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
342 342
343 irq = (unsigned int)irq_map[virq].hwirq; 343 irq = (unsigned int)irq_map[virq].hwirq;
344 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) 344 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
345 return; 345 return -1;
346 346
347 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); 347 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
348 348
349 if (status) { 349 if (status) {
350 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", 350 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
351 __func__, irq, status); 351 __func__, irq, status);
352 return; 352 return -1;
353 } 353 }
354 354
355 /* 355 /*
@@ -363,7 +363,7 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
363 printk(KERN_WARNING 363 printk(KERN_WARNING
364 "%s: No online cpus in the mask %s for irq %d\n", 364 "%s: No online cpus in the mask %s for irq %d\n",
365 __func__, cpulist, virq); 365 __func__, cpulist, virq);
366 return; 366 return -1;
367 } 367 }
368 368
369 status = rtas_call(ibm_set_xive, 3, 1, NULL, 369 status = rtas_call(ibm_set_xive, 3, 1, NULL,
@@ -372,8 +372,10 @@ static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
372 if (status) { 372 if (status) {
373 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", 373 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
374 __func__, irq, status); 374 __func__, irq, status);
375 return; 375 return -1;
376 } 376 }
377
378 return 0;
377} 379}
378 380
379static struct irq_chip xics_pic_direct = { 381static struct irq_chip xics_pic_direct = {
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index 9e105cbc5e5f..a4779912a5ca 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -250,7 +250,7 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id)
250 250
251 set_capacity(bank->disk, bank->size >> AXON_RAM_SECTOR_SHIFT); 251 set_capacity(bank->disk, bank->size >> AXON_RAM_SECTOR_SHIFT);
252 blk_queue_make_request(bank->disk->queue, axon_ram_make_request); 252 blk_queue_make_request(bank->disk->queue, axon_ram_make_request);
253 blk_queue_hardsect_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE); 253 blk_queue_logical_block_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE);
254 add_disk(bank->disk); 254 add_disk(bank->disk);
255 255
256 bank->irq_id = irq_of_parse_and_map(device->node, 0); 256 bank->irq_id = irq_of_parse_and_map(device->node, 0);
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0efc12d1a3d7..352d8c3ef526 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -807,7 +807,7 @@ static void mpic_end_ipi(unsigned int irq)
807 807
808#endif /* CONFIG_SMP */ 808#endif /* CONFIG_SMP */
809 809
810void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 810int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
811{ 811{
812 struct mpic *mpic = mpic_from_irq(irq); 812 struct mpic *mpic = mpic_from_irq(irq);
813 unsigned int src = mpic_irq_to_hw(irq); 813 unsigned int src = mpic_irq_to_hw(irq);
@@ -824,6 +824,8 @@ void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
824 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 824 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
825 mpic_physmask(cpus_addr(tmp)[0])); 825 mpic_physmask(cpus_addr(tmp)[0]));
826 } 826 }
827
828 return 0;
827} 829}
828 830
829static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) 831static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index 3cef2af10f42..eff433c322a0 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -36,6 +36,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
36 36
37extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); 37extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
38extern void mpic_set_vector(unsigned int virq, unsigned int vector); 38extern void mpic_set_vector(unsigned int virq, unsigned int vector);
39extern void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask); 39extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
40 40
41#endif /* _POWERPC_SYSDEV_MPIC_H */ 41#endif /* _POWERPC_SYSDEV_MPIC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 15:13:51 -0500