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authorStephen Rothwell <sfr@canb.auug.org.au>2008-08-01 01:20:30 -0400
committerPaul Mackerras <paulus@samba.org>2008-08-03 22:02:00 -0400
commitb8b572e1015f81b4e748417be2629dfe51ab99f9 (patch)
tree7df58667d5ed71d6c8f8f4ce40ca16b6fb776d0b /arch/powerpc
parent2b12a4c524812fb3f6ee590a02e65b95c8c32229 (diff)
powerpc: Move include files to arch/powerpc/include/asm
from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/io.h2
-rw-r--r--arch/powerpc/include/asm/8253pit.h10
-rw-r--r--arch/powerpc/include/asm/8xx_immap.h564
-rw-r--r--arch/powerpc/include/asm/Kbuild37
-rw-r--r--arch/powerpc/include/asm/a.out.h20
-rw-r--r--arch/powerpc/include/asm/abs_addr.h75
-rw-r--r--arch/powerpc/include/asm/agp.h22
-rw-r--r--arch/powerpc/include/asm/asm-compat.h69
-rw-r--r--arch/powerpc/include/asm/atomic.h479
-rw-r--r--arch/powerpc/include/asm/auxvec.h19
-rw-r--r--arch/powerpc/include/asm/backlight.h41
-rw-r--r--arch/powerpc/include/asm/bitops.h410
-rw-r--r--arch/powerpc/include/asm/bootx.h171
-rw-r--r--arch/powerpc/include/asm/btext.h28
-rw-r--r--arch/powerpc/include/asm/bug.h121
-rw-r--r--arch/powerpc/include/asm/bugs.h18
-rw-r--r--arch/powerpc/include/asm/byteorder.h89
-rw-r--r--arch/powerpc/include/asm/cache.h45
-rw-r--r--arch/powerpc/include/asm/cacheflush.h75
-rw-r--r--arch/powerpc/include/asm/cell-pmu.h105
-rw-r--r--arch/powerpc/include/asm/cell-regs.h315
-rw-r--r--arch/powerpc/include/asm/checksum.h117
-rw-r--r--arch/powerpc/include/asm/clk_interface.h20
-rw-r--r--arch/powerpc/include/asm/code-patching.h54
-rw-r--r--arch/powerpc/include/asm/compat.h214
-rw-r--r--arch/powerpc/include/asm/cpm.h106
-rw-r--r--arch/powerpc/include/asm/cpm1.h652
-rw-r--r--arch/powerpc/include/asm/cpm2.h1195
-rw-r--r--arch/powerpc/include/asm/cputable.h514
-rw-r--r--arch/powerpc/include/asm/cputhreads.h71
-rw-r--r--arch/powerpc/include/asm/cputime.h235
-rw-r--r--arch/powerpc/include/asm/current.h40
-rw-r--r--arch/powerpc/include/asm/dbdma.h108
-rw-r--r--arch/powerpc/include/asm/dcr-generic.h49
-rw-r--r--arch/powerpc/include/asm/dcr-mmio.h61
-rw-r--r--arch/powerpc/include/asm/dcr-native.h116
-rw-r--r--arch/powerpc/include/asm/dcr-regs.h149
-rw-r--r--arch/powerpc/include/asm/dcr.h82
-rw-r--r--arch/powerpc/include/asm/delay.h34
-rw-r--r--arch/powerpc/include/asm/device.h24
-rw-r--r--arch/powerpc/include/asm/div64.h1
-rw-r--r--arch/powerpc/include/asm/dma-mapping.h474
-rw-r--r--arch/powerpc/include/asm/dma.h360
-rw-r--r--arch/powerpc/include/asm/edac.h40
-rw-r--r--arch/powerpc/include/asm/eeh.h211
-rw-r--r--arch/powerpc/include/asm/eeh_event.h53
-rw-r--r--arch/powerpc/include/asm/elf.h424
-rw-r--r--arch/powerpc/include/asm/emergency-restart.h1
-rw-r--r--arch/powerpc/include/asm/errno.h11
-rw-r--r--arch/powerpc/include/asm/exception.h311
-rw-r--r--arch/powerpc/include/asm/fb.h21
-rw-r--r--arch/powerpc/include/asm/fcntl.h11
-rw-r--r--arch/powerpc/include/asm/feature-fixups.h126
-rw-r--r--arch/powerpc/include/asm/firmware.h132
-rw-r--r--arch/powerpc/include/asm/fixmap.h106
-rw-r--r--arch/powerpc/include/asm/floppy.h213
-rw-r--r--arch/powerpc/include/asm/fs_pd.h50
-rw-r--r--arch/powerpc/include/asm/fsl_gtm.h47
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h311
-rw-r--r--arch/powerpc/include/asm/ftrace.h14
-rw-r--r--arch/powerpc/include/asm/futex.h117
-rw-r--r--arch/powerpc/include/asm/gpio.h56
-rw-r--r--arch/powerpc/include/asm/grackle.h12
-rw-r--r--arch/powerpc/include/asm/hardirq.h29
-rw-r--r--arch/powerpc/include/asm/heathrow.h67
-rw-r--r--arch/powerpc/include/asm/highmem.h138
-rw-r--r--arch/powerpc/include/asm/hugetlb.h75
-rw-r--r--arch/powerpc/include/asm/hvcall.h296
-rw-r--r--arch/powerpc/include/asm/hvconsole.h41
-rw-r--r--arch/powerpc/include/asm/hvcserver.h59
-rw-r--r--arch/powerpc/include/asm/hw_irq.h135
-rw-r--r--arch/powerpc/include/asm/hydra.h102
-rw-r--r--arch/powerpc/include/asm/i8259.h17
-rw-r--r--arch/powerpc/include/asm/ibmebus.h60
-rw-r--r--arch/powerpc/include/asm/ide.h59
-rw-r--r--arch/powerpc/include/asm/immap_86xx.h156
-rw-r--r--arch/powerpc/include/asm/immap_cpm2.h650
-rw-r--r--arch/powerpc/include/asm/immap_qe.h483
-rw-r--r--arch/powerpc/include/asm/io-defs.h60
-rw-r--r--arch/powerpc/include/asm/io.h787
-rw-r--r--arch/powerpc/include/asm/ioctl.h13
-rw-r--r--arch/powerpc/include/asm/ioctls.h110
-rw-r--r--arch/powerpc/include/asm/iommu.h131
-rw-r--r--arch/powerpc/include/asm/ipcbuf.h34
-rw-r--r--arch/powerpc/include/asm/ipic.h91
-rw-r--r--arch/powerpc/include/asm/irq.h654
-rw-r--r--arch/powerpc/include/asm/irq_regs.h2
-rw-r--r--arch/powerpc/include/asm/irqflags.h42
-rw-r--r--arch/powerpc/include/asm/iseries/alpaca.h31
-rw-r--r--arch/powerpc/include/asm/iseries/hv_call.h111
-rw-r--r--arch/powerpc/include/asm/iseries/hv_call_event.h201
-rw-r--r--arch/powerpc/include/asm/iseries/hv_call_sc.h50
-rw-r--r--arch/powerpc/include/asm/iseries/hv_call_xm.h61
-rw-r--r--arch/powerpc/include/asm/iseries/hv_lp_config.h128
-rw-r--r--arch/powerpc/include/asm/iseries/hv_lp_event.h162
-rw-r--r--arch/powerpc/include/asm/iseries/hv_types.h112
-rw-r--r--arch/powerpc/include/asm/iseries/iommu.h41
-rw-r--r--arch/powerpc/include/asm/iseries/it_lp_queue.h78
-rw-r--r--arch/powerpc/include/asm/iseries/lpar_map.h85
-rw-r--r--arch/powerpc/include/asm/iseries/mf.h51
-rw-r--r--arch/powerpc/include/asm/iseries/vio.h265
-rw-r--r--arch/powerpc/include/asm/kdebug.h15
-rw-r--r--arch/powerpc/include/asm/kdump.h35
-rw-r--r--arch/powerpc/include/asm/kexec.h160
-rw-r--r--arch/powerpc/include/asm/keylargo.h261
-rw-r--r--arch/powerpc/include/asm/kgdb.h63
-rw-r--r--arch/powerpc/include/asm/kmap_types.h33
-rw-r--r--arch/powerpc/include/asm/kprobes.h118
-rw-r--r--arch/powerpc/include/asm/kvm.h55
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h55
-rw-r--r--arch/powerpc/include/asm/kvm_host.h155
-rw-r--r--arch/powerpc/include/asm/kvm_para.h37
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h95
-rw-r--r--arch/powerpc/include/asm/libata-portmap.h12
-rw-r--r--arch/powerpc/include/asm/linkage.h6
-rw-r--r--arch/powerpc/include/asm/lmb.h15
-rw-r--r--arch/powerpc/include/asm/local.h200
-rw-r--r--arch/powerpc/include/asm/lppaca.h159
-rw-r--r--arch/powerpc/include/asm/lv1call.h348
-rw-r--r--arch/powerpc/include/asm/machdep.h365
-rw-r--r--arch/powerpc/include/asm/macio.h142
-rw-r--r--arch/powerpc/include/asm/mc146818rtc.h36
-rw-r--r--arch/powerpc/include/asm/mediabay.h43
-rw-r--r--arch/powerpc/include/asm/mman.h63
-rw-r--r--arch/powerpc/include/asm/mmu-40x.h63
-rw-r--r--arch/powerpc/include/asm/mmu-44x.h76
-rw-r--r--arch/powerpc/include/asm/mmu-8xx.h145
-rw-r--r--arch/powerpc/include/asm/mmu-fsl-booke.h82
-rw-r--r--arch/powerpc/include/asm/mmu-hash32.h83
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h478
-rw-r--r--arch/powerpc/include/asm/mmu.h26
-rw-r--r--arch/powerpc/include/asm/mmu_context.h280
-rw-r--r--arch/powerpc/include/asm/mmzone.h47
-rw-r--r--arch/powerpc/include/asm/module.h77
-rw-r--r--arch/powerpc/include/asm/mpc512x.h22
-rw-r--r--arch/powerpc/include/asm/mpc52xx.h295
-rw-r--r--arch/powerpc/include/asm/mpc52xx_psc.h276
-rw-r--r--arch/powerpc/include/asm/mpc6xx.h6
-rw-r--r--arch/powerpc/include/asm/mpc8260.h25
-rw-r--r--arch/powerpc/include/asm/mpc86xx.h33
-rw-r--r--arch/powerpc/include/asm/mpc8xx.h12
-rw-r--r--arch/powerpc/include/asm/mpic.h481
-rw-r--r--arch/powerpc/include/asm/msgbuf.h33
-rw-r--r--arch/powerpc/include/asm/mutex.h9
-rw-r--r--arch/powerpc/include/asm/nvram.h139
-rw-r--r--arch/powerpc/include/asm/of_device.h31
-rw-r--r--arch/powerpc/include/asm/of_platform.h42
-rw-r--r--arch/powerpc/include/asm/ohare.h54
-rw-r--r--arch/powerpc/include/asm/oprofile_impl.h134
-rw-r--r--arch/powerpc/include/asm/pSeries_reconfig.h29
-rw-r--r--arch/powerpc/include/asm/paca.h112
-rw-r--r--arch/powerpc/include/asm/page.h225
-rw-r--r--arch/powerpc/include/asm/page_32.h38
-rw-r--r--arch/powerpc/include/asm/page_64.h185
-rw-r--r--arch/powerpc/include/asm/param.h22
-rw-r--r--arch/powerpc/include/asm/parport.h39
-rw-r--r--arch/powerpc/include/asm/pasemi_dma.h538
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h302
-rw-r--r--arch/powerpc/include/asm/pci.h228
-rw-r--r--arch/powerpc/include/asm/percpu.h24
-rw-r--r--arch/powerpc/include/asm/pgalloc-32.h43
-rw-r--r--arch/powerpc/include/asm/pgalloc-64.h166
-rw-r--r--arch/powerpc/include/asm/pgalloc.h12
-rw-r--r--arch/powerpc/include/asm/pgtable-4k.h117
-rw-r--r--arch/powerpc/include/asm/pgtable-64k.h155
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h802
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h468
-rw-r--r--arch/powerpc/include/asm/pgtable.h57
-rw-r--r--arch/powerpc/include/asm/phyp_dump.h47
-rw-r--r--arch/powerpc/include/asm/pmac_feature.h405
-rw-r--r--arch/powerpc/include/asm/pmac_low_i2c.h107
-rw-r--r--arch/powerpc/include/asm/pmac_pfunc.h252
-rw-r--r--arch/powerpc/include/asm/pmc.h37
-rw-r--r--arch/powerpc/include/asm/pmi.h66
-rw-r--r--arch/powerpc/include/asm/poll.h1
-rw-r--r--arch/powerpc/include/asm/posix_types.h128
-rw-r--r--arch/powerpc/include/asm/ppc-pci.h149
-rw-r--r--arch/powerpc/include/asm/ppc4xx.h18
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h689
-rw-r--r--arch/powerpc/include/asm/processor.h314
-rw-r--r--arch/powerpc/include/asm/prom.h356
-rw-r--r--arch/powerpc/include/asm/ps3.h519
-rw-r--r--arch/powerpc/include/asm/ps3av.h744
-rw-r--r--arch/powerpc/include/asm/ps3fb.h44
-rw-r--r--arch/powerpc/include/asm/ps3stor.h71
-rw-r--r--arch/powerpc/include/asm/ptrace.h293
-rw-r--r--arch/powerpc/include/asm/qe.h642
-rw-r--r--arch/powerpc/include/asm/qe_ic.h128
-rw-r--r--arch/powerpc/include/asm/reg.h788
-rw-r--r--arch/powerpc/include/asm/reg_8xx.h42
-rw-r--r--arch/powerpc/include/asm/reg_booke.h501
-rw-r--r--arch/powerpc/include/asm/reg_fsl_emb.h72
-rw-r--r--arch/powerpc/include/asm/resource.h1
-rw-r--r--arch/powerpc/include/asm/rheap.h89
-rw-r--r--arch/powerpc/include/asm/rio.h18
-rw-r--r--arch/powerpc/include/asm/rtas.h247
-rw-r--r--arch/powerpc/include/asm/rtc.h78
-rw-r--r--arch/powerpc/include/asm/rwsem.h173
-rw-r--r--arch/powerpc/include/asm/scatterlist.h50
-rw-r--r--arch/powerpc/include/asm/seccomp.h20
-rw-r--r--arch/powerpc/include/asm/sections.h22
-rw-r--r--arch/powerpc/include/asm/sembuf.h36
-rw-r--r--arch/powerpc/include/asm/serial.h24
-rw-r--r--arch/powerpc/include/asm/setjmp.h18
-rw-r--r--arch/powerpc/include/asm/setup.h6
-rw-r--r--arch/powerpc/include/asm/shmbuf.h59
-rw-r--r--arch/powerpc/include/asm/shmparam.h6
-rw-r--r--arch/powerpc/include/asm/sigcontext.h87
-rw-r--r--arch/powerpc/include/asm/siginfo.h26
-rw-r--r--arch/powerpc/include/asm/signal.h150
-rw-r--r--arch/powerpc/include/asm/smp.h127
-rw-r--r--arch/powerpc/include/asm/smu.h700
-rw-r--r--arch/powerpc/include/asm/socket.h64
-rw-r--r--arch/powerpc/include/asm/sockios.h20
-rw-r--r--arch/powerpc/include/asm/sparsemem.h32
-rw-r--r--arch/powerpc/include/asm/spinlock.h295
-rw-r--r--arch/powerpc/include/asm/spinlock_types.h20
-rw-r--r--arch/powerpc/include/asm/spu.h732
-rw-r--r--arch/powerpc/include/asm/spu_csa.h266
-rw-r--r--arch/powerpc/include/asm/spu_info.h54
-rw-r--r--arch/powerpc/include/asm/spu_priv1.h236
-rw-r--r--arch/powerpc/include/asm/sstep.h27
-rw-r--r--arch/powerpc/include/asm/stat.h81
-rw-r--r--arch/powerpc/include/asm/statfs.h60
-rw-r--r--arch/powerpc/include/asm/string.h32
-rw-r--r--arch/powerpc/include/asm/suspend.h9
-rw-r--r--arch/powerpc/include/asm/synch.h44
-rw-r--r--arch/powerpc/include/asm/syscall.h84
-rw-r--r--arch/powerpc/include/asm/syscalls.h52
-rw-r--r--arch/powerpc/include/asm/systbl.h324
-rw-r--r--arch/powerpc/include/asm/system.h548
-rw-r--r--arch/powerpc/include/asm/tce.h50
-rw-r--r--arch/powerpc/include/asm/termbits.h209
-rw-r--r--arch/powerpc/include/asm/termios.h85
-rw-r--r--arch/powerpc/include/asm/thread_info.h161
-rw-r--r--arch/powerpc/include/asm/time.h255
-rw-r--r--arch/powerpc/include/asm/timex.h50
-rw-r--r--arch/powerpc/include/asm/tlb.h81
-rw-r--r--arch/powerpc/include/asm/tlbflush.h166
-rw-r--r--arch/powerpc/include/asm/topology.h117
-rw-r--r--arch/powerpc/include/asm/tsi108.h121
-rw-r--r--arch/powerpc/include/asm/tsi108_irq.h124
-rw-r--r--arch/powerpc/include/asm/tsi108_pci.h45
-rw-r--r--arch/powerpc/include/asm/types.h75
-rw-r--r--arch/powerpc/include/asm/uaccess.h496
-rw-r--r--arch/powerpc/include/asm/ucc.h64
-rw-r--r--arch/powerpc/include/asm/ucc_fast.h244
-rw-r--r--arch/powerpc/include/asm/ucc_slow.h290
-rw-r--r--arch/powerpc/include/asm/ucontext.h40
-rw-r--r--arch/powerpc/include/asm/udbg.h55
-rw-r--r--arch/powerpc/include/asm/uic.h21
-rw-r--r--arch/powerpc/include/asm/unaligned.h16
-rw-r--r--arch/powerpc/include/asm/uninorth.h229
-rw-r--r--arch/powerpc/include/asm/unistd.h398
-rw-r--r--arch/powerpc/include/asm/user.h51
-rw-r--r--arch/powerpc/include/asm/vdso.h78
-rw-r--r--arch/powerpc/include/asm/vdso_datapage.h121
-rw-r--r--arch/powerpc/include/asm/vga.h53
-rw-r--r--arch/powerpc/include/asm/vio.h118
-rw-r--r--arch/powerpc/include/asm/xilinx_intc.h20
-rw-r--r--arch/powerpc/include/asm/xmon.h33
-rw-r--r--arch/powerpc/include/asm/xor.h1
-rw-r--r--arch/powerpc/mm/tlb_64.c2
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_smp.c2
264 files changed, 39505 insertions, 3 deletions
diff --git a/arch/powerpc/boot/io.h b/arch/powerpc/boot/io.h
index ccaedaec50d5..7c09f4861fe1 100644
--- a/arch/powerpc/boot/io.h
+++ b/arch/powerpc/boot/io.h
@@ -6,7 +6,7 @@
6/* 6/*
7 * Low-level I/O routines. 7 * Low-level I/O routines.
8 * 8 *
9 * Copied from <file:include/asm-powerpc/io.h> (which has no copyright) 9 * Copied from <file:arch/powerpc/include/asm/io.h> (which has no copyright)
10 */ 10 */
11static inline int in_8(const volatile unsigned char *addr) 11static inline int in_8(const volatile unsigned char *addr)
12{ 12{
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h
new file mode 100644
index 000000000000..b70d6e53b303
--- /dev/null
+++ b/arch/powerpc/include/asm/8253pit.h
@@ -0,0 +1,10 @@
1#ifndef _ASM_POWERPC_8253PIT_H
2#define _ASM_POWERPC_8253PIT_H
3
4/*
5 * 8253/8254 Programmable Interval Timer
6 */
7
8#define PIT_TICK_RATE 1193182UL
9
10#endif /* _ASM_POWERPC_8253PIT_H */
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
new file mode 100644
index 000000000000..4b0e15206006
--- /dev/null
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -0,0 +1,564 @@
1/*
2 * MPC8xx Internal Memory Map
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * The I/O on the MPC860 is comprised of blocks of special registers
6 * and the dual port ram for the Communication Processor Module.
7 * Within this space are functional units such as the SIU, memory
8 * controller, system timers, and other control functions. It is
9 * a combination that I found difficult to separate into logical
10 * functional files.....but anyone else is welcome to try. -- Dan
11 */
12#ifdef __KERNEL__
13#ifndef __IMMAP_8XX__
14#define __IMMAP_8XX__
15
16/* System configuration registers.
17*/
18typedef struct sys_conf {
19 uint sc_siumcr;
20 uint sc_sypcr;
21 uint sc_swt;
22 char res1[2];
23 ushort sc_swsr;
24 uint sc_sipend;
25 uint sc_simask;
26 uint sc_siel;
27 uint sc_sivec;
28 uint sc_tesr;
29 char res2[0xc];
30 uint sc_sdcr;
31 char res3[0x4c];
32} sysconf8xx_t;
33
34/* PCMCIA configuration registers.
35*/
36typedef struct pcmcia_conf {
37 uint pcmc_pbr0;
38 uint pcmc_por0;
39 uint pcmc_pbr1;
40 uint pcmc_por1;
41 uint pcmc_pbr2;
42 uint pcmc_por2;
43 uint pcmc_pbr3;
44 uint pcmc_por3;
45 uint pcmc_pbr4;
46 uint pcmc_por4;
47 uint pcmc_pbr5;
48 uint pcmc_por5;
49 uint pcmc_pbr6;
50 uint pcmc_por6;
51 uint pcmc_pbr7;
52 uint pcmc_por7;
53 char res1[0x20];
54 uint pcmc_pgcra;
55 uint pcmc_pgcrb;
56 uint pcmc_pscr;
57 char res2[4];
58 uint pcmc_pipr;
59 char res3[4];
60 uint pcmc_per;
61 char res4[4];
62} pcmconf8xx_t;
63
64/* Memory controller registers.
65*/
66typedef struct mem_ctlr {
67 uint memc_br0;
68 uint memc_or0;
69 uint memc_br1;
70 uint memc_or1;
71 uint memc_br2;
72 uint memc_or2;
73 uint memc_br3;
74 uint memc_or3;
75 uint memc_br4;
76 uint memc_or4;
77 uint memc_br5;
78 uint memc_or5;
79 uint memc_br6;
80 uint memc_or6;
81 uint memc_br7;
82 uint memc_or7;
83 char res1[0x24];
84 uint memc_mar;
85 uint memc_mcr;
86 char res2[4];
87 uint memc_mamr;
88 uint memc_mbmr;
89 ushort memc_mstat;
90 ushort memc_mptpr;
91 uint memc_mdr;
92 char res3[0x80];
93} memctl8xx_t;
94
95/*-----------------------------------------------------------------------
96 * BR - Memory Controler: Base Register 16-9
97 */
98#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99#define BR_AT_MSK 0x00007000 /* Address Type Mask */
100#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101#define BR_PS_32 0x00000000 /* 32 bit port size */
102#define BR_PS_16 0x00000800 /* 16 bit port size */
103#define BR_PS_8 0x00000400 /* 8 bit port size */
104#define BR_PARE 0x00000200 /* Parity Enable */
105#define BR_WP 0x00000100 /* Write Protect */
106#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
107#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
110#define BR_V 0x00000001 /* Bank Valid */
111
112/*-----------------------------------------------------------------------
113 * OR - Memory Controler: Option Register 16-11
114 */
115#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
116#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
117#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
118 /* Address Multiplex */
119#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
120#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
143#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
144#define OR_TRLX 0x00000004 /* Timing Relaxed */
145#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
146
147/* System Integration Timers.
148*/
149typedef struct sys_int_timers {
150 ushort sit_tbscr;
151 char res0[0x02];
152 uint sit_tbreff0;
153 uint sit_tbreff1;
154 char res1[0x14];
155 ushort sit_rtcsc;
156 char res2[0x02];
157 uint sit_rtc;
158 uint sit_rtsec;
159 uint sit_rtcal;
160 char res3[0x10];
161 ushort sit_piscr;
162 char res4[2];
163 uint sit_pitc;
164 uint sit_pitr;
165 char res5[0x34];
166} sit8xx_t;
167
168#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169#define TBSCR_REFA ((ushort)0x0080)
170#define TBSCR_REFB ((ushort)0x0040)
171#define TBSCR_REFAE ((ushort)0x0008)
172#define TBSCR_REFBE ((ushort)0x0004)
173#define TBSCR_TBF ((ushort)0x0002)
174#define TBSCR_TBE ((ushort)0x0001)
175
176#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177#define RTCSC_SEC ((ushort)0x0080)
178#define RTCSC_ALR ((ushort)0x0040)
179#define RTCSC_38K ((ushort)0x0010)
180#define RTCSC_SIE ((ushort)0x0008)
181#define RTCSC_ALE ((ushort)0x0004)
182#define RTCSC_RTF ((ushort)0x0002)
183#define RTCSC_RTE ((ushort)0x0001)
184
185#define PISCR_PIRQ_MASK ((ushort)0xff00)
186#define PISCR_PS ((ushort)0x0080)
187#define PISCR_PIE ((ushort)0x0004)
188#define PISCR_PTF ((ushort)0x0002)
189#define PISCR_PTE ((ushort)0x0001)
190
191/* Clocks and Reset.
192*/
193typedef struct clk_and_reset {
194 uint car_sccr;
195 uint car_plprcr;
196 uint car_rsr;
197 char res[0x74]; /* Reserved area */
198} car8xx_t;
199
200/* System Integration Timers keys.
201*/
202typedef struct sitk {
203 uint sitk_tbscrk;
204 uint sitk_tbreff0k;
205 uint sitk_tbreff1k;
206 uint sitk_tbk;
207 char res1[0x10];
208 uint sitk_rtcsck;
209 uint sitk_rtck;
210 uint sitk_rtseck;
211 uint sitk_rtcalk;
212 char res2[0x10];
213 uint sitk_piscrk;
214 uint sitk_pitck;
215 char res3[0x38];
216} sitk8xx_t;
217
218/* Clocks and reset keys.
219*/
220typedef struct cark {
221 uint cark_sccrk;
222 uint cark_plprcrk;
223 uint cark_rsrk;
224 char res[0x474];
225} cark8xx_t;
226
227/* The key to unlock registers maintained by keep-alive power.
228*/
229#define KAPWR_KEY ((unsigned int)0x55ccaa33)
230
231/* Video interface. MPC823 Only.
232*/
233typedef struct vid823 {
234 ushort vid_vccr;
235 ushort res1;
236 u_char vid_vsr;
237 u_char res2;
238 u_char vid_vcmr;
239 u_char res3;
240 uint vid_vbcb;
241 uint res4;
242 uint vid_vfcr0;
243 uint vid_vfaa0;
244 uint vid_vfba0;
245 uint vid_vfcr1;
246 uint vid_vfaa1;
247 uint vid_vfba1;
248 u_char res5[0x18];
249} vid823_t;
250
251/* LCD interface. 823 Only.
252*/
253typedef struct lcd {
254 uint lcd_lccr;
255 uint lcd_lchcr;
256 uint lcd_lcvcr;
257 char res1[4];
258 uint lcd_lcfaa;
259 uint lcd_lcfba;
260 char lcd_lcsr;
261 char res2[0x7];
262} lcd823_t;
263
264/* I2C
265*/
266typedef struct i2c {
267 u_char i2c_i2mod;
268 char res1[3];
269 u_char i2c_i2add;
270 char res2[3];
271 u_char i2c_i2brg;
272 char res3[3];
273 u_char i2c_i2com;
274 char res4[3];
275 u_char i2c_i2cer;
276 char res5[3];
277 u_char i2c_i2cmr;
278 char res6[0x8b];
279} i2c8xx_t;
280
281/* DMA control/status registers.
282*/
283typedef struct sdma_csr {
284 char res1[4];
285 uint sdma_sdar;
286 u_char sdma_sdsr;
287 char res3[3];
288 u_char sdma_sdmr;
289 char res4[3];
290 u_char sdma_idsr1;
291 char res5[3];
292 u_char sdma_idmr1;
293 char res6[3];
294 u_char sdma_idsr2;
295 char res7[3];
296 u_char sdma_idmr2;
297 char res8[0x13];
298} sdma8xx_t;
299
300/* Communication Processor Module Interrupt Controller.
301*/
302typedef struct cpm_ic {
303 ushort cpic_civr;
304 char res[0xe];
305 uint cpic_cicr;
306 uint cpic_cipr;
307 uint cpic_cimr;
308 uint cpic_cisr;
309} cpic8xx_t;
310
311/* Input/Output Port control/status registers.
312*/
313typedef struct io_port {
314 ushort iop_padir;
315 ushort iop_papar;
316 ushort iop_paodr;
317 ushort iop_padat;
318 char res1[8];
319 ushort iop_pcdir;
320 ushort iop_pcpar;
321 ushort iop_pcso;
322 ushort iop_pcdat;
323 ushort iop_pcint;
324 char res2[6];
325 ushort iop_pddir;
326 ushort iop_pdpar;
327 char res3[2];
328 ushort iop_pddat;
329 uint utmode;
330 char res4[4];
331} iop8xx_t;
332
333/* Communication Processor Module Timers
334*/
335typedef struct cpm_timers {
336 ushort cpmt_tgcr;
337 char res1[0xe];
338 ushort cpmt_tmr1;
339 ushort cpmt_tmr2;
340 ushort cpmt_trr1;
341 ushort cpmt_trr2;
342 ushort cpmt_tcr1;
343 ushort cpmt_tcr2;
344 ushort cpmt_tcn1;
345 ushort cpmt_tcn2;
346 ushort cpmt_tmr3;
347 ushort cpmt_tmr4;
348 ushort cpmt_trr3;
349 ushort cpmt_trr4;
350 ushort cpmt_tcr3;
351 ushort cpmt_tcr4;
352 ushort cpmt_tcn3;
353 ushort cpmt_tcn4;
354 ushort cpmt_ter1;
355 ushort cpmt_ter2;
356 ushort cpmt_ter3;
357 ushort cpmt_ter4;
358 char res2[8];
359} cpmtimer8xx_t;
360
361/* Finally, the Communication Processor stuff.....
362*/
363typedef struct scc { /* Serial communication channels */
364 uint scc_gsmrl;
365 uint scc_gsmrh;
366 ushort scc_psmr;
367 char res1[2];
368 ushort scc_todr;
369 ushort scc_dsr;
370 ushort scc_scce;
371 char res2[2];
372 ushort scc_sccm;
373 char res3;
374 u_char scc_sccs;
375 char res4[8];
376} scc_t;
377
378typedef struct smc { /* Serial management channels */
379 char res1[2];
380 ushort smc_smcmr;
381 char res2[2];
382 u_char smc_smce;
383 char res3[3];
384 u_char smc_smcm;
385 char res4[5];
386} smc_t;
387
388/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
389 * it fits within the address space.
390 */
391
392typedef struct fec {
393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */
401 uint res2[9]; /* reserved */
402 uint fec_ecntrl; /* ethernet control register */
403 uint fec_ievent; /* interrupt event register */
404 uint fec_imask; /* interrupt mask register */
405 uint fec_ivec; /* interrupt level and vector status */
406 uint fec_r_des_active; /* Rx ring updated flag */
407 uint fec_x_des_active; /* Tx ring updated flag */
408 uint res3[10]; /* reserved */
409 uint fec_mii_data; /* MII data register */
410 uint fec_mii_speed; /* MII speed control register */
411 uint res4[17]; /* reserved */
412 uint fec_r_bound; /* end of RAM (read-only) */
413 uint fec_r_fstart; /* Rx FIFO start address */
414 uint res5[6]; /* reserved */
415 uint fec_x_fstart; /* Tx FIFO start address */
416 uint res6[17]; /* reserved */
417 uint fec_fun_code; /* fec SDMA function code */
418 uint res7[3]; /* reserved */
419 uint fec_r_cntrl; /* Rx control register */
420 uint fec_r_hash; /* Rx hash register */
421 uint res8[14]; /* reserved */
422 uint fec_x_cntrl; /* Tx control register */
423 uint res9[0x1e]; /* reserved */
424} fec_t;
425
426/* The FEC and LCD color map share the same address space....
427 * I guess we will never see an 823T :-).
428 */
429union fec_lcd {
430 fec_t fl_un_fec;
431 u_char fl_un_cmap[0x200];
432};
433
434typedef struct comm_proc {
435 /* General control and status registers.
436 */
437 ushort cp_cpcr;
438 u_char res1[2];
439 ushort cp_rccr;
440 u_char res2;
441 u_char cp_rmds;
442 u_char res3[4];
443 ushort cp_cpmcr1;
444 ushort cp_cpmcr2;
445 ushort cp_cpmcr3;
446 ushort cp_cpmcr4;
447 u_char res4[2];
448 ushort cp_rter;
449 u_char res5[2];
450 ushort cp_rtmr;
451 u_char res6[0x14];
452
453 /* Baud rate generators.
454 */
455 uint cp_brgc1;
456 uint cp_brgc2;
457 uint cp_brgc3;
458 uint cp_brgc4;
459
460 /* Serial Communication Channels.
461 */
462 scc_t cp_scc[4];
463
464 /* Serial Management Channels.
465 */
466 smc_t cp_smc[2];
467
468 /* Serial Peripheral Interface.
469 */
470 ushort cp_spmode;
471 u_char res7[4];
472 u_char cp_spie;
473 u_char res8[3];
474 u_char cp_spim;
475 u_char res9[2];
476 u_char cp_spcom;
477 u_char res10[2];
478
479 /* Parallel Interface Port.
480 */
481 u_char res11[2];
482 ushort cp_pipc;
483 u_char res12[2];
484 ushort cp_ptpr;
485 uint cp_pbdir;
486 uint cp_pbpar;
487 u_char res13[2];
488 ushort cp_pbodr;
489 uint cp_pbdat;
490
491 /* Port E - MPC87x/88x only.
492 */
493 uint cp_pedir;
494 uint cp_pepar;
495 uint cp_peso;
496 uint cp_peodr;
497 uint cp_pedat;
498
499 /* Communications Processor Timing Register -
500 Contains RMII Timing for the FECs on MPC87x/88x only.
501 */
502 uint cp_cptr;
503
504 /* Serial Interface and Time Slot Assignment.
505 */
506 uint cp_simode;
507 u_char cp_sigmr;
508 u_char res15;
509 u_char cp_sistr;
510 u_char cp_sicmr;
511 u_char res16[4];
512 uint cp_sicr;
513 uint cp_sirp;
514 u_char res17[0xc];
515
516 /* 256 bytes of MPC823 video controller RAM array.
517 */
518 u_char cp_vcram[0x100];
519 u_char cp_siram[0x200];
520
521 /* The fast ethernet controller is not really part of the CPM,
522 * but it resides in the address space.
523 * The LCD color map is also here.
524 */
525 union fec_lcd fl_un;
526#define cp_fec fl_un.fl_un_fec
527#define lcd_cmap fl_un.fl_un_cmap
528 char res18[0xE00];
529
530 /* The DUET family has a second FEC here */
531 fec_t cp_fec2;
532#define cp_fec1 cp_fec /* consistency macro */
533
534 /* Dual Ported RAM follows.
535 * There are many different formats for this memory area
536 * depending upon the devices used and options chosen.
537 * Some processors don't have all of it populated.
538 */
539 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
540 u_char cp_dparam[0x400]; /* Parameter RAM */
541} cpm8xx_t;
542
543/* Internal memory map.
544*/
545typedef struct immap {
546 sysconf8xx_t im_siu_conf; /* SIU Configuration */
547 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
548 memctl8xx_t im_memctl; /* Memory Controller */
549 sit8xx_t im_sit; /* System integration timers */
550 car8xx_t im_clkrst; /* Clocks and reset */
551 sitk8xx_t im_sitk; /* Sys int timer keys */
552 cark8xx_t im_clkrstk; /* Clocks and reset keys */
553 vid823_t im_vid; /* Video (823 only) */
554 lcd823_t im_lcd; /* LCD (823 only) */
555 i2c8xx_t im_i2c; /* I2C control/status */
556 sdma8xx_t im_sdma; /* SDMA control/status */
557 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
558 iop8xx_t im_ioport; /* IO Port control/status */
559 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
560 cpm8xx_t im_cpm; /* Communication processor */
561} immap_t;
562
563#endif /* __IMMAP_8XX__ */
564#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
new file mode 100644
index 000000000000..5ab7d7fe198c
--- /dev/null
+++ b/arch/powerpc/include/asm/Kbuild
@@ -0,0 +1,37 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += auxvec.h
4header-y += ioctls.h
5header-y += sembuf.h
6header-y += siginfo.h
7header-y += stat.h
8header-y += errno.h
9header-y += ipcbuf.h
10header-y += msgbuf.h
11header-y += shmbuf.h
12header-y += socket.h
13header-y += termbits.h
14header-y += fcntl.h
15header-y += poll.h
16header-y += sockios.h
17header-y += ucontext.h
18header-y += ioctl.h
19header-y += linkage.h
20header-y += resource.h
21header-y += sigcontext.h
22header-y += statfs.h
23header-y += ps3fb.h
24
25unifdef-y += bootx.h
26unifdef-y += byteorder.h
27unifdef-y += cputable.h
28unifdef-y += elf.h
29unifdef-y += nvram.h
30unifdef-y += param.h
31unifdef-y += posix_types.h
32unifdef-y += seccomp.h
33unifdef-y += signal.h
34unifdef-y += spu_info.h
35unifdef-y += termios.h
36unifdef-y += types.h
37unifdef-y += unistd.h
diff --git a/arch/powerpc/include/asm/a.out.h b/arch/powerpc/include/asm/a.out.h
new file mode 100644
index 000000000000..89cead6b176e
--- /dev/null
+++ b/arch/powerpc/include/asm/a.out.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_A_OUT_H
2#define _ASM_POWERPC_A_OUT_H
3
4struct exec
5{
6 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
new file mode 100644
index 000000000000..98324c5a8286
--- /dev/null
+++ b/arch/powerpc/include/asm/abs_addr.h
@@ -0,0 +1,75 @@
1#ifndef _ASM_POWERPC_ABS_ADDR_H
2#define _ASM_POWERPC_ABS_ADDR_H
3#ifdef __KERNEL__
4
5
6/*
7 * c 2001 PPC 64 Team, IBM Corp
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/lmb.h>
16
17#include <asm/types.h>
18#include <asm/page.h>
19#include <asm/prom.h>
20#include <asm/firmware.h>
21
22struct mschunks_map {
23 unsigned long num_chunks;
24 unsigned long chunk_size;
25 unsigned long chunk_shift;
26 unsigned long chunk_mask;
27 u32 *mapping;
28};
29
30extern struct mschunks_map mschunks_map;
31
32/* Chunks are 256 KB */
33#define MSCHUNKS_CHUNK_SHIFT (18)
34#define MSCHUNKS_CHUNK_SIZE (1UL << MSCHUNKS_CHUNK_SHIFT)
35#define MSCHUNKS_OFFSET_MASK (MSCHUNKS_CHUNK_SIZE - 1)
36
37static inline unsigned long chunk_to_addr(unsigned long chunk)
38{
39 return chunk << MSCHUNKS_CHUNK_SHIFT;
40}
41
42static inline unsigned long addr_to_chunk(unsigned long addr)
43{
44 return addr >> MSCHUNKS_CHUNK_SHIFT;
45}
46
47static inline unsigned long phys_to_abs(unsigned long pa)
48{
49 unsigned long chunk;
50
51 /* This is a no-op on non-iSeries */
52 if (!firmware_has_feature(FW_FEATURE_ISERIES))
53 return pa;
54
55 chunk = addr_to_chunk(pa);
56
57 if (chunk < mschunks_map.num_chunks)
58 chunk = mschunks_map.mapping[chunk];
59
60 return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
61}
62
63/* Convenience macros */
64#define virt_to_abs(va) phys_to_abs(__pa(va))
65#define abs_to_virt(aa) __va(aa)
66
67/*
68 * Converts Virtual Address to Real Address for
69 * Legacy iSeries Hypervisor calls
70 */
71#define iseries_hv_addr(virtaddr) \
72 (0x8000000000000000 | virt_to_abs(virtaddr))
73
74#endif /* __KERNEL__ */
75#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/agp.h b/arch/powerpc/include/asm/agp.h
new file mode 100644
index 000000000000..86455c4c31ee
--- /dev/null
+++ b/arch/powerpc/include/asm/agp.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_POWERPC_AGP_H
2#define _ASM_POWERPC_AGP_H
3#ifdef __KERNEL__
4
5#include <asm/io.h>
6
7#define map_page_into_agp(page)
8#define unmap_page_from_agp(page)
9#define flush_agp_cache() mb()
10
11/* Convert a physical address to an address suitable for the GART. */
12#define phys_to_gart(x) (x)
13#define gart_to_phys(x) (x)
14
15/* GATT allocation. Returns/accepts GATT kernel virtual address. */
16#define alloc_gatt_pages(order) \
17 ((char *)__get_free_pages(GFP_KERNEL, (order)))
18#define free_gatt_pages(table, order) \
19 free_pages((unsigned long)(table), (order))
20
21#endif /* __KERNEL__ */
22#endif /* _ASM_POWERPC_AGP_H */
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
new file mode 100644
index 000000000000..8f0fe7971949
--- /dev/null
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -0,0 +1,69 @@
1#ifndef _ASM_POWERPC_ASM_COMPAT_H
2#define _ASM_POWERPC_ASM_COMPAT_H
3
4#include <asm/types.h>
5
6#ifdef __ASSEMBLY__
7# define stringify_in_c(...) __VA_ARGS__
8# define ASM_CONST(x) x
9#else
10/* This version of stringify will deal with commas... */
11# define __stringify_in_c(...) #__VA_ARGS__
12# define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " "
13# define __ASM_CONST(x) x##UL
14# define ASM_CONST(x) __ASM_CONST(x)
15#endif
16
17
18#ifdef __powerpc64__
19
20/* operations for longs and pointers */
21#define PPC_LL stringify_in_c(ld)
22#define PPC_STL stringify_in_c(std)
23#define PPC_LCMPI stringify_in_c(cmpdi)
24#define PPC_LONG stringify_in_c(.llong)
25#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
26#define PPC_TLNEI stringify_in_c(tdnei)
27#define PPC_LLARX stringify_in_c(ldarx)
28#define PPC_STLCX stringify_in_c(stdcx.)
29#define PPC_CNTLZL stringify_in_c(cntlzd)
30
31/* Move to CR, single-entry optimized version. Only available
32 * on POWER4 and later.
33 */
34#ifdef CONFIG_POWER4_ONLY
35#define PPC_MTOCRF stringify_in_c(mtocrf)
36#else
37#define PPC_MTOCRF stringify_in_c(mtcrf)
38#endif
39
40#else /* 32-bit */
41
42/* operations for longs and pointers */
43#define PPC_LL stringify_in_c(lwz)
44#define PPC_STL stringify_in_c(stw)
45#define PPC_LCMPI stringify_in_c(cmpwi)
46#define PPC_LONG stringify_in_c(.long)
47#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
48#define PPC_TLNEI stringify_in_c(twnei)
49#define PPC_LLARX stringify_in_c(lwarx)
50#define PPC_STLCX stringify_in_c(stwcx.)
51#define PPC_CNTLZL stringify_in_c(cntlzw)
52#define PPC_MTOCRF stringify_in_c(mtcrf)
53
54#endif
55
56#ifdef __KERNEL__
57#ifdef CONFIG_IBM405_ERR77
58/* Erratum #77 on the 405 means we need a sync or dcbt before every
59 * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
60 */
61#define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;)
62#define PPC405_ERR77_SYNC stringify_in_c(sync;)
63#else
64#define PPC405_ERR77(ra,rb)
65#define PPC405_ERR77_SYNC
66#endif
67#endif
68
69#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
new file mode 100644
index 000000000000..f3fc733758f5
--- /dev/null
+++ b/arch/powerpc/include/asm/atomic.h
@@ -0,0 +1,479 @@
1#ifndef _ASM_POWERPC_ATOMIC_H_
2#define _ASM_POWERPC_ATOMIC_H_
3
4/*
5 * PowerPC atomic operations
6 */
7
8typedef struct { int counter; } atomic_t;
9
10#ifdef __KERNEL__
11#include <linux/compiler.h>
12#include <asm/synch.h>
13#include <asm/asm-compat.h>
14#include <asm/system.h>
15
16#define ATOMIC_INIT(i) { (i) }
17
18static __inline__ int atomic_read(const atomic_t *v)
19{
20 int t;
21
22 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
23
24 return t;
25}
26
27static __inline__ void atomic_set(atomic_t *v, int i)
28{
29 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
30}
31
32static __inline__ void atomic_add(int a, atomic_t *v)
33{
34 int t;
35
36 __asm__ __volatile__(
37"1: lwarx %0,0,%3 # atomic_add\n\
38 add %0,%2,%0\n"
39 PPC405_ERR77(0,%3)
40" stwcx. %0,0,%3 \n\
41 bne- 1b"
42 : "=&r" (t), "+m" (v->counter)
43 : "r" (a), "r" (&v->counter)
44 : "cc");
45}
46
47static __inline__ int atomic_add_return(int a, atomic_t *v)
48{
49 int t;
50
51 __asm__ __volatile__(
52 LWSYNC_ON_SMP
53"1: lwarx %0,0,%2 # atomic_add_return\n\
54 add %0,%1,%0\n"
55 PPC405_ERR77(0,%2)
56" stwcx. %0,0,%2 \n\
57 bne- 1b"
58 ISYNC_ON_SMP
59 : "=&r" (t)
60 : "r" (a), "r" (&v->counter)
61 : "cc", "memory");
62
63 return t;
64}
65
66#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
67
68static __inline__ void atomic_sub(int a, atomic_t *v)
69{
70 int t;
71
72 __asm__ __volatile__(
73"1: lwarx %0,0,%3 # atomic_sub\n\
74 subf %0,%2,%0\n"
75 PPC405_ERR77(0,%3)
76" stwcx. %0,0,%3 \n\
77 bne- 1b"
78 : "=&r" (t), "+m" (v->counter)
79 : "r" (a), "r" (&v->counter)
80 : "cc");
81}
82
83static __inline__ int atomic_sub_return(int a, atomic_t *v)
84{
85 int t;
86
87 __asm__ __volatile__(
88 LWSYNC_ON_SMP
89"1: lwarx %0,0,%2 # atomic_sub_return\n\
90 subf %0,%1,%0\n"
91 PPC405_ERR77(0,%2)
92" stwcx. %0,0,%2 \n\
93 bne- 1b"
94 ISYNC_ON_SMP
95 : "=&r" (t)
96 : "r" (a), "r" (&v->counter)
97 : "cc", "memory");
98
99 return t;
100}
101
102static __inline__ void atomic_inc(atomic_t *v)
103{
104 int t;
105
106 __asm__ __volatile__(
107"1: lwarx %0,0,%2 # atomic_inc\n\
108 addic %0,%0,1\n"
109 PPC405_ERR77(0,%2)
110" stwcx. %0,0,%2 \n\
111 bne- 1b"
112 : "=&r" (t), "+m" (v->counter)
113 : "r" (&v->counter)
114 : "cc");
115}
116
117static __inline__ int atomic_inc_return(atomic_t *v)
118{
119 int t;
120
121 __asm__ __volatile__(
122 LWSYNC_ON_SMP
123"1: lwarx %0,0,%1 # atomic_inc_return\n\
124 addic %0,%0,1\n"
125 PPC405_ERR77(0,%1)
126" stwcx. %0,0,%1 \n\
127 bne- 1b"
128 ISYNC_ON_SMP
129 : "=&r" (t)
130 : "r" (&v->counter)
131 : "cc", "memory");
132
133 return t;
134}
135
136/*
137 * atomic_inc_and_test - increment and test
138 * @v: pointer of type atomic_t
139 *
140 * Atomically increments @v by 1
141 * and returns true if the result is zero, or false for all
142 * other cases.
143 */
144#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
145
146static __inline__ void atomic_dec(atomic_t *v)
147{
148 int t;
149
150 __asm__ __volatile__(
151"1: lwarx %0,0,%2 # atomic_dec\n\
152 addic %0,%0,-1\n"
153 PPC405_ERR77(0,%2)\
154" stwcx. %0,0,%2\n\
155 bne- 1b"
156 : "=&r" (t), "+m" (v->counter)
157 : "r" (&v->counter)
158 : "cc");
159}
160
161static __inline__ int atomic_dec_return(atomic_t *v)
162{
163 int t;
164
165 __asm__ __volatile__(
166 LWSYNC_ON_SMP
167"1: lwarx %0,0,%1 # atomic_dec_return\n\
168 addic %0,%0,-1\n"
169 PPC405_ERR77(0,%1)
170" stwcx. %0,0,%1\n\
171 bne- 1b"
172 ISYNC_ON_SMP
173 : "=&r" (t)
174 : "r" (&v->counter)
175 : "cc", "memory");
176
177 return t;
178}
179
180#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
181#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
182
183/**
184 * atomic_add_unless - add unless the number is a given value
185 * @v: pointer of type atomic_t
186 * @a: the amount to add to v...
187 * @u: ...unless v is equal to u.
188 *
189 * Atomically adds @a to @v, so long as it was not @u.
190 * Returns non-zero if @v was not @u, and zero otherwise.
191 */
192static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
193{
194 int t;
195
196 __asm__ __volatile__ (
197 LWSYNC_ON_SMP
198"1: lwarx %0,0,%1 # atomic_add_unless\n\
199 cmpw 0,%0,%3 \n\
200 beq- 2f \n\
201 add %0,%2,%0 \n"
202 PPC405_ERR77(0,%2)
203" stwcx. %0,0,%1 \n\
204 bne- 1b \n"
205 ISYNC_ON_SMP
206" subf %0,%2,%0 \n\
2072:"
208 : "=&r" (t)
209 : "r" (&v->counter), "r" (a), "r" (u)
210 : "cc", "memory");
211
212 return t != u;
213}
214
215#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
216
217#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
218#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
219
220/*
221 * Atomically test *v and decrement if it is greater than 0.
222 * The function returns the old value of *v minus 1, even if
223 * the atomic variable, v, was not decremented.
224 */
225static __inline__ int atomic_dec_if_positive(atomic_t *v)
226{
227 int t;
228
229 __asm__ __volatile__(
230 LWSYNC_ON_SMP
231"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
232 cmpwi %0,1\n\
233 addi %0,%0,-1\n\
234 blt- 2f\n"
235 PPC405_ERR77(0,%1)
236" stwcx. %0,0,%1\n\
237 bne- 1b"
238 ISYNC_ON_SMP
239 "\n\
2402:" : "=&b" (t)
241 : "r" (&v->counter)
242 : "cc", "memory");
243
244 return t;
245}
246
247#define smp_mb__before_atomic_dec() smp_mb()
248#define smp_mb__after_atomic_dec() smp_mb()
249#define smp_mb__before_atomic_inc() smp_mb()
250#define smp_mb__after_atomic_inc() smp_mb()
251
252#ifdef __powerpc64__
253
254typedef struct { long counter; } atomic64_t;
255
256#define ATOMIC64_INIT(i) { (i) }
257
258static __inline__ long atomic64_read(const atomic64_t *v)
259{
260 long t;
261
262 __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
263
264 return t;
265}
266
267static __inline__ void atomic64_set(atomic64_t *v, long i)
268{
269 __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
270}
271
272static __inline__ void atomic64_add(long a, atomic64_t *v)
273{
274 long t;
275
276 __asm__ __volatile__(
277"1: ldarx %0,0,%3 # atomic64_add\n\
278 add %0,%2,%0\n\
279 stdcx. %0,0,%3 \n\
280 bne- 1b"
281 : "=&r" (t), "+m" (v->counter)
282 : "r" (a), "r" (&v->counter)
283 : "cc");
284}
285
286static __inline__ long atomic64_add_return(long a, atomic64_t *v)
287{
288 long t;
289
290 __asm__ __volatile__(
291 LWSYNC_ON_SMP
292"1: ldarx %0,0,%2 # atomic64_add_return\n\
293 add %0,%1,%0\n\
294 stdcx. %0,0,%2 \n\
295 bne- 1b"
296 ISYNC_ON_SMP
297 : "=&r" (t)
298 : "r" (a), "r" (&v->counter)
299 : "cc", "memory");
300
301 return t;
302}
303
304#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
305
306static __inline__ void atomic64_sub(long a, atomic64_t *v)
307{
308 long t;
309
310 __asm__ __volatile__(
311"1: ldarx %0,0,%3 # atomic64_sub\n\
312 subf %0,%2,%0\n\
313 stdcx. %0,0,%3 \n\
314 bne- 1b"
315 : "=&r" (t), "+m" (v->counter)
316 : "r" (a), "r" (&v->counter)
317 : "cc");
318}
319
320static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
321{
322 long t;
323
324 __asm__ __volatile__(
325 LWSYNC_ON_SMP
326"1: ldarx %0,0,%2 # atomic64_sub_return\n\
327 subf %0,%1,%0\n\
328 stdcx. %0,0,%2 \n\
329 bne- 1b"
330 ISYNC_ON_SMP
331 : "=&r" (t)
332 : "r" (a), "r" (&v->counter)
333 : "cc", "memory");
334
335 return t;
336}
337
338static __inline__ void atomic64_inc(atomic64_t *v)
339{
340 long t;
341
342 __asm__ __volatile__(
343"1: ldarx %0,0,%2 # atomic64_inc\n\
344 addic %0,%0,1\n\
345 stdcx. %0,0,%2 \n\
346 bne- 1b"
347 : "=&r" (t), "+m" (v->counter)
348 : "r" (&v->counter)
349 : "cc");
350}
351
352static __inline__ long atomic64_inc_return(atomic64_t *v)
353{
354 long t;
355
356 __asm__ __volatile__(
357 LWSYNC_ON_SMP
358"1: ldarx %0,0,%1 # atomic64_inc_return\n\
359 addic %0,%0,1\n\
360 stdcx. %0,0,%1 \n\
361 bne- 1b"
362 ISYNC_ON_SMP
363 : "=&r" (t)
364 : "r" (&v->counter)
365 : "cc", "memory");
366
367 return t;
368}
369
370/*
371 * atomic64_inc_and_test - increment and test
372 * @v: pointer of type atomic64_t
373 *
374 * Atomically increments @v by 1
375 * and returns true if the result is zero, or false for all
376 * other cases.
377 */
378#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
379
380static __inline__ void atomic64_dec(atomic64_t *v)
381{
382 long t;
383
384 __asm__ __volatile__(
385"1: ldarx %0,0,%2 # atomic64_dec\n\
386 addic %0,%0,-1\n\
387 stdcx. %0,0,%2\n\
388 bne- 1b"
389 : "=&r" (t), "+m" (v->counter)
390 : "r" (&v->counter)
391 : "cc");
392}
393
394static __inline__ long atomic64_dec_return(atomic64_t *v)
395{
396 long t;
397
398 __asm__ __volatile__(
399 LWSYNC_ON_SMP
400"1: ldarx %0,0,%1 # atomic64_dec_return\n\
401 addic %0,%0,-1\n\
402 stdcx. %0,0,%1\n\
403 bne- 1b"
404 ISYNC_ON_SMP
405 : "=&r" (t)
406 : "r" (&v->counter)
407 : "cc", "memory");
408
409 return t;
410}
411
412#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
413#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
414
415/*
416 * Atomically test *v and decrement if it is greater than 0.
417 * The function returns the old value of *v minus 1.
418 */
419static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
420{
421 long t;
422
423 __asm__ __volatile__(
424 LWSYNC_ON_SMP
425"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
426 addic. %0,%0,-1\n\
427 blt- 2f\n\
428 stdcx. %0,0,%1\n\
429 bne- 1b"
430 ISYNC_ON_SMP
431 "\n\
4322:" : "=&r" (t)
433 : "r" (&v->counter)
434 : "cc", "memory");
435
436 return t;
437}
438
439#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
440#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
441
442/**
443 * atomic64_add_unless - add unless the number is a given value
444 * @v: pointer of type atomic64_t
445 * @a: the amount to add to v...
446 * @u: ...unless v is equal to u.
447 *
448 * Atomically adds @a to @v, so long as it was not @u.
449 * Returns non-zero if @v was not @u, and zero otherwise.
450 */
451static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
452{
453 long t;
454
455 __asm__ __volatile__ (
456 LWSYNC_ON_SMP
457"1: ldarx %0,0,%1 # atomic_add_unless\n\
458 cmpd 0,%0,%3 \n\
459 beq- 2f \n\
460 add %0,%2,%0 \n"
461" stdcx. %0,0,%1 \n\
462 bne- 1b \n"
463 ISYNC_ON_SMP
464" subf %0,%2,%0 \n\
4652:"
466 : "=&r" (t)
467 : "r" (&v->counter), "r" (a), "r" (u)
468 : "cc", "memory");
469
470 return t != u;
471}
472
473#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
474
475#endif /* __powerpc64__ */
476
477#include <asm-generic/atomic.h>
478#endif /* __KERNEL__ */
479#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/arch/powerpc/include/asm/auxvec.h b/arch/powerpc/include/asm/auxvec.h
new file mode 100644
index 000000000000..19a099b62cd6
--- /dev/null
+++ b/arch/powerpc/include/asm/auxvec.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_POWERPC_AUXVEC_H
2#define _ASM_POWERPC_AUXVEC_H
3
4/*
5 * We need to put in some extra aux table entries to tell glibc what
6 * the cache block size is, so it can use the dcbz instruction safely.
7 */
8#define AT_DCACHEBSIZE 19
9#define AT_ICACHEBSIZE 20
10#define AT_UCACHEBSIZE 21
11/* A special ignored type value for PPC, for glibc compatibility. */
12#define AT_IGNOREPPC 22
13
14/* The vDSO location. We have to use the same value as x86 for glibc's
15 * sake :-)
16 */
17#define AT_SYSINFO_EHDR 33
18
19#endif
diff --git a/arch/powerpc/include/asm/backlight.h b/arch/powerpc/include/asm/backlight.h
new file mode 100644
index 000000000000..8cf5c37c3817
--- /dev/null
+++ b/arch/powerpc/include/asm/backlight.h
@@ -0,0 +1,41 @@
1/*
2 * Routines for handling backlight control on PowerBooks
3 *
4 * For now, implementation resides in
5 * arch/powerpc/platforms/powermac/backlight.c
6 *
7 */
8#ifndef __ASM_POWERPC_BACKLIGHT_H
9#define __ASM_POWERPC_BACKLIGHT_H
10#ifdef __KERNEL__
11
12#include <linux/fb.h>
13#include <linux/mutex.h>
14
15/* For locking instructions, see the implementation file */
16extern struct backlight_device *pmac_backlight;
17extern struct mutex pmac_backlight_mutex;
18
19extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
20
21extern int pmac_has_backlight_type(const char *type);
22
23extern void pmac_backlight_key(int direction);
24static inline void pmac_backlight_key_up(void)
25{
26 pmac_backlight_key(0);
27}
28static inline void pmac_backlight_key_down(void)
29{
30 pmac_backlight_key(1);
31}
32
33extern void pmac_backlight_set_legacy_brightness_pmu(int brightness);
34extern int pmac_backlight_set_legacy_brightness(int brightness);
35extern int pmac_backlight_get_legacy_brightness(void);
36
37extern void pmac_backlight_enable(void);
38extern void pmac_backlight_disable(void);
39
40#endif /* __KERNEL__ */
41#endif
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
new file mode 100644
index 000000000000..897eade3afbe
--- /dev/null
+++ b/arch/powerpc/include/asm/bitops.h
@@ -0,0 +1,410 @@
1/*
2 * PowerPC atomic bit operations.
3 *
4 * Merged version by David Gibson <david@gibson.dropbear.id.au>.
5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
7 * originally took it from the ppc32 code.
8 *
9 * Within a word, bits are numbered LSB first. Lot's of places make
10 * this assumption by directly testing bits with (val & (1<<nr)).
11 * This can cause confusion for large (> 1 word) bitmaps on a
12 * big-endian system because, unlike little endian, the number of each
13 * bit depends on the word size.
14 *
15 * The bitop functions are defined to work on unsigned longs, so for a
16 * ppc64 system the bits end up numbered:
17 * |63..............0|127............64|191...........128|255...........196|
18 * and on ppc32:
19 * |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
20 *
21 * There are a few little-endian macros used mostly for filesystem
22 * bitmaps, these work on similar bit arrays layouts, but
23 * byte-oriented:
24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
25 *
26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
27 * number field needs to be reversed compared to the big-endian bit
28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License
32 * as published by the Free Software Foundation; either version
33 * 2 of the License, or (at your option) any later version.
34 */
35
36#ifndef _ASM_POWERPC_BITOPS_H
37#define _ASM_POWERPC_BITOPS_H
38
39#ifdef __KERNEL__
40
41#ifndef _LINUX_BITOPS_H
42#error only <linux/bitops.h> can be included directly
43#endif
44
45#include <linux/compiler.h>
46#include <asm/asm-compat.h>
47#include <asm/synch.h>
48
49/*
50 * clear_bit doesn't imply a memory barrier
51 */
52#define smp_mb__before_clear_bit() smp_mb()
53#define smp_mb__after_clear_bit() smp_mb()
54
55#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
56#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
57#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
58
59static __inline__ void set_bit(int nr, volatile unsigned long *addr)
60{
61 unsigned long old;
62 unsigned long mask = BITOP_MASK(nr);
63 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
64
65 __asm__ __volatile__(
66"1:" PPC_LLARX "%0,0,%3 # set_bit\n"
67 "or %0,%0,%2\n"
68 PPC405_ERR77(0,%3)
69 PPC_STLCX "%0,0,%3\n"
70 "bne- 1b"
71 : "=&r" (old), "+m" (*p)
72 : "r" (mask), "r" (p)
73 : "cc" );
74}
75
76static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
77{
78 unsigned long old;
79 unsigned long mask = BITOP_MASK(nr);
80 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
81
82 __asm__ __volatile__(
83"1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
84 "andc %0,%0,%2\n"
85 PPC405_ERR77(0,%3)
86 PPC_STLCX "%0,0,%3\n"
87 "bne- 1b"
88 : "=&r" (old), "+m" (*p)
89 : "r" (mask), "r" (p)
90 : "cc" );
91}
92
93static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
94{
95 unsigned long old;
96 unsigned long mask = BITOP_MASK(nr);
97 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
98
99 __asm__ __volatile__(
100 LWSYNC_ON_SMP
101"1:" PPC_LLARX "%0,0,%3 # clear_bit_unlock\n"
102 "andc %0,%0,%2\n"
103 PPC405_ERR77(0,%3)
104 PPC_STLCX "%0,0,%3\n"
105 "bne- 1b"
106 : "=&r" (old), "+m" (*p)
107 : "r" (mask), "r" (p)
108 : "cc", "memory");
109}
110
111static __inline__ void change_bit(int nr, volatile unsigned long *addr)
112{
113 unsigned long old;
114 unsigned long mask = BITOP_MASK(nr);
115 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
116
117 __asm__ __volatile__(
118"1:" PPC_LLARX "%0,0,%3 # change_bit\n"
119 "xor %0,%0,%2\n"
120 PPC405_ERR77(0,%3)
121 PPC_STLCX "%0,0,%3\n"
122 "bne- 1b"
123 : "=&r" (old), "+m" (*p)
124 : "r" (mask), "r" (p)
125 : "cc" );
126}
127
128static __inline__ int test_and_set_bit(unsigned long nr,
129 volatile unsigned long *addr)
130{
131 unsigned long old, t;
132 unsigned long mask = BITOP_MASK(nr);
133 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
134
135 __asm__ __volatile__(
136 LWSYNC_ON_SMP
137"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
138 "or %1,%0,%2 \n"
139 PPC405_ERR77(0,%3)
140 PPC_STLCX "%1,0,%3 \n"
141 "bne- 1b"
142 ISYNC_ON_SMP
143 : "=&r" (old), "=&r" (t)
144 : "r" (mask), "r" (p)
145 : "cc", "memory");
146
147 return (old & mask) != 0;
148}
149
150static __inline__ int test_and_set_bit_lock(unsigned long nr,
151 volatile unsigned long *addr)
152{
153 unsigned long old, t;
154 unsigned long mask = BITOP_MASK(nr);
155 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
156
157 __asm__ __volatile__(
158"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit_lock\n"
159 "or %1,%0,%2 \n"
160 PPC405_ERR77(0,%3)
161 PPC_STLCX "%1,0,%3 \n"
162 "bne- 1b"
163 ISYNC_ON_SMP
164 : "=&r" (old), "=&r" (t)
165 : "r" (mask), "r" (p)
166 : "cc", "memory");
167
168 return (old & mask) != 0;
169}
170
171static __inline__ int test_and_clear_bit(unsigned long nr,
172 volatile unsigned long *addr)
173{
174 unsigned long old, t;
175 unsigned long mask = BITOP_MASK(nr);
176 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
177
178 __asm__ __volatile__(
179 LWSYNC_ON_SMP
180"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
181 "andc %1,%0,%2 \n"
182 PPC405_ERR77(0,%3)
183 PPC_STLCX "%1,0,%3 \n"
184 "bne- 1b"
185 ISYNC_ON_SMP
186 : "=&r" (old), "=&r" (t)
187 : "r" (mask), "r" (p)
188 : "cc", "memory");
189
190 return (old & mask) != 0;
191}
192
193static __inline__ int test_and_change_bit(unsigned long nr,
194 volatile unsigned long *addr)
195{
196 unsigned long old, t;
197 unsigned long mask = BITOP_MASK(nr);
198 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
199
200 __asm__ __volatile__(
201 LWSYNC_ON_SMP
202"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
203 "xor %1,%0,%2 \n"
204 PPC405_ERR77(0,%3)
205 PPC_STLCX "%1,0,%3 \n"
206 "bne- 1b"
207 ISYNC_ON_SMP
208 : "=&r" (old), "=&r" (t)
209 : "r" (mask), "r" (p)
210 : "cc", "memory");
211
212 return (old & mask) != 0;
213}
214
215static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
216{
217 unsigned long old;
218
219 __asm__ __volatile__(
220"1:" PPC_LLARX "%0,0,%3 # set_bits\n"
221 "or %0,%0,%2\n"
222 PPC_STLCX "%0,0,%3\n"
223 "bne- 1b"
224 : "=&r" (old), "+m" (*addr)
225 : "r" (mask), "r" (addr)
226 : "cc");
227}
228
229#include <asm-generic/bitops/non-atomic.h>
230
231static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
232{
233 __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory");
234 __clear_bit(nr, addr);
235}
236
237/*
238 * Return the zero-based bit position (LE, not IBM bit numbering) of
239 * the most significant 1-bit in a double word.
240 */
241static __inline__ __attribute__((const))
242int __ilog2(unsigned long x)
243{
244 int lz;
245
246 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
247 return BITS_PER_LONG - 1 - lz;
248}
249
250static inline __attribute__((const))
251int __ilog2_u32(u32 n)
252{
253 int bit;
254 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
255 return 31 - bit;
256}
257
258#ifdef __powerpc64__
259static inline __attribute__((const))
260int __ilog2_u64(u64 n)
261{
262 int bit;
263 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
264 return 63 - bit;
265}
266#endif
267
268/*
269 * Determines the bit position of the least significant 0 bit in the
270 * specified double word. The returned bit position will be
271 * zero-based, starting from the right side (63/31 - 0).
272 */
273static __inline__ unsigned long ffz(unsigned long x)
274{
275 /* no zero exists anywhere in the 8 byte area. */
276 if ((x = ~x) == 0)
277 return BITS_PER_LONG;
278
279 /*
280 * Calculate the bit position of the least signficant '1' bit in x
281 * (since x has been changed this will actually be the least signficant
282 * '0' bit in * the original x). Note: (x & -x) gives us a mask that
283 * is the least significant * (RIGHT-most) 1-bit of the value in x.
284 */
285 return __ilog2(x & -x);
286}
287
288static __inline__ int __ffs(unsigned long x)
289{
290 return __ilog2(x & -x);
291}
292
293/*
294 * ffs: find first bit set. This is defined the same way as
295 * the libc and compiler builtin ffs routines, therefore
296 * differs in spirit from the above ffz (man ffs).
297 */
298static __inline__ int ffs(int x)
299{
300 unsigned long i = (unsigned long)x;
301 return __ilog2(i & -i) + 1;
302}
303
304/*
305 * fls: find last (most-significant) bit set.
306 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
307 */
308static __inline__ int fls(unsigned int x)
309{
310 int lz;
311
312 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
313 return 32 - lz;
314}
315
316static __inline__ unsigned long __fls(unsigned long x)
317{
318 return __ilog2(x);
319}
320
321/*
322 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
323 * instruction; for 32-bit we use the generic version, which does two
324 * 32-bit fls calls.
325 */
326#ifdef __powerpc64__
327static __inline__ int fls64(__u64 x)
328{
329 int lz;
330
331 asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
332 return 64 - lz;
333}
334#else
335#include <asm-generic/bitops/fls64.h>
336#endif /* __powerpc64__ */
337
338#include <asm-generic/bitops/hweight.h>
339#include <asm-generic/bitops/find.h>
340
341/* Little-endian versions */
342
343static __inline__ int test_le_bit(unsigned long nr,
344 __const__ unsigned long *addr)
345{
346 __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
347 return (tmp[nr >> 3] >> (nr & 7)) & 1;
348}
349
350#define __set_le_bit(nr, addr) \
351 __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
352#define __clear_le_bit(nr, addr) \
353 __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
354
355#define test_and_set_le_bit(nr, addr) \
356 test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
357#define test_and_clear_le_bit(nr, addr) \
358 test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
359
360#define __test_and_set_le_bit(nr, addr) \
361 __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
362#define __test_and_clear_le_bit(nr, addr) \
363 __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
364
365#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
366unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
367 unsigned long size, unsigned long offset);
368
369unsigned long generic_find_next_le_bit(const unsigned long *addr,
370 unsigned long size, unsigned long offset);
371/* Bitmap functions for the ext2 filesystem */
372
373#define ext2_set_bit(nr,addr) \
374 __test_and_set_le_bit((nr), (unsigned long*)addr)
375#define ext2_clear_bit(nr, addr) \
376 __test_and_clear_le_bit((nr), (unsigned long*)addr)
377
378#define ext2_set_bit_atomic(lock, nr, addr) \
379 test_and_set_le_bit((nr), (unsigned long*)addr)
380#define ext2_clear_bit_atomic(lock, nr, addr) \
381 test_and_clear_le_bit((nr), (unsigned long*)addr)
382
383#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
384
385#define ext2_find_first_zero_bit(addr, size) \
386 find_first_zero_le_bit((unsigned long*)addr, size)
387#define ext2_find_next_zero_bit(addr, size, off) \
388 generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
389
390#define ext2_find_next_bit(addr, size, off) \
391 generic_find_next_le_bit((unsigned long *)addr, size, off)
392/* Bitmap functions for the minix filesystem. */
393
394#define minix_test_and_set_bit(nr,addr) \
395 __test_and_set_le_bit(nr, (unsigned long *)addr)
396#define minix_set_bit(nr,addr) \
397 __set_le_bit(nr, (unsigned long *)addr)
398#define minix_test_and_clear_bit(nr,addr) \
399 __test_and_clear_le_bit(nr, (unsigned long *)addr)
400#define minix_test_bit(nr,addr) \
401 test_le_bit(nr, (unsigned long *)addr)
402
403#define minix_find_first_zero_bit(addr,size) \
404 find_first_zero_le_bit((unsigned long *)addr, size)
405
406#include <asm-generic/bitops/sched.h>
407
408#endif /* __KERNEL__ */
409
410#endif /* _ASM_POWERPC_BITOPS_H */
diff --git a/arch/powerpc/include/asm/bootx.h b/arch/powerpc/include/asm/bootx.h
new file mode 100644
index 000000000000..57b82e3f89ce
--- /dev/null
+++ b/arch/powerpc/include/asm/bootx.h
@@ -0,0 +1,171 @@
1/*
2 * This file describes the structure passed from the BootX application
3 * (for MacOS) when it is used to boot Linux.
4 *
5 * Written by Benjamin Herrenschmidt.
6 */
7
8
9#ifndef __ASM_BOOTX_H__
10#define __ASM_BOOTX_H__
11
12#include <asm/types.h>
13
14#ifdef macintosh
15#include <Types.h>
16#include "linux_type_defs.h"
17#endif
18
19#ifdef macintosh
20/* All this requires PowerPC alignment */
21#pragma options align=power
22#endif
23
24/* On kernel entry:
25 *
26 * r3 = 0x426f6f58 ('BooX')
27 * r4 = pointer to boot_infos
28 * r5 = NULL
29 *
30 * Data and instruction translation disabled, interrupts
31 * disabled, kernel loaded at physical 0x00000000 on PCI
32 * machines (will be different on NuBus).
33 */
34
35#define BOOT_INFO_VERSION 5
36#define BOOT_INFO_COMPATIBLE_VERSION 1
37
38/* Bit in the architecture flag mask. More to be defined in
39 future versions. Note that either BOOT_ARCH_PCI or
40 BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
41 set additionally when BOOT_ARCH_NUBUS is set.
42 */
43#define BOOT_ARCH_PCI 0x00000001UL
44#define BOOT_ARCH_NUBUS 0x00000002UL
45#define BOOT_ARCH_NUBUS_PDM 0x00000010UL
46#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL
47#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL
48
49/* Maximum number of ranges in phys memory map */
50#define MAX_MEM_MAP_SIZE 26
51
52/* This is the format of an element in the physical memory map. Note that
53 the map is optional and current BootX will only build it for pre-PCI
54 machines */
55typedef struct boot_info_map_entry
56{
57 __u32 physAddr; /* Physical starting address */
58 __u32 size; /* Size in bytes */
59} boot_info_map_entry_t;
60
61
62/* Here are the boot informations that are passed to the bootstrap
63 * Note that the kernel arguments and the device tree are appended
64 * at the end of this structure. */
65typedef struct boot_infos
66{
67 /* Version of this structure */
68 __u32 version;
69 /* backward compatible down to version: */
70 __u32 compatible_version;
71
72 /* NEW (vers. 2) this holds the current _logical_ base addr of
73 the frame buffer (for use by early boot message) */
74 __u8* logicalDisplayBase;
75
76 /* NEW (vers. 4) Apple's machine identification */
77 __u32 machineID;
78
79 /* NEW (vers. 4) Detected hw architecture */
80 __u32 architecture;
81
82 /* The device tree (internal addresses relative to the beginning of the tree,
83 * device tree offset relative to the beginning of this structure).
84 * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
85 * field is 0.
86 */
87 __u32 deviceTreeOffset; /* Device tree offset */
88 __u32 deviceTreeSize; /* Size of the device tree */
89
90 /* Some infos about the current MacOS display */
91 __u32 dispDeviceRect[4]; /* left,top,right,bottom */
92 __u32 dispDeviceDepth; /* (8, 16 or 32) */
93 __u8* dispDeviceBase; /* base address (physical) */
94 __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */
95 __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */
96 /* Optional offset in the registry to the current
97 * MacOS display. (Can be 0 when not detected) */
98 __u32 dispDeviceRegEntryOffset;
99
100 /* Optional pointer to boot ramdisk (offset from this structure) */
101 __u32 ramDisk;
102 __u32 ramDiskSize; /* size of ramdisk image */
103
104 /* Kernel command line arguments (offset from this structure) */
105 __u32 kernelParamsOffset;
106
107 /* ALL BELOW NEW (vers. 4) */
108
109 /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
110 (non-PCI) only. On PCI, memory is contiguous and it's size is in the
111 device-tree. */
112 boot_info_map_entry_t
113 physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
114 __u32 physMemoryMapSize; /* How many entries in map */
115
116
117 /* The framebuffer size (optional, currently 0) */
118 __u32 frameBufferSize; /* Represents a max size, can be 0. */
119
120 /* NEW (vers. 5) */
121
122 /* Total params size (args + colormap + device tree + ramdisk) */
123 __u32 totalParamsSize;
124
125} boot_infos_t;
126
127#ifdef __KERNEL__
128/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index
129 * is represented by 3 short words containing a 16 bits (unsigned) color
130 * component. Later versions may contain the gamma table for direct-color
131 * devices here.
132 */
133#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL)
134
135/* BootX passes the device-tree using a format that comes from earlier
136 * ppc32 kernels. This used to match what is in prom.h, but not anymore
137 * so we now define it here
138 */
139struct bootx_dt_prop {
140 u32 name;
141 int length;
142 u32 value;
143 u32 next;
144};
145
146struct bootx_dt_node {
147 u32 unused0;
148 u32 unused1;
149 u32 phandle; /* not really available */
150 u32 unused2;
151 u32 unused3;
152 u32 unused4;
153 u32 unused5;
154 u32 full_name;
155 u32 properties;
156 u32 parent;
157 u32 child;
158 u32 sibling;
159 u32 next;
160 u32 allnext;
161};
162
163extern void bootx_init(unsigned long r4, unsigned long phys);
164
165#endif /* __KERNEL__ */
166
167#ifdef macintosh
168#pragma options align=reset
169#endif
170
171#endif
diff --git a/arch/powerpc/include/asm/btext.h b/arch/powerpc/include/asm/btext.h
new file mode 100644
index 000000000000..906f46e31006
--- /dev/null
+++ b/arch/powerpc/include/asm/btext.h
@@ -0,0 +1,28 @@
1/*
2 * Definitions for using the procedures in btext.c.
3 *
4 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 */
6#ifndef __PPC_BTEXT_H
7#define __PPC_BTEXT_H
8#ifdef __KERNEL__
9
10extern int btext_find_display(int allow_nonstdout);
11extern void btext_update_display(unsigned long phys, int width, int height,
12 int depth, int pitch);
13extern void btext_setup_display(int width, int height, int depth, int pitch,
14 unsigned long address);
15extern void btext_prepare_BAT(void);
16extern void btext_unmap(void);
17
18extern void btext_drawchar(char c);
19extern void btext_drawstring(const char *str);
20extern void btext_drawhex(unsigned long v);
21extern void btext_drawtext(const char *c, unsigned int len);
22
23extern void btext_clearscreen(void);
24extern void btext_flushscreen(void);
25extern void btext_flushline(void);
26
27#endif /* __KERNEL__ */
28#endif /* __PPC_BTEXT_H */
diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h
new file mode 100644
index 000000000000..e55d1f66b86f
--- /dev/null
+++ b/arch/powerpc/include/asm/bug.h
@@ -0,0 +1,121 @@
1#ifndef _ASM_POWERPC_BUG_H
2#define _ASM_POWERPC_BUG_H
3#ifdef __KERNEL__
4
5#include <asm/asm-compat.h>
6/*
7 * Define an illegal instr to trap on the bug.
8 * We don't use 0 because that marks the end of a function
9 * in the ELF ABI. That's "Boo Boo" in case you wonder...
10 */
11#define BUG_OPCODE .long 0x00b00b00 /* For asm */
12#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
13
14#ifdef CONFIG_BUG
15
16#ifdef __ASSEMBLY__
17#ifdef CONFIG_DEBUG_BUGVERBOSE
18.macro EMIT_BUG_ENTRY addr,file,line,flags
19 .section __bug_table,"a"
205001: PPC_LONG \addr, 5002f
21 .short \line, \flags
22 .org 5001b+BUG_ENTRY_SIZE
23 .previous
24 .section .rodata,"a"
255002: .asciz "\file"
26 .previous
27.endm
28#else
29 .macro EMIT_BUG_ENTRY addr,file,line,flags
30 .section __bug_table,"a"
315001: PPC_LONG \addr
32 .short \flags
33 .org 5001b+BUG_ENTRY_SIZE
34 .previous
35.endm
36#endif /* verbose */
37
38#else /* !__ASSEMBLY__ */
39/* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and
40 sizeof(struct bug_entry), respectively */
41#ifdef CONFIG_DEBUG_BUGVERBOSE
42#define _EMIT_BUG_ENTRY \
43 ".section __bug_table,\"a\"\n" \
44 "2:\t" PPC_LONG "1b, %0\n" \
45 "\t.short %1, %2\n" \
46 ".org 2b+%3\n" \
47 ".previous\n"
48#else
49#define _EMIT_BUG_ENTRY \
50 ".section __bug_table,\"a\"\n" \
51 "2:\t" PPC_LONG "1b\n" \
52 "\t.short %2\n" \
53 ".org 2b+%3\n" \
54 ".previous\n"
55#endif
56
57/*
58 * BUG_ON() and WARN_ON() do their best to cooperate with compile-time
59 * optimisations. However depending on the complexity of the condition
60 * some compiler versions may not produce optimal results.
61 */
62
63#define BUG() do { \
64 __asm__ __volatile__( \
65 "1: twi 31,0,0\n" \
66 _EMIT_BUG_ENTRY \
67 : : "i" (__FILE__), "i" (__LINE__), \
68 "i" (0), "i" (sizeof(struct bug_entry))); \
69 for(;;) ; \
70} while (0)
71
72#define BUG_ON(x) do { \
73 if (__builtin_constant_p(x)) { \
74 if (x) \
75 BUG(); \
76 } else { \
77 __asm__ __volatile__( \
78 "1: "PPC_TLNEI" %4,0\n" \
79 _EMIT_BUG_ENTRY \
80 : : "i" (__FILE__), "i" (__LINE__), "i" (0), \
81 "i" (sizeof(struct bug_entry)), \
82 "r" ((__force long)(x))); \
83 } \
84} while (0)
85
86#define __WARN() do { \
87 __asm__ __volatile__( \
88 "1: twi 31,0,0\n" \
89 _EMIT_BUG_ENTRY \
90 : : "i" (__FILE__), "i" (__LINE__), \
91 "i" (BUGFLAG_WARNING), \
92 "i" (sizeof(struct bug_entry))); \
93} while (0)
94
95#define WARN_ON(x) ({ \
96 int __ret_warn_on = !!(x); \
97 if (__builtin_constant_p(__ret_warn_on)) { \
98 if (__ret_warn_on) \
99 __WARN(); \
100 } else { \
101 __asm__ __volatile__( \
102 "1: "PPC_TLNEI" %4,0\n" \
103 _EMIT_BUG_ENTRY \
104 : : "i" (__FILE__), "i" (__LINE__), \
105 "i" (BUGFLAG_WARNING), \
106 "i" (sizeof(struct bug_entry)), \
107 "r" (__ret_warn_on)); \
108 } \
109 unlikely(__ret_warn_on); \
110})
111
112#define HAVE_ARCH_BUG
113#define HAVE_ARCH_BUG_ON
114#define HAVE_ARCH_WARN_ON
115#endif /* __ASSEMBLY __ */
116#endif /* CONFIG_BUG */
117
118#include <asm-generic/bug.h>
119
120#endif /* __KERNEL__ */
121#endif /* _ASM_POWERPC_BUG_H */
diff --git a/arch/powerpc/include/asm/bugs.h b/arch/powerpc/include/asm/bugs.h
new file mode 100644
index 000000000000..42fdb73e3068
--- /dev/null
+++ b/arch/powerpc/include/asm/bugs.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_POWERPC_BUGS_H
2#define _ASM_POWERPC_BUGS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * This file is included by 'init/main.c' to check for
13 * architecture-dependent bugs.
14 */
15
16static inline void check_bugs(void) { }
17
18#endif /* _ASM_POWERPC_BUGS_H */
diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h
new file mode 100644
index 000000000000..b37752214a16
--- /dev/null
+++ b/arch/powerpc/include/asm/byteorder.h
@@ -0,0 +1,89 @@
1#ifndef _ASM_POWERPC_BYTEORDER_H
2#define _ASM_POWERPC_BYTEORDER_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/types.h>
12#include <linux/compiler.h>
13
14#ifdef __GNUC__
15#ifdef __KERNEL__
16
17static __inline__ __u16 ld_le16(const volatile __u16 *addr)
18{
19 __u16 val;
20
21 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
22 return val;
23}
24
25static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
26{
27 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
28}
29
30static __inline__ __u32 ld_le32(const volatile __u32 *addr)
31{
32 __u32 val;
33
34 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
35 return val;
36}
37
38static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
39{
40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
41}
42
43static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
44{
45 __u16 result;
46
47 __asm__("rlwimi %0,%1,8,16,23"
48 : "=r" (result)
49 : "r" (value), "0" (value >> 8));
50 return result;
51}
52
53static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
54{
55 __u32 result;
56
57 __asm__("rlwimi %0,%1,24,16,23\n\t"
58 "rlwimi %0,%1,8,8,15\n\t"
59 "rlwimi %0,%1,24,0,7"
60 : "=r" (result)
61 : "r" (value), "0" (value >> 24));
62 return result;
63}
64
65#define __arch__swab16(x) ___arch__swab16(x)
66#define __arch__swab32(x) ___arch__swab32(x)
67
68/* The same, but returns converted value from the location pointer by addr. */
69#define __arch__swab16p(addr) ld_le16(addr)
70#define __arch__swab32p(addr) ld_le32(addr)
71
72/* The same, but do the conversion in situ, ie. put the value back to addr. */
73#define __arch__swab16s(addr) st_le16(addr,*addr)
74#define __arch__swab32s(addr) st_le32(addr,*addr)
75
76#endif /* __KERNEL__ */
77
78#ifndef __STRICT_ANSI__
79#define __BYTEORDER_HAS_U64__
80#ifndef __powerpc64__
81#define __SWAB_64_THRU_32__
82#endif /* __powerpc64__ */
83#endif /* __STRICT_ANSI__ */
84
85#endif /* __GNUC__ */
86
87#include <linux/byteorder/big_endian.h>
88
89#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
new file mode 100644
index 000000000000..81de6eb3455d
--- /dev/null
+++ b/arch/powerpc/include/asm/cache.h
@@ -0,0 +1,45 @@
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
9#define L1_CACHE_SHIFT 4
10#define MAX_COPY_PREFETCH 1
11#elif defined(CONFIG_PPC_E500MC)
12#define L1_CACHE_SHIFT 6
13#define MAX_COPY_PREFETCH 4
14#elif defined(CONFIG_PPC32)
15#define L1_CACHE_SHIFT 5
16#define MAX_COPY_PREFETCH 4
17#else /* CONFIG_PPC64 */
18#define L1_CACHE_SHIFT 7
19#endif
20
21#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
22
23#define SMP_CACHE_BYTES L1_CACHE_BYTES
24
25#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
26struct ppc64_caches {
27 u32 dsize; /* L1 d-cache size */
28 u32 dline_size; /* L1 d-cache line size */
29 u32 log_dline_size;
30 u32 dlines_per_page;
31 u32 isize; /* L1 i-cache size */
32 u32 iline_size; /* L1 i-cache line size */
33 u32 log_iline_size;
34 u32 ilines_per_page;
35};
36
37extern struct ppc64_caches ppc64_caches;
38#endif /* __powerpc64__ && ! __ASSEMBLY__ */
39
40#if !defined(__ASSEMBLY__)
41#define __read_mostly __attribute__((__section__(".data.read_mostly")))
42#endif
43
44#endif /* __KERNEL__ */
45#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
new file mode 100644
index 000000000000..ba667a383b8c
--- /dev/null
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -0,0 +1,75 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_CACHEFLUSH_H
8#define _ASM_POWERPC_CACHEFLUSH_H
9
10#ifdef __KERNEL__
11
12#include <linux/mm.h>
13#include <asm/cputable.h>
14
15/*
16 * No cache flushing is required when address mappings are changed,
17 * because the caches on PowerPCs are physically addressed.
18 */
19#define flush_cache_all() do { } while (0)
20#define flush_cache_mm(mm) do { } while (0)
21#define flush_cache_dup_mm(mm) do { } while (0)
22#define flush_cache_range(vma, start, end) do { } while (0)
23#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24#define flush_icache_page(vma, page) do { } while (0)
25#define flush_cache_vmap(start, end) do { } while (0)
26#define flush_cache_vunmap(start, end) do { } while (0)
27
28extern void flush_dcache_page(struct page *page);
29#define flush_dcache_mmap_lock(mapping) do { } while (0)
30#define flush_dcache_mmap_unlock(mapping) do { } while (0)
31
32extern void __flush_icache_range(unsigned long, unsigned long);
33static inline void flush_icache_range(unsigned long start, unsigned long stop)
34{
35 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
36 __flush_icache_range(start, stop);
37}
38
39extern void flush_icache_user_range(struct vm_area_struct *vma,
40 struct page *page, unsigned long addr,
41 int len);
42extern void __flush_dcache_icache(void *page_va);
43extern void flush_dcache_icache_page(struct page *page);
44#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
45extern void __flush_dcache_icache_phys(unsigned long physaddr);
46#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
47
48extern void flush_dcache_range(unsigned long start, unsigned long stop);
49#ifdef CONFIG_PPC32
50extern void clean_dcache_range(unsigned long start, unsigned long stop);
51extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
52#endif /* CONFIG_PPC32 */
53#ifdef CONFIG_PPC64
54extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
55extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
56#endif
57
58#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
59 do { \
60 memcpy(dst, src, len); \
61 flush_icache_user_range(vma, page, vaddr, len); \
62 } while (0)
63#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
64 memcpy(dst, src, len)
65
66
67
68#ifdef CONFIG_DEBUG_PAGEALLOC
69/* internal debugging function */
70void kernel_map_pages(struct page *page, int numpages, int enable);
71#endif
72
73#endif /* __KERNEL__ */
74
75#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/arch/powerpc/include/asm/cell-pmu.h b/arch/powerpc/include/asm/cell-pmu.h
new file mode 100644
index 000000000000..8066eede3a0c
--- /dev/null
+++ b/arch/powerpc/include/asm/cell-pmu.h
@@ -0,0 +1,105 @@
1/*
2 * Cell Broadband Engine Performance Monitor
3 *
4 * (C) Copyright IBM Corporation 2006
5 *
6 * Author:
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ASM_CELL_PMU_H__
26#define __ASM_CELL_PMU_H__
27
28/* The Cell PMU has four hardware performance counters, which can be
29 * configured as four 32-bit counters or eight 16-bit counters.
30 */
31#define NR_PHYS_CTRS 4
32#define NR_CTRS (NR_PHYS_CTRS * 2)
33
34/* Macros for the pm_control register. */
35#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
36#define CBE_PM_ENABLE_PERF_MON 0x80000000
37#define CBE_PM_STOP_AT_MAX 0x40000000
38#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
39#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
40#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
41#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
42#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
43
44/* Macros for the trace_address register. */
45#define CBE_PM_TRACE_BUF_FULL 0x00000800
46#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
47#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
48#define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
49
50/* Macros for the pm07_control registers. */
51#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
52#define CBE_PM_CTR_INPUT_CONTROL 0x02000000
53#define CBE_PM_CTR_POLARITY 0x01000000
54#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
55#define CBE_PM_CTR_ENABLE 0x00400000
56#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
57#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
58#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
59#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
60#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
61
62/* Macros for the pm_status register. */
63#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
64
65enum pm_reg_name {
66 group_control,
67 debug_bus_control,
68 trace_address,
69 ext_tr_timer,
70 pm_status,
71 pm_control,
72 pm_interval,
73 pm_start_stop,
74};
75
76/* Routines for reading/writing the PMU registers. */
77extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
78extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
79extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
80extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
81
82extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
83extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
84extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
85extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
86
87extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
88extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
89
90extern void cbe_enable_pm(u32 cpu);
91extern void cbe_disable_pm(u32 cpu);
92
93extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
94
95extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
96extern void cbe_disable_pm_interrupts(u32 cpu);
97extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
98extern void cbe_sync_irq(int node);
99
100#define CBE_COUNT_SUPERVISOR_MODE 0
101#define CBE_COUNT_HYPERVISOR_MODE 1
102#define CBE_COUNT_PROBLEM_MODE 2
103#define CBE_COUNT_ALL_MODES 3
104
105#endif /* __ASM_CELL_PMU_H__ */
diff --git a/arch/powerpc/include/asm/cell-regs.h b/arch/powerpc/include/asm/cell-regs.h
new file mode 100644
index 000000000000..fd6fd00434ef
--- /dev/null
+++ b/arch/powerpc/include/asm/cell-regs.h
@@ -0,0 +1,315 @@
1/*
2 * cbe_regs.h
3 *
4 * This file is intended to hold the various register definitions for CBE
5 * on-chip system devices (memory controller, IO controller, etc...)
6 *
7 * (C) Copyright IBM Corporation 2001,2006
8 *
9 * Authors: Maximino Aguilar (maguilar@us.ibm.com)
10 * David J. Erb (djerb@us.ibm.com)
11 *
12 * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
13 */
14
15#ifndef CBE_REGS_H
16#define CBE_REGS_H
17
18#include <asm/cell-pmu.h>
19
20/*
21 *
22 * Some HID register definitions
23 *
24 */
25
26/* CBE specific HID0 bits */
27#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
28#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
29#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
30#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
31
32#define MAX_CBE 2
33
34/*
35 *
36 * Pervasive unit register definitions
37 *
38 */
39
40union spe_reg {
41 u64 val;
42 u8 spe[8];
43};
44
45union ppe_spe_reg {
46 u64 val;
47 struct {
48 u32 ppe;
49 u32 spe;
50 };
51};
52
53
54struct cbe_pmd_regs {
55 /* Debug Bus Control */
56 u64 pad_0x0000; /* 0x0000 */
57
58 u64 group_control; /* 0x0008 */
59
60 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
61
62 u64 debug_bus_control; /* 0x00a8 */
63
64 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
65
66 u64 trace_aux_data; /* 0x0100 */
67 u64 trace_buffer_0_63; /* 0x0108 */
68 u64 trace_buffer_64_127; /* 0x0110 */
69 u64 trace_address; /* 0x0118 */
70 u64 ext_tr_timer; /* 0x0120 */
71
72 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
73
74 /* Performance Monitor */
75 u64 pm_status; /* 0x0400 */
76 u64 pm_control; /* 0x0408 */
77 u64 pm_interval; /* 0x0410 */
78 u64 pm_ctr[4]; /* 0x0418 */
79 u64 pm_start_stop; /* 0x0438 */
80 u64 pm07_control[8]; /* 0x0440 */
81
82 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
83
84 /* Thermal Sensor Registers */
85 union spe_reg ts_ctsr1; /* 0x0800 */
86 u64 ts_ctsr2; /* 0x0808 */
87 union spe_reg ts_mtsr1; /* 0x0810 */
88 u64 ts_mtsr2; /* 0x0818 */
89 union spe_reg ts_itr1; /* 0x0820 */
90 u64 ts_itr2; /* 0x0828 */
91 u64 ts_gitr; /* 0x0830 */
92 u64 ts_isr; /* 0x0838 */
93 u64 ts_imr; /* 0x0840 */
94 union spe_reg tm_cr1; /* 0x0848 */
95 u64 tm_cr2; /* 0x0850 */
96 u64 tm_simr; /* 0x0858 */
97 union ppe_spe_reg tm_tpr; /* 0x0860 */
98 union spe_reg tm_str1; /* 0x0868 */
99 u64 tm_str2; /* 0x0870 */
100 union ppe_spe_reg tm_tsr; /* 0x0878 */
101
102 /* Power Management */
103 u64 pmcr; /* 0x0880 */
104#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
105 u64 pmsr; /* 0x0888 */
106
107 /* Time Base Register */
108 u64 tbr; /* 0x0890 */
109
110 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
111
112 /* Fault Isolation Registers */
113 u64 checkstop_fir; /* 0x0c00 */
114 u64 recoverable_fir; /* 0x0c08 */
115 u64 spec_att_mchk_fir; /* 0x0c10 */
116 u32 fir_mode_reg; /* 0x0c18 */
117 u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */
118#define CBE_PMD_FIR_MODE_M8 0x00800
119 u64 fir_enable_mask; /* 0x0c20 */
120
121 u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
122 u64 ras_esc_0; /* 0x0ca8 */
123 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
124};
125
126extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
127extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
128
129/*
130 * PMU shadow registers
131 *
132 * Many of the registers in the performance monitoring unit are write-only,
133 * so we need to save a copy of what we write to those registers.
134 *
135 * The actual data counters are read/write. However, writing to the counters
136 * only takes effect if the PMU is enabled. Otherwise the value is stored in
137 * a hardware latch until the next time the PMU is enabled. So we save a copy
138 * of the counter values if we need to read them back while the PMU is
139 * disabled. The counter_value_in_latch field is a bitmap indicating which
140 * counters currently have a value waiting to be written.
141 */
142
143struct cbe_pmd_shadow_regs {
144 u32 group_control;
145 u32 debug_bus_control;
146 u32 trace_address;
147 u32 ext_tr_timer;
148 u32 pm_status;
149 u32 pm_control;
150 u32 pm_interval;
151 u32 pm_start_stop;
152 u32 pm07_control[NR_CTRS];
153
154 u32 pm_ctr[NR_PHYS_CTRS];
155 u32 counter_value_in_latch;
156};
157
158extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
159extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
160
161/*
162 *
163 * IIC unit register definitions
164 *
165 */
166
167struct cbe_iic_pending_bits {
168 u32 data;
169 u8 flags;
170 u8 class;
171 u8 source;
172 u8 prio;
173};
174
175#define CBE_IIC_IRQ_VALID 0x80
176#define CBE_IIC_IRQ_IPI 0x40
177
178struct cbe_iic_thread_regs {
179 struct cbe_iic_pending_bits pending;
180 struct cbe_iic_pending_bits pending_destr;
181 u64 generate;
182 u64 prio;
183};
184
185struct cbe_iic_regs {
186 u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
187
188 /* IIC interrupt registers */
189 struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
190
191 u64 iic_ir; /* 0x0440 */
192#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12)
193#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
194#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
195#define CBE_IIC_IR_IOC_0 0x0
196#define CBE_IIC_IR_IOC_1S 0xb
197#define CBE_IIC_IR_PT_0 0xe
198#define CBE_IIC_IR_PT_1 0xf
199
200 u64 iic_is; /* 0x0448 */
201#define CBE_IIC_IS_PMI 0x2
202
203 u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
204
205 /* IOC FIR */
206 u64 ioc_fir_reset; /* 0x0500 */
207 u64 ioc_fir_set; /* 0x0508 */
208 u64 ioc_checkstop_enable; /* 0x0510 */
209 u64 ioc_fir_error_mask; /* 0x0518 */
210 u64 ioc_syserr_enable; /* 0x0520 */
211 u64 ioc_fir; /* 0x0528 */
212
213 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
214};
215
216extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
217extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
218
219
220struct cbe_mic_tm_regs {
221 u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
222
223 u64 mic_ctl_cnfg2; /* 0x0040 */
224#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
225#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL
226#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL
227#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL
228
229 u64 pad_0x0048; /* 0x0048 */
230
231 u64 mic_aux_trc_base; /* 0x0050 */
232 u64 mic_aux_trc_max_addr; /* 0x0058 */
233 u64 mic_aux_trc_cur_addr; /* 0x0060 */
234 u64 mic_aux_trc_grf_addr; /* 0x0068 */
235 u64 mic_aux_trc_grf_data; /* 0x0070 */
236
237 u64 pad_0x0078; /* 0x0078 */
238
239 u64 mic_ctl_cnfg_0; /* 0x0080 */
240#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL
241
242 u64 pad_0x0088; /* 0x0088 */
243
244 u64 slow_fast_timer_0; /* 0x0090 */
245 u64 slow_next_timer_0; /* 0x0098 */
246
247 u8 pad_0x00a0_0x00f8[0x00f8 - 0x00a0]; /* 0x00a0 */
248 u64 mic_df_ecc_address_0; /* 0x00f8 */
249
250 u8 pad_0x0100_0x01b8[0x01b8 - 0x0100]; /* 0x0100 */
251 u64 mic_df_ecc_address_1; /* 0x01b8 */
252
253 u64 mic_ctl_cnfg_1; /* 0x01c0 */
254#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
255
256 u64 pad_0x01c8; /* 0x01c8 */
257
258 u64 slow_fast_timer_1; /* 0x01d0 */
259 u64 slow_next_timer_1; /* 0x01d8 */
260
261 u8 pad_0x01e0_0x0208[0x0208 - 0x01e0]; /* 0x01e0 */
262 u64 mic_exc; /* 0x0208 */
263#define CBE_MIC_EXC_BLOCK_SCRUB 0x0800000000000000ULL
264#define CBE_MIC_EXC_FAST_SCRUB 0x0100000000000000ULL
265
266 u64 mic_mnt_cfg; /* 0x0210 */
267#define CBE_MIC_MNT_CFG_CHAN_0_POP 0x0002000000000000ULL
268#define CBE_MIC_MNT_CFG_CHAN_1_POP 0x0004000000000000ULL
269
270 u64 mic_df_config; /* 0x0218 */
271#define CBE_MIC_ECC_DISABLE_0 0x4000000000000000ULL
272#define CBE_MIC_ECC_REP_SINGLE_0 0x2000000000000000ULL
273#define CBE_MIC_ECC_DISABLE_1 0x0080000000000000ULL
274#define CBE_MIC_ECC_REP_SINGLE_1 0x0040000000000000ULL
275
276 u8 pad_0x0220_0x0230[0x0230 - 0x0220]; /* 0x0220 */
277 u64 mic_fir; /* 0x0230 */
278#define CBE_MIC_FIR_ECC_SINGLE_0_ERR 0x0200000000000000ULL
279#define CBE_MIC_FIR_ECC_MULTI_0_ERR 0x0100000000000000ULL
280#define CBE_MIC_FIR_ECC_SINGLE_1_ERR 0x0080000000000000ULL
281#define CBE_MIC_FIR_ECC_MULTI_1_ERR 0x0040000000000000ULL
282#define CBE_MIC_FIR_ECC_ERR_MASK 0xffff000000000000ULL
283#define CBE_MIC_FIR_ECC_SINGLE_0_CTE 0x0000020000000000ULL
284#define CBE_MIC_FIR_ECC_MULTI_0_CTE 0x0000010000000000ULL
285#define CBE_MIC_FIR_ECC_SINGLE_1_CTE 0x0000008000000000ULL
286#define CBE_MIC_FIR_ECC_MULTI_1_CTE 0x0000004000000000ULL
287#define CBE_MIC_FIR_ECC_CTE_MASK 0x0000ffff00000000ULL
288#define CBE_MIC_FIR_ECC_SINGLE_0_RESET 0x0000000002000000ULL
289#define CBE_MIC_FIR_ECC_MULTI_0_RESET 0x0000000001000000ULL
290#define CBE_MIC_FIR_ECC_SINGLE_1_RESET 0x0000000000800000ULL
291#define CBE_MIC_FIR_ECC_MULTI_1_RESET 0x0000000000400000ULL
292#define CBE_MIC_FIR_ECC_RESET_MASK 0x00000000ffff0000ULL
293#define CBE_MIC_FIR_ECC_SINGLE_0_SET 0x0000000000000200ULL
294#define CBE_MIC_FIR_ECC_MULTI_0_SET 0x0000000000000100ULL
295#define CBE_MIC_FIR_ECC_SINGLE_1_SET 0x0000000000000080ULL
296#define CBE_MIC_FIR_ECC_MULTI_1_SET 0x0000000000000040ULL
297#define CBE_MIC_FIR_ECC_SET_MASK 0x000000000000ffffULL
298 u64 mic_fir_debug; /* 0x0238 */
299
300 u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */
301};
302
303extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
304extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
305
306/* some utility functions to deal with SMT */
307extern u32 cbe_get_hw_thread_id(int cpu);
308extern u32 cbe_cpu_to_node(int cpu);
309extern u32 cbe_node_to_cpu(int node);
310
311/* Init this module early */
312extern void cbe_regs_init(void);
313
314
315#endif /* CBE_REGS_H */
diff --git a/arch/powerpc/include/asm/checksum.h b/arch/powerpc/include/asm/checksum.h
new file mode 100644
index 000000000000..7cdf358337cf
--- /dev/null
+++ b/arch/powerpc/include/asm/checksum.h
@@ -0,0 +1,117 @@
1#ifndef _ASM_POWERPC_CHECKSUM_H
2#define _ASM_POWERPC_CHECKSUM_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/*
13 * This is a version of ip_compute_csum() optimized for IP headers,
14 * which always checksum on 4 octet boundaries. ihl is the number
15 * of 32-bit words and is always >= 5.
16 */
17extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
18
19/*
20 * computes the checksum of the TCP/UDP pseudo-header
21 * returns a 16-bit checksum, already complemented
22 */
23extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
24 unsigned short len,
25 unsigned short proto,
26 __wsum sum);
27
28/*
29 * computes the checksum of a memory block at buff, length len,
30 * and adds in "sum" (32-bit)
31 *
32 * returns a 32-bit number suitable for feeding into itself
33 * or csum_tcpudp_magic
34 *
35 * this function must be called with even lengths, except
36 * for the last fragment, which may be odd
37 *
38 * it's best to have buff aligned on a 32-bit boundary
39 */
40extern __wsum csum_partial(const void *buff, int len, __wsum sum);
41
42/*
43 * Computes the checksum of a memory block at src, length len,
44 * and adds in "sum" (32-bit), while copying the block to dst.
45 * If an access exception occurs on src or dst, it stores -EFAULT
46 * to *src_err or *dst_err respectively (if that pointer is not
47 * NULL), and, for an error on src, zeroes the rest of dst.
48 *
49 * Like csum_partial, this must be called with even lengths,
50 * except for the last fragment.
51 */
52extern __wsum csum_partial_copy_generic(const void *src, void *dst,
53 int len, __wsum sum,
54 int *src_err, int *dst_err);
55/*
56 * the same as csum_partial, but copies from src to dst while it
57 * checksums.
58 */
59#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
60 csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
61
62#define csum_partial_copy_nocheck(src, dst, len, sum) \
63 csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
64
65
66/*
67 * turns a 32-bit partial checksum (e.g. from csum_partial) into a
68 * 1's complement 16-bit checksum.
69 */
70static inline __sum16 csum_fold(__wsum sum)
71{
72 unsigned int tmp;
73
74 /* swap the two 16-bit halves of sum */
75 __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
76 /* if there is a carry from adding the two 16-bit halves,
77 it will carry from the lower half into the upper half,
78 giving us the correct sum in the upper half. */
79 return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
80}
81
82/*
83 * this routine is used for miscellaneous IP-like checksums, mainly
84 * in icmp.c
85 */
86static inline __sum16 ip_compute_csum(const void *buff, int len)
87{
88 return csum_fold(csum_partial(buff, len, 0));
89}
90
91static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
92 unsigned short len,
93 unsigned short proto,
94 __wsum sum)
95{
96#ifdef __powerpc64__
97 unsigned long s = (__force u32)sum;
98
99 s += (__force u32)saddr;
100 s += (__force u32)daddr;
101 s += proto + len;
102 s += (s >> 32);
103 return (__force __wsum) s;
104#else
105 __asm__("\n\
106 addc %0,%0,%1 \n\
107 adde %0,%0,%2 \n\
108 adde %0,%0,%3 \n\
109 addze %0,%0 \n\
110 "
111 : "=r" (sum)
112 : "r" (daddr), "r"(saddr), "r"(proto + len), "0"(sum));
113 return sum;
114#endif
115}
116#endif /* __KERNEL__ */
117#endif
diff --git a/arch/powerpc/include/asm/clk_interface.h b/arch/powerpc/include/asm/clk_interface.h
new file mode 100644
index 000000000000..ab1882c1e176
--- /dev/null
+++ b/arch/powerpc/include/asm/clk_interface.h
@@ -0,0 +1,20 @@
1#ifndef __ASM_POWERPC_CLK_INTERFACE_H
2#define __ASM_POWERPC_CLK_INTERFACE_H
3
4#include <linux/clk.h>
5
6struct clk_interface {
7 struct clk* (*clk_get) (struct device *dev, const char *id);
8 int (*clk_enable) (struct clk *clk);
9 void (*clk_disable) (struct clk *clk);
10 unsigned long (*clk_get_rate) (struct clk *clk);
11 void (*clk_put) (struct clk *clk);
12 long (*clk_round_rate) (struct clk *clk, unsigned long rate);
13 int (*clk_set_rate) (struct clk *clk, unsigned long rate);
14 int (*clk_set_parent) (struct clk *clk, struct clk *parent);
15 struct clk* (*clk_get_parent) (struct clk *clk);
16};
17
18extern struct clk_interface clk_functions;
19
20#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
new file mode 100644
index 000000000000..107d9b915e33
--- /dev/null
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -0,0 +1,54 @@
1#ifndef _ASM_POWERPC_CODE_PATCHING_H
2#define _ASM_POWERPC_CODE_PATCHING_H
3
4/*
5 * Copyright 2008, Michael Ellerman, IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/types.h>
14
15#define PPC_NOP_INSTR 0x60000000
16#define PPC_LWSYNC_INSTR 0x7c2004ac
17
18/* Flags for create_branch:
19 * "b" == create_branch(addr, target, 0);
20 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
21 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
22 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
23 */
24#define BRANCH_SET_LINK 0x1
25#define BRANCH_ABSOLUTE 0x2
26
27unsigned int create_branch(const unsigned int *addr,
28 unsigned long target, int flags);
29unsigned int create_cond_branch(const unsigned int *addr,
30 unsigned long target, int flags);
31void patch_branch(unsigned int *addr, unsigned long target, int flags);
32void patch_instruction(unsigned int *addr, unsigned int instr);
33
34int instr_is_relative_branch(unsigned int instr);
35int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
36unsigned long branch_target(const unsigned int *instr);
37unsigned int translate_branch(const unsigned int *dest,
38 const unsigned int *src);
39
40static inline unsigned long ppc_function_entry(void *func)
41{
42#ifdef CONFIG_PPC64
43 /*
44 * On PPC64 the function pointer actually points to the function's
45 * descriptor. The first entry in the descriptor is the address
46 * of the function text.
47 */
48 return ((func_descr_t *)func)->entry;
49#else
50 return (unsigned long)func;
51#endif
52}
53
54#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
new file mode 100644
index 000000000000..d811a8cd7b58
--- /dev/null
+++ b/arch/powerpc/include/asm/compat.h
@@ -0,0 +1,214 @@
1#ifndef _ASM_POWERPC_COMPAT_H
2#define _ASM_POWERPC_COMPAT_H
3#ifdef __KERNEL__
4/*
5 * Architecture specific compatibility types
6 */
7#include <linux/types.h>
8#include <linux/sched.h>
9
10#define COMPAT_USER_HZ 100
11
12typedef u32 compat_size_t;
13typedef s32 compat_ssize_t;
14typedef s32 compat_time_t;
15typedef s32 compat_clock_t;
16typedef s32 compat_pid_t;
17typedef u32 __compat_uid_t;
18typedef u32 __compat_gid_t;
19typedef u32 __compat_uid32_t;
20typedef u32 __compat_gid32_t;
21typedef u32 compat_mode_t;
22typedef u32 compat_ino_t;
23typedef u32 compat_dev_t;
24typedef s32 compat_off_t;
25typedef s64 compat_loff_t;
26typedef s16 compat_nlink_t;
27typedef u16 compat_ipc_pid_t;
28typedef s32 compat_daddr_t;
29typedef u32 compat_caddr_t;
30typedef __kernel_fsid_t compat_fsid_t;
31typedef s32 compat_key_t;
32typedef s32 compat_timer_t;
33
34typedef s32 compat_int_t;
35typedef s32 compat_long_t;
36typedef s64 compat_s64;
37typedef u32 compat_uint_t;
38typedef u32 compat_ulong_t;
39typedef u64 compat_u64;
40
41struct compat_timespec {
42 compat_time_t tv_sec;
43 s32 tv_nsec;
44};
45
46struct compat_timeval {
47 compat_time_t tv_sec;
48 s32 tv_usec;
49};
50
51struct compat_stat {
52 compat_dev_t st_dev;
53 compat_ino_t st_ino;
54 compat_mode_t st_mode;
55 compat_nlink_t st_nlink;
56 __compat_uid32_t st_uid;
57 __compat_gid32_t st_gid;
58 compat_dev_t st_rdev;
59 compat_off_t st_size;
60 compat_off_t st_blksize;
61 compat_off_t st_blocks;
62 compat_time_t st_atime;
63 u32 st_atime_nsec;
64 compat_time_t st_mtime;
65 u32 st_mtime_nsec;
66 compat_time_t st_ctime;
67 u32 st_ctime_nsec;
68 u32 __unused4[2];
69};
70
71struct compat_flock {
72 short l_type;
73 short l_whence;
74 compat_off_t l_start;
75 compat_off_t l_len;
76 compat_pid_t l_pid;
77};
78
79#define F_GETLK64 12 /* using 'struct flock64' */
80#define F_SETLK64 13
81#define F_SETLKW64 14
82
83struct compat_flock64 {
84 short l_type;
85 short l_whence;
86 compat_loff_t l_start;
87 compat_loff_t l_len;
88 compat_pid_t l_pid;
89};
90
91struct compat_statfs {
92 int f_type;
93 int f_bsize;
94 int f_blocks;
95 int f_bfree;
96 int f_bavail;
97 int f_files;
98 int f_ffree;
99 compat_fsid_t f_fsid;
100 int f_namelen; /* SunOS ignores this field. */
101 int f_frsize;
102 int f_spare[5];
103};
104
105#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
106#define COMPAT_RLIM_INFINITY 0xffffffff
107
108typedef u32 compat_old_sigset_t;
109
110#define _COMPAT_NSIG 64
111#define _COMPAT_NSIG_BPW 32
112
113typedef u32 compat_sigset_word;
114
115#define COMPAT_OFF_T_MAX 0x7fffffff
116#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
117
118/*
119 * A pointer passed in from user mode. This should not
120 * be used for syscall parameters, just declare them
121 * as pointers because the syscall entry code will have
122 * appropriately converted them already.
123 */
124typedef u32 compat_uptr_t;
125
126static inline void __user *compat_ptr(compat_uptr_t uptr)
127{
128 return (void __user *)(unsigned long)uptr;
129}
130
131static inline compat_uptr_t ptr_to_compat(void __user *uptr)
132{
133 return (u32)(unsigned long)uptr;
134}
135
136static inline void __user *compat_alloc_user_space(long len)
137{
138 struct pt_regs *regs = current->thread.regs;
139 unsigned long usp = regs->gpr[1];
140
141 /*
142 * We cant access below the stack pointer in the 32bit ABI and
143 * can access 288 bytes in the 64bit ABI
144 */
145 if (!(test_thread_flag(TIF_32BIT)))
146 usp -= 288;
147
148 return (void __user *) (usp - len);
149}
150
151/*
152 * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
153 * it we may as well define it.
154 */
155struct compat_ipc64_perm {
156 compat_key_t key;
157 __compat_uid_t uid;
158 __compat_gid_t gid;
159 __compat_uid_t cuid;
160 __compat_gid_t cgid;
161 compat_mode_t mode;
162 unsigned int seq;
163 unsigned int __pad2;
164 unsigned long __unused1; /* yes they really are 64bit pads */
165 unsigned long __unused2;
166};
167
168struct compat_semid64_ds {
169 struct compat_ipc64_perm sem_perm;
170 unsigned int __unused1;
171 compat_time_t sem_otime;
172 unsigned int __unused2;
173 compat_time_t sem_ctime;
174 compat_ulong_t sem_nsems;
175 compat_ulong_t __unused3;
176 compat_ulong_t __unused4;
177};
178
179struct compat_msqid64_ds {
180 struct compat_ipc64_perm msg_perm;
181 unsigned int __unused1;
182 compat_time_t msg_stime;
183 unsigned int __unused2;
184 compat_time_t msg_rtime;
185 unsigned int __unused3;
186 compat_time_t msg_ctime;
187 compat_ulong_t msg_cbytes;
188 compat_ulong_t msg_qnum;
189 compat_ulong_t msg_qbytes;
190 compat_pid_t msg_lspid;
191 compat_pid_t msg_lrpid;
192 compat_ulong_t __unused4;
193 compat_ulong_t __unused5;
194};
195
196struct compat_shmid64_ds {
197 struct compat_ipc64_perm shm_perm;
198 unsigned int __unused1;
199 compat_time_t shm_atime;
200 unsigned int __unused2;
201 compat_time_t shm_dtime;
202 unsigned int __unused3;
203 compat_time_t shm_ctime;
204 unsigned int __unused4;
205 compat_size_t shm_segsz;
206 compat_pid_t shm_cpid;
207 compat_pid_t shm_lpid;
208 compat_ulong_t shm_nattch;
209 compat_ulong_t __unused5;
210 compat_ulong_t __unused6;
211};
212
213#endif /* __KERNEL__ */
214#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
new file mode 100644
index 000000000000..24d79e3abd8e
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm.h
@@ -0,0 +1,106 @@
1#ifndef __CPM_H
2#define __CPM_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6#include <linux/of.h>
7
8/* Opcodes common to CPM1 and CPM2
9*/
10#define CPM_CR_INIT_TRX ((ushort)0x0000)
11#define CPM_CR_INIT_RX ((ushort)0x0001)
12#define CPM_CR_INIT_TX ((ushort)0x0002)
13#define CPM_CR_HUNT_MODE ((ushort)0x0003)
14#define CPM_CR_STOP_TX ((ushort)0x0004)
15#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
16#define CPM_CR_RESTART_TX ((ushort)0x0006)
17#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
18#define CPM_CR_SET_GADDR ((ushort)0x0008)
19#define CPM_CR_SET_TIMER ((ushort)0x0008)
20#define CPM_CR_STOP_IDMA ((ushort)0x000b)
21
22/* Buffer descriptors used by many of the CPM protocols. */
23typedef struct cpm_buf_desc {
24 ushort cbd_sc; /* Status and Control */
25 ushort cbd_datlen; /* Data length in buffer */
26 uint cbd_bufaddr; /* Buffer address in host memory */
27} cbd_t;
28
29/* Buffer descriptor control/status used by serial
30 */
31
32#define BD_SC_EMPTY (0x8000) /* Receive is empty */
33#define BD_SC_READY (0x8000) /* Transmit is ready */
34#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
35#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
36#define BD_SC_LAST (0x0800) /* Last buffer in frame */
37#define BD_SC_TC (0x0400) /* Transmit CRC */
38#define BD_SC_CM (0x0200) /* Continous mode */
39#define BD_SC_ID (0x0100) /* Rec'd too many idles */
40#define BD_SC_P (0x0100) /* xmt preamble */
41#define BD_SC_BR (0x0020) /* Break received */
42#define BD_SC_FR (0x0010) /* Framing error */
43#define BD_SC_PR (0x0008) /* Parity error */
44#define BD_SC_NAK (0x0004) /* NAK - did not respond */
45#define BD_SC_OV (0x0002) /* Overrun */
46#define BD_SC_UN (0x0002) /* Underrun */
47#define BD_SC_CD (0x0001) /* */
48#define BD_SC_CL (0x0001) /* Collision */
49
50/* Buffer descriptor control/status used by Ethernet receive.
51 * Common to SCC and FCC.
52 */
53#define BD_ENET_RX_EMPTY (0x8000)
54#define BD_ENET_RX_WRAP (0x2000)
55#define BD_ENET_RX_INTR (0x1000)
56#define BD_ENET_RX_LAST (0x0800)
57#define BD_ENET_RX_FIRST (0x0400)
58#define BD_ENET_RX_MISS (0x0100)
59#define BD_ENET_RX_BC (0x0080) /* FCC Only */
60#define BD_ENET_RX_MC (0x0040) /* FCC Only */
61#define BD_ENET_RX_LG (0x0020)
62#define BD_ENET_RX_NO (0x0010)
63#define BD_ENET_RX_SH (0x0008)
64#define BD_ENET_RX_CR (0x0004)
65#define BD_ENET_RX_OV (0x0002)
66#define BD_ENET_RX_CL (0x0001)
67#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
68
69/* Buffer descriptor control/status used by Ethernet transmit.
70 * Common to SCC and FCC.
71 */
72#define BD_ENET_TX_READY (0x8000)
73#define BD_ENET_TX_PAD (0x4000)
74#define BD_ENET_TX_WRAP (0x2000)
75#define BD_ENET_TX_INTR (0x1000)
76#define BD_ENET_TX_LAST (0x0800)
77#define BD_ENET_TX_TC (0x0400)
78#define BD_ENET_TX_DEF (0x0200)
79#define BD_ENET_TX_HB (0x0100)
80#define BD_ENET_TX_LC (0x0080)
81#define BD_ENET_TX_RL (0x0040)
82#define BD_ENET_TX_RCMASK (0x003c)
83#define BD_ENET_TX_UN (0x0002)
84#define BD_ENET_TX_CSL (0x0001)
85#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
86
87/* Buffer descriptor control/status used by Transparent mode SCC.
88 */
89#define BD_SCC_TX_LAST (0x0800)
90
91/* Buffer descriptor control/status used by I2C.
92 */
93#define BD_I2C_START (0x0400)
94
95int cpm_muram_init(void);
96unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
97int cpm_muram_free(unsigned long offset);
98unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
99void __iomem *cpm_muram_addr(unsigned long offset);
100unsigned long cpm_muram_offset(void __iomem *addr);
101dma_addr_t cpm_muram_dma(void __iomem *addr);
102int cpm_command(u32 command, u8 opcode);
103
104int cpm2_gpiochip_add32(struct device_node *np);
105
106#endif
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
new file mode 100644
index 000000000000..2ff798744c1d
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -0,0 +1,652 @@
1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM1__
18#define __CPM1__
19
20#include <asm/8xx_immap.h>
21#include <asm/ptrace.h>
22#include <asm/cpm.h>
23
24/* CPM Command register.
25*/
26#define CPM_CR_RST ((ushort)0x8000)
27#define CPM_CR_OPCODE ((ushort)0x0f00)
28#define CPM_CR_CHAN ((ushort)0x00f0)
29#define CPM_CR_FLG ((ushort)0x0001)
30
31/* Channel numbers.
32*/
33#define CPM_CR_CH_SCC1 ((ushort)0x0000)
34#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
35#define CPM_CR_CH_SCC2 ((ushort)0x0004)
36#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
37#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
38#define CPM_CR_CH_SCC3 ((ushort)0x0008)
39#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
40#define CPM_CR_CH_SCC4 ((ushort)0x000c)
41#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
42
43#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
44
45/* Export the base address of the communication processor registers
46 * and dual port ram.
47 */
48extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
49
50#define cpm_dpalloc cpm_muram_alloc
51#define cpm_dpfree cpm_muram_free
52#define cpm_dpram_addr cpm_muram_addr
53#define cpm_dpram_phys cpm_muram_dma
54
55extern void cpm_setbrg(uint brg, uint rate);
56
57extern void cpm_load_patch(cpm8xx_t *cp);
58
59extern void cpm_reset(void);
60
61/* Parameter RAM offsets.
62*/
63#define PROFF_SCC1 ((uint)0x0000)
64#define PROFF_IIC ((uint)0x0080)
65#define PROFF_SCC2 ((uint)0x0100)
66#define PROFF_SPI ((uint)0x0180)
67#define PROFF_SCC3 ((uint)0x0200)
68#define PROFF_SMC1 ((uint)0x0280)
69#define PROFF_SCC4 ((uint)0x0300)
70#define PROFF_SMC2 ((uint)0x0380)
71
72/* Define enough so I can at least use the serial port as a UART.
73 * The MBX uses SMC1 as the host serial port.
74 */
75typedef struct smc_uart {
76 ushort smc_rbase; /* Rx Buffer descriptor base address */
77 ushort smc_tbase; /* Tx Buffer descriptor base address */
78 u_char smc_rfcr; /* Rx function code */
79 u_char smc_tfcr; /* Tx function code */
80 ushort smc_mrblr; /* Max receive buffer length */
81 uint smc_rstate; /* Internal */
82 uint smc_idp; /* Internal */
83 ushort smc_rbptr; /* Internal */
84 ushort smc_ibc; /* Internal */
85 uint smc_rxtmp; /* Internal */
86 uint smc_tstate; /* Internal */
87 uint smc_tdp; /* Internal */
88 ushort smc_tbptr; /* Internal */
89 ushort smc_tbc; /* Internal */
90 uint smc_txtmp; /* Internal */
91 ushort smc_maxidl; /* Maximum idle characters */
92 ushort smc_tmpidl; /* Temporary idle counter */
93 ushort smc_brklen; /* Last received break length */
94 ushort smc_brkec; /* rcv'd break condition counter */
95 ushort smc_brkcr; /* xmt break count register */
96 ushort smc_rmask; /* Temporary bit mask */
97 char res1[8]; /* Reserved */
98 ushort smc_rpbase; /* Relocation pointer */
99} smc_uart_t;
100
101/* Function code bits.
102*/
103#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
104
105/* SMC uart mode register.
106*/
107#define SMCMR_REN ((ushort)0x0001)
108#define SMCMR_TEN ((ushort)0x0002)
109#define SMCMR_DM ((ushort)0x000c)
110#define SMCMR_SM_GCI ((ushort)0x0000)
111#define SMCMR_SM_UART ((ushort)0x0020)
112#define SMCMR_SM_TRANS ((ushort)0x0030)
113#define SMCMR_SM_MASK ((ushort)0x0030)
114#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
115#define SMCMR_REVD SMCMR_PM_EVEN
116#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
117#define SMCMR_BS SMCMR_PEN
118#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
119#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
120#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
121
122/* SMC2 as Centronics parallel printer. It is half duplex, in that
123 * it can only receive or transmit. The parameter ram values for
124 * each direction are either unique or properly overlap, so we can
125 * include them in one structure.
126 */
127typedef struct smc_centronics {
128 ushort scent_rbase;
129 ushort scent_tbase;
130 u_char scent_cfcr;
131 u_char scent_smask;
132 ushort scent_mrblr;
133 uint scent_rstate;
134 uint scent_r_ptr;
135 ushort scent_rbptr;
136 ushort scent_r_cnt;
137 uint scent_rtemp;
138 uint scent_tstate;
139 uint scent_t_ptr;
140 ushort scent_tbptr;
141 ushort scent_t_cnt;
142 uint scent_ttemp;
143 ushort scent_max_sl;
144 ushort scent_sl_cnt;
145 ushort scent_character1;
146 ushort scent_character2;
147 ushort scent_character3;
148 ushort scent_character4;
149 ushort scent_character5;
150 ushort scent_character6;
151 ushort scent_character7;
152 ushort scent_character8;
153 ushort scent_rccm;
154 ushort scent_rccr;
155} smc_cent_t;
156
157/* Centronics Status Mask Register.
158*/
159#define SMC_CENT_F ((u_char)0x08)
160#define SMC_CENT_PE ((u_char)0x04)
161#define SMC_CENT_S ((u_char)0x02)
162
163/* SMC Event and Mask register.
164*/
165#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
166#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
167#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
168#define SMCM_BSY ((unsigned char)0x04)
169#define SMCM_TX ((unsigned char)0x02)
170#define SMCM_RX ((unsigned char)0x01)
171
172/* Baud rate generators.
173*/
174#define CPM_BRG_RST ((uint)0x00020000)
175#define CPM_BRG_EN ((uint)0x00010000)
176#define CPM_BRG_EXTC_INT ((uint)0x00000000)
177#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
178#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
179#define CPM_BRG_ATB ((uint)0x00002000)
180#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
181#define CPM_BRG_DIV16 ((uint)0x00000001)
182
183/* SI Clock Route Register
184*/
185#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
186#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
187#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
188#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
189#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
190#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
191#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
192#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
193
194/* SCCs.
195*/
196#define SCC_GSMRH_IRP ((uint)0x00040000)
197#define SCC_GSMRH_GDE ((uint)0x00010000)
198#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
199#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
200#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
201#define SCC_GSMRH_REVD ((uint)0x00002000)
202#define SCC_GSMRH_TRX ((uint)0x00001000)
203#define SCC_GSMRH_TTX ((uint)0x00000800)
204#define SCC_GSMRH_CDP ((uint)0x00000400)
205#define SCC_GSMRH_CTSP ((uint)0x00000200)
206#define SCC_GSMRH_CDS ((uint)0x00000100)
207#define SCC_GSMRH_CTSS ((uint)0x00000080)
208#define SCC_GSMRH_TFL ((uint)0x00000040)
209#define SCC_GSMRH_RFW ((uint)0x00000020)
210#define SCC_GSMRH_TXSY ((uint)0x00000010)
211#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
212#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
213#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
214#define SCC_GSMRH_RTSM ((uint)0x00000002)
215#define SCC_GSMRH_RSYN ((uint)0x00000001)
216
217#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
218#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
219#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
220#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
221#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
222#define SCC_GSMRL_TCI ((uint)0x10000000)
223#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
224#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
225#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
226#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
227#define SCC_GSMRL_RINV ((uint)0x02000000)
228#define SCC_GSMRL_TINV ((uint)0x01000000)
229#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
230#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
231#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
232#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
233#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
234#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
235#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
236#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
237#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
238#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
239#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
240#define SCC_GSMRL_TEND ((uint)0x00040000)
241#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
242#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
243#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
244#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
245#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
246#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
247#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
248#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
249#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
250#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
251#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
252#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
253#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
254#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
255#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
256#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
257#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
258#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
259#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
260#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
261#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
262#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
263#define SCC_GSMRL_ENR ((uint)0x00000020)
264#define SCC_GSMRL_ENT ((uint)0x00000010)
265#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
266#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
267#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
268#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
269#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
270#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
271#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
272#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
273#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
274#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
275#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
276
277#define SCC_TODR_TOD ((ushort)0x8000)
278
279/* SCC Event and Mask register.
280*/
281#define SCCM_TXE ((unsigned char)0x10)
282#define SCCM_BSY ((unsigned char)0x04)
283#define SCCM_TX ((unsigned char)0x02)
284#define SCCM_RX ((unsigned char)0x01)
285
286typedef struct scc_param {
287 ushort scc_rbase; /* Rx Buffer descriptor base address */
288 ushort scc_tbase; /* Tx Buffer descriptor base address */
289 u_char scc_rfcr; /* Rx function code */
290 u_char scc_tfcr; /* Tx function code */
291 ushort scc_mrblr; /* Max receive buffer length */
292 uint scc_rstate; /* Internal */
293 uint scc_idp; /* Internal */
294 ushort scc_rbptr; /* Internal */
295 ushort scc_ibc; /* Internal */
296 uint scc_rxtmp; /* Internal */
297 uint scc_tstate; /* Internal */
298 uint scc_tdp; /* Internal */
299 ushort scc_tbptr; /* Internal */
300 ushort scc_tbc; /* Internal */
301 uint scc_txtmp; /* Internal */
302 uint scc_rcrc; /* Internal */
303 uint scc_tcrc; /* Internal */
304} sccp_t;
305
306/* Function code bits.
307*/
308#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
309
310/* CPM Ethernet through SCCx.
311 */
312typedef struct scc_enet {
313 sccp_t sen_genscc;
314 uint sen_cpres; /* Preset CRC */
315 uint sen_cmask; /* Constant mask for CRC */
316 uint sen_crcec; /* CRC Error counter */
317 uint sen_alec; /* alignment error counter */
318 uint sen_disfc; /* discard frame counter */
319 ushort sen_pads; /* Tx short frame pad character */
320 ushort sen_retlim; /* Retry limit threshold */
321 ushort sen_retcnt; /* Retry limit counter */
322 ushort sen_maxflr; /* maximum frame length register */
323 ushort sen_minflr; /* minimum frame length register */
324 ushort sen_maxd1; /* maximum DMA1 length */
325 ushort sen_maxd2; /* maximum DMA2 length */
326 ushort sen_maxd; /* Rx max DMA */
327 ushort sen_dmacnt; /* Rx DMA counter */
328 ushort sen_maxb; /* Max BD byte count */
329 ushort sen_gaddr1; /* Group address filter */
330 ushort sen_gaddr2;
331 ushort sen_gaddr3;
332 ushort sen_gaddr4;
333 uint sen_tbuf0data0; /* Save area 0 - current frame */
334 uint sen_tbuf0data1; /* Save area 1 - current frame */
335 uint sen_tbuf0rba; /* Internal */
336 uint sen_tbuf0crc; /* Internal */
337 ushort sen_tbuf0bcnt; /* Internal */
338 ushort sen_paddrh; /* physical address (MSB) */
339 ushort sen_paddrm;
340 ushort sen_paddrl; /* physical address (LSB) */
341 ushort sen_pper; /* persistence */
342 ushort sen_rfbdptr; /* Rx first BD pointer */
343 ushort sen_tfbdptr; /* Tx first BD pointer */
344 ushort sen_tlbdptr; /* Tx last BD pointer */
345 uint sen_tbuf1data0; /* Save area 0 - current frame */
346 uint sen_tbuf1data1; /* Save area 1 - current frame */
347 uint sen_tbuf1rba; /* Internal */
348 uint sen_tbuf1crc; /* Internal */
349 ushort sen_tbuf1bcnt; /* Internal */
350 ushort sen_txlen; /* Tx Frame length counter */
351 ushort sen_iaddr1; /* Individual address filter */
352 ushort sen_iaddr2;
353 ushort sen_iaddr3;
354 ushort sen_iaddr4;
355 ushort sen_boffcnt; /* Backoff counter */
356
357 /* NOTE: Some versions of the manual have the following items
358 * incorrectly documented. Below is the proper order.
359 */
360 ushort sen_taddrh; /* temp address (MSB) */
361 ushort sen_taddrm;
362 ushort sen_taddrl; /* temp address (LSB) */
363} scc_enet_t;
364
365/* SCC Event register as used by Ethernet.
366*/
367#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
368#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
369#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
370#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
371#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
372#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
373
374/* SCC Mode Register (PMSR) as used by Ethernet.
375*/
376#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
377#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
378#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
379#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
380#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
381#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
382#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
383#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
384#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
385#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
386#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
387#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
388#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
389
390/* SCC as UART
391*/
392typedef struct scc_uart {
393 sccp_t scc_genscc;
394 char res1[8]; /* Reserved */
395 ushort scc_maxidl; /* Maximum idle chars */
396 ushort scc_idlc; /* temp idle counter */
397 ushort scc_brkcr; /* Break count register */
398 ushort scc_parec; /* receive parity error counter */
399 ushort scc_frmec; /* receive framing error counter */
400 ushort scc_nosec; /* receive noise counter */
401 ushort scc_brkec; /* receive break condition counter */
402 ushort scc_brkln; /* last received break length */
403 ushort scc_uaddr1; /* UART address character 1 */
404 ushort scc_uaddr2; /* UART address character 2 */
405 ushort scc_rtemp; /* Temp storage */
406 ushort scc_toseq; /* Transmit out of sequence char */
407 ushort scc_char1; /* control character 1 */
408 ushort scc_char2; /* control character 2 */
409 ushort scc_char3; /* control character 3 */
410 ushort scc_char4; /* control character 4 */
411 ushort scc_char5; /* control character 5 */
412 ushort scc_char6; /* control character 6 */
413 ushort scc_char7; /* control character 7 */
414 ushort scc_char8; /* control character 8 */
415 ushort scc_rccm; /* receive control character mask */
416 ushort scc_rccr; /* receive control character register */
417 ushort scc_rlbc; /* receive last break character */
418} scc_uart_t;
419
420/* SCC Event and Mask registers when it is used as a UART.
421*/
422#define UART_SCCM_GLR ((ushort)0x1000)
423#define UART_SCCM_GLT ((ushort)0x0800)
424#define UART_SCCM_AB ((ushort)0x0200)
425#define UART_SCCM_IDL ((ushort)0x0100)
426#define UART_SCCM_GRA ((ushort)0x0080)
427#define UART_SCCM_BRKE ((ushort)0x0040)
428#define UART_SCCM_BRKS ((ushort)0x0020)
429#define UART_SCCM_CCR ((ushort)0x0008)
430#define UART_SCCM_BSY ((ushort)0x0004)
431#define UART_SCCM_TX ((ushort)0x0002)
432#define UART_SCCM_RX ((ushort)0x0001)
433
434/* The SCC PMSR when used as a UART.
435*/
436#define SCU_PSMR_FLC ((ushort)0x8000)
437#define SCU_PSMR_SL ((ushort)0x4000)
438#define SCU_PSMR_CL ((ushort)0x3000)
439#define SCU_PSMR_UM ((ushort)0x0c00)
440#define SCU_PSMR_FRZ ((ushort)0x0200)
441#define SCU_PSMR_RZS ((ushort)0x0100)
442#define SCU_PSMR_SYN ((ushort)0x0080)
443#define SCU_PSMR_DRT ((ushort)0x0040)
444#define SCU_PSMR_PEN ((ushort)0x0010)
445#define SCU_PSMR_RPM ((ushort)0x000c)
446#define SCU_PSMR_REVP ((ushort)0x0008)
447#define SCU_PSMR_TPM ((ushort)0x0003)
448#define SCU_PSMR_TEVP ((ushort)0x0002)
449
450/* CPM Transparent mode SCC.
451 */
452typedef struct scc_trans {
453 sccp_t st_genscc;
454 uint st_cpres; /* Preset CRC */
455 uint st_cmask; /* Constant mask for CRC */
456} scc_trans_t;
457
458/* IIC parameter RAM.
459*/
460typedef struct iic {
461 ushort iic_rbase; /* Rx Buffer descriptor base address */
462 ushort iic_tbase; /* Tx Buffer descriptor base address */
463 u_char iic_rfcr; /* Rx function code */
464 u_char iic_tfcr; /* Tx function code */
465 ushort iic_mrblr; /* Max receive buffer length */
466 uint iic_rstate; /* Internal */
467 uint iic_rdp; /* Internal */
468 ushort iic_rbptr; /* Internal */
469 ushort iic_rbc; /* Internal */
470 uint iic_rxtmp; /* Internal */
471 uint iic_tstate; /* Internal */
472 uint iic_tdp; /* Internal */
473 ushort iic_tbptr; /* Internal */
474 ushort iic_tbc; /* Internal */
475 uint iic_txtmp; /* Internal */
476 char res1[4]; /* Reserved */
477 ushort iic_rpbase; /* Relocation pointer */
478 char res2[2]; /* Reserved */
479} iic_t;
480
481/* SPI parameter RAM.
482*/
483typedef struct spi {
484 ushort spi_rbase; /* Rx Buffer descriptor base address */
485 ushort spi_tbase; /* Tx Buffer descriptor base address */
486 u_char spi_rfcr; /* Rx function code */
487 u_char spi_tfcr; /* Tx function code */
488 ushort spi_mrblr; /* Max receive buffer length */
489 uint spi_rstate; /* Internal */
490 uint spi_rdp; /* Internal */
491 ushort spi_rbptr; /* Internal */
492 ushort spi_rbc; /* Internal */
493 uint spi_rxtmp; /* Internal */
494 uint spi_tstate; /* Internal */
495 uint spi_tdp; /* Internal */
496 ushort spi_tbptr; /* Internal */
497 ushort spi_tbc; /* Internal */
498 uint spi_txtmp; /* Internal */
499 uint spi_res;
500 ushort spi_rpbase; /* Relocation pointer */
501 ushort spi_res2;
502} spi_t;
503
504/* SPI Mode register.
505*/
506#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
507#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
508#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
509#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
510#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
511#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
512#define SPMODE_EN ((ushort)0x0100) /* Enable */
513#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
514#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
515#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
516#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
517#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
518
519/* SPIE fields */
520#define SPIE_MME 0x20
521#define SPIE_TXE 0x10
522#define SPIE_BSY 0x04
523#define SPIE_TXB 0x02
524#define SPIE_RXB 0x01
525
526/*
527 * RISC Controller Configuration Register definitons
528 */
529#define RCCR_TIME 0x8000 /* RISC Timer Enable */
530#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
531#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
532
533/* RISC Timer Parameter RAM offset */
534#define PROFF_RTMR ((uint)0x01B0)
535
536typedef struct risc_timer_pram {
537 unsigned short tm_base; /* RISC Timer Table Base Address */
538 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
539 unsigned short r_tmr; /* RISC Timer Mode Register */
540 unsigned short r_tmv; /* RISC Timer Valid Register */
541 unsigned long tm_cmd; /* RISC Timer Command Register */
542 unsigned long tm_cnt; /* RISC Timer Internal Count */
543} rt_pram_t;
544
545/* Bits in RISC Timer Command Register */
546#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
547#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
548#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
549#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
550#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
551
552/* CPM interrupts. There are nearly 32 interrupts generated by CPM
553 * channels or devices. All of these are presented to the PPC core
554 * as a single interrupt. The CPM interrupt handler dispatches its
555 * own handlers, in a similar fashion to the PPC core handler. We
556 * use the table as defined in the manuals (i.e. no special high
557 * priority and SCC1 == SCCa, etc...).
558 */
559#define CPMVEC_NR 32
560#define CPMVEC_PIO_PC15 ((ushort)0x1f)
561#define CPMVEC_SCC1 ((ushort)0x1e)
562#define CPMVEC_SCC2 ((ushort)0x1d)
563#define CPMVEC_SCC3 ((ushort)0x1c)
564#define CPMVEC_SCC4 ((ushort)0x1b)
565#define CPMVEC_PIO_PC14 ((ushort)0x1a)
566#define CPMVEC_TIMER1 ((ushort)0x19)
567#define CPMVEC_PIO_PC13 ((ushort)0x18)
568#define CPMVEC_PIO_PC12 ((ushort)0x17)
569#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
570#define CPMVEC_IDMA1 ((ushort)0x15)
571#define CPMVEC_IDMA2 ((ushort)0x14)
572#define CPMVEC_TIMER2 ((ushort)0x12)
573#define CPMVEC_RISCTIMER ((ushort)0x11)
574#define CPMVEC_I2C ((ushort)0x10)
575#define CPMVEC_PIO_PC11 ((ushort)0x0f)
576#define CPMVEC_PIO_PC10 ((ushort)0x0e)
577#define CPMVEC_TIMER3 ((ushort)0x0c)
578#define CPMVEC_PIO_PC9 ((ushort)0x0b)
579#define CPMVEC_PIO_PC8 ((ushort)0x0a)
580#define CPMVEC_PIO_PC7 ((ushort)0x09)
581#define CPMVEC_TIMER4 ((ushort)0x07)
582#define CPMVEC_PIO_PC6 ((ushort)0x06)
583#define CPMVEC_SPI ((ushort)0x05)
584#define CPMVEC_SMC1 ((ushort)0x04)
585#define CPMVEC_SMC2 ((ushort)0x03)
586#define CPMVEC_PIO_PC5 ((ushort)0x02)
587#define CPMVEC_PIO_PC4 ((ushort)0x01)
588#define CPMVEC_ERROR ((ushort)0x00)
589
590/* CPM interrupt configuration vector.
591*/
592#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
593#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
594#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
595#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
596#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
597#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
598#define CICR_IEN ((uint)0x00000080) /* Int. enable */
599#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
600
601#define IMAP_ADDR (get_immrbase())
602
603#define CPM_PIN_INPUT 0
604#define CPM_PIN_OUTPUT 1
605#define CPM_PIN_PRIMARY 0
606#define CPM_PIN_SECONDARY 2
607#define CPM_PIN_GPIO 4
608#define CPM_PIN_OPENDRAIN 8
609
610enum cpm_port {
611 CPM_PORTA,
612 CPM_PORTB,
613 CPM_PORTC,
614 CPM_PORTD,
615 CPM_PORTE,
616};
617
618void cpm1_set_pin(enum cpm_port port, int pin, int flags);
619
620enum cpm_clk_dir {
621 CPM_CLK_RX,
622 CPM_CLK_TX,
623 CPM_CLK_RTX
624};
625
626enum cpm_clk_target {
627 CPM_CLK_SCC1,
628 CPM_CLK_SCC2,
629 CPM_CLK_SCC3,
630 CPM_CLK_SCC4,
631 CPM_CLK_SMC1,
632 CPM_CLK_SMC2,
633};
634
635enum cpm_clk {
636 CPM_BRG1, /* Baud Rate Generator 1 */
637 CPM_BRG2, /* Baud Rate Generator 2 */
638 CPM_BRG3, /* Baud Rate Generator 3 */
639 CPM_BRG4, /* Baud Rate Generator 4 */
640 CPM_CLK1, /* Clock 1 */
641 CPM_CLK2, /* Clock 2 */
642 CPM_CLK3, /* Clock 3 */
643 CPM_CLK4, /* Clock 4 */
644 CPM_CLK5, /* Clock 5 */
645 CPM_CLK6, /* Clock 6 */
646 CPM_CLK7, /* Clock 7 */
647 CPM_CLK8, /* Clock 8 */
648};
649
650int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
651
652#endif /* __CPM1__ */
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h
new file mode 100644
index 000000000000..2a6fa0183ac9
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm2.h
@@ -0,0 +1,1195 @@
1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14#include <asm/cpm.h>
15#include <sysdev/fsl_soc.h>
16
17#ifdef CONFIG_PPC_85xx
18#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
19#endif
20
21/* CPM Command register.
22*/
23#define CPM_CR_RST ((uint)0x80000000)
24#define CPM_CR_PAGE ((uint)0x7c000000)
25#define CPM_CR_SBLOCK ((uint)0x03e00000)
26#define CPM_CR_FLG ((uint)0x00010000)
27#define CPM_CR_MCN ((uint)0x00003fc0)
28#define CPM_CR_OPCODE ((uint)0x0000000f)
29
30/* Device sub-block and page codes.
31*/
32#define CPM_CR_SCC1_SBLOCK (0x04)
33#define CPM_CR_SCC2_SBLOCK (0x05)
34#define CPM_CR_SCC3_SBLOCK (0x06)
35#define CPM_CR_SCC4_SBLOCK (0x07)
36#define CPM_CR_SMC1_SBLOCK (0x08)
37#define CPM_CR_SMC2_SBLOCK (0x09)
38#define CPM_CR_SPI_SBLOCK (0x0a)
39#define CPM_CR_I2C_SBLOCK (0x0b)
40#define CPM_CR_TIMER_SBLOCK (0x0f)
41#define CPM_CR_RAND_SBLOCK (0x0e)
42#define CPM_CR_FCC1_SBLOCK (0x10)
43#define CPM_CR_FCC2_SBLOCK (0x11)
44#define CPM_CR_FCC3_SBLOCK (0x12)
45#define CPM_CR_IDMA1_SBLOCK (0x14)
46#define CPM_CR_IDMA2_SBLOCK (0x15)
47#define CPM_CR_IDMA3_SBLOCK (0x16)
48#define CPM_CR_IDMA4_SBLOCK (0x17)
49#define CPM_CR_MCC1_SBLOCK (0x1c)
50
51#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
52
53#define CPM_CR_SCC1_PAGE (0x00)
54#define CPM_CR_SCC2_PAGE (0x01)
55#define CPM_CR_SCC3_PAGE (0x02)
56#define CPM_CR_SCC4_PAGE (0x03)
57#define CPM_CR_SMC1_PAGE (0x07)
58#define CPM_CR_SMC2_PAGE (0x08)
59#define CPM_CR_SPI_PAGE (0x09)
60#define CPM_CR_I2C_PAGE (0x0a)
61#define CPM_CR_TIMER_PAGE (0x0a)
62#define CPM_CR_RAND_PAGE (0x0a)
63#define CPM_CR_FCC1_PAGE (0x04)
64#define CPM_CR_FCC2_PAGE (0x05)
65#define CPM_CR_FCC3_PAGE (0x06)
66#define CPM_CR_IDMA1_PAGE (0x07)
67#define CPM_CR_IDMA2_PAGE (0x08)
68#define CPM_CR_IDMA3_PAGE (0x09)
69#define CPM_CR_IDMA4_PAGE (0x0a)
70#define CPM_CR_MCC1_PAGE (0x07)
71#define CPM_CR_MCC2_PAGE (0x08)
72
73#define CPM_CR_FCC_PAGE(x) (x + 0x04)
74
75/* CPM2-specific opcodes (see cpm.h for common opcodes)
76*/
77#define CPM_CR_START_IDMA ((ushort)0x0009)
78
79#define mk_cr_cmd(PG, SBC, MCN, OP) \
80 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
81
82/* The number of pages of host memory we allocate for CPM. This is
83 * done early in kernel initialization to get physically contiguous
84 * pages.
85 */
86#define NUM_CPM_HOST_PAGES 2
87
88/* Export the base address of the communication processor registers
89 * and dual port ram.
90 */
91extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
92
93#define cpm_dpalloc cpm_muram_alloc
94#define cpm_dpfree cpm_muram_free
95#define cpm_dpram_addr cpm_muram_addr
96
97extern void cpm2_reset(void);
98
99/* Baud rate generators.
100*/
101#define CPM_BRG_RST ((uint)0x00020000)
102#define CPM_BRG_EN ((uint)0x00010000)
103#define CPM_BRG_EXTC_INT ((uint)0x00000000)
104#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
105#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
106#define CPM_BRG_ATB ((uint)0x00002000)
107#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
108#define CPM_BRG_DIV16 ((uint)0x00000001)
109
110#define CPM2_BRG_INT_CLK (get_brgfreq())
111#define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16)
112
113extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
114
115/* This function is used by UARTS, or anything else that uses a 16x
116 * oversampled clock.
117 */
118static inline void cpm_setbrg(uint brg, uint rate)
119{
120 __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
121}
122
123/* This function is used to set high speed synchronous baud rate
124 * clocks.
125 */
126static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
127{
128 __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
129}
130
131/* Function code bits, usually generic to devices.
132*/
133#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
134#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
135#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
136#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
137#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
138
139/* Parameter RAM offsets from the base.
140*/
141#define PROFF_SCC1 ((uint)0x8000)
142#define PROFF_SCC2 ((uint)0x8100)
143#define PROFF_SCC3 ((uint)0x8200)
144#define PROFF_SCC4 ((uint)0x8300)
145#define PROFF_FCC1 ((uint)0x8400)
146#define PROFF_FCC2 ((uint)0x8500)
147#define PROFF_FCC3 ((uint)0x8600)
148#define PROFF_MCC1 ((uint)0x8700)
149#define PROFF_SMC1_BASE ((uint)0x87fc)
150#define PROFF_IDMA1_BASE ((uint)0x87fe)
151#define PROFF_MCC2 ((uint)0x8800)
152#define PROFF_SMC2_BASE ((uint)0x88fc)
153#define PROFF_IDMA2_BASE ((uint)0x88fe)
154#define PROFF_SPI_BASE ((uint)0x89fc)
155#define PROFF_IDMA3_BASE ((uint)0x89fe)
156#define PROFF_TIMERS ((uint)0x8ae0)
157#define PROFF_REVNUM ((uint)0x8af0)
158#define PROFF_RAND ((uint)0x8af8)
159#define PROFF_I2C_BASE ((uint)0x8afc)
160#define PROFF_IDMA4_BASE ((uint)0x8afe)
161
162#define PROFF_SCC_SIZE ((uint)0x100)
163#define PROFF_FCC_SIZE ((uint)0x100)
164#define PROFF_SMC_SIZE ((uint)64)
165
166/* The SMCs are relocated to any of the first eight DPRAM pages.
167 * We will fix these at the first locations of DPRAM, until we
168 * get some microcode patches :-).
169 * The parameter ram space for the SMCs is fifty-some bytes, and
170 * they are required to start on a 64 byte boundary.
171 */
172#define PROFF_SMC1 (0)
173#define PROFF_SMC2 (64)
174
175
176/* Define enough so I can at least use the serial port as a UART.
177 */
178typedef struct smc_uart {
179 ushort smc_rbase; /* Rx Buffer descriptor base address */
180 ushort smc_tbase; /* Tx Buffer descriptor base address */
181 u_char smc_rfcr; /* Rx function code */
182 u_char smc_tfcr; /* Tx function code */
183 ushort smc_mrblr; /* Max receive buffer length */
184 uint smc_rstate; /* Internal */
185 uint smc_idp; /* Internal */
186 ushort smc_rbptr; /* Internal */
187 ushort smc_ibc; /* Internal */
188 uint smc_rxtmp; /* Internal */
189 uint smc_tstate; /* Internal */
190 uint smc_tdp; /* Internal */
191 ushort smc_tbptr; /* Internal */
192 ushort smc_tbc; /* Internal */
193 uint smc_txtmp; /* Internal */
194 ushort smc_maxidl; /* Maximum idle characters */
195 ushort smc_tmpidl; /* Temporary idle counter */
196 ushort smc_brklen; /* Last received break length */
197 ushort smc_brkec; /* rcv'd break condition counter */
198 ushort smc_brkcr; /* xmt break count register */
199 ushort smc_rmask; /* Temporary bit mask */
200 uint smc_stmp; /* SDMA Temp */
201} smc_uart_t;
202
203/* SMC uart mode register (Internal memory map).
204*/
205#define SMCMR_REN ((ushort)0x0001)
206#define SMCMR_TEN ((ushort)0x0002)
207#define SMCMR_DM ((ushort)0x000c)
208#define SMCMR_SM_GCI ((ushort)0x0000)
209#define SMCMR_SM_UART ((ushort)0x0020)
210#define SMCMR_SM_TRANS ((ushort)0x0030)
211#define SMCMR_SM_MASK ((ushort)0x0030)
212#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
213#define SMCMR_REVD SMCMR_PM_EVEN
214#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
215#define SMCMR_BS SMCMR_PEN
216#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
217#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
218#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
219
220/* SMC Event and Mask register.
221*/
222#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
223#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
224#define SMCM_TXE ((unsigned char)0x10)
225#define SMCM_BSY ((unsigned char)0x04)
226#define SMCM_TX ((unsigned char)0x02)
227#define SMCM_RX ((unsigned char)0x01)
228
229/* SCCs.
230*/
231#define SCC_GSMRH_IRP ((uint)0x00040000)
232#define SCC_GSMRH_GDE ((uint)0x00010000)
233#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
234#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
235#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
236#define SCC_GSMRH_REVD ((uint)0x00002000)
237#define SCC_GSMRH_TRX ((uint)0x00001000)
238#define SCC_GSMRH_TTX ((uint)0x00000800)
239#define SCC_GSMRH_CDP ((uint)0x00000400)
240#define SCC_GSMRH_CTSP ((uint)0x00000200)
241#define SCC_GSMRH_CDS ((uint)0x00000100)
242#define SCC_GSMRH_CTSS ((uint)0x00000080)
243#define SCC_GSMRH_TFL ((uint)0x00000040)
244#define SCC_GSMRH_RFW ((uint)0x00000020)
245#define SCC_GSMRH_TXSY ((uint)0x00000010)
246#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
247#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
248#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
249#define SCC_GSMRH_RTSM ((uint)0x00000002)
250#define SCC_GSMRH_RSYN ((uint)0x00000001)
251
252#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
253#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
254#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
255#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
256#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
257#define SCC_GSMRL_TCI ((uint)0x10000000)
258#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
259#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
260#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
261#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
262#define SCC_GSMRL_RINV ((uint)0x02000000)
263#define SCC_GSMRL_TINV ((uint)0x01000000)
264#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
265#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
266#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
267#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
268#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
269#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
270#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
271#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
272#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
273#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
274#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
275#define SCC_GSMRL_TEND ((uint)0x00040000)
276#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
277#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
278#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
279#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
280#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
281#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
282#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
283#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
284#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
285#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
286#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
287#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
288#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
289#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
290#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
291#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
292#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
293#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
294#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
295#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
296#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
297#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
298#define SCC_GSMRL_ENR ((uint)0x00000020)
299#define SCC_GSMRL_ENT ((uint)0x00000010)
300#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
301#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
302#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
303#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
304#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
305#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
306#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
307#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
308#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
309#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
310
311#define SCC_TODR_TOD ((ushort)0x8000)
312
313/* SCC Event and Mask register.
314*/
315#define SCCM_TXE ((unsigned char)0x10)
316#define SCCM_BSY ((unsigned char)0x04)
317#define SCCM_TX ((unsigned char)0x02)
318#define SCCM_RX ((unsigned char)0x01)
319
320typedef struct scc_param {
321 ushort scc_rbase; /* Rx Buffer descriptor base address */
322 ushort scc_tbase; /* Tx Buffer descriptor base address */
323 u_char scc_rfcr; /* Rx function code */
324 u_char scc_tfcr; /* Tx function code */
325 ushort scc_mrblr; /* Max receive buffer length */
326 uint scc_rstate; /* Internal */
327 uint scc_idp; /* Internal */
328 ushort scc_rbptr; /* Internal */
329 ushort scc_ibc; /* Internal */
330 uint scc_rxtmp; /* Internal */
331 uint scc_tstate; /* Internal */
332 uint scc_tdp; /* Internal */
333 ushort scc_tbptr; /* Internal */
334 ushort scc_tbc; /* Internal */
335 uint scc_txtmp; /* Internal */
336 uint scc_rcrc; /* Internal */
337 uint scc_tcrc; /* Internal */
338} sccp_t;
339
340/* CPM Ethernet through SCC1.
341 */
342typedef struct scc_enet {
343 sccp_t sen_genscc;
344 uint sen_cpres; /* Preset CRC */
345 uint sen_cmask; /* Constant mask for CRC */
346 uint sen_crcec; /* CRC Error counter */
347 uint sen_alec; /* alignment error counter */
348 uint sen_disfc; /* discard frame counter */
349 ushort sen_pads; /* Tx short frame pad character */
350 ushort sen_retlim; /* Retry limit threshold */
351 ushort sen_retcnt; /* Retry limit counter */
352 ushort sen_maxflr; /* maximum frame length register */
353 ushort sen_minflr; /* minimum frame length register */
354 ushort sen_maxd1; /* maximum DMA1 length */
355 ushort sen_maxd2; /* maximum DMA2 length */
356 ushort sen_maxd; /* Rx max DMA */
357 ushort sen_dmacnt; /* Rx DMA counter */
358 ushort sen_maxb; /* Max BD byte count */
359 ushort sen_gaddr1; /* Group address filter */
360 ushort sen_gaddr2;
361 ushort sen_gaddr3;
362 ushort sen_gaddr4;
363 uint sen_tbuf0data0; /* Save area 0 - current frame */
364 uint sen_tbuf0data1; /* Save area 1 - current frame */
365 uint sen_tbuf0rba; /* Internal */
366 uint sen_tbuf0crc; /* Internal */
367 ushort sen_tbuf0bcnt; /* Internal */
368 ushort sen_paddrh; /* physical address (MSB) */
369 ushort sen_paddrm;
370 ushort sen_paddrl; /* physical address (LSB) */
371 ushort sen_pper; /* persistence */
372 ushort sen_rfbdptr; /* Rx first BD pointer */
373 ushort sen_tfbdptr; /* Tx first BD pointer */
374 ushort sen_tlbdptr; /* Tx last BD pointer */
375 uint sen_tbuf1data0; /* Save area 0 - current frame */
376 uint sen_tbuf1data1; /* Save area 1 - current frame */
377 uint sen_tbuf1rba; /* Internal */
378 uint sen_tbuf1crc; /* Internal */
379 ushort sen_tbuf1bcnt; /* Internal */
380 ushort sen_txlen; /* Tx Frame length counter */
381 ushort sen_iaddr1; /* Individual address filter */
382 ushort sen_iaddr2;
383 ushort sen_iaddr3;
384 ushort sen_iaddr4;
385 ushort sen_boffcnt; /* Backoff counter */
386
387 /* NOTE: Some versions of the manual have the following items
388 * incorrectly documented. Below is the proper order.
389 */
390 ushort sen_taddrh; /* temp address (MSB) */
391 ushort sen_taddrm;
392 ushort sen_taddrl; /* temp address (LSB) */
393} scc_enet_t;
394
395
396/* SCC Event register as used by Ethernet.
397*/
398#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
399#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
400#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
401#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
402#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
403#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
404
405/* SCC Mode Register (PSMR) as used by Ethernet.
406*/
407#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
408#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
409#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
410#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
411#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
412#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
413#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
414#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
415#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
416#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
417#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
418#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
419#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
420
421/* SCC as UART
422*/
423typedef struct scc_uart {
424 sccp_t scc_genscc;
425 uint scc_res1; /* Reserved */
426 uint scc_res2; /* Reserved */
427 ushort scc_maxidl; /* Maximum idle chars */
428 ushort scc_idlc; /* temp idle counter */
429 ushort scc_brkcr; /* Break count register */
430 ushort scc_parec; /* receive parity error counter */
431 ushort scc_frmec; /* receive framing error counter */
432 ushort scc_nosec; /* receive noise counter */
433 ushort scc_brkec; /* receive break condition counter */
434 ushort scc_brkln; /* last received break length */
435 ushort scc_uaddr1; /* UART address character 1 */
436 ushort scc_uaddr2; /* UART address character 2 */
437 ushort scc_rtemp; /* Temp storage */
438 ushort scc_toseq; /* Transmit out of sequence char */
439 ushort scc_char1; /* control character 1 */
440 ushort scc_char2; /* control character 2 */
441 ushort scc_char3; /* control character 3 */
442 ushort scc_char4; /* control character 4 */
443 ushort scc_char5; /* control character 5 */
444 ushort scc_char6; /* control character 6 */
445 ushort scc_char7; /* control character 7 */
446 ushort scc_char8; /* control character 8 */
447 ushort scc_rccm; /* receive control character mask */
448 ushort scc_rccr; /* receive control character register */
449 ushort scc_rlbc; /* receive last break character */
450} scc_uart_t;
451
452/* SCC Event and Mask registers when it is used as a UART.
453*/
454#define UART_SCCM_GLR ((ushort)0x1000)
455#define UART_SCCM_GLT ((ushort)0x0800)
456#define UART_SCCM_AB ((ushort)0x0200)
457#define UART_SCCM_IDL ((ushort)0x0100)
458#define UART_SCCM_GRA ((ushort)0x0080)
459#define UART_SCCM_BRKE ((ushort)0x0040)
460#define UART_SCCM_BRKS ((ushort)0x0020)
461#define UART_SCCM_CCR ((ushort)0x0008)
462#define UART_SCCM_BSY ((ushort)0x0004)
463#define UART_SCCM_TX ((ushort)0x0002)
464#define UART_SCCM_RX ((ushort)0x0001)
465
466/* The SCC PSMR when used as a UART.
467*/
468#define SCU_PSMR_FLC ((ushort)0x8000)
469#define SCU_PSMR_SL ((ushort)0x4000)
470#define SCU_PSMR_CL ((ushort)0x3000)
471#define SCU_PSMR_UM ((ushort)0x0c00)
472#define SCU_PSMR_FRZ ((ushort)0x0200)
473#define SCU_PSMR_RZS ((ushort)0x0100)
474#define SCU_PSMR_SYN ((ushort)0x0080)
475#define SCU_PSMR_DRT ((ushort)0x0040)
476#define SCU_PSMR_PEN ((ushort)0x0010)
477#define SCU_PSMR_RPM ((ushort)0x000c)
478#define SCU_PSMR_REVP ((ushort)0x0008)
479#define SCU_PSMR_TPM ((ushort)0x0003)
480#define SCU_PSMR_TEVP ((ushort)0x0002)
481
482/* CPM Transparent mode SCC.
483 */
484typedef struct scc_trans {
485 sccp_t st_genscc;
486 uint st_cpres; /* Preset CRC */
487 uint st_cmask; /* Constant mask for CRC */
488} scc_trans_t;
489
490/* How about some FCCs.....
491*/
492#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
493#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
494#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
495#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
496#define FCC_GFMR_TCI ((uint)0x20000000)
497#define FCC_GFMR_TRX ((uint)0x10000000)
498#define FCC_GFMR_TTX ((uint)0x08000000)
499#define FCC_GFMR_TTX ((uint)0x08000000)
500#define FCC_GFMR_CDP ((uint)0x04000000)
501#define FCC_GFMR_CTSP ((uint)0x02000000)
502#define FCC_GFMR_CDS ((uint)0x01000000)
503#define FCC_GFMR_CTSS ((uint)0x00800000)
504#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
505#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
506#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
507#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
508#define FCC_GFMR_RTSM ((uint)0x00002000)
509#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
510#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
511#define FCC_GFMR_REVD ((uint)0x00000400)
512#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
513#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
514#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
515#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
516#define FCC_GFMR_ENR ((uint)0x00000020)
517#define FCC_GFMR_ENT ((uint)0x00000010)
518#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
519#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
520#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
521
522/* Generic FCC parameter ram.
523*/
524typedef struct fcc_param {
525 ushort fcc_riptr; /* Rx Internal temp pointer */
526 ushort fcc_tiptr; /* Tx Internal temp pointer */
527 ushort fcc_res1;
528 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
529 uint fcc_rstate; /* Upper byte is Func code, must be set */
530 uint fcc_rbase; /* Receive BD base */
531 ushort fcc_rbdstat; /* RxBD status */
532 ushort fcc_rbdlen; /* RxBD down counter */
533 uint fcc_rdptr; /* RxBD internal data pointer */
534 uint fcc_tstate; /* Upper byte is Func code, must be set */
535 uint fcc_tbase; /* Transmit BD base */
536 ushort fcc_tbdstat; /* TxBD status */
537 ushort fcc_tbdlen; /* TxBD down counter */
538 uint fcc_tdptr; /* TxBD internal data pointer */
539 uint fcc_rbptr; /* Rx BD Internal buf pointer */
540 uint fcc_tbptr; /* Tx BD Internal buf pointer */
541 uint fcc_rcrc; /* Rx temp CRC */
542 uint fcc_res2;
543 uint fcc_tcrc; /* Tx temp CRC */
544} fccp_t;
545
546
547/* Ethernet controller through FCC.
548*/
549typedef struct fcc_enet {
550 fccp_t fen_genfcc;
551 uint fen_statbuf; /* Internal status buffer */
552 uint fen_camptr; /* CAM address */
553 uint fen_cmask; /* Constant mask for CRC */
554 uint fen_cpres; /* Preset CRC */
555 uint fen_crcec; /* CRC Error counter */
556 uint fen_alec; /* alignment error counter */
557 uint fen_disfc; /* discard frame counter */
558 ushort fen_retlim; /* Retry limit */
559 ushort fen_retcnt; /* Retry counter */
560 ushort fen_pper; /* Persistence */
561 ushort fen_boffcnt; /* backoff counter */
562 uint fen_gaddrh; /* Group address filter, high 32-bits */
563 uint fen_gaddrl; /* Group address filter, low 32-bits */
564 ushort fen_tfcstat; /* out of sequence TxBD */
565 ushort fen_tfclen;
566 uint fen_tfcptr;
567 ushort fen_mflr; /* Maximum frame length (1518) */
568 ushort fen_paddrh; /* MAC address */
569 ushort fen_paddrm;
570 ushort fen_paddrl;
571 ushort fen_ibdcount; /* Internal BD counter */
572 ushort fen_ibdstart; /* Internal BD start pointer */
573 ushort fen_ibdend; /* Internal BD end pointer */
574 ushort fen_txlen; /* Internal Tx frame length counter */
575 uint fen_ibdbase[8]; /* Internal use */
576 uint fen_iaddrh; /* Individual address filter */
577 uint fen_iaddrl;
578 ushort fen_minflr; /* Minimum frame length (64) */
579 ushort fen_taddrh; /* Filter transfer MAC address */
580 ushort fen_taddrm;
581 ushort fen_taddrl;
582 ushort fen_padptr; /* Pointer to pad byte buffer */
583 ushort fen_cftype; /* control frame type */
584 ushort fen_cfrange; /* control frame range */
585 ushort fen_maxb; /* maximum BD count */
586 ushort fen_maxd1; /* Max DMA1 length (1520) */
587 ushort fen_maxd2; /* Max DMA2 length (1520) */
588 ushort fen_maxd; /* internal max DMA count */
589 ushort fen_dmacnt; /* internal DMA counter */
590 uint fen_octc; /* Total octect counter */
591 uint fen_colc; /* Total collision counter */
592 uint fen_broc; /* Total broadcast packet counter */
593 uint fen_mulc; /* Total multicast packet count */
594 uint fen_uspc; /* Total packets < 64 bytes */
595 uint fen_frgc; /* Total packets < 64 bytes with errors */
596 uint fen_ospc; /* Total packets > 1518 */
597 uint fen_jbrc; /* Total packets > 1518 with errors */
598 uint fen_p64c; /* Total packets == 64 bytes */
599 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
600 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
601 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
602 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
603 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
604 uint fen_cambuf; /* Internal CAM buffer poiner */
605 ushort fen_rfthr; /* Received frames threshold */
606 ushort fen_rfcnt; /* Received frames count */
607} fcc_enet_t;
608
609/* FCC Event/Mask register as used by Ethernet.
610*/
611#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
612#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
613#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
614#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
615#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
616#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
617#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
618#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
619
620/* FCC Mode Register (FPSMR) as used by Ethernet.
621*/
622#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
623#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
624#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
625#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
626#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
627#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
628#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
629#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
630#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
631#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
632#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
633#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
634#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
635
636/* IIC parameter RAM.
637*/
638typedef struct iic {
639 ushort iic_rbase; /* Rx Buffer descriptor base address */
640 ushort iic_tbase; /* Tx Buffer descriptor base address */
641 u_char iic_rfcr; /* Rx function code */
642 u_char iic_tfcr; /* Tx function code */
643 ushort iic_mrblr; /* Max receive buffer length */
644 uint iic_rstate; /* Internal */
645 uint iic_rdp; /* Internal */
646 ushort iic_rbptr; /* Internal */
647 ushort iic_rbc; /* Internal */
648 uint iic_rxtmp; /* Internal */
649 uint iic_tstate; /* Internal */
650 uint iic_tdp; /* Internal */
651 ushort iic_tbptr; /* Internal */
652 ushort iic_tbc; /* Internal */
653 uint iic_txtmp; /* Internal */
654} iic_t;
655
656/* SPI parameter RAM.
657*/
658typedef struct spi {
659 ushort spi_rbase; /* Rx Buffer descriptor base address */
660 ushort spi_tbase; /* Tx Buffer descriptor base address */
661 u_char spi_rfcr; /* Rx function code */
662 u_char spi_tfcr; /* Tx function code */
663 ushort spi_mrblr; /* Max receive buffer length */
664 uint spi_rstate; /* Internal */
665 uint spi_rdp; /* Internal */
666 ushort spi_rbptr; /* Internal */
667 ushort spi_rbc; /* Internal */
668 uint spi_rxtmp; /* Internal */
669 uint spi_tstate; /* Internal */
670 uint spi_tdp; /* Internal */
671 ushort spi_tbptr; /* Internal */
672 ushort spi_tbc; /* Internal */
673 uint spi_txtmp; /* Internal */
674 uint spi_res; /* Tx temp. */
675 uint spi_res1[4]; /* SDMA temp. */
676} spi_t;
677
678/* SPI Mode register.
679*/
680#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
681#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
682#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
683#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
684#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
685#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
686#define SPMODE_EN ((ushort)0x0100) /* Enable */
687#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
688#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
689
690#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
691#define SPMODE_PM(x) ((x) &0xF)
692
693#define SPI_EB ((u_char)0x10) /* big endian byte order */
694
695/* IDMA parameter RAM
696*/
697typedef struct idma {
698 ushort ibase; /* IDMA buffer descriptor table base address */
699 ushort dcm; /* DMA channel mode */
700 ushort ibdptr; /* IDMA current buffer descriptor pointer */
701 ushort dpr_buf; /* IDMA transfer buffer base address */
702 ushort buf_inv; /* internal buffer inventory */
703 ushort ss_max; /* steady-state maximum transfer size */
704 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
705 ushort sts; /* source transfer size */
706 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
707 ushort seob; /* source end of burst */
708 ushort deob; /* destination end of burst */
709 ushort dts; /* destination transfer size */
710 ushort ret_add; /* return address when working in ERM=1 mode */
711 ushort res0; /* reserved */
712 uint bd_cnt; /* internal byte count */
713 uint s_ptr; /* source internal data pointer */
714 uint d_ptr; /* destination internal data pointer */
715 uint istate; /* internal state */
716 u_char res1[20]; /* pad to 64-byte length */
717} idma_t;
718
719/* DMA channel mode bit fields
720*/
721#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
722#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
723#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
724#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
725#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
726#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
727#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
728#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
729#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
730#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
731#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
732#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
733#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
734#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
735#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
736#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
737#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
738#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
739
740/* IDMA Buffer Descriptors
741*/
742typedef struct idma_bd {
743 uint flags;
744 uint len; /* data length */
745 uint src; /* source data buffer pointer */
746 uint dst; /* destination data buffer pointer */
747} idma_bd_t;
748
749/* IDMA buffer descriptor flag bit fields
750*/
751#define IDMA_BD_V ((uint)0x80000000) /* valid */
752#define IDMA_BD_W ((uint)0x20000000) /* wrap */
753#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
754#define IDMA_BD_L ((uint)0x08000000) /* last */
755#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
756#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
757#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
758#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
759#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
760#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
761#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
762#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
763#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
764#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
765#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
766
767/* per-channel IDMA registers
768*/
769typedef struct im_idma {
770 u_char idsr; /* IDMAn event status register */
771 u_char res0[3];
772 u_char idmr; /* IDMAn event mask register */
773 u_char res1[3];
774} im_idma_t;
775
776/* IDMA event register bit fields
777*/
778#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
779#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
780#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
781#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
782
783/* RISC Controller Configuration Register (RCCR) bit fields
784*/
785#define RCCR_TIME ((uint)0x80000000) /* timer enable */
786#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
787#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
788#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
789#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
790#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
791#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
792#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
793#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
794#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
795#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
796#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
797#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
798#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
799#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
800#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
801#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
802#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
803#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
804#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
805#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
806#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
807#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
808#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
809#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
810#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
811#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
812#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
813#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
814#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
815#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
816#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
817#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
818#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
819#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
820#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
821#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
822#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
823
824/*-----------------------------------------------------------------------
825 * CMXFCR - CMX FCC Clock Route Register
826 */
827#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
828#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
829#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
830#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
831#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
832#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
833#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
834#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
835#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
836
837#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
838#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
839#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
840#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
841#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
842#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
843#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
844#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
845
846#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
847#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
848#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
849#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
850#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
851#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
852#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
853#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
854
855#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
856#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
857#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
858#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
859#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
860#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
861#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
862#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
863
864#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
865#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
866#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
867#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
868#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
869#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
870#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
871#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
872
873#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
874#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
875#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
876#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
877#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
878#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
879#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
880#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
881
882#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
883#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
884#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
885#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
886#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
887#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
888#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
889#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
890
891/*-----------------------------------------------------------------------
892 * CMXSCR - CMX SCC Clock Route Register
893 */
894#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
895#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
896#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
897#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
898#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
899#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
900#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
901#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
902#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
903#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
904#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
905#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
906#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
907#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
908#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
909#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
910
911#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
912#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
913#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
914#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
915#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
916#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
917#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
918#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
919
920#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
921#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
922#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
923#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
924#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
925#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
926#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
927#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
928
929#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
930#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
931#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
932#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
933#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
934#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
935#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
936#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
937
938#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
939#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
940#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
941#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
942#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
943#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
944#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
945#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
946
947#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
948#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
949#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
950#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
951#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
952#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
953#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
954#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
955
956#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
957#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
958#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
959#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
960#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
961#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
962#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
963#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
964
965#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
966#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
967#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
968#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
969#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
970#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
971#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
972#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
973
974#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
975#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
976#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
977#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
978#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
979#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
980#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
981#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
982
983/*-----------------------------------------------------------------------
984 * SIUMCR - SIU Module Configuration Register 4-31
985 */
986#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
987#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
988#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
989#define SIUMCR_CDIS 0x10000000 /* Core Disable */
990#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
991#define SIUMCR_DPPC01 0x04000000 /* - " - */
992#define SIUMCR_DPPC10 0x08000000 /* - " - */
993#define SIUMCR_DPPC11 0x0c000000 /* - " - */
994#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
995#define SIUMCR_L2CPC01 0x01000000 /* - " - */
996#define SIUMCR_L2CPC10 0x02000000 /* - " - */
997#define SIUMCR_L2CPC11 0x03000000 /* - " - */
998#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
999#define SIUMCR_LBPC01 0x00400000 /* - " - */
1000#define SIUMCR_LBPC10 0x00800000 /* - " - */
1001#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1002#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1003#define SIUMCR_APPC01 0x00100000 /* - " - */
1004#define SIUMCR_APPC10 0x00200000 /* - " - */
1005#define SIUMCR_APPC11 0x00300000 /* - " - */
1006#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1007#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1008#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1009#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1010#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1011#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1012#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1013#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1014#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1015#define SIUMCR_MMR01 0x00004000 /* - " - */
1016#define SIUMCR_MMR10 0x00008000 /* - " - */
1017#define SIUMCR_MMR11 0x0000c000 /* - " - */
1018#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1019
1020/*-----------------------------------------------------------------------
1021 * SCCR - System Clock Control Register 9-8
1022*/
1023#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1024#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1025#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1026#define SCCR_PCIDF_SHIFT 3
1027
1028#ifndef CPM_IMMR_OFFSET
1029#define CPM_IMMR_OFFSET 0x101a8
1030#endif
1031
1032#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1033
1034/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1035 * in order to use clock-computing stuff below for the FCC x
1036 */
1037
1038/* Automatically generates register configurations */
1039#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1040
1041#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1042#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1043#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1044#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1045#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1046#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1047
1048#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1049#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1050#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1051#define CMX1_CLK_MASK ((uint)0xff000000)
1052
1053#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1054#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1055#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1056#define CMX2_CLK_MASK ((uint)0x00ff0000)
1057
1058#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1059#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1060#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1061#define CMX3_CLK_MASK ((uint)0x0000ff00)
1062
1063#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1064#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1065
1066#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1067
1068/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1069 * but there is little variation among the choices.
1070 */
1071#define PA1_COL 0x00000001U
1072#define PA1_CRS 0x00000002U
1073#define PA1_TXER 0x00000004U
1074#define PA1_TXEN 0x00000008U
1075#define PA1_RXDV 0x00000010U
1076#define PA1_RXER 0x00000020U
1077#define PA1_TXDAT 0x00003c00U
1078#define PA1_RXDAT 0x0003c000U
1079#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1080#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1081 PA1_RXDV | PA1_RXER)
1082#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1083#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1084
1085
1086/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1087 * but there is little variation among the choices.
1088 */
1089#define PB2_TXER 0x00000001U
1090#define PB2_RXDV 0x00000002U
1091#define PB2_TXEN 0x00000004U
1092#define PB2_RXER 0x00000008U
1093#define PB2_COL 0x00000010U
1094#define PB2_CRS 0x00000020U
1095#define PB2_TXDAT 0x000003c0U
1096#define PB2_RXDAT 0x00003c00U
1097#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1098 PB2_RXER | PB2_RXDV | PB2_TXER)
1099#define PB2_PSORB1 (PB2_TXEN)
1100#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1101#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1102
1103
1104/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1105 * but there is little variation among the choices.
1106 */
1107#define PB3_RXDV 0x00004000U
1108#define PB3_RXER 0x00008000U
1109#define PB3_TXER 0x00010000U
1110#define PB3_TXEN 0x00020000U
1111#define PB3_COL 0x00040000U
1112#define PB3_CRS 0x00080000U
1113#define PB3_TXDAT 0x0f000000U
1114#define PC3_TXDAT 0x00000010U
1115#define PB3_RXDAT 0x00f00000U
1116#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1117 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1118#define PB3_PSORB1 0
1119#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1120#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1121#define PC3_DIRC1 (PC3_TXDAT)
1122
1123/* Handy macro to specify mem for FCCs*/
1124#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1125#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1126#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1127#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1128
1129/* Clocks and GRG's */
1130
1131enum cpm_clk_dir {
1132 CPM_CLK_RX,
1133 CPM_CLK_TX,
1134 CPM_CLK_RTX
1135};
1136
1137enum cpm_clk_target {
1138 CPM_CLK_SCC1,
1139 CPM_CLK_SCC2,
1140 CPM_CLK_SCC3,
1141 CPM_CLK_SCC4,
1142 CPM_CLK_FCC1,
1143 CPM_CLK_FCC2,
1144 CPM_CLK_FCC3,
1145 CPM_CLK_SMC1,
1146 CPM_CLK_SMC2,
1147};
1148
1149enum cpm_clk {
1150 CPM_CLK_NONE = 0,
1151 CPM_BRG1, /* Baud Rate Generator 1 */
1152 CPM_BRG2, /* Baud Rate Generator 2 */
1153 CPM_BRG3, /* Baud Rate Generator 3 */
1154 CPM_BRG4, /* Baud Rate Generator 4 */
1155 CPM_BRG5, /* Baud Rate Generator 5 */
1156 CPM_BRG6, /* Baud Rate Generator 6 */
1157 CPM_BRG7, /* Baud Rate Generator 7 */
1158 CPM_BRG8, /* Baud Rate Generator 8 */
1159 CPM_CLK1, /* Clock 1 */
1160 CPM_CLK2, /* Clock 2 */
1161 CPM_CLK3, /* Clock 3 */
1162 CPM_CLK4, /* Clock 4 */
1163 CPM_CLK5, /* Clock 5 */
1164 CPM_CLK6, /* Clock 6 */
1165 CPM_CLK7, /* Clock 7 */
1166 CPM_CLK8, /* Clock 8 */
1167 CPM_CLK9, /* Clock 9 */
1168 CPM_CLK10, /* Clock 10 */
1169 CPM_CLK11, /* Clock 11 */
1170 CPM_CLK12, /* Clock 12 */
1171 CPM_CLK13, /* Clock 13 */
1172 CPM_CLK14, /* Clock 14 */
1173 CPM_CLK15, /* Clock 15 */
1174 CPM_CLK16, /* Clock 16 */
1175 CPM_CLK17, /* Clock 17 */
1176 CPM_CLK18, /* Clock 18 */
1177 CPM_CLK19, /* Clock 19 */
1178 CPM_CLK20, /* Clock 20 */
1179 CPM_CLK_DUMMY
1180};
1181
1182extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1183extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1184
1185#define CPM_PIN_INPUT 0
1186#define CPM_PIN_OUTPUT 1
1187#define CPM_PIN_PRIMARY 0
1188#define CPM_PIN_SECONDARY 2
1189#define CPM_PIN_GPIO 4
1190#define CPM_PIN_OPENDRAIN 8
1191
1192void cpm2_set_pin(int port, int pin, int flags);
1193
1194#endif /* __CPM2__ */
1195#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
new file mode 100644
index 000000000000..ef8a248dfd55
--- /dev/null
+++ b/arch/powerpc/include/asm/cputable.h
@@ -0,0 +1,514 @@
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
15#define PPC_FEATURE_NO_TB 0x00100000
16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
20#define PPC_FEATURE_BOOKE 0x00008000
21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
23#define PPC_FEATURE_ARCH_2_05 0x00001000
24#define PPC_FEATURE_PA6T 0x00000800
25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
27#define PPC_FEATURE_ARCH_2_06 0x00000100
28#define PPC_FEATURE_HAS_VSX 0x00000080
29
30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
36#ifdef __KERNEL__
37
38#include <asm/asm-compat.h>
39#include <asm/feature-fixups.h>
40
41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
47
48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
49typedef void (*cpu_restore_t)(void);
50
51enum powerpc_oprofile_type {
52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
56 PPC_OPROFILE_FSL_EMB = 4,
57 PPC_OPROFILE_CELL = 5,
58 PPC_OPROFILE_PA6T = 6,
59};
60
61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
65};
66
67struct pt_regs;
68
69extern int machine_check_generic(struct pt_regs *regs);
70extern int machine_check_4xx(struct pt_regs *regs);
71extern int machine_check_440A(struct pt_regs *regs);
72extern int machine_check_e500(struct pt_regs *regs);
73extern int machine_check_e200(struct pt_regs *regs);
74
75/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
76struct cpu_spec {
77 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
78 unsigned int pvr_mask;
79 unsigned int pvr_value;
80
81 char *cpu_name;
82 unsigned long cpu_features; /* Kernel features */
83 unsigned int cpu_user_features; /* Userland features */
84
85 /* cache line sizes */
86 unsigned int icache_bsize;
87 unsigned int dcache_bsize;
88
89 /* number of performance monitor counters */
90 unsigned int num_pmcs;
91 enum powerpc_pmc_type pmc_type;
92
93 /* this is called to initialize various CPU bits like L1 cache,
94 * BHT, SPD, etc... from head.S before branching to identify_machine
95 */
96 cpu_setup_t cpu_setup;
97 /* Used to restore cpu setup on secondary processors and at resume */
98 cpu_restore_t cpu_restore;
99
100 /* Used by oprofile userspace to select the right counters */
101 char *oprofile_cpu_type;
102
103 /* Processor specific oprofile operations */
104 enum powerpc_oprofile_type oprofile_type;
105
106 /* Bit locations inside the mmcra change */
107 unsigned long oprofile_mmcra_sihv;
108 unsigned long oprofile_mmcra_sipr;
109
110 /* Bits to clear during an oprofile exception */
111 unsigned long oprofile_mmcra_clear;
112
113 /* Name of processor class, for the ELF AT_PLATFORM entry */
114 char *platform;
115
116 /* Processor specific machine check handling. Return negative
117 * if the error is fatal, 1 if it was fully recovered and 0 to
118 * pass up (not CPU originated) */
119 int (*machine_check)(struct pt_regs *regs);
120};
121
122extern struct cpu_spec *cur_cpu_spec;
123
124extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
125
126extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
127extern void do_feature_fixups(unsigned long value, void *fixup_start,
128 void *fixup_end);
129
130extern const char *powerpc_base_platform;
131
132#endif /* __ASSEMBLY__ */
133
134/* CPU kernel features */
135
136/* Retain the 32b definitions all use bottom half of word */
137#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
138#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
139#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
140#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
141#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
142#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
143#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
144#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
145#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
146#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
147#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
148#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
149#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
150#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
151#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
152#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
153#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
154#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
155#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
156#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
157#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
158#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
159#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
160#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
161#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
162#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
163#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
164#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
165
166/*
167 * Add the 64-bit processor unique features in the top half of the word;
168 * on 32-bit, make the names available but defined to be 0.
169 */
170#ifdef __powerpc64__
171#define LONG_ASM_CONST(x) ASM_CONST(x)
172#else
173#define LONG_ASM_CONST(x) 0
174#endif
175
176#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
177#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
178#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
179#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
180#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
181#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
182#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
183#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
184#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
185#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
186#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
187#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
188#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
189#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
190#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
191#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
192#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
194#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
195
196#ifndef __ASSEMBLY__
197
198#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
199 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
200 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
201
202/* We only set the altivec features if the kernel was compiled with altivec
203 * support
204 */
205#ifdef CONFIG_ALTIVEC
206#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
207#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
208#else
209#define CPU_FTR_ALTIVEC_COMP 0
210#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
211#endif
212
213/* We only set the VSX features if the kernel was compiled with VSX
214 * support
215 */
216#ifdef CONFIG_VSX
217#define CPU_FTR_VSX_COMP CPU_FTR_VSX
218#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
219#else
220#define CPU_FTR_VSX_COMP 0
221#define PPC_FEATURE_HAS_VSX_COMP 0
222#endif
223
224/* We only set the spe features if the kernel was compiled with spe
225 * support
226 */
227#ifdef CONFIG_SPE
228#define CPU_FTR_SPE_COMP CPU_FTR_SPE
229#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
230#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
231#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
232#else
233#define CPU_FTR_SPE_COMP 0
234#define PPC_FEATURE_HAS_SPE_COMP 0
235#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
236#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
237#endif
238
239/* We need to mark all pages as being coherent if we're SMP or we have a
240 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
241 * require it for PCI "streaming/prefetch" to work properly.
242 */
243#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
244 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
245#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
246#else
247#define CPU_FTR_COMMON 0
248#endif
249
250/* The powersave features NAP & DOZE seems to confuse BDI when
251 debugging. So if a BDI is used, disable theses
252 */
253#ifndef CONFIG_BDI_SWITCH
254#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
255#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
256#else
257#define CPU_FTR_MAYBE_CAN_DOZE 0
258#define CPU_FTR_MAYBE_CAN_NAP 0
259#endif
260
261#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
262 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
263 !defined(CONFIG_BOOKE))
264
265#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
266 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
267#define CPU_FTRS_603 (CPU_FTR_COMMON | \
268 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
269 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
270#define CPU_FTRS_604 (CPU_FTR_COMMON | \
271 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
272#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
274 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
275#define CPU_FTRS_740 (CPU_FTR_COMMON | \
276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
277 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
278 CPU_FTR_PPC_LE)
279#define CPU_FTRS_750 (CPU_FTR_COMMON | \
280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
281 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
282 CPU_FTR_PPC_LE)
283#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
284#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
285#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
286#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
287 CPU_FTR_HAS_HIGH_BATS)
288#define CPU_FTRS_750GX (CPU_FTRS_750FX)
289#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
291 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
293#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
295 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
297#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
298 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
301#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
302 CPU_FTR_USE_TB | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
304 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
305 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
306 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
307#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
310 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
311 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
312#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
313 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
314 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
317#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
320 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
322 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
323#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
324 CPU_FTR_USE_TB | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
334 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
335 CPU_FTR_NEED_PAIRED_STWCX)
336#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
337 CPU_FTR_USE_TB | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
340 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
342#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
343 CPU_FTR_USE_TB | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
346 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
348#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
349 CPU_FTR_USE_TB | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
351 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
352 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
353 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
354#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
355 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
356#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
358#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
359 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
360 CPU_FTR_COMMON)
361#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
362 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
363 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
364#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
365 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
366#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
367#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
368#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
369#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
370 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
371 CPU_FTR_UNIFIED_ID_CACHE)
372#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
373 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
374#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
375 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
376 CPU_FTR_NODSISRALIGN)
377#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
378 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
379 CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
380#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
381
382/* 64-bit CPUs */
383#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
384 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
385#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
386 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
387 CPU_FTR_MMCRA | CPU_FTR_CTRL)
388#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
389 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
390 CPU_FTR_MMCRA)
391#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
392 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
393 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
394#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
395 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
396 CPU_FTR_MMCRA | CPU_FTR_SMT | \
397 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
398 CPU_FTR_PURR)
399#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
400 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
401 CPU_FTR_MMCRA | CPU_FTR_SMT | \
402 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
403 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
404 CPU_FTR_DSCR)
405#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
406 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
410 CPU_FTR_DSCR | CPU_FTR_SAO)
411#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
412 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
413 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
415#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
416 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
418 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
419#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
420 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
421
422#ifdef __powerpc64__
423#define CPU_FTRS_POSSIBLE \
424 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
425 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
426 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
427 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
428#else
429enum {
430 CPU_FTRS_POSSIBLE =
431#if CLASSIC_PPC
432 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
433 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
434 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
435 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
436 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
437 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
438 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
439 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
440 CPU_FTRS_CLASSIC32 |
441#else
442 CPU_FTRS_GENERIC_32 |
443#endif
444#ifdef CONFIG_8xx
445 CPU_FTRS_8XX |
446#endif
447#ifdef CONFIG_40x
448 CPU_FTRS_40X |
449#endif
450#ifdef CONFIG_44x
451 CPU_FTRS_44X |
452#endif
453#ifdef CONFIG_E200
454 CPU_FTRS_E200 |
455#endif
456#ifdef CONFIG_E500
457 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
458#endif
459 0,
460};
461#endif /* __powerpc64__ */
462
463#ifdef __powerpc64__
464#define CPU_FTRS_ALWAYS \
465 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
466 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
467 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
468#else
469enum {
470 CPU_FTRS_ALWAYS =
471#if CLASSIC_PPC
472 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
473 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
474 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
475 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
476 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
477 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
478 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
479 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
480 CPU_FTRS_CLASSIC32 &
481#else
482 CPU_FTRS_GENERIC_32 &
483#endif
484#ifdef CONFIG_8xx
485 CPU_FTRS_8XX &
486#endif
487#ifdef CONFIG_40x
488 CPU_FTRS_40X &
489#endif
490#ifdef CONFIG_44x
491 CPU_FTRS_44X &
492#endif
493#ifdef CONFIG_E200
494 CPU_FTRS_E200 &
495#endif
496#ifdef CONFIG_E500
497 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
498#endif
499 CPU_FTRS_POSSIBLE,
500};
501#endif /* __powerpc64__ */
502
503static inline int cpu_has_feature(unsigned long feature)
504{
505 return (CPU_FTRS_ALWAYS & feature) ||
506 (CPU_FTRS_POSSIBLE
507 & cur_cpu_spec->cpu_features
508 & feature);
509}
510
511#endif /* !__ASSEMBLY__ */
512
513#endif /* __KERNEL__ */
514#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
new file mode 100644
index 000000000000..fb11b0c459b8
--- /dev/null
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -0,0 +1,71 @@
1#ifndef _ASM_POWERPC_CPUTHREADS_H
2#define _ASM_POWERPC_CPUTHREADS_H
3
4#include <linux/cpumask.h>
5
6/*
7 * Mapping of threads to cores
8 */
9
10#ifdef CONFIG_SMP
11extern int threads_per_core;
12extern int threads_shift;
13extern cpumask_t threads_core_mask;
14#else
15#define threads_per_core 1
16#define threads_shift 0
17#define threads_core_mask (CPU_MASK_CPU0)
18#endif
19
20/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
21 * hit by the argument
22 *
23 * @threads: a cpumask of threads
24 *
25 * This function returns a cpumask which will have one "cpu" (or thread)
26 * bit set for each core that has at least one thread set in the argument.
27 *
28 * This can typically be used for things like IPI for tlb invalidations
29 * since those need to be done only once per core/TLB
30 */
31static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
32{
33 cpumask_t tmp, res;
34 int i;
35
36 res = CPU_MASK_NONE;
37 for (i = 0; i < NR_CPUS; i += threads_per_core) {
38 cpus_shift_left(tmp, threads_core_mask, i);
39 if (cpus_intersects(threads, tmp))
40 cpu_set(i, res);
41 }
42 return res;
43}
44
45static inline int cpu_nr_cores(void)
46{
47 return NR_CPUS >> threads_shift;
48}
49
50static inline cpumask_t cpu_online_cores_map(void)
51{
52 return cpu_thread_mask_to_cores(cpu_online_map);
53}
54
55static inline int cpu_thread_to_core(int cpu)
56{
57 return cpu >> threads_shift;
58}
59
60static inline int cpu_thread_in_core(int cpu)
61{
62 return cpu & (threads_per_core - 1);
63}
64
65static inline int cpu_first_thread_in_core(int cpu)
66{
67 return cpu & ~(threads_per_core - 1);
68}
69
70#endif /* _ASM_POWERPC_CPUTHREADS_H */
71
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
new file mode 100644
index 000000000000..f42e623030ee
--- /dev/null
+++ b/arch/powerpc/include/asm/cputime.h
@@ -0,0 +1,235 @@
1/*
2 * Definitions for measuring cputime on powerpc machines.
3 *
4 * Copyright (C) 2006 Paul Mackerras, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in
12 * the same units as the timebase. Otherwise we measure cpu time
13 * in jiffies using the generic definitions.
14 */
15
16#ifndef __POWERPC_CPUTIME_H
17#define __POWERPC_CPUTIME_H
18
19#ifndef CONFIG_VIRT_CPU_ACCOUNTING
20#include <asm-generic/cputime.h>
21#else
22
23#include <linux/types.h>
24#include <linux/time.h>
25#include <asm/div64.h>
26#include <asm/time.h>
27#include <asm/param.h>
28
29typedef u64 cputime_t;
30typedef u64 cputime64_t;
31
32#define cputime_zero ((cputime_t)0)
33#define cputime_max ((~((cputime_t)0) >> 1) - 1)
34#define cputime_add(__a, __b) ((__a) + (__b))
35#define cputime_sub(__a, __b) ((__a) - (__b))
36#define cputime_div(__a, __n) ((__a) / (__n))
37#define cputime_halve(__a) ((__a) >> 1)
38#define cputime_eq(__a, __b) ((__a) == (__b))
39#define cputime_gt(__a, __b) ((__a) > (__b))
40#define cputime_ge(__a, __b) ((__a) >= (__b))
41#define cputime_lt(__a, __b) ((__a) < (__b))
42#define cputime_le(__a, __b) ((__a) <= (__b))
43
44#define cputime64_zero ((cputime64_t)0)
45#define cputime64_add(__a, __b) ((__a) + (__b))
46#define cputime64_sub(__a, __b) ((__a) - (__b))
47#define cputime_to_cputime64(__ct) (__ct)
48
49#ifdef __KERNEL__
50
51/*
52 * Convert cputime <-> jiffies
53 */
54extern u64 __cputime_jiffies_factor;
55DECLARE_PER_CPU(unsigned long, cputime_last_delta);
56DECLARE_PER_CPU(unsigned long, cputime_scaled_last_delta);
57
58static inline unsigned long cputime_to_jiffies(const cputime_t ct)
59{
60 return mulhdu(ct, __cputime_jiffies_factor);
61}
62
63/* Estimate the scaled cputime by scaling the real cputime based on
64 * the last scaled to real ratio */
65static inline cputime_t cputime_to_scaled(const cputime_t ct)
66{
67 if (cpu_has_feature(CPU_FTR_SPURR) &&
68 per_cpu(cputime_last_delta, smp_processor_id()))
69 return ct *
70 per_cpu(cputime_scaled_last_delta, smp_processor_id())/
71 per_cpu(cputime_last_delta, smp_processor_id());
72 return ct;
73}
74
75static inline cputime_t jiffies_to_cputime(const unsigned long jif)
76{
77 cputime_t ct;
78 unsigned long sec;
79
80 /* have to be a little careful about overflow */
81 ct = jif % HZ;
82 sec = jif / HZ;
83 if (ct) {
84 ct *= tb_ticks_per_sec;
85 do_div(ct, HZ);
86 }
87 if (sec)
88 ct += (cputime_t) sec * tb_ticks_per_sec;
89 return ct;
90}
91
92static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
93{
94 cputime_t ct;
95 u64 sec;
96
97 /* have to be a little careful about overflow */
98 ct = jif % HZ;
99 sec = jif / HZ;
100 if (ct) {
101 ct *= tb_ticks_per_sec;
102 do_div(ct, HZ);
103 }
104 if (sec)
105 ct += (cputime_t) sec * tb_ticks_per_sec;
106 return ct;
107}
108
109static inline u64 cputime64_to_jiffies64(const cputime_t ct)
110{
111 return mulhdu(ct, __cputime_jiffies_factor);
112}
113
114/*
115 * Convert cputime <-> milliseconds
116 */
117extern u64 __cputime_msec_factor;
118
119static inline unsigned long cputime_to_msecs(const cputime_t ct)
120{
121 return mulhdu(ct, __cputime_msec_factor);
122}
123
124static inline cputime_t msecs_to_cputime(const unsigned long ms)
125{
126 cputime_t ct;
127 unsigned long sec;
128
129 /* have to be a little careful about overflow */
130 ct = ms % 1000;
131 sec = ms / 1000;
132 if (ct) {
133 ct *= tb_ticks_per_sec;
134 do_div(ct, 1000);
135 }
136 if (sec)
137 ct += (cputime_t) sec * tb_ticks_per_sec;
138 return ct;
139}
140
141/*
142 * Convert cputime <-> seconds
143 */
144extern u64 __cputime_sec_factor;
145
146static inline unsigned long cputime_to_secs(const cputime_t ct)
147{
148 return mulhdu(ct, __cputime_sec_factor);
149}
150
151static inline cputime_t secs_to_cputime(const unsigned long sec)
152{
153 return (cputime_t) sec * tb_ticks_per_sec;
154}
155
156/*
157 * Convert cputime <-> timespec
158 */
159static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
160{
161 u64 x = ct;
162 unsigned int frac;
163
164 frac = do_div(x, tb_ticks_per_sec);
165 p->tv_sec = x;
166 x = (u64) frac * 1000000000;
167 do_div(x, tb_ticks_per_sec);
168 p->tv_nsec = x;
169}
170
171static inline cputime_t timespec_to_cputime(const struct timespec *p)
172{
173 cputime_t ct;
174
175 ct = (u64) p->tv_nsec * tb_ticks_per_sec;
176 do_div(ct, 1000000000);
177 return ct + (u64) p->tv_sec * tb_ticks_per_sec;
178}
179
180/*
181 * Convert cputime <-> timeval
182 */
183static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
184{
185 u64 x = ct;
186 unsigned int frac;
187
188 frac = do_div(x, tb_ticks_per_sec);
189 p->tv_sec = x;
190 x = (u64) frac * 1000000;
191 do_div(x, tb_ticks_per_sec);
192 p->tv_usec = x;
193}
194
195static inline cputime_t timeval_to_cputime(const struct timeval *p)
196{
197 cputime_t ct;
198
199 ct = (u64) p->tv_usec * tb_ticks_per_sec;
200 do_div(ct, 1000000);
201 return ct + (u64) p->tv_sec * tb_ticks_per_sec;
202}
203
204/*
205 * Convert cputime <-> clock_t (units of 1/USER_HZ seconds)
206 */
207extern u64 __cputime_clockt_factor;
208
209static inline unsigned long cputime_to_clock_t(const cputime_t ct)
210{
211 return mulhdu(ct, __cputime_clockt_factor);
212}
213
214static inline cputime_t clock_t_to_cputime(const unsigned long clk)
215{
216 cputime_t ct;
217 unsigned long sec;
218
219 /* have to be a little careful about overflow */
220 ct = clk % USER_HZ;
221 sec = clk / USER_HZ;
222 if (ct) {
223 ct *= tb_ticks_per_sec;
224 do_div(ct, USER_HZ);
225 }
226 if (sec)
227 ct += (cputime_t) sec * tb_ticks_per_sec;
228 return ct;
229}
230
231#define cputime64_to_clock_t(ct) cputime_to_clock_t((cputime_t)(ct))
232
233#endif /* __KERNEL__ */
234#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
235#endif /* __POWERPC_CPUTIME_H */
diff --git a/arch/powerpc/include/asm/current.h b/arch/powerpc/include/asm/current.h
new file mode 100644
index 000000000000..e2c7f06931e7
--- /dev/null
+++ b/arch/powerpc/include/asm/current.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_POWERPC_CURRENT_H
2#define _ASM_POWERPC_CURRENT_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12struct task_struct;
13
14#ifdef __powerpc64__
15#include <linux/stddef.h>
16#include <asm/paca.h>
17
18static inline struct task_struct *get_current(void)
19{
20 struct task_struct *task;
21
22 __asm__ __volatile__("ld %0,%1(13)"
23 : "=r" (task)
24 : "i" (offsetof(struct paca_struct, __current)));
25
26 return task;
27}
28#define current get_current()
29
30#else
31
32/*
33 * We keep `current' in r2 for speed.
34 */
35register struct task_struct *current asm ("r2");
36
37#endif
38
39#endif /* __KERNEL__ */
40#endif /* _ASM_POWERPC_CURRENT_H */
diff --git a/arch/powerpc/include/asm/dbdma.h b/arch/powerpc/include/asm/dbdma.h
new file mode 100644
index 000000000000..e23f07e73cb3
--- /dev/null
+++ b/arch/powerpc/include/asm/dbdma.h
@@ -0,0 +1,108 @@
1/*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#ifdef __KERNEL__
9#ifndef _ASM_DBDMA_H_
10#define _ASM_DBDMA_H_
11/*
12 * DBDMA control/status registers. All little-endian.
13 */
14struct dbdma_regs {
15 unsigned int control; /* lets you change bits in status */
16 unsigned int status; /* DMA and device status bits (see below) */
17 unsigned int cmdptr_hi; /* upper 32 bits of command address */
18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
22 unsigned int xfer_mode;
23 unsigned int data2ptr_hi;
24 unsigned int data2ptr;
25 unsigned int res1;
26 unsigned int address_hi;
27 unsigned int br_addr_hi;
28 unsigned int res2[3];
29};
30
31/* Bits in control and status registers */
32#define RUN 0x8000
33#define PAUSE 0x4000
34#define FLUSH 0x2000
35#define WAKE 0x1000
36#define DEAD 0x0800
37#define ACTIVE 0x0400
38#define BT 0x0100
39#define DEVSTAT 0x00ff
40
41/*
42 * DBDMA command structure. These fields are all little-endian!
43 */
44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */
51};
52
53/* DBDMA command values in command field */
54#define OUTPUT_MORE 0 /* transfer memory data to stream */
55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
56#define INPUT_MORE 0x2000 /* transfer stream data to memory */
57#define INPUT_LAST 0x3000 /* ditto, expect end marker */
58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
60#define DBDMA_NOP 0x6000 /* do nothing */
61#define DBDMA_STOP 0x7000 /* suspend processing */
62
63/* Key values in command field */
64#define KEY_STREAM0 0 /* usual data stream */
65#define KEY_STREAM1 0x100 /* control/status stream */
66#define KEY_STREAM2 0x200 /* device-dependent stream */
67#define KEY_STREAM3 0x300 /* device-dependent stream */
68#define KEY_REGS 0x500 /* device register space */
69#define KEY_SYSTEM 0x600 /* system memory-mapped space */
70#define KEY_DEVICE 0x700 /* device memory-mapped space */
71
72/* Interrupt control values in command field */
73#define INTR_NEVER 0 /* don't interrupt */
74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
76#define INTR_ALWAYS 0x30 /* always interrupt */
77
78/* Branch control values in command field */
79#define BR_NEVER 0 /* don't branch */
80#define BR_IFSET 0x4 /* branch if condition bit is 1 */
81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
82#define BR_ALWAYS 0xc /* always branch */
83
84/* Wait control values in command field */
85#define WAIT_NEVER 0 /* don't wait */
86#define WAIT_IFSET 1 /* wait if condition bit is 1 */
87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
88#define WAIT_ALWAYS 3 /* always wait */
89
90/* Align an address for a DBDMA command structure */
91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
92 & -sizeof(struct dbdma_cmd))
93
94/* Useful macros */
95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \
99} while(0)
100
101#define DBDMA_DO_RESET(regs) do { \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
103 while(in_le32(&((regs)->status)) & (RUN)) \
104 ; \
105} while(0)
106
107#endif /* _ASM_DBDMA_H_ */
108#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/dcr-generic.h b/arch/powerpc/include/asm/dcr-generic.h
new file mode 100644
index 000000000000..35b71599ec46
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-generic.h
@@ -0,0 +1,49 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_GENERIC_H
21#define _ASM_POWERPC_DCR_GENERIC_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
26
27typedef struct {
28 enum host_type_t type;
29 union {
30 dcr_host_mmio_t mmio;
31 dcr_host_native_t native;
32 } host;
33} dcr_host_t;
34
35extern bool dcr_map_ok_generic(dcr_host_t host);
36
37extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
38 unsigned int dcr_c);
39extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
40
41extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
42
43extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
44
45#endif /* __ASSEMBLY__ */
46#endif /* __KERNEL__ */
47#endif /* _ASM_POWERPC_DCR_GENERIC_H */
48
49
diff --git a/arch/powerpc/include/asm/dcr-mmio.h b/arch/powerpc/include/asm/dcr-mmio.h
new file mode 100644
index 000000000000..acd491dbd45a
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-mmio.h
@@ -0,0 +1,61 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_MMIO_H
21#define _ASM_POWERPC_DCR_MMIO_H
22#ifdef __KERNEL__
23
24#include <asm/io.h>
25
26typedef struct {
27 void __iomem *token;
28 unsigned int stride;
29 unsigned int base;
30} dcr_host_mmio_t;
31
32static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
33{
34 return host.token != NULL;
35}
36
37extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
38 unsigned int dcr_n,
39 unsigned int dcr_c);
40extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
41
42static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
43{
44 return in_be32(host.token + ((host.base + dcr_n) * host.stride));
45}
46
47static inline void dcr_write_mmio(dcr_host_mmio_t host,
48 unsigned int dcr_n,
49 u32 value)
50{
51 out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
52}
53
54extern u64 of_translate_dcr_address(struct device_node *dev,
55 unsigned int dcr_n,
56 unsigned int *stride);
57
58#endif /* __KERNEL__ */
59#endif /* _ASM_POWERPC_DCR_MMIO_H */
60
61
diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h
new file mode 100644
index 000000000000..72d2b72c7390
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -0,0 +1,116 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_NATIVE_H
21#define _ASM_POWERPC_DCR_NATIVE_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25#include <linux/spinlock.h>
26
27typedef struct {
28 unsigned int base;
29} dcr_host_native_t;
30
31static inline bool dcr_map_ok_native(dcr_host_native_t host)
32{
33 return 1;
34}
35
36#define dcr_map_native(dev, dcr_n, dcr_c) \
37 ((dcr_host_native_t){ .base = (dcr_n) })
38#define dcr_unmap_native(host, dcr_c) do {} while (0)
39#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
40#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
41
42/* Device Control Registers */
43void __mtdcr(int reg, unsigned int val);
44unsigned int __mfdcr(int reg);
45#define mfdcr(rn) \
46 ({unsigned int rval; \
47 if (__builtin_constant_p(rn)) \
48 asm volatile("mfdcr %0," __stringify(rn) \
49 : "=r" (rval)); \
50 else \
51 rval = __mfdcr(rn); \
52 rval;})
53
54#define mtdcr(rn, v) \
55do { \
56 if (__builtin_constant_p(rn)) \
57 asm volatile("mtdcr " __stringify(rn) ",%0" \
58 : : "r" (v)); \
59 else \
60 __mtdcr(rn, v); \
61} while (0)
62
63/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
64extern spinlock_t dcr_ind_lock;
65
66static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
67{
68 unsigned long flags;
69 unsigned int val;
70
71 spin_lock_irqsave(&dcr_ind_lock, flags);
72 __mtdcr(base_addr, reg);
73 val = __mfdcr(base_data);
74 spin_unlock_irqrestore(&dcr_ind_lock, flags);
75 return val;
76}
77
78static inline void __mtdcri(int base_addr, int base_data, int reg,
79 unsigned val)
80{
81 unsigned long flags;
82
83 spin_lock_irqsave(&dcr_ind_lock, flags);
84 __mtdcr(base_addr, reg);
85 __mtdcr(base_data, val);
86 spin_unlock_irqrestore(&dcr_ind_lock, flags);
87}
88
89static inline void __dcri_clrset(int base_addr, int base_data, int reg,
90 unsigned clr, unsigned set)
91{
92 unsigned long flags;
93 unsigned int val;
94
95 spin_lock_irqsave(&dcr_ind_lock, flags);
96 __mtdcr(base_addr, reg);
97 val = (__mfdcr(base_data) & ~clr) | set;
98 __mtdcr(base_data, val);
99 spin_unlock_irqrestore(&dcr_ind_lock, flags);
100}
101
102#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
103 DCRN_ ## base ## _CONFIG_DATA, \
104 reg)
105
106#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
107 DCRN_ ## base ## _CONFIG_DATA, \
108 reg, data)
109
110#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
111 DCRN_ ## base ## _CONFIG_DATA, \
112 reg, clr, set)
113
114#endif /* __ASSEMBLY__ */
115#endif /* __KERNEL__ */
116#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
new file mode 100644
index 000000000000..29b0ecef980a
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -0,0 +1,149 @@
1/*
2 * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
3 * 4xx processors
4 *
5 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp
6 * <benh@kernel.crashing.org>
7 *
8 * Mostly lifted from asm-ppc/ibm4xx.h by
9 *
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 *
12 */
13
14#ifndef __DCR_REGS_H__
15#define __DCR_REGS_H__
16
17/*
18 * Most DCRs used for controlling devices such as the MAL, DMA engine,
19 * etc... are obtained for the device tree.
20 *
21 * The definitions in this files are fixed DCRs and indirect DCRs that
22 * are commonly used outside of specific drivers or refer to core
23 * common registers that may occasionally have to be tweaked outside
24 * of the driver main register set
25 */
26
27/* CPRs (440GX and 440SP/440SPe) */
28#define DCRN_CPR0_CONFIG_ADDR 0xc
29#define DCRN_CPR0_CONFIG_DATA 0xd
30
31/* SDRs (440GX and 440SP/440SPe) */
32#define DCRN_SDR0_CONFIG_ADDR 0xe
33#define DCRN_SDR0_CONFIG_DATA 0xf
34
35#define SDR0_PFC0 0x4100
36#define SDR0_PFC1 0x4101
37#define SDR0_PFC1_EPS 0x1c00000
38#define SDR0_PFC1_EPS_SHIFT 22
39#define SDR0_PFC1_RMII 0x02000000
40#define SDR0_MFR 0x4300
41#define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
42#define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
43#define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
44#define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */
45#define SDR0_MFR_T0TXFL 0x00080000
46#define SDR0_MFR_T0TXFH 0x00040000
47#define SDR0_MFR_T1TXFL 0x00020000
48#define SDR0_MFR_T1TXFH 0x00010000
49#define SDR0_MFR_E0TXFL 0x00008000
50#define SDR0_MFR_E0TXFH 0x00004000
51#define SDR0_MFR_E0RXFL 0x00002000
52#define SDR0_MFR_E0RXFH 0x00001000
53#define SDR0_MFR_E1TXFL 0x00000800
54#define SDR0_MFR_E1TXFH 0x00000400
55#define SDR0_MFR_E1RXFL 0x00000200
56#define SDR0_MFR_E1RXFH 0x00000100
57#define SDR0_MFR_E2TXFL 0x00000080
58#define SDR0_MFR_E2TXFH 0x00000040
59#define SDR0_MFR_E2RXFL 0x00000020
60#define SDR0_MFR_E2RXFH 0x00000010
61#define SDR0_MFR_E3TXFL 0x00000008
62#define SDR0_MFR_E3TXFH 0x00000004
63#define SDR0_MFR_E3RXFL 0x00000002
64#define SDR0_MFR_E3RXFH 0x00000001
65#define SDR0_UART0 0x0120
66#define SDR0_UART1 0x0121
67#define SDR0_UART2 0x0122
68#define SDR0_UART3 0x0123
69#define SDR0_CUST0 0x4000
70
71/*
72 * All those DCR register addresses are offsets from the base address
73 * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
74 * excluded here and configured in the device tree.
75 */
76#define DCRN_SRAM0_SB0CR 0x00
77#define DCRN_SRAM0_SB1CR 0x01
78#define DCRN_SRAM0_SB2CR 0x02
79#define DCRN_SRAM0_SB3CR 0x03
80#define SRAM_SBCR_BU_MASK 0x00000180
81#define SRAM_SBCR_BS_64KB 0x00000800
82#define SRAM_SBCR_BU_RO 0x00000080
83#define SRAM_SBCR_BU_RW 0x00000180
84#define DCRN_SRAM0_BEAR 0x04
85#define DCRN_SRAM0_BESR0 0x05
86#define DCRN_SRAM0_BESR1 0x06
87#define DCRN_SRAM0_PMEG 0x07
88#define DCRN_SRAM0_CID 0x08
89#define DCRN_SRAM0_REVID 0x09
90#define DCRN_SRAM0_DPC 0x0a
91#define SRAM_DPC_ENABLE 0x80000000
92
93/*
94 * All those DCR register addresses are offsets from the base address
95 * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
96 * excluded here and configured in the device tree.
97 */
98#define DCRN_L2C0_CFG 0x00
99#define L2C_CFG_L2M 0x80000000
100#define L2C_CFG_ICU 0x40000000
101#define L2C_CFG_DCU 0x20000000
102#define L2C_CFG_DCW_MASK 0x1e000000
103#define L2C_CFG_TPC 0x01000000
104#define L2C_CFG_CPC 0x00800000
105#define L2C_CFG_FRAN 0x00200000
106#define L2C_CFG_SS_MASK 0x00180000
107#define L2C_CFG_SS_256 0x00000000
108#define L2C_CFG_CPIM 0x00040000
109#define L2C_CFG_TPIM 0x00020000
110#define L2C_CFG_LIM 0x00010000
111#define L2C_CFG_PMUX_MASK 0x00007000
112#define L2C_CFG_PMUX_SNP 0x00000000
113#define L2C_CFG_PMUX_IF 0x00001000
114#define L2C_CFG_PMUX_DF 0x00002000
115#define L2C_CFG_PMUX_DS 0x00003000
116#define L2C_CFG_PMIM 0x00000800
117#define L2C_CFG_TPEI 0x00000400
118#define L2C_CFG_CPEI 0x00000200
119#define L2C_CFG_NAM 0x00000100
120#define L2C_CFG_SMCM 0x00000080
121#define L2C_CFG_NBRM 0x00000040
122#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
123#define DCRN_L2C0_CMD 0x01
124#define L2C_CMD_CLR 0x80000000
125#define L2C_CMD_DIAG 0x40000000
126#define L2C_CMD_INV 0x20000000
127#define L2C_CMD_CCP 0x10000000
128#define L2C_CMD_CTE 0x08000000
129#define L2C_CMD_STRC 0x04000000
130#define L2C_CMD_STPC 0x02000000
131#define L2C_CMD_RPMC 0x01000000
132#define L2C_CMD_HCC 0x00800000
133#define DCRN_L2C0_ADDR 0x02
134#define DCRN_L2C0_DATA 0x03
135#define DCRN_L2C0_SR 0x04
136#define L2C_SR_CC 0x80000000
137#define L2C_SR_CPE 0x40000000
138#define L2C_SR_TPE 0x20000000
139#define L2C_SR_LRU 0x10000000
140#define L2C_SR_PCS 0x08000000
141#define DCRN_L2C0_REVID 0x05
142#define DCRN_L2C0_SNP0 0x06
143#define DCRN_L2C0_SNP1 0x07
144#define L2C_SNP_BA_MASK 0xffff0000
145#define L2C_SNP_SSR_MASK 0x0000f000
146#define L2C_SNP_SSR_32G 0x0000f000
147#define L2C_SNP_ESR 0x00000800
148
149#endif /* __DCR_REGS_H__ */
diff --git a/arch/powerpc/include/asm/dcr.h b/arch/powerpc/include/asm/dcr.h
new file mode 100644
index 000000000000..53b283050ab3
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr.h
@@ -0,0 +1,82 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_H
21#define _ASM_POWERPC_DCR_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24#ifdef CONFIG_PPC_DCR
25
26#ifdef CONFIG_PPC_DCR_NATIVE
27#include <asm/dcr-native.h>
28#endif
29
30#ifdef CONFIG_PPC_DCR_MMIO
31#include <asm/dcr-mmio.h>
32#endif
33
34
35/* Indirection layer for providing both NATIVE and MMIO support. */
36
37#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
38
39#include <asm/dcr-generic.h>
40
41#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
42#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
43#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
44#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
45#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
46
47#else
48
49#ifdef CONFIG_PPC_DCR_NATIVE
50typedef dcr_host_native_t dcr_host_t;
51#define DCR_MAP_OK(host) dcr_map_ok_native(host)
52#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
53#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
54#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
55#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
56#else
57typedef dcr_host_mmio_t dcr_host_t;
58#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
59#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
60#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
61#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
62#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
63#endif
64
65#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
66
67/*
68 * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
69 * base from the device-tree
70 */
71#ifdef CONFIG_PPC_MERGE
72struct device_node;
73extern unsigned int dcr_resource_start(struct device_node *np,
74 unsigned int index);
75extern unsigned int dcr_resource_len(struct device_node *np,
76 unsigned int index);
77#endif /* CONFIG_PPC_MERGE */
78
79#endif /* CONFIG_PPC_DCR */
80#endif /* __ASSEMBLY__ */
81#endif /* __KERNEL__ */
82#endif /* _ASM_POWERPC_DCR_H */
diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/delay.h
new file mode 100644
index 000000000000..f9200a65c632
--- /dev/null
+++ b/arch/powerpc/include/asm/delay.h
@@ -0,0 +1,34 @@
1#ifndef _ASM_POWERPC_DELAY_H
2#define _ASM_POWERPC_DELAY_H
3#ifdef __KERNEL__
4
5/*
6 * Copyright 1996, Paul Mackerras.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * PPC64 Support added by Dave Engebretsen, Todd Inglett, Mike Corrigan,
14 * Anton Blanchard.
15 */
16
17extern void __delay(unsigned long loops);
18extern void udelay(unsigned long usecs);
19
20/*
21 * On shared processor machines the generic implementation of mdelay can
22 * result in large errors. While each iteration of the loop inside mdelay
23 * is supposed to take 1ms, the hypervisor could sleep our partition for
24 * longer (eg 10ms). With the right timing these errors can add up.
25 *
26 * Since there is no 32bit overflow issue on 64bit kernels, just call
27 * udelay directly.
28 */
29#ifdef CONFIG_PPC64
30#define mdelay(n) udelay((n) * 1000)
31#endif
32
33#endif /* __KERNEL__ */
34#endif /* _ASM_POWERPC_DELAY_H */
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
new file mode 100644
index 000000000000..228ab2a315b9
--- /dev/null
+++ b/arch/powerpc/include/asm/device.h
@@ -0,0 +1,24 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#ifndef _ASM_POWERPC_DEVICE_H
7#define _ASM_POWERPC_DEVICE_H
8
9struct dma_mapping_ops;
10struct device_node;
11
12struct dev_archdata {
13 /* Optional pointer to an OF device node */
14 struct device_node *of_node;
15
16 /* DMA operations on that device */
17 struct dma_mapping_ops *dma_ops;
18 void *dma_data;
19
20 /* NUMA node if applicable */
21 int numa_node;
22};
23
24#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/arch/powerpc/include/asm/div64.h b/arch/powerpc/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/powerpc/include/asm/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..c7ca45f97dd2
--- /dev/null
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -0,0 +1,474 @@
1/*
2 * Copyright (C) 2004 IBM
3 *
4 * Implements the generic device dma API for powerpc.
5 * the pci and vio busses
6 */
7#ifndef _ASM_DMA_MAPPING_H
8#define _ASM_DMA_MAPPING_H
9#ifdef __KERNEL__
10
11#include <linux/types.h>
12#include <linux/cache.h>
13/* need struct page definitions */
14#include <linux/mm.h>
15#include <linux/scatterlist.h>
16#include <linux/dma-attrs.h>
17#include <asm/io.h>
18
19#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
20
21#ifdef CONFIG_NOT_COHERENT_CACHE
22/*
23 * DMA-consistent mapping functions for PowerPCs that don't support
24 * cache snooping. These allocate/free a region of uncached mapped
25 * memory space for use with DMA devices. Alternatively, you could
26 * allocate the space "normally" and use the cache management functions
27 * to ensure it is consistent.
28 */
29extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
30extern void __dma_free_coherent(size_t size, void *vaddr);
31extern void __dma_sync(void *vaddr, size_t size, int direction);
32extern void __dma_sync_page(struct page *page, unsigned long offset,
33 size_t size, int direction);
34
35#else /* ! CONFIG_NOT_COHERENT_CACHE */
36/*
37 * Cache coherent cores.
38 */
39
40#define __dma_alloc_coherent(gfp, size, handle) NULL
41#define __dma_free_coherent(size, addr) ((void)0)
42#define __dma_sync(addr, size, rw) ((void)0)
43#define __dma_sync_page(pg, off, sz, rw) ((void)0)
44
45#endif /* ! CONFIG_NOT_COHERENT_CACHE */
46
47#ifdef CONFIG_PPC64
48
49static inline unsigned long device_to_mask(struct device *dev)
50{
51 if (dev->dma_mask && *dev->dma_mask)
52 return *dev->dma_mask;
53 /* Assume devices without mask can take 32 bit addresses */
54 return 0xfffffffful;
55}
56
57/*
58 * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
59 */
60struct dma_mapping_ops {
61 void * (*alloc_coherent)(struct device *dev, size_t size,
62 dma_addr_t *dma_handle, gfp_t flag);
63 void (*free_coherent)(struct device *dev, size_t size,
64 void *vaddr, dma_addr_t dma_handle);
65 dma_addr_t (*map_single)(struct device *dev, void *ptr,
66 size_t size, enum dma_data_direction direction,
67 struct dma_attrs *attrs);
68 void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
69 size_t size, enum dma_data_direction direction,
70 struct dma_attrs *attrs);
71 int (*map_sg)(struct device *dev, struct scatterlist *sg,
72 int nents, enum dma_data_direction direction,
73 struct dma_attrs *attrs);
74 void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
75 int nents, enum dma_data_direction direction,
76 struct dma_attrs *attrs);
77 int (*dma_supported)(struct device *dev, u64 mask);
78 int (*set_dma_mask)(struct device *dev, u64 dma_mask);
79};
80
81static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
82{
83 /* We don't handle the NULL dev case for ISA for now. We could
84 * do it via an out of line call but it is not needed for now. The
85 * only ISA DMA device we support is the floppy and we have a hack
86 * in the floppy driver directly to get a device for us.
87 */
88 if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
89 return NULL;
90 return dev->archdata.dma_ops;
91}
92
93static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
94{
95 dev->archdata.dma_ops = ops;
96}
97
98static inline int dma_supported(struct device *dev, u64 mask)
99{
100 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
101
102 if (unlikely(dma_ops == NULL))
103 return 0;
104 if (dma_ops->dma_supported == NULL)
105 return 1;
106 return dma_ops->dma_supported(dev, mask);
107}
108
109/* We have our own implementation of pci_set_dma_mask() */
110#define HAVE_ARCH_PCI_SET_DMA_MASK
111
112static inline int dma_set_mask(struct device *dev, u64 dma_mask)
113{
114 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
115
116 if (unlikely(dma_ops == NULL))
117 return -EIO;
118 if (dma_ops->set_dma_mask != NULL)
119 return dma_ops->set_dma_mask(dev, dma_mask);
120 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
121 return -EIO;
122 *dev->dma_mask = dma_mask;
123 return 0;
124}
125
126static inline dma_addr_t dma_map_single_attrs(struct device *dev,
127 void *cpu_addr,
128 size_t size,
129 enum dma_data_direction direction,
130 struct dma_attrs *attrs)
131{
132 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
133
134 BUG_ON(!dma_ops);
135 return dma_ops->map_single(dev, cpu_addr, size, direction, attrs);
136}
137
138static inline void dma_unmap_single_attrs(struct device *dev,
139 dma_addr_t dma_addr,
140 size_t size,
141 enum dma_data_direction direction,
142 struct dma_attrs *attrs)
143{
144 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
145
146 BUG_ON(!dma_ops);
147 dma_ops->unmap_single(dev, dma_addr, size, direction, attrs);
148}
149
150static inline dma_addr_t dma_map_page_attrs(struct device *dev,
151 struct page *page,
152 unsigned long offset, size_t size,
153 enum dma_data_direction direction,
154 struct dma_attrs *attrs)
155{
156 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
157
158 BUG_ON(!dma_ops);
159 return dma_ops->map_single(dev, page_address(page) + offset, size,
160 direction, attrs);
161}
162
163static inline void dma_unmap_page_attrs(struct device *dev,
164 dma_addr_t dma_address,
165 size_t size,
166 enum dma_data_direction direction,
167 struct dma_attrs *attrs)
168{
169 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
170
171 BUG_ON(!dma_ops);
172 dma_ops->unmap_single(dev, dma_address, size, direction, attrs);
173}
174
175static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
176 int nents, enum dma_data_direction direction,
177 struct dma_attrs *attrs)
178{
179 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
180
181 BUG_ON(!dma_ops);
182 return dma_ops->map_sg(dev, sg, nents, direction, attrs);
183}
184
185static inline void dma_unmap_sg_attrs(struct device *dev,
186 struct scatterlist *sg,
187 int nhwentries,
188 enum dma_data_direction direction,
189 struct dma_attrs *attrs)
190{
191 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
192
193 BUG_ON(!dma_ops);
194 dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
195}
196
197static inline void *dma_alloc_coherent(struct device *dev, size_t size,
198 dma_addr_t *dma_handle, gfp_t flag)
199{
200 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
201
202 BUG_ON(!dma_ops);
203 return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
204}
205
206static inline void dma_free_coherent(struct device *dev, size_t size,
207 void *cpu_addr, dma_addr_t dma_handle)
208{
209 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
210
211 BUG_ON(!dma_ops);
212 dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
213}
214
215static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
216 size_t size,
217 enum dma_data_direction direction)
218{
219 return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
220}
221
222static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
223 size_t size,
224 enum dma_data_direction direction)
225{
226 dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
227}
228
229static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
230 unsigned long offset, size_t size,
231 enum dma_data_direction direction)
232{
233 return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
234}
235
236static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
237 size_t size,
238 enum dma_data_direction direction)
239{
240 dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
241}
242
243static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
244 int nents, enum dma_data_direction direction)
245{
246 return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
247}
248
249static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
250 int nhwentries,
251 enum dma_data_direction direction)
252{
253 dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
254}
255
256/*
257 * Available generic sets of operations
258 */
259extern struct dma_mapping_ops dma_iommu_ops;
260extern struct dma_mapping_ops dma_direct_ops;
261
262#else /* CONFIG_PPC64 */
263
264#define dma_supported(dev, mask) (1)
265
266static inline int dma_set_mask(struct device *dev, u64 dma_mask)
267{
268 if (!dev->dma_mask || !dma_supported(dev, mask))
269 return -EIO;
270
271 *dev->dma_mask = dma_mask;
272
273 return 0;
274}
275
276static inline void *dma_alloc_coherent(struct device *dev, size_t size,
277 dma_addr_t * dma_handle,
278 gfp_t gfp)
279{
280#ifdef CONFIG_NOT_COHERENT_CACHE
281 return __dma_alloc_coherent(size, dma_handle, gfp);
282#else
283 void *ret;
284 /* ignore region specifiers */
285 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
286
287 if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
288 gfp |= GFP_DMA;
289
290 ret = (void *)__get_free_pages(gfp, get_order(size));
291
292 if (ret != NULL) {
293 memset(ret, 0, size);
294 *dma_handle = virt_to_bus(ret);
295 }
296
297 return ret;
298#endif
299}
300
301static inline void
302dma_free_coherent(struct device *dev, size_t size, void *vaddr,
303 dma_addr_t dma_handle)
304{
305#ifdef CONFIG_NOT_COHERENT_CACHE
306 __dma_free_coherent(size, vaddr);
307#else
308 free_pages((unsigned long)vaddr, get_order(size));
309#endif
310}
311
312static inline dma_addr_t
313dma_map_single(struct device *dev, void *ptr, size_t size,
314 enum dma_data_direction direction)
315{
316 BUG_ON(direction == DMA_NONE);
317
318 __dma_sync(ptr, size, direction);
319
320 return virt_to_bus(ptr);
321}
322
323static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
324 size_t size,
325 enum dma_data_direction direction)
326{
327 /* We do nothing. */
328}
329
330static inline dma_addr_t
331dma_map_page(struct device *dev, struct page *page,
332 unsigned long offset, size_t size,
333 enum dma_data_direction direction)
334{
335 BUG_ON(direction == DMA_NONE);
336
337 __dma_sync_page(page, offset, size, direction);
338
339 return page_to_bus(page) + offset;
340}
341
342static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
343 size_t size,
344 enum dma_data_direction direction)
345{
346 /* We do nothing. */
347}
348
349static inline int
350dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
351 enum dma_data_direction direction)
352{
353 struct scatterlist *sg;
354 int i;
355
356 BUG_ON(direction == DMA_NONE);
357
358 for_each_sg(sgl, sg, nents, i) {
359 BUG_ON(!sg_page(sg));
360 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
361 sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset;
362 }
363
364 return nents;
365}
366
367static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
368 int nhwentries,
369 enum dma_data_direction direction)
370{
371 /* We don't do anything here. */
372}
373
374#endif /* CONFIG_PPC64 */
375
376static inline void dma_sync_single_for_cpu(struct device *dev,
377 dma_addr_t dma_handle, size_t size,
378 enum dma_data_direction direction)
379{
380 BUG_ON(direction == DMA_NONE);
381 __dma_sync(bus_to_virt(dma_handle), size, direction);
382}
383
384static inline void dma_sync_single_for_device(struct device *dev,
385 dma_addr_t dma_handle, size_t size,
386 enum dma_data_direction direction)
387{
388 BUG_ON(direction == DMA_NONE);
389 __dma_sync(bus_to_virt(dma_handle), size, direction);
390}
391
392static inline void dma_sync_sg_for_cpu(struct device *dev,
393 struct scatterlist *sgl, int nents,
394 enum dma_data_direction direction)
395{
396 struct scatterlist *sg;
397 int i;
398
399 BUG_ON(direction == DMA_NONE);
400
401 for_each_sg(sgl, sg, nents, i)
402 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
403}
404
405static inline void dma_sync_sg_for_device(struct device *dev,
406 struct scatterlist *sgl, int nents,
407 enum dma_data_direction direction)
408{
409 struct scatterlist *sg;
410 int i;
411
412 BUG_ON(direction == DMA_NONE);
413
414 for_each_sg(sgl, sg, nents, i)
415 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
416}
417
418static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
419{
420#ifdef CONFIG_PPC64
421 return (dma_addr == DMA_ERROR_CODE);
422#else
423 return 0;
424#endif
425}
426
427#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
428#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
429#ifdef CONFIG_NOT_COHERENT_CACHE
430#define dma_is_consistent(d, h) (0)
431#else
432#define dma_is_consistent(d, h) (1)
433#endif
434
435static inline int dma_get_cache_alignment(void)
436{
437#ifdef CONFIG_PPC64
438 /* no easy way to get cache size on all processors, so return
439 * the maximum possible, to be safe */
440 return (1 << INTERNODE_CACHE_SHIFT);
441#else
442 /*
443 * Each processor family will define its own L1_CACHE_SHIFT,
444 * L1_CACHE_BYTES wraps to this, so this is always safe.
445 */
446 return L1_CACHE_BYTES;
447#endif
448}
449
450static inline void dma_sync_single_range_for_cpu(struct device *dev,
451 dma_addr_t dma_handle, unsigned long offset, size_t size,
452 enum dma_data_direction direction)
453{
454 /* just sync everything for now */
455 dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
456}
457
458static inline void dma_sync_single_range_for_device(struct device *dev,
459 dma_addr_t dma_handle, unsigned long offset, size_t size,
460 enum dma_data_direction direction)
461{
462 /* just sync everything for now */
463 dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
464}
465
466static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
467 enum dma_data_direction direction)
468{
469 BUG_ON(direction == DMA_NONE);
470 __dma_sync(vaddr, size, (int)direction);
471}
472
473#endif /* __KERNEL__ */
474#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/powerpc/include/asm/dma.h b/arch/powerpc/include/asm/dma.h
new file mode 100644
index 000000000000..a7e06e25c708
--- /dev/null
+++ b/arch/powerpc/include/asm/dma.h
@@ -0,0 +1,360 @@
1#ifndef _ASM_POWERPC_DMA_H
2#define _ASM_POWERPC_DMA_H
3#ifdef __KERNEL__
4
5/*
6 * Defines for using and allocating dma channels.
7 * Written by Hennus Bergman, 1992.
8 * High DMA channel support & info by Hannu Savolainen
9 * and John Boyd, Nov. 1992.
10 * Changes for ppc sound by Christoph Nadig
11 */
12
13/*
14 * Note: Adapted for PowerPC by Gary Thomas
15 * Modified by Cort Dougan <cort@cs.nmt.edu>
16 *
17 * None of this really applies for Power Macintoshes. There is
18 * basically just enough here to get kernel/dma.c to compile.
19 *
20 * There may be some comments or restrictions made here which are
21 * not valid for the PReP platform. Take what you read
22 * with a grain of salt.
23 */
24
25#include <asm/io.h>
26#include <linux/spinlock.h>
27#include <asm/system.h>
28
29#ifndef MAX_DMA_CHANNELS
30#define MAX_DMA_CHANNELS 8
31#endif
32
33/* The maximum address that we can perform a DMA transfer to on this platform */
34/* Doesn't really apply... */
35#define MAX_DMA_ADDRESS (~0UL)
36
37#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
38
39#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
40#define dma_outb outb_p
41#else
42#define dma_outb outb
43#endif
44
45#define dma_inb inb
46
47/*
48 * NOTES about DMA transfers:
49 *
50 * controller 1: channels 0-3, byte operations, ports 00-1F
51 * controller 2: channels 4-7, word operations, ports C0-DF
52 *
53 * - ALL registers are 8 bits only, regardless of transfer size
54 * - channel 4 is not used - cascades 1 into 2.
55 * - channels 0-3 are byte - addresses/counts are for physical bytes
56 * - channels 5-7 are word - addresses/counts are for physical words
57 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
58 * - transfer count loaded to registers is 1 less than actual count
59 * - controller 2 offsets are all even (2x offsets for controller 1)
60 * - page registers for 5-7 don't use data bit 0, represent 128K pages
61 * - page registers for 0-3 use bit 0, represent 64K pages
62 *
63 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
64 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
65 * Note that addresses loaded into registers must be _physical_ addresses,
66 * not logical addresses (which may differ if paging is active).
67 *
68 * Address mapping for channels 0-3:
69 *
70 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
71 * | ... | | ... | | ... |
72 * | ... | | ... | | ... |
73 * | ... | | ... | | ... |
74 * P7 ... P0 A7 ... A0 A7 ... A0
75 * | Page | Addr MSB | Addr LSB | (DMA registers)
76 *
77 * Address mapping for channels 5-7:
78 *
79 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
80 * | ... | \ \ ... \ \ \ ... \ \
81 * | ... | \ \ ... \ \ \ ... \ (not used)
82 * | ... | \ \ ... \ \ \ ... \
83 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
84 * | Page | Addr MSB | Addr LSB | (DMA registers)
85 *
86 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
87 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
88 * the hardware level, so odd-byte transfers aren't possible).
89 *
90 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
91 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
92 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
93 *
94 */
95
96/* 8237 DMA controllers */
97#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
98#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
99
100/* DMA controller registers */
101#define DMA1_CMD_REG 0x08 /* command register (w) */
102#define DMA1_STAT_REG 0x08 /* status register (r) */
103#define DMA1_REQ_REG 0x09 /* request register (w) */
104#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
105#define DMA1_MODE_REG 0x0B /* mode register (w) */
106#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
107#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
108#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
109#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
110#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
111
112#define DMA2_CMD_REG 0xD0 /* command register (w) */
113#define DMA2_STAT_REG 0xD0 /* status register (r) */
114#define DMA2_REQ_REG 0xD2 /* request register (w) */
115#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
116#define DMA2_MODE_REG 0xD6 /* mode register (w) */
117#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
118#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
119#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
120#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
121#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
122
123#define DMA_ADDR_0 0x00 /* DMA address registers */
124#define DMA_ADDR_1 0x02
125#define DMA_ADDR_2 0x04
126#define DMA_ADDR_3 0x06
127#define DMA_ADDR_4 0xC0
128#define DMA_ADDR_5 0xC4
129#define DMA_ADDR_6 0xC8
130#define DMA_ADDR_7 0xCC
131
132#define DMA_CNT_0 0x01 /* DMA count registers */
133#define DMA_CNT_1 0x03
134#define DMA_CNT_2 0x05
135#define DMA_CNT_3 0x07
136#define DMA_CNT_4 0xC2
137#define DMA_CNT_5 0xC6
138#define DMA_CNT_6 0xCA
139#define DMA_CNT_7 0xCE
140
141#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
142#define DMA_LO_PAGE_1 0x83
143#define DMA_LO_PAGE_2 0x81
144#define DMA_LO_PAGE_3 0x82
145#define DMA_LO_PAGE_5 0x8B
146#define DMA_LO_PAGE_6 0x89
147#define DMA_LO_PAGE_7 0x8A
148
149#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
150#define DMA_HI_PAGE_1 0x483
151#define DMA_HI_PAGE_2 0x481
152#define DMA_HI_PAGE_3 0x482
153#define DMA_HI_PAGE_5 0x48B
154#define DMA_HI_PAGE_6 0x489
155#define DMA_HI_PAGE_7 0x48A
156
157#define DMA1_EXT_REG 0x40B
158#define DMA2_EXT_REG 0x4D6
159
160#ifndef __powerpc64__
161 /* in arch/ppc/kernel/setup.c -- Cort */
162 extern unsigned int DMA_MODE_WRITE;
163 extern unsigned int DMA_MODE_READ;
164 extern unsigned long ISA_DMA_THRESHOLD;
165#else
166 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
167 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
168#endif
169
170#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
171
172#define DMA_AUTOINIT 0x10
173
174extern spinlock_t dma_spin_lock;
175
176static __inline__ unsigned long claim_dma_lock(void)
177{
178 unsigned long flags;
179 spin_lock_irqsave(&dma_spin_lock, flags);
180 return flags;
181}
182
183static __inline__ void release_dma_lock(unsigned long flags)
184{
185 spin_unlock_irqrestore(&dma_spin_lock, flags);
186}
187
188/* enable/disable a specific DMA channel */
189static __inline__ void enable_dma(unsigned int dmanr)
190{
191 unsigned char ucDmaCmd = 0x00;
192
193 if (dmanr != 4) {
194 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
195 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
196 }
197 if (dmanr <= 3) {
198 dma_outb(dmanr, DMA1_MASK_REG);
199 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
200 } else {
201 dma_outb(dmanr & 3, DMA2_MASK_REG);
202 }
203}
204
205static __inline__ void disable_dma(unsigned int dmanr)
206{
207 if (dmanr <= 3)
208 dma_outb(dmanr | 4, DMA1_MASK_REG);
209 else
210 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
211}
212
213/* Clear the 'DMA Pointer Flip Flop'.
214 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
215 * Use this once to initialize the FF to a known state.
216 * After that, keep track of it. :-)
217 * --- In order to do that, the DMA routines below should ---
218 * --- only be used while interrupts are disabled! ---
219 */
220static __inline__ void clear_dma_ff(unsigned int dmanr)
221{
222 if (dmanr <= 3)
223 dma_outb(0, DMA1_CLEAR_FF_REG);
224 else
225 dma_outb(0, DMA2_CLEAR_FF_REG);
226}
227
228/* set mode (above) for a specific DMA channel */
229static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
230{
231 if (dmanr <= 3)
232 dma_outb(mode | dmanr, DMA1_MODE_REG);
233 else
234 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
235}
236
237/* Set only the page register bits of the transfer address.
238 * This is used for successive transfers when we know the contents of
239 * the lower 16 bits of the DMA current address register, but a 64k boundary
240 * may have been crossed.
241 */
242static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
243{
244 switch (dmanr) {
245 case 0:
246 dma_outb(pagenr, DMA_LO_PAGE_0);
247 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
248 break;
249 case 1:
250 dma_outb(pagenr, DMA_LO_PAGE_1);
251 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
252 break;
253 case 2:
254 dma_outb(pagenr, DMA_LO_PAGE_2);
255 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
256 break;
257 case 3:
258 dma_outb(pagenr, DMA_LO_PAGE_3);
259 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
260 break;
261 case 5:
262 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
263 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
264 break;
265 case 6:
266 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
267 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
268 break;
269 case 7:
270 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
271 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
272 break;
273 }
274}
275
276/* Set transfer address & page bits for specific DMA channel.
277 * Assumes dma flipflop is clear.
278 */
279static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
280{
281 if (dmanr <= 3) {
282 dma_outb(phys & 0xff,
283 ((dmanr & 3) << 1) + IO_DMA1_BASE);
284 dma_outb((phys >> 8) & 0xff,
285 ((dmanr & 3) << 1) + IO_DMA1_BASE);
286 } else {
287 dma_outb((phys >> 1) & 0xff,
288 ((dmanr & 3) << 2) + IO_DMA2_BASE);
289 dma_outb((phys >> 9) & 0xff,
290 ((dmanr & 3) << 2) + IO_DMA2_BASE);
291 }
292 set_dma_page(dmanr, phys >> 16);
293}
294
295
296/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
297 * a specific DMA channel.
298 * You must ensure the parameters are valid.
299 * NOTE: from a manual: "the number of transfers is one more
300 * than the initial word count"! This is taken into account.
301 * Assumes dma flip-flop is clear.
302 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
303 */
304static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
305{
306 count--;
307 if (dmanr <= 3) {
308 dma_outb(count & 0xff,
309 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
310 dma_outb((count >> 8) & 0xff,
311 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
312 } else {
313 dma_outb((count >> 1) & 0xff,
314 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
315 dma_outb((count >> 9) & 0xff,
316 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
317 }
318}
319
320
321/* Get DMA residue count. After a DMA transfer, this
322 * should return zero. Reading this while a DMA transfer is
323 * still in progress will return unpredictable results.
324 * If called before the channel has been used, it may return 1.
325 * Otherwise, it returns the number of _bytes_ left to transfer.
326 *
327 * Assumes DMA flip-flop is clear.
328 */
329static __inline__ int get_dma_residue(unsigned int dmanr)
330{
331 unsigned int io_port = (dmanr <= 3)
332 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
333 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
334
335 /* using short to get 16-bit wrap around */
336 unsigned short count;
337
338 count = 1 + dma_inb(io_port);
339 count += dma_inb(io_port) << 8;
340
341 return (dmanr <= 3) ? count : (count << 1);
342}
343
344/* These are in kernel/dma.c: */
345
346/* reserve a DMA channel */
347extern int request_dma(unsigned int dmanr, const char *device_id);
348/* release it again */
349extern void free_dma(unsigned int dmanr);
350
351#ifdef CONFIG_PCI
352extern int isa_dma_bridge_buggy;
353#else
354#define isa_dma_bridge_buggy (0)
355#endif
356
357#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
358
359#endif /* __KERNEL__ */
360#endif /* _ASM_POWERPC_DMA_H */
diff --git a/arch/powerpc/include/asm/edac.h b/arch/powerpc/include/asm/edac.h
new file mode 100644
index 000000000000..6ead88bbfbb8
--- /dev/null
+++ b/arch/powerpc/include/asm/edac.h
@@ -0,0 +1,40 @@
1/*
2 * PPC EDAC common defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef ASM_EDAC_H
12#define ASM_EDAC_H
13/*
14 * ECC atomic, DMA, SMP and interrupt safe scrub function.
15 * Implements the per arch atomic_scrub() that EDAC use for software
16 * ECC scrubbing. It reads memory and then writes back the original
17 * value, allowing the hardware to detect and correct memory errors.
18 */
19static __inline__ void atomic_scrub(void *va, u32 size)
20{
21 unsigned int *virt_addr = va;
22 unsigned int temp;
23 unsigned int i;
24
25 for (i = 0; i < size / sizeof(*virt_addr); i++, virt_addr++) {
26 /* Very carefully read and write to memory atomically
27 * so we are interrupt, DMA and SMP safe.
28 */
29 __asm__ __volatile__ ("\n\
30 1: lwarx %0,0,%1\n\
31 stwcx. %0,0,%1\n\
32 bne- 1b\n\
33 isync"
34 : "=&r"(temp)
35 : "r"(virt_addr)
36 : "cr0", "memory");
37 }
38}
39
40#endif
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
new file mode 100644
index 000000000000..b886bec67016
--- /dev/null
+++ b/arch/powerpc/include/asm/eeh.h
@@ -0,0 +1,211 @@
1/*
2 * eeh.h
3 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _PPC64_EEH_H
21#define _PPC64_EEH_H
22#ifdef __KERNEL__
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/string.h>
27
28struct pci_dev;
29struct pci_bus;
30struct device_node;
31
32#ifdef CONFIG_EEH
33
34extern int eeh_subsystem_enabled;
35
36/* Values for eeh_mode bits in device_node */
37#define EEH_MODE_SUPPORTED (1<<0)
38#define EEH_MODE_NOCHECK (1<<1)
39#define EEH_MODE_ISOLATED (1<<2)
40#define EEH_MODE_RECOVERING (1<<3)
41#define EEH_MODE_IRQ_DISABLED (1<<4)
42
43/* Max number of EEH freezes allowed before we consider the device
44 * to be permanently disabled. */
45#define EEH_MAX_ALLOWED_FREEZES 5
46
47void __init eeh_init(void);
48unsigned long eeh_check_failure(const volatile void __iomem *token,
49 unsigned long val);
50int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
51void __init pci_addr_cache_build(void);
52
53/**
54 * eeh_add_device_early
55 * eeh_add_device_late
56 *
57 * Perform eeh initialization for devices added after boot.
58 * Call eeh_add_device_early before doing any i/o to the
59 * device (including config space i/o). Call eeh_add_device_late
60 * to finish the eeh setup for this device.
61 */
62void eeh_add_device_tree_early(struct device_node *);
63void eeh_add_device_tree_late(struct pci_bus *);
64
65/**
66 * eeh_remove_device_recursive - undo EEH for device & children.
67 * @dev: pci device to be removed
68 *
69 * As above, this removes the device; it also removes child
70 * pci devices as well.
71 */
72void eeh_remove_bus_device(struct pci_dev *);
73
74/**
75 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
76 *
77 * If this macro yields TRUE, the caller relays to eeh_check_failure()
78 * which does further tests out of line.
79 */
80#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
81
82/*
83 * Reads from a device which has been isolated by EEH will return
84 * all 1s. This macro gives an all-1s value of the given size (in
85 * bytes: 1, 2, or 4) for comparing with the result of a read.
86 */
87#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
88
89#else /* !CONFIG_EEH */
90static inline void eeh_init(void) { }
91
92static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
93{
94 return val;
95}
96
97static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
98{
99 return 0;
100}
101
102static inline void pci_addr_cache_build(void) { }
103
104static inline void eeh_add_device_tree_early(struct device_node *dn) { }
105
106static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
107
108static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
109#define EEH_POSSIBLE_ERROR(val, type) (0)
110#define EEH_IO_ERROR_VALUE(size) (-1UL)
111#endif /* CONFIG_EEH */
112
113/*
114 * MMIO read/write operations with EEH support.
115 */
116static inline u8 eeh_readb(const volatile void __iomem *addr)
117{
118 u8 val = in_8(addr);
119 if (EEH_POSSIBLE_ERROR(val, u8))
120 return eeh_check_failure(addr, val);
121 return val;
122}
123
124static inline u16 eeh_readw(const volatile void __iomem *addr)
125{
126 u16 val = in_le16(addr);
127 if (EEH_POSSIBLE_ERROR(val, u16))
128 return eeh_check_failure(addr, val);
129 return val;
130}
131
132static inline u32 eeh_readl(const volatile void __iomem *addr)
133{
134 u32 val = in_le32(addr);
135 if (EEH_POSSIBLE_ERROR(val, u32))
136 return eeh_check_failure(addr, val);
137 return val;
138}
139
140static inline u64 eeh_readq(const volatile void __iomem *addr)
141{
142 u64 val = in_le64(addr);
143 if (EEH_POSSIBLE_ERROR(val, u64))
144 return eeh_check_failure(addr, val);
145 return val;
146}
147
148static inline u16 eeh_readw_be(const volatile void __iomem *addr)
149{
150 u16 val = in_be16(addr);
151 if (EEH_POSSIBLE_ERROR(val, u16))
152 return eeh_check_failure(addr, val);
153 return val;
154}
155
156static inline u32 eeh_readl_be(const volatile void __iomem *addr)
157{
158 u32 val = in_be32(addr);
159 if (EEH_POSSIBLE_ERROR(val, u32))
160 return eeh_check_failure(addr, val);
161 return val;
162}
163
164static inline u64 eeh_readq_be(const volatile void __iomem *addr)
165{
166 u64 val = in_be64(addr);
167 if (EEH_POSSIBLE_ERROR(val, u64))
168 return eeh_check_failure(addr, val);
169 return val;
170}
171
172static inline void eeh_memcpy_fromio(void *dest, const
173 volatile void __iomem *src,
174 unsigned long n)
175{
176 _memcpy_fromio(dest, src, n);
177
178 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
179 * were copied. Check all four bytes.
180 */
181 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
182 eeh_check_failure(src, *((u32 *)(dest + n - 4)));
183}
184
185/* in-string eeh macros */
186static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
187 int ns)
188{
189 _insb(addr, buf, ns);
190 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
191 eeh_check_failure(addr, *(u8*)buf);
192}
193
194static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
195 int ns)
196{
197 _insw(addr, buf, ns);
198 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
199 eeh_check_failure(addr, *(u16*)buf);
200}
201
202static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
203 int nl)
204{
205 _insl(addr, buf, nl);
206 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
207 eeh_check_failure(addr, *(u32*)buf);
208}
209
210#endif /* __KERNEL__ */
211#endif /* _PPC64_EEH_H */
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
new file mode 100644
index 000000000000..cc3cb04539ac
--- /dev/null
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -0,0 +1,53 @@
1/*
2 * eeh_event.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
19 */
20
21#ifndef ASM_POWERPC_EEH_EVENT_H
22#define ASM_POWERPC_EEH_EVENT_H
23#ifdef __KERNEL__
24
25/** EEH event -- structure holding pci controller data that describes
26 * a change in the isolation status of a PCI slot. A pointer
27 * to this struct is passed as the data pointer in a notify callback.
28 */
29struct eeh_event {
30 struct list_head list;
31 struct device_node *dn; /* struct device node */
32 struct pci_dev *dev; /* affected device */
33};
34
35/**
36 * eeh_send_failure_event - generate a PCI error event
37 * @dev pci device
38 *
39 * This routine builds a PCI error event which will be delivered
40 * to all listeners on the eeh_notifier_chain.
41 *
42 * This routine can be called within an interrupt context;
43 * the actual event will be delivered in a normal context
44 * (from a workqueue).
45 */
46int eeh_send_failure_event (struct device_node *dn,
47 struct pci_dev *dev);
48
49/* Main recovery function */
50struct pci_dn * handle_eeh_events (struct eeh_event *);
51
52#endif /* __KERNEL__ */
53#endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
new file mode 100644
index 000000000000..80d1f399ee51
--- /dev/null
+++ b/arch/powerpc/include/asm/elf.h
@@ -0,0 +1,424 @@
1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
3
4#ifdef __KERNEL__
5#include <linux/sched.h> /* for task_struct */
6#include <asm/page.h>
7#include <asm/string.h>
8#endif
9
10#include <asm/types.h>
11#include <asm/ptrace.h>
12#include <asm/cputable.h>
13#include <asm/auxvec.h>
14
15/* PowerPC relocations defined by the ABIs */
16#define R_PPC_NONE 0
17#define R_PPC_ADDR32 1 /* 32bit absolute address */
18#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
19#define R_PPC_ADDR16 3 /* 16bit absolute address */
20#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
21#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
22#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
23#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
24#define R_PPC_ADDR14_BRTAKEN 8
25#define R_PPC_ADDR14_BRNTAKEN 9
26#define R_PPC_REL24 10 /* PC relative 26 bit */
27#define R_PPC_REL14 11 /* PC relative 16 bit */
28#define R_PPC_REL14_BRTAKEN 12
29#define R_PPC_REL14_BRNTAKEN 13
30#define R_PPC_GOT16 14
31#define R_PPC_GOT16_LO 15
32#define R_PPC_GOT16_HI 16
33#define R_PPC_GOT16_HA 17
34#define R_PPC_PLTREL24 18
35#define R_PPC_COPY 19
36#define R_PPC_GLOB_DAT 20
37#define R_PPC_JMP_SLOT 21
38#define R_PPC_RELATIVE 22
39#define R_PPC_LOCAL24PC 23
40#define R_PPC_UADDR32 24
41#define R_PPC_UADDR16 25
42#define R_PPC_REL32 26
43#define R_PPC_PLT32 27
44#define R_PPC_PLTREL32 28
45#define R_PPC_PLT16_LO 29
46#define R_PPC_PLT16_HI 30
47#define R_PPC_PLT16_HA 31
48#define R_PPC_SDAREL16 32
49#define R_PPC_SECTOFF 33
50#define R_PPC_SECTOFF_LO 34
51#define R_PPC_SECTOFF_HI 35
52#define R_PPC_SECTOFF_HA 36
53
54/* PowerPC relocations defined for the TLS access ABI. */
55#define R_PPC_TLS 67 /* none (sym+add)@tls */
56#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
57#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
58#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
59#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
60#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
61#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
62#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
63#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
64#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
65#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
66#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
67#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
68#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
69#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
70#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
71#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
72#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
73#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
74#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
75#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
76#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
77#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
78#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
79#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
80#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
81#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
82#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
83
84/* keep this the last entry. */
85#define R_PPC_NUM 95
86
87/*
88 * ELF register definitions..
89 *
90 * This program is free software; you can redistribute it and/or
91 * modify it under the terms of the GNU General Public License
92 * as published by the Free Software Foundation; either version
93 * 2 of the License, or (at your option) any later version.
94 */
95
96#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
97#define ELF_NFPREG 33 /* includes fpscr */
98
99typedef unsigned long elf_greg_t64;
100typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
101
102typedef unsigned int elf_greg_t32;
103typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
104typedef elf_gregset_t32 compat_elf_gregset_t;
105
106/*
107 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
108 */
109#ifdef __powerpc64__
110# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
111# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
112# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
113# define ELF_GREG_TYPE elf_greg_t64
114#else
115# define ELF_NEVRREG 34 /* includes acc (as 2) */
116# define ELF_NVRREG 33 /* includes vscr */
117# define ELF_GREG_TYPE elf_greg_t32
118# define ELF_ARCH EM_PPC
119# define ELF_CLASS ELFCLASS32
120# define ELF_DATA ELFDATA2MSB
121#endif /* __powerpc64__ */
122
123#ifndef ELF_ARCH
124# define ELF_ARCH EM_PPC64
125# define ELF_CLASS ELFCLASS64
126# define ELF_DATA ELFDATA2MSB
127 typedef elf_greg_t64 elf_greg_t;
128 typedef elf_gregset_t64 elf_gregset_t;
129#else
130 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
131 typedef elf_greg_t32 elf_greg_t;
132 typedef elf_gregset_t32 elf_gregset_t;
133#endif /* ELF_ARCH */
134
135/* Floating point registers */
136typedef double elf_fpreg_t;
137typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
138
139/* Altivec registers */
140/*
141 * The entries with indexes 0-31 contain the corresponding vector registers.
142 * The entry with index 32 contains the vscr as the last word (offset 12)
143 * within the quadword. This allows the vscr to be stored as either a
144 * quadword (since it must be copied via a vector register to/from storage)
145 * or as a word.
146 *
147 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
148 * word (offset 0) within the quadword.
149 *
150 * This definition of the VMX state is compatible with the current PPC32
151 * ptrace interface. This allows signal handling and ptrace to use the same
152 * structures. This also simplifies the implementation of a bi-arch
153 * (combined (32- and 64-bit) gdb.
154 *
155 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
156 * vrsave along with vscr and so only uses 33 vectors for the register set
157 */
158typedef __vector128 elf_vrreg_t;
159typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
160#ifdef __powerpc64__
161typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
162typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
163#endif
164
165#ifdef __KERNEL__
166/*
167 * This is used to ensure we don't load something for the wrong architecture.
168 */
169#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
170#define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC)
171
172#define USE_ELF_CORE_DUMP
173#define CORE_DUMP_USE_REGSET
174#define ELF_EXEC_PAGESIZE PAGE_SIZE
175
176/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
177 use of this is to invoke "./ld.so someprog" to test out a new version of
178 the loader. We need to make sure that it is out of the way of the program
179 that it will "exec", and that there is sufficient room for the brk. */
180
181#define ELF_ET_DYN_BASE (0x20000000)
182
183/*
184 * Our registers are always unsigned longs, whether we're a 32 bit
185 * process or 64 bit, on either a 64 bit or 32 bit kernel.
186 *
187 * This macro relies on elf_regs[i] having the right type to truncate to,
188 * either u32 or u64. It defines the body of the elf_core_copy_regs
189 * function, either the native one with elf_gregset_t elf_regs or
190 * the 32-bit one with elf_gregset_t32 elf_regs.
191 */
192#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
193 int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
194 (size_t)ELF_NGREG); \
195 for (i = 0; i < nregs; i++) \
196 elf_regs[i] = ((unsigned long *) regs)[i]; \
197 memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
198
199/* Common routine for both 32-bit and 64-bit native processes */
200static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
201 struct pt_regs *regs)
202{
203 PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
204}
205#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
206
207typedef elf_vrregset_t elf_fpxregset_t;
208
209/* ELF_HWCAP yields a mask that user programs can use to figure out what
210 instruction set this cpu supports. This could be done in userspace,
211 but it's not easy, and we've already done it here. */
212# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
213
214/* This yields a string that ld.so will use to load implementation
215 specific libraries for optimization. This is more specific in
216 intent than poking at uname or /proc/cpuinfo. */
217
218#define ELF_PLATFORM (cur_cpu_spec->platform)
219
220/* While ELF_PLATFORM indicates the ISA supported by the platform, it
221 * may not accurately reflect the underlying behavior of the hardware
222 * (as in the case of running in Power5+ compatibility mode on a
223 * Power6 machine). ELF_BASE_PLATFORM allows ld.so to load libraries
224 * that are tuned for the real hardware.
225 */
226#define ELF_BASE_PLATFORM (powerpc_base_platform)
227
228#ifdef __powerpc64__
229# define ELF_PLAT_INIT(_r, load_addr) do { \
230 _r->gpr[2] = load_addr; \
231} while (0)
232#endif /* __powerpc64__ */
233
234#ifdef __powerpc64__
235# define SET_PERSONALITY(ex, ibcs2) \
236do { \
237 unsigned long new_flags = 0; \
238 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
239 new_flags = _TIF_32BIT; \
240 if ((current_thread_info()->flags & _TIF_32BIT) \
241 != new_flags) \
242 set_thread_flag(TIF_ABI_PENDING); \
243 else \
244 clear_thread_flag(TIF_ABI_PENDING); \
245 if (personality(current->personality) != PER_LINUX32) \
246 set_personality(PER_LINUX | \
247 (current->personality & (~PER_MASK))); \
248} while (0)
249/*
250 * An executable for which elf_read_implies_exec() returns TRUE will
251 * have the READ_IMPLIES_EXEC personality flag set automatically. This
252 * is only required to work around bugs in old 32bit toolchains. Since
253 * the 64bit ABI has never had these issues dont enable the workaround
254 * even if we have an executable stack.
255 */
256# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
257 (exec_stk != EXSTACK_DISABLE_X) : 0)
258#else
259# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
260#endif /* __powerpc64__ */
261
262extern int dcache_bsize;
263extern int icache_bsize;
264extern int ucache_bsize;
265
266/* vDSO has arch_setup_additional_pages */
267#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
268struct linux_binprm;
269extern int arch_setup_additional_pages(struct linux_binprm *bprm,
270 int executable_stack);
271#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
272
273#endif /* __KERNEL__ */
274
275/*
276 * The requirements here are:
277 * - keep the final alignment of sp (sp & 0xf)
278 * - make sure the 32-bit value at the first 16 byte aligned position of
279 * AUXV is greater than 16 for glibc compatibility.
280 * AT_IGNOREPPC is used for that.
281 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
282 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
283 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
284 */
285#define ARCH_DLINFO \
286do { \
287 /* Handle glibc compatibility. */ \
288 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
289 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
290 /* Cache size items */ \
291 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
292 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
293 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
294 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base) \
295} while (0)
296
297/* PowerPC64 relocations defined by the ABIs */
298#define R_PPC64_NONE R_PPC_NONE
299#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
300#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
301#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
302#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
303#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
304#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
305#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
306#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
307#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
308#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
309#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
310#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
311#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
312#define R_PPC64_GOT16 R_PPC_GOT16
313#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
314#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
315#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
316
317#define R_PPC64_COPY R_PPC_COPY
318#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
319#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
320#define R_PPC64_RELATIVE R_PPC_RELATIVE
321
322#define R_PPC64_UADDR32 R_PPC_UADDR32
323#define R_PPC64_UADDR16 R_PPC_UADDR16
324#define R_PPC64_REL32 R_PPC_REL32
325#define R_PPC64_PLT32 R_PPC_PLT32
326#define R_PPC64_PLTREL32 R_PPC_PLTREL32
327#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
328#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
329#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
330
331#define R_PPC64_SECTOFF R_PPC_SECTOFF
332#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
333#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
334#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
335#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
336#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
337#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
338#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
339#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
340#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
341#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
342#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
343#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
344#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
345#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
346#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
347#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
348#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
349#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
350#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
351#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
352#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
353#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
354
355#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
356#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
357#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
358#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
359#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
360#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
361#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
362#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
363#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
364#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
365#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
366
367/* PowerPC64 relocations defined for the TLS access ABI. */
368#define R_PPC64_TLS 67 /* none (sym+add)@tls */
369#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
370#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
371#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
372#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
373#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
374#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
375#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
376#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
377#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
378#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
379#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
380#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
381#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
382#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
383#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
384#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
385#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
386#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
387#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
388#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
389#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
390#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
391#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
392#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
393#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
394#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
395#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
396#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
397#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
398#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
399#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
400#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
401#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
402#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
403#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
404#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
405#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
406#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
407#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
408
409/* Keep this the last entry. */
410#define R_PPC64_NUM 107
411
412#ifdef __KERNEL__
413
414#ifdef CONFIG_SPU_BASE
415/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
416#define NT_SPU 1
417
418#define ARCH_HAVE_EXTRA_ELF_NOTES
419
420#endif /* CONFIG_SPU_BASE */
421
422#endif /* __KERNEL */
423
424#endif /* _ASM_POWERPC_ELF_H */
diff --git a/arch/powerpc/include/asm/emergency-restart.h b/arch/powerpc/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..3711bd9d50bd
--- /dev/null
+++ b/arch/powerpc/include/asm/emergency-restart.h
@@ -0,0 +1 @@
#include <asm-generic/emergency-restart.h>
diff --git a/arch/powerpc/include/asm/errno.h b/arch/powerpc/include/asm/errno.h
new file mode 100644
index 000000000000..8c145fd17d86
--- /dev/null
+++ b/arch/powerpc/include/asm/errno.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_POWERPC_ERRNO_H
2#define _ASM_POWERPC_ERRNO_H
3
4#include <asm-generic/errno.h>
5
6#undef EDEADLOCK
7#define EDEADLOCK 58 /* File locking deadlock error */
8
9#define _LAST_ERRNO 516
10
11#endif /* _ASM_POWERPC_ERRNO_H */
diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception.h
new file mode 100644
index 000000000000..329148b5acc6
--- /dev/null
+++ b/arch/powerpc/include/asm/exception.h
@@ -0,0 +1,311 @@
1#ifndef _ASM_POWERPC_EXCEPTION_H
2#define _ASM_POWERPC_EXCEPTION_H
3/*
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27/*
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
32 *
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
36 */
37
38#define EX_R9 0
39#define EX_R10 8
40#define EX_R11 16
41#define EX_R12 24
42#define EX_R13 32
43#define EX_SRR0 40
44#define EX_DAR 48
45#define EX_DSISR 56
46#define EX_CCR 60
47#define EX_R3 64
48#define EX_LR 72
49
50/*
51 * We're short on space and time in the exception prolog, so we can't
52 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
53 * low halfword of the address, but for Kdump we need the whole low
54 * word.
55 */
56#ifdef CONFIG_CRASH_DUMP
57#define LOAD_HANDLER(reg, label) \
58 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
59 ori reg,reg,(label)@l; /* .. and the rest */
60#else
61#define LOAD_HANDLER(reg, label) \
62 ori reg,reg,(label)@l; /* virt addr of handler ... */
63#endif
64
65#define EXCEPTION_PROLOG_1(area) \
66 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
67 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
68 std r10,area+EX_R10(r13); \
69 std r11,area+EX_R11(r13); \
70 std r12,area+EX_R12(r13); \
71 mfspr r9,SPRN_SPRG1; \
72 std r9,area+EX_R13(r13); \
73 mfcr r9
74
75/*
76 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
77 * The firmware calls the registered system_reset_fwnmi and
78 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
79 * a 32bit application at the time of the event.
80 * This firmware bug is present on POWER4 and JS20.
81 */
82#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
83 EXCEPTION_PROLOG_1(area); \
84 clrrdi r12,r13,32; /* get high part of &label */ \
85 mfmsr r10; \
86 /* force 64bit mode */ \
87 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
88 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
89 /* done 64bit mode */ \
90 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
91 LOAD_HANDLER(r12,label) \
92 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
93 mtspr SPRN_SRR0,r12; \
94 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
95 mtspr SPRN_SRR1,r10; \
96 rfid; \
97 b . /* prevent speculative execution */
98
99#define EXCEPTION_PROLOG_PSERIES(area, label) \
100 EXCEPTION_PROLOG_1(area); \
101 clrrdi r12,r13,32; /* get high part of &label */ \
102 mfmsr r10; \
103 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
104 LOAD_HANDLER(r12,label) \
105 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
106 mtspr SPRN_SRR0,r12; \
107 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
108 mtspr SPRN_SRR1,r10; \
109 rfid; \
110 b . /* prevent speculative execution */
111
112/*
113 * The common exception prolog is used for all except a few exceptions
114 * such as a segment miss on a kernel address. We have to be prepared
115 * to take another exception from the point where we first touch the
116 * kernel stack onwards.
117 *
118 * On entry r13 points to the paca, r9-r13 are saved in the paca,
119 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
120 * SRR1, and relocation is on.
121 */
122#define EXCEPTION_PROLOG_COMMON(n, area) \
123 andi. r10,r12,MSR_PR; /* See if coming from user */ \
124 mr r10,r1; /* Save r1 */ \
125 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
126 beq- 1f; \
127 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
1281: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
129 bge- cr1,2f; /* abort if it is */ \
130 b 3f; \
1312: li r1,(n); /* will be reloaded later */ \
132 sth r1,PACA_TRAP_SAVE(r13); \
133 b bad_stack; \
1343: std r9,_CCR(r1); /* save CR in stackframe */ \
135 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
136 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
137 std r10,0(r1); /* make stack chain pointer */ \
138 std r0,GPR0(r1); /* save r0 in stackframe */ \
139 std r10,GPR1(r1); /* save r1 in stackframe */ \
140 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
141 std r2,GPR2(r1); /* save r2 in stackframe */ \
142 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
143 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
144 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
145 ld r10,area+EX_R10(r13); \
146 std r9,GPR9(r1); \
147 std r10,GPR10(r1); \
148 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
149 ld r10,area+EX_R12(r13); \
150 ld r11,area+EX_R13(r13); \
151 std r9,GPR11(r1); \
152 std r10,GPR12(r1); \
153 std r11,GPR13(r1); \
154 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
155 mflr r9; /* save LR in stackframe */ \
156 std r9,_LINK(r1); \
157 mfctr r10; /* save CTR in stackframe */ \
158 std r10,_CTR(r1); \
159 lbz r10,PACASOFTIRQEN(r13); \
160 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
161 std r10,SOFTE(r1); \
162 std r11,_XER(r1); \
163 li r9,(n)+1; \
164 std r9,_TRAP(r1); /* set trap number */ \
165 li r10,0; \
166 ld r11,exception_marker@toc(r2); \
167 std r10,RESULT(r1); /* clear regs->result */ \
168 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
169
170/*
171 * Exception vectors.
172 */
173#define STD_EXCEPTION_PSERIES(n, label) \
174 . = n; \
175 .globl label##_pSeries; \
176label##_pSeries: \
177 HMT_MEDIUM; \
178 mtspr SPRN_SPRG1,r13; /* save r13 */ \
179 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
180
181#define HSTD_EXCEPTION_PSERIES(n, label) \
182 . = n; \
183 .globl label##_pSeries; \
184label##_pSeries: \
185 HMT_MEDIUM; \
186 mtspr SPRN_SPRG1,r20; /* save r20 */ \
187 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
188 mtspr SPRN_SRR0,r20; \
189 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
190 mtspr SPRN_SRR1,r20; \
191 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
192 mtspr SPRN_SPRG1,r13; /* save r13 */ \
193 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
194
195
196#define MASKABLE_EXCEPTION_PSERIES(n, label) \
197 . = n; \
198 .globl label##_pSeries; \
199label##_pSeries: \
200 HMT_MEDIUM; \
201 mtspr SPRN_SPRG1,r13; /* save r13 */ \
202 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
203 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
204 std r10,PACA_EXGEN+EX_R10(r13); \
205 lbz r10,PACASOFTIRQEN(r13); \
206 mfcr r9; \
207 cmpwi r10,0; \
208 beq masked_interrupt; \
209 mfspr r10,SPRN_SPRG1; \
210 std r10,PACA_EXGEN+EX_R13(r13); \
211 std r11,PACA_EXGEN+EX_R11(r13); \
212 std r12,PACA_EXGEN+EX_R12(r13); \
213 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfmsr r10; \
215 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
216 LOAD_HANDLER(r12,label##_common) \
217 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
218 mtspr SPRN_SRR0,r12; \
219 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
220 mtspr SPRN_SRR1,r10; \
221 rfid; \
222 b . /* prevent speculative execution */
223
224#ifdef CONFIG_PPC_ISERIES
225#define DISABLE_INTS \
226 li r11,0; \
227 stb r11,PACASOFTIRQEN(r13); \
228BEGIN_FW_FTR_SECTION; \
229 stb r11,PACAHARDIRQEN(r13); \
230END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
231 TRACE_DISABLE_INTS; \
232BEGIN_FW_FTR_SECTION; \
233 mfmsr r10; \
234 ori r10,r10,MSR_EE; \
235 mtmsrd r10,1; \
236END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
237#else
238#define DISABLE_INTS \
239 li r11,0; \
240 stb r11,PACASOFTIRQEN(r13); \
241 stb r11,PACAHARDIRQEN(r13); \
242 TRACE_DISABLE_INTS
243#endif /* CONFIG_PPC_ISERIES */
244
245#define ENABLE_INTS \
246 ld r12,_MSR(r1); \
247 mfmsr r11; \
248 rlwimi r11,r12,0,MSR_EE; \
249 mtmsrd r11,1
250
251#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
252 .align 7; \
253 .globl label##_common; \
254label##_common: \
255 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
256 DISABLE_INTS; \
257 bl .save_nvgprs; \
258 addi r3,r1,STACK_FRAME_OVERHEAD; \
259 bl hdlr; \
260 b .ret_from_except
261
262/*
263 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
264 * in the idle task and therefore need the special idle handling.
265 */
266#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
267 .align 7; \
268 .globl label##_common; \
269label##_common: \
270 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
271 FINISH_NAP; \
272 DISABLE_INTS; \
273 bl .save_nvgprs; \
274 addi r3,r1,STACK_FRAME_OVERHEAD; \
275 bl hdlr; \
276 b .ret_from_except
277
278#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
279 .align 7; \
280 .globl label##_common; \
281label##_common: \
282 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
283 FINISH_NAP; \
284 DISABLE_INTS; \
285BEGIN_FTR_SECTION \
286 bl .ppc64_runlatch_on; \
287END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \
288 addi r3,r1,STACK_FRAME_OVERHEAD; \
289 bl hdlr; \
290 b .ret_from_except_lite
291
292/*
293 * When the idle code in power4_idle puts the CPU into NAP mode,
294 * it has to do so in a loop, and relies on the external interrupt
295 * and decrementer interrupt entry code to get it out of the loop.
296 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
297 * to signal that it is in the loop and needs help to get out.
298 */
299#ifdef CONFIG_PPC_970_NAP
300#define FINISH_NAP \
301BEGIN_FTR_SECTION \
302 clrrdi r11,r1,THREAD_SHIFT; \
303 ld r9,TI_LOCAL_FLAGS(r11); \
304 andi. r10,r9,_TLF_NAPPING; \
305 bnel power4_fixup_nap; \
306END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
307#else
308#define FINISH_NAP
309#endif
310
311#endif /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/arch/powerpc/include/asm/fb.h b/arch/powerpc/include/asm/fb.h
new file mode 100644
index 000000000000..411af8d17a69
--- /dev/null
+++ b/arch/powerpc/include/asm/fb.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3
4#include <linux/fb.h>
5#include <linux/fs.h>
6#include <asm/page.h>
7
8static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
9 unsigned long off)
10{
11 vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
12 vma->vm_end - vma->vm_start,
13 vma->vm_page_prot);
14}
15
16static inline int fb_is_primary_device(struct fb_info *info)
17{
18 return 0;
19}
20
21#endif /* _ASM_FB_H_ */
diff --git a/arch/powerpc/include/asm/fcntl.h b/arch/powerpc/include/asm/fcntl.h
new file mode 100644
index 000000000000..ce5c4516d404
--- /dev/null
+++ b/arch/powerpc/include/asm/fcntl.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_FCNTL_H
2#define _ASM_FCNTL_H
3
4#define O_DIRECTORY 040000 /* must be a directory */
5#define O_NOFOLLOW 0100000 /* don't follow links */
6#define O_LARGEFILE 0200000
7#define O_DIRECT 0400000 /* direct disk access hint */
8
9#include <asm-generic/fcntl.h>
10
11#endif /* _ASM_FCNTL_H */
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
new file mode 100644
index 000000000000..a1029967620b
--- /dev/null
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -0,0 +1,126 @@
1#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H
2#define __ASM_POWERPC_FEATURE_FIXUPS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifdef __ASSEMBLY__
12
13/*
14 * Feature section common macros
15 *
16 * Note that the entries now contain offsets between the table entry
17 * and the code rather than absolute code pointers in order to be
18 * useable with the vdso shared library. There is also an assumption
19 * that values will be negative, that is, the fixup table has to be
20 * located after the code it fixes up.
21 */
22#if defined(CONFIG_PPC64) && !defined(__powerpc64__)
23/* 64 bits kernel, 32 bits code (ie. vdso32) */
24#define FTR_ENTRY_LONG .llong
25#define FTR_ENTRY_OFFSET .long 0xffffffff; .long
26#else
27/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
28#define FTR_ENTRY_LONG PPC_LONG
29#define FTR_ENTRY_OFFSET PPC_LONG
30#endif
31
32#define START_FTR_SECTION(label) label##1:
33
34#define FTR_SECTION_ELSE_NESTED(label) \
35label##2: \
36 .pushsection __ftr_alt_##label,"a"; \
37 .align 2; \
38label##3:
39
40#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \
41label##4: \
42 .popsection; \
43 .pushsection sect,"a"; \
44 .align 3; \
45label##5: \
46 FTR_ENTRY_LONG msk; \
47 FTR_ENTRY_LONG val; \
48 FTR_ENTRY_OFFSET label##1b-label##5b; \
49 FTR_ENTRY_OFFSET label##2b-label##5b; \
50 FTR_ENTRY_OFFSET label##3b-label##5b; \
51 FTR_ENTRY_OFFSET label##4b-label##5b; \
52 .popsection;
53
54
55/* CPU feature dependent sections */
56#define BEGIN_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
57#define BEGIN_FTR_SECTION START_FTR_SECTION(97)
58
59#define END_FTR_SECTION_NESTED(msk, val, label) \
60 FTR_SECTION_ELSE_NESTED(label) \
61 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
62
63#define END_FTR_SECTION(msk, val) \
64 END_FTR_SECTION_NESTED(msk, val, 97)
65
66#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
67#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
68
69/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
70#define FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97)
71#define ALT_FTR_SECTION_END_NESTED(msk, val, label) \
72 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
73#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label) \
74 ALT_FTR_SECTION_END_NESTED(msk, msk, label)
75#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
76 ALT_FTR_SECTION_END_NESTED(msk, 0, label)
77#define ALT_FTR_SECTION_END(msk, val) \
78 ALT_FTR_SECTION_END_NESTED(msk, val, 97)
79#define ALT_FTR_SECTION_END_IFSET(msk) \
80 ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97)
81#define ALT_FTR_SECTION_END_IFCLR(msk) \
82 ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
83
84/* Firmware feature dependent sections */
85#define BEGIN_FW_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
86#define BEGIN_FW_FTR_SECTION START_FTR_SECTION(97)
87
88#define END_FW_FTR_SECTION_NESTED(msk, val, label) \
89 FTR_SECTION_ELSE_NESTED(label) \
90 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
91
92#define END_FW_FTR_SECTION(msk, val) \
93 END_FW_FTR_SECTION_NESTED(msk, val, 97)
94
95#define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk))
96#define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0)
97
98/* Firmware feature sections with alternatives */
99#define FW_FTR_SECTION_ELSE_NESTED(label) FTR_SECTION_ELSE_NESTED(label)
100#define FW_FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97)
101#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \
102 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
103#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label) \
104 ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label)
105#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
106 ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label)
107#define ALT_FW_FTR_SECTION_END(msk, val) \
108 ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
109#define ALT_FW_FTR_SECTION_END_IFSET(msk) \
110 ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97)
111#define ALT_FW_FTR_SECTION_END_IFCLR(msk) \
112 ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
113
114#endif /* __ASSEMBLY__ */
115
116/* LWSYNC feature sections */
117#define START_LWSYNC_SECTION(label) label##1:
118#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \
119label##2: \
120 .pushsection sect,"a"; \
121 .align 2; \
122label##3: \
123 .long label##1b-label##3b; \
124 .popsection;
125
126#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
new file mode 100644
index 000000000000..3a179827528d
--- /dev/null
+++ b/arch/powerpc/include/asm/firmware.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
3 *
4 * Modifications for ppc64:
5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef __ASM_POWERPC_FIRMWARE_H
13#define __ASM_POWERPC_FIRMWARE_H
14
15#ifdef __KERNEL__
16
17#include <asm/asm-compat.h>
18#include <asm/feature-fixups.h>
19
20/* firmware feature bitmask values */
21#define FIRMWARE_MAX_FEATURES 63
22
23#define FW_FEATURE_PFT ASM_CONST(0x0000000000000001)
24#define FW_FEATURE_TCE ASM_CONST(0x0000000000000002)
25#define FW_FEATURE_SPRG0 ASM_CONST(0x0000000000000004)
26#define FW_FEATURE_DABR ASM_CONST(0x0000000000000008)
27#define FW_FEATURE_COPY ASM_CONST(0x0000000000000010)
28#define FW_FEATURE_ASR ASM_CONST(0x0000000000000020)
29#define FW_FEATURE_DEBUG ASM_CONST(0x0000000000000040)
30#define FW_FEATURE_TERM ASM_CONST(0x0000000000000080)
31#define FW_FEATURE_PERF ASM_CONST(0x0000000000000100)
32#define FW_FEATURE_DUMP ASM_CONST(0x0000000000000200)
33#define FW_FEATURE_INTERRUPT ASM_CONST(0x0000000000000400)
34#define FW_FEATURE_MIGRATE ASM_CONST(0x0000000000000800)
35#define FW_FEATURE_PERFMON ASM_CONST(0x0000000000001000)
36#define FW_FEATURE_CRQ ASM_CONST(0x0000000000002000)
37#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
38#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
39#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
40#define FW_FEATURE_BULK ASM_CONST(0x0000000000020000)
41#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
42#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
43#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
44#define FW_FEATURE_ISERIES ASM_CONST(0x0000000000200000)
45#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
46#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
48#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0000000002000000)
49#define FW_FEATURE_CMO ASM_CONST(0x0000000004000000)
50
51#ifndef __ASSEMBLY__
52
53enum {
54#ifdef CONFIG_PPC64
55 FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
56 FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
57 FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
58 FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
59 FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
60 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
61 FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE |
62 FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | FW_FEATURE_CMO,
63 FW_FEATURE_PSERIES_ALWAYS = 0,
64 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
65 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
66 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
67 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
68 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
69 FW_FEATURE_CELLEB_ALWAYS = 0,
70 FW_FEATURE_NATIVE_POSSIBLE = 0,
71 FW_FEATURE_NATIVE_ALWAYS = 0,
72 FW_FEATURE_POSSIBLE =
73#ifdef CONFIG_PPC_PSERIES
74 FW_FEATURE_PSERIES_POSSIBLE |
75#endif
76#ifdef CONFIG_PPC_ISERIES
77 FW_FEATURE_ISERIES_POSSIBLE |
78#endif
79#ifdef CONFIG_PPC_PS3
80 FW_FEATURE_PS3_POSSIBLE |
81#endif
82#ifdef CONFIG_PPC_CELLEB
83 FW_FEATURE_CELLEB_POSSIBLE |
84#endif
85#ifdef CONFIG_PPC_NATIVE
86 FW_FEATURE_NATIVE_ALWAYS |
87#endif
88 0,
89 FW_FEATURE_ALWAYS =
90#ifdef CONFIG_PPC_PSERIES
91 FW_FEATURE_PSERIES_ALWAYS &
92#endif
93#ifdef CONFIG_PPC_ISERIES
94 FW_FEATURE_ISERIES_ALWAYS &
95#endif
96#ifdef CONFIG_PPC_PS3
97 FW_FEATURE_PS3_ALWAYS &
98#endif
99#ifdef CONFIG_PPC_CELLEB
100 FW_FEATURE_CELLEB_ALWAYS &
101#endif
102#ifdef CONFIG_PPC_NATIVE
103 FW_FEATURE_NATIVE_ALWAYS &
104#endif
105 FW_FEATURE_POSSIBLE,
106
107#else /* CONFIG_PPC64 */
108 FW_FEATURE_POSSIBLE = 0,
109 FW_FEATURE_ALWAYS = 0,
110#endif
111};
112
113/* This is used to identify firmware features which are available
114 * to the kernel.
115 */
116extern unsigned long powerpc_firmware_features;
117
118#define firmware_has_feature(feature) \
119 ((FW_FEATURE_ALWAYS & (feature)) || \
120 (FW_FEATURE_POSSIBLE & powerpc_firmware_features & (feature)))
121
122extern void system_reset_fwnmi(void);
123extern void machine_check_fwnmi(void);
124
125/* This is true if we are using the firmware NMI handler (typically LPAR) */
126extern int fwnmi_active;
127
128extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup;
129
130#endif /* __ASSEMBLY__ */
131#endif /* __KERNEL__ */
132#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
new file mode 100644
index 000000000000..8428b38a3d30
--- /dev/null
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -0,0 +1,106 @@
1/*
2 * fixmap.h: compile-time virtual memory allocation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Ingo Molnar
9 *
10 * Copyright 2008 Freescale Semiconductor Inc.
11 * Port to powerpc added by Kumar Gala
12 */
13
14#ifndef _ASM_FIXMAP_H
15#define _ASM_FIXMAP_H
16
17extern unsigned long FIXADDR_TOP;
18
19#ifndef __ASSEMBLY__
20#include <linux/kernel.h>
21#include <asm/page.h>
22#ifdef CONFIG_HIGHMEM
23#include <linux/threads.h>
24#include <asm/kmap_types.h>
25#endif
26
27/*
28 * Here we define all the compile-time 'special' virtual
29 * addresses. The point is to have a constant address at
30 * compile time, but to set the physical address only
31 * in the boot process. We allocate these special addresses
32 * from the end of virtual memory (0xfffff000) backwards.
33 * Also this lets us do fail-safe vmalloc(), we
34 * can guarantee that these special addresses and
35 * vmalloc()-ed addresses never overlap.
36 *
37 * these 'compile-time allocated' memory buffers are
38 * fixed-size 4k pages. (or larger if used with an increment
39 * highger than 1) use fixmap_set(idx,phys) to associate
40 * physical memory with fixmap indices.
41 *
42 * TLB entries of such buffers will not be flushed across
43 * task switches.
44 */
45enum fixed_addresses {
46 FIX_HOLE,
47#ifdef CONFIG_HIGHMEM
48 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
49 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
50#endif
51 /* FIX_PCIE_MCFG, */
52 __end_of_fixed_addresses
53};
54
55extern void __set_fixmap (enum fixed_addresses idx,
56 phys_addr_t phys, pgprot_t flags);
57
58#define set_fixmap(idx, phys) \
59 __set_fixmap(idx, phys, PAGE_KERNEL)
60/*
61 * Some hardware wants to get fixmapped without caching.
62 */
63#define set_fixmap_nocache(idx, phys) \
64 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
65
66#define clear_fixmap(idx) \
67 __set_fixmap(idx, 0, __pgprot(0))
68
69#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
70#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
71
72#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
73#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
74
75extern void __this_fixmap_does_not_exist(void);
76
77/*
78 * 'index to address' translation. If anyone tries to use the idx
79 * directly without tranlation, we catch the bug with a NULL-deference
80 * kernel oops. Illegal ranges of incoming indices are caught too.
81 */
82static __always_inline unsigned long fix_to_virt(const unsigned int idx)
83{
84 /*
85 * this branch gets completely eliminated after inlining,
86 * except when someone tries to use fixaddr indices in an
87 * illegal way. (such as mixing up address types or using
88 * out-of-range indices).
89 *
90 * If it doesn't get removed, the linker will complain
91 * loudly with a reasonably clear error message..
92 */
93 if (idx >= __end_of_fixed_addresses)
94 __this_fixmap_does_not_exist();
95
96 return __fix_to_virt(idx);
97}
98
99static inline unsigned long virt_to_fix(const unsigned long vaddr)
100{
101 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
102 return __virt_to_fix(vaddr);
103}
104
105#endif /* !__ASSEMBLY__ */
106#endif
diff --git a/arch/powerpc/include/asm/floppy.h b/arch/powerpc/include/asm/floppy.h
new file mode 100644
index 000000000000..24bd34c57e9d
--- /dev/null
+++ b/arch/powerpc/include/asm/floppy.h
@@ -0,0 +1,213 @@
1/*
2 * Architecture specific parts of the Floppy driver
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995
9 */
10#ifndef __ASM_POWERPC_FLOPPY_H
11#define __ASM_POWERPC_FLOPPY_H
12#ifdef __KERNEL__
13
14#include <asm/machdep.h>
15
16#define fd_inb(port) inb_p(port)
17#define fd_outb(value,port) outb_p(value,port)
18
19#define fd_enable_dma() enable_dma(FLOPPY_DMA)
20#define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA)
21#define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA)
22#define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA)
23#define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA, mode)
24#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA, count)
25#define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA)
26#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
27#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
28#define fd_cacheflush(addr,size) /* nothing */
29#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL);
30
31#include <linux/pci.h>
32#include <asm/ppc-pci.h> /* for isa_bridge_pcidev */
33
34#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io)
35
36static int fd_request_dma(void);
37
38struct fd_dma_ops {
39 void (*_disable_dma)(unsigned int dmanr);
40 void (*_free_dma)(unsigned int dmanr);
41 int (*_get_dma_residue)(unsigned int dummy);
42 int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
43};
44
45static int virtual_dma_count;
46static int virtual_dma_residue;
47static char *virtual_dma_addr;
48static int virtual_dma_mode;
49static int doing_vdma;
50static struct fd_dma_ops *fd_ops;
51
52static irqreturn_t floppy_hardint(int irq, void *dev_id)
53{
54 unsigned char st;
55 int lcount;
56 char *lptr;
57
58 if (!doing_vdma)
59 return floppy_interrupt(irq, dev_id);
60
61
62 st = 1;
63 for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
64 lcount; lcount--, lptr++) {
65 st=inb(virtual_dma_port+4) & 0xa0 ;
66 if (st != 0xa0)
67 break;
68 if (virtual_dma_mode)
69 outb_p(*lptr, virtual_dma_port+5);
70 else
71 *lptr = inb_p(virtual_dma_port+5);
72 }
73 virtual_dma_count = lcount;
74 virtual_dma_addr = lptr;
75 st = inb(virtual_dma_port+4);
76
77 if (st == 0x20)
78 return IRQ_HANDLED;
79 if (!(st & 0x20)) {
80 virtual_dma_residue += virtual_dma_count;
81 virtual_dma_count=0;
82 doing_vdma = 0;
83 floppy_interrupt(irq, dev_id);
84 return IRQ_HANDLED;
85 }
86 return IRQ_HANDLED;
87}
88
89static void vdma_disable_dma(unsigned int dummy)
90{
91 doing_vdma = 0;
92 virtual_dma_residue += virtual_dma_count;
93 virtual_dma_count=0;
94}
95
96static void vdma_nop(unsigned int dummy)
97{
98}
99
100
101static int vdma_get_dma_residue(unsigned int dummy)
102{
103 return virtual_dma_count + virtual_dma_residue;
104}
105
106
107static int fd_request_irq(void)
108{
109 if (can_use_virtual_dma)
110 return request_irq(FLOPPY_IRQ, floppy_hardint,
111 IRQF_DISABLED, "floppy", NULL);
112 else
113 return request_irq(FLOPPY_IRQ, floppy_interrupt,
114 IRQF_DISABLED, "floppy", NULL);
115}
116
117static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
118{
119 doing_vdma = 1;
120 virtual_dma_port = io;
121 virtual_dma_mode = (mode == DMA_MODE_WRITE);
122 virtual_dma_addr = addr;
123 virtual_dma_count = size;
124 virtual_dma_residue = 0;
125 return 0;
126}
127
128static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
129{
130 static unsigned long prev_size;
131 static dma_addr_t bus_addr = 0;
132 static char *prev_addr;
133 static int prev_dir;
134 int dir;
135
136 doing_vdma = 0;
137 dir = (mode == DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
138
139 if (bus_addr
140 && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
141 /* different from last time -- unmap prev */
142 pci_unmap_single(isa_bridge_pcidev, bus_addr, prev_size, prev_dir);
143 bus_addr = 0;
144 }
145
146 if (!bus_addr) /* need to map it */
147 bus_addr = pci_map_single(isa_bridge_pcidev, addr, size, dir);
148
149 /* remember this one as prev */
150 prev_addr = addr;
151 prev_size = size;
152 prev_dir = dir;
153
154 fd_clear_dma_ff();
155 fd_cacheflush(addr, size);
156 fd_set_dma_mode(mode);
157 set_dma_addr(FLOPPY_DMA, bus_addr);
158 fd_set_dma_count(size);
159 virtual_dma_port = io;
160 fd_enable_dma();
161
162 return 0;
163}
164
165static struct fd_dma_ops real_dma_ops =
166{
167 ._disable_dma = disable_dma,
168 ._free_dma = free_dma,
169 ._get_dma_residue = get_dma_residue,
170 ._dma_setup = hard_dma_setup
171};
172
173static struct fd_dma_ops virt_dma_ops =
174{
175 ._disable_dma = vdma_disable_dma,
176 ._free_dma = vdma_nop,
177 ._get_dma_residue = vdma_get_dma_residue,
178 ._dma_setup = vdma_dma_setup
179};
180
181static int fd_request_dma(void)
182{
183 if (can_use_virtual_dma & 1) {
184 fd_ops = &virt_dma_ops;
185 return 0;
186 }
187 else {
188 fd_ops = &real_dma_ops;
189 return request_dma(FLOPPY_DMA, "floppy");
190 }
191}
192
193static int FDC1 = 0x3f0;
194static int FDC2 = -1;
195
196/*
197 * Again, the CMOS information not available
198 */
199#define FLOPPY0_TYPE 6
200#define FLOPPY1_TYPE 0
201
202#define N_FDC 2 /* Don't change this! */
203#define N_DRIVE 8
204
205/*
206 * The PowerPC has no problems with floppy DMA crossing 64k borders.
207 */
208#define CROSS_64KB(a,s) (0)
209
210#define EXTRA_FLOPPY_PARAMS
211
212#endif /* __KERNEL__ */
213#endif /* __ASM_POWERPC_FLOPPY_H */
diff --git a/arch/powerpc/include/asm/fs_pd.h b/arch/powerpc/include/asm/fs_pd.h
new file mode 100644
index 000000000000..9361cd5342cc
--- /dev/null
+++ b/arch/powerpc/include/asm/fs_pd.h
@@ -0,0 +1,50 @@
1/*
2 * Platform information definitions.
3 *
4 * 2006 (c) MontaVista Software, Inc.
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifndef FS_PD_H
13#define FS_PD_H
14#include <sysdev/fsl_soc.h>
15#include <asm/time.h>
16
17#ifdef CONFIG_CPM2
18#include <asm/cpm2.h>
19
20#if defined(CONFIG_8260)
21#include <asm/mpc8260.h>
22#endif
23
24#define cpm2_map(member) (&cpm2_immr->member)
25#define cpm2_map_size(member, size) (&cpm2_immr->member)
26#define cpm2_unmap(addr) do {} while(0)
27#endif
28
29#ifdef CONFIG_8xx
30#include <asm/8xx_immap.h>
31#include <asm/mpc8xx.h>
32
33extern immap_t __iomem *mpc8xx_immr;
34
35#define immr_map(member) (&mpc8xx_immr->member)
36#define immr_map_size(member, size) (&mpc8xx_immr->member)
37#define immr_unmap(addr) do {} while (0)
38#endif
39
40static inline int uart_baudrate(void)
41{
42 return get_baudrate();
43}
44
45static inline int uart_clock(void)
46{
47 return ppc_proc_freq;
48}
49
50#endif
diff --git a/arch/powerpc/include/asm/fsl_gtm.h b/arch/powerpc/include/asm/fsl_gtm.h
new file mode 100644
index 000000000000..8e8c9b5032d3
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_gtm.h
@@ -0,0 +1,47 @@
1/*
2 * Freescale General-purpose Timers Module
3 *
4 * Copyright (c) Freescale Semicondutor, Inc. 2006.
5 * Shlomi Gridish <gridish@freescale.com>
6 * Jerry Huang <Chang-Ming.Huang@freescale.com>
7 * Copyright (c) MontaVista Software, Inc. 2008.
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifndef __ASM_FSL_GTM_H
17#define __ASM_FSL_GTM_H
18
19#include <linux/types.h>
20
21struct gtm;
22
23struct gtm_timer {
24 unsigned int irq;
25
26 struct gtm *gtm;
27 bool requested;
28 u8 __iomem *gtcfr;
29 __be16 __iomem *gtmdr;
30 __be16 __iomem *gtpsr;
31 __be16 __iomem *gtcnr;
32 __be16 __iomem *gtrfr;
33 __be16 __iomem *gtevr;
34};
35
36extern struct gtm_timer *gtm_get_timer16(void);
37extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm,
38 unsigned int timer);
39extern void gtm_put_timer16(struct gtm_timer *tmr);
40extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec,
41 bool reload);
42extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec,
43 bool reload);
44extern void gtm_stop_timer16(struct gtm_timer *tmr);
45extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events);
46
47#endif /* __ASM_FSL_GTM_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
new file mode 100644
index 000000000000..303f5484c050
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -0,0 +1,311 @@
1/* Freescale Local Bus Controller
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_FSL_LBC_H
24#define __ASM_FSL_LBC_H
25
26#include <linux/types.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29
30struct fsl_lbc_bank {
31 __be32 br; /**< Base Register */
32#define BR_BA 0xFFFF8000
33#define BR_BA_SHIFT 15
34#define BR_PS 0x00001800
35#define BR_PS_SHIFT 11
36#define BR_PS_8 0x00000800 /* Port Size 8 bit */
37#define BR_PS_16 0x00001000 /* Port Size 16 bit */
38#define BR_PS_32 0x00001800 /* Port Size 32 bit */
39#define BR_DECC 0x00000600
40#define BR_DECC_SHIFT 9
41#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
42#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
43#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
44#define BR_WP 0x00000100
45#define BR_WP_SHIFT 8
46#define BR_MSEL 0x000000E0
47#define BR_MSEL_SHIFT 5
48#define BR_MS_GPCM 0x00000000 /* GPCM */
49#define BR_MS_FCM 0x00000020 /* FCM */
50#define BR_MS_SDRAM 0x00000060 /* SDRAM */
51#define BR_MS_UPMA 0x00000080 /* UPMA */
52#define BR_MS_UPMB 0x000000A0 /* UPMB */
53#define BR_MS_UPMC 0x000000C0 /* UPMC */
54#define BR_V 0x00000001
55#define BR_V_SHIFT 0
56#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
57
58 __be32 or; /**< Base Register */
59#define OR0 0x5004
60#define OR1 0x500C
61#define OR2 0x5014
62#define OR3 0x501C
63#define OR4 0x5024
64#define OR5 0x502C
65#define OR6 0x5034
66#define OR7 0x503C
67
68#define OR_FCM_AM 0xFFFF8000
69#define OR_FCM_AM_SHIFT 15
70#define OR_FCM_BCTLD 0x00001000
71#define OR_FCM_BCTLD_SHIFT 12
72#define OR_FCM_PGS 0x00000400
73#define OR_FCM_PGS_SHIFT 10
74#define OR_FCM_CSCT 0x00000200
75#define OR_FCM_CSCT_SHIFT 9
76#define OR_FCM_CST 0x00000100
77#define OR_FCM_CST_SHIFT 8
78#define OR_FCM_CHT 0x00000080
79#define OR_FCM_CHT_SHIFT 7
80#define OR_FCM_SCY 0x00000070
81#define OR_FCM_SCY_SHIFT 4
82#define OR_FCM_SCY_1 0x00000010
83#define OR_FCM_SCY_2 0x00000020
84#define OR_FCM_SCY_3 0x00000030
85#define OR_FCM_SCY_4 0x00000040
86#define OR_FCM_SCY_5 0x00000050
87#define OR_FCM_SCY_6 0x00000060
88#define OR_FCM_SCY_7 0x00000070
89#define OR_FCM_RST 0x00000008
90#define OR_FCM_RST_SHIFT 3
91#define OR_FCM_TRLX 0x00000004
92#define OR_FCM_TRLX_SHIFT 2
93#define OR_FCM_EHTR 0x00000002
94#define OR_FCM_EHTR_SHIFT 1
95};
96
97struct fsl_lbc_regs {
98 struct fsl_lbc_bank bank[8];
99 u8 res0[0x28];
100 __be32 mar; /**< UPM Address Register */
101 u8 res1[0x4];
102 __be32 mamr; /**< UPMA Mode Register */
103#define MxMR_OP_NO (0 << 28) /**< normal operation */
104#define MxMR_OP_WA (1 << 28) /**< write array */
105#define MxMR_OP_RA (2 << 28) /**< read array */
106#define MxMR_OP_RP (3 << 28) /**< run pattern */
107#define MxMR_MAD 0x3f /**< machine address */
108 __be32 mbmr; /**< UPMB Mode Register */
109 __be32 mcmr; /**< UPMC Mode Register */
110 u8 res2[0x8];
111 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
112 __be32 mdr; /**< UPM Data Register */
113 u8 res3[0x4];
114 __be32 lsor; /**< Special Operation Initiation Register */
115 __be32 lsdmr; /**< SDRAM Mode Register */
116 u8 res4[0x8];
117 __be32 lurt; /**< UPM Refresh Timer */
118 __be32 lsrt; /**< SDRAM Refresh Timer */
119 u8 res5[0x8];
120 __be32 ltesr; /**< Transfer Error Status Register */
121#define LTESR_BM 0x80000000
122#define LTESR_FCT 0x40000000
123#define LTESR_PAR 0x20000000
124#define LTESR_WP 0x04000000
125#define LTESR_ATMW 0x00800000
126#define LTESR_ATMR 0x00400000
127#define LTESR_CS 0x00080000
128#define LTESR_CC 0x00000001
129#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
130 __be32 ltedr; /**< Transfer Error Disable Register */
131 __be32 lteir; /**< Transfer Error Interrupt Register */
132 __be32 lteatr; /**< Transfer Error Attributes Register */
133 __be32 ltear; /**< Transfer Error Address Register */
134 u8 res6[0xC];
135 __be32 lbcr; /**< Configuration Register */
136#define LBCR_LDIS 0x80000000
137#define LBCR_LDIS_SHIFT 31
138#define LBCR_BCTLC 0x00C00000
139#define LBCR_BCTLC_SHIFT 22
140#define LBCR_AHD 0x00200000
141#define LBCR_LPBSE 0x00020000
142#define LBCR_LPBSE_SHIFT 17
143#define LBCR_EPAR 0x00010000
144#define LBCR_EPAR_SHIFT 16
145#define LBCR_BMT 0x0000FF00
146#define LBCR_BMT_SHIFT 8
147#define LBCR_INIT 0x00040000
148 __be32 lcrr; /**< Clock Ratio Register */
149#define LCRR_DBYP 0x80000000
150#define LCRR_DBYP_SHIFT 31
151#define LCRR_BUFCMDC 0x30000000
152#define LCRR_BUFCMDC_SHIFT 28
153#define LCRR_ECL 0x03000000
154#define LCRR_ECL_SHIFT 24
155#define LCRR_EADC 0x00030000
156#define LCRR_EADC_SHIFT 16
157#define LCRR_CLKDIV 0x0000000F
158#define LCRR_CLKDIV_SHIFT 0
159 u8 res7[0x8];
160 __be32 fmr; /**< Flash Mode Register */
161#define FMR_CWTO 0x0000F000
162#define FMR_CWTO_SHIFT 12
163#define FMR_BOOT 0x00000800
164#define FMR_ECCM 0x00000100
165#define FMR_AL 0x00000030
166#define FMR_AL_SHIFT 4
167#define FMR_OP 0x00000003
168#define FMR_OP_SHIFT 0
169 __be32 fir; /**< Flash Instruction Register */
170#define FIR_OP0 0xF0000000
171#define FIR_OP0_SHIFT 28
172#define FIR_OP1 0x0F000000
173#define FIR_OP1_SHIFT 24
174#define FIR_OP2 0x00F00000
175#define FIR_OP2_SHIFT 20
176#define FIR_OP3 0x000F0000
177#define FIR_OP3_SHIFT 16
178#define FIR_OP4 0x0000F000
179#define FIR_OP4_SHIFT 12
180#define FIR_OP5 0x00000F00
181#define FIR_OP5_SHIFT 8
182#define FIR_OP6 0x000000F0
183#define FIR_OP6_SHIFT 4
184#define FIR_OP7 0x0000000F
185#define FIR_OP7_SHIFT 0
186#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
187#define FIR_OP_CA 0x1 /* Issue current column address */
188#define FIR_OP_PA 0x2 /* Issue current block+page address */
189#define FIR_OP_UA 0x3 /* Issue user defined address */
190#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
191#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
192#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
193#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
194#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
195#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
196#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
197#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
198#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
199#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
200#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
201#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
202 __be32 fcr; /**< Flash Command Register */
203#define FCR_CMD0 0xFF000000
204#define FCR_CMD0_SHIFT 24
205#define FCR_CMD1 0x00FF0000
206#define FCR_CMD1_SHIFT 16
207#define FCR_CMD2 0x0000FF00
208#define FCR_CMD2_SHIFT 8
209#define FCR_CMD3 0x000000FF
210#define FCR_CMD3_SHIFT 0
211 __be32 fbar; /**< Flash Block Address Register */
212#define FBAR_BLK 0x00FFFFFF
213 __be32 fpar; /**< Flash Page Address Register */
214#define FPAR_SP_PI 0x00007C00
215#define FPAR_SP_PI_SHIFT 10
216#define FPAR_SP_MS 0x00000200
217#define FPAR_SP_CI 0x000001FF
218#define FPAR_SP_CI_SHIFT 0
219#define FPAR_LP_PI 0x0003F000
220#define FPAR_LP_PI_SHIFT 12
221#define FPAR_LP_MS 0x00000800
222#define FPAR_LP_CI 0x000007FF
223#define FPAR_LP_CI_SHIFT 0
224 __be32 fbcr; /**< Flash Byte Count Register */
225#define FBCR_BC 0x00000FFF
226 u8 res11[0x8];
227 u8 res8[0xF00];
228};
229
230extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
231extern spinlock_t fsl_lbc_lock;
232
233/*
234 * FSL UPM routines
235 */
236struct fsl_upm {
237 __be32 __iomem *mxmr;
238 int width;
239};
240
241extern int fsl_lbc_find(phys_addr_t addr_base);
242extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
243
244/**
245 * fsl_upm_start_pattern - start UPM patterns execution
246 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
247 * @pat_offset: UPM pattern offset for the command to be executed
248 *
249 * This routine programmes UPM so the next memory access that hits an UPM
250 * will trigger pattern execution, starting at pat_offset.
251 */
252static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
253{
254 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
255}
256
257/**
258 * fsl_upm_end_pattern - end UPM patterns execution
259 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
260 *
261 * This routine reverts UPM to normal operation mode.
262 */
263static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
264{
265 clrbits32(upm->mxmr, MxMR_OP_RP);
266
267 while (in_be32(upm->mxmr) & MxMR_OP_RP)
268 cpu_relax();
269}
270
271/**
272 * fsl_upm_run_pattern - actually run an UPM pattern
273 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
274 * @io_base: remapped pointer to where memory access should happen
275 * @mar: MAR register content during pattern execution
276 *
277 * This function triggers dummy write to the memory specified by the io_base,
278 * thus UPM pattern actually executed. Note that mar usage depends on the
279 * pre-programmed AMX bits in the UPM RAM.
280 */
281static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
282 void __iomem *io_base, u32 mar)
283{
284 int ret = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&fsl_lbc_lock, flags);
288
289 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
290
291 switch (upm->width) {
292 case 8:
293 out_8(io_base, 0x0);
294 break;
295 case 16:
296 out_be16(io_base, 0x0);
297 break;
298 case 32:
299 out_be32(io_base, 0x0);
300 break;
301 default:
302 ret = -EINVAL;
303 break;
304 }
305
306 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
307
308 return ret;
309}
310
311#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h
new file mode 100644
index 000000000000..de921326cca8
--- /dev/null
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_POWERPC_FTRACE
2#define _ASM_POWERPC_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(_mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void _mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
new file mode 100644
index 000000000000..6d406c5c5de4
--- /dev/null
+++ b/arch/powerpc/include/asm/futex.h
@@ -0,0 +1,117 @@
1#ifndef _ASM_POWERPC_FUTEX_H
2#define _ASM_POWERPC_FUTEX_H
3
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9#include <asm/synch.h>
10#include <asm/asm-compat.h>
11
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
13 __asm__ __volatile ( \
14 LWSYNC_ON_SMP \
15"1: lwarx %0,0,%2\n" \
16 insn \
17 PPC405_ERR77(0, %2) \
18"2: stwcx. %1,0,%2\n" \
19 "bne- 1b\n" \
20 "li %1,0\n" \
21"3: .section .fixup,\"ax\"\n" \
22"4: li %1,%3\n" \
23 "b 3b\n" \
24 ".previous\n" \
25 ".section __ex_table,\"a\"\n" \
26 ".align 3\n" \
27 PPC_LONG "1b,4b,2b,4b\n" \
28 ".previous" \
29 : "=&r" (oldval), "=&r" (ret) \
30 : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \
31 : "cr0", "memory")
32
33static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
34{
35 int op = (encoded_op >> 28) & 7;
36 int cmp = (encoded_op >> 24) & 15;
37 int oparg = (encoded_op << 8) >> 20;
38 int cmparg = (encoded_op << 20) >> 20;
39 int oldval = 0, ret;
40 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
41 oparg = 1 << oparg;
42
43 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
44 return -EFAULT;
45
46 pagefault_disable();
47
48 switch (op) {
49 case FUTEX_OP_SET:
50 __futex_atomic_op("", ret, oldval, uaddr, oparg);
51 break;
52 case FUTEX_OP_ADD:
53 __futex_atomic_op("add %1,%0,%1\n", ret, oldval, uaddr, oparg);
54 break;
55 case FUTEX_OP_OR:
56 __futex_atomic_op("or %1,%0,%1\n", ret, oldval, uaddr, oparg);
57 break;
58 case FUTEX_OP_ANDN:
59 __futex_atomic_op("andc %1,%0,%1\n", ret, oldval, uaddr, oparg);
60 break;
61 case FUTEX_OP_XOR:
62 __futex_atomic_op("xor %1,%0,%1\n", ret, oldval, uaddr, oparg);
63 break;
64 default:
65 ret = -ENOSYS;
66 }
67
68 pagefault_enable();
69
70 if (!ret) {
71 switch (cmp) {
72 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
73 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
74 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
75 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
76 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
77 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
78 default: ret = -ENOSYS;
79 }
80 }
81 return ret;
82}
83
84static inline int
85futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
86{
87 int prev;
88
89 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
90 return -EFAULT;
91
92 __asm__ __volatile__ (
93 LWSYNC_ON_SMP
94"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\
95 cmpw 0,%0,%3\n\
96 bne- 3f\n"
97 PPC405_ERR77(0,%2)
98"2: stwcx. %4,0,%2\n\
99 bne- 1b\n"
100 ISYNC_ON_SMP
101"3: .section .fixup,\"ax\"\n\
1024: li %0,%5\n\
103 b 3b\n\
104 .previous\n\
105 .section __ex_table,\"a\"\n\
106 .align 3\n\
107 " PPC_LONG "1b,4b,2b,4b\n\
108 .previous" \
109 : "=&r" (prev), "+m" (*uaddr)
110 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
111 : "cc", "memory");
112
113 return prev;
114}
115
116#endif /* __KERNEL__ */
117#endif /* _ASM_POWERPC_FUTEX_H */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
new file mode 100644
index 000000000000..ea04632399d8
--- /dev/null
+++ b/arch/powerpc/include/asm/gpio.h
@@ -0,0 +1,56 @@
1/*
2 * Generic GPIO API implementation for PowerPC.
3 *
4 * Copyright (c) 2007-2008 MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_POWERPC_GPIO_H
15#define __ASM_POWERPC_GPIO_H
16
17#include <linux/errno.h>
18#include <asm-generic/gpio.h>
19
20#ifdef CONFIG_GPIOLIB
21
22/*
23 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41/*
42 * Not implemented, yet.
43 */
44static inline int gpio_to_irq(unsigned int gpio)
45{
46 return -ENOSYS;
47}
48
49static inline int irq_to_gpio(unsigned int irq)
50{
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
56#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/arch/powerpc/include/asm/grackle.h b/arch/powerpc/include/asm/grackle.h
new file mode 100644
index 000000000000..bd7812a519d4
--- /dev/null
+++ b/arch/powerpc/include/asm/grackle.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_POWERPC_GRACKLE_H
2#define _ASM_POWERPC_GRACKLE_H
3#ifdef __KERNEL__
4/*
5 * Functions for setting up and using a MPC106 northbridge
6 */
7
8#include <asm/pci-bridge.h>
9
10extern void setup_grackle(struct pci_controller *hose);
11#endif /* __KERNEL__ */
12#endif /* _ASM_POWERPC_GRACKLE_H */
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
new file mode 100644
index 000000000000..288e14d53b7f
--- /dev/null
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -0,0 +1,29 @@
1#ifndef _ASM_POWERPC_HARDIRQ_H
2#define _ASM_POWERPC_HARDIRQ_H
3#ifdef __KERNEL__
4
5#include <asm/irq.h>
6#include <asm/bug.h>
7
8/* The __last_jiffy_stamp field is needed to ensure that no decrementer
9 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
10 * cache line as local_irq_count, it is cheap to access and is also used on UP
11 * for uniformity.
12 */
13typedef struct {
14 unsigned int __softirq_pending; /* set_bit is used on this */
15 unsigned int __last_jiffy_stamp;
16} ____cacheline_aligned irq_cpustat_t;
17
18#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
19
20#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
21
22static inline void ack_bad_irq(int irq)
23{
24 printk(KERN_CRIT "illegal vector %d received!\n", irq);
25 BUG();
26}
27
28#endif /* __KERNEL__ */
29#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/arch/powerpc/include/asm/heathrow.h b/arch/powerpc/include/asm/heathrow.h
new file mode 100644
index 000000000000..93f54958a9d1
--- /dev/null
+++ b/arch/powerpc/include/asm/heathrow.h
@@ -0,0 +1,67 @@
1#ifndef _ASM_POWERPC_HEATHROW_H
2#define _ASM_POWERPC_HEATHROW_H
3#ifdef __KERNEL__
4/*
5 * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
6 *
7 * Grabbed from Open Firmware definitions on a PowerBook G3 Series
8 *
9 * Copyright (C) 1997 Paul Mackerras.
10 */
11
12/* Front light color on Yikes/B&W G3. 32 bits */
13#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
14
15/* Brightness/contrast (gossamer iMac ?). 8 bits */
16#define HEATHROW_BRIGHTNESS_CNTL 0x32
17#define HEATHROW_CONTRAST_CNTL 0x33
18
19/* offset from ohare base for feature control register */
20#define HEATHROW_MBCR 0x34 /* Media bay control */
21#define HEATHROW_FCR 0x38 /* Feature control */
22#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
23
24/*
25 * Bits in feature control register.
26 * Bits postfixed with a _N are in inverse logic
27 */
28#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
29#define HRW_BAY_POWER_N 0x00000002
30#define HRW_BAY_PCI_ENABLE 0x00000004
31#define HRW_BAY_IDE_ENABLE 0x00000008
32#define HRW_BAY_FLOPPY_ENABLE 0x00000010
33#define HRW_IDE0_ENABLE 0x00000020
34#define HRW_IDE0_RESET_N 0x00000040
35#define HRW_BAY_DEV_MASK 0x0000001c
36#define HRW_BAY_RESET_N 0x00000080
37#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
38#define HRW_SCC_ENABLE 0x00000200
39#define HRW_MESH_ENABLE 0x00000400
40#define HRW_SWIM_ENABLE 0x00000800
41#define HRW_SOUND_POWER_N 0x00001000
42#define HRW_SOUND_CLK_ENABLE 0x00002000
43#define HRW_SCCA_IO 0x00004000
44#define HRW_SCCB_IO 0x00008000
45#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
46#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
47#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
48#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
49#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
50#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
51#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
52#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
53#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
54#define HRW_RESET_SCC 0x02000000
55#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
56#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
57#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
58#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
59
60/* We OR those features at boot on desktop G3s */
61#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
62
63/* Looks like Heathrow has some sort of GPIOs as well... */
64#define HRW_GPIO_MODEM_RESET 0x6d
65
66#endif /* __KERNEL__ */
67#endif /* _ASM_POWERPC_HEATHROW_H */
diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h
new file mode 100644
index 000000000000..5d99b6489d56
--- /dev/null
+++ b/arch/powerpc/include/asm/highmem.h
@@ -0,0 +1,138 @@
1/*
2 * highmem.h: virtual kernel memory mappings for high memory
3 *
4 * PowerPC version, stolen from the i386 version.
5 *
6 * Used in CONFIG_HIGHMEM systems for memory pages which
7 * are not addressable by direct kernel virtual addresses.
8 *
9 * Copyright (C) 1999 Gerhard Wichert, Siemens AG
10 * Gerhard.Wichert@pdb.siemens.de
11 *
12 *
13 * Redesigned the x86 32-bit VM architecture to deal with
14 * up to 16 Terrabyte physical memory. With current x86 CPUs
15 * we now support up to 64 Gigabytes physical RAM.
16 *
17 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
18 */
19
20#ifndef _ASM_HIGHMEM_H
21#define _ASM_HIGHMEM_H
22
23#ifdef __KERNEL__
24
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <asm/kmap_types.h>
28#include <asm/tlbflush.h>
29#include <asm/page.h>
30#include <asm/fixmap.h>
31
32extern pte_t *kmap_pte;
33extern pgprot_t kmap_prot;
34extern pte_t *pkmap_page_table;
35
36/*
37 * Right now we initialize only a single pte table. It can be extended
38 * easily, subsequent pte tables have to be allocated in one physical
39 * chunk of RAM.
40 */
41#define LAST_PKMAP (1 << PTE_SHIFT)
42#define LAST_PKMAP_MASK (LAST_PKMAP-1)
43#define PKMAP_BASE ((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
44#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
45#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
46
47extern void *kmap_high(struct page *page);
48extern void kunmap_high(struct page *page);
49
50static inline void *kmap(struct page *page)
51{
52 might_sleep();
53 if (!PageHighMem(page))
54 return page_address(page);
55 return kmap_high(page);
56}
57
58static inline void kunmap(struct page *page)
59{
60 BUG_ON(in_interrupt());
61 if (!PageHighMem(page))
62 return;
63 kunmap_high(page);
64}
65
66/*
67 * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
68 * gives a more generic (and caching) interface. But kmap_atomic can
69 * be used in IRQ contexts, so in some (very limited) cases we need
70 * it.
71 */
72static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
73{
74 unsigned int idx;
75 unsigned long vaddr;
76
77 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
78 pagefault_disable();
79 if (!PageHighMem(page))
80 return page_address(page);
81
82 idx = type + KM_TYPE_NR*smp_processor_id();
83 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
84#ifdef CONFIG_DEBUG_HIGHMEM
85 BUG_ON(!pte_none(*(kmap_pte-idx)));
86#endif
87 set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
88 flush_tlb_page(NULL, vaddr);
89
90 return (void*) vaddr;
91}
92
93static inline void *kmap_atomic(struct page *page, enum km_type type)
94{
95 return kmap_atomic_prot(page, type, kmap_prot);
96}
97
98static inline void kunmap_atomic(void *kvaddr, enum km_type type)
99{
100#ifdef CONFIG_DEBUG_HIGHMEM
101 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
102 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
103
104 if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
105 pagefault_enable();
106 return;
107 }
108
109 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
110
111 /*
112 * force other mappings to Oops if they'll try to access
113 * this pte without first remap it
114 */
115 pte_clear(&init_mm, vaddr, kmap_pte-idx);
116 flush_tlb_page(NULL, vaddr);
117#endif
118 pagefault_enable();
119}
120
121static inline struct page *kmap_atomic_to_page(void *ptr)
122{
123 unsigned long idx, vaddr = (unsigned long) ptr;
124 pte_t *pte;
125
126 if (vaddr < FIXADDR_START)
127 return virt_to_page(ptr);
128
129 idx = virt_to_fix(vaddr);
130 pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
131 return pte_page(*pte);
132}
133
134#define flush_cache_kmaps() flush_cache_all()
135
136#endif /* __KERNEL__ */
137
138#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
new file mode 100644
index 000000000000..26f0d0ab27a5
--- /dev/null
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -0,0 +1,75 @@
1#ifndef _ASM_POWERPC_HUGETLB_H
2#define _ASM_POWERPC_HUGETLB_H
3
4#include <asm/page.h>
5
6
7int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
8 unsigned long len);
9
10void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
11 unsigned long end, unsigned long floor,
12 unsigned long ceiling);
13
14void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
15 pte_t *ptep, pte_t pte);
16
17pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
18 pte_t *ptep);
19
20/*
21 * If the arch doesn't supply something else, assume that hugepage
22 * size aligned regions are ok without further preparation.
23 */
24static inline int prepare_hugepage_range(struct file *file,
25 unsigned long addr, unsigned long len)
26{
27 struct hstate *h = hstate_file(file);
28 if (len & ~huge_page_mask(h))
29 return -EINVAL;
30 if (addr & ~huge_page_mask(h))
31 return -EINVAL;
32 return 0;
33}
34
35static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
36{
37}
38
39static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
40 unsigned long addr, pte_t *ptep)
41{
42}
43
44static inline int huge_pte_none(pte_t pte)
45{
46 return pte_none(pte);
47}
48
49static inline pte_t huge_pte_wrprotect(pte_t pte)
50{
51 return pte_wrprotect(pte);
52}
53
54static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
55 unsigned long addr, pte_t *ptep,
56 pte_t pte, int dirty)
57{
58 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
59}
60
61static inline pte_t huge_ptep_get(pte_t *ptep)
62{
63 return *ptep;
64}
65
66static inline int arch_prepare_hugepage(struct page *page)
67{
68 return 0;
69}
70
71static inline void arch_release_hugepage(struct page *page)
72{
73}
74
75#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
new file mode 100644
index 000000000000..fbe2932fa9e9
--- /dev/null
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -0,0 +1,296 @@
1#ifndef _ASM_POWERPC_HVCALL_H
2#define _ASM_POWERPC_HVCALL_H
3#ifdef __KERNEL__
4
5#define HVSC .long 0x44000022
6
7#define H_SUCCESS 0
8#define H_BUSY 1 /* Hardware busy -- retry later */
9#define H_CLOSED 2 /* Resource closed */
10#define H_NOT_AVAILABLE 3
11#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
12#define H_PARTIAL 5
13#define H_IN_PROGRESS 14 /* Kind of like busy */
14#define H_PAGE_REGISTERED 15
15#define H_PARTIAL_STORE 16
16#define H_PENDING 17 /* returned from H_POLL_PENDING */
17#define H_CONTINUE 18 /* Returned from H_Join on success */
18#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
19#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
20 is a good time to retry */
21#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
22 is a good time to retry */
23#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
24 is a good time to retry */
25#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
26 is a good time to retry */
27#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
28 is a good time to retry */
29#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
30 is a good time to retry */
31#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
32#define H_HARDWARE -1 /* Hardware error */
33#define H_FUNCTION -2 /* Function not supported */
34#define H_PRIVILEGE -3 /* Caller not privileged */
35#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
36#define H_BAD_MODE -5 /* Illegal msr value */
37#define H_PTEG_FULL -6 /* PTEG is full */
38#define H_NOT_FOUND -7 /* PTE was not found" */
39#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
40#define H_NO_MEM -9
41#define H_AUTHORITY -10
42#define H_PERMISSION -11
43#define H_DROPPED -12
44#define H_SOURCE_PARM -13
45#define H_DEST_PARM -14
46#define H_REMOTE_PARM -15
47#define H_RESOURCE -16
48#define H_ADAPTER_PARM -17
49#define H_RH_PARM -18
50#define H_RCQ_PARM -19
51#define H_SCQ_PARM -20
52#define H_EQ_PARM -21
53#define H_RT_PARM -22
54#define H_ST_PARM -23
55#define H_SIGT_PARM -24
56#define H_TOKEN_PARM -25
57#define H_MLENGTH_PARM -27
58#define H_MEM_PARM -28
59#define H_MEM_ACCESS_PARM -29
60#define H_ATTR_PARM -30
61#define H_PORT_PARM -31
62#define H_MCG_PARM -32
63#define H_VL_PARM -33
64#define H_TSIZE_PARM -34
65#define H_TRACE_PARM -35
66
67#define H_MASK_PARM -37
68#define H_MCG_FULL -38
69#define H_ALIAS_EXIST -39
70#define H_P_COUNTER -40
71#define H_TABLE_FULL -41
72#define H_ALT_TABLE -42
73#define H_MR_CONDITION -43
74#define H_NOT_ENOUGH_RESOURCES -44
75#define H_R_STATE -45
76#define H_RESCINDEND -46
77
78
79/* Long Busy is a condition that can be returned by the firmware
80 * when a call cannot be completed now, but the identical call
81 * should be retried later. This prevents calls blocking in the
82 * firmware for long periods of time. Annoyingly the firmware can return
83 * a range of return codes, hinting at how long we should wait before
84 * retrying. If you don't care for the hint, the macro below is a good
85 * way to check for the long_busy return codes
86 */
87#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
88 && (x <= H_LONG_BUSY_END_RANGE))
89
90/* Flags */
91#define H_LARGE_PAGE (1UL<<(63-16))
92#define H_EXACT (1UL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
93#define H_R_XLATE (1UL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
94#define H_READ_4 (1UL<<(63-26)) /* Return 4 PTEs */
95#define H_PAGE_STATE_CHANGE (1UL<<(63-28))
96#define H_PAGE_UNUSED ((1UL<<(63-29)) | (1UL<<(63-30)))
97#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
98#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1UL<<(63-31)))
99#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
100#define H_AVPN (1UL<<(63-32)) /* An avpn is provided as a sanity test */
101#define H_ANDCOND (1UL<<(63-33))
102#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
103#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
104#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
105#define H_COPY_PAGE (1UL<<(63-49))
106#define H_N (1UL<<(63-61))
107#define H_PP1 (1UL<<(63-62))
108#define H_PP2 (1UL<<(63-63))
109
110/* VASI States */
111#define H_VASI_INVALID 0
112#define H_VASI_ENABLED 1
113#define H_VASI_ABORTED 2
114#define H_VASI_SUSPENDING 3
115#define H_VASI_SUSPENDED 4
116#define H_VASI_RESUMED 5
117#define H_VASI_COMPLETED 6
118
119/* DABRX flags */
120#define H_DABRX_HYPERVISOR (1UL<<(63-61))
121#define H_DABRX_KERNEL (1UL<<(63-62))
122#define H_DABRX_USER (1UL<<(63-63))
123
124/* Each control block has to be on a 4K bondary */
125#define H_CB_ALIGNMENT 4096
126
127/* pSeries hypervisor opcodes */
128#define H_REMOVE 0x04
129#define H_ENTER 0x08
130#define H_READ 0x0c
131#define H_CLEAR_MOD 0x10
132#define H_CLEAR_REF 0x14
133#define H_PROTECT 0x18
134#define H_GET_TCE 0x1c
135#define H_PUT_TCE 0x20
136#define H_SET_SPRG0 0x24
137#define H_SET_DABR 0x28
138#define H_PAGE_INIT 0x2c
139#define H_SET_ASR 0x30
140#define H_ASR_ON 0x34
141#define H_ASR_OFF 0x38
142#define H_LOGICAL_CI_LOAD 0x3c
143#define H_LOGICAL_CI_STORE 0x40
144#define H_LOGICAL_CACHE_LOAD 0x44
145#define H_LOGICAL_CACHE_STORE 0x48
146#define H_LOGICAL_ICBI 0x4c
147#define H_LOGICAL_DCBF 0x50
148#define H_GET_TERM_CHAR 0x54
149#define H_PUT_TERM_CHAR 0x58
150#define H_REAL_TO_LOGICAL 0x5c
151#define H_HYPERVISOR_DATA 0x60
152#define H_EOI 0x64
153#define H_CPPR 0x68
154#define H_IPI 0x6c
155#define H_IPOLL 0x70
156#define H_XIRR 0x74
157#define H_PERFMON 0x7c
158#define H_MIGRATE_DMA 0x78
159#define H_REGISTER_VPA 0xDC
160#define H_CEDE 0xE0
161#define H_CONFER 0xE4
162#define H_PROD 0xE8
163#define H_GET_PPP 0xEC
164#define H_SET_PPP 0xF0
165#define H_PURR 0xF4
166#define H_PIC 0xF8
167#define H_REG_CRQ 0xFC
168#define H_FREE_CRQ 0x100
169#define H_VIO_SIGNAL 0x104
170#define H_SEND_CRQ 0x108
171#define H_COPY_RDMA 0x110
172#define H_REGISTER_LOGICAL_LAN 0x114
173#define H_FREE_LOGICAL_LAN 0x118
174#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
175#define H_SEND_LOGICAL_LAN 0x120
176#define H_BULK_REMOVE 0x124
177#define H_MULTICAST_CTRL 0x130
178#define H_SET_XDABR 0x134
179#define H_STUFF_TCE 0x138
180#define H_PUT_TCE_INDIRECT 0x13C
181#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
182#define H_VTERM_PARTNER_INFO 0x150
183#define H_REGISTER_VTERM 0x154
184#define H_FREE_VTERM 0x158
185#define H_RESET_EVENTS 0x15C
186#define H_ALLOC_RESOURCE 0x160
187#define H_FREE_RESOURCE 0x164
188#define H_MODIFY_QP 0x168
189#define H_QUERY_QP 0x16C
190#define H_REREGISTER_PMR 0x170
191#define H_REGISTER_SMR 0x174
192#define H_QUERY_MR 0x178
193#define H_QUERY_MW 0x17C
194#define H_QUERY_HCA 0x180
195#define H_QUERY_PORT 0x184
196#define H_MODIFY_PORT 0x188
197#define H_DEFINE_AQP1 0x18C
198#define H_GET_TRACE_BUFFER 0x190
199#define H_DEFINE_AQP0 0x194
200#define H_RESIZE_MR 0x198
201#define H_ATTACH_MCQP 0x19C
202#define H_DETACH_MCQP 0x1A0
203#define H_CREATE_RPT 0x1A4
204#define H_REMOVE_RPT 0x1A8
205#define H_REGISTER_RPAGES 0x1AC
206#define H_DISABLE_AND_GETC 0x1B0
207#define H_ERROR_DATA 0x1B4
208#define H_GET_HCA_INFO 0x1B8
209#define H_GET_PERF_COUNT 0x1BC
210#define H_MANAGE_TRACE 0x1C0
211#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
212#define H_QUERY_INT_STATE 0x1E4
213#define H_POLL_PENDING 0x1D8
214#define H_ILLAN_ATTRIBUTES 0x244
215#define H_JOIN 0x298
216#define H_VASI_STATE 0x2A4
217#define H_ENABLE_CRQ 0x2B0
218#define H_SET_MPP 0x2D0
219#define H_GET_MPP 0x2D4
220#define MAX_HCALL_OPCODE H_GET_MPP
221
222#ifndef __ASSEMBLY__
223
224/**
225 * plpar_hcall_norets: - Make a pseries hypervisor call with no return arguments
226 * @opcode: The hypervisor call to make.
227 *
228 * This call supports up to 7 arguments and only returns the status of
229 * the hcall. Use this version where possible, its slightly faster than
230 * the other plpar_hcalls.
231 */
232long plpar_hcall_norets(unsigned long opcode, ...);
233
234/**
235 * plpar_hcall: - Make a pseries hypervisor call
236 * @opcode: The hypervisor call to make.
237 * @retbuf: Buffer to store up to 4 return arguments in.
238 *
239 * This call supports up to 6 arguments and 4 return arguments. Use
240 * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
241 *
242 * Used for all but the craziest of phyp interfaces (see plpar_hcall9)
243 */
244#define PLPAR_HCALL_BUFSIZE 4
245long plpar_hcall(unsigned long opcode, unsigned long *retbuf, ...);
246
247/**
248 * plpar_hcall_raw: - Make a hypervisor call without calculating hcall stats
249 * @opcode: The hypervisor call to make.
250 * @retbuf: Buffer to store up to 4 return arguments in.
251 *
252 * This call supports up to 6 arguments and 4 return arguments. Use
253 * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
254 *
255 * Used when phyp interface needs to be called in real mode. Similar to
256 * plpar_hcall, but plpar_hcall_raw works in real mode and does not
257 * calculate hypervisor call statistics.
258 */
259long plpar_hcall_raw(unsigned long opcode, unsigned long *retbuf, ...);
260
261/**
262 * plpar_hcall9: - Make a pseries hypervisor call with up to 9 return arguments
263 * @opcode: The hypervisor call to make.
264 * @retbuf: Buffer to store up to 9 return arguments in.
265 *
266 * This call supports up to 9 arguments and 9 return arguments. Use
267 * PLPAR_HCALL9_BUFSIZE to size the return argument buffer.
268 */
269#define PLPAR_HCALL9_BUFSIZE 9
270long plpar_hcall9(unsigned long opcode, unsigned long *retbuf, ...);
271
272/* For hcall instrumentation. One structure per-hcall, per-CPU */
273struct hcall_stats {
274 unsigned long num_calls; /* number of calls (on this CPU) */
275 unsigned long tb_total; /* total wall time (mftb) of calls. */
276 unsigned long purr_total; /* total cpu time (PURR) of calls. */
277};
278#define HCALL_STAT_ARRAY_SIZE ((MAX_HCALL_OPCODE >> 2) + 1)
279
280struct hvcall_mpp_data {
281 unsigned long entitled_mem;
282 unsigned long mapped_mem;
283 unsigned short group_num;
284 unsigned short pool_num;
285 unsigned char mem_weight;
286 unsigned char unallocated_mem_weight;
287 unsigned long unallocated_entitlement; /* value in bytes */
288 unsigned long pool_size;
289 signed long loan_request;
290 unsigned long backing_mem;
291};
292
293int h_get_mpp(struct hvcall_mpp_data *);
294#endif /* __ASSEMBLY__ */
295#endif /* __KERNEL__ */
296#endif /* _ASM_POWERPC_HVCALL_H */
diff --git a/arch/powerpc/include/asm/hvconsole.h b/arch/powerpc/include/asm/hvconsole.h
new file mode 100644
index 000000000000..35ea69e8121f
--- /dev/null
+++ b/arch/powerpc/include/asm/hvconsole.h
@@ -0,0 +1,41 @@
1/*
2 * hvconsole.h
3 * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
4 *
5 * LPAR console support.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _PPC64_HVCONSOLE_H
23#define _PPC64_HVCONSOLE_H
24#ifdef __KERNEL__
25
26/*
27 * PSeries firmware will only send/recv up to 16 bytes of character data per
28 * hcall.
29 */
30#define MAX_VIO_PUT_CHARS 16
31#define SIZE_VIO_GET_CHARS 16
32
33/*
34 * Vio firmware always attempts to fetch MAX_VIO_GET_CHARS chars. The 'count'
35 * parm is included to conform to put_chars() function pointer template
36 */
37extern int hvc_get_chars(uint32_t vtermno, char *buf, int count);
38extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
39
40#endif /* __KERNEL__ */
41#endif /* _PPC64_HVCONSOLE_H */
diff --git a/arch/powerpc/include/asm/hvcserver.h b/arch/powerpc/include/asm/hvcserver.h
new file mode 100644
index 000000000000..67d7da3a4da4
--- /dev/null
+++ b/arch/powerpc/include/asm/hvcserver.h
@@ -0,0 +1,59 @@
1/*
2 * hvcserver.h
3 * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
4 *
5 * PPC64 virtual I/O console server support.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _PPC64_HVCSERVER_H
23#define _PPC64_HVCSERVER_H
24#ifdef __KERNEL__
25
26#include <linux/list.h>
27
28/* Converged Location Code length */
29#define HVCS_CLC_LENGTH 79
30
31/**
32 * hvcs_partner_info - an element in a list of partner info
33 * @node: list_head denoting this partner_info struct's position in the list of
34 * partner info.
35 * @unit_address: The partner unit address of this entry.
36 * @partition_ID: The partner partition ID of this entry.
37 * @location_code: The converged location code of this entry + 1 char for the
38 * null-term.
39 *
40 * This structure outlines the format that partner info is presented to a caller
41 * of the hvcs partner info fetching functions. These are strung together into
42 * a list using linux kernel lists.
43 */
44struct hvcs_partner_info {
45 struct list_head node;
46 uint32_t unit_address;
47 uint32_t partition_ID;
48 char location_code[HVCS_CLC_LENGTH + 1]; /* CLC + 1 null-term char */
49};
50
51extern int hvcs_free_partner_info(struct list_head *head);
52extern int hvcs_get_partner_info(uint32_t unit_address,
53 struct list_head *head, unsigned long *pi_buff);
54extern int hvcs_register_connection(uint32_t unit_address,
55 uint32_t p_partition_ID, uint32_t p_unit_address);
56extern int hvcs_free_connection(uint32_t unit_address);
57
58#endif /* __KERNEL__ */
59#endif /* _PPC64_HVCSERVER_H */
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
new file mode 100644
index 000000000000..f75a5fc64d2e
--- /dev/null
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_HW_IRQ_H
5#define _ASM_POWERPC_HW_IRQ_H
6
7#ifdef __KERNEL__
8
9#include <linux/errno.h>
10#include <linux/compiler.h>
11#include <asm/ptrace.h>
12#include <asm/processor.h>
13
14extern void timer_interrupt(struct pt_regs *);
15
16#ifdef CONFIG_PPC64
17#include <asm/paca.h>
18
19static inline unsigned long local_get_flags(void)
20{
21 unsigned long flags;
22
23 __asm__ __volatile__("lbz %0,%1(13)"
24 : "=r" (flags)
25 : "i" (offsetof(struct paca_struct, soft_enabled)));
26
27 return flags;
28}
29
30static inline unsigned long raw_local_irq_disable(void)
31{
32 unsigned long flags, zero;
33
34 __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
35 : "=r" (flags), "=&r" (zero)
36 : "i" (offsetof(struct paca_struct, soft_enabled))
37 : "memory");
38
39 return flags;
40}
41
42extern void raw_local_irq_restore(unsigned long);
43extern void iseries_handle_interrupts(void);
44
45#define raw_local_irq_enable() raw_local_irq_restore(1)
46#define raw_local_save_flags(flags) ((flags) = local_get_flags())
47#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable())
48
49#define raw_irqs_disabled() (local_get_flags() == 0)
50#define raw_irqs_disabled_flags(flags) ((flags) == 0)
51
52#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
53#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
54
55#define hard_irq_disable() \
56 do { \
57 __hard_irq_disable(); \
58 get_paca()->soft_enabled = 0; \
59 get_paca()->hard_enabled = 0; \
60 } while(0)
61
62static inline int irqs_disabled_flags(unsigned long flags)
63{
64 return flags == 0;
65}
66
67#else
68
69#if defined(CONFIG_BOOKE)
70#define SET_MSR_EE(x) mtmsr(x)
71#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
72#else
73#define SET_MSR_EE(x) mtmsr(x)
74#define local_irq_restore(flags) mtmsr(flags)
75#endif
76
77static inline void local_irq_disable(void)
78{
79#ifdef CONFIG_BOOKE
80 __asm__ __volatile__("wrteei 0": : :"memory");
81#else
82 unsigned long msr;
83 __asm__ __volatile__("": : :"memory");
84 msr = mfmsr();
85 SET_MSR_EE(msr & ~MSR_EE);
86#endif
87}
88
89static inline void local_irq_enable(void)
90{
91#ifdef CONFIG_BOOKE
92 __asm__ __volatile__("wrteei 1": : :"memory");
93#else
94 unsigned long msr;
95 __asm__ __volatile__("": : :"memory");
96 msr = mfmsr();
97 SET_MSR_EE(msr | MSR_EE);
98#endif
99}
100
101static inline void local_irq_save_ptr(unsigned long *flags)
102{
103 unsigned long msr;
104 msr = mfmsr();
105 *flags = msr;
106#ifdef CONFIG_BOOKE
107 __asm__ __volatile__("wrteei 0": : :"memory");
108#else
109 SET_MSR_EE(msr & ~MSR_EE);
110#endif
111 __asm__ __volatile__("": : :"memory");
112}
113
114#define local_save_flags(flags) ((flags) = mfmsr())
115#define local_irq_save(flags) local_irq_save_ptr(&flags)
116#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
117
118#define hard_irq_enable() local_irq_enable()
119#define hard_irq_disable() local_irq_disable()
120
121static inline int irqs_disabled_flags(unsigned long flags)
122{
123 return (flags & MSR_EE) == 0;
124}
125
126#endif /* CONFIG_PPC64 */
127
128/*
129 * interrupt-retrigger: should we handle this via lost interrupts and IPIs
130 * or should we not care like we do now ? --BenH.
131 */
132struct hw_interrupt_type;
133
134#endif /* __KERNEL__ */
135#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/hydra.h b/arch/powerpc/include/asm/hydra.h
new file mode 100644
index 000000000000..1ad4eed07fbe
--- /dev/null
+++ b/arch/powerpc/include/asm/hydra.h
@@ -0,0 +1,102 @@
1/*
2 * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
3 *
4 * Copyright (C) 1997 Geert Uytterhoeven
5 *
6 * This file is based on the following documentation:
7 *
8 * Macintosh Technology in the Common Hardware Reference Platform
9 * Apple Computer, Inc.
10 *
11 * © Copyright 1995 Apple Computer, Inc. All rights reserved.
12 *
13 * It's available online from http://chrp.apple.com/MacTech.pdf.
14 * You can obtain paper copies of this book from computer bookstores or by
15 * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
16 * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file COPYING in the main directory of this archive
20 * for more details.
21 */
22
23#ifndef _ASMPPC_HYDRA_H
24#define _ASMPPC_HYDRA_H
25
26#ifdef __KERNEL__
27
28struct Hydra {
29 /* DBDMA Controller Register Space */
30 char Pad1[0x30];
31 u_int CachePD;
32 u_int IDs;
33 u_int Feature_Control;
34 char Pad2[0x7fc4];
35 /* DBDMA Channel Register Space */
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
43 /* Device Register Space */
44 char SCSI[0x1000];
45 char ADB[0x1000];
46 char SCC_Legacy[0x1000];
47 char SCC[0x1000];
48 char Pad9[0x2000];
49 char VIA[0x2000];
50 char Pad10[0x28000];
51 char OpenPIC[0x40000];
52};
53
54extern volatile struct Hydra __iomem *Hydra;
55
56
57 /*
58 * Feature Control Register
59 */
60
61#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
62#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
63#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
64#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
65#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
66#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
67#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
68#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
69#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
70
71
72 /*
73 * OpenPIC Interrupt Sources
74 */
75
76#define HYDRA_INT_SIO 0
77#define HYDRA_INT_SCSI_DMA 1
78#define HYDRA_INT_SCCA_TX_DMA 2
79#define HYDRA_INT_SCCA_RX_DMA 3
80#define HYDRA_INT_SCCB_TX_DMA 4
81#define HYDRA_INT_SCCB_RX_DMA 5
82#define HYDRA_INT_SCSI 6
83#define HYDRA_INT_SCCA 7
84#define HYDRA_INT_SCCB 8
85#define HYDRA_INT_VIA 9
86#define HYDRA_INT_ADB 10
87#define HYDRA_INT_ADB_NMI 11
88#define HYDRA_INT_EXT1 12 /* PCI IRQW */
89#define HYDRA_INT_EXT2 13 /* PCI IRQX */
90#define HYDRA_INT_EXT3 14 /* PCI IRQY */
91#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
92#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
93#define HYDRA_INT_EXT6 17 /* IDE Secondary */
94#define HYDRA_INT_EXT7 18 /* Power Off Request */
95#define HYDRA_INT_SPARE 19
96
97extern int hydra_init(void);
98extern void macio_adb_init(void);
99
100#endif /* __KERNEL__ */
101
102#endif /* _ASMPPC_HYDRA_H */
diff --git a/arch/powerpc/include/asm/i8259.h b/arch/powerpc/include/asm/i8259.h
new file mode 100644
index 000000000000..db1362f8c603
--- /dev/null
+++ b/arch/powerpc/include/asm/i8259.h
@@ -0,0 +1,17 @@
1#ifndef _ASM_POWERPC_I8259_H
2#define _ASM_POWERPC_I8259_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6
7#ifdef CONFIG_PPC_MERGE
8extern void i8259_init(struct device_node *node, unsigned long intack_addr);
9extern unsigned int i8259_irq(void);
10extern struct irq_host *i8259_get_host(void);
11#else
12extern void i8259_init(unsigned long intack_addr, int offset);
13extern int i8259_irq(void);
14#endif
15
16#endif /* __KERNEL__ */
17#endif /* _ASM_POWERPC_I8259_H */
diff --git a/arch/powerpc/include/asm/ibmebus.h b/arch/powerpc/include/asm/ibmebus.h
new file mode 100644
index 000000000000..1a9d9aea21fa
--- /dev/null
+++ b/arch/powerpc/include/asm/ibmebus.h
@@ -0,0 +1,60 @@
1/*
2 * IBM PowerPC eBus Infrastructure Support.
3 *
4 * Copyright (c) 2005 IBM Corporation
5 * Joachim Fenkes <fenkes@de.ibm.com>
6 * Heiko J Schick <schickhj@de.ibm.com>
7 *
8 * All rights reserved.
9 *
10 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
11 * BSD.
12 *
13 * OpenIB BSD License
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials
24 * provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
33 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef _ASM_EBUS_H
40#define _ASM_EBUS_H
41#ifdef __KERNEL__
42
43#include <linux/device.h>
44#include <linux/interrupt.h>
45#include <linux/mod_devicetable.h>
46#include <linux/of_device.h>
47#include <linux/of_platform.h>
48
49extern struct bus_type ibmebus_bus_type;
50
51int ibmebus_register_driver(struct of_platform_driver *drv);
52void ibmebus_unregister_driver(struct of_platform_driver *drv);
53
54int ibmebus_request_irq(u32 ist, irq_handler_t handler,
55 unsigned long irq_flags, const char *devname,
56 void *dev_id);
57void ibmebus_free_irq(u32 ist, void *dev_id);
58
59#endif /* __KERNEL__ */
60#endif /* _ASM_IBMEBUS_H */
diff --git a/arch/powerpc/include/asm/ide.h b/arch/powerpc/include/asm/ide.h
new file mode 100644
index 000000000000..1aaf27be8741
--- /dev/null
+++ b/arch/powerpc/include/asm/ide.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 1994-1996 Linus Torvalds & authors
3 *
4 * This file contains the powerpc architecture specific IDE code.
5 */
6#ifndef _ASM_POWERPC_IDE_H
7#define _ASM_POWERPC_IDE_H
8
9#ifdef __KERNEL__
10
11#ifndef __powerpc64__
12#include <linux/sched.h>
13#include <asm/mpc8xx.h>
14#endif
15#include <asm/io.h>
16
17#define __ide_mm_insw(p, a, c) readsw((void __iomem *)(p), (a), (c))
18#define __ide_mm_insl(p, a, c) readsl((void __iomem *)(p), (a), (c))
19#define __ide_mm_outsw(p, a, c) writesw((void __iomem *)(p), (a), (c))
20#define __ide_mm_outsl(p, a, c) writesl((void __iomem *)(p), (a), (c))
21
22#ifndef __powerpc64__
23#include <linux/hdreg.h>
24#include <linux/ioport.h>
25
26/* FIXME: use ide_platform host driver */
27static __inline__ int ide_default_irq(unsigned long base)
28{
29#ifdef CONFIG_PPLUS
30 switch (base) {
31 case 0x1f0: return 14;
32 case 0x170: return 15;
33 }
34#endif
35 return 0;
36}
37
38/* FIXME: use ide_platform host driver */
39static __inline__ unsigned long ide_default_io_base(int index)
40{
41#ifdef CONFIG_PPLUS
42 switch (index) {
43 case 0: return 0x1f0;
44 case 1: return 0x170;
45 }
46#endif
47 return 0;
48}
49
50#ifdef CONFIG_BLK_DEV_MPC8xx_IDE
51#define IDE_ARCH_ACK_INTR 1
52#define ide_ack_intr(hwif) ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1)
53#endif
54
55#endif /* __powerpc64__ */
56
57#endif /* __KERNEL__ */
58
59#endif /* _ASM_POWERPC_IDE_H */
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
new file mode 100644
index 000000000000..0f165e59c326
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -0,0 +1,156 @@
1/**
2 * MPC86xx Internal Memory Map
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This header file defines structures for various 86xx SOC devices that are
15 * used by multiple source files.
16 */
17
18#ifndef __ASM_POWERPC_IMMAP_86XX_H__
19#define __ASM_POWERPC_IMMAP_86XX_H__
20#ifdef __KERNEL__
21
22/* Global Utility Registers */
23struct ccsr_guts {
24 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
25 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
26 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
27 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
28 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
29 u8 res1[0x20 - 0x14];
30 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
31 u8 res2[0x30 - 0x24];
32 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
33 u8 res3[0x40 - 0x34];
34 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
35 u8 res4[0x50 - 0x44];
36 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
37 u8 res5[0x60 - 0x54];
38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
39 u8 res6[0x70 - 0x64];
40 __be32 devdisr; /* 0x.0070 - Device Disable Control */
41 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
42 u8 res7[0x80 - 0x78];
43 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
44 u8 res8[0x90 - 0x84];
45 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
46 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
47 u8 res9[0xA0 - 0x98];
48 __be32 pvr; /* 0x.00a0 - Processor Version Register */
49 __be32 svr; /* 0x.00a4 - System Version Register */
50 u8 res10[0xB0 - 0xA8];
51 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
52 u8 res11[0xC0 - 0xB4];
53 __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
54 u8 res12[0x800 - 0xC4];
55 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
56 u8 res13[0x900 - 0x804];
57 __be32 ircr; /* 0x.0900 - Infrared Control Register */
58 u8 res14[0x908 - 0x904];
59 __be32 dmacr; /* 0x.0908 - DMA Control Register */
60 u8 res15[0x914 - 0x90C];
61 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
62 u8 res16[0xB20 - 0x918];
63 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
64 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
65 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
66 u8 res17[0xE00 - 0xB2C];
67 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
68 u8 res18[0xE10 - 0xE04];
69 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
70 u8 res19[0xE20 - 0xE14];
71 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
72 u8 res20[0xF04 - 0xE24];
73 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
74 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
75 u8 res21[0xF40 - 0xF0C];
76 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
77 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
78} __attribute__ ((packed));
79
80#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
81#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
82
83/*
84 * Set the DMACR register in the GUTS
85 *
86 * The DMACR register determines the source of initiated transfers for each
87 * channel on each DMA controller. Rather than have a bunch of repetitive
88 * macros for the bit patterns, we just have a function that calculates
89 * them.
90 *
91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (0 or 1)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device)
98{
99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102}
103
104#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
105#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
106#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
107#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
108#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
109#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
110#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
111#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
112#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
113#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
114#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
115#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
116#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
117#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120
121/*
122 * Set the DMA external control bits in the GUTS
123 *
124 * The DMA external control bits in the PMUXCR are only meaningful for
125 * channels 0 and 3. Any other channels are ignored.
126 *
127 * guts: Pointer to GUTS structure
128 * co: The DMA controller (0 or 1)
129 * ch: The channel on the DMA controller (0, 1, 2, or 3)
130 * value: the new value for the bit (0 or 1)
131 */
132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
145#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
146#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
147#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
148 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
149#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
150#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
151#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
152#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
153#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
154
155#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
156#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/immap_cpm2.h b/arch/powerpc/include/asm/immap_cpm2.h
new file mode 100644
index 000000000000..4080bab0468c
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_cpm2.h
@@ -0,0 +1,650 @@
1/*
2 * CPM2 Internal Memory Map
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
4 *
5 * The Internal Memory Map for devices with CPM2 on them. This
6 * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
7 * 8560).
8 */
9#ifdef __KERNEL__
10#ifndef __IMMAP_CPM2__
11#define __IMMAP_CPM2__
12
13#include <linux/types.h>
14
15/* System configuration registers.
16*/
17typedef struct sys_82xx_conf {
18 u32 sc_siumcr;
19 u32 sc_sypcr;
20 u8 res1[6];
21 u16 sc_swsr;
22 u8 res2[20];
23 u32 sc_bcr;
24 u8 sc_ppc_acr;
25 u8 res3[3];
26 u32 sc_ppc_alrh;
27 u32 sc_ppc_alrl;
28 u8 sc_lcl_acr;
29 u8 res4[3];
30 u32 sc_lcl_alrh;
31 u32 sc_lcl_alrl;
32 u32 sc_tescr1;
33 u32 sc_tescr2;
34 u32 sc_ltescr1;
35 u32 sc_ltescr2;
36 u32 sc_pdtea;
37 u8 sc_pdtem;
38 u8 res5[3];
39 u32 sc_ldtea;
40 u8 sc_ldtem;
41 u8 res6[163];
42} sysconf_82xx_cpm2_t;
43
44typedef struct sys_85xx_conf {
45 u32 sc_cear;
46 u16 sc_ceer;
47 u16 sc_cemr;
48 u8 res1[70];
49 u32 sc_smaer;
50 u8 res2[4];
51 u32 sc_smevr;
52 u32 sc_smctr;
53 u32 sc_lmaer;
54 u8 res3[4];
55 u32 sc_lmevr;
56 u32 sc_lmctr;
57 u8 res4[144];
58} sysconf_85xx_cpm2_t;
59
60typedef union sys_conf {
61 sysconf_82xx_cpm2_t siu_82xx;
62 sysconf_85xx_cpm2_t siu_85xx;
63} sysconf_cpm2_t;
64
65
66
67/* Memory controller registers.
68*/
69typedef struct mem_ctlr {
70 u32 memc_br0;
71 u32 memc_or0;
72 u32 memc_br1;
73 u32 memc_or1;
74 u32 memc_br2;
75 u32 memc_or2;
76 u32 memc_br3;
77 u32 memc_or3;
78 u32 memc_br4;
79 u32 memc_or4;
80 u32 memc_br5;
81 u32 memc_or5;
82 u32 memc_br6;
83 u32 memc_or6;
84 u32 memc_br7;
85 u32 memc_or7;
86 u32 memc_br8;
87 u32 memc_or8;
88 u32 memc_br9;
89 u32 memc_or9;
90 u32 memc_br10;
91 u32 memc_or10;
92 u32 memc_br11;
93 u32 memc_or11;
94 u8 res1[8];
95 u32 memc_mar;
96 u8 res2[4];
97 u32 memc_mamr;
98 u32 memc_mbmr;
99 u32 memc_mcmr;
100 u8 res3[8];
101 u16 memc_mptpr;
102 u8 res4[2];
103 u32 memc_mdr;
104 u8 res5[4];
105 u32 memc_psdmr;
106 u32 memc_lsdmr;
107 u8 memc_purt;
108 u8 res6[3];
109 u8 memc_psrt;
110 u8 res7[3];
111 u8 memc_lurt;
112 u8 res8[3];
113 u8 memc_lsrt;
114 u8 res9[3];
115 u32 memc_immr;
116 u32 memc_pcibr0;
117 u32 memc_pcibr1;
118 u8 res10[16];
119 u32 memc_pcimsk0;
120 u32 memc_pcimsk1;
121 u8 res11[52];
122} memctl_cpm2_t;
123
124/* System Integration Timers.
125*/
126typedef struct sys_int_timers {
127 u8 res1[32];
128 u16 sit_tmcntsc;
129 u8 res2[2];
130 u32 sit_tmcnt;
131 u8 res3[4];
132 u32 sit_tmcntal;
133 u8 res4[16];
134 u16 sit_piscr;
135 u8 res5[2];
136 u32 sit_pitc;
137 u32 sit_pitr;
138 u8 res6[94];
139 u8 res7[390];
140} sit_cpm2_t;
141
142#define PISCR_PIRQ_MASK ((u16)0xff00)
143#define PISCR_PS ((u16)0x0080)
144#define PISCR_PIE ((u16)0x0004)
145#define PISCR_PTF ((u16)0x0002)
146#define PISCR_PTE ((u16)0x0001)
147
148/* PCI Controller.
149*/
150typedef struct pci_ctlr {
151 u32 pci_omisr;
152 u32 pci_omimr;
153 u8 res1[8];
154 u32 pci_ifqpr;
155 u32 pci_ofqpr;
156 u8 res2[8];
157 u32 pci_imr0;
158 u32 pci_imr1;
159 u32 pci_omr0;
160 u32 pci_omr1;
161 u32 pci_odr;
162 u8 res3[4];
163 u32 pci_idr;
164 u8 res4[20];
165 u32 pci_imisr;
166 u32 pci_imimr;
167 u8 res5[24];
168 u32 pci_ifhpr;
169 u8 res6[4];
170 u32 pci_iftpr;
171 u8 res7[4];
172 u32 pci_iphpr;
173 u8 res8[4];
174 u32 pci_iptpr;
175 u8 res9[4];
176 u32 pci_ofhpr;
177 u8 res10[4];
178 u32 pci_oftpr;
179 u8 res11[4];
180 u32 pci_ophpr;
181 u8 res12[4];
182 u32 pci_optpr;
183 u8 res13[8];
184 u32 pci_mucr;
185 u8 res14[8];
186 u32 pci_qbar;
187 u8 res15[12];
188 u32 pci_dmamr0;
189 u32 pci_dmasr0;
190 u32 pci_dmacdar0;
191 u8 res16[4];
192 u32 pci_dmasar0;
193 u8 res17[4];
194 u32 pci_dmadar0;
195 u8 res18[4];
196 u32 pci_dmabcr0;
197 u32 pci_dmandar0;
198 u8 res19[86];
199 u32 pci_dmamr1;
200 u32 pci_dmasr1;
201 u32 pci_dmacdar1;
202 u8 res20[4];
203 u32 pci_dmasar1;
204 u8 res21[4];
205 u32 pci_dmadar1;
206 u8 res22[4];
207 u32 pci_dmabcr1;
208 u32 pci_dmandar1;
209 u8 res23[88];
210 u32 pci_dmamr2;
211 u32 pci_dmasr2;
212 u32 pci_dmacdar2;
213 u8 res24[4];
214 u32 pci_dmasar2;
215 u8 res25[4];
216 u32 pci_dmadar2;
217 u8 res26[4];
218 u32 pci_dmabcr2;
219 u32 pci_dmandar2;
220 u8 res27[88];
221 u32 pci_dmamr3;
222 u32 pci_dmasr3;
223 u32 pci_dmacdar3;
224 u8 res28[4];
225 u32 pci_dmasar3;
226 u8 res29[4];
227 u32 pci_dmadar3;
228 u8 res30[4];
229 u32 pci_dmabcr3;
230 u32 pci_dmandar3;
231 u8 res31[344];
232 u32 pci_potar0;
233 u8 res32[4];
234 u32 pci_pobar0;
235 u8 res33[4];
236 u32 pci_pocmr0;
237 u8 res34[4];
238 u32 pci_potar1;
239 u8 res35[4];
240 u32 pci_pobar1;
241 u8 res36[4];
242 u32 pci_pocmr1;
243 u8 res37[4];
244 u32 pci_potar2;
245 u8 res38[4];
246 u32 pci_pobar2;
247 u8 res39[4];
248 u32 pci_pocmr2;
249 u8 res40[50];
250 u32 pci_ptcr;
251 u32 pci_gpcr;
252 u32 pci_gcr;
253 u32 pci_esr;
254 u32 pci_emr;
255 u32 pci_ecr;
256 u32 pci_eacr;
257 u8 res41[4];
258 u32 pci_edcr;
259 u8 res42[4];
260 u32 pci_eccr;
261 u8 res43[44];
262 u32 pci_pitar1;
263 u8 res44[4];
264 u32 pci_pibar1;
265 u8 res45[4];
266 u32 pci_picmr1;
267 u8 res46[4];
268 u32 pci_pitar0;
269 u8 res47[4];
270 u32 pci_pibar0;
271 u8 res48[4];
272 u32 pci_picmr0;
273 u8 res49[4];
274 u32 pci_cfg_addr;
275 u32 pci_cfg_data;
276 u32 pci_int_ack;
277 u8 res50[756];
278} pci_cpm2_t;
279
280/* Interrupt Controller.
281*/
282typedef struct interrupt_controller {
283 u16 ic_sicr;
284 u8 res1[2];
285 u32 ic_sivec;
286 u32 ic_sipnrh;
287 u32 ic_sipnrl;
288 u32 ic_siprr;
289 u32 ic_scprrh;
290 u32 ic_scprrl;
291 u32 ic_simrh;
292 u32 ic_simrl;
293 u32 ic_siexr;
294 u8 res2[88];
295} intctl_cpm2_t;
296
297/* Clocks and Reset.
298*/
299typedef struct clk_and_reset {
300 u32 car_sccr;
301 u8 res1[4];
302 u32 car_scmr;
303 u8 res2[4];
304 u32 car_rsr;
305 u32 car_rmr;
306 u8 res[104];
307} car_cpm2_t;
308
309/* Input/Output Port control/status registers.
310 * Names consistent with processor manual, although they are different
311 * from the original 8xx names.......
312 */
313typedef struct io_port {
314 u32 iop_pdira;
315 u32 iop_ppara;
316 u32 iop_psora;
317 u32 iop_podra;
318 u32 iop_pdata;
319 u8 res1[12];
320 u32 iop_pdirb;
321 u32 iop_pparb;
322 u32 iop_psorb;
323 u32 iop_podrb;
324 u32 iop_pdatb;
325 u8 res2[12];
326 u32 iop_pdirc;
327 u32 iop_pparc;
328 u32 iop_psorc;
329 u32 iop_podrc;
330 u32 iop_pdatc;
331 u8 res3[12];
332 u32 iop_pdird;
333 u32 iop_ppard;
334 u32 iop_psord;
335 u32 iop_podrd;
336 u32 iop_pdatd;
337 u8 res4[12];
338} iop_cpm2_t;
339
340/* Communication Processor Module Timers
341*/
342typedef struct cpm_timers {
343 u8 cpmt_tgcr1;
344 u8 res1[3];
345 u8 cpmt_tgcr2;
346 u8 res2[11];
347 u16 cpmt_tmr1;
348 u16 cpmt_tmr2;
349 u16 cpmt_trr1;
350 u16 cpmt_trr2;
351 u16 cpmt_tcr1;
352 u16 cpmt_tcr2;
353 u16 cpmt_tcn1;
354 u16 cpmt_tcn2;
355 u16 cpmt_tmr3;
356 u16 cpmt_tmr4;
357 u16 cpmt_trr3;
358 u16 cpmt_trr4;
359 u16 cpmt_tcr3;
360 u16 cpmt_tcr4;
361 u16 cpmt_tcn3;
362 u16 cpmt_tcn4;
363 u16 cpmt_ter1;
364 u16 cpmt_ter2;
365 u16 cpmt_ter3;
366 u16 cpmt_ter4;
367 u8 res3[584];
368} cpmtimer_cpm2_t;
369
370/* DMA control/status registers.
371*/
372typedef struct sdma_csr {
373 u8 res0[24];
374 u8 sdma_sdsr;
375 u8 res1[3];
376 u8 sdma_sdmr;
377 u8 res2[3];
378 u8 sdma_idsr1;
379 u8 res3[3];
380 u8 sdma_idmr1;
381 u8 res4[3];
382 u8 sdma_idsr2;
383 u8 res5[3];
384 u8 sdma_idmr2;
385 u8 res6[3];
386 u8 sdma_idsr3;
387 u8 res7[3];
388 u8 sdma_idmr3;
389 u8 res8[3];
390 u8 sdma_idsr4;
391 u8 res9[3];
392 u8 sdma_idmr4;
393 u8 res10[707];
394} sdma_cpm2_t;
395
396/* Fast controllers
397*/
398typedef struct fcc {
399 u32 fcc_gfmr;
400 u32 fcc_fpsmr;
401 u16 fcc_ftodr;
402 u8 res1[2];
403 u16 fcc_fdsr;
404 u8 res2[2];
405 u16 fcc_fcce;
406 u8 res3[2];
407 u16 fcc_fccm;
408 u8 res4[2];
409 u8 fcc_fccs;
410 u8 res5[3];
411 u8 fcc_ftirr_phy[4];
412} fcc_t;
413
414/* Fast controllers continued
415 */
416typedef struct fcc_c {
417 u32 fcc_firper;
418 u32 fcc_firer;
419 u32 fcc_firsr_hi;
420 u32 fcc_firsr_lo;
421 u8 fcc_gfemr;
422 u8 res1[15];
423} fcc_c_t;
424
425/* TC Layer
426 */
427typedef struct tclayer {
428 u16 tc_tcmode;
429 u16 tc_cdsmr;
430 u16 tc_tcer;
431 u16 tc_rcc;
432 u16 tc_tcmr;
433 u16 tc_fcc;
434 u16 tc_ccc;
435 u16 tc_icc;
436 u16 tc_tcc;
437 u16 tc_ecc;
438 u8 res1[12];
439} tclayer_t;
440
441
442/* I2C
443*/
444typedef struct i2c {
445 u8 i2c_i2mod;
446 u8 res1[3];
447 u8 i2c_i2add;
448 u8 res2[3];
449 u8 i2c_i2brg;
450 u8 res3[3];
451 u8 i2c_i2com;
452 u8 res4[3];
453 u8 i2c_i2cer;
454 u8 res5[3];
455 u8 i2c_i2cmr;
456 u8 res6[331];
457} i2c_cpm2_t;
458
459typedef struct scc { /* Serial communication channels */
460 u32 scc_gsmrl;
461 u32 scc_gsmrh;
462 u16 scc_psmr;
463 u8 res1[2];
464 u16 scc_todr;
465 u16 scc_dsr;
466 u16 scc_scce;
467 u8 res2[2];
468 u16 scc_sccm;
469 u8 res3;
470 u8 scc_sccs;
471 u8 res4[8];
472} scc_t;
473
474typedef struct smc { /* Serial management channels */
475 u8 res1[2];
476 u16 smc_smcmr;
477 u8 res2[2];
478 u8 smc_smce;
479 u8 res3[3];
480 u8 smc_smcm;
481 u8 res4[5];
482} smc_t;
483
484/* Serial Peripheral Interface.
485*/
486typedef struct spi_ctrl {
487 u16 spi_spmode;
488 u8 res1[4];
489 u8 spi_spie;
490 u8 res2[3];
491 u8 spi_spim;
492 u8 res3[2];
493 u8 spi_spcom;
494 u8 res4[82];
495} spictl_cpm2_t;
496
497/* CPM Mux.
498*/
499typedef struct cpmux {
500 u8 cmx_si1cr;
501 u8 res1;
502 u8 cmx_si2cr;
503 u8 res2;
504 u32 cmx_fcr;
505 u32 cmx_scr;
506 u8 cmx_smr;
507 u8 res3;
508 u16 cmx_uar;
509 u8 res4[16];
510} cpmux_t;
511
512/* SIRAM control
513*/
514typedef struct siram {
515 u16 si_amr;
516 u16 si_bmr;
517 u16 si_cmr;
518 u16 si_dmr;
519 u8 si_gmr;
520 u8 res1;
521 u8 si_cmdr;
522 u8 res2;
523 u8 si_str;
524 u8 res3;
525 u16 si_rsr;
526} siramctl_t;
527
528typedef struct mcc {
529 u16 mcc_mcce;
530 u8 res1[2];
531 u16 mcc_mccm;
532 u8 res2[2];
533 u8 mcc_mccf;
534 u8 res3[7];
535} mcc_t;
536
537typedef struct comm_proc {
538 u32 cp_cpcr;
539 u32 cp_rccr;
540 u8 res1[14];
541 u16 cp_rter;
542 u8 res2[2];
543 u16 cp_rtmr;
544 u16 cp_rtscr;
545 u8 res3[2];
546 u32 cp_rtsr;
547 u8 res4[12];
548} cpm_cpm2_t;
549
550/* USB Controller.
551*/
552typedef struct usb_ctlr {
553 u8 usb_usmod;
554 u8 usb_usadr;
555 u8 usb_uscom;
556 u8 res1[1];
557 u16 usb_usep1;
558 u16 usb_usep2;
559 u16 usb_usep3;
560 u16 usb_usep4;
561 u8 res2[4];
562 u16 usb_usber;
563 u8 res3[2];
564 u16 usb_usbmr;
565 u8 usb_usbs;
566 u8 res4[7];
567} usb_cpm2_t;
568
569/* ...and the whole thing wrapped up....
570*/
571
572typedef struct immap {
573 /* Some references are into the unique and known dpram spaces,
574 * others are from the generic base.
575 */
576#define im_dprambase im_dpram1
577 u8 im_dpram1[16*1024];
578 u8 res1[16*1024];
579 u8 im_dpram2[4*1024];
580 u8 res2[8*1024];
581 u8 im_dpram3[4*1024];
582 u8 res3[16*1024];
583
584 sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
585 memctl_cpm2_t im_memctl; /* Memory Controller */
586 sit_cpm2_t im_sit; /* System Integration Timers */
587 pci_cpm2_t im_pci; /* PCI Controller */
588 intctl_cpm2_t im_intctl; /* Interrupt Controller */
589 car_cpm2_t im_clkrst; /* Clocks and reset */
590 iop_cpm2_t im_ioport; /* IO Port control/status */
591 cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
592 sdma_cpm2_t im_sdma; /* SDMA control/status */
593
594 fcc_t im_fcc[3]; /* Three FCCs */
595 u8 res4z[32];
596 fcc_c_t im_fcc_c[3]; /* Continued FCCs */
597
598 u8 res4[32];
599
600 tclayer_t im_tclayer[8]; /* Eight TCLayers */
601 u16 tc_tcgsr;
602 u16 tc_tcger;
603
604 /* First set of baud rate generators.
605 */
606 u8 res[236];
607 u32 im_brgc5;
608 u32 im_brgc6;
609 u32 im_brgc7;
610 u32 im_brgc8;
611
612 u8 res5[608];
613
614 i2c_cpm2_t im_i2c; /* I2C control/status */
615 cpm_cpm2_t im_cpm; /* Communication processor */
616
617 /* Second set of baud rate generators.
618 */
619 u32 im_brgc1;
620 u32 im_brgc2;
621 u32 im_brgc3;
622 u32 im_brgc4;
623
624 scc_t im_scc[4]; /* Four SCCs */
625 smc_t im_smc[2]; /* Couple of SMCs */
626 spictl_cpm2_t im_spi; /* A SPI */
627 cpmux_t im_cpmux; /* CPM clock route mux */
628 siramctl_t im_siramctl1; /* First SI RAM Control */
629 mcc_t im_mcc1; /* First MCC */
630 siramctl_t im_siramctl2; /* Second SI RAM Control */
631 mcc_t im_mcc2; /* Second MCC */
632 usb_cpm2_t im_usb; /* USB Controller */
633
634 u8 res6[1153];
635
636 u16 im_si1txram[256];
637 u8 res7[512];
638 u16 im_si1rxram[256];
639 u8 res8[512];
640 u16 im_si2txram[256];
641 u8 res9[512];
642 u16 im_si2rxram[256];
643 u8 res10[512];
644 u8 res11[4096];
645} cpm2_map_t;
646
647extern cpm2_map_t __iomem *cpm2_immr;
648
649#endif /* __IMMAP_CPM2__ */
650#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
new file mode 100644
index 000000000000..3c2fced3ac22
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -0,0 +1,483 @@
1/*
2 * QUICC Engine (QE) Internal Memory Map.
3 * The Internal Memory Map for devices with QE on them. This
4 * is the superset of all QE devices (8360, etc.).
5
6 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#ifndef _ASM_POWERPC_IMMAP_QE_H
17#define _ASM_POWERPC_IMMAP_QE_H
18#ifdef __KERNEL__
19
20#include <linux/kernel.h>
21#include <asm/io.h>
22
23#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
24
25/* QE I-RAM */
26struct qe_iram {
27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */
29 u8 res0[0x78];
30} __attribute__ ((packed));
31
32/* QE Interrupt Controller */
33struct qe_ic_regs {
34 __be32 qicr;
35 __be32 qivec;
36 __be32 qripnr;
37 __be32 qipnr;
38 __be32 qipxcc;
39 __be32 qipycc;
40 __be32 qipwcc;
41 __be32 qipzcc;
42 __be32 qimr;
43 __be32 qrimr;
44 __be32 qicnr;
45 u8 res0[0x4];
46 __be32 qiprta;
47 __be32 qiprtb;
48 u8 res1[0x4];
49 __be32 qricr;
50 u8 res2[0x20];
51 __be32 qhivec;
52 u8 res3[0x1C];
53} __attribute__ ((packed));
54
55/* Communications Processor */
56struct cp_qe {
57 __be32 cecr; /* QE command register */
58 __be32 ceccr; /* QE controller configuration register */
59 __be32 cecdr; /* QE command data register */
60 u8 res0[0xA];
61 __be16 ceter; /* QE timer event register */
62 u8 res1[0x2];
63 __be16 cetmr; /* QE timers mask register */
64 __be32 cetscr; /* QE time-stamp timer control register */
65 __be32 cetsr1; /* QE time-stamp register 1 */
66 __be32 cetsr2; /* QE time-stamp register 2 */
67 u8 res2[0x8];
68 __be32 cevter; /* QE virtual tasks event register */
69 __be32 cevtmr; /* QE virtual tasks mask register */
70 __be16 cercr; /* QE RAM control register */
71 u8 res3[0x2];
72 u8 res4[0x24];
73 __be16 ceexe1; /* QE external request 1 event register */
74 u8 res5[0x2];
75 __be16 ceexm1; /* QE external request 1 mask register */
76 u8 res6[0x2];
77 __be16 ceexe2; /* QE external request 2 event register */
78 u8 res7[0x2];
79 __be16 ceexm2; /* QE external request 2 mask register */
80 u8 res8[0x2];
81 __be16 ceexe3; /* QE external request 3 event register */
82 u8 res9[0x2];
83 __be16 ceexm3; /* QE external request 3 mask register */
84 u8 res10[0x2];
85 __be16 ceexe4; /* QE external request 4 event register */
86 u8 res11[0x2];
87 __be16 ceexm4; /* QE external request 4 mask register */
88 u8 res12[0x3A];
89 __be32 ceurnr; /* QE microcode revision number register */
90 u8 res13[0x244];
91} __attribute__ ((packed));
92
93/* QE Multiplexer */
94struct qe_mux {
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
100 __be32 cmxupcr; /* CMX UPC clock route register */
101 u8 res0[0x1C];
102} __attribute__ ((packed));
103
104/* QE Timers */
105struct qe_timers {
106 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
107 u8 res0[0x3];
108 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
109 u8 res1[0xB];
110 __be16 gtmdr1; /* Timer 1 mode register */
111 __be16 gtmdr2; /* Timer 2 mode register */
112 __be16 gtrfr1; /* Timer 1 reference register */
113 __be16 gtrfr2; /* Timer 2 reference register */
114 __be16 gtcpr1; /* Timer 1 capture register */
115 __be16 gtcpr2; /* Timer 2 capture register */
116 __be16 gtcnr1; /* Timer 1 counter */
117 __be16 gtcnr2; /* Timer 2 counter */
118 __be16 gtmdr3; /* Timer 3 mode register */
119 __be16 gtmdr4; /* Timer 4 mode register */
120 __be16 gtrfr3; /* Timer 3 reference register */
121 __be16 gtrfr4; /* Timer 4 reference register */
122 __be16 gtcpr3; /* Timer 3 capture register */
123 __be16 gtcpr4; /* Timer 4 capture register */
124 __be16 gtcnr3; /* Timer 3 counter */
125 __be16 gtcnr4; /* Timer 4 counter */
126 __be16 gtevr1; /* Timer 1 event register */
127 __be16 gtevr2; /* Timer 2 event register */
128 __be16 gtevr3; /* Timer 3 event register */
129 __be16 gtevr4; /* Timer 4 event register */
130 __be16 gtps; /* Timer 1 prescale register */
131 u8 res2[0x46];
132} __attribute__ ((packed));
133
134/* BRG */
135struct qe_brg {
136 __be32 brgc[16]; /* BRG configuration registers */
137 u8 res0[0x40];
138} __attribute__ ((packed));
139
140/* SPI */
141struct spi {
142 u8 res0[0x20];
143 __be32 spmode; /* SPI mode register */
144 u8 res1[0x2];
145 u8 spie; /* SPI event register */
146 u8 res2[0x1];
147 u8 res3[0x2];
148 u8 spim; /* SPI mask register */
149 u8 res4[0x1];
150 u8 res5[0x1];
151 u8 spcom; /* SPI command register */
152 u8 res6[0x2];
153 __be32 spitd; /* SPI transmit data register (cpu mode) */
154 __be32 spird; /* SPI receive data register (cpu mode) */
155 u8 res7[0x8];
156} __attribute__ ((packed));
157
158/* SI */
159struct si1 {
160 __be16 siamr1; /* SI1 TDMA mode register */
161 __be16 sibmr1; /* SI1 TDMB mode register */
162 __be16 sicmr1; /* SI1 TDMC mode register */
163 __be16 sidmr1; /* SI1 TDMD mode register */
164 u8 siglmr1_h; /* SI1 global mode register high */
165 u8 res0[0x1];
166 u8 sicmdr1_h; /* SI1 command register high */
167 u8 res2[0x1];
168 u8 sistr1_h; /* SI1 status register high */
169 u8 res3[0x1];
170 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
171 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
172 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
173 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
174 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
175 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
176 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
177 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
178 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
179 u8 res4[0x8];
180 __be16 siemr1; /* SI1 TDME mode register 16 bits */
181 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
182 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
183 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
184 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
185 u8 res5[0x1];
186 u8 sicmdr1_l; /* SI1 command register low 8 bits */
187 u8 res6[0x1];
188 u8 sistr1_l; /* SI1 status register low 8 bits */
189 u8 res7[0x1];
190 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
191 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
192 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
193 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
194 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
195 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
196 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
197 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
198 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
199 u8 res8[0x8];
200 __be32 siml1; /* SI1 multiframe limit register */
201 u8 siedm1; /* SI1 extended diagnostic mode register */
202 u8 res9[0xBB];
203} __attribute__ ((packed));
204
205/* SI Routing Tables */
206struct sir {
207 u8 tx[0x400];
208 u8 rx[0x400];
209 u8 res0[0x800];
210} __attribute__ ((packed));
211
212/* USB Controller */
213struct usb_ctlr {
214 u8 usb_usmod;
215 u8 usb_usadr;
216 u8 usb_uscom;
217 u8 res1[1];
218 __be16 usb_usep1;
219 __be16 usb_usep2;
220 __be16 usb_usep3;
221 __be16 usb_usep4;
222 u8 res2[4];
223 __be16 usb_usber;
224 u8 res3[2];
225 __be16 usb_usbmr;
226 u8 res4[1];
227 u8 usb_usbs;
228 __be16 usb_ussft;
229 u8 res5[2];
230 __be16 usb_usfrn;
231 u8 res6[0x22];
232} __attribute__ ((packed));
233
234/* MCC */
235struct mcc {
236 __be32 mcce; /* MCC event register */
237 __be32 mccm; /* MCC mask register */
238 __be32 mccf; /* MCC configuration register */
239 __be32 merl; /* MCC emergency request level register */
240 u8 res0[0xF0];
241} __attribute__ ((packed));
242
243/* QE UCC Slow */
244struct ucc_slow {
245 __be32 gumr_l; /* UCCx general mode register (low) */
246 __be32 gumr_h; /* UCCx general mode register (high) */
247 __be16 upsmr; /* UCCx protocol-specific mode register */
248 u8 res0[0x2];
249 __be16 utodr; /* UCCx transmit on demand register */
250 __be16 udsr; /* UCCx data synchronization register */
251 __be16 ucce; /* UCCx event register */
252 u8 res1[0x2];
253 __be16 uccm; /* UCCx mask register */
254 u8 res2[0x1];
255 u8 uccs; /* UCCx status register */
256 u8 res3[0x24];
257 __be16 utpt;
258 u8 res4[0x52];
259 u8 guemr; /* UCC general extended mode register */
260} __attribute__ ((packed));
261
262/* QE UCC Fast */
263struct ucc_fast {
264 __be32 gumr; /* UCCx general mode register */
265 __be32 upsmr; /* UCCx protocol-specific mode register */
266 __be16 utodr; /* UCCx transmit on demand register */
267 u8 res0[0x2];
268 __be16 udsr; /* UCCx data synchronization register */
269 u8 res1[0x2];
270 __be32 ucce; /* UCCx event register */
271 __be32 uccm; /* UCCx mask register */
272 u8 uccs; /* UCCx status register */
273 u8 res2[0x7];
274 __be32 urfb; /* UCC receive FIFO base */
275 __be16 urfs; /* UCC receive FIFO size */
276 u8 res3[0x2];
277 __be16 urfet; /* UCC receive FIFO emergency threshold */
278 __be16 urfset; /* UCC receive FIFO special emergency
279 threshold */
280 __be32 utfb; /* UCC transmit FIFO base */
281 __be16 utfs; /* UCC transmit FIFO size */
282 u8 res4[0x2];
283 __be16 utfet; /* UCC transmit FIFO emergency threshold */
284 u8 res5[0x2];
285 __be16 utftt; /* UCC transmit FIFO transmit threshold */
286 u8 res6[0x2];
287 __be16 utpt; /* UCC transmit polling timer */
288 u8 res7[0x2];
289 __be32 urtry; /* UCC retry counter register */
290 u8 res8[0x4C];
291 u8 guemr; /* UCC general extended mode register */
292} __attribute__ ((packed));
293
294struct ucc {
295 union {
296 struct ucc_slow slow;
297 struct ucc_fast fast;
298 u8 res[0x200]; /* UCC blocks are 512 bytes each */
299 };
300} __attribute__ ((packed));
301
302/* MultiPHY UTOPIA POS Controllers (UPC) */
303struct upc {
304 __be32 upgcr; /* UTOPIA/POS general configuration register */
305 __be32 uplpa; /* UTOPIA/POS last PHY address */
306 __be32 uphec; /* ATM HEC register */
307 __be32 upuc; /* UTOPIA/POS UCC configuration */
308 __be32 updc1; /* UTOPIA/POS device 1 configuration */
309 __be32 updc2; /* UTOPIA/POS device 2 configuration */
310 __be32 updc3; /* UTOPIA/POS device 3 configuration */
311 __be32 updc4; /* UTOPIA/POS device 4 configuration */
312 __be32 upstpa; /* UTOPIA/POS STPA threshold */
313 u8 res0[0xC];
314 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
315 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
316 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
317 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
318 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
319 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
320 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
321 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
322 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
323 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
324 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
325 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
326 __be32 upde1; /* UTOPIA/POS device 1 event */
327 __be32 upde2; /* UTOPIA/POS device 2 event */
328 __be32 upde3; /* UTOPIA/POS device 3 event */
329 __be32 upde4; /* UTOPIA/POS device 4 event */
330 __be16 uprp1;
331 __be16 uprp2;
332 __be16 uprp3;
333 __be16 uprp4;
334 u8 res1[0x8];
335 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
336 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
337 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
338 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
339 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
340 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
341 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
342 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
343 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
344 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
345 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
346 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
347 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
348 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
349 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
350 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
351 __be32 uper1; /* Device 1 port enable register */
352 __be32 uper2; /* Device 2 port enable register */
353 __be32 uper3; /* Device 3 port enable register */
354 __be32 uper4; /* Device 4 port enable register */
355 u8 res2[0x150];
356} __attribute__ ((packed));
357
358/* SDMA */
359struct sdma {
360 __be32 sdsr; /* Serial DMA status register */
361 __be32 sdmr; /* Serial DMA mode register */
362 __be32 sdtr1; /* SDMA system bus threshold register */
363 __be32 sdtr2; /* SDMA secondary bus threshold register */
364 __be32 sdhy1; /* SDMA system bus hysteresis register */
365 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
366 __be32 sdta1; /* SDMA system bus address register */
367 __be32 sdta2; /* SDMA secondary bus address register */
368 __be32 sdtm1; /* SDMA system bus MSNUM register */
369 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
370 u8 res0[0x10];
371 __be32 sdaqr; /* SDMA address bus qualify register */
372 __be32 sdaqmr; /* SDMA address bus qualify mask register */
373 u8 res1[0x4];
374 __be32 sdebcr; /* SDMA CAM entries base register */
375 u8 res2[0x38];
376} __attribute__ ((packed));
377
378/* Debug Space */
379struct dbg {
380 __be32 bpdcr; /* Breakpoint debug command register */
381 __be32 bpdsr; /* Breakpoint debug status register */
382 __be32 bpdmr; /* Breakpoint debug mask register */
383 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
384 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
385 u8 res0[0x8];
386 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
387 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
388 u8 res1[0x8];
389 __be32 bprmir; /* Breakpoint request mode immediate register */
390 __be32 bprmsr; /* Breakpoint request mode serial register */
391 __be32 bpemr; /* Breakpoint exit mode register */
392 u8 res2[0x48];
393} __attribute__ ((packed));
394
395/*
396 * RISC Special Registers (Trap and Breakpoint). These are described in
397 * the QE Developer's Handbook.
398 */
399struct rsp {
400 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
401 u8 res0[64];
402 __be32 ibcr0;
403 __be32 ibs0;
404 __be32 ibcnr0;
405 u8 res1[4];
406 __be32 ibcr1;
407 __be32 ibs1;
408 __be32 ibcnr1;
409 __be32 npcr;
410 __be32 dbcr;
411 __be32 dbar;
412 __be32 dbamr;
413 __be32 dbsr;
414 __be32 dbcnr;
415 u8 res2[12];
416 __be32 dbdr_h;
417 __be32 dbdr_l;
418 __be32 dbdmr_h;
419 __be32 dbdmr_l;
420 __be32 bsr;
421 __be32 bor;
422 __be32 bior;
423 u8 res3[4];
424 __be32 iatr[4];
425 __be32 eccr; /* Exception control configuration register */
426 __be32 eicr;
427 u8 res4[0x100-0xf8];
428} __attribute__ ((packed));
429
430struct qe_immap {
431 struct qe_iram iram; /* I-RAM */
432 struct qe_ic_regs ic; /* Interrupt Controller */
433 struct cp_qe cp; /* Communications Processor */
434 struct qe_mux qmx; /* QE Multiplexer */
435 struct qe_timers qet; /* QE Timers */
436 struct spi spi[0x2]; /* spi */
437 struct mcc mcc; /* mcc */
438 struct qe_brg brg; /* brg */
439 struct usb_ctlr usb; /* USB */
440 struct si1 si1; /* SI */
441 u8 res11[0x800];
442 struct sir sir; /* SI Routing Tables */
443 struct ucc ucc1; /* ucc1 */
444 struct ucc ucc3; /* ucc3 */
445 struct ucc ucc5; /* ucc5 */
446 struct ucc ucc7; /* ucc7 */
447 u8 res12[0x600];
448 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
449 struct ucc ucc2; /* ucc2 */
450 struct ucc ucc4; /* ucc4 */
451 struct ucc ucc6; /* ucc6 */
452 struct ucc ucc8; /* ucc8 */
453 u8 res13[0x600];
454 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
455 struct sdma sdma; /* SDMA */
456 struct dbg dbg; /* 0x104080 - 0x1040FF
457 Debug Space */
458 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
459 RISC Special Registers
460 (Trap and Breakpoint) */
461 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
462 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
463 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
464 u8 muram[0xC000]; /* 0x110000 - 0x11C000
465 Multi-user RAM */
466 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
467 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
468} __attribute__ ((packed));
469
470extern struct qe_immap __iomem *qe_immr;
471extern phys_addr_t get_qe_base(void);
472
473static inline unsigned long immrbar_virt_to_phys(void *address)
474{
475 if ( ((u32)address >= (u32)qe_immr) &&
476 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
477 return (unsigned long)(address - (u32)qe_immr +
478 (u32)get_qe_base());
479 return (unsigned long)virt_to_phys(address);
480}
481
482#endif /* __KERNEL__ */
483#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/arch/powerpc/include/asm/io-defs.h b/arch/powerpc/include/asm/io-defs.h
new file mode 100644
index 000000000000..44d7927aec69
--- /dev/null
+++ b/arch/powerpc/include/asm/io-defs.h
@@ -0,0 +1,60 @@
1/* This file is meant to be include multiple times by other headers */
2/* last 2 argments are used by platforms/cell/io-workarounds.[ch] */
3
4DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr), mem, addr)
5DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
6DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
7DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
8DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
9DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
10DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
11DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
12DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
13DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
14
15#ifdef __powerpc64__
16DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
17DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
18DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
19DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
20#endif /* __powerpc64__ */
21
22DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
23DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
24DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
25DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
26DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
27DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
28
29DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c),
30 (a, b, c), mem, a)
31DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c),
32 (a, b, c), mem, a)
33DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c),
34 (a, b, c), mem, a)
35DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c),
36 (a, b, c), mem, a)
37DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c),
38 (a, b, c), mem, a)
39DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c),
40 (a, b, c), mem, a)
41
42DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c),
43 (p, b, c), pio, p)
44DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
45 (p, b, c), pio, p)
46DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
47 (p, b, c), pio, p)
48DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
49 (p, b, c), pio, p)
50DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
51 (p, b, c), pio, p)
52DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
53 (p, b, c), pio, p)
54
55DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),
56 (a, c, n), mem, a)
57DEF_PCI_AC_NORET(memcpy_fromio, (void *d, const PCI_IO_ADDR s, unsigned long n),
58 (d, s, n), mem, s)
59DEF_PCI_AC_NORET(memcpy_toio, (PCI_IO_ADDR d, const void *s, unsigned long n),
60 (d, s, n), mem, d)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
new file mode 100644
index 000000000000..77c7fa025e65
--- /dev/null
+++ b/arch/powerpc/include/asm/io.h
@@ -0,0 +1,787 @@
1#ifndef _ASM_POWERPC_IO_H
2#define _ASM_POWERPC_IO_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/* Check of existence of legacy devices */
13extern int check_legacy_ioport(unsigned long base_port);
14#define I8042_DATA_REG 0x60
15#define FDC_BASE 0x3f0
16/* only relevant for PReP */
17#define _PIDXR 0x279
18#define _PNPWRP 0xa79
19#define PNPBIOS_BASE 0xf000
20
21#include <linux/device.h>
22#include <linux/io.h>
23
24#include <linux/compiler.h>
25#include <asm/page.h>
26#include <asm/byteorder.h>
27#include <asm/synch.h>
28#include <asm/delay.h>
29#include <asm/mmu.h>
30
31#include <asm-generic/iomap.h>
32
33#ifdef CONFIG_PPC64
34#include <asm/paca.h>
35#endif
36
37#define SIO_CONFIG_RA 0x398
38#define SIO_CONFIG_RD 0x399
39
40#define SLOW_DOWN_IO
41
42/* 32 bits uses slightly different variables for the various IO
43 * bases. Most of this file only uses _IO_BASE though which we
44 * define properly based on the platform
45 */
46#ifndef CONFIG_PCI
47#define _IO_BASE 0
48#define _ISA_MEM_BASE 0
49#define PCI_DRAM_OFFSET 0
50#elif defined(CONFIG_PPC32)
51#define _IO_BASE isa_io_base
52#define _ISA_MEM_BASE isa_mem_base
53#define PCI_DRAM_OFFSET pci_dram_offset
54#else
55#define _IO_BASE pci_io_base
56#define _ISA_MEM_BASE isa_mem_base
57#define PCI_DRAM_OFFSET 0
58#endif
59
60extern unsigned long isa_io_base;
61extern unsigned long pci_io_base;
62extern unsigned long pci_dram_offset;
63
64extern resource_size_t isa_mem_base;
65
66#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
67#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
68#endif
69
70/*
71 *
72 * Low level MMIO accessors
73 *
74 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
75 * specific and thus shouldn't be used in generic code. The accessors
76 * provided here are:
77 *
78 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
79 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
80 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
81 *
82 * Those operate directly on a kernel virtual address. Note that the prototype
83 * for the out_* accessors has the arguments in opposite order from the usual
84 * linux PCI accessors. Unlike those, they take the address first and the value
85 * next.
86 *
87 * Note: I might drop the _ns suffix on the stream operations soon as it is
88 * simply normal for stream operations to not swap in the first place.
89 *
90 */
91
92#ifdef CONFIG_PPC64
93#define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
94#else
95#define IO_SET_SYNC_FLAG()
96#endif
97
98/* gcc 4.0 and older doesn't have 'Z' constraint */
99#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
100#define DEF_MMIO_IN_LE(name, size, insn) \
101static inline u##size name(const volatile u##size __iomem *addr) \
102{ \
103 u##size ret; \
104 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
105 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
106 return ret; \
107}
108
109#define DEF_MMIO_OUT_LE(name, size, insn) \
110static inline void name(volatile u##size __iomem *addr, u##size val) \
111{ \
112 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
113 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
114 IO_SET_SYNC_FLAG(); \
115}
116#else /* newer gcc */
117#define DEF_MMIO_IN_LE(name, size, insn) \
118static inline u##size name(const volatile u##size __iomem *addr) \
119{ \
120 u##size ret; \
121 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
122 : "=r" (ret) : "Z" (*addr) : "memory"); \
123 return ret; \
124}
125
126#define DEF_MMIO_OUT_LE(name, size, insn) \
127static inline void name(volatile u##size __iomem *addr, u##size val) \
128{ \
129 __asm__ __volatile__("sync;"#insn" %1,%y0" \
130 : "=Z" (*addr) : "r" (val) : "memory"); \
131 IO_SET_SYNC_FLAG(); \
132}
133#endif
134
135#define DEF_MMIO_IN_BE(name, size, insn) \
136static inline u##size name(const volatile u##size __iomem *addr) \
137{ \
138 u##size ret; \
139 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
140 : "=r" (ret) : "m" (*addr) : "memory"); \
141 return ret; \
142}
143
144#define DEF_MMIO_OUT_BE(name, size, insn) \
145static inline void name(volatile u##size __iomem *addr, u##size val) \
146{ \
147 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
148 : "=m" (*addr) : "r" (val) : "memory"); \
149 IO_SET_SYNC_FLAG(); \
150}
151
152
153DEF_MMIO_IN_BE(in_8, 8, lbz);
154DEF_MMIO_IN_BE(in_be16, 16, lhz);
155DEF_MMIO_IN_BE(in_be32, 32, lwz);
156DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
157DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
158
159DEF_MMIO_OUT_BE(out_8, 8, stb);
160DEF_MMIO_OUT_BE(out_be16, 16, sth);
161DEF_MMIO_OUT_BE(out_be32, 32, stw);
162DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
163DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
164
165#ifdef __powerpc64__
166DEF_MMIO_OUT_BE(out_be64, 64, std);
167DEF_MMIO_IN_BE(in_be64, 64, ld);
168
169/* There is no asm instructions for 64 bits reverse loads and stores */
170static inline u64 in_le64(const volatile u64 __iomem *addr)
171{
172 return swab64(in_be64(addr));
173}
174
175static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176{
177 out_be64(addr, swab64(val));
178}
179#endif /* __powerpc64__ */
180
181/*
182 * Low level IO stream instructions are defined out of line for now
183 */
184extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
185extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
186extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
187extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
188extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
189extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
190
191/* The _ns naming is historical and will be removed. For now, just #define
192 * the non _ns equivalent names
193 */
194#define _insw _insw_ns
195#define _insl _insl_ns
196#define _outsw _outsw_ns
197#define _outsl _outsl_ns
198
199
200/*
201 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
202 */
203
204extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
205extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
206 unsigned long n);
207extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
208 unsigned long n);
209
210/*
211 *
212 * PCI and standard ISA accessors
213 *
214 * Those are globally defined linux accessors for devices on PCI or ISA
215 * busses. They follow the Linux defined semantics. The current implementation
216 * for PowerPC is as close as possible to the x86 version of these, and thus
217 * provides fairly heavy weight barriers for the non-raw versions
218 *
219 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
220 * allowing the platform to provide its own implementation of some or all
221 * of the accessors.
222 */
223
224/*
225 * Include the EEH definitions when EEH is enabled only so they don't get
226 * in the way when building for 32 bits
227 */
228#ifdef CONFIG_EEH
229#include <asm/eeh.h>
230#endif
231
232/* Shortcut to the MMIO argument pointer */
233#define PCI_IO_ADDR volatile void __iomem *
234
235/* Indirect IO address tokens:
236 *
237 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
238 * on all IOs. (Note that this is all 64 bits only for now)
239 *
240 * To help platforms who may need to differenciate MMIO addresses in
241 * their hooks, a bitfield is reserved for use by the platform near the
242 * top of MMIO addresses (not PIO, those have to cope the hard way).
243 *
244 * This bit field is 12 bits and is at the top of the IO virtual
245 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
246 *
247 * The kernel virtual space is thus:
248 *
249 * 0xD000000000000000 : vmalloc
250 * 0xD000080000000000 : PCI PHB IO space
251 * 0xD000080080000000 : ioremap
252 * 0xD0000fffffffffff : end of ioremap region
253 *
254 * Since the top 4 bits are reserved as the region ID, we use thus
255 * the next 12 bits and keep 4 bits available for the future if the
256 * virtual address space is ever to be extended.
257 *
258 * The direct IO mapping operations will then mask off those bits
259 * before doing the actual access, though that only happen when
260 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
261 * mechanism
262 */
263
264#ifdef CONFIG_PPC_INDIRECT_IO
265#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
266#define PCI_IO_IND_TOKEN_SHIFT 48
267#define PCI_FIX_ADDR(addr) \
268 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
269#define PCI_GET_ADDR_TOKEN(addr) \
270 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
271 PCI_IO_IND_TOKEN_SHIFT)
272#define PCI_SET_ADDR_TOKEN(addr, token) \
273do { \
274 unsigned long __a = (unsigned long)(addr); \
275 __a &= ~PCI_IO_IND_TOKEN_MASK; \
276 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
277 (addr) = (void __iomem *)__a; \
278} while(0)
279#else
280#define PCI_FIX_ADDR(addr) (addr)
281#endif
282
283
284/*
285 * Non ordered and non-swapping "raw" accessors
286 */
287
288static inline unsigned char __raw_readb(const volatile void __iomem *addr)
289{
290 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
291}
292static inline unsigned short __raw_readw(const volatile void __iomem *addr)
293{
294 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
295}
296static inline unsigned int __raw_readl(const volatile void __iomem *addr)
297{
298 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
299}
300static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
301{
302 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
303}
304static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
305{
306 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
307}
308static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
309{
310 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
311}
312
313#ifdef __powerpc64__
314static inline unsigned long __raw_readq(const volatile void __iomem *addr)
315{
316 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
317}
318static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
319{
320 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
321}
322#endif /* __powerpc64__ */
323
324/*
325 *
326 * PCI PIO and MMIO accessors.
327 *
328 *
329 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
330 * machine checks (which they occasionally do when probing non existing
331 * IO ports on some platforms, like PowerMac and 8xx).
332 * I always found it to be of dubious reliability and I am tempted to get
333 * rid of it one of these days. So if you think it's important to keep it,
334 * please voice up asap. We never had it for 64 bits and I do not intend
335 * to port it over
336 */
337
338#ifdef CONFIG_PPC32
339
340#define __do_in_asm(name, op) \
341static inline unsigned int name(unsigned int port) \
342{ \
343 unsigned int x; \
344 __asm__ __volatile__( \
345 "sync\n" \
346 "0:" op " %0,0,%1\n" \
347 "1: twi 0,%0,0\n" \
348 "2: isync\n" \
349 "3: nop\n" \
350 "4:\n" \
351 ".section .fixup,\"ax\"\n" \
352 "5: li %0,-1\n" \
353 " b 4b\n" \
354 ".previous\n" \
355 ".section __ex_table,\"a\"\n" \
356 " .align 2\n" \
357 " .long 0b,5b\n" \
358 " .long 1b,5b\n" \
359 " .long 2b,5b\n" \
360 " .long 3b,5b\n" \
361 ".previous" \
362 : "=&r" (x) \
363 : "r" (port + _IO_BASE) \
364 : "memory"); \
365 return x; \
366}
367
368#define __do_out_asm(name, op) \
369static inline void name(unsigned int val, unsigned int port) \
370{ \
371 __asm__ __volatile__( \
372 "sync\n" \
373 "0:" op " %0,0,%1\n" \
374 "1: sync\n" \
375 "2:\n" \
376 ".section __ex_table,\"a\"\n" \
377 " .align 2\n" \
378 " .long 0b,2b\n" \
379 " .long 1b,2b\n" \
380 ".previous" \
381 : : "r" (val), "r" (port + _IO_BASE) \
382 : "memory"); \
383}
384
385__do_in_asm(_rec_inb, "lbzx")
386__do_in_asm(_rec_inw, "lhbrx")
387__do_in_asm(_rec_inl, "lwbrx")
388__do_out_asm(_rec_outb, "stbx")
389__do_out_asm(_rec_outw, "sthbrx")
390__do_out_asm(_rec_outl, "stwbrx")
391
392#endif /* CONFIG_PPC32 */
393
394/* The "__do_*" operations below provide the actual "base" implementation
395 * for each of the defined acccessor. Some of them use the out_* functions
396 * directly, some of them still use EEH, though we might change that in the
397 * future. Those macros below provide the necessary argument swapping and
398 * handling of the IO base for PIO.
399 *
400 * They are themselves used by the macros that define the actual accessors
401 * and can be used by the hooks if any.
402 *
403 * Note that PIO operations are always defined in terms of their corresonding
404 * MMIO operations. That allows platforms like iSeries who want to modify the
405 * behaviour of both to only hook on the MMIO version and get both. It's also
406 * possible to hook directly at the toplevel PIO operation if they have to
407 * be handled differently
408 */
409#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
410#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
411#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
412#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
413#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
414#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
415#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
416
417#ifdef CONFIG_EEH
418#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
419#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
420#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
421#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
422#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
423#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
424#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
425#else /* CONFIG_EEH */
426#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
427#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
428#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
429#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
430#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
431#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
432#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
433#endif /* !defined(CONFIG_EEH) */
434
435#ifdef CONFIG_PPC32
436#define __do_outb(val, port) _rec_outb(val, port)
437#define __do_outw(val, port) _rec_outw(val, port)
438#define __do_outl(val, port) _rec_outl(val, port)
439#define __do_inb(port) _rec_inb(port)
440#define __do_inw(port) _rec_inw(port)
441#define __do_inl(port) _rec_inl(port)
442#else /* CONFIG_PPC32 */
443#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
444#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
445#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
446#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
447#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
448#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
449#endif /* !CONFIG_PPC32 */
450
451#ifdef CONFIG_EEH
452#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
453#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
454#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
455#else /* CONFIG_EEH */
456#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
457#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
458#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
459#endif /* !CONFIG_EEH */
460#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
461#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
462#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
463
464#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
465#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
466#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
467#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
468#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
469#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
470
471#define __do_memset_io(addr, c, n) \
472 _memset_io(PCI_FIX_ADDR(addr), c, n)
473#define __do_memcpy_toio(dst, src, n) \
474 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
475
476#ifdef CONFIG_EEH
477#define __do_memcpy_fromio(dst, src, n) \
478 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
479#else /* CONFIG_EEH */
480#define __do_memcpy_fromio(dst, src, n) \
481 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
482#endif /* !CONFIG_EEH */
483
484#ifdef CONFIG_PPC_INDIRECT_IO
485#define DEF_PCI_HOOK(x) x
486#else
487#define DEF_PCI_HOOK(x) NULL
488#endif
489
490/* Structure containing all the hooks */
491extern struct ppc_pci_io {
492
493#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
494#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
495
496#include <asm/io-defs.h>
497
498#undef DEF_PCI_AC_RET
499#undef DEF_PCI_AC_NORET
500
501} ppc_pci_io;
502
503/* The inline wrappers */
504#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
505static inline ret name at \
506{ \
507 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
508 return ppc_pci_io.name al; \
509 return __do_##name al; \
510}
511
512#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
513static inline void name at \
514{ \
515 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
516 ppc_pci_io.name al; \
517 else \
518 __do_##name al; \
519}
520
521#include <asm/io-defs.h>
522
523#undef DEF_PCI_AC_RET
524#undef DEF_PCI_AC_NORET
525
526/* Some drivers check for the presence of readq & writeq with
527 * a #ifdef, so we make them happy here.
528 */
529#ifdef __powerpc64__
530#define readq readq
531#define writeq writeq
532#endif
533
534/*
535 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
536 * access
537 */
538#define xlate_dev_mem_ptr(p) __va(p)
539
540/*
541 * Convert a virtual cached pointer to an uncached pointer
542 */
543#define xlate_dev_kmem_ptr(p) p
544
545/*
546 * We don't do relaxed operations yet, at least not with this semantic
547 */
548#define readb_relaxed(addr) readb(addr)
549#define readw_relaxed(addr) readw(addr)
550#define readl_relaxed(addr) readl(addr)
551#define readq_relaxed(addr) readq(addr)
552
553#ifdef CONFIG_PPC32
554#define mmiowb()
555#else
556/*
557 * Enforce synchronisation of stores vs. spin_unlock
558 * (this does it explicitly, though our implementation of spin_unlock
559 * does it implicitely too)
560 */
561static inline void mmiowb(void)
562{
563 unsigned long tmp;
564
565 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
566 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
567 : "memory");
568}
569#endif /* !CONFIG_PPC32 */
570
571static inline void iosync(void)
572{
573 __asm__ __volatile__ ("sync" : : : "memory");
574}
575
576/* Enforce in-order execution of data I/O.
577 * No distinction between read/write on PPC; use eieio for all three.
578 * Those are fairly week though. They don't provide a barrier between
579 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
580 * they only provide barriers between 2 __raw MMIO operations and
581 * possibly break write combining.
582 */
583#define iobarrier_rw() eieio()
584#define iobarrier_r() eieio()
585#define iobarrier_w() eieio()
586
587
588/*
589 * output pause versions need a delay at least for the
590 * w83c105 ide controller in a p610.
591 */
592#define inb_p(port) inb(port)
593#define outb_p(val, port) (udelay(1), outb((val), (port)))
594#define inw_p(port) inw(port)
595#define outw_p(val, port) (udelay(1), outw((val), (port)))
596#define inl_p(port) inl(port)
597#define outl_p(val, port) (udelay(1), outl((val), (port)))
598
599
600#define IO_SPACE_LIMIT ~(0UL)
601
602
603/**
604 * ioremap - map bus memory into CPU space
605 * @address: bus address of the memory
606 * @size: size of the resource to map
607 *
608 * ioremap performs a platform specific sequence of operations to
609 * make bus memory CPU accessible via the readb/readw/readl/writeb/
610 * writew/writel functions and the other mmio helpers. The returned
611 * address is not guaranteed to be usable directly as a virtual
612 * address.
613 *
614 * We provide a few variations of it:
615 *
616 * * ioremap is the standard one and provides non-cacheable guarded mappings
617 * and can be hooked by the platform via ppc_md
618 *
619 * * ioremap_flags allows to specify the page flags as an argument and can
620 * also be hooked by the platform via ppc_md. ioremap_prot is the exact
621 * same thing as ioremap_flags.
622 *
623 * * ioremap_nocache is identical to ioremap
624 *
625 * * iounmap undoes such a mapping and can be hooked
626 *
627 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
628 * create hand-made mappings for use only by the PCI code and cannot
629 * currently be hooked. Must be page aligned.
630 *
631 * * __ioremap is the low level implementation used by ioremap and
632 * ioremap_flags and cannot be hooked (but can be used by a hook on one
633 * of the previous ones)
634 *
635 * * __iounmap, is the low level implementation used by iounmap and cannot
636 * be hooked (but can be used by a hook on iounmap)
637 *
638 */
639extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
640extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
641 unsigned long flags);
642#define ioremap_nocache(addr, size) ioremap((addr), (size))
643#define ioremap_prot(addr, size, prot) ioremap_flags((addr), (size), (prot))
644
645extern void iounmap(volatile void __iomem *addr);
646
647extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
648 unsigned long flags);
649extern void __iounmap(volatile void __iomem *addr);
650
651extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
652 unsigned long size, unsigned long flags);
653extern void __iounmap_at(void *ea, unsigned long size);
654
655/*
656 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
657 * which needs some additional definitions here. They basically allow PIO
658 * space overall to be 1GB. This will work as long as we never try to use
659 * iomap to map MMIO below 1GB which should be fine on ppc64
660 */
661#define HAVE_ARCH_PIO_SIZE 1
662#define PIO_OFFSET 0x00000000UL
663#define PIO_MASK (FULL_IO_SIZE - 1)
664#define PIO_RESERVED (FULL_IO_SIZE)
665
666#define mmio_read16be(addr) readw_be(addr)
667#define mmio_read32be(addr) readl_be(addr)
668#define mmio_write16be(val, addr) writew_be(val, addr)
669#define mmio_write32be(val, addr) writel_be(val, addr)
670#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
671#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
672#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
673#define mmio_outsb(addr, src, count) writesb(addr, src, count)
674#define mmio_outsw(addr, src, count) writesw(addr, src, count)
675#define mmio_outsl(addr, src, count) writesl(addr, src, count)
676
677/**
678 * virt_to_phys - map virtual addresses to physical
679 * @address: address to remap
680 *
681 * The returned physical address is the physical (CPU) mapping for
682 * the memory address given. It is only valid to use this function on
683 * addresses directly mapped or allocated via kmalloc.
684 *
685 * This function does not give bus mappings for DMA transfers. In
686 * almost all conceivable cases a device driver should not be using
687 * this function
688 */
689static inline unsigned long virt_to_phys(volatile void * address)
690{
691 return __pa((unsigned long)address);
692}
693
694/**
695 * phys_to_virt - map physical address to virtual
696 * @address: address to remap
697 *
698 * The returned virtual address is a current CPU mapping for
699 * the memory address given. It is only valid to use this function on
700 * addresses that have a kernel mapping
701 *
702 * This function does not handle bus mappings for DMA transfers. In
703 * almost all conceivable cases a device driver should not be using
704 * this function
705 */
706static inline void * phys_to_virt(unsigned long address)
707{
708 return (void *)__va(address);
709}
710
711/*
712 * Change "struct page" to physical address.
713 */
714#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
715
716/* We do NOT want virtual merging, it would put too much pressure on
717 * our iommu allocator. Instead, we want drivers to be smart enough
718 * to coalesce sglists that happen to have been mapped in a contiguous
719 * way by the iommu
720 */
721#define BIO_VMERGE_BOUNDARY 0
722
723/*
724 * 32 bits still uses virt_to_bus() for it's implementation of DMA
725 * mappings se we have to keep it defined here. We also have some old
726 * drivers (shame shame shame) that use bus_to_virt() and haven't been
727 * fixed yet so I need to define it here.
728 */
729#ifdef CONFIG_PPC32
730
731static inline unsigned long virt_to_bus(volatile void * address)
732{
733 if (address == NULL)
734 return 0;
735 return __pa(address) + PCI_DRAM_OFFSET;
736}
737
738static inline void * bus_to_virt(unsigned long address)
739{
740 if (address == 0)
741 return NULL;
742 return __va(address - PCI_DRAM_OFFSET);
743}
744
745#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
746
747#endif /* CONFIG_PPC32 */
748
749/* access ports */
750#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
751#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
752
753#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
754#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
755
756#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
757#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
758
759/* Clear and set bits in one shot. These macros can be used to clear and
760 * set multiple bits in a register using a single read-modify-write. These
761 * macros can also be used to set a multiple-bit bit pattern using a mask,
762 * by specifying the mask in the 'clear' parameter and the new bit pattern
763 * in the 'set' parameter.
764 */
765
766#define clrsetbits(type, addr, clear, set) \
767 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
768
769#ifdef __powerpc64__
770#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
771#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
772#endif
773
774#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
775#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
776
777#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
778#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
779
780#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
781
782void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
783 size_t size, unsigned long flags);
784
785#endif /* __KERNEL__ */
786
787#endif /* _ASM_POWERPC_IO_H */
diff --git a/arch/powerpc/include/asm/ioctl.h b/arch/powerpc/include/asm/ioctl.h
new file mode 100644
index 000000000000..57d68304218b
--- /dev/null
+++ b/arch/powerpc/include/asm/ioctl.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_POWERPC_IOCTL_H
2#define _ASM_POWERPC_IOCTL_H
3
4#define _IOC_SIZEBITS 13
5#define _IOC_DIRBITS 3
6
7#define _IOC_NONE 1U
8#define _IOC_READ 2U
9#define _IOC_WRITE 4U
10
11#include <asm-generic/ioctl.h>
12
13#endif /* _ASM_POWERPC_IOCTL_H */
diff --git a/arch/powerpc/include/asm/ioctls.h b/arch/powerpc/include/asm/ioctls.h
new file mode 100644
index 000000000000..279a6229584b
--- /dev/null
+++ b/arch/powerpc/include/asm/ioctls.h
@@ -0,0 +1,110 @@
1#ifndef _ASM_POWERPC_IOCTLS_H
2#define _ASM_POWERPC_IOCTLS_H
3
4#include <asm/ioctl.h>
5
6#define FIOCLEX _IO('f', 1)
7#define FIONCLEX _IO('f', 2)
8#define FIOASYNC _IOW('f', 125, int)
9#define FIONBIO _IOW('f', 126, int)
10#define FIONREAD _IOR('f', 127, int)
11#define TIOCINQ FIONREAD
12#define FIOQSIZE _IOR('f', 128, loff_t)
13
14#define TIOCGETP _IOR('t', 8, struct sgttyb)
15#define TIOCSETP _IOW('t', 9, struct sgttyb)
16#define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */
17
18#define TIOCSETC _IOW('t', 17, struct tchars)
19#define TIOCGETC _IOR('t', 18, struct tchars)
20#define TCGETS _IOR('t', 19, struct termios)
21#define TCSETS _IOW('t', 20, struct termios)
22#define TCSETSW _IOW('t', 21, struct termios)
23#define TCSETSF _IOW('t', 22, struct termios)
24
25#define TCGETA _IOR('t', 23, struct termio)
26#define TCSETA _IOW('t', 24, struct termio)
27#define TCSETAW _IOW('t', 25, struct termio)
28#define TCSETAF _IOW('t', 28, struct termio)
29
30#define TCSBRK _IO('t', 29)
31#define TCXONC _IO('t', 30)
32#define TCFLSH _IO('t', 31)
33
34#define TIOCSWINSZ _IOW('t', 103, struct winsize)
35#define TIOCGWINSZ _IOR('t', 104, struct winsize)
36#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
37#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
38#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
39
40#define TIOCGLTC _IOR('t', 116, struct ltchars)
41#define TIOCSLTC _IOW('t', 117, struct ltchars)
42#define TIOCSPGRP _IOW('t', 118, int)
43#define TIOCGPGRP _IOR('t', 119, int)
44
45#define TIOCEXCL 0x540C
46#define TIOCNXCL 0x540D
47#define TIOCSCTTY 0x540E
48
49#define TIOCSTI 0x5412
50#define TIOCMGET 0x5415
51#define TIOCMBIS 0x5416
52#define TIOCMBIC 0x5417
53#define TIOCMSET 0x5418
54# define TIOCM_LE 0x001
55# define TIOCM_DTR 0x002
56# define TIOCM_RTS 0x004
57# define TIOCM_ST 0x008
58# define TIOCM_SR 0x010
59# define TIOCM_CTS 0x020
60# define TIOCM_CAR 0x040
61# define TIOCM_RNG 0x080
62# define TIOCM_DSR 0x100
63# define TIOCM_CD TIOCM_CAR
64# define TIOCM_RI TIOCM_RNG
65#define TIOCM_OUT1 0x2000
66#define TIOCM_OUT2 0x4000
67#define TIOCM_LOOP 0x8000
68
69#define TIOCGSOFTCAR 0x5419
70#define TIOCSSOFTCAR 0x541A
71#define TIOCLINUX 0x541C
72#define TIOCCONS 0x541D
73#define TIOCGSERIAL 0x541E
74#define TIOCSSERIAL 0x541F
75#define TIOCPKT 0x5420
76# define TIOCPKT_DATA 0
77# define TIOCPKT_FLUSHREAD 1
78# define TIOCPKT_FLUSHWRITE 2
79# define TIOCPKT_STOP 4
80# define TIOCPKT_START 8
81# define TIOCPKT_NOSTOP 16
82# define TIOCPKT_DOSTOP 32
83
84
85#define TIOCNOTTY 0x5422
86#define TIOCSETD 0x5423
87#define TIOCGETD 0x5424
88#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
89#define TIOCSBRK 0x5427 /* BSD compatibility */
90#define TIOCCBRK 0x5428 /* BSD compatibility */
91#define TIOCGSID 0x5429 /* Return the session ID of FD */
92#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
93#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
94
95#define TIOCSERCONFIG 0x5453
96#define TIOCSERGWILD 0x5454
97#define TIOCSERSWILD 0x5455
98#define TIOCGLCKTRMIOS 0x5456
99#define TIOCSLCKTRMIOS 0x5457
100#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
101#define TIOCSERGETLSR 0x5459 /* Get line status register */
102 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
103# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
104#define TIOCSERGETMULTI 0x545A /* Get multiport config */
105#define TIOCSERSETMULTI 0x545B /* Set multiport config */
106
107#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
108#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
109
110#endif /* _ASM_POWERPC_IOCTLS_H */
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
new file mode 100644
index 000000000000..51ecfef8d843
--- /dev/null
+++ b/arch/powerpc/include/asm/iommu.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_IOMMU_H
22#define _ASM_IOMMU_H
23#ifdef __KERNEL__
24
25#include <linux/compiler.h>
26#include <linux/spinlock.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29#include <linux/bitops.h>
30#include <asm/machdep.h>
31#include <asm/types.h>
32
33#define IOMMU_PAGE_SHIFT 12
34#define IOMMU_PAGE_SIZE (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
35#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
36#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
37
38/* Boot time flags */
39extern int iommu_is_off;
40extern int iommu_force_on;
41
42/* Pure 2^n version of get_order */
43static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
44{
45 return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
46}
47
48
49/*
50 * IOMAP_MAX_ORDER defines the largest contiguous block
51 * of dma space we can get. IOMAP_MAX_ORDER = 13
52 * allows up to 2**12 pages (4096 * 4096) = 16 MB
53 */
54#define IOMAP_MAX_ORDER 13
55
56struct iommu_table {
57 unsigned long it_busno; /* Bus number this table belongs to */
58 unsigned long it_size; /* Size of iommu table in entries */
59 unsigned long it_offset; /* Offset into global table */
60 unsigned long it_base; /* mapped address of tce table */
61 unsigned long it_index; /* which iommu table this is */
62 unsigned long it_type; /* type: PCI or Virtual Bus */
63 unsigned long it_blocksize; /* Entries in each block (cacheline) */
64 unsigned long it_hint; /* Hint for next alloc */
65 unsigned long it_largehint; /* Hint for large allocs */
66 unsigned long it_halfpoint; /* Breaking point for small/large allocs */
67 spinlock_t it_lock; /* Protects it_map */
68 unsigned long *it_map; /* A simple allocation bitmap for now */
69};
70
71struct scatterlist;
72
73/* Frees table for an individual device node */
74extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
75
76/* Initializes an iommu_table based in values set in the passed-in
77 * structure
78 */
79extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
80 int nid);
81
82extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
83 struct scatterlist *sglist, int nelems,
84 unsigned long mask, enum dma_data_direction direction,
85 struct dma_attrs *attrs);
86extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
87 int nelems, enum dma_data_direction direction,
88 struct dma_attrs *attrs);
89
90extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
91 size_t size, dma_addr_t *dma_handle,
92 unsigned long mask, gfp_t flag, int node);
93extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
94 void *vaddr, dma_addr_t dma_handle);
95extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl,
96 void *vaddr, size_t size, unsigned long mask,
97 enum dma_data_direction direction,
98 struct dma_attrs *attrs);
99extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
100 size_t size, enum dma_data_direction direction,
101 struct dma_attrs *attrs);
102
103extern void iommu_init_early_pSeries(void);
104extern void iommu_init_early_iSeries(void);
105extern void iommu_init_early_dart(void);
106extern void iommu_init_early_pasemi(void);
107
108#ifdef CONFIG_PCI
109extern void pci_iommu_init(void);
110extern void pci_direct_iommu_init(void);
111#else
112static inline void pci_iommu_init(void) { }
113#endif
114
115extern void alloc_dart_table(void);
116#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
117static inline void iommu_save(void)
118{
119 if (ppc_md.iommu_save)
120 ppc_md.iommu_save();
121}
122
123static inline void iommu_restore(void)
124{
125 if (ppc_md.iommu_restore)
126 ppc_md.iommu_restore();
127}
128#endif
129
130#endif /* __KERNEL__ */
131#endif /* _ASM_IOMMU_H */
diff --git a/arch/powerpc/include/asm/ipcbuf.h b/arch/powerpc/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..2c3e1d94db1d
--- /dev/null
+++ b/arch/powerpc/include/asm/ipcbuf.h
@@ -0,0 +1,34 @@
1#ifndef _ASM_POWERPC_IPCBUF_H
2#define _ASM_POWERPC_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for the powerpc is identical to
6 * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the
7 * kernel. Note extra padding because this structure is passed back
8 * and forth between kernel and user space. Pad space is left for:
9 * - 1 32-bit value to fill up for 8-byte alignment
10 * - 2 miscellaneous 64-bit values
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/types.h>
19
20struct ipc64_perm
21{
22 __kernel_key_t key;
23 __kernel_uid_t uid;
24 __kernel_gid_t gid;
25 __kernel_uid_t cuid;
26 __kernel_gid_t cgid;
27 __kernel_mode_t mode;
28 unsigned int seq;
29 unsigned int __pad1;
30 unsigned long long __unused1;
31 unsigned long long __unused2;
32};
33
34#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/arch/powerpc/include/asm/ipic.h b/arch/powerpc/include/asm/ipic.h
new file mode 100644
index 000000000000..4cf35531c0ef
--- /dev/null
+++ b/arch/powerpc/include/asm/ipic.h
@@ -0,0 +1,91 @@
1/*
2 * IPIC external definitions and structure.
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifdef __KERNEL__
14#ifndef __ASM_IPIC_H__
15#define __ASM_IPIC_H__
16
17#include <linux/irq.h>
18
19/* Flags when we init the IPIC */
20#define IPIC_SPREADMODE_GRP_A 0x00000001
21#define IPIC_SPREADMODE_GRP_B 0x00000002
22#define IPIC_SPREADMODE_GRP_C 0x00000004
23#define IPIC_SPREADMODE_GRP_D 0x00000008
24#define IPIC_SPREADMODE_MIX_A 0x00000010
25#define IPIC_SPREADMODE_MIX_B 0x00000020
26#define IPIC_DISABLE_MCP_OUT 0x00000040
27#define IPIC_IRQ0_MCP 0x00000080
28
29/* IPIC registers offsets */
30#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
31#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
32#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
33#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
34#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
35#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
36#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
37#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
38#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
39#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
40#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
41#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
42#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
43#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
44#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
45#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
46#define IPIC_SERSR 0x40 /* System Error Status Register */
47#define IPIC_SERMR 0x44 /* System Error Mask Register */
48#define IPIC_SERCR 0x48 /* System Error Control Register */
49#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
50#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
51#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
52#define IPIC_SERFR 0x5C /* System Error Force Register */
53#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
54#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
55
56enum ipic_prio_grp {
57 IPIC_INT_GRP_A = IPIC_SIPRR_A,
58 IPIC_INT_GRP_D = IPIC_SIPRR_D,
59 IPIC_MIX_GRP_A = IPIC_SMPRR_A,
60 IPIC_MIX_GRP_B = IPIC_SMPRR_B,
61};
62
63enum ipic_mcp_irq {
64 IPIC_MCP_IRQ0 = 0,
65 IPIC_MCP_WDT = 1,
66 IPIC_MCP_SBA = 2,
67 IPIC_MCP_PCI1 = 5,
68 IPIC_MCP_PCI2 = 6,
69 IPIC_MCP_MU = 7,
70};
71
72extern int ipic_set_priority(unsigned int irq, unsigned int priority);
73extern void ipic_set_highest_priority(unsigned int irq);
74extern void ipic_set_default_priority(void);
75extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
76extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
77extern u32 ipic_get_mcp_status(void);
78extern void ipic_clear_mcp_status(u32 mask);
79
80#ifdef CONFIG_PPC_MERGE
81extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
82extern unsigned int ipic_get_irq(void);
83#else
84extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
85 unsigned int irq_offset,
86 unsigned char *senses, unsigned int senses_count);
87extern int ipic_get_irq(void);
88#endif
89
90#endif /* __ASM_IPIC_H__ */
91#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
new file mode 100644
index 000000000000..1ef8e304e0ea
--- /dev/null
+++ b/arch/powerpc/include/asm/irq.h
@@ -0,0 +1,654 @@
1#ifdef __KERNEL__
2#ifndef _ASM_POWERPC_IRQ_H
3#define _ASM_POWERPC_IRQ_H
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/threads.h>
13#include <linux/list.h>
14#include <linux/radix-tree.h>
15
16#include <asm/types.h>
17#include <asm/atomic.h>
18
19
20#define get_irq_desc(irq) (&irq_desc[(irq)])
21
22/* Define a way to iterate across irqs. */
23#define for_each_irq(i) \
24 for ((i) = 0; (i) < NR_IRQS; ++(i))
25
26extern atomic_t ppc_n_lost_interrupts;
27
28#ifdef CONFIG_PPC_MERGE
29
30/* This number is used when no interrupt has been assigned */
31#define NO_IRQ (0)
32
33/* This is a special irq number to return from get_irq() to tell that
34 * no interrupt happened _and_ ignore it (don't count it as bad). Some
35 * platforms like iSeries rely on that.
36 */
37#define NO_IRQ_IGNORE ((unsigned int)-1)
38
39/* Total number of virq in the platform (make it a CONFIG_* option ? */
40#define NR_IRQS 512
41
42/* Number of irqs reserved for the legacy controller */
43#define NUM_ISA_INTERRUPTS 16
44
45/* This type is the placeholder for a hardware interrupt number. It has to
46 * be big enough to enclose whatever representation is used by a given
47 * platform.
48 */
49typedef unsigned long irq_hw_number_t;
50
51/* Interrupt controller "host" data structure. This could be defined as a
52 * irq domain controller. That is, it handles the mapping between hardware
53 * and virtual interrupt numbers for a given interrupt domain. The host
54 * structure is generally created by the PIC code for a given PIC instance
55 * (though a host can cover more than one PIC if they have a flat number
56 * model). It's the host callbacks that are responsible for setting the
57 * irq_chip on a given irq_desc after it's been mapped.
58 *
59 * The host code and data structures are fairly agnostic to the fact that
60 * we use an open firmware device-tree. We do have references to struct
61 * device_node in two places: in irq_find_host() to find the host matching
62 * a given interrupt controller node, and of course as an argument to its
63 * counterpart host->ops->match() callback. However, those are treated as
64 * generic pointers by the core and the fact that it's actually a device-node
65 * pointer is purely a convention between callers and implementation. This
66 * code could thus be used on other architectures by replacing those two
67 * by some sort of arch-specific void * "token" used to identify interrupt
68 * controllers.
69 */
70struct irq_host;
71struct radix_tree_root;
72
73/* Functions below are provided by the host and called whenever a new mapping
74 * is created or an old mapping is disposed. The host can then proceed to
75 * whatever internal data structures management is required. It also needs
76 * to setup the irq_desc when returning from map().
77 */
78struct irq_host_ops {
79 /* Match an interrupt controller device node to a host, returns
80 * 1 on a match
81 */
82 int (*match)(struct irq_host *h, struct device_node *node);
83
84 /* Create or update a mapping between a virtual irq number and a hw
85 * irq number. This is called only once for a given mapping.
86 */
87 int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
88
89 /* Dispose of such a mapping */
90 void (*unmap)(struct irq_host *h, unsigned int virq);
91
92 /* Update of such a mapping */
93 void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
94
95 /* Translate device-tree interrupt specifier from raw format coming
96 * from the firmware to a irq_hw_number_t (interrupt line number) and
97 * type (sense) that can be passed to set_irq_type(). In the absence
98 * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
99 * will return the hw number in the first cell and IRQ_TYPE_NONE for
100 * the type (which amount to keeping whatever default value the
101 * interrupt controller has for that line)
102 */
103 int (*xlate)(struct irq_host *h, struct device_node *ctrler,
104 u32 *intspec, unsigned int intsize,
105 irq_hw_number_t *out_hwirq, unsigned int *out_type);
106};
107
108struct irq_host {
109 struct list_head link;
110
111 /* type of reverse mapping technique */
112 unsigned int revmap_type;
113#define IRQ_HOST_MAP_LEGACY 0 /* legacy 8259, gets irqs 1..15 */
114#define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
115#define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
116#define IRQ_HOST_MAP_TREE 3 /* radix tree */
117 union {
118 struct {
119 unsigned int size;
120 unsigned int *revmap;
121 } linear;
122 struct radix_tree_root tree;
123 } revmap_data;
124 struct irq_host_ops *ops;
125 void *host_data;
126 irq_hw_number_t inval_irq;
127
128 /* Optional device node pointer */
129 struct device_node *of_node;
130};
131
132/* The main irq map itself is an array of NR_IRQ entries containing the
133 * associate host and irq number. An entry with a host of NULL is free.
134 * An entry can be allocated if it's free, the allocator always then sets
135 * hwirq first to the host's invalid irq number and then fills ops.
136 */
137struct irq_map_entry {
138 irq_hw_number_t hwirq;
139 struct irq_host *host;
140};
141
142extern struct irq_map_entry irq_map[NR_IRQS];
143
144extern irq_hw_number_t virq_to_hw(unsigned int virq);
145
146/**
147 * irq_alloc_host - Allocate a new irq_host data structure
148 * @of_node: optional device-tree node of the interrupt controller
149 * @revmap_type: type of reverse mapping to use
150 * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
151 * @ops: map/unmap host callbacks
152 * @inval_irq: provide a hw number in that host space that is always invalid
153 *
154 * Allocates and initialize and irq_host structure. Note that in the case of
155 * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
156 * for all legacy interrupts except 0 (which is always the invalid irq for
157 * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
158 * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
159 * later during boot automatically (the reverse mapping will use the slow path
160 * until that happens).
161 */
162extern struct irq_host *irq_alloc_host(struct device_node *of_node,
163 unsigned int revmap_type,
164 unsigned int revmap_arg,
165 struct irq_host_ops *ops,
166 irq_hw_number_t inval_irq);
167
168
169/**
170 * irq_find_host - Locates a host for a given device node
171 * @node: device-tree node of the interrupt controller
172 */
173extern struct irq_host *irq_find_host(struct device_node *node);
174
175
176/**
177 * irq_set_default_host - Set a "default" host
178 * @host: default host pointer
179 *
180 * For convenience, it's possible to set a "default" host that will be used
181 * whenever NULL is passed to irq_create_mapping(). It makes life easier for
182 * platforms that want to manipulate a few hard coded interrupt numbers that
183 * aren't properly represented in the device-tree.
184 */
185extern void irq_set_default_host(struct irq_host *host);
186
187
188/**
189 * irq_set_virq_count - Set the maximum number of virt irqs
190 * @count: number of linux virtual irqs, capped with NR_IRQS
191 *
192 * This is mainly for use by platforms like iSeries who want to program
193 * the virtual irq number in the controller to avoid the reverse mapping
194 */
195extern void irq_set_virq_count(unsigned int count);
196
197
198/**
199 * irq_create_mapping - Map a hardware interrupt into linux virq space
200 * @host: host owning this hardware interrupt or NULL for default host
201 * @hwirq: hardware irq number in that host space
202 *
203 * Only one mapping per hardware interrupt is permitted. Returns a linux
204 * virq number.
205 * If the sense/trigger is to be specified, set_irq_type() should be called
206 * on the number returned from that call.
207 */
208extern unsigned int irq_create_mapping(struct irq_host *host,
209 irq_hw_number_t hwirq);
210
211
212/**
213 * irq_dispose_mapping - Unmap an interrupt
214 * @virq: linux virq number of the interrupt to unmap
215 */
216extern void irq_dispose_mapping(unsigned int virq);
217
218/**
219 * irq_find_mapping - Find a linux virq from an hw irq number.
220 * @host: host owning this hardware interrupt
221 * @hwirq: hardware irq number in that host space
222 *
223 * This is a slow path, for use by generic code. It's expected that an
224 * irq controller implementation directly calls the appropriate low level
225 * mapping function.
226 */
227extern unsigned int irq_find_mapping(struct irq_host *host,
228 irq_hw_number_t hwirq);
229
230/**
231 * irq_create_direct_mapping - Allocate a virq for direct mapping
232 * @host: host to allocate the virq for or NULL for default host
233 *
234 * This routine is used for irq controllers which can choose the hardware
235 * interrupt numbers they generate. In such a case it's simplest to use
236 * the linux virq as the hardware interrupt number.
237 */
238extern unsigned int irq_create_direct_mapping(struct irq_host *host);
239
240/**
241 * irq_radix_revmap - Find a linux virq from a hw irq number.
242 * @host: host owning this hardware interrupt
243 * @hwirq: hardware irq number in that host space
244 *
245 * This is a fast path, for use by irq controller code that uses radix tree
246 * revmaps
247 */
248extern unsigned int irq_radix_revmap(struct irq_host *host,
249 irq_hw_number_t hwirq);
250
251/**
252 * irq_linear_revmap - Find a linux virq from a hw irq number.
253 * @host: host owning this hardware interrupt
254 * @hwirq: hardware irq number in that host space
255 *
256 * This is a fast path, for use by irq controller code that uses linear
257 * revmaps. It does fallback to the slow path if the revmap doesn't exist
258 * yet and will create the revmap entry with appropriate locking
259 */
260
261extern unsigned int irq_linear_revmap(struct irq_host *host,
262 irq_hw_number_t hwirq);
263
264
265
266/**
267 * irq_alloc_virt - Allocate virtual irq numbers
268 * @host: host owning these new virtual irqs
269 * @count: number of consecutive numbers to allocate
270 * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
271 *
272 * This is a low level function that is used internally by irq_create_mapping()
273 * and that can be used by some irq controllers implementations for things
274 * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
275 */
276extern unsigned int irq_alloc_virt(struct irq_host *host,
277 unsigned int count,
278 unsigned int hint);
279
280/**
281 * irq_free_virt - Free virtual irq numbers
282 * @virq: virtual irq number of the first interrupt to free
283 * @count: number of interrupts to free
284 *
285 * This function is the opposite of irq_alloc_virt. It will not clear reverse
286 * maps, this should be done previously by unmap'ing the interrupt. In fact,
287 * all interrupts covered by the range being freed should have been unmapped
288 * prior to calling this.
289 */
290extern void irq_free_virt(unsigned int virq, unsigned int count);
291
292
293/* -- OF helpers -- */
294
295/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
296 * @controller: Device node of the interrupt controller
297 * @inspec: Interrupt specifier from the device-tree
298 * @intsize: Size of the interrupt specifier from the device-tree
299 *
300 * This function is identical to irq_create_mapping except that it takes
301 * as input informations straight from the device-tree (typically the results
302 * of the of_irq_map_*() functions.
303 */
304extern unsigned int irq_create_of_mapping(struct device_node *controller,
305 u32 *intspec, unsigned int intsize);
306
307
308/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
309 * @device: Device node of the device whose interrupt is to be mapped
310 * @index: Index of the interrupt to map
311 *
312 * This function is a wrapper that chains of_irq_map_one() and
313 * irq_create_of_mapping() to make things easier to callers
314 */
315extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
316
317/* -- End OF helpers -- */
318
319/**
320 * irq_early_init - Init irq remapping subsystem
321 */
322extern void irq_early_init(void);
323
324static __inline__ int irq_canonicalize(int irq)
325{
326 return irq;
327}
328
329
330#else /* CONFIG_PPC_MERGE */
331
332/* This number is used when no interrupt has been assigned */
333#define NO_IRQ (-1)
334#define NO_IRQ_IGNORE (-2)
335
336
337/*
338 * These constants are used for passing information about interrupt
339 * signal polarity and level/edge sensing to the low-level PIC chip
340 * drivers.
341 */
342#define IRQ_SENSE_MASK 0x1
343#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
344#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
345
346#define IRQ_POLARITY_MASK 0x2
347#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
348#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
349
350
351#if defined(CONFIG_40x)
352#include <asm/ibm4xx.h>
353
354#ifndef NR_BOARD_IRQS
355#define NR_BOARD_IRQS 0
356#endif
357
358#ifndef UIC_WIDTH /* Number of interrupts per device */
359#define UIC_WIDTH 32
360#endif
361
362#ifndef NR_UICS /* number of UIC devices */
363#define NR_UICS 1
364#endif
365
366#if defined (CONFIG_403)
367/*
368 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
369 * 32 possible interrupts, a majority of which are not implemented on
370 * all cores. There are six configurable, external interrupt pins and
371 * there are eight internal interrupts for the on-chip serial port
372 * (SPU), DMA controller, and JTAG controller.
373 *
374 */
375
376#define NR_AIC_IRQS 32
377#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
378
379#elif !defined (CONFIG_403)
380
381/*
382 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
383 * possible interrupts as well. There are seven, configurable external
384 * interrupt pins and there are 17 internal interrupts for the on-chip
385 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
386 *
387 */
388
389
390#define NR_UIC_IRQS UIC_WIDTH
391#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
392#endif
393
394#elif defined(CONFIG_44x)
395#include <asm/ibm44x.h>
396
397#define NR_UIC_IRQS 32
398#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
399
400#elif defined(CONFIG_8xx)
401
402/* Now include the board configuration specific associations.
403*/
404#include <asm/mpc8xx.h>
405
406/* The MPC8xx cores have 16 possible interrupts. There are eight
407 * possible level sensitive interrupts assigned and generated internally
408 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
409 * There are eight external interrupts (IRQs) that can be configured
410 * as either level or edge sensitive.
411 *
412 * On some implementations, there is also the possibility of an 8259
413 * through the PCI and PCI-ISA bridges.
414 *
415 * We are "flattening" the interrupt vectors of the cascaded CPM
416 * and 8259 interrupt controllers so that we can uniquely identify
417 * any interrupt source with a single integer.
418 */
419#define NR_SIU_INTS 16
420#define NR_CPM_INTS 32
421#ifndef NR_8259_INTS
422#define NR_8259_INTS 0
423#endif
424
425#define SIU_IRQ_OFFSET 0
426#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
427#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
428
429#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
430
431/* These values must be zero-based and map 1:1 with the SIU configuration.
432 * They are used throughout the 8xx I/O subsystem to generate
433 * interrupt masks, flags, and other control patterns. This is why the
434 * current kernel assumption of the 8259 as the base controller is such
435 * a pain in the butt.
436 */
437#define SIU_IRQ0 (0) /* Highest priority */
438#define SIU_LEVEL0 (1)
439#define SIU_IRQ1 (2)
440#define SIU_LEVEL1 (3)
441#define SIU_IRQ2 (4)
442#define SIU_LEVEL2 (5)
443#define SIU_IRQ3 (6)
444#define SIU_LEVEL3 (7)
445#define SIU_IRQ4 (8)
446#define SIU_LEVEL4 (9)
447#define SIU_IRQ5 (10)
448#define SIU_LEVEL5 (11)
449#define SIU_IRQ6 (12)
450#define SIU_LEVEL6 (13)
451#define SIU_IRQ7 (14)
452#define SIU_LEVEL7 (15)
453
454#define MPC8xx_INT_FEC1 SIU_LEVEL1
455#define MPC8xx_INT_FEC2 SIU_LEVEL3
456
457#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
458#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
459#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
460#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
461#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
462#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
463
464/* The internal interrupts we can configure as we see fit.
465 * My personal preference is CPM at level 2, which puts it above the
466 * MBX PCI/ISA/IDE interrupts.
467 */
468#ifndef PIT_INTERRUPT
469#define PIT_INTERRUPT SIU_LEVEL0
470#endif
471#ifndef CPM_INTERRUPT
472#define CPM_INTERRUPT SIU_LEVEL2
473#endif
474#ifndef PCMCIA_INTERRUPT
475#define PCMCIA_INTERRUPT SIU_LEVEL6
476#endif
477#ifndef DEC_INTERRUPT
478#define DEC_INTERRUPT SIU_LEVEL7
479#endif
480
481/* Some internal interrupt registers use an 8-bit mask for the interrupt
482 * level instead of a number.
483 */
484#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
485
486#else /* CONFIG_40x + CONFIG_8xx */
487/*
488 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
489 * so it is the max of them all
490 */
491#define NR_IRQS 256
492#define __DO_IRQ_CANON 1
493
494#ifndef CONFIG_8260
495
496#define NUM_8259_INTERRUPTS 16
497
498#else /* CONFIG_8260 */
499
500/* The 8260 has an internal interrupt controller with a maximum of
501 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
502 * Don't be confused by the 8260 documentation where they list an
503 * "interrupt number" and "interrupt vector". We are only interested
504 * in the interrupt vector. There are "reserved" holes where the
505 * vector number increases, but the interrupt number in the table does not.
506 * (Document errata updates have fixed this...make sure you have up to
507 * date processor documentation -- Dan).
508 */
509
510#ifndef CPM_IRQ_OFFSET
511#define CPM_IRQ_OFFSET 0
512#endif
513
514#define NR_CPM_INTS 64
515
516#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
517#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
518#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
519#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
520#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
521#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
522#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
523#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
524#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
525#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
526#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
527#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
528#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
529#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
530#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
531#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
532#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
533#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
534#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
535#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
536#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
537#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
538#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
539#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
540#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
541#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
542#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
543#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
544#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
545#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
546#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
547#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
548#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
549#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
550#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
551#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
552#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
553#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
554#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
555#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
556#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
557#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
558#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
559#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
560#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
561#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
562#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
563#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
564#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
565#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
566#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
567
568#endif /* CONFIG_8260 */
569
570#endif /* Whatever way too big #ifdef */
571
572#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
573/* pedantic: these are long because they are used with set_bit --RR */
574extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
575
576/*
577 * Because many systems have two overlapping names spaces for
578 * interrupts (ISA and XICS for example), and the ISA interrupts
579 * have historically not been easy to renumber, we allow ISA
580 * interrupts to take values 0 - 15, and shift up the remaining
581 * interrupts by 0x10.
582 */
583#define NUM_ISA_INTERRUPTS 0x10
584extern int __irq_offset_value;
585
586static inline int irq_offset_up(int irq)
587{
588 return(irq + __irq_offset_value);
589}
590
591static inline int irq_offset_down(int irq)
592{
593 return(irq - __irq_offset_value);
594}
595
596static inline int irq_offset_value(void)
597{
598 return __irq_offset_value;
599}
600
601#ifdef __DO_IRQ_CANON
602extern int ppc_do_canonicalize_irqs;
603#else
604#define ppc_do_canonicalize_irqs 0
605#endif
606
607static __inline__ int irq_canonicalize(int irq)
608{
609 if (ppc_do_canonicalize_irqs && irq == 2)
610 irq = 9;
611 return irq;
612}
613#endif /* CONFIG_PPC_MERGE */
614
615extern int distribute_irqs;
616
617struct irqaction;
618struct pt_regs;
619
620#define __ARCH_HAS_DO_SOFTIRQ
621
622#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
623/*
624 * Per-cpu stacks for handling critical, debug and machine check
625 * level interrupts.
626 */
627extern struct thread_info *critirq_ctx[NR_CPUS];
628extern struct thread_info *dbgirq_ctx[NR_CPUS];
629extern struct thread_info *mcheckirq_ctx[NR_CPUS];
630extern void exc_lvl_ctx_init(void);
631#else
632#define exc_lvl_ctx_init()
633#endif
634
635#ifdef CONFIG_IRQSTACKS
636/*
637 * Per-cpu stacks for handling hard and soft interrupts.
638 */
639extern struct thread_info *hardirq_ctx[NR_CPUS];
640extern struct thread_info *softirq_ctx[NR_CPUS];
641
642extern void irq_ctx_init(void);
643extern void call_do_softirq(struct thread_info *tp);
644extern int call_handle_irq(int irq, void *p1,
645 struct thread_info *tp, void *func);
646#else
647#define irq_ctx_init()
648
649#endif /* CONFIG_IRQSTACKS */
650
651extern void do_IRQ(struct pt_regs *regs);
652
653#endif /* _ASM_IRQ_H */
654#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/irq_regs.h b/arch/powerpc/include/asm/irq_regs.h
new file mode 100644
index 000000000000..ba94b51a0a70
--- /dev/null
+++ b/arch/powerpc/include/asm/irq_regs.h
@@ -0,0 +1,2 @@
1#include <asm-generic/irq_regs.h>
2
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
new file mode 100644
index 000000000000..17ba3a881bfd
--- /dev/null
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -0,0 +1,42 @@
1/*
2 * IRQ flags handling
3 */
4#ifndef _ASM_IRQFLAGS_H
5#define _ASM_IRQFLAGS_H
6
7#ifndef __ASSEMBLY__
8/*
9 * Get definitions for raw_local_save_flags(x), etc.
10 */
11#include <asm/hw_irq.h>
12
13#else
14#ifdef CONFIG_TRACE_IRQFLAGS
15/*
16 * Most of the CPU's IRQ-state tracing is done from assembly code; we
17 * have to call a C function so call a wrapper that saves all the
18 * C-clobbered registers.
19 */
20#define TRACE_ENABLE_INTS bl .trace_hardirqs_on
21#define TRACE_DISABLE_INTS bl .trace_hardirqs_off
22#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \
23 cmpdi en, 0; \
24 bne 95f; \
25 stb en,PACASOFTIRQEN(r13); \
26 bl .trace_hardirqs_off; \
27 b skip; \
2895: bl .trace_hardirqs_on; \
29 li en,1;
30#define TRACE_AND_RESTORE_IRQ(en) \
31 TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \
3296: stb en,PACASOFTIRQEN(r13)
33#else
34#define TRACE_ENABLE_INTS
35#define TRACE_DISABLE_INTS
36#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
37#define TRACE_AND_RESTORE_IRQ(en) \
38 stb en,PACASOFTIRQEN(r13)
39#endif
40#endif
41
42#endif
diff --git a/arch/powerpc/include/asm/iseries/alpaca.h b/arch/powerpc/include/asm/iseries/alpaca.h
new file mode 100644
index 000000000000..c0cce6727a69
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/alpaca.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright © 2008 Stephen Rothwell IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
19#define _ASM_POWERPC_ISERIES_ALPACA_H
20
21/*
22 * This is the part of the paca that the iSeries hypervisor
23 * needs to be statically initialised. Immediately after boot
24 * we switch to the normal Linux paca.
25 */
26struct alpaca {
27 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
28 const void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
29};
30
31#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call.h b/arch/powerpc/include/asm/iseries/hv_call.h
new file mode 100644
index 000000000000..162d653ad51f
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call.h
@@ -0,0 +1,111 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * This file contains the "hypervisor call" interface which is used to
19 * drive the hypervisor from the OS.
20 */
21#ifndef _ASM_POWERPC_ISERIES_HV_CALL_H
22#define _ASM_POWERPC_ISERIES_HV_CALL_H
23
24#include <asm/iseries/hv_call_sc.h>
25#include <asm/iseries/hv_types.h>
26#include <asm/paca.h>
27
28/* Type of yield for HvCallBaseYieldProcessor */
29#define HvCall_YieldTimed 0 /* Yield until specified time (tb) */
30#define HvCall_YieldToActive 1 /* Yield until all active procs have run */
31#define HvCall_YieldToProc 2 /* Yield until the specified processor has run */
32
33/* interrupt masks for setEnabledInterrupts */
34#define HvCall_MaskIPI 0x00000001
35#define HvCall_MaskLpEvent 0x00000002
36#define HvCall_MaskLpProd 0x00000004
37#define HvCall_MaskTimeout 0x00000008
38
39/* Log buffer formats */
40#define HvCall_LogBuffer_ASCII 0
41#define HvCall_LogBuffer_EBCDIC 1
42
43#define HvCallBaseAckDeferredInts HvCallBase + 0
44#define HvCallBaseCpmPowerOff HvCallBase + 1
45#define HvCallBaseGetHwPatch HvCallBase + 2
46#define HvCallBaseReIplSpAttn HvCallBase + 3
47#define HvCallBaseSetASR HvCallBase + 4
48#define HvCallBaseSetASRAndRfi HvCallBase + 5
49#define HvCallBaseSetIMR HvCallBase + 6
50#define HvCallBaseSendIPI HvCallBase + 7
51#define HvCallBaseTerminateMachine HvCallBase + 8
52#define HvCallBaseTerminateMachineSrc HvCallBase + 9
53#define HvCallBaseProcessPlicInterrupts HvCallBase + 10
54#define HvCallBaseIsPrimaryCpmOrMsdIpl HvCallBase + 11
55#define HvCallBaseSetVirtualSIT HvCallBase + 12
56#define HvCallBaseVaryOffThisProcessor HvCallBase + 13
57#define HvCallBaseVaryOffMemoryChunk HvCallBase + 14
58#define HvCallBaseVaryOffInteractivePercentage HvCallBase + 15
59#define HvCallBaseSendLpProd HvCallBase + 16
60#define HvCallBaseSetEnabledInterrupts HvCallBase + 17
61#define HvCallBaseYieldProcessor HvCallBase + 18
62#define HvCallBaseVaryOffSharedProcUnits HvCallBase + 19
63#define HvCallBaseSetVirtualDecr HvCallBase + 20
64#define HvCallBaseClearLogBuffer HvCallBase + 21
65#define HvCallBaseGetLogBufferCodePage HvCallBase + 22
66#define HvCallBaseGetLogBufferFormat HvCallBase + 23
67#define HvCallBaseGetLogBufferLength HvCallBase + 24
68#define HvCallBaseReadLogBuffer HvCallBase + 25
69#define HvCallBaseSetLogBufferFormatAndCodePage HvCallBase + 26
70#define HvCallBaseWriteLogBuffer HvCallBase + 27
71#define HvCallBaseRouter28 HvCallBase + 28
72#define HvCallBaseRouter29 HvCallBase + 29
73#define HvCallBaseRouter30 HvCallBase + 30
74#define HvCallBaseSetDebugBus HvCallBase + 31
75
76#define HvCallCcSetDABR HvCallCc + 7
77
78static inline void HvCall_setVirtualDecr(void)
79{
80 /*
81 * Ignore any error return codes - most likely means that the
82 * target value for the LP has been increased and this vary off
83 * would bring us below the new target.
84 */
85 HvCall0(HvCallBaseSetVirtualDecr);
86}
87
88static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
89{
90 HvCall2(HvCallBaseYieldProcessor, typeOfYield, yieldParm);
91}
92
93static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts)
94{
95 HvCall1(HvCallBaseSetEnabledInterrupts, enabledInterrupts);
96}
97
98static inline void HvCall_setLogBufferFormatAndCodepage(int format,
99 u32 codePage)
100{
101 HvCall2(HvCallBaseSetLogBufferFormatAndCodePage, format, codePage);
102}
103
104extern void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
105
106static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
107{
108 HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
109}
110
111#endif /* _ASM_POWERPC_ISERIES_HV_CALL_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_event.h b/arch/powerpc/include/asm/iseries/hv_call_event.h
new file mode 100644
index 000000000000..cc029d388e11
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_event.h
@@ -0,0 +1,201 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * This file contains the "hypervisor call" interface which is used to
19 * drive the hypervisor from the OS.
20 */
21#ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
22#define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
23
24#include <linux/types.h>
25#include <linux/dma-mapping.h>
26
27#include <asm/iseries/hv_call_sc.h>
28#include <asm/iseries/hv_types.h>
29#include <asm/abs_addr.h>
30
31struct HvLpEvent;
32
33typedef u8 HvLpEvent_Type;
34typedef u8 HvLpEvent_AckInd;
35typedef u8 HvLpEvent_AckType;
36
37typedef u8 HvLpDma_Direction;
38typedef u8 HvLpDma_AddressType;
39
40typedef u64 HvLpEvent_Rc;
41typedef u64 HvLpDma_Rc;
42
43#define HvCallEventAckLpEvent HvCallEvent + 0
44#define HvCallEventCancelLpEvent HvCallEvent + 1
45#define HvCallEventCloseLpEventPath HvCallEvent + 2
46#define HvCallEventDmaBufList HvCallEvent + 3
47#define HvCallEventDmaSingle HvCallEvent + 4
48#define HvCallEventDmaToSp HvCallEvent + 5
49#define HvCallEventGetOverflowLpEvents HvCallEvent + 6
50#define HvCallEventGetSourceLpInstanceId HvCallEvent + 7
51#define HvCallEventGetTargetLpInstanceId HvCallEvent + 8
52#define HvCallEventOpenLpEventPath HvCallEvent + 9
53#define HvCallEventSetLpEventStack HvCallEvent + 10
54#define HvCallEventSignalLpEvent HvCallEvent + 11
55#define HvCallEventSignalLpEventParms HvCallEvent + 12
56#define HvCallEventSetInterLpQueueIndex HvCallEvent + 13
57#define HvCallEventSetLpEventQueueInterruptProc HvCallEvent + 14
58#define HvCallEventRouter15 HvCallEvent + 15
59
60static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex)
61{
62 HvCall1(HvCallEventGetOverflowLpEvents, queueIndex);
63}
64
65static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex)
66{
67 HvCall1(HvCallEventSetInterLpQueueIndex, queueIndex);
68}
69
70static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
71 char *eventStackAddr, u32 eventStackSize)
72{
73 HvCall3(HvCallEventSetLpEventStack, queueIndex,
74 virt_to_abs(eventStackAddr), eventStackSize);
75}
76
77static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
78 u16 lpLogicalProcIndex)
79{
80 HvCall2(HvCallEventSetLpEventQueueInterruptProc, queueIndex,
81 lpLogicalProcIndex);
82}
83
84static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent *event)
85{
86 return HvCall1(HvCallEventSignalLpEvent, virt_to_abs(event));
87}
88
89static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
90 HvLpEvent_Type type, u16 subtype, HvLpEvent_AckInd ackInd,
91 HvLpEvent_AckType ackType, HvLpInstanceId sourceInstanceId,
92 HvLpInstanceId targetInstanceId, u64 correlationToken,
93 u64 eventData1, u64 eventData2, u64 eventData3,
94 u64 eventData4, u64 eventData5)
95{
96 /* Pack the misc bits into a single Dword to pass to PLIC */
97 union {
98 struct {
99 u8 ack_and_target;
100 u8 type;
101 u16 subtype;
102 HvLpInstanceId src_inst;
103 HvLpInstanceId target_inst;
104 } parms;
105 u64 dword;
106 } packed;
107
108 packed.parms.ack_and_target = (ackType << 7) | (ackInd << 6) | targetLp;
109 packed.parms.type = type;
110 packed.parms.subtype = subtype;
111 packed.parms.src_inst = sourceInstanceId;
112 packed.parms.target_inst = targetInstanceId;
113
114 return HvCall7(HvCallEventSignalLpEventParms, packed.dword,
115 correlationToken, eventData1, eventData2,
116 eventData3, eventData4, eventData5);
117}
118
119extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag);
120extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle);
121extern dma_addr_t iseries_hv_map(void *vaddr, size_t size,
122 enum dma_data_direction direction);
123extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
124 enum dma_data_direction direction);
125
126static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
127{
128 return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event));
129}
130
131static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent *event)
132{
133 return HvCall1(HvCallEventCancelLpEvent, virt_to_abs(event));
134}
135
136static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(
137 HvLpIndex targetLp, HvLpEvent_Type type)
138{
139 return HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
140}
141
142static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(
143 HvLpIndex targetLp, HvLpEvent_Type type)
144{
145 return HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
146}
147
148static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp,
149 HvLpEvent_Type type)
150{
151 HvCall2(HvCallEventOpenLpEventPath, targetLp, type);
152}
153
154static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp,
155 HvLpEvent_Type type)
156{
157 HvCall2(HvCallEventCloseLpEventPath, targetLp, type);
158}
159
160static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
161 HvLpIndex remoteLp, HvLpDma_Direction direction,
162 HvLpInstanceId localInstanceId,
163 HvLpInstanceId remoteInstanceId,
164 HvLpDma_AddressType localAddressType,
165 HvLpDma_AddressType remoteAddressType,
166 /* Do these need to be converted to absolute addresses? */
167 u64 localBufList, u64 remoteBufList, u32 transferLength)
168{
169 /* Pack the misc bits into a single Dword to pass to PLIC */
170 union {
171 struct {
172 u8 flags;
173 HvLpIndex remote;
174 u8 type;
175 u8 reserved;
176 HvLpInstanceId local_inst;
177 HvLpInstanceId remote_inst;
178 } parms;
179 u64 dword;
180 } packed;
181
182 packed.parms.flags = (direction << 7) |
183 (localAddressType << 6) | (remoteAddressType << 5);
184 packed.parms.remote = remoteLp;
185 packed.parms.type = type;
186 packed.parms.reserved = 0;
187 packed.parms.local_inst = localInstanceId;
188 packed.parms.remote_inst = remoteInstanceId;
189
190 return HvCall4(HvCallEventDmaBufList, packed.dword, localBufList,
191 remoteBufList, transferLength);
192}
193
194static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
195 u32 length, HvLpDma_Direction dir)
196{
197 return HvCall4(HvCallEventDmaToSp, virt_to_abs(local), remote,
198 length, dir);
199}
200
201#endif /* _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_sc.h b/arch/powerpc/include/asm/iseries/hv_call_sc.h
new file mode 100644
index 000000000000..f5d210959250
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_sc.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_CALL_SC_H
19#define _ASM_POWERPC_ISERIES_HV_CALL_SC_H
20
21#include <linux/types.h>
22
23#define HvCallBase 0x8000000000000000ul
24#define HvCallCc 0x8001000000000000ul
25#define HvCallCfg 0x8002000000000000ul
26#define HvCallEvent 0x8003000000000000ul
27#define HvCallHpt 0x8004000000000000ul
28#define HvCallPci 0x8005000000000000ul
29#define HvCallSm 0x8007000000000000ul
30#define HvCallXm 0x8009000000000000ul
31
32extern u64 HvCall0(u64);
33extern u64 HvCall1(u64, u64);
34extern u64 HvCall2(u64, u64, u64);
35extern u64 HvCall3(u64, u64, u64, u64);
36extern u64 HvCall4(u64, u64, u64, u64, u64);
37extern u64 HvCall5(u64, u64, u64, u64, u64, u64);
38extern u64 HvCall6(u64, u64, u64, u64, u64, u64, u64);
39extern u64 HvCall7(u64, u64, u64, u64, u64, u64, u64, u64);
40
41extern u64 HvCall0Ret16(u64, void *);
42extern u64 HvCall1Ret16(u64, void *, u64);
43extern u64 HvCall2Ret16(u64, void *, u64, u64);
44extern u64 HvCall3Ret16(u64, void *, u64, u64, u64);
45extern u64 HvCall4Ret16(u64, void *, u64, u64, u64, u64);
46extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
47extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
48extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
49
50#endif /* _ASM_POWERPC_ISERIES_HV_CALL_SC_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_xm.h b/arch/powerpc/include/asm/iseries/hv_call_xm.h
new file mode 100644
index 000000000000..392ac3f54df0
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_xm.h
@@ -0,0 +1,61 @@
1/*
2 * This file contains the "hypervisor call" interface which is used to
3 * drive the hypervisor from SLIC.
4 */
5#ifndef _ASM_POWERPC_ISERIES_HV_CALL_XM_H
6#define _ASM_POWERPC_ISERIES_HV_CALL_XM_H
7
8#include <asm/iseries/hv_call_sc.h>
9#include <asm/iseries/hv_types.h>
10
11#define HvCallXmGetTceTableParms HvCallXm + 0
12#define HvCallXmTestBus HvCallXm + 1
13#define HvCallXmConnectBusUnit HvCallXm + 2
14#define HvCallXmLoadTod HvCallXm + 8
15#define HvCallXmTestBusUnit HvCallXm + 9
16#define HvCallXmSetTce HvCallXm + 11
17#define HvCallXmSetTces HvCallXm + 13
18
19static inline void HvCallXm_getTceTableParms(u64 cb)
20{
21 HvCall1(HvCallXmGetTceTableParms, cb);
22}
23
24static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
25{
26 return HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce);
27}
28
29static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset,
30 u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
31{
32 return HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
33 tce1, tce2, tce3, tce4);
34}
35
36static inline u64 HvCallXm_testBus(u16 busNumber)
37{
38 return HvCall1(HvCallXmTestBus, busNumber);
39}
40
41static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber,
42 u8 deviceId)
43{
44 return HvCall2(HvCallXmTestBusUnit, busNumber,
45 (subBusNumber << 8) | deviceId);
46}
47
48static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber,
49 u8 deviceId, u64 interruptToken)
50{
51 return HvCall5(HvCallXmConnectBusUnit, busNumber,
52 (subBusNumber << 8) | deviceId, interruptToken, 0,
53 0 /* HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)) */);
54}
55
56static inline u64 HvCallXm_loadTod(void)
57{
58 return HvCall0(HvCallXmLoadTod);
59}
60
61#endif /* _ASM_POWERPC_ISERIES_HV_CALL_XM_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_config.h b/arch/powerpc/include/asm/iseries/hv_lp_config.h
new file mode 100644
index 000000000000..a006fd1e4a2c
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_lp_config.h
@@ -0,0 +1,128 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
19#define _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
20
21/*
22 * This file contains the interface to the LPAR configuration data
23 * to determine which resources should be allocated to each partition.
24 */
25
26#include <asm/iseries/hv_call_sc.h>
27#include <asm/iseries/hv_types.h>
28
29enum {
30 HvCallCfg_Cur = 0,
31 HvCallCfg_Init = 1,
32 HvCallCfg_Max = 2,
33 HvCallCfg_Min = 3
34};
35
36#define HvCallCfgGetSystemPhysicalProcessors HvCallCfg + 6
37#define HvCallCfgGetPhysicalProcessors HvCallCfg + 7
38#define HvCallCfgGetMsChunks HvCallCfg + 9
39#define HvCallCfgGetSharedPoolIndex HvCallCfg + 20
40#define HvCallCfgGetSharedProcUnits HvCallCfg + 21
41#define HvCallCfgGetNumProcsInSharedPool HvCallCfg + 22
42#define HvCallCfgGetVirtualLanIndexMap HvCallCfg + 30
43#define HvCallCfgGetHostingLpIndex HvCallCfg + 32
44
45extern HvLpIndex HvLpConfig_getLpIndex_outline(void);
46extern HvLpIndex HvLpConfig_getLpIndex(void);
47extern HvLpIndex HvLpConfig_getPrimaryLpIndex(void);
48
49static inline u64 HvLpConfig_getMsChunks(void)
50{
51 return HvCall2(HvCallCfgGetMsChunks, HvLpConfig_getLpIndex(),
52 HvCallCfg_Cur);
53}
54
55static inline u64 HvLpConfig_getSystemPhysicalProcessors(void)
56{
57 return HvCall0(HvCallCfgGetSystemPhysicalProcessors);
58}
59
60static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
61{
62 return (u16)HvCall1(HvCallCfgGetNumProcsInSharedPool, sPI);
63}
64
65static inline u64 HvLpConfig_getPhysicalProcessors(void)
66{
67 return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
68 HvCallCfg_Cur);
69}
70
71static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void)
72{
73 return HvCall1(HvCallCfgGetSharedPoolIndex, HvLpConfig_getLpIndex());
74}
75
76static inline u64 HvLpConfig_getSharedProcUnits(void)
77{
78 return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
79 HvCallCfg_Cur);
80}
81
82static inline u64 HvLpConfig_getMaxSharedProcUnits(void)
83{
84 return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
85 HvCallCfg_Max);
86}
87
88static inline u64 HvLpConfig_getMaxPhysicalProcessors(void)
89{
90 return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
91 HvCallCfg_Max);
92}
93
94static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(
95 HvLpIndex lp)
96{
97 /*
98 * This is a new function in V5R1 so calls to this on older
99 * hypervisors will return -1
100 */
101 u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
102 if (retVal == -1)
103 retVal = 0;
104 return retVal;
105}
106
107static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void)
108{
109 return HvLpConfig_getVirtualLanIndexMapForLp(
110 HvLpConfig_getLpIndex_outline());
111}
112
113static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1,
114 HvLpIndex lp2)
115{
116 HvLpVirtualLanIndexMap virtualLanIndexMap1 =
117 HvLpConfig_getVirtualLanIndexMapForLp(lp1);
118 HvLpVirtualLanIndexMap virtualLanIndexMap2 =
119 HvLpConfig_getVirtualLanIndexMapForLp(lp2);
120 return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0);
121}
122
123static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
124{
125 return HvCall1(HvCallCfgGetHostingLpIndex, lp);
126}
127
128#endif /* _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_event.h b/arch/powerpc/include/asm/iseries/hv_lp_event.h
new file mode 100644
index 000000000000..8f5da7d77202
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_lp_event.h
@@ -0,0 +1,162 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19/* This file contains the class for HV events in the system. */
20
21#ifndef _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
22#define _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
23
24#include <asm/types.h>
25#include <asm/ptrace.h>
26#include <asm/iseries/hv_types.h>
27#include <asm/iseries/hv_call_event.h>
28
29/*
30 * HvLpEvent is the structure for Lp Event messages passed between
31 * partitions through PLIC.
32 */
33
34struct HvLpEvent {
35 u8 flags; /* Event flags x00-x00 */
36 u8 xType; /* Type of message x01-x01 */
37 u16 xSubtype; /* Subtype for event x02-x03 */
38 u8 xSourceLp; /* Source LP x04-x04 */
39 u8 xTargetLp; /* Target LP x05-x05 */
40 u8 xSizeMinus1; /* Size of Derived class - 1 x06-x06 */
41 u8 xRc; /* RC for Ack flows x07-x07 */
42 u16 xSourceInstanceId; /* Source sides instance id x08-x09 */
43 u16 xTargetInstanceId; /* Target sides instance id x0A-x0B */
44 union {
45 u32 xSubtypeData; /* Data usable by the subtype x0C-x0F */
46 u16 xSubtypeDataShort[2]; /* Data as 2 shorts */
47 u8 xSubtypeDataChar[4]; /* Data as 4 chars */
48 } x;
49
50 u64 xCorrelationToken; /* Unique value for source/type x10-x17 */
51};
52
53typedef void (*LpEventHandler)(struct HvLpEvent *);
54
55/* Register a handler for an event type - returns 0 on success */
56extern int HvLpEvent_registerHandler(HvLpEvent_Type eventType,
57 LpEventHandler hdlr);
58
59/*
60 * Unregister a handler for an event type
61 *
62 * This call will sleep until the handler being removed is guaranteed to
63 * be no longer executing on any CPU. Do not call with locks held.
64 *
65 * returns 0 on success
66 * Unregister will fail if there are any paths open for the type
67 */
68extern int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType);
69
70/*
71 * Open an Lp Event Path for an event type
72 * returns 0 on success
73 * openPath will fail if there is no handler registered for the event type.
74 * The lpIndex specified is the partition index for the target partition
75 * (for VirtualIo, VirtualLan and SessionMgr) other types specify zero)
76 */
77extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
78
79/*
80 * Close an Lp Event Path for a type and partition
81 * returns 0 on success
82 */
83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
84
85#define HvLpEvent_Type_Hypervisor 0
86#define HvLpEvent_Type_MachineFac 1
87#define HvLpEvent_Type_SessionMgr 2
88#define HvLpEvent_Type_SpdIo 3
89#define HvLpEvent_Type_VirtualBus 4
90#define HvLpEvent_Type_PciIo 5
91#define HvLpEvent_Type_RioIo 6
92#define HvLpEvent_Type_VirtualLan 7
93#define HvLpEvent_Type_VirtualIo 8
94#define HvLpEvent_Type_NumTypes 9
95
96#define HvLpEvent_Rc_Good 0
97#define HvLpEvent_Rc_BufferNotAvailable 1
98#define HvLpEvent_Rc_Cancelled 2
99#define HvLpEvent_Rc_GenericError 3
100#define HvLpEvent_Rc_InvalidAddress 4
101#define HvLpEvent_Rc_InvalidPartition 5
102#define HvLpEvent_Rc_InvalidSize 6
103#define HvLpEvent_Rc_InvalidSubtype 7
104#define HvLpEvent_Rc_InvalidSubtypeData 8
105#define HvLpEvent_Rc_InvalidType 9
106#define HvLpEvent_Rc_PartitionDead 10
107#define HvLpEvent_Rc_PathClosed 11
108#define HvLpEvent_Rc_SubtypeError 12
109
110#define HvLpEvent_Function_Ack 0
111#define HvLpEvent_Function_Int 1
112
113#define HvLpEvent_AckInd_NoAck 0
114#define HvLpEvent_AckInd_DoAck 1
115
116#define HvLpEvent_AckType_ImmediateAck 0
117#define HvLpEvent_AckType_DeferredAck 1
118
119#define HV_LP_EVENT_INT 0x01
120#define HV_LP_EVENT_DO_ACK 0x02
121#define HV_LP_EVENT_DEFERRED_ACK 0x04
122#define HV_LP_EVENT_VALID 0x80
123
124#define HvLpDma_Direction_LocalToRemote 0
125#define HvLpDma_Direction_RemoteToLocal 1
126
127#define HvLpDma_AddressType_TceIndex 0
128#define HvLpDma_AddressType_RealAddress 1
129
130#define HvLpDma_Rc_Good 0
131#define HvLpDma_Rc_Error 1
132#define HvLpDma_Rc_PartitionDead 2
133#define HvLpDma_Rc_PathClosed 3
134#define HvLpDma_Rc_InvalidAddress 4
135#define HvLpDma_Rc_InvalidLength 5
136
137static inline int hvlpevent_is_valid(struct HvLpEvent *h)
138{
139 return h->flags & HV_LP_EVENT_VALID;
140}
141
142static inline void hvlpevent_invalidate(struct HvLpEvent *h)
143{
144 h->flags &= ~ HV_LP_EVENT_VALID;
145}
146
147static inline int hvlpevent_is_int(struct HvLpEvent *h)
148{
149 return h->flags & HV_LP_EVENT_INT;
150}
151
152static inline int hvlpevent_is_ack(struct HvLpEvent *h)
153{
154 return !hvlpevent_is_int(h);
155}
156
157static inline int hvlpevent_need_ack(struct HvLpEvent *h)
158{
159 return h->flags & HV_LP_EVENT_DO_ACK;
160}
161
162#endif /* _ASM_POWERPC_ISERIES_HV_LP_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_types.h b/arch/powerpc/include/asm/iseries/hv_types.h
new file mode 100644
index 000000000000..c3e6d2a1d1c3
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_types.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_TYPES_H
19#define _ASM_POWERPC_ISERIES_HV_TYPES_H
20
21/*
22 * General typedefs for the hypervisor.
23 */
24
25#include <asm/types.h>
26
27typedef u8 HvLpIndex;
28typedef u16 HvLpInstanceId;
29typedef u64 HvLpTOD;
30typedef u64 HvLpSystemSerialNum;
31typedef u8 HvLpDeviceSerialNum[12];
32typedef u16 HvLpSanHwSet;
33typedef u16 HvLpBus;
34typedef u16 HvLpBoard;
35typedef u16 HvLpCard;
36typedef u8 HvLpDeviceType[4];
37typedef u8 HvLpDeviceModel[3];
38typedef u64 HvIoToken;
39typedef u8 HvLpName[8];
40typedef u32 HvIoId;
41typedef u64 HvRealMemoryIndex;
42typedef u32 HvLpIndexMap; /* Must hold HVMAXARCHITECTEDLPS bits!!! */
43typedef u16 HvLpVrmIndex;
44typedef u32 HvXmGenerationId;
45typedef u8 HvLpBusPool;
46typedef u8 HvLpSharedPoolIndex;
47typedef u16 HvLpSharedProcUnitsX100;
48typedef u8 HvLpVirtualLanIndex;
49typedef u16 HvLpVirtualLanIndexMap; /* Must hold HVMAXARCHITECTEDVIRTUALLANS bits!!! */
50typedef u16 HvBusNumber; /* Hypervisor Bus Number */
51typedef u8 HvSubBusNumber; /* Hypervisor SubBus Number */
52typedef u8 HvAgentId; /* Hypervisor DevFn */
53
54
55#define HVMAXARCHITECTEDLPS 32
56#define HVMAXARCHITECTEDVIRTUALLANS 16
57#define HVMAXARCHITECTEDVIRTUALDISKS 32
58#define HVMAXARCHITECTEDVIRTUALCDROMS 8
59#define HVMAXARCHITECTEDVIRTUALTAPES 8
60#define HVCHUNKSIZE (256 * 1024)
61#define HVPAGESIZE (4 * 1024)
62#define HVLPMINMEGSPRIMARY 256
63#define HVLPMINMEGSSECONDARY 64
64#define HVCHUNKSPERMEG 4
65#define HVPAGESPERMEG 256
66#define HVPAGESPERCHUNK 64
67
68#define HvLpIndexInvalid ((HvLpIndex)0xff)
69
70/*
71 * Enums for the sub-components under PLIC
72 * Used in HvCall and HvPrimaryCall
73 */
74enum {
75 HvCallCompId = 0,
76 HvCallCpuCtlsCompId = 1,
77 HvCallCfgCompId = 2,
78 HvCallEventCompId = 3,
79 HvCallHptCompId = 4,
80 HvCallPciCompId = 5,
81 HvCallSlmCompId = 6,
82 HvCallSmCompId = 7,
83 HvCallSpdCompId = 8,
84 HvCallXmCompId = 9,
85 HvCallRioCompId = 10,
86 HvCallRsvd3CompId = 11,
87 HvCallRsvd2CompId = 12,
88 HvCallRsvd1CompId = 13,
89 HvCallMaxCompId = 14,
90 HvPrimaryCallCompId = 0,
91 HvPrimaryCallCfgCompId = 1,
92 HvPrimaryCallPciCompId = 2,
93 HvPrimaryCallSmCompId = 3,
94 HvPrimaryCallSpdCompId = 4,
95 HvPrimaryCallXmCompId = 5,
96 HvPrimaryCallRioCompId = 6,
97 HvPrimaryCallRsvd7CompId = 7,
98 HvPrimaryCallRsvd6CompId = 8,
99 HvPrimaryCallRsvd5CompId = 9,
100 HvPrimaryCallRsvd4CompId = 10,
101 HvPrimaryCallRsvd3CompId = 11,
102 HvPrimaryCallRsvd2CompId = 12,
103 HvPrimaryCallRsvd1CompId = 13,
104 HvPrimaryCallMaxCompId = HvCallMaxCompId
105};
106
107struct HvLpBufferList {
108 u64 addr;
109 u64 len;
110};
111
112#endif /* _ASM_POWERPC_ISERIES_HV_TYPES_H */
diff --git a/arch/powerpc/include/asm/iseries/iommu.h b/arch/powerpc/include/asm/iseries/iommu.h
new file mode 100644
index 000000000000..c59ee7e4bed1
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/iommu.h
@@ -0,0 +1,41 @@
1#ifndef _ASM_POWERPC_ISERIES_IOMMU_H
2#define _ASM_POWERPC_ISERIES_IOMMU_H
3
4/*
5 * Copyright (C) 2005 Stephen Rothwell, IBM Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the:
19 * Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330,
21 * Boston, MA 02111-1307 USA
22 */
23
24struct pci_dev;
25struct vio_dev;
26struct device_node;
27struct iommu_table;
28
29/* Creates table for an individual device node */
30extern void iommu_devnode_init_iSeries(struct pci_dev *pdev,
31 struct device_node *dn);
32
33/* Get table parameters from HV */
34extern void iommu_table_getparms_iSeries(unsigned long busno,
35 unsigned char slotno, unsigned char virtbus,
36 struct iommu_table *tbl);
37
38extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev);
39extern void iommu_vio_init(void);
40
41#endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/arch/powerpc/include/asm/iseries/it_lp_queue.h b/arch/powerpc/include/asm/iseries/it_lp_queue.h
new file mode 100644
index 000000000000..428278838821
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/it_lp_queue.h
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
19#define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
20
21/*
22 * This control block defines the simple LP queue structure that is
23 * shared between the hypervisor (PLIC) and the OS in order to send
24 * events to an LP.
25 */
26
27#include <asm/types.h>
28#include <asm/ptrace.h>
29
30#define IT_LP_MAX_QUEUES 8
31
32#define IT_LP_NOT_USED 0 /* Queue will not be used by PLIC */
33#define IT_LP_DEDICATED_IO 1 /* Queue dedicated to IO processor specified */
34#define IT_LP_DEDICATED_LP 2 /* Queue dedicated to LP specified */
35#define IT_LP_SHARED 3 /* Queue shared for both IO and LP */
36
37#define IT_LP_EVENT_STACK_SIZE 4096
38#define IT_LP_EVENT_MAX_SIZE 256
39#define IT_LP_EVENT_ALIGN 64
40
41struct hvlpevent_queue {
42/*
43 * The hq_current_event is the pointer to the next event stack entry
44 * that will become valid. The OS must peek at this entry to determine
45 * if it is valid. PLIC will set the valid indicator as the very last
46 * store into that entry.
47 *
48 * When the OS has completed processing of the event then it will mark
49 * the event as invalid so that PLIC knows it can store into that event
50 * location again.
51 *
52 * If the event stack fills and there are overflow events, then PLIC
53 * will set the hq_overflow_pending flag in which case the OS will
54 * have to fetch the additional LP events once they have drained the
55 * event stack.
56 *
57 * The first 16-bytes are known by both the OS and PLIC. The remainder
58 * of the cache line is for use by the OS.
59 */
60 u8 hq_overflow_pending; /* 0x00 Overflow events are pending */
61 u8 hq_status; /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
62 u16 hq_proc_index; /* 0x02 Logical Proc Index for correlation */
63 u8 hq_reserved1[12]; /* 0x04 */
64 char *hq_current_event; /* 0x10 */
65 char *hq_last_event; /* 0x18 */
66 char *hq_event_stack; /* 0x20 */
67 u8 hq_index; /* 0x28 unique sequential index. */
68 u8 hq_reserved2[3]; /* 0x29-2b */
69 spinlock_t hq_lock;
70};
71
72extern struct hvlpevent_queue hvlpevent_queue;
73
74extern int hvlpevent_is_pending(void);
75extern void process_hvlpevents(void);
76extern void setup_hvlpevent_queue(void);
77
78#endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */
diff --git a/arch/powerpc/include/asm/iseries/lpar_map.h b/arch/powerpc/include/asm/iseries/lpar_map.h
new file mode 100644
index 000000000000..5e9f3e128ee2
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/lpar_map.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
19#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
20
21#ifndef __ASSEMBLY__
22
23#include <asm/types.h>
24
25#endif
26
27/*
28 * The iSeries hypervisor will set up mapping for one or more
29 * ESID/VSID pairs (in SLB/segment registers) and will set up
30 * mappings of one or more ranges of pages to VAs.
31 * We will have the hypervisor set up the ESID->VSID mapping
32 * for the four kernel segments (C-F). With shared processors,
33 * the hypervisor will clear all segment registers and reload
34 * these four whenever the processor is switched from one
35 * partition to another.
36 */
37
38/* The Vsid and Esid identified below will be used by the hypervisor
39 * to set up a memory mapping for part of the load area before giving
40 * control to the Linux kernel. The load area is 64 MB, but this must
41 * not attempt to map the whole load area. The Hashed Page Table may
42 * need to be located within the load area (if the total partition size
43 * is 64 MB), but cannot be mapped. Typically, this should specify
44 * to map half (32 MB) of the load area.
45 *
46 * The hypervisor will set up page table entries for the number of
47 * pages specified.
48 *
49 * In 32-bit mode, the hypervisor will load all four of the
50 * segment registers (identified by the low-order four bits of the
51 * Esid field. In 64-bit mode, the hypervisor will load one SLB
52 * entry to map the Esid to the Vsid.
53*/
54
55#define HvEsidsToMap 2
56#define HvRangesToMap 1
57
58/* Hypervisor initially maps 32MB of the load area */
59#define HvPagesToMap 8192
60
61#ifndef __ASSEMBLY__
62struct LparMap {
63 u64 xNumberEsids; // Number of ESID/VSID pairs
64 u64 xNumberRanges; // Number of VA ranges to map
65 u64 xSegmentTableOffs; // Page number within load area of seg table
66 u64 xRsvd[5];
67 struct {
68 u64 xKernelEsid; // Esid used to map kernel load
69 u64 xKernelVsid; // Vsid used to map kernel load
70 } xEsids[HvEsidsToMap];
71 struct {
72 u64 xPages; // Number of pages to be mapped
73 u64 xOffset; // Offset from start of load area
74 u64 xVPN; // Virtual Page Number
75 } xRanges[HvRangesToMap];
76};
77
78extern const struct LparMap xLparMap;
79
80#endif /* __ASSEMBLY__ */
81
82/* the fixed address where the LparMap exists */
83#define LPARMAP_PHYS 0x7000
84
85#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
diff --git a/arch/powerpc/include/asm/iseries/mf.h b/arch/powerpc/include/asm/iseries/mf.h
new file mode 100644
index 000000000000..eb851a9c9e5c
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/mf.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2001 Troy D. Armstrong IBM Corporation
3 * Copyright (C) 2004 Stephen Rothwell IBM Corporation
4 *
5 * This modules exists as an interface between a Linux secondary partition
6 * running on an iSeries and the primary partition's Virtual Service
7 * Processor (VSP) object. The VSP has final authority over powering on/off
8 * all partitions in the iSeries. It also provides miscellaneous low-level
9 * machine facility type operations.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#ifndef _ASM_POWERPC_ISERIES_MF_H
26#define _ASM_POWERPC_ISERIES_MF_H
27
28#include <linux/types.h>
29
30#include <asm/iseries/hv_types.h>
31#include <asm/iseries/hv_call_event.h>
32
33struct rtc_time;
34
35typedef void (*MFCompleteHandler)(void *clientToken, int returnCode);
36
37extern void mf_allocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
38 unsigned size, unsigned amount, MFCompleteHandler hdlr,
39 void *userToken);
40extern void mf_deallocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
41 unsigned count, MFCompleteHandler hdlr, void *userToken);
42
43extern void mf_power_off(void);
44extern void mf_reboot(char *cmd);
45
46extern void mf_display_src(u32 word);
47extern void mf_display_progress(u16 value);
48
49extern void mf_init(void);
50
51#endif /* _ASM_POWERPC_ISERIES_MF_H */
diff --git a/arch/powerpc/include/asm/iseries/vio.h b/arch/powerpc/include/asm/iseries/vio.h
new file mode 100644
index 000000000000..f9ac0d00b951
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/vio.h
@@ -0,0 +1,265 @@
1/* -*- linux-c -*-
2 *
3 * iSeries Virtual I/O Message Path header
4 *
5 * Authors: Dave Boutcher <boutcher@us.ibm.com>
6 * Ryan Arnold <ryanarn@us.ibm.com>
7 * Colin Devilbiss <devilbis@us.ibm.com>
8 *
9 * (C) Copyright 2000 IBM Corporation
10 *
11 * This header file is used by the iSeries virtual I/O device
12 * drivers. It defines the interfaces to the common functions
13 * (implemented in drivers/char/viopath.h) as well as defining
14 * common functions and structures. Currently (at the time I
15 * wrote this comment) the iSeries virtual I/O device drivers
16 * that use this are
17 * drivers/block/viodasd.c
18 * drivers/char/viocons.c
19 * drivers/char/viotape.c
20 * drivers/cdrom/viocd.c
21 *
22 * The iSeries virtual ethernet support (veth.c) uses a whole
23 * different set of functions.
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of the
28 * License, or (at your option) anyu later version.
29 *
30 * This program is distributed in the hope that it will be useful, but
31 * WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
33 * General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software Foundation,
37 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 *
39 */
40#ifndef _ASM_POWERPC_ISERIES_VIO_H
41#define _ASM_POWERPC_ISERIES_VIO_H
42
43#include <asm/iseries/hv_types.h>
44#include <asm/iseries/hv_lp_event.h>
45
46/*
47 * iSeries virtual I/O events use the subtype field in
48 * HvLpEvent to figure out what kind of vio event is coming
49 * in. We use a table to route these, and this defines
50 * the maximum number of distinct subtypes
51 */
52#define VIO_MAX_SUBTYPES 8
53
54#define VIOMAXBLOCKDMA 12
55
56struct open_data {
57 u64 disk_size;
58 u16 max_disk;
59 u16 cylinders;
60 u16 tracks;
61 u16 sectors;
62 u16 bytes_per_sector;
63};
64
65struct rw_data {
66 u64 offset;
67 struct {
68 u32 token;
69 u32 reserved;
70 u64 len;
71 } dma_info[VIOMAXBLOCKDMA];
72};
73
74struct vioblocklpevent {
75 struct HvLpEvent event;
76 u32 reserved;
77 u16 version;
78 u16 sub_result;
79 u16 disk;
80 u16 flags;
81 union {
82 struct open_data open_data;
83 struct rw_data rw_data;
84 u64 changed;
85 } u;
86};
87
88#define vioblockflags_ro 0x0001
89
90enum vioblocksubtype {
91 vioblockopen = 0x0001,
92 vioblockclose = 0x0002,
93 vioblockread = 0x0003,
94 vioblockwrite = 0x0004,
95 vioblockflush = 0x0005,
96 vioblockcheck = 0x0007
97};
98
99struct viocdlpevent {
100 struct HvLpEvent event;
101 u32 reserved;
102 u16 version;
103 u16 sub_result;
104 u16 disk;
105 u16 flags;
106 u32 token;
107 u64 offset; /* On open, max number of disks */
108 u64 len; /* On open, size of the disk */
109 u32 block_size; /* Only set on open */
110 u32 media_size; /* Only set on open */
111};
112
113enum viocdsubtype {
114 viocdopen = 0x0001,
115 viocdclose = 0x0002,
116 viocdread = 0x0003,
117 viocdwrite = 0x0004,
118 viocdlockdoor = 0x0005,
119 viocdgetinfo = 0x0006,
120 viocdcheck = 0x0007
121};
122
123struct viotapelpevent {
124 struct HvLpEvent event;
125 u32 reserved;
126 u16 version;
127 u16 sub_type_result;
128 u16 tape;
129 u16 flags;
130 u32 token;
131 u64 len;
132 union {
133 struct {
134 u32 tape_op;
135 u32 count;
136 } op;
137 struct {
138 u32 type;
139 u32 resid;
140 u32 dsreg;
141 u32 gstat;
142 u32 erreg;
143 u32 file_no;
144 u32 block_no;
145 } get_status;
146 struct {
147 u32 block_no;
148 } get_pos;
149 } u;
150};
151
152enum viotapesubtype {
153 viotapeopen = 0x0001,
154 viotapeclose = 0x0002,
155 viotaperead = 0x0003,
156 viotapewrite = 0x0004,
157 viotapegetinfo = 0x0005,
158 viotapeop = 0x0006,
159 viotapegetpos = 0x0007,
160 viotapesetpos = 0x0008,
161 viotapegetstatus = 0x0009
162};
163
164/*
165 * Each subtype can register a handler to process their events.
166 * The handler must have this interface.
167 */
168typedef void (vio_event_handler_t) (struct HvLpEvent * event);
169
170extern int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
171extern int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
172extern int vio_setHandler(int subtype, vio_event_handler_t * beh);
173extern int vio_clearHandler(int subtype);
174extern int viopath_isactive(HvLpIndex lp);
175extern HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
176extern HvLpInstanceId viopath_targetinst(HvLpIndex lp);
177extern void vio_set_hostlp(void);
178extern void *vio_get_event_buffer(int subtype);
179extern void vio_free_event_buffer(int subtype, void *buffer);
180
181extern struct vio_dev *vio_create_viodasd(u32 unit);
182
183extern HvLpIndex viopath_hostLp;
184extern HvLpIndex viopath_ourLp;
185
186#define VIOCHAR_MAX_DATA 200
187
188#define VIOMAJOR_SUBTYPE_MASK 0xff00
189#define VIOMINOR_SUBTYPE_MASK 0x00ff
190#define VIOMAJOR_SUBTYPE_SHIFT 8
191
192#define VIOVERSION 0x0101
193
194/*
195 * This is the general structure for VIO errors; each module should have
196 * a table of them, and each table should be terminated by an entry of
197 * { 0, 0, NULL }. Then, to find a specific error message, a module
198 * should pass its local table and the return code.
199 */
200struct vio_error_entry {
201 u16 rc;
202 int errno;
203 const char *msg;
204};
205extern const struct vio_error_entry *vio_lookup_rc(
206 const struct vio_error_entry *local_table, u16 rc);
207
208enum viosubtypes {
209 viomajorsubtype_monitor = 0x0100,
210 viomajorsubtype_blockio = 0x0200,
211 viomajorsubtype_chario = 0x0300,
212 viomajorsubtype_config = 0x0400,
213 viomajorsubtype_cdio = 0x0500,
214 viomajorsubtype_tape = 0x0600,
215 viomajorsubtype_scsi = 0x0700
216};
217
218enum vioconfigsubtype {
219 vioconfigget = 0x0001,
220};
221
222enum viorc {
223 viorc_good = 0x0000,
224 viorc_noConnection = 0x0001,
225 viorc_noReceiver = 0x0002,
226 viorc_noBufferAvailable = 0x0003,
227 viorc_invalidMessageType = 0x0004,
228 viorc_invalidRange = 0x0201,
229 viorc_invalidToken = 0x0202,
230 viorc_DMAError = 0x0203,
231 viorc_useError = 0x0204,
232 viorc_releaseError = 0x0205,
233 viorc_invalidDisk = 0x0206,
234 viorc_openRejected = 0x0301
235};
236
237/*
238 * The structure of the events that flow between us and OS/400 for chario
239 * events. You can't mess with this unless the OS/400 side changes too.
240 */
241struct viocharlpevent {
242 struct HvLpEvent event;
243 u32 reserved;
244 u16 version;
245 u16 subtype_result_code;
246 u8 virtual_device;
247 u8 len;
248 u8 data[VIOCHAR_MAX_DATA];
249};
250
251#define VIOCHAR_WINDOW 10
252
253enum viocharsubtype {
254 viocharopen = 0x0001,
255 viocharclose = 0x0002,
256 viochardata = 0x0003,
257 viocharack = 0x0004,
258 viocharconfig = 0x0005
259};
260
261enum viochar_rc {
262 viochar_rc_ebusy = 1
263};
264
265#endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/arch/powerpc/include/asm/kdebug.h b/arch/powerpc/include/asm/kdebug.h
new file mode 100644
index 000000000000..ae6d206728af
--- /dev/null
+++ b/arch/powerpc/include/asm/kdebug.h
@@ -0,0 +1,15 @@
1#ifndef _ASM_POWERPC_KDEBUG_H
2#define _ASM_POWERPC_KDEBUG_H
3#ifdef __KERNEL__
4
5/* Grossly misnamed. */
6enum die_val {
7 DIE_OOPS = 1,
8 DIE_IABR_MATCH,
9 DIE_DABR_MATCH,
10 DIE_BPT,
11 DIE_SSTEP,
12};
13
14#endif /* __KERNEL__ */
15#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
new file mode 100644
index 000000000000..f6c93c716898
--- /dev/null
+++ b/arch/powerpc/include/asm/kdump.h
@@ -0,0 +1,35 @@
1#ifndef _PPC64_KDUMP_H
2#define _PPC64_KDUMP_H
3
4/* Kdump kernel runs at 32 MB, change at your peril. */
5#define KDUMP_KERNELBASE 0x2000000
6
7/* How many bytes to reserve at zero for kdump. The reserve limit should
8 * be greater or equal to the trampoline's end address.
9 * Reserve to the end of the FWNMI area, see head_64.S */
10#define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
11
12#ifdef CONFIG_CRASH_DUMP
13
14#define KDUMP_TRAMPOLINE_START 0x0100
15#define KDUMP_TRAMPOLINE_END 0x3000
16
17#define KDUMP_MIN_TCE_ENTRIES 2048
18
19#endif /* CONFIG_CRASH_DUMP */
20
21#ifndef __ASSEMBLY__
22#ifdef CONFIG_CRASH_DUMP
23
24extern void reserve_kdump_trampoline(void);
25extern void setup_kdump_trampoline(void);
26
27#else /* !CONFIG_CRASH_DUMP */
28
29static inline void reserve_kdump_trampoline(void) { ; }
30static inline void setup_kdump_trampoline(void) { ; }
31
32#endif /* CONFIG_CRASH_DUMP */
33#endif /* __ASSEMBLY__ */
34
35#endif /* __PPC64_KDUMP_H */
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
new file mode 100644
index 000000000000..acdcdc66f1b6
--- /dev/null
+++ b/arch/powerpc/include/asm/kexec.h
@@ -0,0 +1,160 @@
1#ifndef _ASM_POWERPC_KEXEC_H
2#define _ASM_POWERPC_KEXEC_H
3#ifdef __KERNEL__
4
5/*
6 * Maximum page that is mapped directly into kernel memory.
7 * XXX: Since we copy virt we can use any page we allocate
8 */
9#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
10
11/*
12 * Maximum address we can reach in physical address mode.
13 * XXX: I want to allow initrd in highmem. Otherwise set to rmo on LPAR.
14 */
15#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
16
17/* Maximum address we can use for the control code buffer */
18#ifdef __powerpc64__
19#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
20#else
21/* TASK_SIZE, probably left over from use_mm ?? */
22#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
23#endif
24
25#define KEXEC_CONTROL_CODE_SIZE 4096
26
27/* The native architecture */
28#ifdef __powerpc64__
29#define KEXEC_ARCH KEXEC_ARCH_PPC64
30#else
31#define KEXEC_ARCH KEXEC_ARCH_PPC
32#endif
33
34#ifndef __ASSEMBLY__
35#include <linux/cpumask.h>
36
37typedef void (*crash_shutdown_t)(void);
38
39#ifdef CONFIG_KEXEC
40
41#ifdef __powerpc64__
42/*
43 * This function is responsible for capturing register states if coming
44 * via panic or invoking dump using sysrq-trigger.
45 */
46static inline void crash_setup_regs(struct pt_regs *newregs,
47 struct pt_regs *oldregs)
48{
49 if (oldregs)
50 memcpy(newregs, oldregs, sizeof(*newregs));
51 else {
52 /* FIXME Merge this with xmon_save_regs ?? */
53 unsigned long tmp1, tmp2;
54 __asm__ __volatile__ (
55 "std 0,0(%2)\n"
56 "std 1,8(%2)\n"
57 "std 2,16(%2)\n"
58 "std 3,24(%2)\n"
59 "std 4,32(%2)\n"
60 "std 5,40(%2)\n"
61 "std 6,48(%2)\n"
62 "std 7,56(%2)\n"
63 "std 8,64(%2)\n"
64 "std 9,72(%2)\n"
65 "std 10,80(%2)\n"
66 "std 11,88(%2)\n"
67 "std 12,96(%2)\n"
68 "std 13,104(%2)\n"
69 "std 14,112(%2)\n"
70 "std 15,120(%2)\n"
71 "std 16,128(%2)\n"
72 "std 17,136(%2)\n"
73 "std 18,144(%2)\n"
74 "std 19,152(%2)\n"
75 "std 20,160(%2)\n"
76 "std 21,168(%2)\n"
77 "std 22,176(%2)\n"
78 "std 23,184(%2)\n"
79 "std 24,192(%2)\n"
80 "std 25,200(%2)\n"
81 "std 26,208(%2)\n"
82 "std 27,216(%2)\n"
83 "std 28,224(%2)\n"
84 "std 29,232(%2)\n"
85 "std 30,240(%2)\n"
86 "std 31,248(%2)\n"
87 "mfmsr %0\n"
88 "std %0, 264(%2)\n"
89 "mfctr %0\n"
90 "std %0, 280(%2)\n"
91 "mflr %0\n"
92 "std %0, 288(%2)\n"
93 "bl 1f\n"
94 "1: mflr %1\n"
95 "std %1, 256(%2)\n"
96 "mtlr %0\n"
97 "mfxer %0\n"
98 "std %0, 296(%2)\n"
99 : "=&r" (tmp1), "=&r" (tmp2)
100 : "b" (newregs)
101 : "memory");
102 }
103}
104#else
105/*
106 * Provide a dummy definition to avoid build failures. Will remain
107 * empty till crash dump support is enabled.
108 */
109static inline void crash_setup_regs(struct pt_regs *newregs,
110 struct pt_regs *oldregs) { }
111#endif /* !__powerpc64 __ */
112
113extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
114 master to copy new code to 0 */
115extern int crashing_cpu;
116extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
117extern cpumask_t cpus_in_sr;
118static inline int kexec_sr_activated(int cpu)
119{
120 return cpu_isset(cpu,cpus_in_sr);
121}
122
123struct kimage;
124struct pt_regs;
125extern void default_machine_kexec(struct kimage *image);
126extern int default_machine_kexec_prepare(struct kimage *image);
127extern void default_machine_crash_shutdown(struct pt_regs *regs);
128extern int crash_shutdown_register(crash_shutdown_t handler);
129extern int crash_shutdown_unregister(crash_shutdown_t handler);
130
131extern void machine_kexec_simple(struct kimage *image);
132extern void crash_kexec_secondary(struct pt_regs *regs);
133extern int overlaps_crashkernel(unsigned long start, unsigned long size);
134extern void reserve_crashkernel(void);
135
136#else /* !CONFIG_KEXEC */
137static inline int kexec_sr_activated(int cpu) { return 0; }
138static inline void crash_kexec_secondary(struct pt_regs *regs) { }
139
140static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
141{
142 return 0;
143}
144
145static inline void reserve_crashkernel(void) { ; }
146
147static inline int crash_shutdown_register(crash_shutdown_t handler)
148{
149 return 0;
150}
151
152static inline int crash_shutdown_unregister(crash_shutdown_t handler)
153{
154 return 0;
155}
156
157#endif /* CONFIG_KEXEC */
158#endif /* ! __ASSEMBLY__ */
159#endif /* __KERNEL__ */
160#endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/arch/powerpc/include/asm/keylargo.h b/arch/powerpc/include/asm/keylargo.h
new file mode 100644
index 000000000000..d8520ef121f9
--- /dev/null
+++ b/arch/powerpc/include/asm/keylargo.h
@@ -0,0 +1,261 @@
1#ifndef _ASM_POWERPC_KEYLARGO_H
2#define _ASM_POWERPC_KEYLARGO_H
3#ifdef __KERNEL__
4/*
5 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
6 *
7 */
8
9/* "Pangea" chipset has keylargo device-id 0x25 while core99
10 * has device-id 0x22. The rev. of the pangea one is 0, so we
11 * fake an artificial rev. in keylargo_rev by oring 0x100
12 */
13#define KL_PANGEA_REV 0x100
14
15/* offset from base for feature control registers */
16#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
17#define KEYLARGO_FCR0 0x38
18#define KEYLARGO_FCR1 0x3c
19#define KEYLARGO_FCR2 0x40
20#define KEYLARGO_FCR3 0x44
21#define KEYLARGO_FCR4 0x48
22#define KEYLARGO_FCR5 0x4c /* Pangea only */
23
24/* K2 aditional FCRs */
25#define K2_FCR6 0x34
26#define K2_FCR7 0x30
27#define K2_FCR8 0x2c
28#define K2_FCR9 0x28
29#define K2_FCR10 0x24
30
31/* GPIO registers */
32#define KEYLARGO_GPIO_LEVELS0 0x50
33#define KEYLARGO_GPIO_LEVELS1 0x54
34#define KEYLARGO_GPIO_EXTINT_0 0x58
35#define KEYLARGO_GPIO_EXTINT_CNT 18
36#define KEYLARGO_GPIO_0 0x6A
37#define KEYLARGO_GPIO_CNT 17
38#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
39#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
40#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
41#define KEYLARGO_GPIO_INPUT_DATA 0x02
42
43/* K2 does only extint GPIOs and does 51 of them */
44#define K2_GPIO_EXTINT_0 0x58
45#define K2_GPIO_EXTINT_CNT 51
46
47/* Specific GPIO regs */
48
49#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
50#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
51
52#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
53
54/* Hrm... this one is only to be used on Pismo. It seeem to also
55 * control the timebase enable on other machines. Still to be
56 * experimented... --BenH.
57 */
58#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
59#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
60
61#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
62
63#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
64#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
65#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
66
67#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
68#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
69#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
70#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
71
72#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
73#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
74
75#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
76
77#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
78#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
79#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
80#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
81#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
82
83/*
84 * Bits in feature control register. Those bits different for K2 are
85 * listed separately
86 */
87#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
88#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
89#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
90#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
91#define KL_MBCR_MB0_DEV_MASK 0x00007800
92#define KL_MBCR_MB0_DEV_POWER 0x00000400
93#define KL_MBCR_MB0_DEV_RESET 0x00000200
94#define KL_MBCR_MB0_ENABLE 0x00000100
95#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
96#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
97#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
98#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
99#define KL_MBCR_MB1_DEV_MASK 0x78000000
100#define KL_MBCR_MB1_DEV_POWER 0x04000000
101#define KL_MBCR_MB1_DEV_RESET 0x02000000
102#define KL_MBCR_MB1_ENABLE 0x01000000
103
104#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
105#define KL0_SCC_A_INTF_ENABLE 0x00000002
106#define KL0_SCC_SLOWPCLK 0x00000004
107#define KL0_SCC_RESET 0x00000008
108#define KL0_SCCA_ENABLE 0x00000010
109#define KL0_SCCB_ENABLE 0x00000020
110#define KL0_SCC_CELL_ENABLE 0x00000040
111#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
112#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
113#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
114#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
115#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
116#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
117#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
118#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
119#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
120#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
121#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
122#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
123#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
124#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
125#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
126#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
127#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
128#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
129#define KL0_USB0_PAD_SUSPEND0 0x00040000
130#define KL0_USB0_PAD_SUSPEND1 0x00080000
131#define KL0_USB0_CELL_ENABLE 0x00100000
132#define KL0_USB1_PAD_SUSPEND0 0x00400000
133#define KL0_USB1_PAD_SUSPEND1 0x00800000
134#define KL0_USB1_CELL_ENABLE 0x01000000
135#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
136
137#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
138 KL0_SCC_SLOWPCLK | \
139 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
140
141#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
142#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
143#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
144#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
145#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
147#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
148#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
149#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
150#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
151#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
152#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
153#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
154#define KL1_I2S0_CELL_ENABLE 0x00000400
155#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
156#define KL1_I2S0_ENABLE 0x00002000
157#define KL1_I2S1_CELL_ENABLE 0x00020000
158#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
159#define KL1_I2S1_ENABLE 0x00100000
160#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
161#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
162#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
163#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
164#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
165#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
166
167#define KL2_IOBUS_ENABLE 0x00000002
168#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
169#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
170#define KL2_MPIC_ENABLE 0x00020000
171#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
172#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
173#define KL2_MEM_IS_BIG 0x04000000
174#define KL2_CARDSEL_16 0x08000000
175
176#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
177#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
178#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
179#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
180#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
181#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
182#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
183#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
184#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
186#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
187#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
188#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
189#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
190#define KL3_CLK49_ENABLE 0x00000200
191#define KL3_CLK45_ENABLE 0x00000400
192#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
193#define KL3_TIMER_CLK18_ENABLE 0x00001000
194#define KL3_I2S1_CLK18_ENABLE 0x00002000
195#define KL3_I2S0_CLK18_ENABLE 0x00004000
196#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
197#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
198#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
199#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
200
201/* Intrepid USB bus 2, port 0,1 */
202#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
206#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
207#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
208#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
209
210/* Port 0,1 : bus 0, port 2,3 : bus 1 */
211#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
212#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
213#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
215#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
216#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
217#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
218
219/* Pangea and Intrepid only */
220#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
221#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
222#define KL5_PWM_CLK32_EN 0x00000004
223#define KL5_CLK3_68_EN 0x00000010
224#define KL5_CLK32_EN 0x00000020
225
226
227/* K2 definitions */
228#define K2_FCR0_USB0_SWRESET 0x00200000
229#define K2_FCR0_USB1_SWRESET 0x02000000
230#define K2_FCR0_RING_PME_DISABLE 0x08000000
231
232#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
233#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
234#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
235#define K2_FCR1_I2S0_RESET 0x00000800
236#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
237#define K2_FCR1_I2S0_ENABLE 0x00002000
238#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
239#define K2_FCR1_FW_CLK_ENABLE 0x00008000
240#define K2_FCR1_FW_RESET_N 0x00010000
241#define K2_FCR1_I2S1_CELL_ENABLE 0x00020000
242#define K2_FCR1_I2S1_CLK_ENABLE_BIT 0x00080000
243#define K2_FCR1_I2S1_ENABLE 0x00100000
244#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
245#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
246#define K2_FCR1_GMAC_RESET_N 0x01000000
247#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
248#define K2_FCR1_SATA_POWER_DOWN 0x04000000
249#define K2_FCR1_SATA_RESET_N 0x08000000
250#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
251#define K2_FCR1_UATA_RESET_N 0x40000000
252#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
253
254/* Shasta definitions */
255#define SH_FCR1_I2S2_CELL_ENABLE 0x00000010
256#define SH_FCR1_I2S2_CLK_ENABLE_BIT 0x00000040
257#define SH_FCR1_I2S2_ENABLE 0x00000080
258#define SH_FCR3_I2S2_CLK18_ENABLE 0x00008000
259
260#endif /* __KERNEL__ */
261#endif /* _ASM_POWERPC_KEYLARGO_H */
diff --git a/arch/powerpc/include/asm/kgdb.h b/arch/powerpc/include/asm/kgdb.h
new file mode 100644
index 000000000000..edd217006d27
--- /dev/null
+++ b/arch/powerpc/include/asm/kgdb.h
@@ -0,0 +1,63 @@
1/*
2 * The PowerPC (32/64) specific defines / externs for KGDB. Based on
3 * the previous 32bit and 64bit specific files, which had the following
4 * copyrights:
5 *
6 * PPC64 Mods (C) 2005 Frank Rowand (frowand@mvista.com)
7 * PPC Mods (C) 2004 Tom Rini (trini@mvista.com)
8 * PPC Mods (C) 2003 John Whitney (john.whitney@timesys.com)
9 * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
10 *
11 *
12 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
13 * Author: Tom Rini <trini@kernel.crashing.org>
14 *
15 * 2006 (c) MontaVista Software, Inc. This file is licensed under
16 * the terms of the GNU General Public License version 2. This program
17 * is licensed "as is" without any warranty of any kind, whether express
18 * or implied.
19 */
20#ifdef __KERNEL__
21#ifndef __POWERPC_KGDB_H__
22#define __POWERPC_KGDB_H__
23
24#ifndef __ASSEMBLY__
25
26#define BREAK_INSTR_SIZE 4
27#define BUFMAX ((NUMREGBYTES * 2) + 512)
28#define OUTBUFMAX ((NUMREGBYTES * 2) + 512)
29static inline void arch_kgdb_breakpoint(void)
30{
31 asm(".long 0x7d821008"); /* twge r2, r2 */
32}
33#define CACHE_FLUSH_IS_SAFE 1
34
35/* The number bytes of registers we have to save depends on a few
36 * things. For 64bit we default to not including vector registers and
37 * vector state registers. */
38#ifdef CONFIG_PPC64
39/*
40 * 64 bit (8 byte) registers:
41 * 32 gpr, 32 fpr, nip, msr, link, ctr
42 * 32 bit (4 byte) registers:
43 * ccr, xer, fpscr
44 */
45#define NUMREGBYTES ((68 * 8) + (3 * 4))
46#define NUMCRITREGBYTES 184
47#else /* CONFIG_PPC32 */
48/* On non-E500 family PPC32 we determine the size by picking the last
49 * register we need, but on E500 we skip sections so we list what we
50 * need to store, and add it up. */
51#ifndef CONFIG_E500
52#define MAXREG (PT_FPSCR+1)
53#else
54/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
55#define MAXREG ((32*2)+6+2+1)
56#endif
57#define NUMREGBYTES (MAXREG * sizeof(int))
58/* CR/LR, R1, R2, R13-R31 inclusive. */
59#define NUMCRITREGBYTES (23 * sizeof(int))
60#endif /* 32/64 */
61#endif /* !(__ASSEMBLY__) */
62#endif /* !__POWERPC_KGDB_H__ */
63#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/kmap_types.h b/arch/powerpc/include/asm/kmap_types.h
new file mode 100644
index 000000000000..b6bac6f61c16
--- /dev/null
+++ b/arch/powerpc/include/asm/kmap_types.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_POWERPC_KMAP_TYPES_H
2#define _ASM_POWERPC_KMAP_TYPES_H
3
4#ifdef __KERNEL__
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13enum km_type {
14 KM_BOUNCE_READ,
15 KM_SKB_SUNRPC_DATA,
16 KM_SKB_DATA_SOFTIRQ,
17 KM_USER0,
18 KM_USER1,
19 KM_BIO_SRC_IRQ,
20 KM_BIO_DST_IRQ,
21 KM_PTE0,
22 KM_PTE1,
23 KM_IRQ0,
24 KM_IRQ1,
25 KM_SOFTIRQ0,
26 KM_SOFTIRQ1,
27 KM_PPC_SYNC_PAGE,
28 KM_PPC_SYNC_ICACHE,
29 KM_TYPE_NR
30};
31
32#endif /* __KERNEL__ */
33#endif /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h
new file mode 100644
index 000000000000..d0e7701fa1f6
--- /dev/null
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -0,0 +1,118 @@
1#ifndef _ASM_POWERPC_KPROBES_H
2#define _ASM_POWERPC_KPROBES_H
3#ifdef __KERNEL__
4/*
5 * Kernel Probes (KProbes)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 * Copyright (C) IBM Corporation, 2002, 2004
22 *
23 * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
24 * Probes initial implementation ( includes suggestions from
25 * Rusty Russell).
26 * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli
27 * <ananth@in.ibm.com>
28 */
29#include <linux/types.h>
30#include <linux/ptrace.h>
31#include <linux/percpu.h>
32
33#define __ARCH_WANT_KPROBES_INSN_SLOT
34
35struct pt_regs;
36struct kprobe;
37
38typedef unsigned int kprobe_opcode_t;
39#define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */
40#define MAX_INSN_SIZE 1
41
42#define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
43#define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
44#define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
45#define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
46
47#ifdef CONFIG_PPC64
48/*
49 * 64bit powerpc uses function descriptors.
50 * Handle cases where:
51 * - User passes a <.symbol> or <module:.symbol>
52 * - User passes a <symbol> or <module:symbol>
53 * - User passes a non-existant symbol, kallsyms_lookup_name
54 * returns 0. Don't deref the NULL pointer in that case
55 */
56#define kprobe_lookup_name(name, addr) \
57{ \
58 addr = (kprobe_opcode_t *)kallsyms_lookup_name(name); \
59 if (addr) { \
60 char *colon; \
61 if ((colon = strchr(name, ':')) != NULL) { \
62 colon++; \
63 if (*colon != '\0' && *colon != '.') \
64 addr = *(kprobe_opcode_t **)addr; \
65 } else if (name[0] != '.') \
66 addr = *(kprobe_opcode_t **)addr; \
67 } else { \
68 char dot_name[KSYM_NAME_LEN]; \
69 dot_name[0] = '.'; \
70 dot_name[1] = '\0'; \
71 strncat(dot_name, name, KSYM_NAME_LEN - 2); \
72 addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
73 } \
74}
75
76#define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \
77 IS_TWI(instr) || IS_TDI(instr))
78#else
79/* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */
80#define is_trap(instr) (IS_TW(instr) || IS_TWI(instr))
81#endif
82
83#define flush_insn_slot(p) do { } while (0)
84#define kretprobe_blacklist_size 0
85
86void kretprobe_trampoline(void);
87extern void arch_remove_kprobe(struct kprobe *p);
88
89/* Architecture specific copy of original instruction */
90struct arch_specific_insn {
91 /* copy of original instruction */
92 kprobe_opcode_t *insn;
93 /*
94 * Set in kprobes code, initially to 0. If the instruction can be
95 * eumulated, this is set to 1, if not, to -1.
96 */
97 int boostable;
98};
99
100struct prev_kprobe {
101 struct kprobe *kp;
102 unsigned long status;
103 unsigned long saved_msr;
104};
105
106/* per-cpu kprobe control block */
107struct kprobe_ctlblk {
108 unsigned long kprobe_status;
109 unsigned long kprobe_saved_msr;
110 struct pt_regs jprobe_saved_regs;
111 struct prev_kprobe prev_kprobe;
112};
113
114extern int kprobe_exceptions_notify(struct notifier_block *self,
115 unsigned long val, void *data);
116extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
117#endif /* __KERNEL__ */
118#endif /* _ASM_POWERPC_KPROBES_H */
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
new file mode 100644
index 000000000000..f993e4198d5c
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm.h
@@ -0,0 +1,55 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __LINUX_KVM_POWERPC_H
21#define __LINUX_KVM_POWERPC_H
22
23#include <asm/types.h>
24
25struct kvm_regs {
26 __u64 pc;
27 __u64 cr;
28 __u64 ctr;
29 __u64 lr;
30 __u64 xer;
31 __u64 msr;
32 __u64 srr0;
33 __u64 srr1;
34 __u64 pid;
35
36 __u64 sprg0;
37 __u64 sprg1;
38 __u64 sprg2;
39 __u64 sprg3;
40 __u64 sprg4;
41 __u64 sprg5;
42 __u64 sprg6;
43 __u64 sprg7;
44
45 __u64 gpr[32];
46};
47
48struct kvm_sregs {
49};
50
51struct kvm_fpu {
52 __u64 fpr[32];
53};
54
55#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..2197764796d9
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -0,0 +1,55 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_ASM_H__
21#define __POWERPC_KVM_ASM_H__
22
23/* IVPR must be 64KiB-aligned. */
24#define VCPU_SIZE_ORDER 4
25#define VCPU_SIZE_LOG (VCPU_SIZE_ORDER + 12)
26#define VCPU_TLB_PGSZ PPC44x_TLB_64K
27#define VCPU_SIZE_BYTES (1<<VCPU_SIZE_LOG)
28
29#define BOOKE_INTERRUPT_CRITICAL 0
30#define BOOKE_INTERRUPT_MACHINE_CHECK 1
31#define BOOKE_INTERRUPT_DATA_STORAGE 2
32#define BOOKE_INTERRUPT_INST_STORAGE 3
33#define BOOKE_INTERRUPT_EXTERNAL 4
34#define BOOKE_INTERRUPT_ALIGNMENT 5
35#define BOOKE_INTERRUPT_PROGRAM 6
36#define BOOKE_INTERRUPT_FP_UNAVAIL 7
37#define BOOKE_INTERRUPT_SYSCALL 8
38#define BOOKE_INTERRUPT_AP_UNAVAIL 9
39#define BOOKE_INTERRUPT_DECREMENTER 10
40#define BOOKE_INTERRUPT_FIT 11
41#define BOOKE_INTERRUPT_WATCHDOG 12
42#define BOOKE_INTERRUPT_DTLB_MISS 13
43#define BOOKE_INTERRUPT_ITLB_MISS 14
44#define BOOKE_INTERRUPT_DEBUG 15
45#define BOOKE_MAX_INTERRUPT 15
46
47#define RESUME_FLAG_NV (1<<0) /* Reload guest nonvolatile state? */
48#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
49
50#define RESUME_GUEST 0
51#define RESUME_GUEST_NV RESUME_FLAG_NV
52#define RESUME_HOST RESUME_FLAG_HOST
53#define RESUME_HOST_NV (RESUME_FLAG_HOST|RESUME_FLAG_NV)
54
55#endif /* __POWERPC_KVM_ASM_H__ */
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
new file mode 100644
index 000000000000..2655e2a4831e
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -0,0 +1,155 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_HOST_H__
21#define __POWERPC_KVM_HOST_H__
22
23#include <linux/mutex.h>
24#include <linux/timer.h>
25#include <linux/types.h>
26#include <linux/kvm_types.h>
27#include <asm/kvm_asm.h>
28
29#define KVM_MAX_VCPUS 1
30#define KVM_MEMORY_SLOTS 32
31/* memory slots that does not exposed to userspace */
32#define KVM_PRIVATE_MEM_SLOTS 4
33
34#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
35
36/* We don't currently support large pages. */
37#define KVM_PAGES_PER_HPAGE (1<<31)
38
39struct kvm;
40struct kvm_run;
41struct kvm_vcpu;
42
43struct kvm_vm_stat {
44 u32 remote_tlb_flush;
45};
46
47struct kvm_vcpu_stat {
48 u32 sum_exits;
49 u32 mmio_exits;
50 u32 dcr_exits;
51 u32 signal_exits;
52 u32 light_exits;
53 /* Account for special types of light exits: */
54 u32 itlb_real_miss_exits;
55 u32 itlb_virt_miss_exits;
56 u32 dtlb_real_miss_exits;
57 u32 dtlb_virt_miss_exits;
58 u32 syscall_exits;
59 u32 isi_exits;
60 u32 dsi_exits;
61 u32 emulated_inst_exits;
62 u32 dec_exits;
63 u32 ext_intr_exits;
64 u32 halt_wakeup;
65};
66
67struct tlbe {
68 u32 tid; /* Only the low 8 bits are used. */
69 u32 word0;
70 u32 word1;
71 u32 word2;
72};
73
74struct kvm_arch {
75};
76
77struct kvm_vcpu_arch {
78 /* Unmodified copy of the guest's TLB. */
79 struct tlbe guest_tlb[PPC44x_TLB_SIZE];
80 /* TLB that's actually used when the guest is running. */
81 struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
82 /* Pages which are referenced in the shadow TLB. */
83 struct page *shadow_pages[PPC44x_TLB_SIZE];
84 /* Copy of the host's TLB. */
85 struct tlbe host_tlb[PPC44x_TLB_SIZE];
86
87 u32 host_stack;
88 u32 host_pid;
89
90 u64 fpr[32];
91 u32 gpr[32];
92
93 u32 pc;
94 u32 cr;
95 u32 ctr;
96 u32 lr;
97 u32 xer;
98
99 u32 msr;
100 u32 mmucr;
101 u32 sprg0;
102 u32 sprg1;
103 u32 sprg2;
104 u32 sprg3;
105 u32 sprg4;
106 u32 sprg5;
107 u32 sprg6;
108 u32 sprg7;
109 u32 srr0;
110 u32 srr1;
111 u32 csrr0;
112 u32 csrr1;
113 u32 dsrr0;
114 u32 dsrr1;
115 u32 dear;
116 u32 esr;
117 u32 dec;
118 u32 decar;
119 u32 tbl;
120 u32 tbu;
121 u32 tcr;
122 u32 tsr;
123 u32 ivor[16];
124 u32 ivpr;
125 u32 pir;
126 u32 pid;
127 u32 pvr;
128 u32 ccr0;
129 u32 ccr1;
130 u32 dbcr0;
131 u32 dbcr1;
132
133 u32 last_inst;
134 u32 fault_dear;
135 u32 fault_esr;
136 gpa_t paddr_accessed;
137
138 u8 io_gpr; /* GPR used as IO source/target */
139 u8 mmio_is_bigendian;
140 u8 dcr_needed;
141 u8 dcr_is_write;
142
143 u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
144
145 struct timer_list dec_timer;
146 unsigned long pending_exceptions;
147};
148
149struct kvm_guest_debug {
150 int enabled;
151 unsigned long bp[4];
152 int singlestep;
153};
154
155#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
new file mode 100644
index 000000000000..2d48f6a63d0b
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -0,0 +1,37 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_PARA_H__
21#define __POWERPC_KVM_PARA_H__
22
23#ifdef __KERNEL__
24
25static inline int kvm_para_available(void)
26{
27 return 0;
28}
29
30static inline unsigned int kvm_arch_para_features(void)
31{
32 return 0;
33}
34
35#endif /* __KERNEL__ */
36
37#endif /* __POWERPC_KVM_PARA_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
new file mode 100644
index 000000000000..a8b068792260
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -0,0 +1,95 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_PPC_H__
21#define __POWERPC_KVM_PPC_H__
22
23/* This file exists just so we can dereference kvm_vcpu, avoiding nested header
24 * dependencies. */
25
26#include <linux/mutex.h>
27#include <linux/timer.h>
28#include <linux/types.h>
29#include <linux/kvm_types.h>
30#include <linux/kvm_host.h>
31
32struct kvm_tlb {
33 struct tlbe guest_tlb[PPC44x_TLB_SIZE];
34 struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
35};
36
37enum emulation_result {
38 EMULATE_DONE, /* no further processing */
39 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
40 EMULATE_DO_DCR, /* kvm_run filled with DCR request */
41 EMULATE_FAIL, /* can't emulate this instruction */
42};
43
44extern const unsigned char exception_priority[];
45extern const unsigned char priority_exception[];
46
47extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
48extern char kvmppc_handlers_start[];
49extern unsigned long kvmppc_handler_len;
50
51extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
52extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
53 unsigned int rt, unsigned int bytes,
54 int is_bigendian);
55extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
56 u32 val, unsigned int bytes, int is_bigendian);
57
58extern int kvmppc_emulate_instruction(struct kvm_run *run,
59 struct kvm_vcpu *vcpu);
60extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
61
62extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn,
63 u64 asid, u32 flags);
64extern void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
65 gva_t eend, u32 asid);
66extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode);
67
68extern void kvmppc_check_and_deliver_interrupts(struct kvm_vcpu *vcpu);
69
70static inline void kvmppc_queue_exception(struct kvm_vcpu *vcpu, int exception)
71{
72 unsigned int priority = exception_priority[exception];
73 set_bit(priority, &vcpu->arch.pending_exceptions);
74}
75
76static inline void kvmppc_clear_exception(struct kvm_vcpu *vcpu, int exception)
77{
78 unsigned int priority = exception_priority[exception];
79 clear_bit(priority, &vcpu->arch.pending_exceptions);
80}
81
82/* Helper function for "full" MSR writes. No need to call this if only EE is
83 * changing. */
84static inline void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
85{
86 if ((new_msr & MSR_PR) != (vcpu->arch.msr & MSR_PR))
87 kvmppc_mmu_priv_switch(vcpu, new_msr & MSR_PR);
88
89 vcpu->arch.msr = new_msr;
90
91 if (vcpu->arch.msr & MSR_WE)
92 kvm_vcpu_block(vcpu);
93}
94
95#endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/libata-portmap.h b/arch/powerpc/include/asm/libata-portmap.h
new file mode 100644
index 000000000000..4d8518049f4d
--- /dev/null
+++ b/arch/powerpc/include/asm/libata-portmap.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_POWERPC_LIBATA_PORTMAP_H
2#define __ASM_POWERPC_LIBATA_PORTMAP_H
3
4#define ATA_PRIMARY_CMD 0x1F0
5#define ATA_PRIMARY_CTL 0x3F6
6#define ATA_PRIMARY_IRQ(dev) pci_get_legacy_ide_irq(dev, 0)
7
8#define ATA_SECONDARY_CMD 0x170
9#define ATA_SECONDARY_CTL 0x376
10#define ATA_SECONDARY_IRQ(dev) pci_get_legacy_ide_irq(dev, 1)
11
12#endif
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 000000000000..e1c4ac1cc4ba
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_POWERPC_LINKAGE_H
2#define _ASM_POWERPC_LINKAGE_H
3
4/* Nothing to see here... */
5
6#endif /* _ASM_POWERPC_LINKAGE_H */
diff --git a/arch/powerpc/include/asm/lmb.h b/arch/powerpc/include/asm/lmb.h
new file mode 100644
index 000000000000..6f5fdf0a19ae
--- /dev/null
+++ b/arch/powerpc/include/asm/lmb.h
@@ -0,0 +1,15 @@
1#ifndef _ASM_POWERPC_LMB_H
2#define _ASM_POWERPC_LMB_H
3
4#include <asm/udbg.h>
5
6#define LMB_DBG(fmt...) udbg_printf(fmt)
7
8#ifdef CONFIG_PPC32
9extern phys_addr_t lowmem_end_addr;
10#define LMB_REAL_LIMIT lowmem_end_addr
11#else
12#define LMB_REAL_LIMIT 0
13#endif
14
15#endif /* _ASM_POWERPC_LMB_H */
diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h
new file mode 100644
index 000000000000..612d83276653
--- /dev/null
+++ b/arch/powerpc/include/asm/local.h
@@ -0,0 +1,200 @@
1#ifndef _ARCH_POWERPC_LOCAL_H
2#define _ARCH_POWERPC_LOCAL_H
3
4#include <linux/percpu.h>
5#include <asm/atomic.h>
6
7typedef struct
8{
9 atomic_long_t a;
10} local_t;
11
12#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
13
14#define local_read(l) atomic_long_read(&(l)->a)
15#define local_set(l,i) atomic_long_set(&(l)->a, (i))
16
17#define local_add(i,l) atomic_long_add((i),(&(l)->a))
18#define local_sub(i,l) atomic_long_sub((i),(&(l)->a))
19#define local_inc(l) atomic_long_inc(&(l)->a)
20#define local_dec(l) atomic_long_dec(&(l)->a)
21
22static __inline__ long local_add_return(long a, local_t *l)
23{
24 long t;
25
26 __asm__ __volatile__(
27"1:" PPC_LLARX "%0,0,%2 # local_add_return\n\
28 add %0,%1,%0\n"
29 PPC405_ERR77(0,%2)
30 PPC_STLCX "%0,0,%2 \n\
31 bne- 1b"
32 : "=&r" (t)
33 : "r" (a), "r" (&(l->a.counter))
34 : "cc", "memory");
35
36 return t;
37}
38
39#define local_add_negative(a, l) (local_add_return((a), (l)) < 0)
40
41static __inline__ long local_sub_return(long a, local_t *l)
42{
43 long t;
44
45 __asm__ __volatile__(
46"1:" PPC_LLARX "%0,0,%2 # local_sub_return\n\
47 subf %0,%1,%0\n"
48 PPC405_ERR77(0,%2)
49 PPC_STLCX "%0,0,%2 \n\
50 bne- 1b"
51 : "=&r" (t)
52 : "r" (a), "r" (&(l->a.counter))
53 : "cc", "memory");
54
55 return t;
56}
57
58static __inline__ long local_inc_return(local_t *l)
59{
60 long t;
61
62 __asm__ __volatile__(
63"1:" PPC_LLARX "%0,0,%1 # local_inc_return\n\
64 addic %0,%0,1\n"
65 PPC405_ERR77(0,%1)
66 PPC_STLCX "%0,0,%1 \n\
67 bne- 1b"
68 : "=&r" (t)
69 : "r" (&(l->a.counter))
70 : "cc", "memory");
71
72 return t;
73}
74
75/*
76 * local_inc_and_test - increment and test
77 * @l: pointer of type local_t
78 *
79 * Atomically increments @l by 1
80 * and returns true if the result is zero, or false for all
81 * other cases.
82 */
83#define local_inc_and_test(l) (local_inc_return(l) == 0)
84
85static __inline__ long local_dec_return(local_t *l)
86{
87 long t;
88
89 __asm__ __volatile__(
90"1:" PPC_LLARX "%0,0,%1 # local_dec_return\n\
91 addic %0,%0,-1\n"
92 PPC405_ERR77(0,%1)
93 PPC_STLCX "%0,0,%1\n\
94 bne- 1b"
95 : "=&r" (t)
96 : "r" (&(l->a.counter))
97 : "cc", "memory");
98
99 return t;
100}
101
102#define local_cmpxchg(l, o, n) \
103 (cmpxchg_local(&((l)->a.counter), (o), (n)))
104#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
105
106/**
107 * local_add_unless - add unless the number is a given value
108 * @l: pointer of type local_t
109 * @a: the amount to add to v...
110 * @u: ...unless v is equal to u.
111 *
112 * Atomically adds @a to @l, so long as it was not @u.
113 * Returns non-zero if @l was not @u, and zero otherwise.
114 */
115static __inline__ int local_add_unless(local_t *l, long a, long u)
116{
117 long t;
118
119 __asm__ __volatile__ (
120"1:" PPC_LLARX "%0,0,%1 # local_add_unless\n\
121 cmpw 0,%0,%3 \n\
122 beq- 2f \n\
123 add %0,%2,%0 \n"
124 PPC405_ERR77(0,%2)
125 PPC_STLCX "%0,0,%1 \n\
126 bne- 1b \n"
127" subf %0,%2,%0 \n\
1282:"
129 : "=&r" (t)
130 : "r" (&(l->a.counter)), "r" (a), "r" (u)
131 : "cc", "memory");
132
133 return t != u;
134}
135
136#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
137
138#define local_sub_and_test(a, l) (local_sub_return((a), (l)) == 0)
139#define local_dec_and_test(l) (local_dec_return((l)) == 0)
140
141/*
142 * Atomically test *l and decrement if it is greater than 0.
143 * The function returns the old value of *l minus 1.
144 */
145static __inline__ long local_dec_if_positive(local_t *l)
146{
147 long t;
148
149 __asm__ __volatile__(
150"1:" PPC_LLARX "%0,0,%1 # local_dec_if_positive\n\
151 cmpwi %0,1\n\
152 addi %0,%0,-1\n\
153 blt- 2f\n"
154 PPC405_ERR77(0,%1)
155 PPC_STLCX "%0,0,%1\n\
156 bne- 1b"
157 "\n\
1582:" : "=&b" (t)
159 : "r" (&(l->a.counter))
160 : "cc", "memory");
161
162 return t;
163}
164
165/* Use these for per-cpu local_t variables: on some archs they are
166 * much more efficient than these naive implementations. Note they take
167 * a variable, not an address.
168 */
169
170#define __local_inc(l) ((l)->a.counter++)
171#define __local_dec(l) ((l)->a.counter++)
172#define __local_add(i,l) ((l)->a.counter+=(i))
173#define __local_sub(i,l) ((l)->a.counter-=(i))
174
175/* Need to disable preemption for the cpu local counters otherwise we could
176 still access a variable of a previous CPU in a non atomic way. */
177#define cpu_local_wrap_v(l) \
178 ({ local_t res__; \
179 preempt_disable(); \
180 res__ = (l); \
181 preempt_enable(); \
182 res__; })
183#define cpu_local_wrap(l) \
184 ({ preempt_disable(); \
185 l; \
186 preempt_enable(); }) \
187
188#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
189#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
190#define cpu_local_inc(l) cpu_local_wrap(local_inc(&__get_cpu_var(l)))
191#define cpu_local_dec(l) cpu_local_wrap(local_dec(&__get_cpu_var(l)))
192#define cpu_local_add(i, l) cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
193#define cpu_local_sub(i, l) cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
194
195#define __cpu_local_inc(l) cpu_local_inc(l)
196#define __cpu_local_dec(l) cpu_local_dec(l)
197#define __cpu_local_add(i, l) cpu_local_add((i), (l))
198#define __cpu_local_sub(i, l) cpu_local_sub((i), (l))
199
200#endif /* _ARCH_POWERPC_LOCAL_H */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
new file mode 100644
index 000000000000..2fe268b10333
--- /dev/null
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -0,0 +1,159 @@
1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
21#ifdef __KERNEL__
22
23//=============================================================================
24//
25// This control block contains the data that is shared between the
26// hypervisor (PLIC) and the OS.
27//
28//
29//----------------------------------------------------------------------------
30#include <linux/cache.h>
31#include <asm/types.h>
32#include <asm/mmu.h>
33
34/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
35 * alignment is sufficient to prevent this */
36struct lppaca {
37//=============================================================================
38// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
39// NOTE: The xDynXyz fields are fields that will be dynamically changed by
40// PLIC when preparing to bring a processor online or when dispatching a
41// virtual processor!
42//=============================================================================
43 u32 desc; // Eye catcher 0xD397D781 x00-x03
44 u16 size; // Size of this struct x04-x05
45 u16 reserved1; // Reserved x06-x07
46 u16 reserved2:14; // Reserved x08-x09
47 u8 shared_proc:1; // Shared processor indicator ...
48 u8 secondary_thread:1; // Secondary thread indicator ...
49 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
50 u8 secondary_thread_count; // Secondary thread count x0B-x0B
51 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
52 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
53 u32 decr_val; // Value for Decr programming x10-x13
54 u32 pmc_val; // Value for PMC regs x14-x17
55 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
56 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
57 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
58 u32 dsei_data; // DSEI data x24-x27
59 u64 sprg3; // SPRG3 value x28-x2F
60 u8 reserved3[80]; // Reserved x30-x7F
61
62//=============================================================================
63// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
64//=============================================================================
65 // This Dword contains a byte for each type of interrupt that can occur.
66 // The IPI is a count while the others are just a binary 1 or 0.
67 union {
68 u64 any_int;
69 struct {
70 u16 reserved; // Reserved - cleared by #mpasmbl
71 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
72 u8 ipi_cnt; // IPI Count
73 u8 decr_int; // DECR interrupt occurred
74 u8 pdc_int; // PDC interrupt occurred
75 u8 quantum_int; // Interrupt quantum reached
76 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
77 } fields;
78 } int_dword;
79
80 // Whenever any fields in this Dword are set then PLIC will defer the
81 // processing of external interrupts. Note that PLIC will store the
82 // XIRR directly into the xXirrValue field so that another XIRR will
83 // not be presented until this one clears. The layout of the low
84 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
85 // entire Dword is zero or not. A non-zero value in the low order
86 // 2-bytes will result in SLIC being granted the highest thread
87 // priority upon return. A 0 will return to SLIC as medium priority.
88 u64 plic_defer_ints_area; // Entire Dword
89
90 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
91 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
92 u64 saved_srr0; // Saved SRR0 x10-x17
93 u64 saved_srr1; // Saved SRR1 x18-x1F
94
95 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
96 u64 saved_gpr3; // Saved GPR3 x20-x27
97 u64 saved_gpr4; // Saved GPR4 x28-x2F
98 u64 saved_gpr5; // Saved GPR5 x30-x37
99
100 u8 reserved4; // Reserved x38-x38
101 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
102 u8 fpregs_in_use; // FP regs in use x3A-x3A
103 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
104 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
105 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
106 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
107 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
108 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
109 u64 end_of_quantum; // TB at end of quantum x60-x67
110 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
111 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
112 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
113 u16 slb_count; // # of SLBs to maintain x7C-x7D
114 u8 idle; // Indicate OS is idle x7E
115 u8 vmxregs_in_use; // VMX registers in use x7F
116
117
118//=============================================================================
119// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
120//=============================================================================
121 // This is the yield_count. An "odd" value (low bit on) means that
122 // the processor is yielded (either because of an OS yield or a PLIC
123 // preempt). An even value implies that the processor is currently
124 // executing.
125 // NOTE: This value will ALWAYS be zero for dedicated processors and
126 // will NEVER be zero for shared processors (ie, initialized to a 1).
127 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
128 u32 reserved6;
129 volatile u64 cmo_faults; // CMO page fault count x08-x0F
130 volatile u64 cmo_fault_time; // CMO page fault time x10-x17
131 u8 reserved7[104]; // Reserved x18-x7F
132
133//=============================================================================
134// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
135//=============================================================================
136 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
137} __attribute__((__aligned__(0x400)));
138
139extern struct lppaca lppaca[];
140
141/*
142 * SLB shadow buffer structure as defined in the PAPR. The save_area
143 * contains adjacent ESID and VSID pairs for each shadowed SLB. The
144 * ESID is stored in the lower 64bits, then the VSID.
145 */
146struct slb_shadow {
147 u32 persistent; // Number of persistent SLBs x00-x03
148 u32 buffer_length; // Total shadow buffer length x04-x07
149 u64 reserved; // Alignment x08-x0f
150 struct {
151 u64 esid;
152 u64 vsid;
153 } save_area[SLB_NUM_BOLTED]; // x10-x40
154} ____cacheline_aligned;
155
156extern struct slb_shadow slb_shadow[];
157
158#endif /* __KERNEL__ */
159#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
new file mode 100644
index 000000000000..81713acf7529
--- /dev/null
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -0,0 +1,348 @@
1/*
2 * PS3 hvcall interface.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 * Copyright 2003, 2004 (c) MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#if !defined(_ASM_POWERPC_LV1CALL_H)
23#define _ASM_POWERPC_LV1CALL_H
24
25#if !defined(__ASSEMBLY__)
26
27#include <linux/types.h>
28
29/* lv1 call declaration macros */
30
31#define LV1_1_IN_ARG_DECL u64 in_1
32#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
33#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
34#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
35#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
36#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
37#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
38#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
39#define LV1_1_OUT_ARG_DECL u64 *out_1
40#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
41#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
42#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
43#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
44#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
45#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
46
47#define LV1_0_IN_0_OUT_ARG_DECL void
48#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
49#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
50#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
51#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
52#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
53#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
54#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
55
56#define LV1_0_IN_1_OUT_ARG_DECL LV1_1_OUT_ARG_DECL
57#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
58#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
59#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
60#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
61#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
62#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
63#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
64#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
65
66#define LV1_0_IN_2_OUT_ARG_DECL LV1_2_OUT_ARG_DECL
67#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
68#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
69#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
70#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
71#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
72#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
73#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
74
75#define LV1_0_IN_3_OUT_ARG_DECL LV1_3_OUT_ARG_DECL
76#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
77#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
78#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
79#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
80#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
81#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
82#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
83
84#define LV1_0_IN_4_OUT_ARG_DECL LV1_4_OUT_ARG_DECL
85#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
86#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
87#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
88#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
89#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
90#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
91#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
92
93#define LV1_0_IN_5_OUT_ARG_DECL LV1_5_OUT_ARG_DECL
94#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
95#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
96#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
97#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
98#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
99#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
100#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
101
102#define LV1_0_IN_6_OUT_ARG_DECL LV1_6_OUT_ARG_DECL
103#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
104#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
105#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
106#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
107#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
108#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
109#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
110
111#define LV1_0_IN_7_OUT_ARG_DECL LV1_7_OUT_ARG_DECL
112#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
113#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
114#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
115#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
116#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
117#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
118#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
119
120#define LV1_1_IN_ARGS in_1
121#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
122#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
123#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
124#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
125#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
126#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
127#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
128
129#define LV1_1_OUT_ARGS out_1
130#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
131#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
132#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
133#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
134#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
135#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
136
137#define LV1_0_IN_0_OUT_ARGS
138#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
139#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
140#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
141#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
142#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
143#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
144#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
145
146#define LV1_0_IN_1_OUT_ARGS LV1_1_OUT_ARGS
147#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
148#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
149#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
150#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
151#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
152#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
153#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
154#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
155
156#define LV1_0_IN_2_OUT_ARGS LV1_2_OUT_ARGS
157#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
158#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
159#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
160#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
161#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
162#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
163#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
164
165#define LV1_0_IN_3_OUT_ARGS LV1_3_OUT_ARGS
166#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
167#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
168#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
169#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
170#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
171#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
172#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
173
174#define LV1_0_IN_4_OUT_ARGS LV1_4_OUT_ARGS
175#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
176#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
177#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
178#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
179#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
180#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
181#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
182
183#define LV1_0_IN_5_OUT_ARGS LV1_5_OUT_ARGS
184#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
185#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
186#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
187#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
188#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
189#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
190#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
191
192#define LV1_0_IN_6_OUT_ARGS LV1_6_OUT_ARGS
193#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
194#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
195#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
196#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
197#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
198#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
199#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
200
201#define LV1_0_IN_7_OUT_ARGS LV1_7_OUT_ARGS
202#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
203#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
204#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
205#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
206#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
207#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
208#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
209
210/*
211 * This LV1_CALL() macro is for use by callers. It expands into an
212 * inline call wrapper and an underscored HV call declaration. The
213 * wrapper can be used to instrument the lv1 call interface. The
214 * file lv1call.S defines its own LV1_CALL() macro to expand into
215 * the actual underscored call definition.
216 */
217
218#if !defined(LV1_CALL)
219#define LV1_CALL(name, in, out, num) \
220 extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL); \
221 static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
222 {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
223#endif
224
225#endif /* !defined(__ASSEMBLY__) */
226
227/* lv1 call table */
228
229LV1_CALL(allocate_memory, 4, 2, 0 )
230LV1_CALL(write_htab_entry, 4, 0, 1 )
231LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
232LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
233LV1_CALL(get_virtual_address_space_id_of_ppe, 1, 1, 4 )
234LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
235LV1_CALL(select_virtual_address_space, 1, 0, 7 )
236LV1_CALL(pause, 1, 0, 9 )
237LV1_CALL(destruct_virtual_address_space, 1, 0, 10 )
238LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 )
239LV1_CALL(connect_irq_plug_ext, 5, 0, 12 )
240LV1_CALL(release_memory, 1, 0, 13 )
241LV1_CALL(put_iopte, 5, 0, 15 )
242LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 )
243LV1_CALL(construct_event_receive_port, 0, 1, 18 )
244LV1_CALL(destruct_event_receive_port, 1, 0, 19 )
245LV1_CALL(send_event_locally, 1, 0, 24 )
246LV1_CALL(end_of_interrupt, 1, 0, 27 )
247LV1_CALL(connect_irq_plug, 2, 0, 28 )
248LV1_CALL(disconnect_irq_plug, 1, 0, 29 )
249LV1_CALL(end_of_interrupt_ext, 3, 0, 30 )
250LV1_CALL(did_update_interrupt_mask, 2, 0, 31 )
251LV1_CALL(shutdown_logical_partition, 1, 0, 44 )
252LV1_CALL(destruct_logical_spe, 1, 0, 54 )
253LV1_CALL(construct_logical_spe, 7, 6, 57 )
254LV1_CALL(set_spe_interrupt_mask, 3, 0, 61 )
255LV1_CALL(set_spe_transition_notifier, 3, 0, 64 )
256LV1_CALL(disable_logical_spe, 2, 0, 65 )
257LV1_CALL(clear_spe_interrupt_status, 4, 0, 66 )
258LV1_CALL(get_spe_interrupt_status, 2, 1, 67 )
259LV1_CALL(get_logical_ppe_id, 0, 1, 69 )
260LV1_CALL(set_interrupt_mask, 5, 0, 73 )
261LV1_CALL(get_logical_partition_id, 0, 1, 74 )
262LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
263LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
264LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
265LV1_CALL(create_repository_node, 6, 0, 90 )
266LV1_CALL(get_repository_node_value, 5, 2, 91 )
267LV1_CALL(modify_repository_node_value, 6, 0, 92 )
268LV1_CALL(remove_repository_node, 4, 0, 93 )
269LV1_CALL(read_htab_entries, 2, 5, 95 )
270LV1_CALL(set_dabr, 2, 0, 96 )
271LV1_CALL(get_total_execution_time, 2, 1, 103 )
272LV1_CALL(allocate_io_segment, 3, 1, 116 )
273LV1_CALL(release_io_segment, 2, 0, 117 )
274LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
275LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
276LV1_CALL(map_htab, 1, 1, 122 )
277LV1_CALL(unmap_htab, 1, 0, 123 )
278LV1_CALL(get_version_info, 0, 1, 127 )
279LV1_CALL(insert_htab_entry, 6, 3, 158 )
280LV1_CALL(read_virtual_uart, 3, 1, 162 )
281LV1_CALL(write_virtual_uart, 3, 1, 163 )
282LV1_CALL(set_virtual_uart_param, 3, 0, 164 )
283LV1_CALL(get_virtual_uart_param, 2, 1, 165 )
284LV1_CALL(configure_virtual_uart_irq, 1, 1, 166 )
285LV1_CALL(open_device, 3, 0, 170 )
286LV1_CALL(close_device, 2, 0, 171 )
287LV1_CALL(map_device_mmio_region, 5, 1, 172 )
288LV1_CALL(unmap_device_mmio_region, 3, 0, 173 )
289LV1_CALL(allocate_device_dma_region, 5, 1, 174 )
290LV1_CALL(free_device_dma_region, 3, 0, 175 )
291LV1_CALL(map_device_dma_region, 6, 0, 176 )
292LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
293LV1_CALL(net_add_multicast_address, 4, 0, 185 )
294LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
295LV1_CALL(net_start_tx_dma, 4, 0, 187 )
296LV1_CALL(net_stop_tx_dma, 3, 0, 188 )
297LV1_CALL(net_start_rx_dma, 4, 0, 189 )
298LV1_CALL(net_stop_rx_dma, 3, 0, 190 )
299LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
300LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
301LV1_CALL(net_control, 6, 2, 194 )
302LV1_CALL(connect_interrupt_event_receive_port, 4, 0, 197 )
303LV1_CALL(disconnect_interrupt_event_receive_port, 4, 0, 198 )
304LV1_CALL(get_spe_all_interrupt_statuses, 1, 1, 199 )
305LV1_CALL(deconfigure_virtual_uart_irq, 0, 0, 202 )
306LV1_CALL(enable_logical_spe, 2, 0, 207 )
307LV1_CALL(gpu_open, 1, 0, 210 )
308LV1_CALL(gpu_close, 0, 0, 211 )
309LV1_CALL(gpu_device_map, 1, 2, 212 )
310LV1_CALL(gpu_device_unmap, 1, 0, 213 )
311LV1_CALL(gpu_memory_allocate, 5, 2, 214 )
312LV1_CALL(gpu_memory_free, 1, 0, 216 )
313LV1_CALL(gpu_context_allocate, 2, 5, 217 )
314LV1_CALL(gpu_context_free, 1, 0, 218 )
315LV1_CALL(gpu_context_iomap, 5, 0, 221 )
316LV1_CALL(gpu_context_attribute, 6, 0, 225 )
317LV1_CALL(gpu_context_intr, 1, 1, 227 )
318LV1_CALL(gpu_attribute, 5, 0, 228 )
319LV1_CALL(get_rtc, 0, 2, 232 )
320LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 )
321LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 )
322LV1_CALL(stop_ppe_periodic_tracer, 1, 1, 242 )
323LV1_CALL(storage_read, 6, 1, 245 )
324LV1_CALL(storage_write, 6, 1, 246 )
325LV1_CALL(storage_send_device_command, 6, 1, 248 )
326LV1_CALL(storage_get_async_status, 1, 2, 249 )
327LV1_CALL(storage_check_async_status, 2, 1, 254 )
328LV1_CALL(panic, 1, 0, 255 )
329LV1_CALL(construct_lpm, 6, 3, 140 )
330LV1_CALL(destruct_lpm, 1, 0, 141 )
331LV1_CALL(start_lpm, 1, 0, 142 )
332LV1_CALL(stop_lpm, 1, 1, 143 )
333LV1_CALL(copy_lpm_trace_buffer, 3, 1, 144 )
334LV1_CALL(add_lpm_event_bookmark, 5, 0, 145 )
335LV1_CALL(delete_lpm_event_bookmark, 3, 0, 146 )
336LV1_CALL(set_lpm_interrupt_mask, 3, 1, 147 )
337LV1_CALL(get_lpm_interrupt_status, 1, 1, 148 )
338LV1_CALL(set_lpm_general_control, 5, 2, 149 )
339LV1_CALL(set_lpm_interval, 3, 1, 150 )
340LV1_CALL(set_lpm_trigger_control, 3, 1, 151 )
341LV1_CALL(set_lpm_counter_control, 4, 1, 152 )
342LV1_CALL(set_lpm_group_control, 3, 1, 153 )
343LV1_CALL(set_lpm_debug_bus_control, 3, 1, 154 )
344LV1_CALL(set_lpm_counter, 5, 2, 155 )
345LV1_CALL(set_lpm_signal, 7, 0, 156 )
346LV1_CALL(set_lpm_spr_trigger, 2, 0, 157 )
347
348#endif
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
new file mode 100644
index 000000000000..893aafd87fde
--- /dev/null
+++ b/arch/powerpc/include/asm/machdep.h
@@ -0,0 +1,365 @@
1#ifndef _ASM_POWERPC_MACHDEP_H
2#define _ASM_POWERPC_MACHDEP_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/seq_file.h>
13#include <linux/init.h>
14#include <linux/dma-mapping.h>
15
16#include <asm/setup.h>
17
18/* We export this macro for external modules like Alsa to know if
19 * ppc_md.feature_call is implemented or not
20 */
21#define CONFIG_PPC_HAS_FEATURE_CALLS
22
23struct pt_regs;
24struct pci_bus;
25struct device_node;
26struct iommu_table;
27struct rtc_time;
28struct file;
29struct pci_controller;
30#ifdef CONFIG_KEXEC
31struct kimage;
32#endif
33
34#ifdef CONFIG_SMP
35struct smp_ops_t {
36 void (*message_pass)(int target, int msg);
37 int (*probe)(void);
38 void (*kick_cpu)(int nr);
39 void (*setup_cpu)(int nr);
40 void (*take_timebase)(void);
41 void (*give_timebase)(void);
42 int (*cpu_enable)(unsigned int nr);
43 int (*cpu_disable)(void);
44 void (*cpu_die)(unsigned int nr);
45 int (*cpu_bootable)(unsigned int nr);
46};
47#endif
48
49struct machdep_calls {
50 char *name;
51#ifdef CONFIG_PPC64
52 void (*hpte_invalidate)(unsigned long slot,
53 unsigned long va,
54 int psize, int ssize,
55 int local);
56 long (*hpte_updatepp)(unsigned long slot,
57 unsigned long newpp,
58 unsigned long va,
59 int psize, int ssize,
60 int local);
61 void (*hpte_updateboltedpp)(unsigned long newpp,
62 unsigned long ea,
63 int psize, int ssize);
64 long (*hpte_insert)(unsigned long hpte_group,
65 unsigned long va,
66 unsigned long prpn,
67 unsigned long rflags,
68 unsigned long vflags,
69 int psize, int ssize);
70 long (*hpte_remove)(unsigned long hpte_group);
71 void (*hpte_removebolted)(unsigned long ea,
72 int psize, int ssize);
73 void (*flush_hash_range)(unsigned long number, int local);
74
75 /* special for kexec, to be called in real mode, linar mapping is
76 * destroyed as well */
77 void (*hpte_clear_all)(void);
78
79 int (*tce_build)(struct iommu_table *tbl,
80 long index,
81 long npages,
82 unsigned long uaddr,
83 enum dma_data_direction direction,
84 struct dma_attrs *attrs);
85 void (*tce_free)(struct iommu_table *tbl,
86 long index,
87 long npages);
88 unsigned long (*tce_get)(struct iommu_table *tbl,
89 long index);
90 void (*tce_flush)(struct iommu_table *tbl);
91 void (*pci_dma_dev_setup)(struct pci_dev *dev);
92 void (*pci_dma_bus_setup)(struct pci_bus *bus);
93
94 void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
95 unsigned long flags);
96 void (*iounmap)(volatile void __iomem *token);
97
98#ifdef CONFIG_PM
99 void (*iommu_save)(void);
100 void (*iommu_restore)(void);
101#endif
102#endif /* CONFIG_PPC64 */
103
104 int (*probe)(void);
105 void (*setup_arch)(void); /* Optional, may be NULL */
106 void (*init_early)(void);
107 /* Optional, may be NULL. */
108 void (*show_cpuinfo)(struct seq_file *m);
109 void (*show_percpuinfo)(struct seq_file *m, int i);
110
111 void (*init_IRQ)(void);
112 unsigned int (*get_irq)(void);
113#ifdef CONFIG_KEXEC
114 void (*kexec_cpu_down)(int crash_shutdown, int secondary);
115#endif
116
117 /* PCI stuff */
118 /* Called after scanning the bus, before allocating resources */
119 void (*pcibios_fixup)(void);
120 int (*pci_probe_mode)(struct pci_bus *);
121 void (*pci_irq_fixup)(struct pci_dev *dev);
122
123 /* To setup PHBs when using automatic OF platform driver for PCI */
124 int (*pci_setup_phb)(struct pci_controller *host);
125
126#ifdef CONFIG_PCI_MSI
127 int (*msi_check_device)(struct pci_dev* dev,
128 int nvec, int type);
129 int (*setup_msi_irqs)(struct pci_dev *dev,
130 int nvec, int type);
131 void (*teardown_msi_irqs)(struct pci_dev *dev);
132#endif
133
134 void (*restart)(char *cmd);
135 void (*power_off)(void);
136 void (*halt)(void);
137 void (*panic)(char *str);
138 void (*cpu_die)(void);
139
140 long (*time_init)(void); /* Optional, may be NULL */
141
142 int (*set_rtc_time)(struct rtc_time *);
143 void (*get_rtc_time)(struct rtc_time *);
144 unsigned long (*get_boot_time)(void);
145 unsigned char (*rtc_read_val)(int addr);
146 void (*rtc_write_val)(int addr, unsigned char val);
147
148 void (*calibrate_decr)(void);
149
150 void (*progress)(char *, unsigned short);
151
152 /* Interface for platform error logging */
153 void (*log_error)(char *buf, unsigned int err_type, int fatal);
154
155 unsigned char (*nvram_read_val)(int addr);
156 void (*nvram_write_val)(int addr, unsigned char val);
157 ssize_t (*nvram_write)(char *buf, size_t count, loff_t *index);
158 ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index);
159 ssize_t (*nvram_size)(void);
160 void (*nvram_sync)(void);
161
162 /* Exception handlers */
163 int (*system_reset_exception)(struct pt_regs *regs);
164 int (*machine_check_exception)(struct pt_regs *regs);
165
166 /* Motherboard/chipset features. This is a kind of general purpose
167 * hook used to control some machine specific features (like reset
168 * lines, chip power control, etc...).
169 */
170 long (*feature_call)(unsigned int feature, ...);
171
172 /* Get legacy PCI/IDE interrupt mapping */
173 int (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int channel);
174
175 /* Get access protection for /dev/mem */
176 pgprot_t (*phys_mem_access_prot)(struct file *file,
177 unsigned long pfn,
178 unsigned long size,
179 pgprot_t vma_prot);
180
181 /* Idle loop for this platform, leave empty for default idle loop */
182 void (*idle_loop)(void);
183
184 /*
185 * Function for waiting for work with reduced power in idle loop;
186 * called with interrupts disabled.
187 */
188 void (*power_save)(void);
189
190 /* Function to enable performance monitor counters for this
191 platform, called once per cpu. */
192 void (*enable_pmcs)(void);
193
194 /* Set DABR for this platform, leave empty for default implemenation */
195 int (*set_dabr)(unsigned long dabr);
196
197#ifdef CONFIG_PPC32 /* XXX for now */
198 /* A general init function, called by ppc_init in init/main.c.
199 May be NULL. */
200 void (*init)(void);
201
202 void (*kgdb_map_scc)(void);
203
204 /*
205 * optional PCI "hooks"
206 */
207 /* Called in indirect_* to avoid touching devices */
208 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
209
210 /* Called at then very end of pcibios_init() */
211 void (*pcibios_after_init)(void);
212
213#endif /* CONFIG_PPC32 */
214
215 /* Called after PPC generic resource fixup to perform
216 machine specific fixups */
217 void (*pcibios_fixup_resources)(struct pci_dev *);
218
219 /* Called for each PCI bus in the system when it's probed */
220 void (*pcibios_fixup_bus)(struct pci_bus *);
221
222 /* Called when pci_enable_device() is called. Returns 0 to
223 * allow assignment/enabling of the device. */
224 int (*pcibios_enable_device_hook)(struct pci_dev *);
225
226 /* Called to shutdown machine specific hardware not already controlled
227 * by other drivers.
228 */
229 void (*machine_shutdown)(void);
230
231#ifdef CONFIG_KEXEC
232 /* Called to do the minimal shutdown needed to run a kexec'd kernel
233 * to run successfully.
234 * XXX Should we move this one out of kexec scope?
235 */
236 void (*machine_crash_shutdown)(struct pt_regs *regs);
237
238 /* Called to do what every setup is needed on image and the
239 * reboot code buffer. Returns 0 on success.
240 * Provide your own (maybe dummy) implementation if your platform
241 * claims to support kexec.
242 */
243 int (*machine_kexec_prepare)(struct kimage *image);
244
245 /* Called to handle any machine specific cleanup on image */
246 void (*machine_kexec_cleanup)(struct kimage *image);
247
248 /* Called to perform the _real_ kexec.
249 * Do NOT allocate memory or fail here. We are past the point of
250 * no return.
251 */
252 void (*machine_kexec)(struct kimage *image);
253#endif /* CONFIG_KEXEC */
254
255#ifdef CONFIG_SUSPEND
256 /* These are called to disable and enable, respectively, IRQs when
257 * entering a suspend state. If NULL, then the generic versions
258 * will be called. The generic versions disable/enable the
259 * decrementer along with interrupts.
260 */
261 void (*suspend_disable_irqs)(void);
262 void (*suspend_enable_irqs)(void);
263#endif
264};
265
266extern void e500_idle(void);
267extern void power4_idle(void);
268extern void power4_cpu_offline_powersave(void);
269extern void ppc6xx_idle(void);
270
271/*
272 * ppc_md contains a copy of the machine description structure for the
273 * current platform. machine_id contains the initial address where the
274 * description was found during boot.
275 */
276extern struct machdep_calls ppc_md;
277extern struct machdep_calls *machine_id;
278
279#define __machine_desc __attribute__ ((__section__ (".machine.desc")))
280
281#define define_machine(name) \
282 extern struct machdep_calls mach_##name; \
283 EXPORT_SYMBOL(mach_##name); \
284 struct machdep_calls mach_##name __machine_desc =
285
286#define machine_is(name) \
287 ({ \
288 extern struct machdep_calls mach_##name \
289 __attribute__((weak)); \
290 machine_id == &mach_##name; \
291 })
292
293extern void probe_machine(void);
294
295extern char cmd_line[COMMAND_LINE_SIZE];
296
297#ifdef CONFIG_PPC_PMAC
298/*
299 * Power macintoshes have either a CUDA, PMU or SMU controlling
300 * system reset, power, NVRAM, RTC.
301 */
302typedef enum sys_ctrler_kind {
303 SYS_CTRLER_UNKNOWN = 0,
304 SYS_CTRLER_CUDA = 1,
305 SYS_CTRLER_PMU = 2,
306 SYS_CTRLER_SMU = 3,
307} sys_ctrler_t;
308extern sys_ctrler_t sys_ctrler;
309
310#endif /* CONFIG_PPC_PMAC */
311
312extern void setup_pci_ptrs(void);
313
314#ifdef CONFIG_SMP
315/* Poor default implementations */
316extern void __devinit smp_generic_give_timebase(void);
317extern void __devinit smp_generic_take_timebase(void);
318#endif /* CONFIG_SMP */
319
320
321/* Functions to produce codes on the leds.
322 * The SRC code should be unique for the message category and should
323 * be limited to the lower 24 bits (the upper 8 are set by these funcs),
324 * and (for boot & dump) should be sorted numerically in the order
325 * the events occur.
326 */
327/* Print a boot progress message. */
328void ppc64_boot_msg(unsigned int src, const char *msg);
329/* Print a termination message (print only -- does not stop the kernel) */
330void ppc64_terminate_msg(unsigned int src, const char *msg);
331
332static inline void log_error(char *buf, unsigned int err_type, int fatal)
333{
334 if (ppc_md.log_error)
335 ppc_md.log_error(buf, err_type, fatal);
336}
337
338#define __define_machine_initcall(mach,level,fn,id) \
339 static int __init __machine_initcall_##mach##_##fn(void) { \
340 if (machine_is(mach)) return fn(); \
341 return 0; \
342 } \
343 __define_initcall(level,__machine_initcall_##mach##_##fn,id);
344
345#define machine_core_initcall(mach,fn) __define_machine_initcall(mach,"1",fn,1)
346#define machine_core_initcall_sync(mach,fn) __define_machine_initcall(mach,"1s",fn,1s)
347#define machine_postcore_initcall(mach,fn) __define_machine_initcall(mach,"2",fn,2)
348#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s)
349#define machine_arch_initcall(mach,fn) __define_machine_initcall(mach,"3",fn,3)
350#define machine_arch_initcall_sync(mach,fn) __define_machine_initcall(mach,"3s",fn,3s)
351#define machine_subsys_initcall(mach,fn) __define_machine_initcall(mach,"4",fn,4)
352#define machine_subsys_initcall_sync(mach,fn) __define_machine_initcall(mach,"4s",fn,4s)
353#define machine_fs_initcall(mach,fn) __define_machine_initcall(mach,"5",fn,5)
354#define machine_fs_initcall_sync(mach,fn) __define_machine_initcall(mach,"5s",fn,5s)
355#define machine_rootfs_initcall(mach,fn) __define_machine_initcall(mach,"rootfs",fn,rootfs)
356#define machine_device_initcall(mach,fn) __define_machine_initcall(mach,"6",fn,6)
357#define machine_device_initcall_sync(mach,fn) __define_machine_initcall(mach,"6s",fn,6s)
358#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7)
359#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s)
360
361void generic_suspend_disable_irqs(void);
362void generic_suspend_enable_irqs(void);
363
364#endif /* __KERNEL__ */
365#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/arch/powerpc/include/asm/macio.h b/arch/powerpc/include/asm/macio.h
new file mode 100644
index 000000000000..079c06eae446
--- /dev/null
+++ b/arch/powerpc/include/asm/macio.h
@@ -0,0 +1,142 @@
1#ifndef __MACIO_ASIC_H__
2#define __MACIO_ASIC_H__
3#ifdef __KERNEL__
4
5#include <linux/of_device.h>
6
7extern struct bus_type macio_bus_type;
8
9/* MacIO device driver is defined later */
10struct macio_driver;
11struct macio_chip;
12
13#define MACIO_DEV_COUNT_RESOURCES 8
14#define MACIO_DEV_COUNT_IRQS 8
15
16/*
17 * the macio_bus structure is used to describe a "virtual" bus
18 * within a MacIO ASIC. It's typically provided by a macio_pci_asic
19 * PCI device, but could be provided differently as well (nubus
20 * machines using a fake OF tree).
21 *
22 * The pdev field can be NULL on non-PCI machines
23 */
24struct macio_bus
25{
26 struct macio_chip *chip; /* macio_chip (private use) */
27 int index; /* macio chip index in system */
28#ifdef CONFIG_PCI
29 struct pci_dev *pdev; /* PCI device hosting this bus */
30#endif
31};
32
33/*
34 * the macio_dev structure is used to describe a device
35 * within an Apple MacIO ASIC.
36 */
37struct macio_dev
38{
39 struct macio_bus *bus; /* macio bus this device is on */
40 struct macio_dev *media_bay; /* Device is part of a media bay */
41 struct of_device ofdev;
42 int n_resources;
43 struct resource resource[MACIO_DEV_COUNT_RESOURCES];
44 int n_interrupts;
45 struct resource interrupt[MACIO_DEV_COUNT_IRQS];
46};
47#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
48#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
49
50extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
51extern void macio_dev_put(struct macio_dev *dev);
52
53/*
54 * Accessors to resources & interrupts and other device
55 * fields
56 */
57
58static inline int macio_resource_count(struct macio_dev *dev)
59{
60 return dev->n_resources;
61}
62
63static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
64{
65 return dev->resource[resource_no].start;
66}
67
68static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
69{
70 return dev->resource[resource_no].end;
71}
72
73static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
74{
75 struct resource *res = &dev->resource[resource_no];
76 if (res->start == 0 || res->end == 0 || res->end < res->start)
77 return 0;
78 return res->end - res->start + 1;
79}
80
81extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
82extern void macio_release_resource(struct macio_dev *dev, int resource_no);
83extern int macio_request_resources(struct macio_dev *dev, const char *name);
84extern void macio_release_resources(struct macio_dev *dev);
85
86static inline int macio_irq_count(struct macio_dev *dev)
87{
88 return dev->n_interrupts;
89}
90
91static inline int macio_irq(struct macio_dev *dev, int irq_no)
92{
93 return dev->interrupt[irq_no].start;
94}
95
96static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
97{
98 dev_set_drvdata(&dev->ofdev.dev, data);
99}
100
101static inline void* macio_get_drvdata(struct macio_dev *dev)
102{
103 return dev_get_drvdata(&dev->ofdev.dev);
104}
105
106static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
107{
108 return mdev->ofdev.node;
109}
110
111#ifdef CONFIG_PCI
112static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
113{
114 return mdev->bus->pdev;
115}
116#endif
117
118/*
119 * A driver for a mac-io chip based device
120 */
121struct macio_driver
122{
123 char *name;
124 struct of_device_id *match_table;
125 struct module *owner;
126
127 int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
128 int (*remove)(struct macio_dev* dev);
129
130 int (*suspend)(struct macio_dev* dev, pm_message_t state);
131 int (*resume)(struct macio_dev* dev);
132 int (*shutdown)(struct macio_dev* dev);
133
134 struct device_driver driver;
135};
136#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
137
138extern int macio_register_driver(struct macio_driver *);
139extern void macio_unregister_driver(struct macio_driver *);
140
141#endif /* __KERNEL__ */
142#endif /* __MACIO_ASIC_H__ */
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..f2741c8b59a1
--- /dev/null
+++ b/arch/powerpc/include/asm/mc146818rtc.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_POWERPC_MC146818RTC_H
2#define _ASM_POWERPC_MC146818RTC_H
3
4/*
5 * Machine dependent access functions for RTC registers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifdef __KERNEL__
14
15#include <asm/io.h>
16
17#ifndef RTC_PORT
18#define RTC_PORT(x) (0x70 + (x))
19#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
20#endif
21
22/*
23 * The yet supported machines all access the RTC index register via
24 * an ISA port access but the way to access the date register differs ...
25 */
26#define CMOS_READ(addr) ({ \
27outb_p((addr),RTC_PORT(0)); \
28inb_p(RTC_PORT(1)); \
29})
30#define CMOS_WRITE(val, addr) ({ \
31outb_p((addr),RTC_PORT(0)); \
32outb_p((val),RTC_PORT(1)); \
33})
34
35#endif /* __KERNEL__ */
36#endif /* _ASM_POWERPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/mediabay.h b/arch/powerpc/include/asm/mediabay.h
new file mode 100644
index 000000000000..b2efb3325808
--- /dev/null
+++ b/arch/powerpc/include/asm/mediabay.h
@@ -0,0 +1,43 @@
1/*
2 * mediabay.h: definitions for using the media bay
3 * on PowerBook 3400 and similar computers.
4 *
5 * Copyright (C) 1997 Paul Mackerras.
6 */
7#ifndef _PPC_MEDIABAY_H
8#define _PPC_MEDIABAY_H
9
10#ifdef __KERNEL__
11
12#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
13#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
14#define MB_SOUND 2 /* sound device ? */
15#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
16#define MB_PCI 5 /* media bay contains a PCI device */
17#define MB_POWER 6 /* media bay contains a Power device (???) */
18#define MB_NO 7 /* media bay contains nothing */
19
20/* Number of bays in the machine or 0 */
21extern int media_bay_count;
22
23#ifdef CONFIG_BLK_DEV_IDE_PMAC
24#include <linux/ide.h>
25
26int check_media_bay_by_base(unsigned long base, int what);
27/* called by IDE PMAC host driver to register IDE controller for media bay */
28int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
29 int irq, ide_hwif_t *hwif);
30
31int check_media_bay(struct device_node *which_bay, int what);
32
33#else
34
35static inline int check_media_bay(struct device_node *which_bay, int what)
36{
37 return -ENODEV;
38}
39
40#endif
41
42#endif /* __KERNEL__ */
43#endif /* _PPC_MEDIABAY_H */
diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h
new file mode 100644
index 000000000000..9209f755763e
--- /dev/null
+++ b/arch/powerpc/include/asm/mman.h
@@ -0,0 +1,63 @@
1#ifndef _ASM_POWERPC_MMAN_H
2#define _ASM_POWERPC_MMAN_H
3
4#include <asm-generic/mman.h>
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define PROT_SAO 0x10 /* Strong Access Ordering */
14
15#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
16#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
17#define MAP_LOCKED 0x80
18
19#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
20#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
21#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
22
23#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
24#define MCL_FUTURE 0x4000 /* lock all additions to address space */
25
26#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
27#define MAP_NONBLOCK 0x10000 /* do not block on IO */
28
29#ifdef __KERNEL__
30#ifdef CONFIG_PPC64
31
32#include <asm/cputable.h>
33#include <linux/mm.h>
34
35/*
36 * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits()
37 * here. How important is the optimization?
38 */
39static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot)
40{
41 return (prot & PROT_SAO) ? VM_SAO : 0;
42}
43#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot)
44
45static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
46{
47 return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : 0;
48}
49#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
50
51static inline int arch_validate_prot(unsigned long prot)
52{
53 if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
54 return 0;
55 if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))
56 return 0;
57 return 1;
58}
59#define arch_validate_prot(prot) arch_validate_prot(prot)
60
61#endif /* CONFIG_PPC64 */
62#endif /* __KERNEL__ */
63#endif /* _ASM_POWERPC_MMAN_H */
diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/mmu-40x.h
new file mode 100644
index 000000000000..3d108676584c
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-40x.h
@@ -0,0 +1,63 @@
1#ifndef _ASM_POWERPC_MMU_40X_H_
2#define _ASM_POWERPC_MMU_40X_H_
3
4/*
5 * PPC40x support
6 */
7
8#define PPC40X_TLB_SIZE 64
9
10/*
11 * TLB entries are defined by a "high" tag portion and a "low" data
12 * portion. On all architectures, the data portion is 32-bits.
13 *
14 * TLB entries are managed entirely under software control by reading,
15 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
16 * instructions.
17 */
18
19#define TLB_LO 1
20#define TLB_HI 0
21
22#define TLB_DATA TLB_LO
23#define TLB_TAG TLB_HI
24
25/* Tag portion */
26
27#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
28#define TLB_PAGESZ_MASK 0x00000380
29#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
30#define PAGESZ_1K 0
31#define PAGESZ_4K 1
32#define PAGESZ_16K 2
33#define PAGESZ_64K 3
34#define PAGESZ_256K 4
35#define PAGESZ_1M 5
36#define PAGESZ_4M 6
37#define PAGESZ_16M 7
38#define TLB_VALID 0x00000040 /* Entry is valid */
39
40/* Data portion */
41
42#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
43#define TLB_PERM_MASK 0x00000300
44#define TLB_EX 0x00000200 /* Instruction execution allowed */
45#define TLB_WR 0x00000100 /* Writes permitted */
46#define TLB_ZSEL_MASK 0x000000F0
47#define TLB_ZSEL(x) (((x) & 0xF) << 4)
48#define TLB_ATTR_MASK 0x0000000F
49#define TLB_W 0x00000008 /* Caching is write-through */
50#define TLB_I 0x00000004 /* Caching is inhibited */
51#define TLB_M 0x00000002 /* Memory is coherent */
52#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
53
54#ifndef __ASSEMBLY__
55
56typedef struct {
57 unsigned long id;
58 unsigned long vdso_base;
59} mm_context_t;
60
61#endif /* !__ASSEMBLY__ */
62
63#endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
new file mode 100644
index 000000000000..a825524c981a
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -0,0 +1,76 @@
1#ifndef _ASM_POWERPC_MMU_44X_H_
2#define _ASM_POWERPC_MMU_44X_H_
3/*
4 * PPC440 support
5 */
6
7#define PPC44x_MMUCR_TID 0x000000ff
8#define PPC44x_MMUCR_STS 0x00010000
9
10#define PPC44x_TLB_PAGEID 0
11#define PPC44x_TLB_XLAT 1
12#define PPC44x_TLB_ATTRIB 2
13
14/* Page identification fields */
15#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
16#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
17#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
18#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
19#define PPC44x_TLB_4K 0x00000010
20#define PPC44x_TLB_16K 0x00000020
21#define PPC44x_TLB_64K 0x00000030
22#define PPC44x_TLB_256K 0x00000040
23#define PPC44x_TLB_1M 0x00000050
24#define PPC44x_TLB_16M 0x00000070
25#define PPC44x_TLB_256M 0x00000090
26
27/* Translation fields */
28#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
29#define PPC44x_TLB_ERPN_MASK 0x0000000f
30
31/* Storage attribute and access control fields */
32#define PPC44x_TLB_ATTR_MASK 0x0000ff80
33#define PPC44x_TLB_U0 0x00008000 /* User 0 */
34#define PPC44x_TLB_U1 0x00004000 /* User 1 */
35#define PPC44x_TLB_U2 0x00002000 /* User 2 */
36#define PPC44x_TLB_U3 0x00001000 /* User 3 */
37#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
38#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
39#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
40#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
41#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
42
43#define PPC44x_TLB_PERM_MASK 0x0000003f
44#define PPC44x_TLB_UX 0x00000020 /* User execution */
45#define PPC44x_TLB_UW 0x00000010 /* User write */
46#define PPC44x_TLB_UR 0x00000008 /* User read */
47#define PPC44x_TLB_SX 0x00000004 /* Super execution */
48#define PPC44x_TLB_SW 0x00000002 /* Super write */
49#define PPC44x_TLB_SR 0x00000001 /* Super read */
50
51/* Number of TLB entries */
52#define PPC44x_TLB_SIZE 64
53
54#ifndef __ASSEMBLY__
55
56extern unsigned int tlb_44x_hwater;
57
58typedef struct {
59 unsigned long id;
60 unsigned long vdso_base;
61} mm_context_t;
62
63#endif /* !__ASSEMBLY__ */
64
65#ifndef CONFIG_PPC_EARLY_DEBUG_44x
66#define PPC44x_EARLY_TLBS 1
67#else
68#define PPC44x_EARLY_TLBS 2
69#define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \
70 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
71#endif
72
73/* Size of the TLBs used for pinning in lowmem */
74#define PPC_PIN_SIZE (1 << 28) /* 256M */
75
76#endif /* _ASM_POWERPC_MMU_44X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
new file mode 100644
index 000000000000..9db877eb88db
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -0,0 +1,145 @@
1#ifndef _ASM_POWERPC_MMU_8XX_H_
2#define _ASM_POWERPC_MMU_8XX_H_
3/*
4 * PPC8xx support
5 */
6
7/* Control/status registers for the MPC8xx.
8 * A write operation to these registers causes serialized access.
9 * During software tablewalk, the registers used perform mask/shift-add
10 * operations when written/read. A TLB entry is created when the Mx_RPN
11 * is written, and the contents of several registers are used to
12 * create the entry.
13 */
14#define SPRN_MI_CTR 784 /* Instruction TLB control register */
15#define MI_GPM 0x80000000 /* Set domain manager mode */
16#define MI_PPM 0x40000000 /* Set subpage protection */
17#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
18#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
19#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
20#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
21#define MI_RESETVAL 0x00000000 /* Value of register at reset */
22
23/* These are the Ks and Kp from the PowerPC books. For proper operation,
24 * Ks = 0, Kp = 1.
25 */
26#define SPRN_MI_AP 786
27#define MI_Ks 0x80000000 /* Should not be set */
28#define MI_Kp 0x40000000 /* Should always be set */
29
30/* The effective page number register. When read, contains the information
31 * about the last instruction TLB miss. When MI_RPN is written, bits in
32 * this register are used to create the TLB entry.
33 */
34#define SPRN_MI_EPN 787
35#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
36#define MI_EVALID 0x00000200 /* Entry is valid */
37#define MI_ASIDMASK 0x0000000f /* ASID match value */
38 /* Reset value is undefined */
39
40/* A "level 1" or "segment" or whatever you want to call it register.
41 * For the instruction TLB, it contains bits that get loaded into the
42 * TLB entry when the MI_RPN is written.
43 */
44#define SPRN_MI_TWC 789
45#define MI_APG 0x000001e0 /* Access protection group (0) */
46#define MI_GUARDED 0x00000010 /* Guarded storage */
47#define MI_PSMASK 0x0000000c /* Mask of page size bits */
48#define MI_PS8MEG 0x0000000c /* 8M page size */
49#define MI_PS512K 0x00000004 /* 512K page size */
50#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
51#define MI_SVALID 0x00000001 /* Segment entry is valid */
52 /* Reset value is undefined */
53
54/* Real page number. Defined by the pte. Writing this register
55 * causes a TLB entry to be created for the instruction TLB, using
56 * additional information from the MI_EPN, and MI_TWC registers.
57 */
58#define SPRN_MI_RPN 790
59
60/* Define an RPN value for mapping kernel memory to large virtual
61 * pages for boot initialization. This has real page number of 0,
62 * large page size, shared page, cache enabled, and valid.
63 * Also mark all subpages valid and write access.
64 */
65#define MI_BOOTINIT 0x000001fd
66
67#define SPRN_MD_CTR 792 /* Data TLB control register */
68#define MD_GPM 0x80000000 /* Set domain manager mode */
69#define MD_PPM 0x40000000 /* Set subpage protection */
70#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
71#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
72#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
73#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
74#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
75#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
76#define MD_RESETVAL 0x04000000 /* Value of register at reset */
77
78#define SPRN_M_CASID 793 /* Address space ID (context) to match */
79#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
80
81
82/* These are the Ks and Kp from the PowerPC books. For proper operation,
83 * Ks = 0, Kp = 1.
84 */
85#define SPRN_MD_AP 794
86#define MD_Ks 0x80000000 /* Should not be set */
87#define MD_Kp 0x40000000 /* Should always be set */
88
89/* The effective page number register. When read, contains the information
90 * about the last instruction TLB miss. When MD_RPN is written, bits in
91 * this register are used to create the TLB entry.
92 */
93#define SPRN_MD_EPN 795
94#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
95#define MD_EVALID 0x00000200 /* Entry is valid */
96#define MD_ASIDMASK 0x0000000f /* ASID match value */
97 /* Reset value is undefined */
98
99/* The pointer to the base address of the first level page table.
100 * During a software tablewalk, reading this register provides the address
101 * of the entry associated with MD_EPN.
102 */
103#define SPRN_M_TWB 796
104#define M_L1TB 0xfffff000 /* Level 1 table base address */
105#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
106 /* Reset value is undefined */
107
108/* A "level 1" or "segment" or whatever you want to call it register.
109 * For the data TLB, it contains bits that get loaded into the TLB entry
110 * when the MD_RPN is written. It is also provides the hardware assist
111 * for finding the PTE address during software tablewalk.
112 */
113#define SPRN_MD_TWC 797
114#define MD_L2TB 0xfffff000 /* Level 2 table base address */
115#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
116#define MD_APG 0x000001e0 /* Access protection group (0) */
117#define MD_GUARDED 0x00000010 /* Guarded storage */
118#define MD_PSMASK 0x0000000c /* Mask of page size bits */
119#define MD_PS8MEG 0x0000000c /* 8M page size */
120#define MD_PS512K 0x00000004 /* 512K page size */
121#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
122#define MD_WT 0x00000002 /* Use writethrough page attribute */
123#define MD_SVALID 0x00000001 /* Segment entry is valid */
124 /* Reset value is undefined */
125
126
127/* Real page number. Defined by the pte. Writing this register
128 * causes a TLB entry to be created for the data TLB, using
129 * additional information from the MD_EPN, and MD_TWC registers.
130 */
131#define SPRN_MD_RPN 798
132
133/* This is a temporary storage register that could be used to save
134 * a processor working register during a tablewalk.
135 */
136#define SPRN_M_TW 799
137
138#ifndef __ASSEMBLY__
139typedef struct {
140 unsigned long id;
141 unsigned long vdso_base;
142} mm_context_t;
143#endif /* !__ASSEMBLY__ */
144
145#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-fsl-booke.h
new file mode 100644
index 000000000000..925d93cf64d8
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-fsl-booke.h
@@ -0,0 +1,82 @@
1#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
2#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
3/*
4 * Freescale Book-E MMU support
5 */
6
7/* Book-E defined page sizes */
8#define BOOKE_PAGESZ_1K 0
9#define BOOKE_PAGESZ_4K 1
10#define BOOKE_PAGESZ_16K 2
11#define BOOKE_PAGESZ_64K 3
12#define BOOKE_PAGESZ_256K 4
13#define BOOKE_PAGESZ_1M 5
14#define BOOKE_PAGESZ_4M 6
15#define BOOKE_PAGESZ_16M 7
16#define BOOKE_PAGESZ_64M 8
17#define BOOKE_PAGESZ_256M 9
18#define BOOKE_PAGESZ_1GB 10
19#define BOOKE_PAGESZ_4GB 11
20#define BOOKE_PAGESZ_16GB 12
21#define BOOKE_PAGESZ_64GB 13
22#define BOOKE_PAGESZ_256GB 14
23#define BOOKE_PAGESZ_1TB 15
24
25#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
26#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
27#define MAS0_NV(x) ((x) & 0x00000FFF)
28
29#define MAS1_VALID 0x80000000
30#define MAS1_IPROT 0x40000000
31#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
32#define MAS1_TS 0x00001000
33#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
34
35#define MAS2_EPN 0xFFFFF000
36#define MAS2_X0 0x00000040
37#define MAS2_X1 0x00000020
38#define MAS2_W 0x00000010
39#define MAS2_I 0x00000008
40#define MAS2_M 0x00000004
41#define MAS2_G 0x00000002
42#define MAS2_E 0x00000001
43
44#define MAS3_RPN 0xFFFFF000
45#define MAS3_U0 0x00000200
46#define MAS3_U1 0x00000100
47#define MAS3_U2 0x00000080
48#define MAS3_U3 0x00000040
49#define MAS3_UX 0x00000020
50#define MAS3_SX 0x00000010
51#define MAS3_UW 0x00000008
52#define MAS3_SW 0x00000004
53#define MAS3_UR 0x00000002
54#define MAS3_SR 0x00000001
55
56#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
57#define MAS4_TIDDSEL 0x000F0000
58#define MAS4_TSIZED(x) MAS1_TSIZE(x)
59#define MAS4_X0D 0x00000040
60#define MAS4_X1D 0x00000020
61#define MAS4_WD 0x00000010
62#define MAS4_ID 0x00000008
63#define MAS4_MD 0x00000004
64#define MAS4_GD 0x00000002
65#define MAS4_ED 0x00000001
66
67#define MAS6_SPID0 0x3FFF0000
68#define MAS6_SPID1 0x00007FFE
69#define MAS6_SAS 0x00000001
70#define MAS6_SPID MAS6_SPID0
71
72#define MAS7_RPN 0xFFFFFFFF
73
74#ifndef __ASSEMBLY__
75
76typedef struct {
77 unsigned long id;
78 unsigned long vdso_base;
79} mm_context_t;
80#endif /* !__ASSEMBLY__ */
81
82#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
new file mode 100644
index 000000000000..16b1a1e77e64
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -0,0 +1,83 @@
1#ifndef _ASM_POWERPC_MMU_HASH32_H_
2#define _ASM_POWERPC_MMU_HASH32_H_
3/*
4 * 32-bit hash table MMU support
5 */
6
7/*
8 * BATs
9 */
10
11/* Block size masks */
12#define BL_128K 0x000
13#define BL_256K 0x001
14#define BL_512K 0x003
15#define BL_1M 0x007
16#define BL_2M 0x00F
17#define BL_4M 0x01F
18#define BL_8M 0x03F
19#define BL_16M 0x07F
20#define BL_32M 0x0FF
21#define BL_64M 0x1FF
22#define BL_128M 0x3FF
23#define BL_256M 0x7FF
24
25/* BAT Access Protection */
26#define BPP_XX 0x00 /* No access */
27#define BPP_RX 0x01 /* Read only */
28#define BPP_RW 0x02 /* Read/write */
29
30#ifndef __ASSEMBLY__
31/* Contort a phys_addr_t into the right format/bits for a BAT */
32#ifdef CONFIG_PHYS_64BIT
33#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
34 ((x & 0x0000000e00000000ULL) >> 24) | \
35 ((x & 0x0000000100000000ULL) >> 30)))
36#else
37#define BAT_PHYS_ADDR(x) (x)
38#endif
39
40struct ppc_bat {
41 u32 batu;
42 u32 batl;
43};
44#endif /* !__ASSEMBLY__ */
45
46/*
47 * Hash table
48 */
49
50/* Values for PP (assumes Ks=0, Kp=1) */
51#define PP_RWXX 0 /* Supervisor read/write, User none */
52#define PP_RWRX 1 /* Supervisor read/write, User read */
53#define PP_RWRW 2 /* Supervisor read/write, User read/write */
54#define PP_RXRX 3 /* Supervisor read, User read */
55
56#ifndef __ASSEMBLY__
57
58/* Hardware Page Table Entry */
59struct hash_pte {
60 unsigned long v:1; /* Entry is valid */
61 unsigned long vsid:24; /* Virtual segment identifier */
62 unsigned long h:1; /* Hash algorithm indicator */
63 unsigned long api:6; /* Abbreviated page index */
64 unsigned long rpn:20; /* Real (physical) page number */
65 unsigned long :3; /* Unused */
66 unsigned long r:1; /* Referenced */
67 unsigned long c:1; /* Changed */
68 unsigned long w:1; /* Write-thru cache mode */
69 unsigned long i:1; /* Cache inhibited */
70 unsigned long m:1; /* Memory coherence */
71 unsigned long g:1; /* Guarded */
72 unsigned long :1; /* Unused */
73 unsigned long pp:2; /* Page protection */
74};
75
76typedef struct {
77 unsigned long id;
78 unsigned long vdso_base;
79} mm_context_t;
80
81#endif /* !__ASSEMBLY__ */
82
83#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
new file mode 100644
index 000000000000..19c7a9403490
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -0,0 +1,478 @@
1#ifndef _ASM_POWERPC_MMU_HASH64_H_
2#define _ASM_POWERPC_MMU_HASH64_H_
3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/asm-compat.h>
16#include <asm/page.h>
17
18/*
19 * Segment table
20 */
21
22#define STE_ESID_V 0x80
23#define STE_ESID_KS 0x20
24#define STE_ESID_KP 0x10
25#define STE_ESID_N 0x08
26
27#define STE_VSID_SHIFT 12
28
29/* Location of cpu0's segment table */
30#define STAB0_PAGE 0x6
31#define STAB0_OFFSET (STAB0_PAGE << 12)
32#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
33
34#ifndef __ASSEMBLY__
35extern char initial_stab[];
36#endif /* ! __ASSEMBLY */
37
38/*
39 * SLB
40 */
41
42#define SLB_NUM_BOLTED 3
43#define SLB_CACHE_ENTRIES 8
44
45/* Bits in the SLB ESID word */
46#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
47
48/* Bits in the SLB VSID word */
49#define SLB_VSID_SHIFT 12
50#define SLB_VSID_SHIFT_1T 24
51#define SLB_VSID_SSIZE_SHIFT 62
52#define SLB_VSID_B ASM_CONST(0xc000000000000000)
53#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
54#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
55#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
56#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
57#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
58#define SLB_VSID_L ASM_CONST(0x0000000000000100)
59#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
60#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
61#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
62#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
63#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
64#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
65#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
66
67#define SLB_VSID_KERNEL (SLB_VSID_KP)
68#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
69
70#define SLBIE_C (0x08000000)
71#define SLBIE_SSIZE_SHIFT 25
72
73/*
74 * Hash table
75 */
76
77#define HPTES_PER_GROUP 8
78
79#define HPTE_V_SSIZE_SHIFT 62
80#define HPTE_V_AVPN_SHIFT 7
81#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
82#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
83#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
84#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
85#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
86#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
87#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
88#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
89
90#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
91#define HPTE_R_TS ASM_CONST(0x4000000000000000)
92#define HPTE_R_RPN_SHIFT 12
93#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
94#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
95#define HPTE_R_PP ASM_CONST(0x0000000000000003)
96#define HPTE_R_N ASM_CONST(0x0000000000000004)
97#define HPTE_R_C ASM_CONST(0x0000000000000080)
98#define HPTE_R_R ASM_CONST(0x0000000000000100)
99
100#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
101#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
102
103/* Values for PP (assumes Ks=0, Kp=1) */
104/* pp0 will always be 0 for linux */
105#define PP_RWXX 0 /* Supervisor read/write, User none */
106#define PP_RWRX 1 /* Supervisor read/write, User read */
107#define PP_RWRW 2 /* Supervisor read/write, User read/write */
108#define PP_RXRX 3 /* Supervisor read, User read */
109
110#ifndef __ASSEMBLY__
111
112struct hash_pte {
113 unsigned long v;
114 unsigned long r;
115};
116
117extern struct hash_pte *htab_address;
118extern unsigned long htab_size_bytes;
119extern unsigned long htab_hash_mask;
120
121/*
122 * Page size definition
123 *
124 * shift : is the "PAGE_SHIFT" value for that page size
125 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
126 * directly to a slbmte "vsid" value
127 * penc : is the HPTE encoding mask for the "LP" field:
128 *
129 */
130struct mmu_psize_def
131{
132 unsigned int shift; /* number of bits */
133 unsigned int penc; /* HPTE encoding */
134 unsigned int tlbiel; /* tlbiel supported for that page size */
135 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
136 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
137};
138
139#endif /* __ASSEMBLY__ */
140
141/*
142 * The kernel use the constants below to index in the page sizes array.
143 * The use of fixed constants for this purpose is better for performances
144 * of the low level hash refill handlers.
145 *
146 * A non supported page size has a "shift" field set to 0
147 *
148 * Any new page size being implemented can get a new entry in here. Whether
149 * the kernel will use it or not is a different matter though. The actual page
150 * size used by hugetlbfs is not defined here and may be made variable
151 */
152
153#define MMU_PAGE_4K 0 /* 4K */
154#define MMU_PAGE_64K 1 /* 64K */
155#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
156#define MMU_PAGE_1M 3 /* 1M */
157#define MMU_PAGE_16M 4 /* 16M */
158#define MMU_PAGE_16G 5 /* 16G */
159#define MMU_PAGE_COUNT 6
160
161/*
162 * Segment sizes.
163 * These are the values used by hardware in the B field of
164 * SLB entries and the first dword of MMU hashtable entries.
165 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
166 */
167#define MMU_SEGSIZE_256M 0
168#define MMU_SEGSIZE_1T 1
169
170
171#ifndef __ASSEMBLY__
172
173/*
174 * The current system page and segment sizes
175 */
176extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
177extern int mmu_linear_psize;
178extern int mmu_virtual_psize;
179extern int mmu_vmalloc_psize;
180extern int mmu_vmemmap_psize;
181extern int mmu_io_psize;
182extern int mmu_kernel_ssize;
183extern int mmu_highuser_ssize;
184extern u16 mmu_slb_size;
185extern unsigned long tce_alloc_start, tce_alloc_end;
186
187/*
188 * If the processor supports 64k normal pages but not 64k cache
189 * inhibited pages, we have to be prepared to switch processes
190 * to use 4k pages when they create cache-inhibited mappings.
191 * If this is the case, mmu_ci_restrictions will be set to 1.
192 */
193extern int mmu_ci_restrictions;
194
195#ifdef CONFIG_HUGETLB_PAGE
196/*
197 * The page size indexes of the huge pages for use by hugetlbfs
198 */
199extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT];
200
201#endif /* CONFIG_HUGETLB_PAGE */
202
203/*
204 * This function sets the AVPN and L fields of the HPTE appropriately
205 * for the page size
206 */
207static inline unsigned long hpte_encode_v(unsigned long va, int psize,
208 int ssize)
209{
210 unsigned long v;
211 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
212 v <<= HPTE_V_AVPN_SHIFT;
213 if (psize != MMU_PAGE_4K)
214 v |= HPTE_V_LARGE;
215 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
216 return v;
217}
218
219/*
220 * This function sets the ARPN, and LP fields of the HPTE appropriately
221 * for the page size. We assume the pa is already "clean" that is properly
222 * aligned for the requested page size
223 */
224static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
225{
226 unsigned long r;
227
228 /* A 4K page needs no special encoding */
229 if (psize == MMU_PAGE_4K)
230 return pa & HPTE_R_RPN;
231 else {
232 unsigned int penc = mmu_psize_defs[psize].penc;
233 unsigned int shift = mmu_psize_defs[psize].shift;
234 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
235 }
236 return r;
237}
238
239/*
240 * Build a VA given VSID, EA and segment size
241 */
242static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
243 int ssize)
244{
245 if (ssize == MMU_SEGSIZE_256M)
246 return (vsid << 28) | (ea & 0xfffffffUL);
247 return (vsid << 40) | (ea & 0xffffffffffUL);
248}
249
250/*
251 * This hashes a virtual address
252 */
253
254static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
255 int ssize)
256{
257 unsigned long hash, vsid;
258
259 if (ssize == MMU_SEGSIZE_256M) {
260 hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
261 } else {
262 vsid = va >> 40;
263 hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
264 }
265 return hash & 0x7fffffffffUL;
266}
267
268extern int __hash_page_4K(unsigned long ea, unsigned long access,
269 unsigned long vsid, pte_t *ptep, unsigned long trap,
270 unsigned int local, int ssize, int subpage_prot);
271extern int __hash_page_64K(unsigned long ea, unsigned long access,
272 unsigned long vsid, pte_t *ptep, unsigned long trap,
273 unsigned int local, int ssize);
274struct mm_struct;
275extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
276extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
277 unsigned long ea, unsigned long vsid, int local,
278 unsigned long trap);
279
280extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
281 unsigned long pstart, unsigned long mode,
282 int psize, int ssize);
283extern void set_huge_psize(int psize);
284extern void add_gpage(unsigned long addr, unsigned long page_size,
285 unsigned long number_of_pages);
286extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
287
288extern void htab_initialize(void);
289extern void htab_initialize_secondary(void);
290extern void hpte_init_native(void);
291extern void hpte_init_lpar(void);
292extern void hpte_init_iSeries(void);
293extern void hpte_init_beat(void);
294extern void hpte_init_beat_v3(void);
295
296extern void stabs_alloc(void);
297extern void slb_initialize(void);
298extern void slb_flush_and_rebolt(void);
299extern void stab_initialize(unsigned long stab);
300
301extern void slb_vmalloc_update(void);
302#endif /* __ASSEMBLY__ */
303
304/*
305 * VSID allocation
306 *
307 * We first generate a 36-bit "proto-VSID". For kernel addresses this
308 * is equal to the ESID, for user addresses it is:
309 * (context << 15) | (esid & 0x7fff)
310 *
311 * The two forms are distinguishable because the top bit is 0 for user
312 * addresses, whereas the top two bits are 1 for kernel addresses.
313 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
314 * now.
315 *
316 * The proto-VSIDs are then scrambled into real VSIDs with the
317 * multiplicative hash:
318 *
319 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
320 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
321 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
322 *
323 * This scramble is only well defined for proto-VSIDs below
324 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
325 * reserved. VSID_MULTIPLIER is prime, so in particular it is
326 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
327 * Because the modulus is 2^n-1 we can compute it efficiently without
328 * a divide or extra multiply (see below).
329 *
330 * This scheme has several advantages over older methods:
331 *
332 * - We have VSIDs allocated for every kernel address
333 * (i.e. everything above 0xC000000000000000), except the very top
334 * segment, which simplifies several things.
335 *
336 * - We allow for 15 significant bits of ESID and 20 bits of
337 * context for user addresses. i.e. 8T (43 bits) of address space for
338 * up to 1M contexts (although the page table structure and context
339 * allocation will need changes to take advantage of this).
340 *
341 * - The scramble function gives robust scattering in the hash
342 * table (at least based on some initial results). The previous
343 * method was more susceptible to pathological cases giving excessive
344 * hash collisions.
345 */
346/*
347 * WARNING - If you change these you must make sure the asm
348 * implementations in slb_allocate (slb_low.S), do_stab_bolted
349 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
350 *
351 * You'll also need to change the precomputed VSID values in head.S
352 * which are used by the iSeries firmware.
353 */
354
355#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
356#define VSID_BITS_256M 36
357#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
358
359#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
360#define VSID_BITS_1T 24
361#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
362
363#define CONTEXT_BITS 19
364#define USER_ESID_BITS 16
365#define USER_ESID_BITS_1T 4
366
367#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
368
369/*
370 * This macro generates asm code to compute the VSID scramble
371 * function. Used in slb_allocate() and do_stab_bolted. The function
372 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
373 *
374 * rt = register continaing the proto-VSID and into which the
375 * VSID will be stored
376 * rx = scratch register (clobbered)
377 *
378 * - rt and rx must be different registers
379 * - The answer will end up in the low VSID_BITS bits of rt. The higher
380 * bits may contain other garbage, so you may need to mask the
381 * result.
382 */
383#define ASM_VSID_SCRAMBLE(rt, rx, size) \
384 lis rx,VSID_MULTIPLIER_##size@h; \
385 ori rx,rx,VSID_MULTIPLIER_##size@l; \
386 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
387 \
388 srdi rx,rt,VSID_BITS_##size; \
389 clrldi rt,rt,(64-VSID_BITS_##size); \
390 add rt,rt,rx; /* add high and low bits */ \
391 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
392 * 2^36-1+2^28-1. That in particular means that if r3 >= \
393 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
394 * the bit clear, r3 already has the answer we want, if it \
395 * doesn't, the answer is the low 36 bits of r3+1. So in all \
396 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
397 addi rx,rt,1; \
398 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
399 add rt,rt,rx
400
401
402#ifndef __ASSEMBLY__
403
404typedef unsigned long mm_context_id_t;
405
406typedef struct {
407 mm_context_id_t id;
408 u16 user_psize; /* page size index */
409
410#ifdef CONFIG_PPC_MM_SLICES
411 u64 low_slices_psize; /* SLB page size encodings */
412 u64 high_slices_psize; /* 4 bits per slice for now */
413#else
414 u16 sllp; /* SLB page size encoding */
415#endif
416 unsigned long vdso_base;
417} mm_context_t;
418
419
420#if 0
421/*
422 * The code below is equivalent to this function for arguments
423 * < 2^VSID_BITS, which is all this should ever be called
424 * with. However gcc is not clever enough to compute the
425 * modulus (2^n-1) without a second multiply.
426 */
427#define vsid_scrample(protovsid, size) \
428 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
429
430#else /* 1 */
431#define vsid_scramble(protovsid, size) \
432 ({ \
433 unsigned long x; \
434 x = (protovsid) * VSID_MULTIPLIER_##size; \
435 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
436 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
437 })
438#endif /* 1 */
439
440/* This is only valid for addresses >= KERNELBASE */
441static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
442{
443 if (ssize == MMU_SEGSIZE_256M)
444 return vsid_scramble(ea >> SID_SHIFT, 256M);
445 return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
446}
447
448/* Returns the segment size indicator for a user address */
449static inline int user_segment_size(unsigned long addr)
450{
451 /* Use 1T segments if possible for addresses >= 1T */
452 if (addr >= (1UL << SID_SHIFT_1T))
453 return mmu_highuser_ssize;
454 return MMU_SEGSIZE_256M;
455}
456
457/* This is only valid for user addresses (which are below 2^44) */
458static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
459 int ssize)
460{
461 if (ssize == MMU_SEGSIZE_256M)
462 return vsid_scramble((context << USER_ESID_BITS)
463 | (ea >> SID_SHIFT), 256M);
464 return vsid_scramble((context << USER_ESID_BITS_1T)
465 | (ea >> SID_SHIFT_1T), 1T);
466}
467
468/*
469 * This is only used on legacy iSeries in lparmap.c,
470 * hence the 256MB segment assumption.
471 */
472#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \
473 VSID_MODULUS_256M)
474#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
475
476#endif /* __ASSEMBLY__ */
477
478#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
new file mode 100644
index 000000000000..4c0e1b4f975c
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu.h
@@ -0,0 +1,26 @@
1#ifndef _ASM_POWERPC_MMU_H_
2#define _ASM_POWERPC_MMU_H_
3#ifdef __KERNEL__
4
5#ifdef CONFIG_PPC64
6/* 64-bit classic hash table MMU */
7# include <asm/mmu-hash64.h>
8#elif defined(CONFIG_PPC_STD_MMU)
9/* 32-bit classic hash table MMU */
10# include <asm/mmu-hash32.h>
11#elif defined(CONFIG_40x)
12/* 40x-style software loaded TLB */
13# include <asm/mmu-40x.h>
14#elif defined(CONFIG_44x)
15/* 44x-style software loaded TLB */
16# include <asm/mmu-44x.h>
17#elif defined(CONFIG_FSL_BOOKE)
18/* Freescale Book-E software loaded TLB */
19# include <asm/mmu-fsl-booke.h>
20#elif defined (CONFIG_PPC_8xx)
21/* Motorola/Freescale 8xx software loaded TLB */
22# include <asm/mmu-8xx.h>
23#endif
24
25#endif /* __KERNEL__ */
26#endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
new file mode 100644
index 000000000000..9102b8bf0ead
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -0,0 +1,280 @@
1#ifndef __ASM_POWERPC_MMU_CONTEXT_H
2#define __ASM_POWERPC_MMU_CONTEXT_H
3#ifdef __KERNEL__
4
5#include <asm/mmu.h>
6#include <asm/cputable.h>
7#include <asm-generic/mm_hooks.h>
8
9#ifndef CONFIG_PPC64
10#include <asm/atomic.h>
11#include <linux/bitops.h>
12
13/*
14 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
15 * (virtual segment identifiers) for each context. Although the
16 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
17 * we only use 32,768 of them. That is ample, since there can be
18 * at most around 30,000 tasks in the system anyway, and it means
19 * that we can use a bitmap to indicate which contexts are in use.
20 * Using a bitmap means that we entirely avoid all of the problems
21 * that we used to have when the context number overflowed,
22 * particularly on SMP systems.
23 * -- paulus.
24 */
25
26/*
27 * This function defines the mapping from contexts to VSIDs (virtual
28 * segment IDs). We use a skew on both the context and the high 4 bits
29 * of the 32-bit virtual address (the "effective segment ID") in order
30 * to spread out the entries in the MMU hash table. Note, if this
31 * function is changed then arch/ppc/mm/hashtable.S will have to be
32 * changed to correspond.
33 */
34#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
35 & 0xffffff)
36
37/*
38 The MPC8xx has only 16 contexts. We rotate through them on each
39 task switch. A better way would be to keep track of tasks that
40 own contexts, and implement an LRU usage. That way very active
41 tasks don't always have to pay the TLB reload overhead. The
42 kernel pages are mapped shared, so the kernel can run on behalf
43 of any task that makes a kernel entry. Shared does not mean they
44 are not protected, just that the ASID comparison is not performed.
45 -- Dan
46
47 The IBM4xx has 256 contexts, so we can just rotate through these
48 as a way of "switching" contexts. If the TID of the TLB is zero,
49 the PID/TID comparison is disabled, so we can use a TID of zero
50 to represent all kernel pages as shared among all contexts.
51 -- Dan
52 */
53
54static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
55{
56}
57
58#ifdef CONFIG_8xx
59#define NO_CONTEXT 16
60#define LAST_CONTEXT 15
61#define FIRST_CONTEXT 0
62
63#elif defined(CONFIG_4xx)
64#define NO_CONTEXT 256
65#define LAST_CONTEXT 255
66#define FIRST_CONTEXT 1
67
68#elif defined(CONFIG_E200) || defined(CONFIG_E500)
69#define NO_CONTEXT 256
70#define LAST_CONTEXT 255
71#define FIRST_CONTEXT 1
72
73#else
74
75/* PPC 6xx, 7xx CPUs */
76#define NO_CONTEXT ((unsigned long) -1)
77#define LAST_CONTEXT 32767
78#define FIRST_CONTEXT 1
79#endif
80
81/*
82 * Set the current MMU context.
83 * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
84 * loading up the segment registers for the user part of the address space.
85 *
86 * Since the PGD is immediately available, it is much faster to simply
87 * pass this along as a second parameter, which is required for 8xx and
88 * can be used for debugging on all processors (if you happen to have
89 * an Abatron).
90 */
91extern void set_context(unsigned long contextid, pgd_t *pgd);
92
93/*
94 * Bitmap of contexts in use.
95 * The size of this bitmap is LAST_CONTEXT + 1 bits.
96 */
97extern unsigned long context_map[];
98
99/*
100 * This caches the next context number that we expect to be free.
101 * Its use is an optimization only, we can't rely on this context
102 * number to be free, but it usually will be.
103 */
104extern unsigned long next_mmu_context;
105
106/*
107 * If we don't have sufficient contexts to give one to every task
108 * that could be in the system, we need to be able to steal contexts.
109 * These variables support that.
110 */
111#if LAST_CONTEXT < 30000
112#define FEW_CONTEXTS 1
113extern atomic_t nr_free_contexts;
114extern struct mm_struct *context_mm[LAST_CONTEXT+1];
115extern void steal_context(void);
116#endif
117
118/*
119 * Get a new mmu context for the address space described by `mm'.
120 */
121static inline void get_mmu_context(struct mm_struct *mm)
122{
123 unsigned long ctx;
124
125 if (mm->context.id != NO_CONTEXT)
126 return;
127#ifdef FEW_CONTEXTS
128 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
129 steal_context();
130#endif
131 ctx = next_mmu_context;
132 while (test_and_set_bit(ctx, context_map)) {
133 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
134 if (ctx > LAST_CONTEXT)
135 ctx = 0;
136 }
137 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
138 mm->context.id = ctx;
139#ifdef FEW_CONTEXTS
140 context_mm[ctx] = mm;
141#endif
142}
143
144/*
145 * Set up the context for a new address space.
146 */
147static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
148{
149 mm->context.id = NO_CONTEXT;
150 mm->context.vdso_base = 0;
151 return 0;
152}
153
154/*
155 * We're finished using the context for an address space.
156 */
157static inline void destroy_context(struct mm_struct *mm)
158{
159 preempt_disable();
160 if (mm->context.id != NO_CONTEXT) {
161 clear_bit(mm->context.id, context_map);
162 mm->context.id = NO_CONTEXT;
163#ifdef FEW_CONTEXTS
164 atomic_inc(&nr_free_contexts);
165#endif
166 }
167 preempt_enable();
168}
169
170static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
171 struct task_struct *tsk)
172{
173#ifdef CONFIG_ALTIVEC
174 if (cpu_has_feature(CPU_FTR_ALTIVEC))
175 asm volatile ("dssall;\n"
176#ifndef CONFIG_POWER4
177 "sync;\n" /* G4 needs a sync here, G5 apparently not */
178#endif
179 : : );
180#endif /* CONFIG_ALTIVEC */
181
182 tsk->thread.pgdir = next->pgd;
183
184 /* No need to flush userspace segments if the mm doesnt change */
185 if (prev == next)
186 return;
187
188 /* Setup new userspace context */
189 get_mmu_context(next);
190 set_context(next->context.id, next->pgd);
191}
192
193#define deactivate_mm(tsk,mm) do { } while (0)
194
195/*
196 * After we have set current->mm to a new value, this activates
197 * the context for the new mm so we see the new mappings.
198 */
199#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
200
201extern void mmu_context_init(void);
202
203
204#else
205
206#include <linux/kernel.h>
207#include <linux/mm.h>
208#include <linux/sched.h>
209
210/*
211 * Copyright (C) 2001 PPC 64 Team, IBM Corp
212 *
213 * This program is free software; you can redistribute it and/or
214 * modify it under the terms of the GNU General Public License
215 * as published by the Free Software Foundation; either version
216 * 2 of the License, or (at your option) any later version.
217 */
218
219static inline void enter_lazy_tlb(struct mm_struct *mm,
220 struct task_struct *tsk)
221{
222}
223
224/*
225 * The proto-VSID space has 2^35 - 1 segments available for user mappings.
226 * Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
227 * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
228 */
229#define NO_CONTEXT 0
230#define MAX_CONTEXT ((1UL << 19) - 1)
231
232extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
233extern void destroy_context(struct mm_struct *mm);
234
235extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
236extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
237
238/*
239 * switch_mm is the entry point called from the architecture independent
240 * code in kernel/sched.c
241 */
242static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
243 struct task_struct *tsk)
244{
245 if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
246 cpu_set(smp_processor_id(), next->cpu_vm_mask);
247
248 /* No need to flush userspace segments if the mm doesnt change */
249 if (prev == next)
250 return;
251
252#ifdef CONFIG_ALTIVEC
253 if (cpu_has_feature(CPU_FTR_ALTIVEC))
254 asm volatile ("dssall");
255#endif /* CONFIG_ALTIVEC */
256
257 if (cpu_has_feature(CPU_FTR_SLB))
258 switch_slb(tsk, next);
259 else
260 switch_stab(tsk, next);
261}
262
263#define deactivate_mm(tsk,mm) do { } while (0)
264
265/*
266 * After we have set current->mm to a new value, this activates
267 * the context for the new mm so we see the new mappings.
268 */
269static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
270{
271 unsigned long flags;
272
273 local_irq_save(flags);
274 switch_mm(prev, next, current);
275 local_irq_restore(flags);
276}
277
278#endif /* CONFIG_PPC64 */
279#endif /* __KERNEL__ */
280#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
new file mode 100644
index 000000000000..19f299b7e256
--- /dev/null
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -0,0 +1,47 @@
1/*
2 * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
3 *
4 * PowerPC64 port:
5 * Copyright (C) 2002 Anton Blanchard, IBM Corp.
6 */
7#ifndef _ASM_MMZONE_H_
8#define _ASM_MMZONE_H_
9#ifdef __KERNEL__
10
11
12/*
13 * generic non-linear memory support:
14 *
15 * 1) we will not split memory into more chunks than will fit into the
16 * flags field of the struct page
17 */
18
19#ifdef CONFIG_NEED_MULTIPLE_NODES
20
21extern struct pglist_data *node_data[];
22/*
23 * Return a pointer to the node data for node n.
24 */
25#define NODE_DATA(nid) (node_data[nid])
26
27/*
28 * Following are specific to this numa platform.
29 */
30
31extern int numa_cpu_lookup_table[];
32extern cpumask_t numa_cpumask_lookup_table[];
33#ifdef CONFIG_MEMORY_HOTPLUG
34extern unsigned long max_pfn;
35#endif
36
37/*
38 * Following are macros that each numa implmentation must define.
39 */
40
41#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
42#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
43
44#endif /* CONFIG_NEED_MULTIPLE_NODES */
45
46#endif /* __KERNEL__ */
47#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/powerpc/include/asm/module.h b/arch/powerpc/include/asm/module.h
new file mode 100644
index 000000000000..e5f14b13ccf0
--- /dev/null
+++ b/arch/powerpc/include/asm/module.h
@@ -0,0 +1,77 @@
1#ifndef _ASM_POWERPC_MODULE_H
2#define _ASM_POWERPC_MODULE_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <asm/bug.h>
14
15
16#ifndef __powerpc64__
17/*
18 * Thanks to Paul M for explaining this.
19 *
20 * PPC can only do rel jumps += 32MB, and often the kernel and other
21 * modules are furthur away than this. So, we jump to a table of
22 * trampolines attached to the module (the Procedure Linkage Table)
23 * whenever that happens.
24 */
25
26struct ppc_plt_entry {
27 /* 16 byte jump instruction sequence (4 instructions) */
28 unsigned int jump[4];
29};
30#endif /* __powerpc64__ */
31
32
33struct mod_arch_specific {
34#ifdef __powerpc64__
35 unsigned int stubs_section; /* Index of stubs section in module */
36 unsigned int toc_section; /* What section is the TOC? */
37#else
38 /* Indices of PLT sections within module. */
39 unsigned int core_plt_section;
40 unsigned int init_plt_section;
41#endif
42
43 /* List of BUG addresses, source line numbers and filenames */
44 struct list_head bug_list;
45 struct bug_entry *bug_table;
46 unsigned int num_bugs;
47};
48
49/*
50 * Select ELF headers.
51 * Make empty section for module_frob_arch_sections to expand.
52 */
53
54#ifdef __powerpc64__
55# define Elf_Shdr Elf64_Shdr
56# define Elf_Sym Elf64_Sym
57# define Elf_Ehdr Elf64_Ehdr
58# ifdef MODULE
59 asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
60# endif
61#else
62# define Elf_Shdr Elf32_Shdr
63# define Elf_Sym Elf32_Sym
64# define Elf_Ehdr Elf32_Ehdr
65# ifdef MODULE
66 asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
67 asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
68# endif /* MODULE */
69#endif
70
71
72struct exception_table_entry;
73void sort_ex_table(struct exception_table_entry *start,
74 struct exception_table_entry *finish);
75
76#endif /* __KERNEL__ */
77#endif /* _ASM_POWERPC_MODULE_H */
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
new file mode 100644
index 000000000000..c48a1658eeac
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc512x.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
5 *
6 * Description:
7 * MPC5121 Prototypes and definitions
8 *
9 * This is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#ifndef __ASM_POWERPC_MPC512x_H__
17#define __ASM_POWERPC_MPC512x_H__
18
19extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
20
21#endif /* __ASM_POWERPC_MPC512x_H__ */
22
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
new file mode 100644
index 000000000000..81ef10b6b672
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -0,0 +1,295 @@
1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21#include <linux/suspend.h>
22
23/* Variants of the 5200(B) */
24#define MPC5200_SVR 0x80110010
25#define MPC5200_SVR_MASK 0xfffffff0
26#define MPC5200B_SVR 0x80110020
27#define MPC5200B_SVR_MASK 0xfffffff0
28
29/* ======================================================================== */
30/* Structures mapping of some unit register set */
31/* ======================================================================== */
32
33#ifndef __ASSEMBLY__
34
35/* Memory Mapping Control */
36struct mpc52xx_mmap_ctl {
37 u32 mbar; /* MMAP_CTRL + 0x00 */
38
39 u32 cs0_start; /* MMAP_CTRL + 0x04 */
40 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
41 u32 cs1_start; /* MMAP_CTRL + 0x0c */
42 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
43 u32 cs2_start; /* MMAP_CTRL + 0x14 */
44 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
45 u32 cs3_start; /* MMAP_CTRL + 0x1c */
46 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
47 u32 cs4_start; /* MMAP_CTRL + 0x24 */
48 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
49 u32 cs5_start; /* MMAP_CTRL + 0x2c */
50 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
51
52 u32 sdram0; /* MMAP_CTRL + 0x34 */
53 u32 sdram1; /* MMAP_CTRL + 0X38 */
54
55 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
56
57 u32 boot_start; /* MMAP_CTRL + 0x4c */
58 u32 boot_stop; /* MMAP_CTRL + 0x50 */
59
60 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
61
62 u32 cs6_start; /* MMAP_CTRL + 0x58 */
63 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
64 u32 cs7_start; /* MMAP_CTRL + 0x60 */
65 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
66};
67
68/* SDRAM control */
69struct mpc52xx_sdram {
70 u32 mode; /* SDRAM + 0x00 */
71 u32 ctrl; /* SDRAM + 0x04 */
72 u32 config1; /* SDRAM + 0x08 */
73 u32 config2; /* SDRAM + 0x0c */
74};
75
76/* SDMA */
77struct mpc52xx_sdma {
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
82
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
86
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
89
90 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
91
92 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
93
94 u32 cReqSelect; /* SDMA + 0x5c */
95 u32 task_size0; /* SDMA + 0x60 */
96 u32 task_size1; /* SDMA + 0x64 */
97 u32 MDEDebug; /* SDMA + 0x68 */
98 u32 ADSDebug; /* SDMA + 0x6c */
99 u32 Value1; /* SDMA + 0x70 */
100 u32 Value2; /* SDMA + 0x74 */
101 u32 Control; /* SDMA + 0x78 */
102 u32 Status; /* SDMA + 0x7c */
103 u32 PTDDebug; /* SDMA + 0x80 */
104};
105
106/* GPT */
107struct mpc52xx_gpt {
108 u32 mode; /* GPTx + 0x00 */
109 u32 count; /* GPTx + 0x04 */
110 u32 pwm; /* GPTx + 0x08 */
111 u32 status; /* GPTx + 0X0c */
112};
113
114/* GPIO */
115struct mpc52xx_gpio {
116 u32 port_config; /* GPIO + 0x00 */
117 u32 simple_gpioe; /* GPIO + 0x04 */
118 u32 simple_ode; /* GPIO + 0x08 */
119 u32 simple_ddr; /* GPIO + 0x0c */
120 u32 simple_dvo; /* GPIO + 0x10 */
121 u32 simple_ival; /* GPIO + 0x14 */
122 u8 outo_gpioe; /* GPIO + 0x18 */
123 u8 reserved1[3]; /* GPIO + 0x19 */
124 u8 outo_dvo; /* GPIO + 0x1c */
125 u8 reserved2[3]; /* GPIO + 0x1d */
126 u8 sint_gpioe; /* GPIO + 0x20 */
127 u8 reserved3[3]; /* GPIO + 0x21 */
128 u8 sint_ode; /* GPIO + 0x24 */
129 u8 reserved4[3]; /* GPIO + 0x25 */
130 u8 sint_ddr; /* GPIO + 0x28 */
131 u8 reserved5[3]; /* GPIO + 0x29 */
132 u8 sint_dvo; /* GPIO + 0x2c */
133 u8 reserved6[3]; /* GPIO + 0x2d */
134 u8 sint_inten; /* GPIO + 0x30 */
135 u8 reserved7[3]; /* GPIO + 0x31 */
136 u16 sint_itype; /* GPIO + 0x34 */
137 u16 reserved8; /* GPIO + 0x36 */
138 u8 gpio_control; /* GPIO + 0x38 */
139 u8 reserved9[3]; /* GPIO + 0x39 */
140 u8 sint_istat; /* GPIO + 0x3c */
141 u8 sint_ival; /* GPIO + 0x3d */
142 u8 bus_errs; /* GPIO + 0x3e */
143 u8 reserved10; /* GPIO + 0x3f */
144};
145
146#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
147#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
148#define MPC52xx_GPIO_PCI_DIS (1<<15)
149
150/* GPIO with WakeUp*/
151struct mpc52xx_gpio_wkup {
152 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
153 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
154 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
155 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
156 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
157 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
158 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
159 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
160 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
161 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
162 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
163 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
164 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
165 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
166 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
167 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
168 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
169 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
170 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
171 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
172};
173
174/* XLB Bus control */
175struct mpc52xx_xlb {
176 u8 reserved[0x40];
177 u32 config; /* XLB + 0x40 */
178 u32 version; /* XLB + 0x44 */
179 u32 status; /* XLB + 0x48 */
180 u32 int_enable; /* XLB + 0x4c */
181 u32 addr_capture; /* XLB + 0x50 */
182 u32 bus_sig_capture; /* XLB + 0x54 */
183 u32 addr_timeout; /* XLB + 0x58 */
184 u32 data_timeout; /* XLB + 0x5c */
185 u32 bus_act_timeout; /* XLB + 0x60 */
186 u32 master_pri_enable; /* XLB + 0x64 */
187 u32 master_priority; /* XLB + 0x68 */
188 u32 base_address; /* XLB + 0x6c */
189 u32 snoop_window; /* XLB + 0x70 */
190};
191
192#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
193#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
194
195/* Clock Distribution control */
196struct mpc52xx_cdm {
197 u32 jtag_id; /* CDM + 0x00 reg0 read only */
198 u32 rstcfg; /* CDM + 0x04 reg1 read only */
199 u32 breadcrumb; /* CDM + 0x08 reg2 */
200
201 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
202 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
203 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
204 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
205
206 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
207 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
208 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
209
210 u32 clk_enables; /* CDM + 0x14 reg5 */
211
212 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
213 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
214
215 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
216 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
217 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
218 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
219
220 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
221 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
222 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
223
224 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
225 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
226 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
227 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
228
229 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
230 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
231
232 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
233 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
234
235 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
236 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
237
238 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
239 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
240};
241
242#endif /* __ASSEMBLY__ */
243
244
245/* ========================================================================= */
246/* Prototypes for MPC52xx sysdev */
247/* ========================================================================= */
248
249#ifndef __ASSEMBLY__
250
251/* mpc52xx_common.c */
252extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
253extern void mpc5200_setup_xlb_arbiter(void);
254extern void mpc52xx_declare_of_platform_devices(void);
255extern void mpc52xx_map_common_devices(void);
256extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
257extern void mpc52xx_restart(char *cmd);
258
259/* mpc52xx_pic.c */
260extern void mpc52xx_init_irq(void);
261extern unsigned int mpc52xx_get_irq(void);
262
263/* mpc52xx_pci.c */
264#ifdef CONFIG_PCI
265extern int __init mpc52xx_add_bridge(struct device_node *node);
266extern void __init mpc52xx_setup_pci(void);
267#else
268static inline void mpc52xx_setup_pci(void) { }
269#endif
270
271#endif /* __ASSEMBLY__ */
272
273#ifdef CONFIG_PM
274struct mpc52xx_suspend {
275 void (*board_suspend_prepare)(void __iomem *mbar);
276 void (*board_resume_finish)(void __iomem *mbar);
277};
278
279extern struct mpc52xx_suspend mpc52xx_suspend;
280extern int __init mpc52xx_pm_init(void);
281extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
282
283#ifdef CONFIG_PPC_LITE5200
284extern int __init lite5200_pm_init(void);
285
286/* lite5200 calls mpc5200 suspend functions, so here they are */
287extern int mpc52xx_pm_prepare(void);
288extern int mpc52xx_pm_enter(suspend_state_t);
289extern void mpc52xx_pm_finish(void);
290extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
291#endif
292#endif /* CONFIG_PM */
293
294#endif /* __ASM_POWERPC_MPC52xx_H__ */
295
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
new file mode 100644
index 000000000000..8917ed630565
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -0,0 +1,276 @@
1/*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22#ifndef __ASM_MPC52xx_PSC_H__
23#define __ASM_MPC52xx_PSC_H__
24
25#include <asm/types.h>
26
27/* Max number of PSCs */
28#define MPC52xx_PSC_MAXNUM 6
29
30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_CDE 0x0080
32#define MPC52xx_PSC_SR_RXRDY 0x0100
33#define MPC52xx_PSC_SR_RXFULL 0x0200
34#define MPC52xx_PSC_SR_TXRDY 0x0400
35#define MPC52xx_PSC_SR_TXEMP 0x0800
36#define MPC52xx_PSC_SR_OE 0x1000
37#define MPC52xx_PSC_SR_PE 0x2000
38#define MPC52xx_PSC_SR_FE 0x4000
39#define MPC52xx_PSC_SR_RB 0x8000
40
41/* PSC Command values */
42#define MPC52xx_PSC_RX_ENABLE 0x0001
43#define MPC52xx_PSC_RX_DISABLE 0x0002
44#define MPC52xx_PSC_TX_ENABLE 0x0004
45#define MPC52xx_PSC_TX_DISABLE 0x0008
46#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
47#define MPC52xx_PSC_RST_RX 0x0020
48#define MPC52xx_PSC_RST_TX 0x0030
49#define MPC52xx_PSC_RST_ERR_STAT 0x0040
50#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
51#define MPC52xx_PSC_START_BRK 0x0060
52#define MPC52xx_PSC_STOP_BRK 0x0070
53
54/* PSC TxRx FIFO status bits */
55#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
56#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
57#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
58#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
59#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
60#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
61#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
62
63/* PSC interrupt status/mask bits */
64#define MPC52xx_PSC_IMR_TXRDY 0x0100
65#define MPC52xx_PSC_IMR_RXRDY 0x0200
66#define MPC52xx_PSC_IMR_DB 0x0400
67#define MPC52xx_PSC_IMR_TXEMP 0x0800
68#define MPC52xx_PSC_IMR_ORERR 0x1000
69#define MPC52xx_PSC_IMR_IPC 0x8000
70
71/* PSC input port change bit */
72#define MPC52xx_PSC_CTS 0x01
73#define MPC52xx_PSC_DCD 0x02
74#define MPC52xx_PSC_D_CTS 0x10
75#define MPC52xx_PSC_D_DCD 0x20
76
77/* PSC mode fields */
78#define MPC52xx_PSC_MODE_5_BITS 0x00
79#define MPC52xx_PSC_MODE_6_BITS 0x01
80#define MPC52xx_PSC_MODE_7_BITS 0x02
81#define MPC52xx_PSC_MODE_8_BITS 0x03
82#define MPC52xx_PSC_MODE_BITS_MASK 0x03
83#define MPC52xx_PSC_MODE_PAREVEN 0x00
84#define MPC52xx_PSC_MODE_PARODD 0x04
85#define MPC52xx_PSC_MODE_PARFORCE 0x08
86#define MPC52xx_PSC_MODE_PARNONE 0x10
87#define MPC52xx_PSC_MODE_ERR 0x20
88#define MPC52xx_PSC_MODE_FFULL 0x40
89#define MPC52xx_PSC_MODE_RXRTS 0x80
90
91#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
92#define MPC52xx_PSC_MODE_ONE_STOP 0x07
93#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
94
95#define MPC52xx_PSC_RFNUM_MASK 0x01ff
96
97#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
98#define MPC52xx_PSC_SICR_SHDR (1 << 28)
99#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
100#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
101#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
102#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
103#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
104#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
105#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
106#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
107#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
108#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
109#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
110#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
111#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
112#define MPC52xx_PSC_SICR_I2S (1 << 22)
113#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
114#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
115#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
116#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
117#define MPC52xx_PSC_SICR_ESAI (1 << 17)
118#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
119#define MPC52xx_PSC_SICR_SPI (1 << 15)
120#define MPC52xx_PSC_SICR_MSTR (1 << 14)
121#define MPC52xx_PSC_SICR_CPOL (1 << 13)
122#define MPC52xx_PSC_SICR_CPHA (1 << 12)
123#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
124#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
125
126/* Structure of the hardware registers */
127struct mpc52xx_psc {
128 u8 mode; /* PSC + 0x00 */
129 u8 reserved0[3];
130 union { /* PSC + 0x04 */
131 u16 status;
132 u16 clock_select;
133 } sr_csr;
134#define mpc52xx_psc_status sr_csr.status
135#define mpc52xx_psc_clock_select sr_csr.clock_select
136 u16 reserved1;
137 u8 command; /* PSC + 0x08 */
138 u8 reserved2[3];
139 union { /* PSC + 0x0c */
140 u8 buffer_8;
141 u16 buffer_16;
142 u32 buffer_32;
143 } buffer;
144#define mpc52xx_psc_buffer_8 buffer.buffer_8
145#define mpc52xx_psc_buffer_16 buffer.buffer_16
146#define mpc52xx_psc_buffer_32 buffer.buffer_32
147 union { /* PSC + 0x10 */
148 u8 ipcr;
149 u8 acr;
150 } ipcr_acr;
151#define mpc52xx_psc_ipcr ipcr_acr.ipcr
152#define mpc52xx_psc_acr ipcr_acr.acr
153 u8 reserved3[3];
154 union { /* PSC + 0x14 */
155 u16 isr;
156 u16 imr;
157 } isr_imr;
158#define mpc52xx_psc_isr isr_imr.isr
159#define mpc52xx_psc_imr isr_imr.imr
160 u16 reserved4;
161 u8 ctur; /* PSC + 0x18 */
162 u8 reserved5[3];
163 u8 ctlr; /* PSC + 0x1c */
164 u8 reserved6[3];
165 /* BitClkDiv field of CCR is byte swapped in
166 * the hardware for mpc5200/b compatibility */
167 u32 ccr; /* PSC + 0x20 */
168 u32 ac97_slots; /* PSC + 0x24 */
169 u32 ac97_cmd; /* PSC + 0x28 */
170 u32 ac97_data; /* PSC + 0x2c */
171 u8 ivr; /* PSC + 0x30 */
172 u8 reserved8[3];
173 u8 ip; /* PSC + 0x34 */
174 u8 reserved9[3];
175 u8 op1; /* PSC + 0x38 */
176 u8 reserved10[3];
177 u8 op0; /* PSC + 0x3c */
178 u8 reserved11[3];
179 u32 sicr; /* PSC + 0x40 */
180 u8 ircr1; /* PSC + 0x44 */
181 u8 reserved13[3];
182 u8 ircr2; /* PSC + 0x44 */
183 u8 reserved14[3];
184 u8 irsdr; /* PSC + 0x4c */
185 u8 reserved15[3];
186 u8 irmdr; /* PSC + 0x50 */
187 u8 reserved16[3];
188 u8 irfdr; /* PSC + 0x54 */
189 u8 reserved17[3];
190};
191
192struct mpc52xx_psc_fifo {
193 u16 rfnum; /* PSC + 0x58 */
194 u16 reserved18;
195 u16 tfnum; /* PSC + 0x5c */
196 u16 reserved19;
197 u32 rfdata; /* PSC + 0x60 */
198 u16 rfstat; /* PSC + 0x64 */
199 u16 reserved20;
200 u8 rfcntl; /* PSC + 0x68 */
201 u8 reserved21[5];
202 u16 rfalarm; /* PSC + 0x6e */
203 u16 reserved22;
204 u16 rfrptr; /* PSC + 0x72 */
205 u16 reserved23;
206 u16 rfwptr; /* PSC + 0x76 */
207 u16 reserved24;
208 u16 rflrfptr; /* PSC + 0x7a */
209 u16 reserved25;
210 u16 rflwfptr; /* PSC + 0x7e */
211 u32 tfdata; /* PSC + 0x80 */
212 u16 tfstat; /* PSC + 0x84 */
213 u16 reserved26;
214 u8 tfcntl; /* PSC + 0x88 */
215 u8 reserved27[5];
216 u16 tfalarm; /* PSC + 0x8e */
217 u16 reserved28;
218 u16 tfrptr; /* PSC + 0x92 */
219 u16 reserved29;
220 u16 tfwptr; /* PSC + 0x96 */
221 u16 reserved30;
222 u16 tflrfptr; /* PSC + 0x9a */
223 u16 reserved31;
224 u16 tflwfptr; /* PSC + 0x9e */
225};
226
227#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
228#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
229#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
230
231#define MPC512x_PSC_FIFO_EMPTY 0x1
232#define MPC512x_PSC_FIFO_FULL 0x2
233#define MPC512x_PSC_FIFO_ALARM 0x4
234#define MPC512x_PSC_FIFO_URERR 0x8
235#define MPC512x_PSC_FIFO_ORERR 0x01
236#define MPC512x_PSC_FIFO_MEMERROR 0x02
237
238struct mpc512x_psc_fifo {
239 u32 reserved1[10];
240 u32 txcmd; /* PSC + 0x80 */
241 u32 txalarm; /* PSC + 0x84 */
242 u32 txsr; /* PSC + 0x88 */
243 u32 txisr; /* PSC + 0x8c */
244 u32 tximr; /* PSC + 0x90 */
245 u32 txcnt; /* PSC + 0x94 */
246 u32 txptr; /* PSC + 0x98 */
247 u32 txsz; /* PSC + 0x9c */
248 u32 reserved2[7];
249 union {
250 u8 txdata_8;
251 u16 txdata_16;
252 u32 txdata_32;
253 } txdata; /* PSC + 0xbc */
254#define txdata_8 txdata.txdata_8
255#define txdata_16 txdata.txdata_16
256#define txdata_32 txdata.txdata_32
257 u32 rxcmd; /* PSC + 0xc0 */
258 u32 rxalarm; /* PSC + 0xc4 */
259 u32 rxsr; /* PSC + 0xc8 */
260 u32 rxisr; /* PSC + 0xcc */
261 u32 rximr; /* PSC + 0xd0 */
262 u32 rxcnt; /* PSC + 0xd4 */
263 u32 rxptr; /* PSC + 0xd8 */
264 u32 rxsz; /* PSC + 0xdc */
265 u32 reserved3[7];
266 union {
267 u8 rxdata_8;
268 u16 rxdata_16;
269 u32 rxdata_32;
270 } rxdata; /* PSC + 0xfc */
271#define rxdata_8 rxdata.rxdata_8
272#define rxdata_16 rxdata.rxdata_16
273#define rxdata_32 rxdata.rxdata_32
274};
275
276#endif /* __ASM_MPC52xx_PSC_H__ */
diff --git a/arch/powerpc/include/asm/mpc6xx.h b/arch/powerpc/include/asm/mpc6xx.h
new file mode 100644
index 000000000000..effc2291beb2
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc6xx.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_POWERPC_MPC6xx_H
2#define __ASM_POWERPC_MPC6xx_H
3
4void mpc6xx_enter_standby(void);
5
6#endif
diff --git a/arch/powerpc/include/asm/mpc8260.h b/arch/powerpc/include/asm/mpc8260.h
new file mode 100644
index 000000000000..03317e1e6185
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8260.h
@@ -0,0 +1,25 @@
1/*
2 * Since there are many different boards and no standard configuration,
3 * we have a unique include file for each. Rather than change every
4 * file that has to include MPC8260 configuration, they all include
5 * this one and the configuration switching is done here.
6 */
7#ifdef __KERNEL__
8#ifndef __ASM_POWERPC_MPC8260_H__
9#define __ASM_POWERPC_MPC8260_H__
10
11#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
12
13#ifdef CONFIG_8260
14
15#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
16#include <platforms/82xx/pq2ads.h>
17#endif
18
19#ifdef CONFIG_PCI_8260
20#include <platforms/82xx/m82xx_pci.h>
21#endif
22
23#endif /* CONFIG_8260 */
24#endif /* !__ASM_POWERPC_MPC8260_H__ */
25#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mpc86xx.h b/arch/powerpc/include/asm/mpc86xx.h
new file mode 100644
index 000000000000..15f650f987e7
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc86xx.h
@@ -0,0 +1,33 @@
1/*
2 * MPC86xx definitions
3 *
4 * Author: Jeff Brown
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_POWERPC_MPC86xx_H__
16#define __ASM_POWERPC_MPC86xx_H__
17
18#include <asm/mmu.h>
19
20#ifdef CONFIG_PPC_86xx
21
22#define CPU0_BOOT_RELEASE 0x01000000
23#define CPU1_BOOT_RELEASE 0x02000000
24#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
25#define MCM_PORT_CONFIG_OFFSET 0x1010
26
27/* Offset from CCSRBAR */
28#define MPC86xx_MCM_OFFSET (0x00000)
29#define MPC86xx_MCM_SIZE (0x02000)
30
31#endif /* CONFIG_PPC_86xx */
32#endif /* __ASM_POWERPC_MPC86xx_H__ */
33#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mpc8xx.h b/arch/powerpc/include/asm/mpc8xx.h
new file mode 100644
index 000000000000..98f3c4f17328
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8xx.h
@@ -0,0 +1,12 @@
1/* This is the single file included by all MPC8xx build options.
2 * Since there are many different boards and no standard configuration,
3 * we have a unique include file for each. Rather than change every
4 * file that has to include MPC8xx configuration, they all include
5 * this one and the configuration switching is done here.
6 */
7#ifndef __CONFIG_8xx_DEFS
8#define __CONFIG_8xx_DEFS
9
10extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
11
12#endif /* __CONFIG_8xx_DEFS */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
new file mode 100644
index 000000000000..fe566a348a86
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic.h
@@ -0,0 +1,481 @@
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8
9/*
10 * Global registers
11 */
12
13#define MPIC_GREG_BASE 0x01000
14
15#define MPIC_GREG_FEATURE_0 0x00000
16#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
17#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
18#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
19#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
20#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
21#define MPIC_GREG_FEATURE_1 0x00010
22#define MPIC_GREG_GLOBAL_CONF_0 0x00020
23#define MPIC_GREG_GCONF_RESET 0x80000000
24#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
25#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
26#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
27#define MPIC_GREG_GCONF_MCK 0x08000000
28#define MPIC_GREG_GLOBAL_CONF_1 0x00030
29#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
30#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
31#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
32 (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
33#define MPIC_GREG_VENDOR_0 0x00040
34#define MPIC_GREG_VENDOR_1 0x00050
35#define MPIC_GREG_VENDOR_2 0x00060
36#define MPIC_GREG_VENDOR_3 0x00070
37#define MPIC_GREG_VENDOR_ID 0x00080
38#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
39#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
40#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
41#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
42#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
43#define MPIC_GREG_PROCESSOR_INIT 0x00090
44#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
45#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
46#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
47#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
48#define MPIC_GREG_IPI_STRIDE 0x10
49#define MPIC_GREG_SPURIOUS 0x000e0
50#define MPIC_GREG_TIMER_FREQ 0x000f0
51
52/*
53 *
54 * Timer registers
55 */
56#define MPIC_TIMER_BASE 0x01100
57#define MPIC_TIMER_STRIDE 0x40
58
59#define MPIC_TIMER_CURRENT_CNT 0x00000
60#define MPIC_TIMER_BASE_CNT 0x00010
61#define MPIC_TIMER_VECTOR_PRI 0x00020
62#define MPIC_TIMER_DESTINATION 0x00030
63
64/*
65 * Per-Processor registers
66 */
67
68#define MPIC_CPU_THISBASE 0x00000
69#define MPIC_CPU_BASE 0x20000
70#define MPIC_CPU_STRIDE 0x01000
71
72#define MPIC_CPU_IPI_DISPATCH_0 0x00040
73#define MPIC_CPU_IPI_DISPATCH_1 0x00050
74#define MPIC_CPU_IPI_DISPATCH_2 0x00060
75#define MPIC_CPU_IPI_DISPATCH_3 0x00070
76#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
77#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
78#define MPIC_CPU_TASKPRI_MASK 0x0000000f
79#define MPIC_CPU_WHOAMI 0x00090
80#define MPIC_CPU_WHOAMI_MASK 0x0000001f
81#define MPIC_CPU_INTACK 0x000a0
82#define MPIC_CPU_EOI 0x000b0
83#define MPIC_CPU_MCACK 0x000c0
84
85/*
86 * Per-source registers
87 */
88
89#define MPIC_IRQ_BASE 0x10000
90#define MPIC_IRQ_STRIDE 0x00020
91#define MPIC_IRQ_VECTOR_PRI 0x00000
92#define MPIC_VECPRI_MASK 0x80000000
93#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
94#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
95#define MPIC_VECPRI_PRIORITY_SHIFT 16
96#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
97#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
98#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
99#define MPIC_VECPRI_POLARITY_MASK 0x00800000
100#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
101#define MPIC_VECPRI_SENSE_EDGE 0x00000000
102#define MPIC_VECPRI_SENSE_MASK 0x00400000
103#define MPIC_IRQ_DESTINATION 0x00010
104
105#define MPIC_MAX_IRQ_SOURCES 2048
106#define MPIC_MAX_CPUS 32
107#define MPIC_MAX_ISU 32
108
109/*
110 * Tsi108 implementation of MPIC has many differences from the original one
111 */
112
113/*
114 * Global registers
115 */
116
117#define TSI108_GREG_BASE 0x00000
118#define TSI108_GREG_FEATURE_0 0x00000
119#define TSI108_GREG_GLOBAL_CONF_0 0x00004
120#define TSI108_GREG_VENDOR_ID 0x0000c
121#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
122#define TSI108_GREG_IPI_STRIDE 0x0c
123#define TSI108_GREG_SPURIOUS 0x00010
124#define TSI108_GREG_TIMER_FREQ 0x00014
125
126/*
127 * Timer registers
128 */
129#define TSI108_TIMER_BASE 0x0030
130#define TSI108_TIMER_STRIDE 0x10
131#define TSI108_TIMER_CURRENT_CNT 0x00000
132#define TSI108_TIMER_BASE_CNT 0x00004
133#define TSI108_TIMER_VECTOR_PRI 0x00008
134#define TSI108_TIMER_DESTINATION 0x0000c
135
136/*
137 * Per-Processor registers
138 */
139#define TSI108_CPU_BASE 0x00300
140#define TSI108_CPU_STRIDE 0x00040
141#define TSI108_CPU_IPI_DISPATCH_0 0x00200
142#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
143#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
144#define TSI108_CPU_WHOAMI 0xffffffff
145#define TSI108_CPU_INTACK 0x00004
146#define TSI108_CPU_EOI 0x00008
147#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
148
149/*
150 * Per-source registers
151 */
152#define TSI108_IRQ_BASE 0x00100
153#define TSI108_IRQ_STRIDE 0x00008
154#define TSI108_IRQ_VECTOR_PRI 0x00000
155#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
156#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
157#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
158#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
159#define TSI108_VECPRI_SENSE_EDGE 0x00000000
160#define TSI108_VECPRI_POLARITY_MASK 0x01000000
161#define TSI108_VECPRI_SENSE_MASK 0x02000000
162#define TSI108_IRQ_DESTINATION 0x00004
163
164/* weird mpic register indices and mask bits in the HW info array */
165enum {
166 MPIC_IDX_GREG_BASE = 0,
167 MPIC_IDX_GREG_FEATURE_0,
168 MPIC_IDX_GREG_GLOBAL_CONF_0,
169 MPIC_IDX_GREG_VENDOR_ID,
170 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
171 MPIC_IDX_GREG_IPI_STRIDE,
172 MPIC_IDX_GREG_SPURIOUS,
173 MPIC_IDX_GREG_TIMER_FREQ,
174
175 MPIC_IDX_TIMER_BASE,
176 MPIC_IDX_TIMER_STRIDE,
177 MPIC_IDX_TIMER_CURRENT_CNT,
178 MPIC_IDX_TIMER_BASE_CNT,
179 MPIC_IDX_TIMER_VECTOR_PRI,
180 MPIC_IDX_TIMER_DESTINATION,
181
182 MPIC_IDX_CPU_BASE,
183 MPIC_IDX_CPU_STRIDE,
184 MPIC_IDX_CPU_IPI_DISPATCH_0,
185 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
186 MPIC_IDX_CPU_CURRENT_TASK_PRI,
187 MPIC_IDX_CPU_WHOAMI,
188 MPIC_IDX_CPU_INTACK,
189 MPIC_IDX_CPU_EOI,
190 MPIC_IDX_CPU_MCACK,
191
192 MPIC_IDX_IRQ_BASE,
193 MPIC_IDX_IRQ_STRIDE,
194 MPIC_IDX_IRQ_VECTOR_PRI,
195
196 MPIC_IDX_VECPRI_VECTOR_MASK,
197 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
198 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
199 MPIC_IDX_VECPRI_SENSE_LEVEL,
200 MPIC_IDX_VECPRI_SENSE_EDGE,
201 MPIC_IDX_VECPRI_POLARITY_MASK,
202 MPIC_IDX_VECPRI_SENSE_MASK,
203 MPIC_IDX_IRQ_DESTINATION,
204 MPIC_IDX_END
205};
206
207
208#ifdef CONFIG_MPIC_U3_HT_IRQS
209/* Fixup table entry */
210struct mpic_irq_fixup
211{
212 u8 __iomem *base;
213 u8 __iomem *applebase;
214 u32 data;
215 unsigned int index;
216};
217#endif /* CONFIG_MPIC_U3_HT_IRQS */
218
219
220enum mpic_reg_type {
221 mpic_access_mmio_le,
222 mpic_access_mmio_be,
223#ifdef CONFIG_PPC_DCR
224 mpic_access_dcr
225#endif
226};
227
228struct mpic_reg_bank {
229 u32 __iomem *base;
230#ifdef CONFIG_PPC_DCR
231 dcr_host_t dhost;
232#endif /* CONFIG_PPC_DCR */
233};
234
235struct mpic_irq_save {
236 u32 vecprio,
237 dest;
238#ifdef CONFIG_MPIC_U3_HT_IRQS
239 u32 fixup_data;
240#endif
241};
242
243/* The instance data of a given MPIC */
244struct mpic
245{
246 /* The remapper for this MPIC */
247 struct irq_host *irqhost;
248
249 /* The "linux" controller struct */
250 struct irq_chip hc_irq;
251#ifdef CONFIG_MPIC_U3_HT_IRQS
252 struct irq_chip hc_ht_irq;
253#endif
254#ifdef CONFIG_SMP
255 struct irq_chip hc_ipi;
256#endif
257 const char *name;
258 /* Flags */
259 unsigned int flags;
260 /* How many irq sources in a given ISU */
261 unsigned int isu_size;
262 unsigned int isu_shift;
263 unsigned int isu_mask;
264 unsigned int irq_count;
265 /* Number of sources */
266 unsigned int num_sources;
267 /* Number of CPUs */
268 unsigned int num_cpus;
269 /* default senses array */
270 unsigned char *senses;
271 unsigned int senses_count;
272
273 /* vector numbers used for internal sources (ipi/timers) */
274 unsigned int ipi_vecs[4];
275 unsigned int timer_vecs[4];
276
277 /* Spurious vector to program into unused sources */
278 unsigned int spurious_vec;
279
280#ifdef CONFIG_MPIC_U3_HT_IRQS
281 /* The fixup table */
282 struct mpic_irq_fixup *fixups;
283 spinlock_t fixup_lock;
284#endif
285
286 /* Register access method */
287 enum mpic_reg_type reg_type;
288
289 /* The various ioremap'ed bases */
290 struct mpic_reg_bank gregs;
291 struct mpic_reg_bank tmregs;
292 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
293 struct mpic_reg_bank isus[MPIC_MAX_ISU];
294
295 /* Protected sources */
296 unsigned long *protected;
297
298#ifdef CONFIG_MPIC_WEIRD
299 /* Pointer to HW info array */
300 u32 *hw_set;
301#endif
302
303#ifdef CONFIG_PCI_MSI
304 spinlock_t bitmap_lock;
305 unsigned long *hwirq_bitmap;
306#endif
307
308#ifdef CONFIG_MPIC_BROKEN_REGREAD
309 u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
310#endif
311
312 /* link */
313 struct mpic *next;
314
315 struct sys_device sysdev;
316
317#ifdef CONFIG_PM
318 struct mpic_irq_save *save_data;
319#endif
320};
321
322/*
323 * MPIC flags (passed to mpic_alloc)
324 *
325 * The top 4 bits contain an MPIC bhw id that is used to index the
326 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
327 * Note setting any ID (leaving those bits to 0) means standard MPIC
328 */
329
330/* This is the primary controller, only that one has IPIs and
331 * has afinity control. A non-primary MPIC always uses CPU0
332 * registers only
333 */
334#define MPIC_PRIMARY 0x00000001
335
336/* Set this for a big-endian MPIC */
337#define MPIC_BIG_ENDIAN 0x00000002
338/* Broken U3 MPIC */
339#define MPIC_U3_HT_IRQS 0x00000004
340/* Broken IPI registers (autodetected) */
341#define MPIC_BROKEN_IPI 0x00000008
342/* MPIC wants a reset */
343#define MPIC_WANTS_RESET 0x00000010
344/* Spurious vector requires EOI */
345#define MPIC_SPV_EOI 0x00000020
346/* No passthrough disable */
347#define MPIC_NO_PTHROU_DIS 0x00000040
348/* DCR based MPIC */
349#define MPIC_USES_DCR 0x00000080
350/* MPIC has 11-bit vector fields (or larger) */
351#define MPIC_LARGE_VECTORS 0x00000100
352/* Enable delivery of prio 15 interrupts as MCK instead of EE */
353#define MPIC_ENABLE_MCK 0x00000200
354/* Disable bias among target selection, spread interrupts evenly */
355#define MPIC_NO_BIAS 0x00000400
356/* Ignore NIRQS as reported by FRR */
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358
359/* MPIC HW modification ID */
360#define MPIC_REGSET_MASK 0xf0000000
361#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
362#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
363
364#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
365#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
366
367/* Allocate the controller structure and setup the linux irq descs
368 * for the range if interrupts passed in. No HW initialization is
369 * actually performed.
370 *
371 * @phys_addr: physial base address of the MPIC
372 * @flags: flags, see constants above
373 * @isu_size: number of interrupts in an ISU. Use 0 to use a
374 * standard ISU-less setup (aka powermac)
375 * @irq_offset: first irq number to assign to this mpic
376 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
377 * to match the number of sources
378 * @ipi_offset: first irq number to assign to this mpic IPI sources,
379 * used only on primary mpic
380 * @senses: array of sense values
381 * @senses_num: number of entries in the array
382 *
383 * Note about the sense array. If none is passed, all interrupts are
384 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
385 * case they are edge positive (and the array is ignored anyway).
386 * The values in the array start at the first source of the MPIC,
387 * that is senses[0] correspond to linux irq "irq_offset".
388 */
389extern struct mpic *mpic_alloc(struct device_node *node,
390 phys_addr_t phys_addr,
391 unsigned int flags,
392 unsigned int isu_size,
393 unsigned int irq_count,
394 const char *name);
395
396/* Assign ISUs, to call before mpic_init()
397 *
398 * @mpic: controller structure as returned by mpic_alloc()
399 * @isu_num: ISU number
400 * @phys_addr: physical address of the ISU
401 */
402extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
403 phys_addr_t phys_addr);
404
405/* Set default sense codes
406 *
407 * @mpic: controller
408 * @senses: array of sense codes
409 * @count: size of above array
410 *
411 * Optionally provide an array (indexed on hardware interrupt numbers
412 * for this MPIC) of default sense codes for the chip. Those are linux
413 * sense codes IRQ_TYPE_*
414 *
415 * The driver gets ownership of the pointer, don't dispose of it or
416 * anything like that. __init only.
417 */
418extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
419
420
421/* Initialize the controller. After this has been called, none of the above
422 * should be called again for this mpic
423 */
424extern void mpic_init(struct mpic *mpic);
425
426/*
427 * All of the following functions must only be used after the
428 * ISUs have been assigned and the controller fully initialized
429 * with mpic_init()
430 */
431
432
433/* Change the priority of an interrupt. Default is 8 for irqs and
434 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
435 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
436 */
437extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
438
439/* Setup a non-boot CPU */
440extern void mpic_setup_this_cpu(void);
441
442/* Clean up for kexec (or cpu offline or ...) */
443extern void mpic_teardown_this_cpu(int secondary);
444
445/* Get the current cpu priority for this cpu (0..15) */
446extern int mpic_cpu_get_priority(void);
447
448/* Set the current cpu priority for this cpu */
449extern void mpic_cpu_set_priority(int prio);
450
451/* Request IPIs on primary mpic */
452extern void mpic_request_ipis(void);
453
454/* Send an IPI (non offseted number 0..3) */
455extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
456
457/* Send a message (IPI) to a given target (cpu number or MSG_*) */
458void smp_mpic_message_pass(int target, int msg);
459
460/* Unmask a specific virq */
461extern void mpic_unmask_irq(unsigned int irq);
462/* Mask a specific virq */
463extern void mpic_mask_irq(unsigned int irq);
464/* EOI a specific virq */
465extern void mpic_end_irq(unsigned int irq);
466
467/* Fetch interrupt from a given mpic */
468extern unsigned int mpic_get_one_irq(struct mpic *mpic);
469/* This one gets from the primary mpic */
470extern unsigned int mpic_get_irq(void);
471/* Fetch Machine Check interrupt from primary mpic */
472extern unsigned int mpic_get_mcirq(void);
473
474/* Set the EPIC clock ratio */
475void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
476
477/* Enable/Disable EPIC serial interrupt mode */
478void mpic_set_serial_int(struct mpic *mpic, int enable);
479
480#endif /* __KERNEL__ */
481#endif /* _ASM_POWERPC_MPIC_H */
diff --git a/arch/powerpc/include/asm/msgbuf.h b/arch/powerpc/include/asm/msgbuf.h
new file mode 100644
index 000000000000..dd76743c7537
--- /dev/null
+++ b/arch/powerpc/include/asm/msgbuf.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_POWERPC_MSGBUF_H
2#define _ASM_POWERPC_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for the PowerPC architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 */
9
10struct msqid64_ds {
11 struct ipc64_perm msg_perm;
12#ifndef __powerpc64__
13 unsigned int __unused1;
14#endif
15 __kernel_time_t msg_stime; /* last msgsnd time */
16#ifndef __powerpc64__
17 unsigned int __unused2;
18#endif
19 __kernel_time_t msg_rtime; /* last msgrcv time */
20#ifndef __powerpc64__
21 unsigned int __unused3;
22#endif
23 __kernel_time_t msg_ctime; /* last change time */
24 unsigned long msg_cbytes; /* current number of bytes on queue */
25 unsigned long msg_qnum; /* number of messages in queue */
26 unsigned long msg_qbytes; /* max number of bytes on queue */
27 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
28 __kernel_pid_t msg_lrpid; /* last receive pid */
29 unsigned long __unused4;
30 unsigned long __unused5;
31};
32
33#endif /* _ASM_POWERPC_MSGBUF_H */
diff --git a/arch/powerpc/include/asm/mutex.h b/arch/powerpc/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/powerpc/include/asm/mutex.h
@@ -0,0 +1,9 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
new file mode 100644
index 000000000000..efde5ac82f7b
--- /dev/null
+++ b/arch/powerpc/include/asm/nvram.h
@@ -0,0 +1,139 @@
1/*
2 * NVRAM definitions and access functions.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _ASM_POWERPC_NVRAM_H
11#define _ASM_POWERPC_NVRAM_H
12
13#include <linux/errno.h>
14
15#define NVRW_CNT 0x20
16#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
17#define NVRAM_BLOCK_LEN 16
18#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
19#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
20
21#define NVRAM_AS0 0x74
22#define NVRAM_AS1 0x75
23#define NVRAM_DATA 0x77
24
25
26/* RTC Offsets */
27
28#define MOTO_RTC_SECONDS 0x1FF9
29#define MOTO_RTC_MINUTES 0x1FFA
30#define MOTO_RTC_HOURS 0x1FFB
31#define MOTO_RTC_DAY_OF_WEEK 0x1FFC
32#define MOTO_RTC_DAY_OF_MONTH 0x1FFD
33#define MOTO_RTC_MONTH 0x1FFE
34#define MOTO_RTC_YEAR 0x1FFF
35#define MOTO_RTC_CONTROLA 0x1FF8
36#define MOTO_RTC_CONTROLB 0x1FF9
37
38#define NVRAM_SIG_SP 0x02 /* support processor */
39#define NVRAM_SIG_OF 0x50 /* open firmware config */
40#define NVRAM_SIG_FW 0x51 /* general firmware */
41#define NVRAM_SIG_HW 0x52 /* hardware (VPD) */
42#define NVRAM_SIG_FLIP 0x5a /* Apple flip/flop header */
43#define NVRAM_SIG_APPL 0x5f /* Apple "system" (???) */
44#define NVRAM_SIG_SYS 0x70 /* system env vars */
45#define NVRAM_SIG_CFG 0x71 /* config data */
46#define NVRAM_SIG_ELOG 0x72 /* error log */
47#define NVRAM_SIG_VEND 0x7e /* vendor defined */
48#define NVRAM_SIG_FREE 0x7f /* Free space */
49#define NVRAM_SIG_OS 0xa0 /* OS defined */
50#define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */
51
52/* If change this size, then change the size of NVNAME_LEN */
53struct nvram_header {
54 unsigned char signature;
55 unsigned char checksum;
56 unsigned short length;
57 char name[12];
58};
59
60#ifdef __KERNEL__
61
62#include <linux/list.h>
63
64struct nvram_partition {
65 struct list_head partition;
66 struct nvram_header header;
67 unsigned int index;
68};
69
70
71extern int nvram_write_error_log(char * buff, int length,
72 unsigned int err_type, unsigned int err_seq);
73extern int nvram_read_error_log(char * buff, int length,
74 unsigned int * err_type, unsigned int *err_seq);
75extern int nvram_clear_error_log(void);
76extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
77
78extern int pSeries_nvram_init(void);
79
80#ifdef CONFIG_MMIO_NVRAM
81extern int mmio_nvram_init(void);
82#else
83static inline int mmio_nvram_init(void)
84{
85 return -ENODEV;
86}
87#endif
88
89#endif /* __KERNEL__ */
90
91/* PowerMac specific nvram stuffs */
92
93enum {
94 pmac_nvram_OF, /* Open Firmware partition */
95 pmac_nvram_XPRAM, /* MacOS XPRAM partition */
96 pmac_nvram_NR /* MacOS Name Registry partition */
97};
98
99#ifdef __KERNEL__
100/* Return partition offset in nvram */
101extern int pmac_get_partition(int partition);
102
103/* Direct access to XPRAM on PowerMacs */
104extern u8 pmac_xpram_read(int xpaddr);
105extern void pmac_xpram_write(int xpaddr, u8 data);
106
107/* Synchronize NVRAM */
108extern void nvram_sync(void);
109
110/* Normal access to NVRAM */
111extern unsigned char nvram_read_byte(int i);
112extern void nvram_write_byte(unsigned char c, int i);
113#endif
114
115/* Some offsets in XPRAM */
116#define PMAC_XPRAM_MACHINE_LOC 0xe4
117#define PMAC_XPRAM_SOUND_VOLUME 0x08
118
119/* Machine location structure in PowerMac XPRAM */
120struct pmac_machine_location {
121 unsigned int latitude; /* 2+30 bit Fractional number */
122 unsigned int longitude; /* 2+30 bit Fractional number */
123 unsigned int delta; /* mix of GMT delta and DLS */
124};
125
126/*
127 * /dev/nvram ioctls
128 *
129 * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
130 * definitely obsolete. Do not use it if you can avoid it
131 */
132
133#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
134 _IOWR('p', 0x40, int)
135
136#define IOC_NVRAM_GET_OFFSET _IOWR('p', 0x42, int) /* Get NVRAM partition offset */
137#define IOC_NVRAM_SYNC _IO('p', 0x43) /* Sync NVRAM image */
138
139#endif /* _ASM_POWERPC_NVRAM_H */
diff --git a/arch/powerpc/include/asm/of_device.h b/arch/powerpc/include/asm/of_device.h
new file mode 100644
index 000000000000..3c123990ca2e
--- /dev/null
+++ b/arch/powerpc/include/asm/of_device.h
@@ -0,0 +1,31 @@
1#ifndef _ASM_POWERPC_OF_DEVICE_H
2#define _ASM_POWERPC_OF_DEVICE_H
3#ifdef __KERNEL__
4
5#include <linux/device.h>
6#include <linux/of.h>
7
8/*
9 * The of_device is a kind of "base class" that is a superset of
10 * struct device for use by devices attached to an OF node and
11 * probed using OF properties.
12 */
13struct of_device
14{
15 struct device_node *node; /* to be obsoleted */
16 u64 dma_mask; /* DMA mask */
17 struct device dev; /* Generic device interface */
18};
19
20extern struct of_device *of_device_alloc(struct device_node *np,
21 const char *bus_id,
22 struct device *parent);
23
24extern int of_device_uevent(struct device *dev,
25 struct kobj_uevent_env *env);
26
27/* This is just here during the transition */
28#include <linux/of_device.h>
29
30#endif /* __KERNEL__ */
31#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/arch/powerpc/include/asm/of_platform.h b/arch/powerpc/include/asm/of_platform.h
new file mode 100644
index 000000000000..18659ef72139
--- /dev/null
+++ b/arch/powerpc/include/asm/of_platform.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_POWERPC_OF_PLATFORM_H
2#define _ASM_POWERPC_OF_PLATFORM_H
3/*
4 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
5 * <benh@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 */
13
14/* This is just here during the transition */
15#include <linux/of_platform.h>
16
17/* Platform drivers register/unregister */
18static inline int of_register_platform_driver(struct of_platform_driver *drv)
19{
20 return of_register_driver(drv, &of_platform_bus_type);
21}
22static inline void of_unregister_platform_driver(struct of_platform_driver *drv)
23{
24 of_unregister_driver(drv);
25}
26
27/* Platform devices and busses creation */
28extern struct of_device *of_platform_device_create(struct device_node *np,
29 const char *bus_id,
30 struct device *parent);
31/* pseudo "matches" value to not do deep probe */
32#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
33
34extern int of_platform_bus_probe(struct device_node *root,
35 const struct of_device_id *matches,
36 struct device *parent);
37
38extern struct of_device *of_find_device_by_phandle(phandle ph);
39
40extern void of_instantiate_rtc(void);
41
42#endif /* _ASM_POWERPC_OF_PLATFORM_H */
diff --git a/arch/powerpc/include/asm/ohare.h b/arch/powerpc/include/asm/ohare.h
new file mode 100644
index 000000000000..0d030f9dea24
--- /dev/null
+++ b/arch/powerpc/include/asm/ohare.h
@@ -0,0 +1,54 @@
1#ifndef _ASM_POWERPC_OHARE_H
2#define _ASM_POWERPC_OHARE_H
3#ifdef __KERNEL__
4/*
5 * ohare.h: definitions for using the "O'Hare" I/O controller chip.
6 *
7 * Copyright (C) 1997 Paul Mackerras.
8 *
9 * BenH: Changed to match those of heathrow (but not all of them). Please
10 * check if I didn't break anything (especially the media bay).
11 */
12
13/* offset from ohare base for feature control register */
14#define OHARE_MBCR 0x34
15#define OHARE_FCR 0x38
16
17/*
18 * Bits in feature control register.
19 * These were mostly derived by experiment on a powerbook 3400
20 * and may differ for other machines.
21 */
22#define OH_SCC_RESET 1
23#define OH_BAY_POWER_N 2 /* a guess */
24#define OH_BAY_PCI_ENABLE 4 /* a guess */
25#define OH_BAY_IDE_ENABLE 8
26#define OH_BAY_FLOPPY_ENABLE 0x10
27#define OH_IDE0_ENABLE 0x20
28#define OH_IDE0_RESET_N 0x40 /* a guess */
29#define OH_BAY_DEV_MASK 0x1c
30#define OH_BAY_RESET_N 0x80
31#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
32#define OH_SCC_ENABLE 0x200
33#define OH_MESH_ENABLE 0x400
34#define OH_FLOPPY_ENABLE 0x800
35#define OH_SCCA_IO 0x4000
36#define OH_SCCB_IO 0x8000
37#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
38#define OH_IDE1_RESET_N 0x800000
39
40/*
41 * Bits to set in the feature control register on PowerBooks.
42 */
43#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
44 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
45
46/*
47 * A magic value to put into the feature control register of the
48 * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
49 * Contributed by Harry Eaton.
50 */
51#define STARMAX_FEATURES 0xbeff7a
52
53#endif /* __KERNEL__ */
54#endif /* _ASM_POWERPC_OHARE_H */
diff --git a/arch/powerpc/include/asm/oprofile_impl.h b/arch/powerpc/include/asm/oprofile_impl.h
new file mode 100644
index 000000000000..95035c602ba6
--- /dev/null
+++ b/arch/powerpc/include/asm/oprofile_impl.h
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * Based on alpha version.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
13#define _ASM_POWERPC_OPROFILE_IMPL_H
14#ifdef __KERNEL__
15
16#define OP_MAX_COUNTER 8
17
18/* Per-counter configuration as set via oprofilefs. */
19struct op_counter_config {
20 unsigned long enabled;
21 unsigned long event;
22 unsigned long count;
23 /* Classic doesn't support per-counter user/kernel selection */
24 unsigned long kernel;
25 unsigned long user;
26 unsigned long unit_mask;
27};
28
29/* System-wide configuration as set via oprofilefs. */
30struct op_system_config {
31#ifdef CONFIG_PPC64
32 unsigned long mmcr0;
33 unsigned long mmcr1;
34 unsigned long mmcra;
35#endif
36 unsigned long enable_kernel;
37 unsigned long enable_user;
38};
39
40/* Per-arch configuration */
41struct op_powerpc_model {
42 int (*reg_setup) (struct op_counter_config *,
43 struct op_system_config *,
44 int num_counters);
45 int (*cpu_setup) (struct op_counter_config *);
46 int (*start) (struct op_counter_config *);
47 int (*global_start) (struct op_counter_config *);
48 void (*stop) (void);
49 void (*global_stop) (void);
50 int (*sync_start)(void);
51 int (*sync_stop)(void);
52 void (*handle_interrupt) (struct pt_regs *,
53 struct op_counter_config *);
54 int num_counters;
55};
56
57extern struct op_powerpc_model op_model_fsl_emb;
58extern struct op_powerpc_model op_model_rs64;
59extern struct op_powerpc_model op_model_power4;
60extern struct op_powerpc_model op_model_7450;
61extern struct op_powerpc_model op_model_cell;
62extern struct op_powerpc_model op_model_pa6t;
63
64
65/* All the classic PPC parts use these */
66static inline unsigned int classic_ctr_read(unsigned int i)
67{
68 switch(i) {
69 case 0:
70 return mfspr(SPRN_PMC1);
71 case 1:
72 return mfspr(SPRN_PMC2);
73 case 2:
74 return mfspr(SPRN_PMC3);
75 case 3:
76 return mfspr(SPRN_PMC4);
77 case 4:
78 return mfspr(SPRN_PMC5);
79 case 5:
80 return mfspr(SPRN_PMC6);
81
82/* No PPC32 chip has more than 6 so far */
83#ifdef CONFIG_PPC64
84 case 6:
85 return mfspr(SPRN_PMC7);
86 case 7:
87 return mfspr(SPRN_PMC8);
88#endif
89 default:
90 return 0;
91 }
92}
93
94static inline void classic_ctr_write(unsigned int i, unsigned int val)
95{
96 switch(i) {
97 case 0:
98 mtspr(SPRN_PMC1, val);
99 break;
100 case 1:
101 mtspr(SPRN_PMC2, val);
102 break;
103 case 2:
104 mtspr(SPRN_PMC3, val);
105 break;
106 case 3:
107 mtspr(SPRN_PMC4, val);
108 break;
109 case 4:
110 mtspr(SPRN_PMC5, val);
111 break;
112 case 5:
113 mtspr(SPRN_PMC6, val);
114 break;
115
116/* No PPC32 chip has more than 6, yet */
117#ifdef CONFIG_PPC64
118 case 6:
119 mtspr(SPRN_PMC7, val);
120 break;
121 case 7:
122 mtspr(SPRN_PMC8, val);
123 break;
124#endif
125 default:
126 break;
127 }
128}
129
130
131extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
132
133#endif /* __KERNEL__ */
134#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
new file mode 100644
index 000000000000..e482e5352e69
--- /dev/null
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -0,0 +1,29 @@
1#ifndef _PPC64_PSERIES_RECONFIG_H
2#define _PPC64_PSERIES_RECONFIG_H
3#ifdef __KERNEL__
4
5#include <linux/notifier.h>
6
7/*
8 * Use this API if your code needs to know about OF device nodes being
9 * added or removed on pSeries systems.
10 */
11
12#define PSERIES_RECONFIG_ADD 0x0001
13#define PSERIES_RECONFIG_REMOVE 0x0002
14#define PSERIES_DRCONF_MEM_ADD 0x0003
15#define PSERIES_DRCONF_MEM_REMOVE 0x0004
16
17#ifdef CONFIG_PPC_PSERIES
18extern int pSeries_reconfig_notifier_register(struct notifier_block *);
19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
20#else /* !CONFIG_PPC_PSERIES */
21static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
22{
23 return 0;
24}
25static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
26#endif /* CONFIG_PPC_PSERIES */
27
28#endif /* __KERNEL__ */
29#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
new file mode 100644
index 000000000000..6493a395508b
--- /dev/null
+++ b/arch/powerpc/include/asm/paca.h
@@ -0,0 +1,112 @@
1/*
2 * This control block defines the PACA which defines the processor
3 * specific data for each logical processor on the system.
4 * There are some pointers defined that are utilized by PLIC.
5 *
6 * C 2001 PPC 64 Team, IBM Corp
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef _ASM_POWERPC_PACA_H
14#define _ASM_POWERPC_PACA_H
15#ifdef __KERNEL__
16
17#include <asm/types.h>
18#include <asm/lppaca.h>
19#include <asm/mmu.h>
20
21register struct paca_struct *local_paca asm("r13");
22
23#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
24extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
25/*
26 * Add standard checks that preemption cannot occur when using get_paca():
27 * otherwise the paca_struct it points to may be the wrong one just after.
28 */
29#define get_paca() ((void) debug_smp_processor_id(), local_paca)
30#else
31#define get_paca() local_paca
32#endif
33
34#define get_lppaca() (get_paca()->lppaca_ptr)
35#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
36
37struct task_struct;
38
39/*
40 * Defines the layout of the paca.
41 *
42 * This structure is not directly accessed by firmware or the service
43 * processor.
44 */
45struct paca_struct {
46 /*
47 * Because hw_cpu_id, unlike other paca fields, is accessed
48 * routinely from other CPUs (from the IRQ code), we stick to
49 * read-only (after boot) fields in the first cacheline to
50 * avoid cacheline bouncing.
51 */
52
53 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
54
55 /*
56 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
57 * load lock_token and paca_index with a single lwz
58 * instruction. They must travel together and be properly
59 * aligned.
60 */
61 u16 lock_token; /* Constant 0x8000, used in locks */
62 u16 paca_index; /* Logical processor number */
63
64 u64 kernel_toc; /* Kernel TOC address */
65 u64 stab_real; /* Absolute address of segment table */
66 u64 stab_addr; /* Virtual address of segment table */
67 void *emergency_sp; /* pointer to emergency stack */
68 u64 data_offset; /* per cpu data offset */
69 s16 hw_cpu_id; /* Physical processor number */
70 u8 cpu_start; /* At startup, processor spins until */
71 /* this becomes non-zero. */
72 struct slb_shadow *slb_shadow_ptr;
73
74 /*
75 * Now, starting in cacheline 2, the exception save areas
76 */
77 /* used for most interrupts/exceptions */
78 u64 exgen[10] __attribute__((aligned(0x80)));
79 u64 exmc[10]; /* used for machine checks */
80 u64 exslb[10]; /* used for SLB/segment table misses
81 * on the linear mapping */
82
83 mm_context_t context;
84 u16 vmalloc_sllp;
85 u16 slb_cache_ptr;
86 u16 slb_cache[SLB_CACHE_ENTRIES];
87
88 /*
89 * then miscellaneous read-write fields
90 */
91 struct task_struct *__current; /* Pointer to current */
92 u64 kstack; /* Saved Kernel stack addr */
93 u64 stab_rr; /* stab/slb round-robin counter */
94 u64 saved_r1; /* r1 save for RTAS calls */
95 u64 saved_msr; /* MSR saved here by enter_rtas */
96 u16 trap_save; /* Used when bad stack is encountered */
97 u8 soft_enabled; /* irq soft-enable flag */
98 u8 hard_enabled; /* set if irqs are enabled in MSR */
99 u8 io_sync; /* writel() needs spin_unlock sync */
100
101 /* Stuff for accurate time accounting */
102 u64 user_time; /* accumulated usermode TB ticks */
103 u64 system_time; /* accumulated system TB ticks */
104 u64 startpurr; /* PURR/TB value snapshot */
105 u64 startspurr; /* SPURR value snapshot */
106};
107
108extern struct paca_struct paca[];
109extern void initialise_pacas(void);
110
111#endif /* __KERNEL__ */
112#endif /* _ASM_POWERPC_PACA_H */
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
new file mode 100644
index 000000000000..e088545cb3f5
--- /dev/null
+++ b/arch/powerpc/include/asm/page.h
@@ -0,0 +1,225 @@
1#ifndef _ASM_POWERPC_PAGE_H
2#define _ASM_POWERPC_PAGE_H
3
4/*
5 * Copyright (C) 2001,2005 IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/asm-compat.h>
14#include <asm/kdump.h>
15#include <asm/types.h>
16
17/*
18 * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
19 * page size. When using 64K pages however, whether we are really supporting
20 * 64K pages in HW or not is irrelevant to those definitions.
21 */
22#ifdef CONFIG_PPC_64K_PAGES
23#define PAGE_SHIFT 16
24#else
25#define PAGE_SHIFT 12
26#endif
27
28#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT)
29
30/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
31#define __HAVE_ARCH_GATE_AREA 1
32
33/*
34 * Subtle: (1 << PAGE_SHIFT) is an int, not an unsigned long. So if we
35 * assign PAGE_MASK to a larger type it gets extended the way we want
36 * (i.e. with 1s in the high bits)
37 */
38#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
39
40/*
41 * KERNELBASE is the virtual address of the start of the kernel, it's often
42 * the same as PAGE_OFFSET, but _might not be_.
43 *
44 * The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
45 *
46 * PAGE_OFFSET is the virtual address of the start of lowmem.
47 *
48 * PHYSICAL_START is the physical address of the start of the kernel.
49 *
50 * MEMORY_START is the physical address of the start of lowmem.
51 *
52 * KERNELBASE, PAGE_OFFSET, and PHYSICAL_START are all configurable on
53 * ppc32 and based on how they are set we determine MEMORY_START.
54 *
55 * For the linear mapping the following equation should be true:
56 * KERNELBASE - PAGE_OFFSET = PHYSICAL_START - MEMORY_START
57 *
58 * Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
59 *
60 * There are two was to determine a physical address from a virtual one:
61 * va = pa + PAGE_OFFSET - MEMORY_START
62 * va = pa + KERNELBASE - PHYSICAL_START
63 *
64 * If you want to know something's offset from the start of the kernel you
65 * should subtract KERNELBASE.
66 *
67 * If you want to test if something's a kernel address, use is_kernel_addr().
68 */
69
70#define KERNELBASE ASM_CONST(CONFIG_KERNEL_START)
71#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET)
72#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
73
74#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_FLATMEM)
75#ifndef __ASSEMBLY__
76extern phys_addr_t memstart_addr;
77extern phys_addr_t kernstart_addr;
78#endif
79#define PHYSICAL_START kernstart_addr
80#define MEMORY_START memstart_addr
81#else
82#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START)
83#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
84#endif
85
86#ifdef CONFIG_FLATMEM
87#define ARCH_PFN_OFFSET (MEMORY_START >> PAGE_SHIFT)
88#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < (ARCH_PFN_OFFSET + max_mapnr))
89#endif
90
91#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
92#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
93#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
94
95#define __va(x) ((void *)((unsigned long)(x) - PHYSICAL_START + KERNELBASE))
96#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
97
98/*
99 * Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
100 * and needs to be executable. This means the whole heap ends
101 * up being executable.
102 */
103#define VM_DATA_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
104 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
105
106#define VM_DATA_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
107 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
108
109#ifdef __powerpc64__
110#include <asm/page_64.h>
111#else
112#include <asm/page_32.h>
113#endif
114
115/* align addr on a size boundary - adjust address up/down if needed */
116#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1)))
117#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1)))
118
119/* align addr on a size boundary - adjust address up if needed */
120#define _ALIGN(addr,size) _ALIGN_UP(addr,size)
121
122/*
123 * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
124 * "kernelness", use is_kernel_addr() - it should do what you want.
125 */
126#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
127
128#ifndef __ASSEMBLY__
129
130#undef STRICT_MM_TYPECHECKS
131
132#ifdef STRICT_MM_TYPECHECKS
133/* These are used to make use of C type-checking. */
134
135/* PTE level */
136typedef struct { pte_basic_t pte; } pte_t;
137#define pte_val(x) ((x).pte)
138#define __pte(x) ((pte_t) { (x) })
139
140/* 64k pages additionally define a bigger "real PTE" type that gathers
141 * the "second half" part of the PTE for pseudo 64k pages
142 */
143#ifdef CONFIG_PPC_64K_PAGES
144typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
145#else
146typedef struct { pte_t pte; } real_pte_t;
147#endif
148
149/* PMD level */
150#ifdef CONFIG_PPC64
151typedef struct { unsigned long pmd; } pmd_t;
152#define pmd_val(x) ((x).pmd)
153#define __pmd(x) ((pmd_t) { (x) })
154
155/* PUD level exusts only on 4k pages */
156#ifndef CONFIG_PPC_64K_PAGES
157typedef struct { unsigned long pud; } pud_t;
158#define pud_val(x) ((x).pud)
159#define __pud(x) ((pud_t) { (x) })
160#endif /* !CONFIG_PPC_64K_PAGES */
161#endif /* CONFIG_PPC64 */
162
163/* PGD level */
164typedef struct { unsigned long pgd; } pgd_t;
165#define pgd_val(x) ((x).pgd)
166#define __pgd(x) ((pgd_t) { (x) })
167
168/* Page protection bits */
169typedef struct { unsigned long pgprot; } pgprot_t;
170#define pgprot_val(x) ((x).pgprot)
171#define __pgprot(x) ((pgprot_t) { (x) })
172
173#else
174
175/*
176 * .. while these make it easier on the compiler
177 */
178
179typedef pte_basic_t pte_t;
180#define pte_val(x) (x)
181#define __pte(x) (x)
182
183#ifdef CONFIG_PPC_64K_PAGES
184typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
185#else
186typedef unsigned long real_pte_t;
187#endif
188
189
190#ifdef CONFIG_PPC64
191typedef unsigned long pmd_t;
192#define pmd_val(x) (x)
193#define __pmd(x) (x)
194
195#ifndef CONFIG_PPC_64K_PAGES
196typedef unsigned long pud_t;
197#define pud_val(x) (x)
198#define __pud(x) (x)
199#endif /* !CONFIG_PPC_64K_PAGES */
200#endif /* CONFIG_PPC64 */
201
202typedef unsigned long pgd_t;
203#define pgd_val(x) (x)
204#define pgprot_val(x) (x)
205
206typedef unsigned long pgprot_t;
207#define __pgd(x) (x)
208#define __pgprot(x) (x)
209
210#endif
211
212struct page;
213extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
214extern void copy_user_page(void *to, void *from, unsigned long vaddr,
215 struct page *p);
216extern int page_is_ram(unsigned long pfn);
217
218struct vm_area_struct;
219
220typedef struct page *pgtable_t;
221
222#include <asm-generic/memory_model.h>
223#endif /* __ASSEMBLY__ */
224
225#endif /* _ASM_POWERPC_PAGE_H */
diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h
new file mode 100644
index 000000000000..ebfae530a379
--- /dev/null
+++ b/arch/powerpc/include/asm/page_32.h
@@ -0,0 +1,38 @@
1#ifndef _ASM_POWERPC_PAGE_32_H
2#define _ASM_POWERPC_PAGE_32_H
3
4#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
5#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
6#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
7#endif
8#endif
9
10#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
11
12#ifdef CONFIG_NOT_COHERENT_CACHE
13#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
14#endif
15
16#ifndef __ASSEMBLY__
17/*
18 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
19 * physical addressing. For now this just the IBM PPC440.
20 */
21#ifdef CONFIG_PTE_64BIT
22typedef unsigned long long pte_basic_t;
23#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
24#else
25typedef unsigned long pte_basic_t;
26#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
27#endif
28
29struct page;
30extern void clear_pages(void *page, int order);
31static inline void clear_page(void *page) { clear_pages(page, 0); }
32extern void copy_page(void *to, void *from);
33
34#include <asm-generic/page.h>
35
36#endif /* __ASSEMBLY__ */
37
38#endif /* _ASM_POWERPC_PAGE_32_H */
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
new file mode 100644
index 000000000000..043bfdfe4f73
--- /dev/null
+++ b/arch/powerpc/include/asm/page_64.h
@@ -0,0 +1,185 @@
1#ifndef _ASM_POWERPC_PAGE_64_H
2#define _ASM_POWERPC_PAGE_64_H
3
4/*
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13/*
14 * We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
15 * specific, every notion of page number shared with the firmware, TCEs,
16 * iommu, etc... still uses a page size of 4K.
17 */
18#define HW_PAGE_SHIFT 12
19#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
20#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
21
22/*
23 * PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
24 * HW_PAGE_SHIFT, that is 4K pages.
25 */
26#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
27
28/* Segment size; normal 256M segments */
29#define SID_SHIFT 28
30#define SID_MASK ASM_CONST(0xfffffffff)
31#define ESID_MASK 0xfffffffff0000000UL
32#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
33
34/* 1T segments */
35#define SID_SHIFT_1T 40
36#define SID_MASK_1T 0xffffffUL
37#define ESID_MASK_1T 0xffffff0000000000UL
38#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
39
40#ifndef __ASSEMBLY__
41#include <asm/cache.h>
42
43typedef unsigned long pte_basic_t;
44
45static __inline__ void clear_page(void *addr)
46{
47 unsigned long lines, line_size;
48
49 line_size = ppc64_caches.dline_size;
50 lines = ppc64_caches.dlines_per_page;
51
52 __asm__ __volatile__(
53 "mtctr %1 # clear_page\n\
541: dcbz 0,%0\n\
55 add %0,%0,%3\n\
56 bdnz+ 1b"
57 : "=r" (addr)
58 : "r" (lines), "0" (addr), "r" (line_size)
59 : "ctr", "memory");
60}
61
62extern void copy_4K_page(void *to, void *from);
63
64#ifdef CONFIG_PPC_64K_PAGES
65static inline void copy_page(void *to, void *from)
66{
67 unsigned int i;
68 for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
69 copy_4K_page(to, from);
70 to += 4096;
71 from += 4096;
72 }
73}
74#else /* CONFIG_PPC_64K_PAGES */
75static inline void copy_page(void *to, void *from)
76{
77 copy_4K_page(to, from);
78}
79#endif /* CONFIG_PPC_64K_PAGES */
80
81/* Log 2 of page table size */
82extern u64 ppc64_pft_size;
83
84/* Large pages size */
85#ifdef CONFIG_HUGETLB_PAGE
86extern unsigned int HPAGE_SHIFT;
87#else
88#define HPAGE_SHIFT PAGE_SHIFT
89#endif
90#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
91#define HPAGE_MASK (~(HPAGE_SIZE - 1))
92#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
93#define HUGE_MAX_HSTATE 3
94
95#endif /* __ASSEMBLY__ */
96
97#ifdef CONFIG_PPC_MM_SLICES
98
99#define SLICE_LOW_SHIFT 28
100#define SLICE_HIGH_SHIFT 40
101
102#define SLICE_LOW_TOP (0x100000000ul)
103#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
104#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
105
106#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
107#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
108
109#ifndef __ASSEMBLY__
110
111struct slice_mask {
112 u16 low_slices;
113 u16 high_slices;
114};
115
116struct mm_struct;
117
118extern unsigned long slice_get_unmapped_area(unsigned long addr,
119 unsigned long len,
120 unsigned long flags,
121 unsigned int psize,
122 int topdown,
123 int use_cache);
124
125extern unsigned int get_slice_psize(struct mm_struct *mm,
126 unsigned long addr);
127
128extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
129extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
130extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
131 unsigned long len, unsigned int psize);
132
133#define slice_mm_new_context(mm) ((mm)->context.id == 0)
134
135#endif /* __ASSEMBLY__ */
136#else
137#define slice_init()
138#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
139#define slice_set_user_psize(mm, psize) \
140do { \
141 (mm)->context.user_psize = (psize); \
142 (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
143} while (0)
144#define slice_set_range_psize(mm, start, len, psize) \
145 slice_set_user_psize((mm), (psize))
146#define slice_mm_new_context(mm) 1
147#endif /* CONFIG_PPC_MM_SLICES */
148
149#ifdef CONFIG_HUGETLB_PAGE
150
151#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
152
153#endif /* !CONFIG_HUGETLB_PAGE */
154
155#ifdef MODULE
156#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
157#else
158#define __page_aligned \
159 __attribute__((__aligned__(PAGE_SIZE), \
160 __section__(".data.page_aligned")))
161#endif
162
163#define VM_DATA_DEFAULT_FLAGS \
164 (test_thread_flag(TIF_32BIT) ? \
165 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
166
167/*
168 * This is the default if a program doesn't have a PT_GNU_STACK
169 * program header entry. The PPC64 ELF ABI has a non executable stack
170 * stack by default, so in the absense of a PT_GNU_STACK program header
171 * we turn execute permission off.
172 */
173#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
174 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
175
176#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
177 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
178
179#define VM_STACK_DEFAULT_FLAGS \
180 (test_thread_flag(TIF_32BIT) ? \
181 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
182
183#include <asm-generic/page.h>
184
185#endif /* _ASM_POWERPC_PAGE_64_H */
diff --git a/arch/powerpc/include/asm/param.h b/arch/powerpc/include/asm/param.h
new file mode 100644
index 000000000000..094f63d4d5ca
--- /dev/null
+++ b/arch/powerpc/include/asm/param.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_POWERPC_PARAM_H
2#define _ASM_POWERPC_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ /* internal kernel timer frequency */
6#define USER_HZ 100 /* for user interfaces in "ticks" */
7#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
8#endif /* __KERNEL__ */
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _ASM_POWERPC_PARAM_H */
diff --git a/arch/powerpc/include/asm/parport.h b/arch/powerpc/include/asm/parport.h
new file mode 100644
index 000000000000..414c50e2e881
--- /dev/null
+++ b/arch/powerpc/include/asm/parport.h
@@ -0,0 +1,39 @@
1/*
2 * parport.h: platform-specific PC-style parport initialisation
3 *
4 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
5 *
6 * This file should only be included by drivers/parport/parport_pc.c.
7 */
8
9#ifndef _ASM_POWERPC_PARPORT_H
10#define _ASM_POWERPC_PARPORT_H
11#ifdef __KERNEL__
12
13#include <asm/prom.h>
14
15static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
16{
17 struct device_node *np;
18 const u32 *prop;
19 u32 io1, io2;
20 int propsize;
21 int count = 0;
22 for (np = NULL; (np = of_find_compatible_node(np,
23 "parallel",
24 "pnpPNP,400")) != NULL;) {
25 prop = of_get_property(np, "reg", &propsize);
26 if (!prop || propsize > 6*sizeof(u32))
27 continue;
28 io1 = prop[1]; io2 = prop[2];
29 prop = of_get_property(np, "interrupts", NULL);
30 if (!prop)
31 continue;
32 if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL) != NULL)
33 count++;
34 }
35 return count;
36}
37
38#endif /* __KERNEL__ */
39#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/arch/powerpc/include/asm/pasemi_dma.h b/arch/powerpc/include/asm/pasemi_dma.h
new file mode 100644
index 000000000000..19fd7933e2d9
--- /dev/null
+++ b/arch/powerpc/include/asm/pasemi_dma.h
@@ -0,0 +1,538 @@
1/*
2 * Copyright (C) 2006-2008 PA Semi, Inc
3 *
4 * Hardware register layout and descriptor formats for the on-board
5 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
6 * drivers.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef ASM_PASEMI_DMA_H
23#define ASM_PASEMI_DMA_H
24
25/* status register layout in IOB region, at 0xfb800000 */
26struct pasdma_status {
27 u64 rx_sta[64]; /* RX channel status */
28 u64 tx_sta[20]; /* TX channel status */
29};
30
31
32/* All these registers live in the PCI configuration space for the DMA PCI
33 * device. Use the normal PCI config access functions for them.
34 */
35enum {
36 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
37 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
38 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
39 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
40 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
41 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
42 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
43 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
44 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
45 PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */
46 PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */
47 PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */
48};
49
50
51#define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
52#define PAS_DMA_CAP_TXCH_TCHN_S 16
53
54#define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
55#define PAS_DMA_CAP_RXCH_RCHN_S 16
56
57#define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */
58#define PAS_DMA_CAP_IFI_IOFF_S 24
59#define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */
60#define PAS_DMA_CAP_IFI_NIN_S 16
61
62#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
63#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
64#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
65#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
66
67
68/* Per-interface and per-channel registers */
69#define _PAS_DMA_RXINT_STRIDE 0x20
70#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
71#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
72#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
73#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
74#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
75#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
76#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
77#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
78#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
79#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
80#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
81#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
82#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
83#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
84#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
85#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
86#define PAS_DMA_RXINT_CFG_RBP 0x80000000
87#define PAS_DMA_RXINT_CFG_ITRR 0x40000000
88#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
89#define PAS_DMA_RXINT_CFG_DHL_S 24
90#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
91 PAS_DMA_RXINT_CFG_DHL_M)
92#define PAS_DMA_RXINT_CFG_ITR 0x00400000
93#define PAS_DMA_RXINT_CFG_LW 0x00200000
94#define PAS_DMA_RXINT_CFG_L2 0x00100000
95#define PAS_DMA_RXINT_CFG_HEN 0x00080000
96#define PAS_DMA_RXINT_CFG_WIF 0x00000002
97#define PAS_DMA_RXINT_CFG_WIL 0x00000001
98
99#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
100#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
101#define PAS_DMA_RXINT_INCR_INCR_S 0
102#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
103#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
104#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
105#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
106#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
107#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
108#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
109#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
110 PAS_DMA_RXINT_BASEU_SIZ_M)
111
112
113#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
114#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
115#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
116#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
117#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
118#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
119#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
120#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
121#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
122#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
123#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
124#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
125#define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800
126#define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400
127#define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200
128#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
129#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
130#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
131#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
132#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
133#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
134#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
135#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
136#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
137 PAS_DMA_TXCHAN_CFG_TATTR_M)
138#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
139#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
140#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
141#define PAS_DMA_TXCHAN_CFG_WT_S 6
142#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
143 PAS_DMA_TXCHAN_CFG_WT_M)
144#define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */
145#define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */
146#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
147#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
148#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
149#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
150#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
151#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
152#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
153#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
154 PAS_DMA_TXCHAN_BASEL_BRBL_M)
155#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
156#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
157#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
158#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
159 PAS_DMA_TXCHAN_BASEU_BRBH_M)
160/* # of cache lines worth of buffer ring */
161#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
162#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
163#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
164 PAS_DMA_TXCHAN_BASEU_SIZ_M)
165
166#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
167#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
168#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
169#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
170#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
171#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
172#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
173#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
174#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
175#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
176#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
177#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
178#define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000
179#define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000
180#define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800
181#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
182#define PAS_DMA_RXCHAN_CFG_CTR 0x00000400
183#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
184#define PAS_DMA_RXCHAN_CFG_HBU_S 7
185#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
186 PAS_DMA_RXCHAN_CFG_HBU_M)
187#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
188#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
189#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
190#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
191#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
192 PAS_DMA_RXCHAN_BASEL_BRBL_M)
193#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
194#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
195#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
196#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
197 PAS_DMA_RXCHAN_BASEU_BRBH_M)
198/* # of cache lines worth of buffer ring */
199#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
200#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
201#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
202 PAS_DMA_RXCHAN_BASEU_SIZ_M)
203
204#define PAS_STATUS_PCNT_M 0x000000000000ffffull
205#define PAS_STATUS_PCNT_S 0
206#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
207#define PAS_STATUS_DCNT_S 16
208#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
209#define PAS_STATUS_BPCNT_S 32
210#define PAS_STATUS_CAUSE_M 0xf000000000000000ull
211#define PAS_STATUS_TIMER 0x1000000000000000ull
212#define PAS_STATUS_ERROR 0x2000000000000000ull
213#define PAS_STATUS_SOFT 0x4000000000000000ull
214#define PAS_STATUS_INT 0x8000000000000000ull
215
216#define PAS_IOB_COM_PKTHDRCNT 0x120
217#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000
218#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16
219#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff
220#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0
221
222#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
223#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
224#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
225#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
226 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
227#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
228#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
229#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
230#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
231 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
232#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
233#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
234#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
235#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
236#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
237 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
238#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
239#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
240#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
241#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
242#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
243 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
244#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
245#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
246#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
247#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
248 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
249#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
250#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
251#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
252#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
253#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
254#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
255#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
256#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
257#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
258#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
259 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
260#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
261#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
262#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
263#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
264#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
265#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
266
267#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
268#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
269#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
270#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
271 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
272
273/* Transmit descriptor fields */
274#define XCT_MACTX_T 0x8000000000000000ull
275#define XCT_MACTX_ST 0x4000000000000000ull
276#define XCT_MACTX_NORES 0x0000000000000000ull
277#define XCT_MACTX_8BRES 0x1000000000000000ull
278#define XCT_MACTX_24BRES 0x2000000000000000ull
279#define XCT_MACTX_40BRES 0x3000000000000000ull
280#define XCT_MACTX_I 0x0800000000000000ull
281#define XCT_MACTX_O 0x0400000000000000ull
282#define XCT_MACTX_E 0x0200000000000000ull
283#define XCT_MACTX_VLAN_M 0x0180000000000000ull
284#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
285#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
286#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
287#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
288#define XCT_MACTX_CRC_M 0x0060000000000000ull
289#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
290#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
291#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
292#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
293#define XCT_MACTX_SS 0x0010000000000000ull
294#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
295#define XCT_MACTX_LLEN_S 32ull
296#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
297 XCT_MACTX_LLEN_M)
298#define XCT_MACTX_IPH_M 0x00000000f8000000ull
299#define XCT_MACTX_IPH_S 27ull
300#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
301 XCT_MACTX_IPH_M)
302#define XCT_MACTX_IPO_M 0x0000000007c00000ull
303#define XCT_MACTX_IPO_S 22ull
304#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
305 XCT_MACTX_IPO_M)
306#define XCT_MACTX_CSUM_M 0x0000000000000060ull
307#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
308#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
309#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
310#define XCT_MACTX_V6 0x0000000000000010ull
311#define XCT_MACTX_C 0x0000000000000004ull
312#define XCT_MACTX_AL2 0x0000000000000002ull
313
314/* Receive descriptor fields */
315#define XCT_MACRX_T 0x8000000000000000ull
316#define XCT_MACRX_ST 0x4000000000000000ull
317#define XCT_MACRX_RR_M 0x3000000000000000ull
318#define XCT_MACRX_RR_NORES 0x0000000000000000ull
319#define XCT_MACRX_RR_8BRES 0x1000000000000000ull
320#define XCT_MACRX_O 0x0400000000000000ull
321#define XCT_MACRX_E 0x0200000000000000ull
322#define XCT_MACRX_FF 0x0100000000000000ull
323#define XCT_MACRX_PF 0x0080000000000000ull
324#define XCT_MACRX_OB 0x0040000000000000ull
325#define XCT_MACRX_OD 0x0020000000000000ull
326#define XCT_MACRX_FS 0x0010000000000000ull
327#define XCT_MACRX_NB_M 0x000fc00000000000ull
328#define XCT_MACRX_NB_S 46ULL
329#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
330 XCT_MACRX_NB_M)
331#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
332#define XCT_MACRX_LLEN_S 32ULL
333#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
334 XCT_MACRX_LLEN_M)
335#define XCT_MACRX_CRC 0x0000000080000000ull
336#define XCT_MACRX_LEN_M 0x0000000060000000ull
337#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
338#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
339#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
340#define XCT_MACRX_CAST_M 0x0000000018000000ull
341#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
342#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
343#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
344#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
345#define XCT_MACRX_VLC_M 0x0000000006000000ull
346#define XCT_MACRX_FM 0x0000000001000000ull
347#define XCT_MACRX_HTY_M 0x0000000000c00000ull
348#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
349#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
350#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
351#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
352#define XCT_MACRX_IPP_M 0x00000000003f0000ull
353#define XCT_MACRX_IPP_S 16
354#define XCT_MACRX_CSUM_M 0x000000000000ffffull
355#define XCT_MACRX_CSUM_S 0
356
357#define XCT_PTR_T 0x8000000000000000ull
358#define XCT_PTR_LEN_M 0x7ffff00000000000ull
359#define XCT_PTR_LEN_S 44
360#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
361 XCT_PTR_LEN_M)
362#define XCT_PTR_ADDR_M 0x00000fffffffffffull
363#define XCT_PTR_ADDR_S 0
364#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
365 XCT_PTR_ADDR_M)
366
367/* Receive interface 8byte result fields */
368#define XCT_RXRES_8B_L4O_M 0xff00000000000000ull
369#define XCT_RXRES_8B_L4O_S 56
370#define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull
371#define XCT_RXRES_8B_RULE_S 40
372#define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull
373#define XCT_RXRES_8B_EVAL_S 24
374#define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull
375#define XCT_RXRES_8B_HASH_M 0x00000000000fffffull
376#define XCT_RXRES_8B_HASH_S 0
377
378/* Receive interface buffer fields */
379#define XCT_RXB_LEN_M 0x0ffff00000000000ull
380#define XCT_RXB_LEN_S 44
381#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \
382 XCT_RXB_LEN_M)
383#define XCT_RXB_ADDR_M 0x00000fffffffffffull
384#define XCT_RXB_ADDR_S 0
385#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \
386 XCT_RXB_ADDR_M)
387
388/* Copy descriptor fields */
389#define XCT_COPY_T 0x8000000000000000ull
390#define XCT_COPY_ST 0x4000000000000000ull
391#define XCT_COPY_RR_M 0x3000000000000000ull
392#define XCT_COPY_RR_NORES 0x0000000000000000ull
393#define XCT_COPY_RR_8BRES 0x1000000000000000ull
394#define XCT_COPY_RR_24BRES 0x2000000000000000ull
395#define XCT_COPY_RR_40BRES 0x3000000000000000ull
396#define XCT_COPY_I 0x0800000000000000ull
397#define XCT_COPY_O 0x0400000000000000ull
398#define XCT_COPY_E 0x0200000000000000ull
399#define XCT_COPY_STY_ZERO 0x01c0000000000000ull
400#define XCT_COPY_DTY_PREF 0x0038000000000000ull
401#define XCT_COPY_LLEN_M 0x0007ffff00000000ull
402#define XCT_COPY_LLEN_S 32
403#define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \
404 XCT_COPY_LLEN_M)
405#define XCT_COPY_SE 0x0000000000000001ull
406
407/* Function descriptor fields */
408#define XCT_FUN_T 0x8000000000000000ull
409#define XCT_FUN_ST 0x4000000000000000ull
410#define XCT_FUN_RR_M 0x3000000000000000ull
411#define XCT_FUN_RR_NORES 0x0000000000000000ull
412#define XCT_FUN_RR_8BRES 0x1000000000000000ull
413#define XCT_FUN_RR_24BRES 0x2000000000000000ull
414#define XCT_FUN_RR_40BRES 0x3000000000000000ull
415#define XCT_FUN_I 0x0800000000000000ull
416#define XCT_FUN_O 0x0400000000000000ull
417#define XCT_FUN_E 0x0200000000000000ull
418#define XCT_FUN_FUN_M 0x01c0000000000000ull
419#define XCT_FUN_FUN_S 54
420#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
421#define XCT_FUN_CRM_M 0x0038000000000000ull
422#define XCT_FUN_CRM_NOP 0x0000000000000000ull
423#define XCT_FUN_CRM_SIG 0x0008000000000000ull
424#define XCT_FUN_LLEN_M 0x0007ffff00000000ull
425#define XCT_FUN_LLEN_S 32
426#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
427#define XCT_FUN_SHL_M 0x00000000f8000000ull
428#define XCT_FUN_SHL_S 27
429#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
430#define XCT_FUN_CHL_M 0x0000000007c00000ull
431#define XCT_FUN_HSZ_M 0x00000000003c0000ull
432#define XCT_FUN_ALG_M 0x0000000000038000ull
433#define XCT_FUN_HP 0x0000000000004000ull
434#define XCT_FUN_BCM_M 0x0000000000003800ull
435#define XCT_FUN_BCP_M 0x0000000000000600ull
436#define XCT_FUN_SIG_M 0x00000000000001f0ull
437#define XCT_FUN_SIG_TCP4 0x0000000000000140ull
438#define XCT_FUN_SIG_TCP6 0x0000000000000150ull
439#define XCT_FUN_SIG_UDP4 0x0000000000000160ull
440#define XCT_FUN_SIG_UDP6 0x0000000000000170ull
441#define XCT_FUN_A 0x0000000000000008ull
442#define XCT_FUN_C 0x0000000000000004ull
443#define XCT_FUN_AL2 0x0000000000000002ull
444#define XCT_FUN_SE 0x0000000000000001ull
445
446/* Function descriptor 8byte result fields */
447#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
448#define XCT_FUNRES_8B_CS_S 32
449#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
450#define XCT_FUNRES_8B_CRC_S 0
451
452/* Control descriptor fields */
453#define CTRL_CMD_T 0x8000000000000000ull
454#define CTRL_CMD_META_EVT 0x2000000000000000ull
455#define CTRL_CMD_O 0x0400000000000000ull
456#define CTRL_CMD_ETYPE_M 0x0038000000000000ull
457#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
458#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
459#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
460#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
461#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
462#define CTRL_CMD_REG_M 0x000000000000007full
463#define CTRL_CMD_REG_S 0
464#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
465 CTRL_CMD_REG_M)
466
467
468
469/* Prototypes for the shared DMA functions in the platform code. */
470
471/* DMA TX Channel type. Right now only limitations used are event types 0/1,
472 * for event-triggered DMA transactions.
473 */
474
475enum pasemi_dmachan_type {
476 RXCHAN = 0, /* Any RX chan */
477 TXCHAN = 1, /* Any TX chan */
478 TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */
479 TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */
480};
481
482struct pasemi_dmachan {
483 int chno; /* Channel number */
484 enum pasemi_dmachan_type chan_type; /* TX / RX */
485 u64 *status; /* Ptr to cacheable status */
486 int irq; /* IRQ used by channel */
487 unsigned int ring_size; /* size of allocated ring */
488 dma_addr_t ring_dma; /* DMA address for ring */
489 u64 *ring_virt; /* Virt address for ring */
490 void *priv; /* Ptr to start of client struct */
491};
492
493/* Read/write the different registers in the I/O Bridge, Ethernet
494 * and DMA Controller
495 */
496extern unsigned int pasemi_read_iob_reg(unsigned int reg);
497extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
498
499extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
500extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
501
502extern unsigned int pasemi_read_dma_reg(unsigned int reg);
503extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
504
505/* Channel management routines */
506
507extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
508 int total_size, int offset);
509extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
510
511extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
512 const u32 cmdsta);
513extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
514
515/* Common routines to allocate rings and buffers */
516
517extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
518extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
519
520extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
521 dma_addr_t *handle);
522extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
523 dma_addr_t *handle);
524
525/* Routines to allocate flags (events) for channel syncronization */
526extern int pasemi_dma_alloc_flag(void);
527extern void pasemi_dma_free_flag(int flag);
528extern void pasemi_dma_set_flag(int flag);
529extern void pasemi_dma_clear_flag(int flag);
530
531/* Routines to allocate function engines */
532extern int pasemi_dma_alloc_fun(void);
533extern void pasemi_dma_free_fun(int fun);
534
535/* Initialize the library, must be called before any other functions */
536extern int pasemi_dma_init(void);
537
538#endif /* ASM_PASEMI_DMA_H */
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
new file mode 100644
index 000000000000..ae2ea803a0f2
--- /dev/null
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -0,0 +1,302 @@
1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#include <linux/pci.h>
11#include <linux/list.h>
12#include <linux/ioport.h>
13
14struct device_node;
15
16extern unsigned int ppc_pci_flags;
17enum {
18 /* Force re-assigning all resources (ignore firmware
19 * setup completely)
20 */
21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22
23 /* Re-assign all bus numbers */
24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25
26 /* Do not try to assign, just use existing setup */
27 PPC_PCI_PROBE_ONLY = 0x00000004,
28
29 /* Don't bother with ISA alignment unless the bridge has
30 * ISA forwarding enabled
31 */
32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33
34 /* Enable domain numbers in /proc */
35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
36 /* ... except for domain 0 */
37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
38};
39
40
41/*
42 * Structure of a PCI controller (host bridge)
43 */
44struct pci_controller {
45 struct pci_bus *bus;
46 char is_dynamic;
47#ifdef CONFIG_PPC64
48 int node;
49#endif
50 struct device_node *dn;
51 struct list_head list_node;
52 struct device *parent;
53
54 int first_busno;
55 int last_busno;
56#ifndef CONFIG_PPC64
57 int self_busno;
58#endif
59
60 void __iomem *io_base_virt;
61#ifdef CONFIG_PPC64
62 void *io_base_alloc;
63#endif
64 resource_size_t io_base_phys;
65#ifndef CONFIG_PPC64
66 resource_size_t pci_io_size;
67#endif
68
69 /* Some machines (PReP) have a non 1:1 mapping of
70 * the PCI memory space in the CPU bus space
71 */
72 resource_size_t pci_mem_offset;
73#ifdef CONFIG_PPC64
74 unsigned long pci_io_size;
75#endif
76
77 struct pci_ops *ops;
78 unsigned int __iomem *cfg_addr;
79 void __iomem *cfg_data;
80
81#ifndef CONFIG_PPC64
82 /*
83 * Used for variants of PCI indirect handling and possible quirks:
84 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
85 * EXT_REG - provides access to PCI-e extended registers
86 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
87 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
88 * to determine which bus number to match on when generating type0
89 * config cycles
90 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
91 * hanging if we don't have link and try to do config cycles to
92 * anything but the PHB. Only allow talking to the PHB if this is
93 * set.
94 * BIG_ENDIAN - cfg_addr is a big endian register
95 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
96 * the PLB4. Effectively disable MRM commands by setting this.
97 */
98#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
99#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
100#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
101#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
102#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
103#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
104 u32 indirect_type;
105#endif /* !CONFIG_PPC64 */
106 /* Currently, we limit ourselves to 1 IO range and 3 mem
107 * ranges since the common pci_bus structure can't handle more
108 */
109 struct resource io_resource;
110 struct resource mem_resources[3];
111 int global_number; /* PCI domain number */
112#ifdef CONFIG_PPC64
113 unsigned long buid;
114 unsigned long dma_window_base_cur;
115 unsigned long dma_window_size;
116
117 void *private_data;
118#endif /* CONFIG_PPC64 */
119};
120
121#ifndef CONFIG_PPC64
122
123static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
124{
125 return bus->sysdata;
126}
127
128static inline int isa_vaddr_is_ioport(void __iomem *address)
129{
130 /* No specific ISA handling on ppc32 at this stage, it
131 * all goes through PCI
132 */
133 return 0;
134}
135
136/* These are used for config access before all the PCI probing
137 has been done. */
138extern int early_read_config_byte(struct pci_controller *hose, int bus,
139 int dev_fn, int where, u8 *val);
140extern int early_read_config_word(struct pci_controller *hose, int bus,
141 int dev_fn, int where, u16 *val);
142extern int early_read_config_dword(struct pci_controller *hose, int bus,
143 int dev_fn, int where, u32 *val);
144extern int early_write_config_byte(struct pci_controller *hose, int bus,
145 int dev_fn, int where, u8 val);
146extern int early_write_config_word(struct pci_controller *hose, int bus,
147 int dev_fn, int where, u16 val);
148extern int early_write_config_dword(struct pci_controller *hose, int bus,
149 int dev_fn, int where, u32 val);
150
151extern int early_find_capability(struct pci_controller *hose, int bus,
152 int dev_fn, int cap);
153
154extern void setup_indirect_pci(struct pci_controller* hose,
155 resource_size_t cfg_addr,
156 resource_size_t cfg_data, u32 flags);
157extern void setup_grackle(struct pci_controller *hose);
158#else /* CONFIG_PPC64 */
159
160/*
161 * PCI stuff, for nodes representing PCI devices, pointed to
162 * by device_node->data.
163 */
164struct iommu_table;
165
166struct pci_dn {
167 int busno; /* pci bus number */
168 int devfn; /* pci device and function number */
169
170 struct pci_controller *phb; /* for pci devices */
171 struct iommu_table *iommu_table; /* for phb's or bridges */
172 struct device_node *node; /* back-pointer to the device_node */
173
174 int pci_ext_config_space; /* for pci devices */
175
176#ifdef CONFIG_EEH
177 struct pci_dev *pcidev; /* back-pointer to the pci device */
178 int class_code; /* pci device class */
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */
186#endif
187};
188
189/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191
192extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193
194/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed
196 * up (this will only happen once).
197 * In this case the sysdata will have been inherited from a PCI host
198 * bridge or a PCI-PCI bridge further up the tree, so it will point
199 * to a valid struct pci_dn, just not the one we want.
200 */
201static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
202{
203 struct device_node *dn = dev->sysdata;
204 struct pci_dn *pdn = dn->data;
205
206 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
207 return dn; /* fast path. sysdata is good */
208 return fetch_dev_dn(dev);
209}
210
211static inline int pci_device_from_OF_node(struct device_node *np,
212 u8 *bus, u8 *devfn)
213{
214 if (!PCI_DN(np))
215 return -ENODEV;
216 *bus = PCI_DN(np)->busno;
217 *devfn = PCI_DN(np)->devfn;
218 return 0;
219}
220
221static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
222{
223 if (bus->self)
224 return pci_device_to_OF_node(bus->self);
225 else
226 return bus->sysdata; /* Must be root bus (PHB) */
227}
228
229/** Find the bus corresponding to the indicated device node */
230extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231
232/** Remove all of the PCI devices under this bus */
233extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234
235/** Discover new pci devices under this bus, and add them */
236extern void pcibios_add_pci_devices(struct pci_bus *bus);
237extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
238
239extern int pcibios_remove_root_bus(struct pci_controller *phb);
240
241static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
242{
243 struct device_node *busdn = bus->sysdata;
244
245 BUG_ON(busdn == NULL);
246 return PCI_DN(busdn)->phb;
247}
248
249
250extern void isa_bridge_find_early(struct pci_controller *hose);
251
252static inline int isa_vaddr_is_ioport(void __iomem *address)
253{
254 /* Check if address hits the reserved legacy IO range */
255 unsigned long ea = (unsigned long)address;
256 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
257}
258
259extern int pcibios_unmap_io_space(struct pci_bus *bus);
260extern int pcibios_map_io_space(struct pci_bus *bus);
261
262/* Return values for ppc_md.pci_probe_mode function */
263#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
264#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
265#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
266
267#ifdef CONFIG_NUMA
268#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
269#else
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif
272
273#endif /* CONFIG_PPC64 */
274
275/* Get the PCI host controller for an OF device */
276extern struct pci_controller *pci_find_hose_for_OF_device(
277 struct device_node* node);
278
279/* Fill up host controller resources from the OF node */
280extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281 struct device_node *dev, int primary);
282
283/* Allocate & free a PCI host bridge structure */
284extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
285extern void pcibios_free_controller(struct pci_controller *phb);
286
287#ifdef CONFIG_PCI
288extern unsigned long pci_address_to_pio(phys_addr_t address);
289extern int pcibios_vaddr_is_ioport(void __iomem *address);
290#else
291static inline unsigned long pci_address_to_pio(phys_addr_t address)
292{
293 return (unsigned long)-1;
294}
295static inline int pcibios_vaddr_is_ioport(void __iomem *address)
296{
297 return 0;
298}
299#endif /* CONFIG_PCI */
300
301#endif /* __KERNEL__ */
302#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
new file mode 100644
index 000000000000..a05a942b1c25
--- /dev/null
+++ b/arch/powerpc/include/asm/pci.h
@@ -0,0 +1,228 @@
1#ifndef __ASM_POWERPC_PCI_H
2#define __ASM_POWERPC_PCI_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/machdep.h>
18#include <asm/scatterlist.h>
19#include <asm/io.h>
20#include <asm/prom.h>
21#include <asm/pci-bridge.h>
22
23#include <asm-generic/pci-dma-compat.h>
24
25#define PCIBIOS_MIN_IO 0x1000
26#define PCIBIOS_MIN_MEM 0x10000000
27
28struct pci_dev;
29
30/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
31#define IOBASE_BRIDGE_NUMBER 0
32#define IOBASE_MEMORY 1
33#define IOBASE_IO 2
34#define IOBASE_ISA_IO 3
35#define IOBASE_ISA_MEM 4
36
37/*
38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers (don't do that on ppc64 yet !)
40 */
41#define pcibios_assign_all_busses() (ppc_pci_flags & \
42 PPC_PCI_REASSIGN_ALL_BUS)
43#define pcibios_scan_all_fns(a, b) 0
44
45static inline void pcibios_set_master(struct pci_dev *dev)
46{
47 /* No special bus mastering setup handling */
48}
49
50static inline void pcibios_penalize_isa_irq(int irq, int active)
51{
52 /* We don't do dynamic PCI IRQ allocation */
53}
54
55#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
56static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
57{
58 if (ppc_md.pci_get_legacy_ide_irq)
59 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
60 return channel ? 15 : 14;
61}
62
63#ifdef CONFIG_PPC64
64
65/*
66 * We want to avoid touching the cacheline size or MWI bit.
67 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
68 * size in all cases) and hardware treats MWI the same as memory write.
69 */
70#define PCI_DISABLE_MWI
71
72#ifdef CONFIG_PCI
73extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
74extern struct dma_mapping_ops *get_pci_dma_ops(void);
75
76static inline void pci_dma_burst_advice(struct pci_dev *pdev,
77 enum pci_dma_burst_strategy *strat,
78 unsigned long *strategy_parameter)
79{
80 unsigned long cacheline_size;
81 u8 byte;
82
83 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
84 if (byte == 0)
85 cacheline_size = 1024;
86 else
87 cacheline_size = (int) byte * 4;
88
89 *strat = PCI_DMA_BURST_MULTIPLE;
90 *strategy_parameter = cacheline_size;
91}
92#else /* CONFIG_PCI */
93#define set_pci_dma_ops(d)
94#define get_pci_dma_ops() NULL
95#endif
96
97#else /* 32-bit */
98
99#ifdef CONFIG_PCI
100static inline void pci_dma_burst_advice(struct pci_dev *pdev,
101 enum pci_dma_burst_strategy *strat,
102 unsigned long *strategy_parameter)
103{
104 *strat = PCI_DMA_BURST_INFINITY;
105 *strategy_parameter = ~0UL;
106}
107#endif
108#endif /* CONFIG_PPC64 */
109
110extern int pci_domain_nr(struct pci_bus *bus);
111
112/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus);
114
115
116struct vm_area_struct;
117/* Map a range of PCI memory or I/O space for a device into user space */
118int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
119 enum pci_mmap_state mmap_state, int write_combine);
120
121/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
122#define HAVE_PCI_MMAP 1
123
124#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
125/*
126 * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
127 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
128 * so on are not nops.
129 * and thus...
130 */
131#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
132 dma_addr_t ADDR_NAME;
133#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
134 __u32 LEN_NAME;
135#define pci_unmap_addr(PTR, ADDR_NAME) \
136 ((PTR)->ADDR_NAME)
137#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
138 (((PTR)->ADDR_NAME) = (VAL))
139#define pci_unmap_len(PTR, LEN_NAME) \
140 ((PTR)->LEN_NAME)
141#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
142 (((PTR)->LEN_NAME) = (VAL))
143
144#else /* 32-bit && coherent */
145
146/* pci_unmap_{page,single} is a nop so... */
147#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
148#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
149#define pci_unmap_addr(PTR, ADDR_NAME) (0)
150#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
151#define pci_unmap_len(PTR, LEN_NAME) (0)
152#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
153
154#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
155
156#ifdef CONFIG_PPC64
157
158/* The PCI address space does not equal the physical memory address
159 * space (we have an IOMMU). The IDE and SCSI device layers use
160 * this boolean for bounce buffer decisions.
161 */
162#define PCI_DMA_BUS_IS_PHYS (0)
163
164#else /* 32-bit */
165
166/* The PCI address space does equal the physical memory
167 * address space (no IOMMU). The IDE and SCSI device layers use
168 * this boolean for bounce buffer decisions.
169 */
170#define PCI_DMA_BUS_IS_PHYS (1)
171
172#endif /* CONFIG_PPC64 */
173
174extern void pcibios_resource_to_bus(struct pci_dev *dev,
175 struct pci_bus_region *region,
176 struct resource *res);
177
178extern void pcibios_bus_to_resource(struct pci_dev *dev,
179 struct resource *res,
180 struct pci_bus_region *region);
181
182static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
183 struct resource *res)
184{
185 struct resource *root = NULL;
186
187 if (res->flags & IORESOURCE_IO)
188 root = &ioport_resource;
189 if (res->flags & IORESOURCE_MEM)
190 root = &iomem_resource;
191
192 return root;
193}
194
195extern void pcibios_setup_new_device(struct pci_dev *dev);
196
197extern void pcibios_claim_one_bus(struct pci_bus *b);
198
199extern void pcibios_resource_survey(void);
200
201extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
202
203extern struct pci_dev *of_create_pci_dev(struct device_node *node,
204 struct pci_bus *bus, int devfn);
205
206extern void of_scan_pci_bridge(struct device_node *node,
207 struct pci_dev *dev);
208
209extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
210
211extern int pci_read_irq_line(struct pci_dev *dev);
212
213struct file;
214extern pgprot_t pci_phys_mem_access_prot(struct file *file,
215 unsigned long pfn,
216 unsigned long size,
217 pgprot_t prot);
218
219#define HAVE_ARCH_PCI_RESOURCE_TO_USER
220extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
221 const struct resource *rsrc,
222 resource_size_t *start, resource_size_t *end);
223
224extern void pcibios_do_bus_setup(struct pci_bus *bus);
225extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
226
227#endif /* __KERNEL__ */
228#endif /* __ASM_POWERPC_PCI_H */
diff --git a/arch/powerpc/include/asm/percpu.h b/arch/powerpc/include/asm/percpu.h
new file mode 100644
index 000000000000..f879252b7ea6
--- /dev/null
+++ b/arch/powerpc/include/asm/percpu.h
@@ -0,0 +1,24 @@
1#ifndef _ASM_POWERPC_PERCPU_H_
2#define _ASM_POWERPC_PERCPU_H_
3#ifdef __powerpc64__
4#include <linux/compiler.h>
5
6/*
7 * Same as asm-generic/percpu.h, except that we store the per cpu offset
8 * in the paca. Based on the x86-64 implementation.
9 */
10
11#ifdef CONFIG_SMP
12
13#include <asm/paca.h>
14
15#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
16#define __my_cpu_offset local_paca->data_offset
17#define per_cpu_offset(x) (__per_cpu_offset(x))
18
19#endif /* CONFIG_SMP */
20#endif /* __powerpc64__ */
21
22#include <asm-generic/percpu.h>
23
24#endif /* _ASM_POWERPC_PERCPU_H_ */
diff --git a/arch/powerpc/include/asm/pgalloc-32.h b/arch/powerpc/include/asm/pgalloc-32.h
new file mode 100644
index 000000000000..58c07147b3ea
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc-32.h
@@ -0,0 +1,43 @@
1#ifndef _ASM_POWERPC_PGALLOC_32_H
2#define _ASM_POWERPC_PGALLOC_32_H
3
4#include <linux/threads.h>
5
6extern void __bad_pte(pmd_t *pmd);
7
8extern pgd_t *pgd_alloc(struct mm_struct *mm);
9extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
10
11/*
12 * We don't have any real pmd's, and this code never triggers because
13 * the pgd will always be present..
14 */
15/* #define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) */
16#define pmd_free(mm, x) do { } while (0)
17#define __pmd_free_tlb(tlb,x) do { } while (0)
18/* #define pgd_populate(mm, pmd, pte) BUG() */
19
20#ifndef CONFIG_BOOKE
21#define pmd_populate_kernel(mm, pmd, pte) \
22 (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
23#define pmd_populate(mm, pmd, pte) \
24 (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
25#define pmd_pgtable(pmd) pmd_page(pmd)
26#else
27#define pmd_populate_kernel(mm, pmd, pte) \
28 (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
29#define pmd_populate(mm, pmd, pte) \
30 (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
31#define pmd_pgtable(pmd) pmd_page(pmd)
32#endif
33
34extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
35extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
36extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
37extern void pte_free(struct mm_struct *mm, pgtable_t pte);
38
39#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte))
40
41#define check_pgt_cache() do { } while (0)
42
43#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
new file mode 100644
index 000000000000..812a1d8f35cb
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -0,0 +1,166 @@
1#ifndef _ASM_POWERPC_PGALLOC_64_H
2#define _ASM_POWERPC_PGALLOC_64_H
3/*
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/mm.h>
11#include <linux/slab.h>
12#include <linux/cpumask.h>
13#include <linux/percpu.h>
14
15#ifndef CONFIG_PPC_SUBPAGE_PROT
16static inline void subpage_prot_free(pgd_t *pgd) {}
17#endif
18
19extern struct kmem_cache *pgtable_cache[];
20
21#define PGD_CACHE_NUM 0
22#define PUD_CACHE_NUM 1
23#define PMD_CACHE_NUM 1
24#define HUGEPTE_CACHE_NUM 2
25#define PTE_NONCACHE_NUM 7 /* from GFP rather than kmem_cache */
26
27static inline pgd_t *pgd_alloc(struct mm_struct *mm)
28{
29 return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
30}
31
32static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
33{
34 subpage_prot_free(pgd);
35 kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
36}
37
38#ifndef CONFIG_PPC_64K_PAGES
39
40#define pgd_populate(MM, PGD, PUD) pgd_set(PGD, PUD)
41
42static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
43{
44 return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
45 GFP_KERNEL|__GFP_REPEAT);
46}
47
48static inline void pud_free(struct mm_struct *mm, pud_t *pud)
49{
50 kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
51}
52
53static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
54{
55 pud_set(pud, (unsigned long)pmd);
56}
57
58#define pmd_populate(mm, pmd, pte_page) \
59 pmd_populate_kernel(mm, pmd, page_address(pte_page))
60#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
61#define pmd_pgtable(pmd) pmd_page(pmd)
62
63
64#else /* CONFIG_PPC_64K_PAGES */
65
66#define pud_populate(mm, pud, pmd) pud_set(pud, (unsigned long)pmd)
67
68static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
69 pte_t *pte)
70{
71 pmd_set(pmd, (unsigned long)pte);
72}
73
74#define pmd_populate(mm, pmd, pte_page) \
75 pmd_populate_kernel(mm, pmd, page_address(pte_page))
76#define pmd_pgtable(pmd) pmd_page(pmd)
77
78#endif /* CONFIG_PPC_64K_PAGES */
79
80static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
81{
82 return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
83 GFP_KERNEL|__GFP_REPEAT);
84}
85
86static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
87{
88 kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
89}
90
91static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
92 unsigned long address)
93{
94 return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
95}
96
97static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
98 unsigned long address)
99{
100 struct page *page;
101 pte_t *pte;
102
103 pte = pte_alloc_one_kernel(mm, address);
104 if (!pte)
105 return NULL;
106 page = virt_to_page(pte);
107 pgtable_page_ctor(page);
108 return page;
109}
110
111static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
112{
113 free_page((unsigned long)pte);
114}
115
116static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
117{
118 pgtable_page_dtor(ptepage);
119 __free_page(ptepage);
120}
121
122#define PGF_CACHENUM_MASK 0x7
123
124typedef struct pgtable_free {
125 unsigned long val;
126} pgtable_free_t;
127
128static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
129 unsigned long mask)
130{
131 BUG_ON(cachenum > PGF_CACHENUM_MASK);
132
133 return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
134}
135
136static inline void pgtable_free(pgtable_free_t pgf)
137{
138 void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
139 int cachenum = pgf.val & PGF_CACHENUM_MASK;
140
141 if (cachenum == PTE_NONCACHE_NUM)
142 free_page((unsigned long)p);
143 else
144 kmem_cache_free(pgtable_cache[cachenum], p);
145}
146
147extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
148
149#define __pte_free_tlb(tlb,ptepage) \
150do { \
151 pgtable_page_dtor(ptepage); \
152 pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
153 PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
154} while (0)
155#define __pmd_free_tlb(tlb, pmd) \
156 pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
157 PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
158#ifndef CONFIG_PPC_64K_PAGES
159#define __pud_free_tlb(tlb, pud) \
160 pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
161 PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
162#endif /* CONFIG_PPC_64K_PAGES */
163
164#define check_pgt_cache() do { } while (0)
165
166#endif /* _ASM_POWERPC_PGALLOC_64_H */
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
new file mode 100644
index 000000000000..b4505ed0f0f2
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_POWERPC_PGALLOC_H
2#define _ASM_POWERPC_PGALLOC_H
3#ifdef __KERNEL__
4
5#ifdef CONFIG_PPC64
6#include <asm/pgalloc-64.h>
7#else
8#include <asm/pgalloc-32.h>
9#endif
10
11#endif /* __KERNEL__ */
12#endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-4k.h
new file mode 100644
index 000000000000..6b18ba9d2d85
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-4k.h
@@ -0,0 +1,117 @@
1#ifndef _ASM_POWERPC_PGTABLE_4K_H
2#define _ASM_POWERPC_PGTABLE_4K_H
3/*
4 * Entries per page directory level. The PTE level must use a 64b record
5 * for each page table entry. The PMD and PGD level use a 32b record for
6 * each entry by assuming that each entry is page aligned.
7 */
8#define PTE_INDEX_SIZE 9
9#define PMD_INDEX_SIZE 7
10#define PUD_INDEX_SIZE 7
11#define PGD_INDEX_SIZE 9
12
13#ifndef __ASSEMBLY__
14#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
15#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
16#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
17#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
18#endif /* __ASSEMBLY__ */
19
20#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
21#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
22#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE)
23#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
24
25/* PMD_SHIFT determines what a second-level page table entry can map */
26#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
27#define PMD_SIZE (1UL << PMD_SHIFT)
28#define PMD_MASK (~(PMD_SIZE-1))
29
30/* With 4k base page size, hugepage PTEs go at the PMD level */
31#define MIN_HUGEPTE_SHIFT PMD_SHIFT
32
33/* PUD_SHIFT determines what a third-level page table entry can map */
34#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
35#define PUD_SIZE (1UL << PUD_SHIFT)
36#define PUD_MASK (~(PUD_SIZE-1))
37
38/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
39#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
40#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
41#define PGDIR_MASK (~(PGDIR_SIZE-1))
42
43/* PTE bits */
44#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
45#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
46#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
47#define _PAGE_F_SECOND _PAGE_SECONDARY
48#define _PAGE_F_GIX _PAGE_GROUP_IX
49#define _PAGE_SPECIAL 0x10000 /* software: special page */
50#define __HAVE_ARCH_PTE_SPECIAL
51
52/* PTE flags to conserve for HPTE identification */
53#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
54 _PAGE_SECONDARY | _PAGE_GROUP_IX)
55
56/* There is no 4K PFN hack on 4K pages */
57#define _PAGE_4K_PFN 0
58
59/* PAGE_MASK gives the right answer below, but only by accident */
60/* It should be preserving the high 48 bits and then specifically */
61/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
62#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
63 _PAGE_HPTEFLAGS)
64
65/* Bits to mask out from a PMD to get to the PTE page */
66#define PMD_MASKED_BITS 0
67/* Bits to mask out from a PUD to get to the PMD page */
68#define PUD_MASKED_BITS 0
69/* Bits to mask out from a PGD to get to the PUD page */
70#define PGD_MASKED_BITS 0
71
72/* shift to put page number into pte */
73#define PTE_RPN_SHIFT (17)
74
75#ifdef STRICT_MM_TYPECHECKS
76#define __real_pte(e,p) ((real_pte_t){(e)})
77#define __rpte_to_pte(r) ((r).pte)
78#else
79#define __real_pte(e,p) (e)
80#define __rpte_to_pte(r) (__pte(r))
81#endif
82#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
83
84#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
85 do { \
86 index = 0; \
87 shift = mmu_psize_defs[psize].shift; \
88
89#define pte_iterate_hashed_end() } while(0)
90
91#ifdef CONFIG_PPC_HAS_HASH_64K
92#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
93#else
94#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
95#endif
96
97/*
98 * 4-level page tables related bits
99 */
100
101#define pgd_none(pgd) (!pgd_val(pgd))
102#define pgd_bad(pgd) (pgd_val(pgd) == 0)
103#define pgd_present(pgd) (pgd_val(pgd) != 0)
104#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0)
105#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
106#define pgd_page(pgd) virt_to_page(pgd_page_vaddr(pgd))
107
108#define pud_offset(pgdp, addr) \
109 (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
110 (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
111
112#define pud_ERROR(e) \
113 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
114
115#define remap_4k_pfn(vma, addr, pfn, prot) \
116 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
117#endif /* _ASM_POWERPC_PGTABLE_4K_H */
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pgtable-64k.h
new file mode 100644
index 000000000000..07b0d8f09cb6
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-64k.h
@@ -0,0 +1,155 @@
1#ifndef _ASM_POWERPC_PGTABLE_64K_H
2#define _ASM_POWERPC_PGTABLE_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16
17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
20
21#ifdef CONFIG_PPC_SUBPAGE_PROT
22/*
23 * For the sub-page protection option, we extend the PGD with one of
24 * these. Basically we have a 3-level tree, with the top level being
25 * the protptrs array. To optimize speed and memory consumption when
26 * only addresses < 4GB are being protected, pointers to the first
27 * four pages of sub-page protection words are stored in the low_prot
28 * array.
29 * Each page of sub-page protection words protects 1GB (4 bytes
30 * protects 64k). For the 3-level tree, each page of pointers then
31 * protects 8TB.
32 */
33struct subpage_prot_table {
34 unsigned long maxaddr; /* only addresses < this are protected */
35 unsigned int **protptrs[2];
36 unsigned int *low_prot[4];
37};
38
39#undef PGD_TABLE_SIZE
40#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
41 sizeof(struct subpage_prot_table))
42
43#define SBP_L1_BITS (PAGE_SHIFT - 2)
44#define SBP_L2_BITS (PAGE_SHIFT - 3)
45#define SBP_L1_COUNT (1 << SBP_L1_BITS)
46#define SBP_L2_COUNT (1 << SBP_L2_BITS)
47#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
48#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
49
50extern void subpage_prot_free(pgd_t *pgd);
51
52static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
53{
54 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
55}
56#endif /* CONFIG_PPC_SUBPAGE_PROT */
57#endif /* __ASSEMBLY__ */
58
59/* With 4k base page size, hugepage PTEs go at the PMD level */
60#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
61
62/* PMD_SHIFT determines what a second-level page table entry can map */
63#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
64#define PMD_SIZE (1UL << PMD_SHIFT)
65#define PMD_MASK (~(PMD_SIZE-1))
66
67/* PGDIR_SHIFT determines what a third-level page table entry can map */
68#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
69#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71
72/* Additional PTE bits (don't change without checking asm in hash_low.S) */
73#define __HAVE_ARCH_PTE_SPECIAL
74#define _PAGE_SPECIAL 0x00000400 /* software: special page */
75#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
76#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
77#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
78#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
79
80/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
81 * we set that to be the whole sub-bits mask. The C code will only
82 * test this, so a multi-bit mask will work. For combo pages, this
83 * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
84 * all the sub bits. For real 64k pages, we now have the assembly set
85 * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
86 * that mask. This is fine as long as the HIDX bits are never set on
87 * a PTE that isn't hashed, which is the case today.
88 *
89 * A little nit is for the huge page C code, which does the hashing
90 * in C, we need to provide which bit to use.
91 */
92#define _PAGE_HASHPTE _PAGE_HPTE_SUB
93
94/* Note the full page bits must be in the same location as for normal
95 * 4k pages as the same asssembly will be used to insert 64K pages
96 * wether the kernel has CONFIG_PPC_64K_PAGES or not
97 */
98#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
99#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
100
101/* PTE flags to conserve for HPTE identification */
102#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
103
104/* Shift to put page number into pte.
105 *
106 * That gives us a max RPN of 34 bits, which means a max of 50 bits
107 * of addressable physical space, or 46 bits for the special 4k PFNs.
108 */
109#define PTE_RPN_SHIFT (30)
110#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
111#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
112
113/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
114 * pgprot changes
115 */
116#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
117 _PAGE_ACCESSED)
118
119/* Bits to mask out from a PMD to get to the PTE page */
120#define PMD_MASKED_BITS 0x1ff
121/* Bits to mask out from a PGD/PUD to get to the PMD page */
122#define PUD_MASKED_BITS 0x1ff
123
124/* Manipulate "rpte" values */
125#define __real_pte(e,p) ((real_pte_t) { \
126 (e), pte_val(*((p) + PTRS_PER_PTE)) })
127#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
128 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
129#define __rpte_to_pte(r) ((r).pte)
130#define __rpte_sub_valid(rpte, index) \
131 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
132
133
134/* Trick: we set __end to va + 64k, which happens works for
135 * a 16M page as well as we want only one iteration
136 */
137#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
138 do { \
139 unsigned long __end = va + PAGE_SIZE; \
140 unsigned __split = (psize == MMU_PAGE_4K || \
141 psize == MMU_PAGE_64K_AP); \
142 shift = mmu_psize_defs[psize].shift; \
143 for (index = 0; va < __end; index++, va += (1L << shift)) { \
144 if (!__split || __rpte_sub_valid(rpte, index)) do { \
145
146#define pte_iterate_hashed_end() } while(0); } } while(0)
147
148#define pte_pagesize_index(mm, addr, pte) \
149 (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
150
151#define remap_4k_pfn(vma, addr, pfn, prot) \
152 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
153 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
154
155#endif /* _ASM_POWERPC_PGTABLE_64K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
new file mode 100644
index 000000000000..6fe39e327047
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -0,0 +1,802 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
2#define _ASM_POWERPC_PGTABLE_PPC32_H
3
4#include <asm-generic/pgtable-nopmd.h>
5
6#ifndef __ASSEMBLY__
7#include <linux/sched.h>
8#include <linux/threads.h>
9#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
10
11extern unsigned long va_to_phys(unsigned long address);
12extern pte_t *va_to_pte(unsigned long address);
13extern unsigned long ioremap_bot, ioremap_base;
14
15#ifdef CONFIG_44x
16extern int icache_44x_need_flush;
17#endif
18
19#endif /* __ASSEMBLY__ */
20
21/*
22 * The PowerPC MMU uses a hash table containing PTEs, together with
23 * a set of 16 segment registers (on 32-bit implementations), to define
24 * the virtual to physical address mapping.
25 *
26 * We use the hash table as an extended TLB, i.e. a cache of currently
27 * active mappings. We maintain a two-level page table tree, much
28 * like that used by the i386, for the sake of the Linux memory
29 * management code. Low-level assembler code in hashtable.S
30 * (procedure hash_page) is responsible for extracting ptes from the
31 * tree and putting them into the hash table when necessary, and
32 * updating the accessed and modified bits in the page table tree.
33 */
34
35/*
36 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
37 * We also use the two level tables, but we can put the real bits in them
38 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
39 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
40 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
41 * based upon user/super access. The TLB does not have accessed nor write
42 * protect. We assume that if the TLB get loaded with an entry it is
43 * accessed, and overload the changed bit for write protect. We use
44 * two bits in the software pte that are supposed to be set to zero in
45 * the TLB entry (24 and 25) for these indicators. Although the level 1
46 * descriptor contains the guarded and writethrough/copyback bits, we can
47 * set these at the page level since they get copied from the Mx_TWC
48 * register when the TLB entry is loaded. We will use bit 27 for guard, since
49 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
50 * These will get masked from the level 2 descriptor at TLB load time, and
51 * copied to the MD_TWC before it gets loaded.
52 * Large page sizes added. We currently support two sizes, 4K and 8M.
53 * This also allows a TLB hander optimization because we can directly
54 * load the PMD into MD_TWC. The 8M pages are only used for kernel
55 * mapping of well known areas. The PMD (PGD) entries contain control
56 * flags in addition to the address, so care must be taken that the
57 * software no longer assumes these are only pointers.
58 */
59
60/*
61 * At present, all PowerPC 400-class processors share a similar TLB
62 * architecture. The instruction and data sides share a unified,
63 * 64-entry, fully-associative TLB which is maintained totally under
64 * software control. In addition, the instruction side has a
65 * hardware-managed, 4-entry, fully-associative TLB which serves as a
66 * first level to the shared TLB. These two TLBs are known as the UTLB
67 * and ITLB, respectively (see "mmu.h" for definitions).
68 */
69
70/*
71 * The normal case is that PTEs are 32-bits and we have a 1-page
72 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 *
74 * For any >32-bit physical address platform, we can use the following
75 * two level page table layout where the pgdir is 8KB and the MS 13 bits
76 * are an index to the second level table. The combined pgdir/pmd first
77 * level has 2048 entries and the second level has 512 64-bit PTE entries.
78 * -Matt
79 */
80/* PGDIR_SHIFT determines what a top-level page table entry can map */
81#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
82#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
84
85/*
86 * entries per page directory level: our page-table tree is two-level, so
87 * we don't really have any PMD directory.
88 */
89#ifndef __ASSEMBLY__
90#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
91#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
92#endif /* __ASSEMBLY__ */
93
94#define PTRS_PER_PTE (1 << PTE_SHIFT)
95#define PTRS_PER_PMD 1
96#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
97
98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
99#define FIRST_USER_ADDRESS 0
100
101#define pte_ERROR(e) \
102 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
103 (unsigned long long)pte_val(e))
104#define pgd_ERROR(e) \
105 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
106
107/*
108 * Just any arbitrary offset to the start of the vmalloc VM area: the
109 * current 64MB value just means that there will be a 64MB "hole" after the
110 * physical memory until the kernel virtual memory starts. That means that
111 * any out-of-bounds memory accesses will hopefully be caught.
112 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
113 * area for the same reason. ;)
114 *
115 * We no longer map larger than phys RAM with the BATs so we don't have
116 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
117 * about clashes between our early calls to ioremap() that start growing down
118 * from ioremap_base being run into the VM area allocations (growing upwards
119 * from VMALLOC_START). For this reason we have ioremap_bot to check when
120 * we actually run into our mappings setup in the early boot with the VM
121 * system. This really does become a problem for machines with good amounts
122 * of RAM. -- Cort
123 */
124#define VMALLOC_OFFSET (0x1000000) /* 16M */
125#ifdef PPC_PIN_SIZE
126#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
127#else
128#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
129#endif
130#define VMALLOC_END ioremap_bot
131
132/*
133 * Bits in a linux-style PTE. These match the bits in the
134 * (hardware-defined) PowerPC PTE as closely as possible.
135 */
136
137#if defined(CONFIG_40x)
138
139/* There are several potential gotchas here. The 40x hardware TLBLO
140 field looks like this:
141
142 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
143 RPN..................... 0 0 EX WR ZSEL....... W I M G
144
145 Where possible we make the Linux PTE bits match up with this
146
147 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
148 support down to 1k pages), this is done in the TLBMiss exception
149 handler.
150 - We use only zones 0 (for kernel pages) and 1 (for user pages)
151 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
152 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
153 zone.
154 - PRESENT *must* be in the bottom two bits because swap cache
155 entries use the top 30 bits. Because 40x doesn't support SMP
156 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
157 is cleared in the TLB miss handler before the TLB entry is loaded.
158 - All other bits of the PTE are loaded into TLBLO without
159 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
160 software PTE bits. We actually use use bits 21, 24, 25, and
161 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
162 PRESENT.
163*/
164
165/* Definitions for 40x embedded chips. */
166#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
167#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
168#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
169#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
170#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
171#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
172#define _PAGE_RW 0x040 /* software: Writes permitted */
173#define _PAGE_DIRTY 0x080 /* software: dirty page */
174#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
175#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
176#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
177
178#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
179#define _PMD_BAD 0x802
180#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
181#define _PMD_SIZE_4M 0x0c0
182#define _PMD_SIZE_16M 0x0e0
183#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
184
185/* Until my rework is finished, 40x still needs atomic PTE updates */
186#define PTE_ATOMIC_UPDATES 1
187
188#elif defined(CONFIG_44x)
189/*
190 * Definitions for PPC440
191 *
192 * Because of the 3 word TLB entries to support 36-bit addressing,
193 * the attribute are difficult to map in such a fashion that they
194 * are easily loaded during exception processing. I decided to
195 * organize the entry so the ERPN is the only portion in the
196 * upper word of the PTE and the attribute bits below are packed
197 * in as sensibly as they can be in the area below a 4KB page size
198 * oriented RPN. This at least makes it easy to load the RPN and
199 * ERPN fields in the TLB. -Matt
200 *
201 * Note that these bits preclude future use of a page size
202 * less than 4KB.
203 *
204 *
205 * PPC 440 core has following TLB attribute fields;
206 *
207 * TLB1:
208 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
209 * RPN................................. - - - - - - ERPN.......
210 *
211 * TLB2:
212 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
213 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
214 *
215 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
216 * TLB2 storage attibute fields. Those are:
217 *
218 * TLB2:
219 * 0...10 11 12 13 14 15 16...31
220 * no change WL1 IL1I IL1D IL2I IL2D no change
221 *
222 * There are some constrains and options, to decide mapping software bits
223 * into TLB entry.
224 *
225 * - PRESENT *must* be in the bottom three bits because swap cache
226 * entries use the top 29 bits for TLB2.
227 *
228 * - FILE *must* be in the bottom three bits because swap cache
229 * entries use the top 29 bits for TLB2.
230 *
231 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
232 * doesn't support SMP. So we can use this as software bit, like
233 * DIRTY.
234 *
235 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
236 * for memory protection related functions (see PTE structure in
237 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
238 * above bits. Note that the bit values are CPU specific, not architecture
239 * specific.
240 *
241 * The kernel PTE entry holds an arch-dependent swp_entry structure under
242 * certain situations. In other words, in such situations some portion of
243 * the PTE bits are used as a swp_entry. In the PPC implementation, the
244 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
245 * hold protection values. That means the three protection bits are
246 * reserved for both PTE and SWAP entry at the most significant three
247 * LSBs.
248 *
249 * There are three protection bits available for SWAP entry:
250 * _PAGE_PRESENT
251 * _PAGE_FILE
252 * _PAGE_HASHPTE (if HW has)
253 *
254 * So those three bits have to be inside of 0-2nd LSB of PTE.
255 *
256 */
257
258#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
259#define _PAGE_RW 0x00000002 /* S: Write permission */
260#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
261#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
262#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
263#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
264#define _PAGE_USER 0x00000040 /* S: User page */
265#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
266#define _PAGE_GUARDED 0x00000100 /* H: G bit */
267#define _PAGE_COHERENT 0x00000200 /* H: M bit */
268#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
269#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
270
271/* TODO: Add large page lowmem mapping support */
272#define _PMD_PRESENT 0
273#define _PMD_PRESENT_MASK (PAGE_MASK)
274#define _PMD_BAD (~PAGE_MASK)
275
276/* ERPN in a PTE never gets cleared, ignore it */
277#define _PTE_NONE_MASK 0xffffffff00000000ULL
278
279
280#elif defined(CONFIG_FSL_BOOKE)
281/*
282 MMU Assist Register 3:
283
284 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
285 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
286
287 - PRESENT *must* be in the bottom three bits because swap cache
288 entries use the top 29 bits.
289
290 - FILE *must* be in the bottom three bits because swap cache
291 entries use the top 29 bits.
292*/
293
294/* Definitions for FSL Book-E Cores */
295#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
296#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
297#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
298#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
299#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
300#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
301#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
302
303#define _PAGE_ENDIAN 0x00040 /* H: E bit */
304#define _PAGE_GUARDED 0x00080 /* H: G bit */
305#define _PAGE_COHERENT 0x00100 /* H: M bit */
306#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
307#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
308
309#ifdef CONFIG_PTE_64BIT
310/* ERPN in a PTE never gets cleared, ignore it */
311#define _PTE_NONE_MASK 0xffffffffffff0000ULL
312#endif
313
314#define _PMD_PRESENT 0
315#define _PMD_PRESENT_MASK (PAGE_MASK)
316#define _PMD_BAD (~PAGE_MASK)
317
318#elif defined(CONFIG_8xx)
319/* Definitions for 8xx embedded chips. */
320#define _PAGE_PRESENT 0x0001 /* Page is valid */
321#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
322#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
323#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
324
325/* These five software bits must be masked out when the entry is loaded
326 * into the TLB.
327 */
328#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
329#define _PAGE_GUARDED 0x0010 /* software: guarded access */
330#define _PAGE_DIRTY 0x0020 /* software: page changed */
331#define _PAGE_RW 0x0040 /* software: user write access allowed */
332#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
333
334/* Setting any bits in the nibble with the follow two controls will
335 * require a TLB exception handler change. It is assumed unused bits
336 * are always zero.
337 */
338#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
339#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
340
341#define _PMD_PRESENT 0x0001
342#define _PMD_BAD 0x0ff0
343#define _PMD_PAGE_MASK 0x000c
344#define _PMD_PAGE_8M 0x000c
345
346#define _PTE_NONE_MASK _PAGE_ACCESSED
347
348/* Until my rework is finished, 8xx still needs atomic PTE updates */
349#define PTE_ATOMIC_UPDATES 1
350
351#else /* CONFIG_6xx */
352/* Definitions for 60x, 740/750, etc. */
353#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
354#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
355#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
356#define _PAGE_USER 0x004 /* usermode access allowed */
357#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
358#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
359#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
360#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
361#define _PAGE_DIRTY 0x080 /* C: page changed */
362#define _PAGE_ACCESSED 0x100 /* R: page referenced */
363#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
364#define _PAGE_RW 0x400 /* software: user write access allowed */
365
366#define _PTE_NONE_MASK _PAGE_HASHPTE
367
368#define _PMD_PRESENT 0
369#define _PMD_PRESENT_MASK (PAGE_MASK)
370#define _PMD_BAD (~PAGE_MASK)
371
372/* Hash table based platforms need atomic updates of the linux PTE */
373#define PTE_ATOMIC_UPDATES 1
374
375#endif
376
377/*
378 * Some bits are only used on some cpu families...
379 */
380#ifndef _PAGE_HASHPTE
381#define _PAGE_HASHPTE 0
382#endif
383#ifndef _PTE_NONE_MASK
384#define _PTE_NONE_MASK 0
385#endif
386#ifndef _PAGE_SHARED
387#define _PAGE_SHARED 0
388#endif
389#ifndef _PAGE_HWWRITE
390#define _PAGE_HWWRITE 0
391#endif
392#ifndef _PAGE_HWEXEC
393#define _PAGE_HWEXEC 0
394#endif
395#ifndef _PAGE_EXEC
396#define _PAGE_EXEC 0
397#endif
398#ifndef _PAGE_ENDIAN
399#define _PAGE_ENDIAN 0
400#endif
401#ifndef _PAGE_COHERENT
402#define _PAGE_COHERENT 0
403#endif
404#ifndef _PAGE_WRITETHRU
405#define _PAGE_WRITETHRU 0
406#endif
407#ifndef _PMD_PRESENT_MASK
408#define _PMD_PRESENT_MASK _PMD_PRESENT
409#endif
410#ifndef _PMD_SIZE
411#define _PMD_SIZE 0
412#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
413#endif
414
415#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
416
417
418#define PAGE_PROT_BITS __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
419 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
420 _PAGE_USER | _PAGE_ACCESSED | \
421 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
422 _PAGE_EXEC | _PAGE_HWEXEC)
423/*
424 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
425 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
426 * to have it in the Linux PTE, and in fact the bit could be reused for
427 * another purpose. -- paulus.
428 */
429
430#ifdef CONFIG_44x
431#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
432#else
433#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
434#endif
435#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
436#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
437
438#ifdef CONFIG_PPC_STD_MMU
439/* On standard PPC MMU, no user access implies kernel read/write access,
440 * so to write-protect kernel memory we must turn on user access */
441#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
442#else
443#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
444#endif
445
446#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
447#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
448
449#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
450 defined(CONFIG_KPROBES)
451/* We want the debuggers to be able to set breakpoints anywhere, so
452 * don't write protect the kernel text */
453#define _PAGE_RAM_TEXT _PAGE_RAM
454#else
455#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
456#endif
457
458#define PAGE_NONE __pgprot(_PAGE_BASE)
459#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
460#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
461#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
462#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
463#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
464#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
465
466#define PAGE_KERNEL __pgprot(_PAGE_RAM)
467#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
468
469/*
470 * The PowerPC can only do execute protection on a segment (256MB) basis,
471 * not on a page basis. So we consider execute permission the same as read.
472 * Also, write permissions imply read permissions.
473 * This is the closest we can get..
474 */
475#define __P000 PAGE_NONE
476#define __P001 PAGE_READONLY_X
477#define __P010 PAGE_COPY
478#define __P011 PAGE_COPY_X
479#define __P100 PAGE_READONLY
480#define __P101 PAGE_READONLY_X
481#define __P110 PAGE_COPY
482#define __P111 PAGE_COPY_X
483
484#define __S000 PAGE_NONE
485#define __S001 PAGE_READONLY_X
486#define __S010 PAGE_SHARED
487#define __S011 PAGE_SHARED_X
488#define __S100 PAGE_READONLY
489#define __S101 PAGE_READONLY_X
490#define __S110 PAGE_SHARED
491#define __S111 PAGE_SHARED_X
492
493#ifndef __ASSEMBLY__
494/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
495 * kernel without large page PMD support */
496extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
497
498/*
499 * Conversions between PTE values and page frame numbers.
500 */
501
502/* in some case we want to additionaly adjust where the pfn is in the pte to
503 * allow room for more flags */
504#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
505#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
506#else
507#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
508#endif
509
510#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
511#define pte_page(x) pfn_to_page(pte_pfn(x))
512
513#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
514 pgprot_val(prot))
515#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
516#endif /* __ASSEMBLY__ */
517
518#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
519#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
520#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
521
522#define pmd_none(pmd) (!pmd_val(pmd))
523#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
524#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
525#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
526
527#ifndef __ASSEMBLY__
528/*
529 * The following only work if pte_present() is true.
530 * Undefined behaviour if not..
531 */
532static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
533static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
534static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
535static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
536static inline int pte_special(pte_t pte) { return 0; }
537
538static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
539static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
540
541static inline pte_t pte_wrprotect(pte_t pte) {
542 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
543static inline pte_t pte_mkclean(pte_t pte) {
544 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
545static inline pte_t pte_mkold(pte_t pte) {
546 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
547
548static inline pte_t pte_mkwrite(pte_t pte) {
549 pte_val(pte) |= _PAGE_RW; return pte; }
550static inline pte_t pte_mkdirty(pte_t pte) {
551 pte_val(pte) |= _PAGE_DIRTY; return pte; }
552static inline pte_t pte_mkyoung(pte_t pte) {
553 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
554static inline pte_t pte_mkspecial(pte_t pte) {
555 return pte; }
556static inline unsigned long pte_pgprot(pte_t pte)
557{
558 return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
559}
560
561static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
562{
563 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
564 return pte;
565}
566
567/*
568 * When flushing the tlb entry for a page, we also need to flush the hash
569 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
570 */
571extern int flush_hash_pages(unsigned context, unsigned long va,
572 unsigned long pmdval, int count);
573
574/* Add an HPTE to the hash table */
575extern void add_hash_page(unsigned context, unsigned long va,
576 unsigned long pmdval);
577
578/*
579 * Atomic PTE updates.
580 *
581 * pte_update clears and sets bit atomically, and returns
582 * the old pte value. In the 64-bit PTE case we lock around the
583 * low PTE word since we expect ALL flag bits to be there
584 */
585#ifndef CONFIG_PTE_64BIT
586static inline unsigned long pte_update(pte_t *p,
587 unsigned long clr,
588 unsigned long set)
589{
590#ifdef PTE_ATOMIC_UPDATES
591 unsigned long old, tmp;
592
593 __asm__ __volatile__("\
5941: lwarx %0,0,%3\n\
595 andc %1,%0,%4\n\
596 or %1,%1,%5\n"
597 PPC405_ERR77(0,%3)
598" stwcx. %1,0,%3\n\
599 bne- 1b"
600 : "=&r" (old), "=&r" (tmp), "=m" (*p)
601 : "r" (p), "r" (clr), "r" (set), "m" (*p)
602 : "cc" );
603#else /* PTE_ATOMIC_UPDATES */
604 unsigned long old = pte_val(*p);
605 *p = __pte((old & ~clr) | set);
606#endif /* !PTE_ATOMIC_UPDATES */
607
608#ifdef CONFIG_44x
609 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
610 icache_44x_need_flush = 1;
611#endif
612 return old;
613}
614#else /* CONFIG_PTE_64BIT */
615/* TODO: Change that to only modify the low word and move set_pte_at()
616 * out of line
617 */
618static inline unsigned long long pte_update(pte_t *p,
619 unsigned long clr,
620 unsigned long set)
621{
622#ifdef PTE_ATOMIC_UPDATES
623 unsigned long long old;
624 unsigned long tmp;
625
626 __asm__ __volatile__("\
6271: lwarx %L0,0,%4\n\
628 lwzx %0,0,%3\n\
629 andc %1,%L0,%5\n\
630 or %1,%1,%6\n"
631 PPC405_ERR77(0,%3)
632" stwcx. %1,0,%4\n\
633 bne- 1b"
634 : "=&r" (old), "=&r" (tmp), "=m" (*p)
635 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
636 : "cc" );
637#else /* PTE_ATOMIC_UPDATES */
638 unsigned long long old = pte_val(*p);
639 *p = __pte((old & ~(unsigned long long)clr) | set);
640#endif /* !PTE_ATOMIC_UPDATES */
641
642#ifdef CONFIG_44x
643 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
644 icache_44x_need_flush = 1;
645#endif
646 return old;
647}
648#endif /* CONFIG_PTE_64BIT */
649
650/*
651 * set_pte stores a linux PTE into the linux page table.
652 * On machines which use an MMU hash table we avoid changing the
653 * _PAGE_HASHPTE bit.
654 */
655static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
656 pte_t *ptep, pte_t pte)
657{
658#if _PAGE_HASHPTE != 0
659 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
660#else
661 *ptep = pte;
662#endif
663}
664
665/*
666 * 2.6 calls this without flushing the TLB entry; this is wrong
667 * for our hash-based implementation, we fix that up here.
668 */
669#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
670static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
671{
672 unsigned long old;
673 old = pte_update(ptep, _PAGE_ACCESSED, 0);
674#if _PAGE_HASHPTE != 0
675 if (old & _PAGE_HASHPTE) {
676 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
677 flush_hash_pages(context, addr, ptephys, 1);
678 }
679#endif
680 return (old & _PAGE_ACCESSED) != 0;
681}
682#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
683 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
684
685#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
686static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
687 pte_t *ptep)
688{
689 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
690}
691
692#define __HAVE_ARCH_PTEP_SET_WRPROTECT
693static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
694 pte_t *ptep)
695{
696 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
697}
698static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
699 unsigned long addr, pte_t *ptep)
700{
701 ptep_set_wrprotect(mm, addr, ptep);
702}
703
704
705#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
706static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
707{
708 unsigned long bits = pte_val(entry) &
709 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
710 pte_update(ptep, 0, bits);
711}
712
713#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
714({ \
715 int __changed = !pte_same(*(__ptep), __entry); \
716 if (__changed) { \
717 __ptep_set_access_flags(__ptep, __entry, __dirty); \
718 flush_tlb_page_nohash(__vma, __address); \
719 } \
720 __changed; \
721})
722
723/*
724 * Macro to mark a page protection value as "uncacheable".
725 */
726#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
727
728struct file;
729extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
730 unsigned long size, pgprot_t vma_prot);
731#define __HAVE_PHYS_MEM_ACCESS_PROT
732
733#define __HAVE_ARCH_PTE_SAME
734#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
735
736/*
737 * Note that on Book E processors, the pmd contains the kernel virtual
738 * (lowmem) address of the pte page. The physical address is less useful
739 * because everything runs with translation enabled (even the TLB miss
740 * handler). On everything else the pmd contains the physical address
741 * of the pte page. -- paulus
742 */
743#ifndef CONFIG_BOOKE
744#define pmd_page_vaddr(pmd) \
745 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
746#define pmd_page(pmd) \
747 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
748#else
749#define pmd_page_vaddr(pmd) \
750 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
751#define pmd_page(pmd) \
752 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
753#endif
754
755/* to find an entry in a kernel page-table-directory */
756#define pgd_offset_k(address) pgd_offset(&init_mm, address)
757
758/* to find an entry in a page-table-directory */
759#define pgd_index(address) ((address) >> PGDIR_SHIFT)
760#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
761
762/* Find an entry in the third-level page table.. */
763#define pte_index(address) \
764 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
765#define pte_offset_kernel(dir, addr) \
766 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
767#define pte_offset_map(dir, addr) \
768 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
769#define pte_offset_map_nested(dir, addr) \
770 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
771
772#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
773#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
774
775/*
776 * Encode and decode a swap entry.
777 * Note that the bits we use in a PTE for representing a swap entry
778 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
779 *_PAGE_HASHPTE bit (if used). -- paulus
780 */
781#define __swp_type(entry) ((entry).val & 0x1f)
782#define __swp_offset(entry) ((entry).val >> 5)
783#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
784#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
785#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
786
787/* Encode and decode a nonlinear file mapping entry */
788#define PTE_FILE_MAX_BITS 29
789#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
790#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
791
792/*
793 * No page table caches to initialise
794 */
795#define pgtable_cache_init() do { } while (0)
796
797extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
798 pmd_t **pmdp);
799
800#endif /* !__ASSEMBLY__ */
801
802#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
new file mode 100644
index 000000000000..db0b8f3b8807
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -0,0 +1,468 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
2#define _ASM_POWERPC_PGTABLE_PPC64_H_
3/*
4 * This file contains the functions and defines necessary to modify and use
5 * the ppc64 hashed page table.
6 */
7
8#ifndef __ASSEMBLY__
9#include <linux/stddef.h>
10#include <asm/tlbflush.h>
11#endif /* __ASSEMBLY__ */
12
13#ifdef CONFIG_PPC_64K_PAGES
14#include <asm/pgtable-64k.h>
15#else
16#include <asm/pgtable-4k.h>
17#endif
18
19#define FIRST_USER_ADDRESS 0
20
21/*
22 * Size of EA range mapped by our pagetables.
23 */
24#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
27
28#if TASK_SIZE_USER64 > PGTABLE_RANGE
29#error TASK_SIZE_USER64 exceeds pagetable range
30#endif
31
32#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
33#error TASK_SIZE_USER64 exceeds user VSID range
34#endif
35
36
37/*
38 * Define the address range of the vmalloc VM area.
39 */
40#define VMALLOC_START ASM_CONST(0xD000000000000000)
41#define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
42#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
43
44/*
45 * Define the address ranges for MMIO and IO space :
46 *
47 * ISA_IO_BASE = VMALLOC_END, 64K reserved area
48 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
49 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
50 */
51#define FULL_IO_SIZE 0x80000000ul
52#define ISA_IO_BASE (VMALLOC_END)
53#define ISA_IO_END (VMALLOC_END + 0x10000ul)
54#define PHB_IO_BASE (ISA_IO_END)
55#define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
56#define IOREMAP_BASE (PHB_IO_END)
57#define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
58
59/*
60 * Region IDs
61 */
62#define REGION_SHIFT 60UL
63#define REGION_MASK (0xfUL << REGION_SHIFT)
64#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
65
66#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
67#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
68#define VMEMMAP_REGION_ID (0xfUL)
69#define USER_REGION_ID (0UL)
70
71/*
72 * Defines the address of the vmemap area, in its own region
73 */
74#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
75#define vmemmap ((struct page *)VMEMMAP_BASE)
76
77
78/*
79 * Common bits in a linux-style PTE. These match the bits in the
80 * (hardware-defined) PowerPC PTE as closely as possible. Additional
81 * bits may be defined in pgtable-*.h
82 */
83#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
84#define _PAGE_USER 0x0002 /* matches one of the PP bits */
85#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
86#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
87#define _PAGE_GUARDED 0x0008
88#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
89#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
90#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
91#define _PAGE_DIRTY 0x0080 /* C: page changed */
92#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
93#define _PAGE_RW 0x0200 /* software: user write access allowed */
94#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
95
96/* Strong Access Ordering */
97#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
98
99#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
100
101#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
102
103/* __pgprot defined in arch/powerpc/incliude/asm/page.h */
104#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
105
106#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
107#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
108#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
109#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
110#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
111#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
112#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
113#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
114 _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
115#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
116
117#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
118#define HAVE_PAGE_AGP
119
120#define PAGE_PROT_BITS __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | \
121 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
122 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
123 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
124/* PTEIDX nibble */
125#define _PTEIDX_SECONDARY 0x8
126#define _PTEIDX_GROUP_IX 0x7
127
128
129/*
130 * POWER4 and newer have per page execute protection, older chips can only
131 * do this on a segment (256MB) basis.
132 *
133 * Also, write permissions imply read permissions.
134 * This is the closest we can get..
135 *
136 * Note due to the way vm flags are laid out, the bits are XWR
137 */
138#define __P000 PAGE_NONE
139#define __P001 PAGE_READONLY
140#define __P010 PAGE_COPY
141#define __P011 PAGE_COPY
142#define __P100 PAGE_READONLY_X
143#define __P101 PAGE_READONLY_X
144#define __P110 PAGE_COPY_X
145#define __P111 PAGE_COPY_X
146
147#define __S000 PAGE_NONE
148#define __S001 PAGE_READONLY
149#define __S010 PAGE_SHARED
150#define __S011 PAGE_SHARED
151#define __S100 PAGE_READONLY_X
152#define __S101 PAGE_READONLY_X
153#define __S110 PAGE_SHARED_X
154#define __S111 PAGE_SHARED_X
155
156#ifdef CONFIG_HUGETLB_PAGE
157
158#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
160
161#endif
162
163#ifndef __ASSEMBLY__
164
165/*
166 * Conversion functions: convert a page and protection to a page entry,
167 * and a page entry and page directory to the page they refer to.
168 *
169 * mk_pte takes a (struct page *) as input
170 */
171#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
172
173static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
174{
175 pte_t pte;
176
177
178 pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
179 return pte;
180}
181
182#define pte_modify(_pte, newprot) \
183 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
184
185#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
186#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
187
188/* pte_clear moved to later in this file */
189
190#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
191#define pte_page(x) pfn_to_page(pte_pfn(x))
192
193#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
194#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
195
196#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
197#define pmd_none(pmd) (!pmd_val(pmd))
198#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
199 || (pmd_val(pmd) & PMD_BAD_BITS))
200#define pmd_present(pmd) (pmd_val(pmd) != 0)
201#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
202#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
203#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
204
205#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
206#define pud_none(pud) (!pud_val(pud))
207#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
208 || (pud_val(pud) & PUD_BAD_BITS))
209#define pud_present(pud) (pud_val(pud) != 0)
210#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
211#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
212#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
213
214#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
215
216/*
217 * Find an entry in a page-table-directory. We combine the address region
218 * (the high order N bits) and the pgd portion of the address.
219 */
220/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
221#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
222
223#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
224
225#define pmd_offset(pudp,addr) \
226 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
227
228#define pte_offset_kernel(dir,addr) \
229 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
230
231#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
232#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
233#define pte_unmap(pte) do { } while(0)
234#define pte_unmap_nested(pte) do { } while(0)
235
236/* to find an entry in a kernel page-table-directory */
237/* This now only contains the vmalloc pages */
238#define pgd_offset_k(address) pgd_offset(&init_mm, address)
239
240/*
241 * The following only work if pte_present() is true.
242 * Undefined behaviour if not..
243 */
244static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
245static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
246static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
247static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
248static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
249
250static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
251static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
252
253static inline pte_t pte_wrprotect(pte_t pte) {
254 pte_val(pte) &= ~(_PAGE_RW); return pte; }
255static inline pte_t pte_mkclean(pte_t pte) {
256 pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
257static inline pte_t pte_mkold(pte_t pte) {
258 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
259static inline pte_t pte_mkwrite(pte_t pte) {
260 pte_val(pte) |= _PAGE_RW; return pte; }
261static inline pte_t pte_mkdirty(pte_t pte) {
262 pte_val(pte) |= _PAGE_DIRTY; return pte; }
263static inline pte_t pte_mkyoung(pte_t pte) {
264 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
265static inline pte_t pte_mkhuge(pte_t pte) {
266 return pte; }
267static inline pte_t pte_mkspecial(pte_t pte) {
268 pte_val(pte) |= _PAGE_SPECIAL; return pte; }
269static inline unsigned long pte_pgprot(pte_t pte)
270{
271 return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
272}
273
274/* Atomic PTE updates */
275static inline unsigned long pte_update(struct mm_struct *mm,
276 unsigned long addr,
277 pte_t *ptep, unsigned long clr,
278 int huge)
279{
280 unsigned long old, tmp;
281
282 __asm__ __volatile__(
283 "1: ldarx %0,0,%3 # pte_update\n\
284 andi. %1,%0,%6\n\
285 bne- 1b \n\
286 andc %1,%0,%4 \n\
287 stdcx. %1,0,%3 \n\
288 bne- 1b"
289 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
290 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
291 : "cc" );
292
293 if (old & _PAGE_HASHPTE)
294 hpte_need_flush(mm, addr, ptep, old, huge);
295 return old;
296}
297
298static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
299 unsigned long addr, pte_t *ptep)
300{
301 unsigned long old;
302
303 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
304 return 0;
305 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
306 return (old & _PAGE_ACCESSED) != 0;
307}
308#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
309#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
310({ \
311 int __r; \
312 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
313 __r; \
314})
315
316#define __HAVE_ARCH_PTEP_SET_WRPROTECT
317static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
318 pte_t *ptep)
319{
320 unsigned long old;
321
322 if ((pte_val(*ptep) & _PAGE_RW) == 0)
323 return;
324 old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
325}
326
327static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
328 unsigned long addr, pte_t *ptep)
329{
330 unsigned long old;
331
332 if ((pte_val(*ptep) & _PAGE_RW) == 0)
333 return;
334 old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
335}
336
337/*
338 * We currently remove entries from the hashtable regardless of whether
339 * the entry was young or dirty. The generic routines only flush if the
340 * entry was young or dirty which is not good enough.
341 *
342 * We should be more intelligent about this but for the moment we override
343 * these functions and force a tlb flush unconditionally
344 */
345#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
346#define ptep_clear_flush_young(__vma, __address, __ptep) \
347({ \
348 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
349 __ptep); \
350 __young; \
351})
352
353#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
354static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
355 unsigned long addr, pte_t *ptep)
356{
357 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
358 return __pte(old);
359}
360
361static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
362 pte_t * ptep)
363{
364 pte_update(mm, addr, ptep, ~0UL, 0);
365}
366
367/*
368 * set_pte stores a linux PTE into the linux page table.
369 */
370static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
371 pte_t *ptep, pte_t pte)
372{
373 if (pte_present(*ptep))
374 pte_clear(mm, addr, ptep);
375 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
376 *ptep = pte;
377}
378
379/* Set the dirty and/or accessed bits atomically in a linux PTE, this
380 * function doesn't need to flush the hash entry
381 */
382#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
383static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
384{
385 unsigned long bits = pte_val(entry) &
386 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
387 unsigned long old, tmp;
388
389 __asm__ __volatile__(
390 "1: ldarx %0,0,%4\n\
391 andi. %1,%0,%6\n\
392 bne- 1b \n\
393 or %0,%3,%0\n\
394 stdcx. %0,0,%4\n\
395 bne- 1b"
396 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
397 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
398 :"cc");
399}
400#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
401({ \
402 int __changed = !pte_same(*(__ptep), __entry); \
403 if (__changed) { \
404 __ptep_set_access_flags(__ptep, __entry, __dirty); \
405 flush_tlb_page_nohash(__vma, __address); \
406 } \
407 __changed; \
408})
409
410/*
411 * Macro to mark a page protection value as "uncacheable".
412 */
413#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
414
415struct file;
416extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
417 unsigned long size, pgprot_t vma_prot);
418#define __HAVE_PHYS_MEM_ACCESS_PROT
419
420#define __HAVE_ARCH_PTE_SAME
421#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
422
423#define pte_ERROR(e) \
424 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
425#define pmd_ERROR(e) \
426 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
427#define pgd_ERROR(e) \
428 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
429
430/* Encode and de-code a swap entry */
431#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
432#define __swp_offset(entry) ((entry).val >> 8)
433#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
434#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
435#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
436#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
437#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
438#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
439
440void pgtable_cache_init(void);
441
442/*
443 * find_linux_pte returns the address of a linux pte for a given
444 * effective address and directory. If not found, it returns zero.
445 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
446{
447 pgd_t *pg;
448 pud_t *pu;
449 pmd_t *pm;
450 pte_t *pt = NULL;
451
452 pg = pgdir + pgd_index(ea);
453 if (!pgd_none(*pg)) {
454 pu = pud_offset(pg, ea);
455 if (!pud_none(*pu)) {
456 pm = pmd_offset(pu, ea);
457 if (pmd_present(*pm))
458 pt = pte_offset_kernel(pm, ea);
459 }
460 }
461 return pt;
462}
463
464pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);
465
466#endif /* __ASSEMBLY__ */
467
468#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
new file mode 100644
index 000000000000..dbb8ca172e44
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -0,0 +1,57 @@
1#ifndef _ASM_POWERPC_PGTABLE_H
2#define _ASM_POWERPC_PGTABLE_H
3#ifdef __KERNEL__
4
5#ifndef __ASSEMBLY__
6#include <asm/processor.h> /* For TASK_SIZE */
7#include <asm/mmu.h>
8#include <asm/page.h>
9struct mm_struct;
10#endif /* !__ASSEMBLY__ */
11
12#if defined(CONFIG_PPC64)
13# include <asm/pgtable-ppc64.h>
14#else
15# include <asm/pgtable-ppc32.h>
16#endif
17
18#ifndef __ASSEMBLY__
19/*
20 * ZERO_PAGE is a global shared page that is always zero: used
21 * for zero-mapped memory areas etc..
22 */
23extern unsigned long empty_zero_page[];
24#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
25
26extern pgd_t swapper_pg_dir[];
27
28extern void paging_init(void);
29
30/*
31 * kern_addr_valid is intended to indicate whether an address is a valid
32 * kernel address. Most 32-bit archs define it as always true (like this)
33 * but most 64-bit archs actually perform a test. What should we do here?
34 */
35#define kern_addr_valid(addr) (1)
36
37#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
38 remap_pfn_range(vma, vaddr, pfn, size, prot)
39
40#include <asm-generic/pgtable.h>
41
42
43/*
44 * This gets called at the end of handling a page fault, when
45 * the kernel has put a new PTE into the page table for the process.
46 * We use it to ensure coherency between the i-cache and d-cache
47 * for the page which has just been mapped in.
48 * On machines which use an MMU hash table, we use this to put a
49 * corresponding HPTE into the hash table ahead of time, instead of
50 * waiting for the inevitable extra hash-table miss exception.
51 */
52extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
53
54#endif /* __ASSEMBLY__ */
55
56#endif /* __KERNEL__ */
57#endif /* _ASM_POWERPC_PGTABLE_H */
diff --git a/arch/powerpc/include/asm/phyp_dump.h b/arch/powerpc/include/asm/phyp_dump.h
new file mode 100644
index 000000000000..fa74c6c3e106
--- /dev/null
+++ b/arch/powerpc/include/asm/phyp_dump.h
@@ -0,0 +1,47 @@
1/*
2 * Hypervisor-assisted dump
3 *
4 * Linas Vepstas, Manish Ahuja 2008
5 * Copyright 2008 IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _PPC64_PHYP_DUMP_H
14#define _PPC64_PHYP_DUMP_H
15
16#ifdef CONFIG_PHYP_DUMP
17
18/* The RMR region will be saved for later dumping
19 * whenever the kernel crashes. Set this to 256MB. */
20#define PHYP_DUMP_RMR_START 0x0
21#define PHYP_DUMP_RMR_END (1UL<<28)
22
23struct phyp_dump {
24 /* Memory that is reserved during very early boot. */
25 unsigned long init_reserve_start;
26 unsigned long init_reserve_size;
27 /* cmd line options during boot */
28 unsigned long reserve_bootvar;
29 unsigned long phyp_dump_at_boot;
30 /* Check status during boot if dump supported, active & present*/
31 unsigned long phyp_dump_configured;
32 unsigned long phyp_dump_is_active;
33 /* store cpu & hpte size */
34 unsigned long cpu_state_size;
35 unsigned long hpte_region_size;
36 /* previous scratch area values */
37 unsigned long reserved_scratch_addr;
38 unsigned long reserved_scratch_size;
39};
40
41extern struct phyp_dump *phyp_dump_info;
42
43int early_init_dt_scan_phyp_dump(unsigned long node,
44 const char *uname, int depth, void *data);
45
46#endif /* CONFIG_PHYP_DUMP */
47#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
new file mode 100644
index 000000000000..877c35a4356e
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -0,0 +1,405 @@
1/*
2 * Definition of platform feature hooks for PowerMacs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Paul Mackerras &
9 * Ben. Herrenschmidt.
10 *
11 *
12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
14 * ASIC registers.
15 *
16 * Implementation note: Currently, none of these functions will block.
17 * However, they may internally protect themselves with a spinlock
18 * for way too long. Be prepared for at least some of these to block
19 * in the future.
20 *
21 * Unless specifically defined, the result code is assumed to be an
22 * error when negative, 0 is the default success result. Some functions
23 * may return additional positive result values.
24 *
25 * To keep implementation simple, all feature calls are assumed to have
26 * the prototype parameters (struct device_node* node, int value).
27 * When either is not used, pass 0.
28 */
29
30#ifdef __KERNEL__
31#ifndef __ASM_POWERPC_PMAC_FEATURE_H
32#define __ASM_POWERPC_PMAC_FEATURE_H
33
34#include <asm/macio.h>
35#include <asm/machdep.h>
36
37/*
38 * Known Mac motherboard models
39 *
40 * Please, report any error here to benh@kernel.crashing.org, thanks !
41 *
42 * Note that I don't fully maintain this list for Core99 & MacRISC2
43 * and I'm considering removing all NewWorld entries from it and
44 * entirely rely on the model string.
45 */
46
47/* PowerSurge are the first generation of PCI Pmacs. This include
48 * all of the Grand-Central based machines. We currently don't
49 * differenciate most of them.
50 */
51#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52#define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
53
54/* Here is the infamous serie of OHare based machines
55 */
56#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */
57#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */
58#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */
59#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */
60#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */
61#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */
62
63/* Here are the Heathrow based machines
64 * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
65 */
66#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */
67#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */
68#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/
69#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */
70
71/* Here are newworld machines based on Paddington (heathrow derivative)
72 */
73#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */
74#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */
75#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */
76#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */
77#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
78
79/* Core99 machines based on UniNorth 1.0 and 1.5
80 *
81 * Note: A single entry here may cover several actual models according
82 * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
83 * FireWire based iMacs, etc...). Those machines are too similar to be
84 * distinguished here, when they need to be differencied, use the
85 * device-tree "model" or "compatible" property.
86 */
87#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */
88#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */
89#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */
90#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */
91#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */
92#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
93#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
94#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
95#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
98#define PMAC_TYPE_EMAC 0x50 /* eMac */
99#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
100
101/* MacRisc2 with UniNorth 2.0 */
102#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
103#define PMAC_TYPE_WINDTUNNEL 0x81
104
105/* MacRISC2 machines based on the Pangea chipset
106 */
107#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
108#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */
109#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
110#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
111
112/* MacRISC2 machines based on the Intrepid chipset
113 */
114#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
115
116/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
117 * but rather machine families
118 */
119#define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */
120#define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124#define PMAC_TYPE_UNKNOWN_SHASTA 0x19e /* Any other Shasta based */
125
126/*
127 * Motherboard flags
128 */
129
130#define PMAC_MB_CAN_SLEEP 0x00000001
131#define PMAC_MB_HAS_FW_POWER 0x00000002
132#define PMAC_MB_OLD_CORE99 0x00000004
133#define PMAC_MB_MOBILE 0x00000008
134#define PMAC_MB_MAY_SLEEP 0x00000010
135
136/*
137 * Feature calls supported on pmac
138 *
139 */
140
141/*
142 * Use this inline wrapper
143 */
144struct device_node;
145
146static inline long pmac_call_feature(int selector, struct device_node* node,
147 long param, long value)
148{
149 if (!ppc_md.feature_call || !machine_is(powermac))
150 return -ENODEV;
151 return ppc_md.feature_call(selector, node, param, value);
152}
153
154/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value)
155 * enable/disable an SCC side. Pass the node corresponding to the
156 * channel side as a parameter.
157 * param is the type of port
158 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
159 * for use by xmon.
160 */
161#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0)
162 #define PMAC_SCC_ASYNC 0
163 #define PMAC_SCC_IRDA 1
164 #define PMAC_SCC_I2S1 2
165 #define PMAC_SCC_FLAG_XMON 0x00001000
166
167/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value)
168 * enable/disable the internal modem.
169 */
170#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1)
171
172/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value)
173 * enable/disable the swim3 (floppy) cell of a mac-io ASIC
174 */
175#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2)
176
177/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value)
178 * enable/disable the mesh (scsi) cell of a mac-io ASIC
179 */
180#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3)
181
182/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value)
183 * enable/disable an IDE port of a mac-io ASIC
184 * pass the busID parameter
185 */
186#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4)
187
188/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value)
189 * assert(1)/release(0) an IDE reset line (mac-io IDE only)
190 */
191#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5)
192
193/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
194 * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
195 * it's reset line
196 */
197#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
198
199/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value)
200 * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
201 * control the cell's clock.
202 */
203#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7)
204
205/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0)
206 * Perform a HW reset of the PHY connected to a gmac controller.
207 * Pass the gmac device node, not the PHY node.
208 */
209#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8)
210
211/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
212 * enable/disable the sound chip, whatever it is and provided it can
213 * acually be controlled
214 */
215#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
216
217/* -- add various tweaks related to sound routing -- */
218
219/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
220 * enable/disable the airport card
221 */
222#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10)
223
224/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0)
225 * toggle the reset line of a CPU on an uninorth-based SMP machine
226 */
227#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11)
228
229/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value)
230 * enable/disable an USB cell, along with the power of the USB "pad"
231 * on keylargo based machines
232 */
233#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12)
234
235/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value)
236 * enable/disable the firewire cell of an uninorth ASIC.
237 */
238#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13)
239
240/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value)
241 * enable/disable the firewire cable power supply of the uninorth
242 * firewire cell
243 */
244#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14)
245
246/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value)
247 * set the sleep state of the motherboard.
248 *
249 * Pass -1 as value to query for sleep capability
250 * Pass 1 to set IOs to sleep
251 * Pass 0 to set IOs to wake
252 */
253#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
254
255/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
256 *
257 * returns some motherboard infos.
258 * selector: 0 - model id
259 * 1 - model flags (capabilities)
260 * 2 - model name (cast to const char *)
261 */
262#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16)
263#define PMAC_MB_INFO_MODEL 0
264#define PMAC_MB_INFO_FLAGS 1
265#define PMAC_MB_INFO_NAME 2
266
267/* PMAC_FTR_READ_GPIO (NULL, int index, 0)
268 *
269 * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
270 * the value returned is a byte (positive), or a negative error code
271 */
272#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17)
273
274/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value)
275 *
276 * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
277 */
278#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18)
279
280/* PMAC_FTR_ENABLE_MPIC
281 *
282 * Enable the MPIC cell
283 */
284#define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19)
285
286/* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0)
287 *
288 * Enable/disable the AACK delay on the northbridge for systems using DFS
289 */
290#define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20)
291
292/* PMAC_FTR_DEVICE_CAN_WAKE
293 *
294 * Used by video drivers to inform system that they can actually perform
295 * wakeup from sleep
296 */
297#define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22)
298
299
300/* Don't use those directly, they are for the sake of pmac_setup.c */
301extern long pmac_do_feature_call(unsigned int selector, ...);
302extern void pmac_feature_init(void);
303
304/* Video suspend tweak */
305extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
306extern void pmac_call_early_video_resume(void);
307
308#define PMAC_FTR_DEF(x) ((0x6660000) | (x))
309
310/* The AGP driver registers itself here */
311extern void pmac_register_agp_pm(struct pci_dev *bridge,
312 int (*suspend)(struct pci_dev *bridge),
313 int (*resume)(struct pci_dev *bridge));
314
315/* Those are meant to be used by video drivers to deal with AGP
316 * suspend resume properly
317 */
318extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
319extern void pmac_resume_agp_for_card(struct pci_dev *dev);
320
321/*
322 * The part below is for use by macio_asic.c only, do not rely
323 * on the data structures or constants below in a normal driver
324 *
325 */
326
327#define MAX_MACIO_CHIPS 2
328
329enum {
330 macio_unknown = 0,
331 macio_grand_central,
332 macio_ohare,
333 macio_ohareII,
334 macio_heathrow,
335 macio_gatwick,
336 macio_paddington,
337 macio_keylargo,
338 macio_pangea,
339 macio_intrepid,
340 macio_keylargo2,
341 macio_shasta,
342};
343
344struct macio_chip
345{
346 struct device_node *of_node;
347 int type;
348 const char *name;
349 int rev;
350 volatile u32 __iomem *base;
351 unsigned long flags;
352
353 /* For use by macio_asic PCI driver */
354 struct macio_bus lbus;
355};
356
357extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
358
359#define MACIO_FLAG_SCCA_ON 0x00000001
360#define MACIO_FLAG_SCCB_ON 0x00000002
361#define MACIO_FLAG_SCC_LOCKED 0x00000004
362#define MACIO_FLAG_AIRPORT_ON 0x00000010
363#define MACIO_FLAG_FW_SUPPORTED 0x00000020
364
365extern struct macio_chip* macio_find(struct device_node* child, int type);
366
367#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
368#define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r))
369
370#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
371#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
372#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
373#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
374#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
375#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
376
377/*
378 * Those are exported by pmac feature for internal use by arch code
379 * only like the platform function callbacks, do not use directly in drivers
380 */
381extern spinlock_t feature_lock;
382extern struct device_node *uninorth_node;
383extern u32 __iomem *uninorth_base;
384
385/*
386 * Uninorth reg. access. Note that Uni-N regs are big endian
387 */
388
389#define UN_REG(r) (uninorth_base + ((r) >> 2))
390#define UN_IN(r) (in_be32(UN_REG(r)))
391#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
392#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
393#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
394
395/* Uninorth variant:
396 *
397 * 0 = not uninorth
398 * 1 = U1.x or U2.x
399 * 3 = U3
400 * 4 = U4
401 */
402extern int pmac_get_uninorth_variant(void);
403
404#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
405#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/pmac_low_i2c.h b/arch/powerpc/include/asm/pmac_low_i2c.h
new file mode 100644
index 000000000000..131011bd7e76
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_low_i2c.h
@@ -0,0 +1,107 @@
1/*
2 * include/asm-ppc/pmac_low_i2c.h
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#ifndef __PMAC_LOW_I2C_H__
13#define __PMAC_LOW_I2C_H__
14#ifdef __KERNEL__
15
16/* i2c mode (based on the platform functions format) */
17enum {
18 pmac_i2c_mode_dumb = 1,
19 pmac_i2c_mode_std = 2,
20 pmac_i2c_mode_stdsub = 3,
21 pmac_i2c_mode_combined = 4,
22};
23
24/* RW bit in address */
25enum {
26 pmac_i2c_read = 0x01,
27 pmac_i2c_write = 0x00
28};
29
30/* i2c bus type */
31enum {
32 pmac_i2c_bus_keywest = 0,
33 pmac_i2c_bus_pmu = 1,
34 pmac_i2c_bus_smu = 2,
35};
36
37/* i2c bus features */
38enum {
39 /* can_largesub : supports >1 byte subaddresses (SMU only) */
40 pmac_i2c_can_largesub = 0x00000001u,
41
42 /* multibus : device node holds multiple busses, bus number is
43 * encoded in bits 0xff00 of "reg" of a given device
44 */
45 pmac_i2c_multibus = 0x00000002u,
46};
47
48/* i2c busses in the system */
49struct pmac_i2c_bus;
50struct i2c_adapter;
51
52/* Init, called early during boot */
53extern int pmac_i2c_init(void);
54
55/* Lookup an i2c bus for a device-node. The node can be either the bus
56 * node itself or a device below it. In the case of a multibus, the bus
57 * node itself is the controller node, else, it's a child of the controller
58 * node
59 */
60extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
61
62/* Get the address for an i2c device. This strips the bus number if
63 * necessary. The 7 bits address is returned 1 bit right shifted so that the
64 * direction can be directly ored in
65 */
66extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
67
68/* Get infos about a bus */
69extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
70extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
71extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
72extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
73extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
74
75/* i2c layer adapter attach/detach */
76extern void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
77 struct i2c_adapter *adapter);
78extern void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
79 struct i2c_adapter *adapter);
80extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
81extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
82
83/* March a device or bus with an i2c adapter structure, to be used by drivers
84 * to match device-tree nodes with i2c adapters during adapter discovery
85 * callbacks
86 */
87extern int pmac_i2c_match_adapter(struct device_node *dev,
88 struct i2c_adapter *adapter);
89
90
91/* (legacy) Locking functions exposed to i2c-keywest */
92extern int pmac_low_i2c_lock(struct device_node *np);
93extern int pmac_low_i2c_unlock(struct device_node *np);
94
95/* Access functions for platform code */
96extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
97extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
98extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
99extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
100 u32 subaddr, u8 *data, int len);
101
102/* Suspend/resume code called by via-pmu directly for now */
103extern void pmac_pfunc_i2c_suspend(void);
104extern void pmac_pfunc_i2c_resume(void);
105
106#endif /* __KERNEL__ */
107#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/arch/powerpc/include/asm/pmac_pfunc.h b/arch/powerpc/include/asm/pmac_pfunc.h
new file mode 100644
index 000000000000..1330d6a58c57
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_pfunc.h
@@ -0,0 +1,252 @@
1#ifndef __PMAC_PFUNC_H__
2#define __PMAC_PFUNC_H__
3
4#include <linux/types.h>
5#include <linux/list.h>
6
7/* Flags in command lists */
8#define PMF_FLAGS_ON_INIT 0x80000000u
9#define PMF_FLGAS_ON_TERM 0x40000000u
10#define PMF_FLAGS_ON_SLEEP 0x20000000u
11#define PMF_FLAGS_ON_WAKE 0x10000000u
12#define PMF_FLAGS_ON_DEMAND 0x08000000u
13#define PMF_FLAGS_INT_GEN 0x04000000u
14#define PMF_FLAGS_HIGH_SPEED 0x02000000u
15#define PMF_FLAGS_LOW_SPEED 0x01000000u
16#define PMF_FLAGS_SIDE_EFFECTS 0x00800000u
17
18/*
19 * Arguments to a platform function call.
20 *
21 * NOTE: By convention, pointer arguments point to an u32
22 */
23struct pmf_args {
24 union {
25 u32 v;
26 u32 *p;
27 } u[4];
28 unsigned int count;
29};
30
31/*
32 * A driver capable of interpreting commands provides a handlers
33 * structure filled with whatever handlers are implemented by this
34 * driver. Non implemented handlers are left NULL.
35 *
36 * PMF_STD_ARGS are the same arguments that are passed to the parser
37 * and that gets passed back to the various handlers.
38 *
39 * Interpreting a given function always start with a begin() call which
40 * returns an instance data to be passed around subsequent calls, and
41 * ends with an end() call. This allows the low level driver to implement
42 * locking policy or per-function instance data.
43 *
44 * For interrupt capable functions, irq_enable() is called when a client
45 * registers, and irq_disable() is called when the last client unregisters
46 * Note that irq_enable & irq_disable are called within a semaphore held
47 * by the core, thus you should not try to register yourself to some other
48 * pmf interrupt during those calls.
49 */
50
51#define PMF_STD_ARGS struct pmf_function *func, void *instdata, \
52 struct pmf_args *args
53
54struct pmf_function;
55
56struct pmf_handlers {
57 void * (*begin)(struct pmf_function *func, struct pmf_args *args);
58 void (*end)(struct pmf_function *func, void *instdata);
59
60 int (*irq_enable)(struct pmf_function *func);
61 int (*irq_disable)(struct pmf_function *func);
62
63 int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask);
64 int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor);
65
66 int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
67 int (*read_reg32)(PMF_STD_ARGS, u32 offset);
68 int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
69 int (*read_reg16)(PMF_STD_ARGS, u32 offset);
70 int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
71 int (*read_reg8)(PMF_STD_ARGS, u32 offset);
72
73 int (*delay)(PMF_STD_ARGS, u32 duration);
74
75 int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
76 int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
77 int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
78
79 int (*read_i2c)(PMF_STD_ARGS, u32 len);
80 int (*write_i2c)(PMF_STD_ARGS, u32 len, const u8 *data);
81 int (*rmw_i2c)(PMF_STD_ARGS, u32 masklen, u32 valuelen, u32 totallen,
82 const u8 *maskdata, const u8 *valuedata);
83
84 int (*read_cfg)(PMF_STD_ARGS, u32 offset, u32 len);
85 int (*write_cfg)(PMF_STD_ARGS, u32 offset, u32 len, const u8 *data);
86 int (*rmw_cfg)(PMF_STD_ARGS, u32 offset, u32 masklen, u32 valuelen,
87 u32 totallen, const u8 *maskdata, const u8 *valuedata);
88
89 int (*read_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len);
90 int (*write_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len, const u8 *data);
91 int (*set_i2c_mode)(PMF_STD_ARGS, int mode);
92 int (*rmw_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 masklen, u32 valuelen,
93 u32 totallen, const u8 *maskdata,
94 const u8 *valuedata);
95
96 int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
97 u32 xor);
98 int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
99 u32 xor);
100 int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
101 u32 xor);
102
103 int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
104 int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
105 int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
106
107 int (*mask_and_compare)(PMF_STD_ARGS, u32 len, const u8 *maskdata,
108 const u8 *valuedata);
109
110 struct module *owner;
111};
112
113
114/*
115 * Drivers who expose platform functions register at init time, this
116 * causes the platform functions for that device node to be parsed in
117 * advance and associated with the device. The data structures are
118 * partially public so a driver can walk the list of platform functions
119 * and eventually inspect the flags
120 */
121struct pmf_device;
122
123struct pmf_function {
124 /* All functions for a given driver are linked */
125 struct list_head link;
126
127 /* Function node & driver data */
128 struct device_node *node;
129 void *driver_data;
130
131 /* For internal use by core */
132 struct pmf_device *dev;
133
134 /* The name is the "xxx" in "platform-do-xxx", this is how
135 * platform functions are identified by this code. Some functions
136 * only operate for a given target, in which case the phandle is
137 * here (or 0 if the filter doesn't apply)
138 */
139 const char *name;
140 u32 phandle;
141
142 /* The flags for that function. You can have several functions
143 * with the same name and different flag
144 */
145 u32 flags;
146
147 /* The actual tokenized function blob */
148 const void *data;
149 unsigned int length;
150
151 /* Interrupt clients */
152 struct list_head irq_clients;
153
154 /* Refcounting */
155 struct kref ref;
156};
157
158/*
159 * For platform functions that are interrupts, one can register
160 * irq_client structures. You canNOT use the same structure twice
161 * as it contains a link member. Also, the callback is called with
162 * a spinlock held, you must not call back into any of the pmf_* functions
163 * from within that callback
164 */
165struct pmf_irq_client {
166 void (*handler)(void *data);
167 void *data;
168 struct module *owner;
169 struct list_head link;
170 struct pmf_function *func;
171};
172
173
174/*
175 * Register/Unregister a function-capable driver and its handlers
176 */
177extern int pmf_register_driver(struct device_node *np,
178 struct pmf_handlers *handlers,
179 void *driverdata);
180
181extern void pmf_unregister_driver(struct device_node *np);
182
183
184/*
185 * Register/Unregister interrupt clients
186 */
187extern int pmf_register_irq_client(struct device_node *np,
188 const char *name,
189 struct pmf_irq_client *client);
190
191extern void pmf_unregister_irq_client(struct pmf_irq_client *client);
192
193/*
194 * Called by the handlers when an irq happens
195 */
196extern void pmf_do_irq(struct pmf_function *func);
197
198
199/*
200 * Low level call to platform functions.
201 *
202 * The phandle can filter on the target object for functions that have
203 * multiple targets, the flags allow you to restrict the call to a given
204 * combination of flags.
205 *
206 * The args array contains as many arguments as is required by the function,
207 * this is dependent on the function you are calling, unfortunately Apple
208 * mechanism provides no way to encode that so you have to get it right at
209 * the call site. Some functions require no args, in which case, you can
210 * pass NULL.
211 *
212 * You can also pass NULL to the name. This will match any function that has
213 * the appropriate combination of flags & phandle or you can pass 0 to the
214 * phandle to match any
215 */
216extern int pmf_do_functions(struct device_node *np, const char *name,
217 u32 phandle, u32 flags, struct pmf_args *args);
218
219
220
221/*
222 * High level call to a platform function.
223 *
224 * This one looks for the platform-xxx first so you should call it to the
225 * actual target if any. It will fallback to platform-do-xxx if it can't
226 * find one. It will also exclusively target functions that have
227 * the "OnDemand" flag.
228 */
229
230extern int pmf_call_function(struct device_node *target, const char *name,
231 struct pmf_args *args);
232
233
234/*
235 * For low latency interrupt usage, you can lookup for on-demand functions
236 * using the functions below
237 */
238
239extern struct pmf_function *pmf_find_function(struct device_node *target,
240 const char *name);
241
242extern struct pmf_function * pmf_get_function(struct pmf_function *func);
243extern void pmf_put_function(struct pmf_function *func);
244
245extern int pmf_call_one(struct pmf_function *func, struct pmf_args *args);
246
247
248/* Suspend/resume code called by via-pmu directly for now */
249extern void pmac_pfunc_base_suspend(void);
250extern void pmac_pfunc_base_resume(void);
251
252#endif /* __PMAC_PFUNC_H__ */
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
new file mode 100644
index 000000000000..d6a616a1b3ea
--- /dev/null
+++ b/arch/powerpc/include/asm/pmc.h
@@ -0,0 +1,37 @@
1/*
2 * pmc.h
3 * Copyright (C) 2004 David Gibson, IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _POWERPC_PMC_H
20#define _POWERPC_PMC_H
21#ifdef __KERNEL__
22
23#include <asm/ptrace.h>
24
25typedef void (*perf_irq_t)(struct pt_regs *);
26extern perf_irq_t perf_irq;
27
28int reserve_pmc_hardware(perf_irq_t new_perf_irq);
29void release_pmc_hardware(void);
30
31#ifdef CONFIG_PPC64
32void power4_enable_pmcs(void);
33void pasemi_enable_pmcs(void);
34#endif
35
36#endif /* __KERNEL__ */
37#endif /* _POWERPC_PMC_H */
diff --git a/arch/powerpc/include/asm/pmi.h b/arch/powerpc/include/asm/pmi.h
new file mode 100644
index 000000000000..b4e91fbf5081
--- /dev/null
+++ b/arch/powerpc/include/asm/pmi.h
@@ -0,0 +1,66 @@
1#ifndef _POWERPC_PMI_H
2#define _POWERPC_PMI_H
3
4/*
5 * Definitions for talking with PMI device on PowerPC
6 *
7 * PMI (Platform Management Interrupt) is a way to communicate
8 * with the BMC (Baseboard Management Controller) via interrupts.
9 * Unlike IPMI it is bidirectional and has a low latency.
10 *
11 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
12 *
13 * Author: Christian Krafft <krafft@de.ibm.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifdef __KERNEL__
31
32#define PMI_TYPE_FREQ_CHANGE 0x01
33#define PMI_TYPE_POWER_BUTTON 0x02
34#define PMI_READ_TYPE 0
35#define PMI_READ_DATA0 1
36#define PMI_READ_DATA1 2
37#define PMI_READ_DATA2 3
38#define PMI_WRITE_TYPE 4
39#define PMI_WRITE_DATA0 5
40#define PMI_WRITE_DATA1 6
41#define PMI_WRITE_DATA2 7
42
43#define PMI_ACK 0x80
44
45#define PMI_TIMEOUT 100
46
47typedef struct {
48 u8 type;
49 u8 data0;
50 u8 data1;
51 u8 data2;
52} pmi_message_t;
53
54struct pmi_handler {
55 struct list_head node;
56 u8 type;
57 void (*handle_pmi_message) (pmi_message_t);
58};
59
60int pmi_register_handler(struct pmi_handler *);
61void pmi_unregister_handler(struct pmi_handler *);
62
63int pmi_send_message(pmi_message_t);
64
65#endif /* __KERNEL__ */
66#endif /* _POWERPC_PMI_H */
diff --git a/arch/powerpc/include/asm/poll.h b/arch/powerpc/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/powerpc/include/asm/poll.h
@@ -0,0 +1 @@
#include <asm-generic/poll.h>
diff --git a/arch/powerpc/include/asm/posix_types.h b/arch/powerpc/include/asm/posix_types.h
new file mode 100644
index 000000000000..c4e396b540df
--- /dev/null
+++ b/arch/powerpc/include/asm/posix_types.h
@@ -0,0 +1,128 @@
1#ifndef _ASM_POWERPC_POSIX_TYPES_H
2#define _ASM_POWERPC_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned int __kernel_mode_t;
12typedef long __kernel_off_t;
13typedef int __kernel_pid_t;
14typedef unsigned int __kernel_uid_t;
15typedef unsigned int __kernel_gid_t;
16typedef long __kernel_ptrdiff_t;
17typedef long __kernel_time_t;
18typedef long __kernel_clock_t;
19typedef int __kernel_timer_t;
20typedef int __kernel_clockid_t;
21typedef long __kernel_suseconds_t;
22typedef int __kernel_daddr_t;
23typedef char * __kernel_caddr_t;
24typedef unsigned short __kernel_uid16_t;
25typedef unsigned short __kernel_gid16_t;
26typedef unsigned int __kernel_uid32_t;
27typedef unsigned int __kernel_gid32_t;
28typedef unsigned int __kernel_old_uid_t;
29typedef unsigned int __kernel_old_gid_t;
30
31#ifdef __powerpc64__
32typedef unsigned long __kernel_nlink_t;
33typedef int __kernel_ipc_pid_t;
34typedef unsigned long __kernel_size_t;
35typedef long __kernel_ssize_t;
36typedef unsigned long __kernel_old_dev_t;
37#else
38typedef unsigned short __kernel_nlink_t;
39typedef short __kernel_ipc_pid_t;
40typedef unsigned int __kernel_size_t;
41typedef int __kernel_ssize_t;
42typedef unsigned int __kernel_old_dev_t;
43#endif
44
45#ifdef __powerpc64__
46typedef long long __kernel_loff_t;
47#else
48#ifdef __GNUC__
49typedef long long __kernel_loff_t;
50#endif
51#endif
52
53typedef struct {
54 int val[2];
55} __kernel_fsid_t;
56
57#ifndef __GNUC__
58
59#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
60#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
61#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
62#define __FD_ZERO(set) \
63 ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
64
65#else /* __GNUC__ */
66
67#if defined(__KERNEL__)
68/* With GNU C, use inline functions instead so args are evaluated only once: */
69
70#undef __FD_SET
71static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
72{
73 unsigned long _tmp = fd / __NFDBITS;
74 unsigned long _rem = fd % __NFDBITS;
75 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
76}
77
78#undef __FD_CLR
79static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
80{
81 unsigned long _tmp = fd / __NFDBITS;
82 unsigned long _rem = fd % __NFDBITS;
83 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
84}
85
86#undef __FD_ISSET
87static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
88{
89 unsigned long _tmp = fd / __NFDBITS;
90 unsigned long _rem = fd % __NFDBITS;
91 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
92}
93
94/*
95 * This will unroll the loop for the normal constant case (8 ints,
96 * for a 256-bit fd_set)
97 */
98#undef __FD_ZERO
99static __inline__ void __FD_ZERO(__kernel_fd_set *p)
100{
101 unsigned long *tmp = (unsigned long *)p->fds_bits;
102 int i;
103
104 if (__builtin_constant_p(__FDSET_LONGS)) {
105 switch (__FDSET_LONGS) {
106 case 16:
107 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
108 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
109
110 case 8:
111 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
112
113 case 4:
114 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
115 return;
116 }
117 }
118 i = __FDSET_LONGS;
119 while (i) {
120 i--;
121 *tmp = 0;
122 tmp++;
123 }
124}
125
126#endif /* defined(__KERNEL__) */
127#endif /* __GNUC__ */
128#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
new file mode 100644
index 000000000000..854ab713f56c
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -0,0 +1,149 @@
1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef _ASM_POWERPC_PPC_PCI_H
10#define _ASM_POWERPC_PPC_PCI_H
11#ifdef __KERNEL__
12
13#ifdef CONFIG_PCI
14
15#include <linux/pci.h>
16#include <asm/pci-bridge.h>
17
18extern unsigned long isa_io_base;
19
20extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
21extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
22
23
24extern struct list_head hose_list;
25
26extern void find_and_init_phbs(void);
27
28extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
29
30/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
31#define BUID_HI(buid) ((buid) >> 32)
32#define BUID_LO(buid) ((buid) & 0xffffffff)
33
34/* PCI device_node operations */
35struct device_node;
36typedef void *(*traverse_func)(struct device_node *me, void *data);
37void *traverse_pci_devices(struct device_node *start, traverse_func pre,
38 void *data);
39
40extern void pci_devs_phb_init(void);
41extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
42extern void scan_phb(struct pci_controller *hose);
43
44/* From rtas_pci.h */
45extern void init_pci_config_tokens (void);
46extern unsigned long get_phb_buid (struct device_node *);
47extern int rtas_setup_phb(struct pci_controller *phb);
48
49extern unsigned long pci_probe_only;
50
51/* ---- EEH internal-use-only related routines ---- */
52#ifdef CONFIG_EEH
53
54void pci_addr_cache_insert_device(struct pci_dev *dev);
55void pci_addr_cache_remove_device(struct pci_dev *dev);
56void pci_addr_cache_build(void);
57struct pci_dev *pci_get_device_by_addr(unsigned long addr);
58
59/**
60 * eeh_slot_error_detail -- record and EEH error condition to the log
61 * @pdn: pci device node
62 * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE
63 *
64 * Obtains the EEH error details from the RTAS subsystem,
65 * and then logs these details with the RTAS error log system.
66 */
67#define EEH_LOG_TEMP_FAILURE 1
68#define EEH_LOG_PERM_FAILURE 2
69void eeh_slot_error_detail (struct pci_dn *pdn, int severity);
70
71/**
72 * rtas_pci_enable - enable IO transfers for this slot
73 * @pdn: pci device node
74 * @function: either EEH_THAW_MMIO or EEH_THAW_DMA
75 *
76 * Enable I/O transfers to this slot
77 */
78#define EEH_THAW_MMIO 2
79#define EEH_THAW_DMA 3
80int rtas_pci_enable(struct pci_dn *pdn, int function);
81
82/**
83 * rtas_set_slot_reset -- unfreeze a frozen slot
84 * @pdn: pci device node
85 *
86 * Clear the EEH-frozen condition on a slot. This routine
87 * does this by asserting the PCI #RST line for 1/8th of
88 * a second; this routine will sleep while the adapter is
89 * being reset.
90 *
91 * Returns a non-zero value if the reset failed.
92 */
93int rtas_set_slot_reset (struct pci_dn *);
94int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs);
95
96/**
97 * eeh_restore_bars - Restore device configuration info.
98 * @pdn: pci device node
99 *
100 * A reset of a PCI device will clear out its config space.
101 * This routines will restore the config space for this
102 * device, and is children, to values previously obtained
103 * from the firmware.
104 */
105void eeh_restore_bars(struct pci_dn *);
106
107/**
108 * rtas_configure_bridge -- firmware initialization of pci bridge
109 * @pdn: pci device node
110 *
111 * Ask the firmware to configure all PCI bridges devices
112 * located behind the indicated node. Required after a
113 * pci device reset. Does essentially the same hing as
114 * eeh_restore_bars, but for brdges, and lets firmware
115 * do the work.
116 */
117void rtas_configure_bridge(struct pci_dn *);
118
119int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
120int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
121
122/**
123 * eeh_mark_slot -- set mode flags for pertition endpoint
124 * @pdn: pci device node
125 *
126 * mark and clear slots: find "partition endpoint" PE and set or
127 * clear the flags for each subnode of the PE.
128 */
129void eeh_mark_slot (struct device_node *dn, int mode_flag);
130void eeh_clear_slot (struct device_node *dn, int mode_flag);
131
132/**
133 * find_device_pe -- Find the associated "Partiationable Endpoint" PE
134 * @pdn: pci device node
135 */
136struct device_node * find_device_pe(struct device_node *dn);
137
138void eeh_sysfs_add_device(struct pci_dev *pdev);
139void eeh_sysfs_remove_device(struct pci_dev *pdev);
140
141#endif /* CONFIG_EEH */
142
143#else /* CONFIG_PCI */
144static inline void find_and_init_phbs(void) { }
145static inline void init_pci_config_tokens(void) { }
146#endif /* !CONFIG_PCI */
147
148#endif /* __KERNEL__ */
149#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
new file mode 100644
index 000000000000..033039a80c42
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -0,0 +1,18 @@
1/*
2 * PPC4xx Prototypes and definitions
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_POWERPC_PPC4xx_H__
14#define __ASM_POWERPC_PPC4xx_H__
15
16extern void ppc4xx_reset_system(char *cmd);
17
18#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
new file mode 100644
index 000000000000..0966899d974b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -0,0 +1,689 @@
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <asm/asm-compat.h>
9#include <asm/processor.h>
10
11#ifndef __ASSEMBLY__
12#error __FILE__ should only be used in assembler files
13#else
14
15#define SZL (BITS_PER_LONG/8)
16
17/*
18 * Stuff for accurate CPU time accounting.
19 * These macros handle transitions between user and system state
20 * in exception entry and exit and accumulate time to the
21 * user_time and system_time fields in the paca.
22 */
23
24#ifndef CONFIG_VIRT_CPU_ACCOUNTING
25#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
26#define ACCOUNT_CPU_USER_EXIT(ra, rb)
27#else
28#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
29 beq 2f; /* if from kernel mode */ \
30BEGIN_FTR_SECTION; \
31 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
32END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
33BEGIN_FTR_SECTION; \
34 MFTB(ra); /* or get TB if no PURR */ \
35END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
36 ld rb,PACA_STARTPURR(r13); \
37 std ra,PACA_STARTPURR(r13); \
38 subf rb,rb,ra; /* subtract start value */ \
39 ld ra,PACA_USER_TIME(r13); \
40 add ra,ra,rb; /* add on to user time */ \
41 std ra,PACA_USER_TIME(r13); \
422:
43
44#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
45BEGIN_FTR_SECTION; \
46 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
47END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
48BEGIN_FTR_SECTION; \
49 MFTB(ra); /* or get TB if no PURR */ \
50END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
51 ld rb,PACA_STARTPURR(r13); \
52 std ra,PACA_STARTPURR(r13); \
53 subf rb,rb,ra; /* subtract start value */ \
54 ld ra,PACA_SYSTEM_TIME(r13); \
55 add ra,ra,rb; /* add on to user time */ \
56 std ra,PACA_SYSTEM_TIME(r13);
57#endif
58
59/*
60 * Macros for storing registers into and loading registers from
61 * exception frames.
62 */
63#ifdef __powerpc64__
64#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
65#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
66#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
67#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
68#else
69#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
70#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
71#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
72 SAVE_10GPRS(22, base)
73#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
74 REST_10GPRS(22, base)
75#endif
76
77/*
78 * Define what the VSX XX1 form instructions will look like, then add
79 * the 128 bit load store instructions based on that.
80 */
81#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
82 ((rb) << 11) | (((xs) >> 5)))
83
84#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
85#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
86
87#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
88#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
89#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
90#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
91#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
92#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
93#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
94#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
95
96#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
97#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
98#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
99#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
100#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
101#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
102#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
103#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
104#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
105#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
106#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
107#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
108
109#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
110#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
111#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
112#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
113#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
114#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
115#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
116#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
117#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
118#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
119#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
120#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
121
122/* Save the lower 32 VSRs in the thread VSR region */
123#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
124#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
125#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
126#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
127#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
128#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
129#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
130#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
131#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
132#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
133#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
134#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
135/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
136#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
137#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
138#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
139#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
140#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
141#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
142#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
143#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
144#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
145#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
146#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
147#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
148
149#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
150#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
151#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
152#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
153#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
154#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
155#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
156#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
157#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
158#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
159#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
160#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
161
162/* Macros to adjust thread priority for hardware multithreading */
163#define HMT_VERY_LOW or 31,31,31 # very low priority
164#define HMT_LOW or 1,1,1
165#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
166#define HMT_MEDIUM or 2,2,2
167#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
168#define HMT_HIGH or 3,3,3
169
170/* handle instructions that older assemblers may not know */
171#define RFCI .long 0x4c000066 /* rfci instruction */
172#define RFDI .long 0x4c00004e /* rfdi instruction */
173#define RFMCI .long 0x4c00004c /* rfmci instruction */
174
175#ifdef __KERNEL__
176#ifdef CONFIG_PPC64
177
178#define XGLUE(a,b) a##b
179#define GLUE(a,b) XGLUE(a,b)
180
181#define _GLOBAL(name) \
182 .section ".text"; \
183 .align 2 ; \
184 .globl name; \
185 .globl GLUE(.,name); \
186 .section ".opd","aw"; \
187name: \
188 .quad GLUE(.,name); \
189 .quad .TOC.@tocbase; \
190 .quad 0; \
191 .previous; \
192 .type GLUE(.,name),@function; \
193GLUE(.,name):
194
195#define _INIT_GLOBAL(name) \
196 .section ".text.init.refok"; \
197 .align 2 ; \
198 .globl name; \
199 .globl GLUE(.,name); \
200 .section ".opd","aw"; \
201name: \
202 .quad GLUE(.,name); \
203 .quad .TOC.@tocbase; \
204 .quad 0; \
205 .previous; \
206 .type GLUE(.,name),@function; \
207GLUE(.,name):
208
209#define _KPROBE(name) \
210 .section ".kprobes.text","a"; \
211 .align 2 ; \
212 .globl name; \
213 .globl GLUE(.,name); \
214 .section ".opd","aw"; \
215name: \
216 .quad GLUE(.,name); \
217 .quad .TOC.@tocbase; \
218 .quad 0; \
219 .previous; \
220 .type GLUE(.,name),@function; \
221GLUE(.,name):
222
223#define _STATIC(name) \
224 .section ".text"; \
225 .align 2 ; \
226 .section ".opd","aw"; \
227name: \
228 .quad GLUE(.,name); \
229 .quad .TOC.@tocbase; \
230 .quad 0; \
231 .previous; \
232 .type GLUE(.,name),@function; \
233GLUE(.,name):
234
235#define _INIT_STATIC(name) \
236 .section ".text.init.refok"; \
237 .align 2 ; \
238 .section ".opd","aw"; \
239name: \
240 .quad GLUE(.,name); \
241 .quad .TOC.@tocbase; \
242 .quad 0; \
243 .previous; \
244 .type GLUE(.,name),@function; \
245GLUE(.,name):
246
247#else /* 32-bit */
248
249#define _ENTRY(n) \
250 .globl n; \
251n:
252
253#define _GLOBAL(n) \
254 .text; \
255 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
256 .globl n; \
257n:
258
259#define _KPROBE(n) \
260 .section ".kprobes.text","a"; \
261 .globl n; \
262n:
263
264#endif
265
266/*
267 * LOAD_REG_IMMEDIATE(rn, expr)
268 * Loads the value of the constant expression 'expr' into register 'rn'
269 * using immediate instructions only. Use this when it's important not
270 * to reference other data (i.e. on ppc64 when the TOC pointer is not
271 * valid).
272 *
273 * LOAD_REG_ADDR(rn, name)
274 * Loads the address of label 'name' into register 'rn'. Use this when
275 * you don't particularly need immediate instructions only, but you need
276 * the whole address in one register (e.g. it's a structure address and
277 * you want to access various offsets within it). On ppc32 this is
278 * identical to LOAD_REG_IMMEDIATE.
279 *
280 * LOAD_REG_ADDRBASE(rn, name)
281 * ADDROFF(name)
282 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
283 * register 'rn'. ADDROFF(name) returns the remainder of the address as
284 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
285 * in size, so is suitable for use directly as an offset in load and store
286 * instructions. Use this when loading/storing a single word or less as:
287 * LOAD_REG_ADDRBASE(rX, name)
288 * ld rY,ADDROFF(name)(rX)
289 */
290#ifdef __powerpc64__
291#define LOAD_REG_IMMEDIATE(reg,expr) \
292 lis (reg),(expr)@highest; \
293 ori (reg),(reg),(expr)@higher; \
294 rldicr (reg),(reg),32,31; \
295 oris (reg),(reg),(expr)@h; \
296 ori (reg),(reg),(expr)@l;
297
298#define LOAD_REG_ADDR(reg,name) \
299 ld (reg),name@got(r2)
300
301#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
302#define ADDROFF(name) 0
303
304/* offsets for stack frame layout */
305#define LRSAVE 16
306
307#else /* 32-bit */
308
309#define LOAD_REG_IMMEDIATE(reg,expr) \
310 lis (reg),(expr)@ha; \
311 addi (reg),(reg),(expr)@l;
312
313#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
314
315#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
316#define ADDROFF(name) name@l
317
318/* offsets for stack frame layout */
319#define LRSAVE 4
320
321#endif
322
323/* various errata or part fixups */
324#ifdef CONFIG_PPC601_SYNC_FIX
325#define SYNC \
326BEGIN_FTR_SECTION \
327 sync; \
328 isync; \
329END_FTR_SECTION_IFSET(CPU_FTR_601)
330#define SYNC_601 \
331BEGIN_FTR_SECTION \
332 sync; \
333END_FTR_SECTION_IFSET(CPU_FTR_601)
334#define ISYNC_601 \
335BEGIN_FTR_SECTION \
336 isync; \
337END_FTR_SECTION_IFSET(CPU_FTR_601)
338#else
339#define SYNC
340#define SYNC_601
341#define ISYNC_601
342#endif
343
344#ifdef CONFIG_PPC_CELL
345#define MFTB(dest) \
34690: mftb dest; \
347BEGIN_FTR_SECTION_NESTED(96); \
348 cmpwi dest,0; \
349 beq- 90b; \
350END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
351#else
352#define MFTB(dest) mftb dest
353#endif
354
355#ifndef CONFIG_SMP
356#define TLBSYNC
357#else /* CONFIG_SMP */
358/* tlbsync is not implemented on 601 */
359#define TLBSYNC \
360BEGIN_FTR_SECTION \
361 tlbsync; \
362 sync; \
363END_FTR_SECTION_IFCLR(CPU_FTR_601)
364#endif
365
366
367/*
368 * This instruction is not implemented on the PPC 603 or 601; however, on
369 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
370 * All of these instructions exist in the 8xx, they have magical powers,
371 * and they must be used.
372 */
373
374#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
375#define tlbia \
376 li r4,1024; \
377 mtctr r4; \
378 lis r4,KERNELBASE@h; \
3790: tlbie r4; \
380 addi r4,r4,0x1000; \
381 bdnz 0b
382#endif
383
384
385#ifdef CONFIG_IBM440EP_ERR42
386#define PPC440EP_ERR42 isync
387#else
388#define PPC440EP_ERR42
389#endif
390
391
392#if defined(CONFIG_BOOKE)
393#define toreal(rd)
394#define fromreal(rd)
395
396/*
397 * We use addis to ensure compatibility with the "classic" ppc versions of
398 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
399 * converting the address in r0, and so this version has to do that too
400 * (i.e. set register rd to 0 when rs == 0).
401 */
402#define tophys(rd,rs) \
403 addis rd,rs,0
404
405#define tovirt(rd,rs) \
406 addis rd,rs,0
407
408#elif defined(CONFIG_PPC64)
409#define toreal(rd) /* we can access c000... in real mode */
410#define fromreal(rd)
411
412#define tophys(rd,rs) \
413 clrldi rd,rs,2
414
415#define tovirt(rd,rs) \
416 rotldi rd,rs,16; \
417 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
418 rotldi rd,rd,48
419#else
420/*
421 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
422 * physical base address of RAM at compile time.
423 */
424#define toreal(rd) tophys(rd,rd)
425#define fromreal(rd) tovirt(rd,rd)
426
427#define tophys(rd,rs) \
4280: addis rd,rs,-KERNELBASE@h; \
429 .section ".vtop_fixup","aw"; \
430 .align 1; \
431 .long 0b; \
432 .previous
433
434#define tovirt(rd,rs) \
4350: addis rd,rs,KERNELBASE@h; \
436 .section ".ptov_fixup","aw"; \
437 .align 1; \
438 .long 0b; \
439 .previous
440#endif
441
442#ifdef CONFIG_PPC64
443#define RFI rfid
444#define MTMSRD(r) mtmsrd r
445
446#else
447#define FIX_SRR1(ra, rb)
448#ifndef CONFIG_40x
449#define RFI rfi
450#else
451#define RFI rfi; b . /* Prevent prefetch past rfi */
452#endif
453#define MTMSRD(r) mtmsr r
454#define CLR_TOP32(r)
455#endif
456
457#endif /* __KERNEL__ */
458
459/* The boring bits... */
460
461/* Condition Register Bit Fields */
462
463#define cr0 0
464#define cr1 1
465#define cr2 2
466#define cr3 3
467#define cr4 4
468#define cr5 5
469#define cr6 6
470#define cr7 7
471
472
473/* General Purpose Registers (GPRs) */
474
475#define r0 0
476#define r1 1
477#define r2 2
478#define r3 3
479#define r4 4
480#define r5 5
481#define r6 6
482#define r7 7
483#define r8 8
484#define r9 9
485#define r10 10
486#define r11 11
487#define r12 12
488#define r13 13
489#define r14 14
490#define r15 15
491#define r16 16
492#define r17 17
493#define r18 18
494#define r19 19
495#define r20 20
496#define r21 21
497#define r22 22
498#define r23 23
499#define r24 24
500#define r25 25
501#define r26 26
502#define r27 27
503#define r28 28
504#define r29 29
505#define r30 30
506#define r31 31
507
508
509/* Floating Point Registers (FPRs) */
510
511#define fr0 0
512#define fr1 1
513#define fr2 2
514#define fr3 3
515#define fr4 4
516#define fr5 5
517#define fr6 6
518#define fr7 7
519#define fr8 8
520#define fr9 9
521#define fr10 10
522#define fr11 11
523#define fr12 12
524#define fr13 13
525#define fr14 14
526#define fr15 15
527#define fr16 16
528#define fr17 17
529#define fr18 18
530#define fr19 19
531#define fr20 20
532#define fr21 21
533#define fr22 22
534#define fr23 23
535#define fr24 24
536#define fr25 25
537#define fr26 26
538#define fr27 27
539#define fr28 28
540#define fr29 29
541#define fr30 30
542#define fr31 31
543
544/* AltiVec Registers (VPRs) */
545
546#define vr0 0
547#define vr1 1
548#define vr2 2
549#define vr3 3
550#define vr4 4
551#define vr5 5
552#define vr6 6
553#define vr7 7
554#define vr8 8
555#define vr9 9
556#define vr10 10
557#define vr11 11
558#define vr12 12
559#define vr13 13
560#define vr14 14
561#define vr15 15
562#define vr16 16
563#define vr17 17
564#define vr18 18
565#define vr19 19
566#define vr20 20
567#define vr21 21
568#define vr22 22
569#define vr23 23
570#define vr24 24
571#define vr25 25
572#define vr26 26
573#define vr27 27
574#define vr28 28
575#define vr29 29
576#define vr30 30
577#define vr31 31
578
579/* VSX Registers (VSRs) */
580
581#define vsr0 0
582#define vsr1 1
583#define vsr2 2
584#define vsr3 3
585#define vsr4 4
586#define vsr5 5
587#define vsr6 6
588#define vsr7 7
589#define vsr8 8
590#define vsr9 9
591#define vsr10 10
592#define vsr11 11
593#define vsr12 12
594#define vsr13 13
595#define vsr14 14
596#define vsr15 15
597#define vsr16 16
598#define vsr17 17
599#define vsr18 18
600#define vsr19 19
601#define vsr20 20
602#define vsr21 21
603#define vsr22 22
604#define vsr23 23
605#define vsr24 24
606#define vsr25 25
607#define vsr26 26
608#define vsr27 27
609#define vsr28 28
610#define vsr29 29
611#define vsr30 30
612#define vsr31 31
613#define vsr32 32
614#define vsr33 33
615#define vsr34 34
616#define vsr35 35
617#define vsr36 36
618#define vsr37 37
619#define vsr38 38
620#define vsr39 39
621#define vsr40 40
622#define vsr41 41
623#define vsr42 42
624#define vsr43 43
625#define vsr44 44
626#define vsr45 45
627#define vsr46 46
628#define vsr47 47
629#define vsr48 48
630#define vsr49 49
631#define vsr50 50
632#define vsr51 51
633#define vsr52 52
634#define vsr53 53
635#define vsr54 54
636#define vsr55 55
637#define vsr56 56
638#define vsr57 57
639#define vsr58 58
640#define vsr59 59
641#define vsr60 60
642#define vsr61 61
643#define vsr62 62
644#define vsr63 63
645
646/* SPE Registers (EVPRs) */
647
648#define evr0 0
649#define evr1 1
650#define evr2 2
651#define evr3 3
652#define evr4 4
653#define evr5 5
654#define evr6 6
655#define evr7 7
656#define evr8 8
657#define evr9 9
658#define evr10 10
659#define evr11 11
660#define evr12 12
661#define evr13 13
662#define evr14 14
663#define evr15 15
664#define evr16 16
665#define evr17 17
666#define evr18 18
667#define evr19 19
668#define evr20 20
669#define evr21 21
670#define evr22 22
671#define evr23 23
672#define evr24 24
673#define evr25 25
674#define evr26 26
675#define evr27 27
676#define evr28 28
677#define evr29 29
678#define evr30 30
679#define evr31 31
680
681/* some stab codes */
682#define N_FUN 36
683#define N_RSYM 64
684#define N_SLINE 68
685#define N_SO 100
686
687#endif /* __ASSEMBLY__ */
688
689#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
new file mode 100644
index 000000000000..101ed87f7d84
--- /dev/null
+++ b/arch/powerpc/include/asm/processor.h
@@ -0,0 +1,314 @@
1#ifndef _ASM_POWERPC_PROCESSOR_H
2#define _ASM_POWERPC_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/reg.h>
14
15#ifdef CONFIG_VSX
16#define TS_FPRWIDTH 2
17#else
18#define TS_FPRWIDTH 1
19#endif
20
21#ifndef __ASSEMBLY__
22#include <linux/compiler.h>
23#include <asm/ptrace.h>
24#include <asm/types.h>
25
26/* We do _not_ want to define new machine types at all, those must die
27 * in favor of using the device-tree
28 * -- BenH.
29 */
30
31/* PREP sub-platform types see residual.h for these */
32#define _PREP_Motorola 0x01 /* motorola prep */
33#define _PREP_Firm 0x02 /* firmworks prep */
34#define _PREP_IBM 0x00 /* ibm prep */
35#define _PREP_Bull 0x03 /* bull prep */
36
37/* CHRP sub-platform types. These are arbitrary */
38#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
39#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
40#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
41#define _CHRP_briq 0x07 /* TotalImpact's briQ */
42
43#if defined(__KERNEL__) && defined(CONFIG_PPC32)
44
45extern int _chrp_type;
46
47#ifdef CONFIG_PPC_PREP
48
49/* what kind of prep workstation we are */
50extern int _prep_type;
51
52#endif /* CONFIG_PPC_PREP */
53
54#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
55
56/*
57 * Default implementation of macro that returns current
58 * instruction pointer ("program counter").
59 */
60#define current_text_addr() ({ __label__ _l; _l: &&_l;})
61
62/* Macros for adjusting thread priority (hardware multi-threading) */
63#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
64#define HMT_low() asm volatile("or 1,1,1 # low priority")
65#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
66#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
67#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
68#define HMT_high() asm volatile("or 3,3,3 # high priority")
69
70#ifdef __KERNEL__
71
72extern int have_of;
73
74struct task_struct;
75void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
76void release_thread(struct task_struct *);
77
78/* Prepare to copy thread state - unlazy all lazy status */
79extern void prepare_to_copy(struct task_struct *tsk);
80
81/* Create a new kernel thread. */
82extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
83
84/* Lazy FPU handling on uni-processor */
85extern struct task_struct *last_task_used_math;
86extern struct task_struct *last_task_used_altivec;
87extern struct task_struct *last_task_used_vsx;
88extern struct task_struct *last_task_used_spe;
89
90#ifdef CONFIG_PPC32
91
92#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
93#error User TASK_SIZE overlaps with KERNEL_START address
94#endif
95#define TASK_SIZE (CONFIG_TASK_SIZE)
96
97/* This decides where the kernel will search for a free chunk of vm
98 * space during mmap's.
99 */
100#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
101#endif
102
103#ifdef CONFIG_PPC64
104/* 64-bit user address space is 44-bits (16TB user VM) */
105#define TASK_SIZE_USER64 (0x0000100000000000UL)
106
107/*
108 * 32-bit user address space is 4GB - 1 page
109 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
110 */
111#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
112
113#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
114 TASK_SIZE_USER32 : TASK_SIZE_USER64)
115#define TASK_SIZE TASK_SIZE_OF(current)
116
117/* This decides where the kernel will search for a free chunk of vm
118 * space during mmap's.
119 */
120#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
121#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
122
123#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
124 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
125#endif
126
127#ifdef __KERNEL__
128#ifdef __powerpc64__
129
130#define STACK_TOP_USER64 TASK_SIZE_USER64
131#define STACK_TOP_USER32 TASK_SIZE_USER32
132
133#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
134 STACK_TOP_USER32 : STACK_TOP_USER64)
135
136#define STACK_TOP_MAX STACK_TOP_USER64
137
138#else /* __powerpc64__ */
139
140#define STACK_TOP TASK_SIZE
141#define STACK_TOP_MAX STACK_TOP
142
143#endif /* __powerpc64__ */
144#endif /* __KERNEL__ */
145
146typedef struct {
147 unsigned long seg;
148} mm_segment_t;
149
150#define TS_FPROFFSET 0
151#define TS_VSRLOWOFFSET 1
152#define TS_FPR(i) fpr[i][TS_FPROFFSET]
153
154struct thread_struct {
155 unsigned long ksp; /* Kernel stack pointer */
156 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
157
158#ifdef CONFIG_PPC64
159 unsigned long ksp_vsid;
160#endif
161 struct pt_regs *regs; /* Pointer to saved register state */
162 mm_segment_t fs; /* for get_fs() validation */
163#ifdef CONFIG_PPC32
164 void *pgdir; /* root of page-table tree */
165#endif
166#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
167 unsigned long dbcr0; /* debug control register values */
168 unsigned long dbcr1;
169#endif
170 /* FP and VSX 0-31 register set */
171 double fpr[32][TS_FPRWIDTH];
172 struct {
173
174 unsigned int pad;
175 unsigned int val; /* Floating point status */
176 } fpscr;
177 int fpexc_mode; /* floating-point exception mode */
178 unsigned int align_ctl; /* alignment handling control */
179#ifdef CONFIG_PPC64
180 unsigned long start_tb; /* Start purr when proc switched in */
181 unsigned long accum_tb; /* Total accumilated purr for process */
182#endif
183 unsigned long dabr; /* Data address breakpoint register */
184#ifdef CONFIG_ALTIVEC
185 /* Complete AltiVec register set */
186 vector128 vr[32] __attribute__((aligned(16)));
187 /* AltiVec status */
188 vector128 vscr __attribute__((aligned(16)));
189 unsigned long vrsave;
190 int used_vr; /* set if process has used altivec */
191#endif /* CONFIG_ALTIVEC */
192#ifdef CONFIG_VSX
193 /* VSR status */
194 int used_vsr; /* set if process has used altivec */
195#endif /* CONFIG_VSX */
196#ifdef CONFIG_SPE
197 unsigned long evr[32]; /* upper 32-bits of SPE regs */
198 u64 acc; /* Accumulator */
199 unsigned long spefscr; /* SPE & eFP status */
200 int used_spe; /* set if process has used spe */
201#endif /* CONFIG_SPE */
202};
203
204#define ARCH_MIN_TASKALIGN 16
205
206#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
207#define INIT_SP_LIMIT \
208 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
209
210
211#ifdef CONFIG_PPC32
212#define INIT_THREAD { \
213 .ksp = INIT_SP, \
214 .ksp_limit = INIT_SP_LIMIT, \
215 .fs = KERNEL_DS, \
216 .pgdir = swapper_pg_dir, \
217 .fpexc_mode = MSR_FE0 | MSR_FE1, \
218}
219#else
220#define INIT_THREAD { \
221 .ksp = INIT_SP, \
222 .ksp_limit = INIT_SP_LIMIT, \
223 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
224 .fs = KERNEL_DS, \
225 .fpr = {{0}}, \
226 .fpscr = { .val = 0, }, \
227 .fpexc_mode = 0, \
228}
229#endif
230
231/*
232 * Return saved PC of a blocked thread. For now, this is the "user" PC
233 */
234#define thread_saved_pc(tsk) \
235 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
236
237#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
238
239unsigned long get_wchan(struct task_struct *p);
240
241#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
242#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
243
244/* Get/set floating-point exception mode */
245#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
246#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
247
248extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
249extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
250
251#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
252#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
253
254extern int get_endian(struct task_struct *tsk, unsigned long adr);
255extern int set_endian(struct task_struct *tsk, unsigned int val);
256
257#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
258#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
259
260extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
261extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
262
263static inline unsigned int __unpack_fe01(unsigned long msr_bits)
264{
265 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
266}
267
268static inline unsigned long __pack_fe01(unsigned int fpmode)
269{
270 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
271}
272
273#ifdef CONFIG_PPC64
274#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
275#else
276#define cpu_relax() barrier()
277#endif
278
279/* Check that a certain kernel stack pointer is valid in task_struct p */
280int validate_sp(unsigned long sp, struct task_struct *p,
281 unsigned long nbytes);
282
283/*
284 * Prefetch macros.
285 */
286#define ARCH_HAS_PREFETCH
287#define ARCH_HAS_PREFETCHW
288#define ARCH_HAS_SPINLOCK_PREFETCH
289
290static inline void prefetch(const void *x)
291{
292 if (unlikely(!x))
293 return;
294
295 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
296}
297
298static inline void prefetchw(const void *x)
299{
300 if (unlikely(!x))
301 return;
302
303 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
304}
305
306#define spin_lock_prefetch(x) prefetchw(x)
307
308#ifdef CONFIG_PPC64
309#define HAVE_ARCH_PICK_MMAP_LAYOUT
310#endif
311
312#endif /* __KERNEL__ */
313#endif /* __ASSEMBLY__ */
314#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
new file mode 100644
index 000000000000..eb3bd2e1c7f6
--- /dev/null
+++ b/arch/powerpc/include/asm/prom.h
@@ -0,0 +1,356 @@
1#ifndef _POWERPC_PROM_H
2#define _POWERPC_PROM_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for talking to the Open Firmware PROM on
7 * Power Macintosh computers.
8 *
9 * Copyright (C) 1996-2005 Paul Mackerras.
10 *
11 * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#include <linux/types.h>
19#include <linux/proc_fs.h>
20#include <linux/platform_device.h>
21#include <asm/irq.h>
22#include <asm/atomic.h>
23
24#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
25#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
26
27#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2))
28#define of_prop_cmp(s1, s2) strcmp((s1), (s2))
29#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
30
31/* Definitions used by the flattened device tree */
32#define OF_DT_HEADER 0xd00dfeed /* marker */
33#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
34#define OF_DT_END_NODE 0x2 /* End node */
35#define OF_DT_PROP 0x3 /* Property: name off, size,
36 * content */
37#define OF_DT_NOP 0x4 /* nop */
38#define OF_DT_END 0x9
39
40#define OF_DT_VERSION 0x10
41
42/*
43 * This is what gets passed to the kernel by prom_init or kexec
44 *
45 * The dt struct contains the device tree structure, full pathes and
46 * property contents. The dt strings contain a separate block with just
47 * the strings for the property names, and is fully page aligned and
48 * self contained in a page, so that it can be kept around by the kernel,
49 * each property name appears only once in this page (cheap compression)
50 *
51 * the mem_rsvmap contains a map of reserved ranges of physical memory,
52 * passing it here instead of in the device-tree itself greatly simplifies
53 * the job of everybody. It's just a list of u64 pairs (base/size) that
54 * ends when size is 0
55 */
56struct boot_param_header
57{
58 u32 magic; /* magic word OF_DT_HEADER */
59 u32 totalsize; /* total size of DT block */
60 u32 off_dt_struct; /* offset to structure */
61 u32 off_dt_strings; /* offset to strings */
62 u32 off_mem_rsvmap; /* offset to memory reserve map */
63 u32 version; /* format version */
64 u32 last_comp_version; /* last compatible version */
65 /* version 2 fields below */
66 u32 boot_cpuid_phys; /* Physical CPU id we're booting on */
67 /* version 3 fields below */
68 u32 dt_strings_size; /* size of the DT strings block */
69 /* version 17 fields below */
70 u32 dt_struct_size; /* size of the DT structure block */
71};
72
73
74
75typedef u32 phandle;
76typedef u32 ihandle;
77
78struct property {
79 char *name;
80 int length;
81 void *value;
82 struct property *next;
83};
84
85struct device_node {
86 const char *name;
87 const char *type;
88 phandle node;
89 phandle linux_phandle;
90 char *full_name;
91
92 struct property *properties;
93 struct property *deadprops; /* removed properties */
94 struct device_node *parent;
95 struct device_node *child;
96 struct device_node *sibling;
97 struct device_node *next; /* next device of same type */
98 struct device_node *allnext; /* next in list of all nodes */
99 struct proc_dir_entry *pde; /* this node's proc directory */
100 struct kref kref;
101 unsigned long _flags;
102 void *data;
103};
104
105extern struct device_node *of_chosen;
106
107static inline int of_node_check_flag(struct device_node *n, unsigned long flag)
108{
109 return test_bit(flag, &n->_flags);
110}
111
112static inline void of_node_set_flag(struct device_node *n, unsigned long flag)
113{
114 set_bit(flag, &n->_flags);
115}
116
117
118#define HAVE_ARCH_DEVTREE_FIXUPS
119
120static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
121{
122 dn->pde = de;
123}
124
125
126extern struct device_node *of_find_all_nodes(struct device_node *prev);
127extern struct device_node *of_node_get(struct device_node *node);
128extern void of_node_put(struct device_node *node);
129
130/* For scanning the flat device-tree at boot time */
131extern int __init of_scan_flat_dt(int (*it)(unsigned long node,
132 const char *uname, int depth,
133 void *data),
134 void *data);
135extern void* __init of_get_flat_dt_prop(unsigned long node, const char *name,
136 unsigned long *size);
137extern int __init of_flat_dt_is_compatible(unsigned long node, const char *name);
138extern unsigned long __init of_get_flat_dt_root(void);
139
140/* For updating the device tree at runtime */
141extern void of_attach_node(struct device_node *);
142extern void of_detach_node(struct device_node *);
143
144/* Other Prototypes */
145extern void finish_device_tree(void);
146extern void unflatten_device_tree(void);
147extern void early_init_devtree(void *);
148extern int machine_is_compatible(const char *compat);
149extern void print_properties(struct device_node *node);
150extern int prom_n_intr_cells(struct device_node* np);
151extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
152extern int prom_add_property(struct device_node* np, struct property* prop);
153extern int prom_remove_property(struct device_node *np, struct property *prop);
154extern int prom_update_property(struct device_node *np,
155 struct property *newprop,
156 struct property *oldprop);
157
158#ifdef CONFIG_PPC32
159/*
160 * PCI <-> OF matching functions
161 * (XXX should these be here?)
162 */
163struct pci_bus;
164struct pci_dev;
165extern int pci_device_from_OF_node(struct device_node *node,
166 u8* bus, u8* devfn);
167extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
168extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
169extern void pci_create_OF_bus_map(void);
170#endif
171
172extern struct resource *request_OF_resource(struct device_node* node,
173 int index, const char* name_postfix);
174extern int release_OF_resource(struct device_node* node, int index);
175
176
177/*
178 * OF address retreival & translation
179 */
180
181
182/* Helper to read a big number; size is in cells (not bytes) */
183static inline u64 of_read_number(const u32 *cell, int size)
184{
185 u64 r = 0;
186 while (size--)
187 r = (r << 32) | *(cell++);
188 return r;
189}
190
191/* Like of_read_number, but we want an unsigned long result */
192#ifdef CONFIG_PPC32
193static inline unsigned long of_read_ulong(const u32 *cell, int size)
194{
195 return cell[size-1];
196}
197#else
198#define of_read_ulong(cell, size) of_read_number(cell, size)
199#endif
200
201/* Translate an OF address block into a CPU physical address
202 */
203extern u64 of_translate_address(struct device_node *np, const u32 *addr);
204
205/* Translate a DMA address from device space to CPU space */
206extern u64 of_translate_dma_address(struct device_node *dev,
207 const u32 *in_addr);
208
209/* Extract an address from a device, returns the region size and
210 * the address space flags too. The PCI version uses a BAR number
211 * instead of an absolute index
212 */
213extern const u32 *of_get_address(struct device_node *dev, int index,
214 u64 *size, unsigned int *flags);
215#ifdef CONFIG_PCI
216extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
217 u64 *size, unsigned int *flags);
218#else
219static inline const u32 *of_get_pci_address(struct device_node *dev,
220 int bar_no, u64 *size, unsigned int *flags)
221{
222 return NULL;
223}
224#endif /* CONFIG_PCI */
225
226/* Get an address as a resource. Note that if your address is
227 * a PIO address, the conversion will fail if the physical address
228 * can't be internally converted to an IO token with
229 * pci_address_to_pio(), that is because it's either called to early
230 * or it can't be matched to any host bridge IO space
231 */
232extern int of_address_to_resource(struct device_node *dev, int index,
233 struct resource *r);
234#ifdef CONFIG_PCI
235extern int of_pci_address_to_resource(struct device_node *dev, int bar,
236 struct resource *r);
237#else
238static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
239 struct resource *r)
240{
241 return -ENOSYS;
242}
243#endif /* CONFIG_PCI */
244
245/* Parse the ibm,dma-window property of an OF node into the busno, phys and
246 * size parameters.
247 */
248void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
249 unsigned long *busno, unsigned long *phys, unsigned long *size);
250
251extern void kdump_move_device_tree(void);
252
253/* CPU OF node matching */
254struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
255
256/* Get the MAC address */
257extern const void *of_get_mac_address(struct device_node *np);
258
259/*
260 * OF interrupt mapping
261 */
262
263/* This structure is returned when an interrupt is mapped. The controller
264 * field needs to be put() after use
265 */
266
267#define OF_MAX_IRQ_SPEC 4 /* We handle specifiers of at most 4 cells */
268
269struct of_irq {
270 struct device_node *controller; /* Interrupt controller node */
271 u32 size; /* Specifier size */
272 u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
273};
274
275/**
276 * of_irq_map_init - Initialize the irq remapper
277 * @flags: flags defining workarounds to enable
278 *
279 * Some machines have bugs in the device-tree which require certain workarounds
280 * to be applied. Call this before any interrupt mapping attempts to enable
281 * those workarounds.
282 */
283#define OF_IMAP_OLDWORLD_MAC 0x00000001
284#define OF_IMAP_NO_PHANDLE 0x00000002
285
286extern void of_irq_map_init(unsigned int flags);
287
288/**
289 * of_irq_map_raw - Low level interrupt tree parsing
290 * @parent: the device interrupt parent
291 * @intspec: interrupt specifier ("interrupts" property of the device)
292 * @ointsize: size of the passed in interrupt specifier
293 * @addr: address specifier (start of "reg" property of the device)
294 * @out_irq: structure of_irq filled by this function
295 *
296 * Returns 0 on success and a negative number on error
297 *
298 * This function is a low-level interrupt tree walking function. It
299 * can be used to do a partial walk with synthetized reg and interrupts
300 * properties, for example when resolving PCI interrupts when no device
301 * node exist for the parent.
302 *
303 */
304
305extern int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
306 u32 ointsize, const u32 *addr,
307 struct of_irq *out_irq);
308
309
310/**
311 * of_irq_map_one - Resolve an interrupt for a device
312 * @device: the device whose interrupt is to be resolved
313 * @index: index of the interrupt to resolve
314 * @out_irq: structure of_irq filled by this function
315 *
316 * This function resolves an interrupt, walking the tree, for a given
317 * device-tree node. It's the high level pendant to of_irq_map_raw().
318 * It also implements the workarounds for OldWolrd Macs.
319 */
320extern int of_irq_map_one(struct device_node *device, int index,
321 struct of_irq *out_irq);
322
323/**
324 * of_irq_map_pci - Resolve the interrupt for a PCI device
325 * @pdev: the device whose interrupt is to be resolved
326 * @out_irq: structure of_irq filled by this function
327 *
328 * This function resolves the PCI interrupt for a given PCI device. If a
329 * device-node exists for a given pci_dev, it will use normal OF tree
330 * walking. If not, it will implement standard swizzling and walk up the
331 * PCI tree until an device-node is found, at which point it will finish
332 * resolving using the OF tree walking.
333 */
334struct pci_dev;
335extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
336
337extern int of_irq_to_resource(struct device_node *dev, int index,
338 struct resource *r);
339
340/**
341 * of_iomap - Maps the memory mapped IO for a given device_node
342 * @device: the device whose io range will be mapped
343 * @index: index of the io range
344 *
345 * Returns a pointer to the mapped memory
346 */
347extern void __iomem *of_iomap(struct device_node *device, int index);
348
349/*
350 * NB: This is here while we transition from using asm/prom.h
351 * to linux/of.h
352 */
353#include <linux/of.h>
354
355#endif /* __KERNEL__ */
356#endif /* _POWERPC_PROM_H */
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
new file mode 100644
index 000000000000..f9e34c493cbb
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3.h
@@ -0,0 +1,519 @@
1/*
2 * PS3 platform declarations.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#if !defined(_ASM_POWERPC_PS3_H)
22#define _ASM_POWERPC_PS3_H
23
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/device.h>
27#include "cell-pmu.h"
28
29union ps3_firmware_version {
30 u64 raw;
31 struct {
32 u16 pad;
33 u16 major;
34 u16 minor;
35 u16 rev;
36 };
37};
38
39void ps3_get_firmware_version(union ps3_firmware_version *v);
40int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev);
41
42/* 'Other OS' area */
43
44enum ps3_param_av_multi_out {
45 PS3_PARAM_AV_MULTI_OUT_NTSC = 0,
46 PS3_PARAM_AV_MULTI_OUT_PAL_RGB = 1,
47 PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR = 2,
48 PS3_PARAM_AV_MULTI_OUT_SECAM = 3,
49};
50
51enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
52
53/* dma routines */
54
55enum ps3_dma_page_size {
56 PS3_DMA_4K = 12U,
57 PS3_DMA_64K = 16U,
58 PS3_DMA_1M = 20U,
59 PS3_DMA_16M = 24U,
60};
61
62enum ps3_dma_region_type {
63 PS3_DMA_OTHER = 0,
64 PS3_DMA_INTERNAL = 2,
65};
66
67struct ps3_dma_region_ops;
68
69/**
70 * struct ps3_dma_region - A per device dma state variables structure
71 * @did: The HV device id.
72 * @page_size: The ioc pagesize.
73 * @region_type: The HV region type.
74 * @bus_addr: The 'translated' bus address of the region.
75 * @len: The length in bytes of the region.
76 * @offset: The offset from the start of memory of the region.
77 * @ioid: The IOID of the device who owns this region
78 * @chunk_list: Opaque variable used by the ioc page manager.
79 * @region_ops: struct ps3_dma_region_ops - dma region operations
80 */
81
82struct ps3_dma_region {
83 struct ps3_system_bus_device *dev;
84 /* device variables */
85 const struct ps3_dma_region_ops *region_ops;
86 unsigned char ioid;
87 enum ps3_dma_page_size page_size;
88 enum ps3_dma_region_type region_type;
89 unsigned long len;
90 unsigned long offset;
91
92 /* driver variables (set by ps3_dma_region_create) */
93 unsigned long bus_addr;
94 struct {
95 spinlock_t lock;
96 struct list_head head;
97 } chunk_list;
98};
99
100struct ps3_dma_region_ops {
101 int (*create)(struct ps3_dma_region *);
102 int (*free)(struct ps3_dma_region *);
103 int (*map)(struct ps3_dma_region *,
104 unsigned long virt_addr,
105 unsigned long len,
106 unsigned long *bus_addr,
107 u64 iopte_pp);
108 int (*unmap)(struct ps3_dma_region *,
109 unsigned long bus_addr,
110 unsigned long len);
111};
112/**
113 * struct ps3_dma_region_init - Helper to initialize structure variables
114 *
115 * Helper to properly initialize variables prior to calling
116 * ps3_system_bus_device_register.
117 */
118
119struct ps3_system_bus_device;
120
121int ps3_dma_region_init(struct ps3_system_bus_device *dev,
122 struct ps3_dma_region *r, enum ps3_dma_page_size page_size,
123 enum ps3_dma_region_type region_type, void *addr, unsigned long len);
124int ps3_dma_region_create(struct ps3_dma_region *r);
125int ps3_dma_region_free(struct ps3_dma_region *r);
126int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
127 unsigned long len, unsigned long *bus_addr,
128 u64 iopte_pp);
129int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
130 unsigned long len);
131
132/* mmio routines */
133
134enum ps3_mmio_page_size {
135 PS3_MMIO_4K = 12U,
136 PS3_MMIO_64K = 16U
137};
138
139struct ps3_mmio_region_ops;
140/**
141 * struct ps3_mmio_region - a per device mmio state variables structure
142 *
143 * Current systems can be supported with a single region per device.
144 */
145
146struct ps3_mmio_region {
147 struct ps3_system_bus_device *dev;
148 const struct ps3_mmio_region_ops *mmio_ops;
149 unsigned long bus_addr;
150 unsigned long len;
151 enum ps3_mmio_page_size page_size;
152 unsigned long lpar_addr;
153};
154
155struct ps3_mmio_region_ops {
156 int (*create)(struct ps3_mmio_region *);
157 int (*free)(struct ps3_mmio_region *);
158};
159/**
160 * struct ps3_mmio_region_init - Helper to initialize structure variables
161 *
162 * Helper to properly initialize variables prior to calling
163 * ps3_system_bus_device_register.
164 */
165
166int ps3_mmio_region_init(struct ps3_system_bus_device *dev,
167 struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len,
168 enum ps3_mmio_page_size page_size);
169int ps3_mmio_region_create(struct ps3_mmio_region *r);
170int ps3_free_mmio_region(struct ps3_mmio_region *r);
171unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
172
173/* inrerrupt routines */
174
175enum ps3_cpu_binding {
176 PS3_BINDING_CPU_ANY = -1,
177 PS3_BINDING_CPU_0 = 0,
178 PS3_BINDING_CPU_1 = 1,
179};
180
181int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
182 unsigned int *virq);
183int ps3_irq_plug_destroy(unsigned int virq);
184int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq);
185int ps3_event_receive_port_destroy(unsigned int virq);
186int ps3_send_event_locally(unsigned int virq);
187
188int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
189 unsigned int *virq);
190int ps3_io_irq_destroy(unsigned int virq);
191int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
192 unsigned int *virq);
193int ps3_vuart_irq_destroy(unsigned int virq);
194int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
195 unsigned int class, unsigned int *virq);
196int ps3_spe_irq_destroy(unsigned int virq);
197
198int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
199 enum ps3_cpu_binding cpu, unsigned int *virq);
200int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
201 unsigned int virq);
202
203/* lv1 result codes */
204
205enum lv1_result {
206 LV1_SUCCESS = 0,
207 /* not used -1 */
208 LV1_RESOURCE_SHORTAGE = -2,
209 LV1_NO_PRIVILEGE = -3,
210 LV1_DENIED_BY_POLICY = -4,
211 LV1_ACCESS_VIOLATION = -5,
212 LV1_NO_ENTRY = -6,
213 LV1_DUPLICATE_ENTRY = -7,
214 LV1_TYPE_MISMATCH = -8,
215 LV1_BUSY = -9,
216 LV1_EMPTY = -10,
217 LV1_WRONG_STATE = -11,
218 /* not used -12 */
219 LV1_NO_MATCH = -13,
220 LV1_ALREADY_CONNECTED = -14,
221 LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
222 LV1_CONDITION_NOT_SATISFIED = -16,
223 LV1_ILLEGAL_PARAMETER_VALUE = -17,
224 LV1_BAD_OPTION = -18,
225 LV1_IMPLEMENTATION_LIMITATION = -19,
226 LV1_NOT_IMPLEMENTED = -20,
227 LV1_INVALID_CLASS_ID = -21,
228 LV1_CONSTRAINT_NOT_SATISFIED = -22,
229 LV1_ALIGNMENT_ERROR = -23,
230 LV1_HARDWARE_ERROR = -24,
231 LV1_INVALID_DATA_FORMAT = -25,
232 LV1_INVALID_OPERATION = -26,
233 LV1_INTERNAL_ERROR = -32768,
234};
235
236static inline const char* ps3_result(int result)
237{
238#if defined(DEBUG)
239 switch (result) {
240 case LV1_SUCCESS:
241 return "LV1_SUCCESS (0)";
242 case -1:
243 return "** unknown result ** (-1)";
244 case LV1_RESOURCE_SHORTAGE:
245 return "LV1_RESOURCE_SHORTAGE (-2)";
246 case LV1_NO_PRIVILEGE:
247 return "LV1_NO_PRIVILEGE (-3)";
248 case LV1_DENIED_BY_POLICY:
249 return "LV1_DENIED_BY_POLICY (-4)";
250 case LV1_ACCESS_VIOLATION:
251 return "LV1_ACCESS_VIOLATION (-5)";
252 case LV1_NO_ENTRY:
253 return "LV1_NO_ENTRY (-6)";
254 case LV1_DUPLICATE_ENTRY:
255 return "LV1_DUPLICATE_ENTRY (-7)";
256 case LV1_TYPE_MISMATCH:
257 return "LV1_TYPE_MISMATCH (-8)";
258 case LV1_BUSY:
259 return "LV1_BUSY (-9)";
260 case LV1_EMPTY:
261 return "LV1_EMPTY (-10)";
262 case LV1_WRONG_STATE:
263 return "LV1_WRONG_STATE (-11)";
264 case -12:
265 return "** unknown result ** (-12)";
266 case LV1_NO_MATCH:
267 return "LV1_NO_MATCH (-13)";
268 case LV1_ALREADY_CONNECTED:
269 return "LV1_ALREADY_CONNECTED (-14)";
270 case LV1_UNSUPPORTED_PARAMETER_VALUE:
271 return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
272 case LV1_CONDITION_NOT_SATISFIED:
273 return "LV1_CONDITION_NOT_SATISFIED (-16)";
274 case LV1_ILLEGAL_PARAMETER_VALUE:
275 return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
276 case LV1_BAD_OPTION:
277 return "LV1_BAD_OPTION (-18)";
278 case LV1_IMPLEMENTATION_LIMITATION:
279 return "LV1_IMPLEMENTATION_LIMITATION (-19)";
280 case LV1_NOT_IMPLEMENTED:
281 return "LV1_NOT_IMPLEMENTED (-20)";
282 case LV1_INVALID_CLASS_ID:
283 return "LV1_INVALID_CLASS_ID (-21)";
284 case LV1_CONSTRAINT_NOT_SATISFIED:
285 return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
286 case LV1_ALIGNMENT_ERROR:
287 return "LV1_ALIGNMENT_ERROR (-23)";
288 case LV1_HARDWARE_ERROR:
289 return "LV1_HARDWARE_ERROR (-24)";
290 case LV1_INVALID_DATA_FORMAT:
291 return "LV1_INVALID_DATA_FORMAT (-25)";
292 case LV1_INVALID_OPERATION:
293 return "LV1_INVALID_OPERATION (-26)";
294 case LV1_INTERNAL_ERROR:
295 return "LV1_INTERNAL_ERROR (-32768)";
296 default:
297 BUG();
298 return "** unknown result **";
299 };
300#else
301 return "";
302#endif
303}
304
305/* system bus routines */
306
307enum ps3_match_id {
308 PS3_MATCH_ID_EHCI = 1,
309 PS3_MATCH_ID_OHCI = 2,
310 PS3_MATCH_ID_GELIC = 3,
311 PS3_MATCH_ID_AV_SETTINGS = 4,
312 PS3_MATCH_ID_SYSTEM_MANAGER = 5,
313 PS3_MATCH_ID_STOR_DISK = 6,
314 PS3_MATCH_ID_STOR_ROM = 7,
315 PS3_MATCH_ID_STOR_FLASH = 8,
316 PS3_MATCH_ID_SOUND = 9,
317 PS3_MATCH_ID_GRAPHICS = 10,
318 PS3_MATCH_ID_LPM = 11,
319};
320
321#define PS3_MODULE_ALIAS_EHCI "ps3:1"
322#define PS3_MODULE_ALIAS_OHCI "ps3:2"
323#define PS3_MODULE_ALIAS_GELIC "ps3:3"
324#define PS3_MODULE_ALIAS_AV_SETTINGS "ps3:4"
325#define PS3_MODULE_ALIAS_SYSTEM_MANAGER "ps3:5"
326#define PS3_MODULE_ALIAS_STOR_DISK "ps3:6"
327#define PS3_MODULE_ALIAS_STOR_ROM "ps3:7"
328#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
329#define PS3_MODULE_ALIAS_SOUND "ps3:9"
330#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
331#define PS3_MODULE_ALIAS_LPM "ps3:11"
332
333enum ps3_system_bus_device_type {
334 PS3_DEVICE_TYPE_IOC0 = 1,
335 PS3_DEVICE_TYPE_SB,
336 PS3_DEVICE_TYPE_VUART,
337 PS3_DEVICE_TYPE_LPM,
338};
339
340enum ps3_match_sub_id {
341 /* for PS3_MATCH_ID_GRAPHICS */
342 PS3_MATCH_SUB_ID_FB = 1,
343};
344
345/**
346 * struct ps3_system_bus_device - a device on the system bus
347 */
348
349struct ps3_system_bus_device {
350 enum ps3_match_id match_id;
351 enum ps3_match_sub_id match_sub_id;
352 enum ps3_system_bus_device_type dev_type;
353
354 u64 bus_id; /* SB */
355 u64 dev_id; /* SB */
356 unsigned int interrupt_id; /* SB */
357 struct ps3_dma_region *d_region; /* SB, IOC0 */
358 struct ps3_mmio_region *m_region; /* SB, IOC0*/
359 unsigned int port_number; /* VUART */
360 struct { /* LPM */
361 u64 node_id;
362 u64 pu_id;
363 u64 rights;
364 } lpm;
365
366/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
367 struct device core;
368 void *driver_priv; /* private driver variables */
369};
370
371int ps3_open_hv_device(struct ps3_system_bus_device *dev);
372int ps3_close_hv_device(struct ps3_system_bus_device *dev);
373
374/**
375 * struct ps3_system_bus_driver - a driver for a device on the system bus
376 */
377
378struct ps3_system_bus_driver {
379 enum ps3_match_id match_id;
380 enum ps3_match_sub_id match_sub_id;
381 struct device_driver core;
382 int (*probe)(struct ps3_system_bus_device *);
383 int (*remove)(struct ps3_system_bus_device *);
384 int (*shutdown)(struct ps3_system_bus_device *);
385/* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
386/* int (*resume)(struct ps3_system_bus_device *); */
387};
388
389int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
390int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
391void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
392
393static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv(
394 struct device_driver *_drv)
395{
396 return container_of(_drv, struct ps3_system_bus_driver, core);
397}
398static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev(
399 struct device *_dev)
400{
401 return container_of(_dev, struct ps3_system_bus_device, core);
402}
403static inline struct ps3_system_bus_driver *
404 ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev)
405{
406 BUG_ON(!_dev);
407 BUG_ON(!_dev->core.driver);
408 return ps3_drv_to_system_bus_drv(_dev->core.driver);
409}
410
411/**
412 * ps3_system_bus_set_drvdata -
413 * @dev: device structure
414 * @data: Data to set
415 */
416
417static inline void ps3_system_bus_set_driver_data(
418 struct ps3_system_bus_device *dev, void *data)
419{
420 dev->core.driver_data = data;
421}
422static inline void *ps3_system_bus_get_driver_data(
423 struct ps3_system_bus_device *dev)
424{
425 return dev->core.driver_data;
426}
427
428/* These two need global scope for get_dma_ops(). */
429
430extern struct bus_type ps3_system_bus_type;
431
432/* system manager */
433
434struct ps3_sys_manager_ops {
435 struct ps3_system_bus_device *dev;
436 void (*power_off)(struct ps3_system_bus_device *dev);
437 void (*restart)(struct ps3_system_bus_device *dev);
438};
439
440void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
441void __noreturn ps3_sys_manager_power_off(void);
442void __noreturn ps3_sys_manager_restart(void);
443void __noreturn ps3_sys_manager_halt(void);
444int ps3_sys_manager_get_wol(void);
445void ps3_sys_manager_set_wol(int state);
446
447struct ps3_prealloc {
448 const char *name;
449 void *address;
450 unsigned long size;
451 unsigned long align;
452};
453
454extern struct ps3_prealloc ps3fb_videomemory;
455extern struct ps3_prealloc ps3flash_bounce_buffer;
456
457/* logical performance monitor */
458
459/**
460 * enum ps3_lpm_rights - Rigths granted by the system policy module.
461 *
462 * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
463 * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
464 */
465
466enum ps3_lpm_rights {
467 PS3_LPM_RIGHTS_USE_LPM = 0x001,
468 PS3_LPM_RIGHTS_USE_TB = 0x100,
469};
470
471/**
472 * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
473 *
474 * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
475 * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have
476 * rights @PS3_LPM_RIGHTS_USE_TB.
477 */
478
479enum ps3_lpm_tb_type {
480 PS3_LPM_TB_TYPE_NONE = 0,
481 PS3_LPM_TB_TYPE_INTERNAL = 1,
482};
483
484int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
485 u64 tb_cache_size);
486int ps3_lpm_close(void);
487int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
488 unsigned long *bytes_copied);
489int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
490 unsigned long count, unsigned long *bytes_copied);
491void ps3_set_bookmark(u64 bookmark);
492void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
493int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
494 u8 bus_word);
495
496u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
497void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
498u32 ps3_read_ctr(u32 cpu, u32 ctr);
499void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
500
501u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
502void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
503u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
504void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
505
506u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
507void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
508
509void ps3_enable_pm(u32 cpu);
510void ps3_disable_pm(u32 cpu);
511void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
512void ps3_disable_pm_interrupts(u32 cpu);
513
514u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
515void ps3_sync_irq(int node);
516u32 ps3_get_hw_thread_id(int cpu);
517u64 ps3_get_spe_id(void *arg);
518
519#endif
diff --git a/arch/powerpc/include/asm/ps3av.h b/arch/powerpc/include/asm/ps3av.h
new file mode 100644
index 000000000000..fda98715cd35
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3av.h
@@ -0,0 +1,744 @@
1/*
2 * PS3 AV backend support.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_PS3AV_H_
22#define _ASM_POWERPC_PS3AV_H_
23
24/** command for ioctl() **/
25#define PS3AV_VERSION 0x205 /* version of ps3av command */
26
27#define PS3AV_CID_AV_INIT 0x00000001
28#define PS3AV_CID_AV_FIN 0x00000002
29#define PS3AV_CID_AV_GET_HW_CONF 0x00000003
30#define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
31#define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
32#define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
33#define PS3AV_CID_AV_TV_MUTE 0x0000000a
34
35#define PS3AV_CID_AV_VIDEO_CS 0x00010001
36#define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
37#define PS3AV_CID_AV_VIDEO_DISABLE_SIG 0x00010003
38#define PS3AV_CID_AV_AUDIO_PARAM 0x00020001
39#define PS3AV_CID_AV_AUDIO_MUTE 0x00020002
40#define PS3AV_CID_AV_HDMI_MODE 0x00040001
41
42#define PS3AV_CID_VIDEO_INIT 0x01000001
43#define PS3AV_CID_VIDEO_MODE 0x01000002
44#define PS3AV_CID_VIDEO_FORMAT 0x01000004
45#define PS3AV_CID_VIDEO_PITCH 0x01000005
46
47#define PS3AV_CID_AUDIO_INIT 0x02000001
48#define PS3AV_CID_AUDIO_MODE 0x02000002
49#define PS3AV_CID_AUDIO_MUTE 0x02000003
50#define PS3AV_CID_AUDIO_ACTIVE 0x02000004
51#define PS3AV_CID_AUDIO_INACTIVE 0x02000005
52#define PS3AV_CID_AUDIO_SPDIF_BIT 0x02000006
53#define PS3AV_CID_AUDIO_CTRL 0x02000007
54
55#define PS3AV_CID_EVENT_UNPLUGGED 0x10000001
56#define PS3AV_CID_EVENT_PLUGGED 0x10000002
57#define PS3AV_CID_EVENT_HDCP_DONE 0x10000003
58#define PS3AV_CID_EVENT_HDCP_FAIL 0x10000004
59#define PS3AV_CID_EVENT_HDCP_AUTH 0x10000005
60#define PS3AV_CID_EVENT_HDCP_ERROR 0x10000006
61
62#define PS3AV_CID_AVB_PARAM 0x04000001
63
64/* max backend ports */
65#define PS3AV_HDMI_MAX 2 /* HDMI_0 HDMI_1 */
66#define PS3AV_AVMULTI_MAX 1 /* AVMULTI_0 */
67#define PS3AV_AV_PORT_MAX (PS3AV_HDMI_MAX + PS3AV_AVMULTI_MAX)
68#define PS3AV_OPT_PORT_MAX 1 /* SPDIF0 */
69#define PS3AV_HEAD_MAX 2 /* HEAD_A HEAD_B */
70
71/* num of pkt for PS3AV_CID_AVB_PARAM */
72#define PS3AV_AVB_NUM_VIDEO PS3AV_HEAD_MAX
73#define PS3AV_AVB_NUM_AUDIO 0 /* not supported */
74#define PS3AV_AVB_NUM_AV_VIDEO PS3AV_AV_PORT_MAX
75#define PS3AV_AVB_NUM_AV_AUDIO PS3AV_HDMI_MAX
76
77#define PS3AV_MUTE_PORT_MAX 1 /* num of ports in mute pkt */
78
79/* event_bit */
80#define PS3AV_CMD_EVENT_BIT_UNPLUGGED (1 << 0)
81#define PS3AV_CMD_EVENT_BIT_PLUGGED (1 << 1)
82#define PS3AV_CMD_EVENT_BIT_HDCP_DONE (1 << 2)
83#define PS3AV_CMD_EVENT_BIT_HDCP_FAIL (1 << 3)
84#define PS3AV_CMD_EVENT_BIT_HDCP_REAUTH (1 << 4)
85#define PS3AV_CMD_EVENT_BIT_HDCP_TOPOLOGY (1 << 5)
86
87/* common params */
88/* mute */
89#define PS3AV_CMD_MUTE_OFF 0x0000
90#define PS3AV_CMD_MUTE_ON 0x0001
91/* avport */
92#define PS3AV_CMD_AVPORT_HDMI_0 0x0000
93#define PS3AV_CMD_AVPORT_HDMI_1 0x0001
94#define PS3AV_CMD_AVPORT_AVMULTI_0 0x0010
95#define PS3AV_CMD_AVPORT_SPDIF_0 0x0020
96#define PS3AV_CMD_AVPORT_SPDIF_1 0x0021
97
98/* for av backend */
99/* av_mclk */
100#define PS3AV_CMD_AV_MCLK_128 0x0000
101#define PS3AV_CMD_AV_MCLK_256 0x0001
102#define PS3AV_CMD_AV_MCLK_512 0x0003
103/* av_inputlen */
104#define PS3AV_CMD_AV_INPUTLEN_16 0x02
105#define PS3AV_CMD_AV_INPUTLEN_20 0x0a
106#define PS3AV_CMD_AV_INPUTLEN_24 0x0b
107/* alayout */
108#define PS3AV_CMD_AV_LAYOUT_32 (1 << 0)
109#define PS3AV_CMD_AV_LAYOUT_44 (1 << 1)
110#define PS3AV_CMD_AV_LAYOUT_48 (1 << 2)
111#define PS3AV_CMD_AV_LAYOUT_88 (1 << 3)
112#define PS3AV_CMD_AV_LAYOUT_96 (1 << 4)
113#define PS3AV_CMD_AV_LAYOUT_176 (1 << 5)
114#define PS3AV_CMD_AV_LAYOUT_192 (1 << 6)
115/* hdmi_mode */
116#define PS3AV_CMD_AV_HDMI_MODE_NORMAL 0xff
117#define PS3AV_CMD_AV_HDMI_HDCP_OFF 0x01
118#define PS3AV_CMD_AV_HDMI_EDID_PASS 0x80
119#define PS3AV_CMD_AV_HDMI_DVI 0x40
120
121/* for video module */
122/* video_head */
123#define PS3AV_CMD_VIDEO_HEAD_A 0x0000
124#define PS3AV_CMD_VIDEO_HEAD_B 0x0001
125/* video_cs_out video_cs_in */
126#define PS3AV_CMD_VIDEO_CS_NONE 0x0000
127#define PS3AV_CMD_VIDEO_CS_RGB_8 0x0001
128#define PS3AV_CMD_VIDEO_CS_YUV444_8 0x0002
129#define PS3AV_CMD_VIDEO_CS_YUV422_8 0x0003
130#define PS3AV_CMD_VIDEO_CS_XVYCC_8 0x0004
131#define PS3AV_CMD_VIDEO_CS_RGB_10 0x0005
132#define PS3AV_CMD_VIDEO_CS_YUV444_10 0x0006
133#define PS3AV_CMD_VIDEO_CS_YUV422_10 0x0007
134#define PS3AV_CMD_VIDEO_CS_XVYCC_10 0x0008
135#define PS3AV_CMD_VIDEO_CS_RGB_12 0x0009
136#define PS3AV_CMD_VIDEO_CS_YUV444_12 0x000a
137#define PS3AV_CMD_VIDEO_CS_YUV422_12 0x000b
138#define PS3AV_CMD_VIDEO_CS_XVYCC_12 0x000c
139/* video_vid */
140#define PS3AV_CMD_VIDEO_VID_NONE 0x0000
141#define PS3AV_CMD_VIDEO_VID_480I 0x0001
142#define PS3AV_CMD_VIDEO_VID_576I 0x0003
143#define PS3AV_CMD_VIDEO_VID_480P 0x0005
144#define PS3AV_CMD_VIDEO_VID_576P 0x0006
145#define PS3AV_CMD_VIDEO_VID_1080I_60HZ 0x0007
146#define PS3AV_CMD_VIDEO_VID_1080I_50HZ 0x0008
147#define PS3AV_CMD_VIDEO_VID_720P_60HZ 0x0009
148#define PS3AV_CMD_VIDEO_VID_720P_50HZ 0x000a
149#define PS3AV_CMD_VIDEO_VID_1080P_60HZ 0x000b
150#define PS3AV_CMD_VIDEO_VID_1080P_50HZ 0x000c
151#define PS3AV_CMD_VIDEO_VID_WXGA 0x000d
152#define PS3AV_CMD_VIDEO_VID_SXGA 0x000e
153#define PS3AV_CMD_VIDEO_VID_WUXGA 0x000f
154#define PS3AV_CMD_VIDEO_VID_480I_A 0x0010
155/* video_format */
156#define PS3AV_CMD_VIDEO_FORMAT_BLACK 0x0000
157#define PS3AV_CMD_VIDEO_FORMAT_ARGB_8BIT 0x0007
158/* video_order */
159#define PS3AV_CMD_VIDEO_ORDER_RGB 0x0000
160#define PS3AV_CMD_VIDEO_ORDER_BGR 0x0001
161/* video_fmt */
162#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8 0x0000
163/* video_out_format */
164#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT 0x0000
165/* video_cl_cnv */
166#define PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT 0x0000
167#define PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT 0x0010
168/* video_sync */
169#define PS3AV_CMD_VIDEO_SYNC_VSYNC 0x0001
170#define PS3AV_CMD_VIDEO_SYNC_CSYNC 0x0004
171#define PS3AV_CMD_VIDEO_SYNC_HSYNC 0x0010
172
173/* for audio module */
174/* num_of_ch */
175#define PS3AV_CMD_AUDIO_NUM_OF_CH_2 0x0000
176#define PS3AV_CMD_AUDIO_NUM_OF_CH_3 0x0001
177#define PS3AV_CMD_AUDIO_NUM_OF_CH_4 0x0002
178#define PS3AV_CMD_AUDIO_NUM_OF_CH_5 0x0003
179#define PS3AV_CMD_AUDIO_NUM_OF_CH_6 0x0004
180#define PS3AV_CMD_AUDIO_NUM_OF_CH_7 0x0005
181#define PS3AV_CMD_AUDIO_NUM_OF_CH_8 0x0006
182/* audio_fs */
183#define PS3AV_CMD_AUDIO_FS_32K 0x0001
184#define PS3AV_CMD_AUDIO_FS_44K 0x0002
185#define PS3AV_CMD_AUDIO_FS_48K 0x0003
186#define PS3AV_CMD_AUDIO_FS_88K 0x0004
187#define PS3AV_CMD_AUDIO_FS_96K 0x0005
188#define PS3AV_CMD_AUDIO_FS_176K 0x0006
189#define PS3AV_CMD_AUDIO_FS_192K 0x0007
190/* audio_word_bits */
191#define PS3AV_CMD_AUDIO_WORD_BITS_16 0x0001
192#define PS3AV_CMD_AUDIO_WORD_BITS_20 0x0002
193#define PS3AV_CMD_AUDIO_WORD_BITS_24 0x0003
194/* audio_format */
195#define PS3AV_CMD_AUDIO_FORMAT_PCM 0x0001
196#define PS3AV_CMD_AUDIO_FORMAT_BITSTREAM 0x00ff
197/* audio_source */
198#define PS3AV_CMD_AUDIO_SOURCE_SERIAL 0x0000
199#define PS3AV_CMD_AUDIO_SOURCE_SPDIF 0x0001
200/* audio_swap */
201#define PS3AV_CMD_AUDIO_SWAP_0 0x0000
202#define PS3AV_CMD_AUDIO_SWAP_1 0x0000
203/* audio_map */
204#define PS3AV_CMD_AUDIO_MAP_OUTPUT_0 0x0000
205#define PS3AV_CMD_AUDIO_MAP_OUTPUT_1 0x0001
206#define PS3AV_CMD_AUDIO_MAP_OUTPUT_2 0x0002
207#define PS3AV_CMD_AUDIO_MAP_OUTPUT_3 0x0003
208/* audio_layout */
209#define PS3AV_CMD_AUDIO_LAYOUT_2CH 0x0000
210#define PS3AV_CMD_AUDIO_LAYOUT_6CH 0x000b /* LREClr */
211#define PS3AV_CMD_AUDIO_LAYOUT_8CH 0x001f /* LREClrXY */
212/* audio_downmix */
213#define PS3AV_CMD_AUDIO_DOWNMIX_PERMITTED 0x0000
214#define PS3AV_CMD_AUDIO_DOWNMIX_PROHIBITED 0x0001
215
216/* audio_port */
217#define PS3AV_CMD_AUDIO_PORT_HDMI_0 ( 1 << 0 )
218#define PS3AV_CMD_AUDIO_PORT_HDMI_1 ( 1 << 1 )
219#define PS3AV_CMD_AUDIO_PORT_AVMULTI_0 ( 1 << 10 )
220#define PS3AV_CMD_AUDIO_PORT_SPDIF_0 ( 1 << 20 )
221#define PS3AV_CMD_AUDIO_PORT_SPDIF_1 ( 1 << 21 )
222
223/* audio_ctrl_id */
224#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_RESET 0x0000
225#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_DE_EMPHASIS 0x0001
226#define PS3AV_CMD_AUDIO_CTRL_ID_AVCLK 0x0002
227/* audio_ctrl_data[0] reset */
228#define PS3AV_CMD_AUDIO_CTRL_RESET_NEGATE 0x0000
229#define PS3AV_CMD_AUDIO_CTRL_RESET_ASSERT 0x0001
230/* audio_ctrl_data[0] de-emphasis */
231#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_OFF 0x0000
232#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_ON 0x0001
233/* audio_ctrl_data[0] avclk */
234#define PS3AV_CMD_AUDIO_CTRL_AVCLK_22 0x0000
235#define PS3AV_CMD_AUDIO_CTRL_AVCLK_18 0x0001
236
237/* av_vid */
238/* do not use these params directly, use vid_video2av */
239#define PS3AV_CMD_AV_VID_480I 0x0000
240#define PS3AV_CMD_AV_VID_480P 0x0001
241#define PS3AV_CMD_AV_VID_720P_60HZ 0x0002
242#define PS3AV_CMD_AV_VID_1080I_60HZ 0x0003
243#define PS3AV_CMD_AV_VID_1080P_60HZ 0x0004
244#define PS3AV_CMD_AV_VID_576I 0x0005
245#define PS3AV_CMD_AV_VID_576P 0x0006
246#define PS3AV_CMD_AV_VID_720P_50HZ 0x0007
247#define PS3AV_CMD_AV_VID_1080I_50HZ 0x0008
248#define PS3AV_CMD_AV_VID_1080P_50HZ 0x0009
249#define PS3AV_CMD_AV_VID_WXGA 0x000a
250#define PS3AV_CMD_AV_VID_SXGA 0x000b
251#define PS3AV_CMD_AV_VID_WUXGA 0x000c
252/* av_cs_out av_cs_in */
253/* use cs_video2av() */
254#define PS3AV_CMD_AV_CS_RGB_8 0x0000
255#define PS3AV_CMD_AV_CS_YUV444_8 0x0001
256#define PS3AV_CMD_AV_CS_YUV422_8 0x0002
257#define PS3AV_CMD_AV_CS_XVYCC_8 0x0003
258#define PS3AV_CMD_AV_CS_RGB_10 0x0004
259#define PS3AV_CMD_AV_CS_YUV444_10 0x0005
260#define PS3AV_CMD_AV_CS_YUV422_10 0x0006
261#define PS3AV_CMD_AV_CS_XVYCC_10 0x0007
262#define PS3AV_CMD_AV_CS_RGB_12 0x0008
263#define PS3AV_CMD_AV_CS_YUV444_12 0x0009
264#define PS3AV_CMD_AV_CS_YUV422_12 0x000a
265#define PS3AV_CMD_AV_CS_XVYCC_12 0x000b
266#define PS3AV_CMD_AV_CS_8 0x0000
267#define PS3AV_CMD_AV_CS_10 0x0001
268#define PS3AV_CMD_AV_CS_12 0x0002
269/* dither */
270#define PS3AV_CMD_AV_DITHER_OFF 0x0000
271#define PS3AV_CMD_AV_DITHER_ON 0x0001
272#define PS3AV_CMD_AV_DITHER_8BIT 0x0000
273#define PS3AV_CMD_AV_DITHER_10BIT 0x0002
274#define PS3AV_CMD_AV_DITHER_12BIT 0x0004
275/* super_white */
276#define PS3AV_CMD_AV_SUPER_WHITE_OFF 0x0000
277#define PS3AV_CMD_AV_SUPER_WHITE_ON 0x0001
278/* aspect */
279#define PS3AV_CMD_AV_ASPECT_16_9 0x0000
280#define PS3AV_CMD_AV_ASPECT_4_3 0x0001
281/* video_cs_cnv() */
282#define PS3AV_CMD_VIDEO_CS_RGB 0x0001
283#define PS3AV_CMD_VIDEO_CS_YUV422 0x0002
284#define PS3AV_CMD_VIDEO_CS_YUV444 0x0003
285
286/* for broadcast automode */
287#define PS3AV_RESBIT_720x480P 0x0003 /* 0x0001 | 0x0002 */
288#define PS3AV_RESBIT_720x576P 0x0003 /* 0x0001 | 0x0002 */
289#define PS3AV_RESBIT_1280x720P 0x0004
290#define PS3AV_RESBIT_1920x1080I 0x0008
291#define PS3AV_RESBIT_1920x1080P 0x4000
292#define PS3AV_RES_MASK_60 (PS3AV_RESBIT_720x480P \
293 | PS3AV_RESBIT_1280x720P \
294 | PS3AV_RESBIT_1920x1080I \
295 | PS3AV_RESBIT_1920x1080P)
296#define PS3AV_RES_MASK_50 (PS3AV_RESBIT_720x576P \
297 | PS3AV_RESBIT_1280x720P \
298 | PS3AV_RESBIT_1920x1080I \
299 | PS3AV_RESBIT_1920x1080P)
300
301/* for VESA automode */
302#define PS3AV_RESBIT_VGA 0x0001
303#define PS3AV_RESBIT_WXGA 0x0002
304#define PS3AV_RESBIT_SXGA 0x0004
305#define PS3AV_RESBIT_WUXGA 0x0008
306#define PS3AV_RES_MASK_VESA (PS3AV_RESBIT_WXGA |\
307 PS3AV_RESBIT_SXGA |\
308 PS3AV_RESBIT_WUXGA)
309
310#define PS3AV_MONITOR_TYPE_HDMI 1 /* HDMI */
311#define PS3AV_MONITOR_TYPE_DVI 2 /* DVI */
312
313
314/* for video mode */
315enum ps3av_mode_num {
316 PS3AV_MODE_AUTO = 0,
317 PS3AV_MODE_480I = 1,
318 PS3AV_MODE_480P = 2,
319 PS3AV_MODE_720P60 = 3,
320 PS3AV_MODE_1080I60 = 4,
321 PS3AV_MODE_1080P60 = 5,
322 PS3AV_MODE_576I = 6,
323 PS3AV_MODE_576P = 7,
324 PS3AV_MODE_720P50 = 8,
325 PS3AV_MODE_1080I50 = 9,
326 PS3AV_MODE_1080P50 = 10,
327 PS3AV_MODE_WXGA = 11,
328 PS3AV_MODE_SXGA = 12,
329 PS3AV_MODE_WUXGA = 13,
330};
331
332#define PS3AV_MODE_MASK 0x000F
333#define PS3AV_MODE_HDCP_OFF 0x1000 /* Retail PS3 product doesn't support this */
334#define PS3AV_MODE_DITHER 0x0800
335#define PS3AV_MODE_COLOR 0x0400
336#define PS3AV_MODE_WHITE 0x0200
337#define PS3AV_MODE_FULL 0x0080
338#define PS3AV_MODE_DVI 0x0040
339#define PS3AV_MODE_RGB 0x0020
340
341
342#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_60 PS3AV_MODE_480P
343#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_60 PS3AV_MODE_480I
344#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_50 PS3AV_MODE_576P
345#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_50 PS3AV_MODE_576I
346
347#define PS3AV_REGION_60 0x01
348#define PS3AV_REGION_50 0x02
349#define PS3AV_REGION_RGB 0x10
350
351#define get_status(buf) (((__u32 *)buf)[2])
352#define PS3AV_HDR_SIZE 4 /* version + size */
353
354
355/** command packet structure **/
356struct ps3av_send_hdr {
357 u16 version;
358 u16 size; /* size of command packet */
359 u32 cid; /* command id */
360};
361
362struct ps3av_reply_hdr {
363 u16 version;
364 u16 size;
365 u32 cid;
366 u32 status;
367};
368
369/* backend: initialization */
370struct ps3av_pkt_av_init {
371 struct ps3av_send_hdr send_hdr;
372 u32 event_bit;
373};
374
375/* backend: finalize */
376struct ps3av_pkt_av_fin {
377 struct ps3av_send_hdr send_hdr;
378 /* recv */
379 u32 reserved;
380};
381
382/* backend: get port */
383struct ps3av_pkt_av_get_hw_conf {
384 struct ps3av_send_hdr send_hdr;
385 /* recv */
386 u32 status;
387 u16 num_of_hdmi; /* out: number of hdmi */
388 u16 num_of_avmulti; /* out: number of avmulti */
389 u16 num_of_spdif; /* out: number of hdmi */
390 u16 reserved;
391};
392
393/* backend: get monitor info */
394struct ps3av_info_resolution {
395 u32 res_bits;
396 u32 native;
397};
398
399struct ps3av_info_cs {
400 u8 rgb;
401 u8 yuv444;
402 u8 yuv422;
403 u8 reserved;
404};
405
406struct ps3av_info_color {
407 u16 red_x;
408 u16 red_y;
409 u16 green_x;
410 u16 green_y;
411 u16 blue_x;
412 u16 blue_y;
413 u16 white_x;
414 u16 white_y;
415 u32 gamma;
416};
417
418struct ps3av_info_audio {
419 u8 type;
420 u8 max_num_of_ch;
421 u8 fs;
422 u8 sbit;
423};
424
425struct ps3av_info_monitor {
426 u8 avport;
427 u8 monitor_id[10];
428 u8 monitor_type;
429 u8 monitor_name[16];
430 struct ps3av_info_resolution res_60;
431 struct ps3av_info_resolution res_50;
432 struct ps3av_info_resolution res_other;
433 struct ps3av_info_resolution res_vesa;
434 struct ps3av_info_cs cs;
435 struct ps3av_info_color color;
436 u8 supported_ai;
437 u8 speaker_info;
438 u8 num_of_audio_block;
439 struct ps3av_info_audio audio[0]; /* 0 or more audio blocks */
440 u8 reserved[169];
441} __attribute__ ((packed));
442
443struct ps3av_pkt_av_get_monitor_info {
444 struct ps3av_send_hdr send_hdr;
445 u16 avport; /* in: avport */
446 u16 reserved;
447 /* recv */
448 struct ps3av_info_monitor info; /* out: monitor info */
449};
450
451/* backend: enable/disable event */
452struct ps3av_pkt_av_event {
453 struct ps3av_send_hdr send_hdr;
454 u32 event_bit; /* in */
455};
456
457/* backend: video cs param */
458struct ps3av_pkt_av_video_cs {
459 struct ps3av_send_hdr send_hdr;
460 u16 avport; /* in: avport */
461 u16 av_vid; /* in: video resolution */
462 u16 av_cs_out; /* in: output color space */
463 u16 av_cs_in; /* in: input color space */
464 u8 dither; /* in: dither bit length */
465 u8 bitlen_out; /* in: bit length */
466 u8 super_white; /* in: super white */
467 u8 aspect; /* in: aspect ratio */
468};
469
470/* backend: video mute */
471struct ps3av_av_mute {
472 u16 avport; /* in: avport */
473 u16 mute; /* in: mute on/off */
474};
475
476struct ps3av_pkt_av_video_mute {
477 struct ps3av_send_hdr send_hdr;
478 struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
479};
480
481/* backend: video disable signal */
482struct ps3av_pkt_av_video_disable_sig {
483 struct ps3av_send_hdr send_hdr;
484 u16 avport; /* in: avport */
485 u16 reserved;
486};
487
488/* backend: audio param */
489struct ps3av_audio_info_frame {
490 struct pb1_bit {
491 u8 ct:4;
492 u8 rsv:1;
493 u8 cc:3;
494 } pb1;
495 struct pb2_bit {
496 u8 rsv:3;
497 u8 sf:3;
498 u8 ss:2;
499 } pb2;
500 u8 pb3;
501 u8 pb4;
502 struct pb5_bit {
503 u8 dm:1;
504 u8 lsv:4;
505 u8 rsv:3;
506 } pb5;
507};
508
509struct ps3av_pkt_av_audio_param {
510 struct ps3av_send_hdr send_hdr;
511 u16 avport; /* in: avport */
512 u16 reserved;
513 u8 mclk; /* in: audio mclk */
514 u8 ns[3]; /* in: audio ns val */
515 u8 enable; /* in: audio enable */
516 u8 swaplr; /* in: audio swap */
517 u8 fifomap; /* in: audio fifomap */
518 u8 inputctrl; /* in: audio input ctrl */
519 u8 inputlen; /* in: sample bit size */
520 u8 layout; /* in: speaker layout param */
521 struct ps3av_audio_info_frame info; /* in: info */
522 u8 chstat[5]; /* in: ch stat */
523};
524
525/* backend: audio_mute */
526struct ps3av_pkt_av_audio_mute {
527 struct ps3av_send_hdr send_hdr;
528 struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
529};
530
531/* backend: hdmi_mode */
532struct ps3av_pkt_av_hdmi_mode {
533 struct ps3av_send_hdr send_hdr;
534 u8 mode; /* in: hdmi_mode */
535 u8 reserved0;
536 u8 reserved1;
537 u8 reserved2;
538};
539
540/* backend: tv_mute */
541struct ps3av_pkt_av_tv_mute {
542 struct ps3av_send_hdr send_hdr;
543 u16 avport; /* in: avport HDMI only */
544 u16 mute; /* in: mute */
545};
546
547/* video: initialize */
548struct ps3av_pkt_video_init {
549 struct ps3av_send_hdr send_hdr;
550 /* recv */
551 u32 reserved;
552};
553
554/* video: mode setting */
555struct ps3av_pkt_video_mode {
556 struct ps3av_send_hdr send_hdr;
557 u32 video_head; /* in: head */
558 u32 reserved;
559 u32 video_vid; /* in: video resolution */
560 u16 reserved1;
561 u16 width; /* in: width in pixel */
562 u16 reserved2;
563 u16 height; /* in: height in pixel */
564 u32 pitch; /* in: line size in byte */
565 u32 video_out_format; /* in: out format */
566 u32 video_format; /* in: input frame buffer format */
567 u8 reserved3;
568 u8 video_cl_cnv; /* in: color conversion */
569 u16 video_order; /* in: input RGB order */
570 u32 reserved4;
571};
572
573/* video: format */
574struct ps3av_pkt_video_format {
575 struct ps3av_send_hdr send_hdr;
576 u32 video_head; /* in: head */
577 u32 video_format; /* in: frame buffer format */
578 u8 reserved;
579 u8 video_cl_cnv; /* in: color conversion */
580 u16 video_order; /* in: input RGB order */
581};
582
583/* video: pitch */
584struct ps3av_pkt_video_pitch {
585 u16 version;
586 u16 size; /* size of command packet */
587 u32 cid; /* command id */
588 u32 video_head; /* in: head */
589 u32 pitch; /* in: line size in byte */
590};
591
592/* audio: initialize */
593struct ps3av_pkt_audio_init {
594 struct ps3av_send_hdr send_hdr;
595 /* recv */
596 u32 reserved;
597};
598
599/* audio: mode setting */
600struct ps3av_pkt_audio_mode {
601 struct ps3av_send_hdr send_hdr;
602 u8 avport; /* in: avport */
603 u8 reserved0[3];
604 u32 mask; /* in: mask */
605 u32 audio_num_of_ch; /* in: number of ch */
606 u32 audio_fs; /* in: sampling freq */
607 u32 audio_word_bits; /* in: sample bit size */
608 u32 audio_format; /* in: audio output format */
609 u32 audio_source; /* in: audio source */
610 u8 audio_enable[4]; /* in: audio enable */
611 u8 audio_swap[4]; /* in: audio swap */
612 u8 audio_map[4]; /* in: audio map */
613 u32 audio_layout; /* in: speaker layout */
614 u32 audio_downmix; /* in: audio downmix permission */
615 u32 audio_downmix_level;
616 u8 audio_cs_info[8]; /* in: IEC channel status */
617};
618
619/* audio: mute */
620struct ps3av_audio_mute {
621 u8 avport; /* in: opt_port optical */
622 u8 reserved[3];
623 u32 mute; /* in: mute */
624};
625
626struct ps3av_pkt_audio_mute {
627 struct ps3av_send_hdr send_hdr;
628 struct ps3av_audio_mute mute[PS3AV_OPT_PORT_MAX];
629};
630
631/* audio: active/inactive */
632struct ps3av_pkt_audio_active {
633 struct ps3av_send_hdr send_hdr;
634 u32 audio_port; /* in: audio active/inactive port */
635};
636
637/* audio: SPDIF user bit */
638struct ps3av_pkt_audio_spdif_bit {
639 u16 version;
640 u16 size; /* size of command packet */
641 u32 cid; /* command id */
642 u8 avport; /* in: avport SPDIF only */
643 u8 reserved[3];
644 u32 audio_port; /* in: SPDIF only */
645 u32 spdif_bit_data[12]; /* in: user bit data */
646};
647
648/* audio: audio control */
649struct ps3av_pkt_audio_ctrl {
650 u16 version;
651 u16 size; /* size of command packet */
652 u32 cid; /* command id */
653 u32 audio_ctrl_id; /* in: control id */
654 u32 audio_ctrl_data[4]; /* in: control data */
655};
656
657/* avb:param */
658#define PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE \
659 (PS3AV_AVB_NUM_VIDEO*sizeof(struct ps3av_pkt_video_mode) + \
660 PS3AV_AVB_NUM_AUDIO*sizeof(struct ps3av_pkt_audio_mode) + \
661 PS3AV_AVB_NUM_AV_VIDEO*sizeof(struct ps3av_pkt_av_video_cs) + \
662 PS3AV_AVB_NUM_AV_AUDIO*sizeof(struct ps3av_pkt_av_audio_param))
663
664struct ps3av_pkt_avb_param {
665 struct ps3av_send_hdr send_hdr;
666 u16 num_of_video_pkt;
667 u16 num_of_audio_pkt;
668 u16 num_of_av_video_pkt;
669 u16 num_of_av_audio_pkt;
670 /*
671 * The actual buffer layout depends on the fields above:
672 *
673 * struct ps3av_pkt_video_mode video[num_of_video_pkt];
674 * struct ps3av_pkt_audio_mode audio[num_of_audio_pkt];
675 * struct ps3av_pkt_av_video_cs av_video[num_of_av_video_pkt];
676 * struct ps3av_pkt_av_audio_param av_audio[num_of_av_audio_pkt];
677 */
678 u8 buf[PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE];
679};
680
681
682/** command status **/
683#define PS3AV_STATUS_SUCCESS 0x0000 /* success */
684#define PS3AV_STATUS_RECEIVE_VUART_ERROR 0x0001 /* receive vuart error */
685#define PS3AV_STATUS_SYSCON_COMMUNICATE_FAIL 0x0002 /* syscon communication error */
686#define PS3AV_STATUS_INVALID_COMMAND 0x0003 /* obsolete invalid CID */
687#define PS3AV_STATUS_INVALID_PORT 0x0004 /* invalid port number */
688#define PS3AV_STATUS_INVALID_VID 0x0005 /* invalid video format */
689#define PS3AV_STATUS_INVALID_COLOR_SPACE 0x0006 /* invalid video colose space */
690#define PS3AV_STATUS_INVALID_FS 0x0007 /* invalid audio sampling freq */
691#define PS3AV_STATUS_INVALID_AUDIO_CH 0x0008 /* invalid audio channel number */
692#define PS3AV_STATUS_UNSUPPORTED_VERSION 0x0009 /* version mismatch */
693#define PS3AV_STATUS_INVALID_SAMPLE_SIZE 0x000a /* invalid audio sample bit size */
694#define PS3AV_STATUS_FAILURE 0x000b /* other failures */
695#define PS3AV_STATUS_UNSUPPORTED_COMMAND 0x000c /* unsupported cid */
696#define PS3AV_STATUS_BUFFER_OVERFLOW 0x000d /* write buffer overflow */
697#define PS3AV_STATUS_INVALID_VIDEO_PARAM 0x000e /* invalid video param */
698#define PS3AV_STATUS_NO_SEL 0x000f /* not exist selector */
699#define PS3AV_STATUS_INVALID_AV_PARAM 0x0010 /* invalid backend param */
700#define PS3AV_STATUS_INVALID_AUDIO_PARAM 0x0011 /* invalid audio param */
701#define PS3AV_STATUS_UNSUPPORTED_HDMI_MODE 0x0012 /* unsupported hdmi mode */
702#define PS3AV_STATUS_NO_SYNC_HEAD 0x0013 /* sync head failed */
703
704extern void ps3av_set_hdr(u32, u16, struct ps3av_send_hdr *);
705extern int ps3av_do_pkt(u32, u16, size_t, struct ps3av_send_hdr *);
706
707extern int ps3av_cmd_init(void);
708extern int ps3av_cmd_fin(void);
709extern int ps3av_cmd_av_video_mute(int, u32 *, u32);
710extern int ps3av_cmd_av_video_disable_sig(u32);
711extern int ps3av_cmd_av_tv_mute(u32, u32);
712extern int ps3av_cmd_enable_event(void);
713extern int ps3av_cmd_av_hdmi_mode(u8);
714extern u32 ps3av_cmd_set_av_video_cs(void *, u32, int, int, int, u32);
715extern u32 ps3av_cmd_set_video_mode(void *, u32, int, int, u32);
716extern int ps3av_cmd_video_format_black(u32, u32, u32);
717extern int ps3av_cmd_av_audio_mute(int, u32 *, u32);
718extern u32 ps3av_cmd_set_av_audio_param(void *, u32,
719 const struct ps3av_pkt_audio_mode *,
720 u32);
721extern void ps3av_cmd_set_audio_mode(struct ps3av_pkt_audio_mode *, u32, u32,
722 u32, u32, u32, u32);
723extern int ps3av_cmd_audio_mode(struct ps3av_pkt_audio_mode *);
724extern int ps3av_cmd_audio_mute(int, u32 *, u32);
725extern int ps3av_cmd_audio_active(int, u32);
726extern int ps3av_cmd_avb_param(struct ps3av_pkt_avb_param *, u32);
727extern int ps3av_cmd_av_get_hw_conf(struct ps3av_pkt_av_get_hw_conf *);
728extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *,
729 u32);
730
731extern int ps3av_set_video_mode(u32);
732extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32);
733extern int ps3av_get_auto_mode(void);
734extern int ps3av_get_mode(void);
735extern int ps3av_video_mode2res(u32, u32 *, u32 *);
736extern int ps3av_video_mute(int);
737extern int ps3av_audio_mute(int);
738extern int ps3av_dev_open(void);
739extern int ps3av_dev_close(void);
740extern void ps3av_register_flip_ctl(void (*flip_ctl)(int on, void *data),
741 void *flip_data);
742extern void ps3av_flip_ctl(int on);
743
744#endif /* _ASM_POWERPC_PS3AV_H_ */
diff --git a/arch/powerpc/include/asm/ps3fb.h b/arch/powerpc/include/asm/ps3fb.h
new file mode 100644
index 000000000000..3f121fe4010d
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3fb.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2006 Sony Computer Entertainment Inc.
3 * Copyright 2006, 2007 Sony Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published
7 * by the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _ASM_POWERPC_PS3FB_H_
20#define _ASM_POWERPC_PS3FB_H_
21
22#include <linux/ioctl.h>
23
24/* ioctl */
25#define PS3FB_IOCTL_SETMODE _IOW('r', 1, int) /* set video mode */
26#define PS3FB_IOCTL_GETMODE _IOR('r', 2, int) /* get video mode */
27#define PS3FB_IOCTL_SCREENINFO _IOR('r', 3, int) /* get screen info */
28#define PS3FB_IOCTL_ON _IO('r', 4) /* use IOCTL_FSEL */
29#define PS3FB_IOCTL_OFF _IO('r', 5) /* return to normal-flip */
30#define PS3FB_IOCTL_FSEL _IOW('r', 6, int) /* blit and flip request */
31
32#ifndef FBIO_WAITFORVSYNC
33#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) /* wait for vsync */
34#endif
35
36struct ps3fb_ioctl_res {
37 __u32 xres; /* frame buffer x_size */
38 __u32 yres; /* frame buffer y_size */
39 __u32 xoff; /* margine x */
40 __u32 yoff; /* margine y */
41 __u32 num_frames; /* num of frame buffers */
42};
43
44#endif /* _ASM_POWERPC_PS3FB_H_ */
diff --git a/arch/powerpc/include/asm/ps3stor.h b/arch/powerpc/include/asm/ps3stor.h
new file mode 100644
index 000000000000..6fcaf714fa50
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3stor.h
@@ -0,0 +1,71 @@
1/*
2 * PS3 Storage Devices
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published
9 * by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _ASM_POWERPC_PS3STOR_H_
22#define _ASM_POWERPC_PS3STOR_H_
23
24#include <linux/interrupt.h>
25
26#include <asm/ps3.h>
27
28
29struct ps3_storage_region {
30 unsigned int id;
31 u64 start;
32 u64 size;
33};
34
35struct ps3_storage_device {
36 struct ps3_system_bus_device sbd;
37
38 struct ps3_dma_region dma_region;
39 unsigned int irq;
40 u64 blk_size;
41
42 u64 tag;
43 u64 lv1_status;
44 struct completion done;
45
46 unsigned long bounce_size;
47 void *bounce_buf;
48 u64 bounce_lpar;
49 dma_addr_t bounce_dma;
50
51 unsigned int num_regions;
52 unsigned long accessible_regions;
53 unsigned int region_idx; /* first accessible region */
54 struct ps3_storage_region regions[0]; /* Must be last */
55};
56
57static inline struct ps3_storage_device *to_ps3_storage_device(struct device *dev)
58{
59 return container_of(dev, struct ps3_storage_device, sbd.core);
60}
61
62extern int ps3stor_setup(struct ps3_storage_device *dev,
63 irq_handler_t handler);
64extern void ps3stor_teardown(struct ps3_storage_device *dev);
65extern u64 ps3stor_read_write_sectors(struct ps3_storage_device *dev, u64 lpar,
66 u64 start_sector, u64 sectors,
67 int write);
68extern u64 ps3stor_send_command(struct ps3_storage_device *dev, u64 cmd,
69 u64 arg1, u64 arg2, u64 arg3, u64 arg4);
70
71#endif /* _ASM_POWERPC_PS3STOR_H_ */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
new file mode 100644
index 000000000000..734e0754fb9b
--- /dev/null
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -0,0 +1,293 @@
1#ifndef _ASM_POWERPC_PTRACE_H
2#define _ASM_POWERPC_PTRACE_H
3
4/*
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This struct defines the way the registers are stored on the
8 * kernel stack during a system call or other kernel entry.
9 *
10 * this should only contain volatile regs
11 * since we can keep non-volatile in the thread_struct
12 * should set this up when only volatiles are saved
13 * by intr code.
14 *
15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
16 * that the overall structure is a multiple of 16 bytes in length.
17 *
18 * Note that the offsets of the fields in this struct correspond with
19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version
24 * 2 of the License, or (at your option) any later version.
25 */
26
27#ifndef __ASSEMBLY__
28
29struct pt_regs {
30 unsigned long gpr[32];
31 unsigned long nip;
32 unsigned long msr;
33 unsigned long orig_gpr3; /* Used for restarting system calls */
34 unsigned long ctr;
35 unsigned long link;
36 unsigned long xer;
37 unsigned long ccr;
38#ifdef __powerpc64__
39 unsigned long softe; /* Soft enabled/disabled */
40#else
41 unsigned long mq; /* 601 only (not used at present) */
42 /* Used on APUS to hold IPL value. */
43#endif
44 unsigned long trap; /* Reason for being here */
45 /* N.B. for critical exceptions on 4xx, the dar and dsisr
46 fields are overloaded to hold srr0 and srr1. */
47 unsigned long dar; /* Fault registers */
48 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
49 unsigned long result; /* Result of a system call */
50};
51
52#endif /* __ASSEMBLY__ */
53
54#ifdef __KERNEL__
55
56#ifdef __powerpc64__
57
58#define __ARCH_WANT_COMPAT_SYS_PTRACE
59
60#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
61#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
62#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
63#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
64 STACK_FRAME_OVERHEAD + 288)
65#define STACK_FRAME_MARKER 12
66
67/* Size of dummy stack frame allocated when calling signal handler. */
68#define __SIGNAL_FRAMESIZE 128
69#define __SIGNAL_FRAMESIZE32 64
70
71#else /* __powerpc64__ */
72
73#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
74#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
75#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
76#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
77#define STACK_FRAME_MARKER 2
78
79/* Size of stack frame allocated when calling signal handler. */
80#define __SIGNAL_FRAMESIZE 64
81
82#endif /* __powerpc64__ */
83
84#ifndef __ASSEMBLY__
85
86#define instruction_pointer(regs) ((regs)->nip)
87#define user_stack_pointer(regs) ((regs)->gpr[1])
88#define regs_return_value(regs) ((regs)->gpr[3])
89
90#ifdef CONFIG_SMP
91extern unsigned long profile_pc(struct pt_regs *regs);
92#else
93#define profile_pc(regs) instruction_pointer(regs)
94#endif
95
96#ifdef __powerpc64__
97#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
98#else
99#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
100#endif
101
102#define force_successful_syscall_return() \
103 do { \
104 set_thread_flag(TIF_NOERROR); \
105 } while(0)
106
107struct task_struct;
108extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
109extern int ptrace_put_reg(struct task_struct *task, int regno,
110 unsigned long data);
111
112/*
113 * We use the least-significant bit of the trap field to indicate
114 * whether we have saved the full set of registers, or only a
115 * partial set. A 1 there means the partial set.
116 * On 4xx we use the next bit to indicate whether the exception
117 * is a critical exception (1 means it is).
118 */
119#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
120#ifndef __powerpc64__
121#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0)
122#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0)
123#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0)
124#endif /* ! __powerpc64__ */
125#define TRAP(regs) ((regs)->trap & ~0xF)
126#ifdef __powerpc64__
127#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
128#else
129#define CHECK_FULL_REGS(regs) \
130do { \
131 if ((regs)->trap & 1) \
132 printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
133} while (0)
134#endif /* __powerpc64__ */
135
136/*
137 * These are defined as per linux/ptrace.h, which see.
138 */
139#define arch_has_single_step() (1)
140extern void user_enable_single_step(struct task_struct *);
141extern void user_disable_single_step(struct task_struct *);
142
143#endif /* __ASSEMBLY__ */
144
145#endif /* __KERNEL__ */
146
147/*
148 * Offsets used by 'ptrace' system call interface.
149 * These can't be changed without breaking binary compatibility
150 * with MkLinux, etc.
151 */
152#define PT_R0 0
153#define PT_R1 1
154#define PT_R2 2
155#define PT_R3 3
156#define PT_R4 4
157#define PT_R5 5
158#define PT_R6 6
159#define PT_R7 7
160#define PT_R8 8
161#define PT_R9 9
162#define PT_R10 10
163#define PT_R11 11
164#define PT_R12 12
165#define PT_R13 13
166#define PT_R14 14
167#define PT_R15 15
168#define PT_R16 16
169#define PT_R17 17
170#define PT_R18 18
171#define PT_R19 19
172#define PT_R20 20
173#define PT_R21 21
174#define PT_R22 22
175#define PT_R23 23
176#define PT_R24 24
177#define PT_R25 25
178#define PT_R26 26
179#define PT_R27 27
180#define PT_R28 28
181#define PT_R29 29
182#define PT_R30 30
183#define PT_R31 31
184
185#define PT_NIP 32
186#define PT_MSR 33
187#define PT_ORIG_R3 34
188#define PT_CTR 35
189#define PT_LNK 36
190#define PT_XER 37
191#define PT_CCR 38
192#ifndef __powerpc64__
193#define PT_MQ 39
194#else
195#define PT_SOFTE 39
196#endif
197#define PT_TRAP 40
198#define PT_DAR 41
199#define PT_DSISR 42
200#define PT_RESULT 43
201#define PT_REGS_COUNT 44
202
203#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
204
205#ifndef __powerpc64__
206
207#define PT_FPR31 (PT_FPR0 + 2*31)
208#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
209
210#else /* __powerpc64__ */
211
212#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
213
214#ifdef __KERNEL__
215#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
216#endif
217
218#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
219#define PT_VSCR (PT_VR0 + 32*2 + 1)
220#define PT_VRSAVE (PT_VR0 + 33*2)
221
222#ifdef __KERNEL__
223#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */
224#define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
225#define PT_VRSAVE_32 (PT_VR0 + 33*4)
226#endif
227
228/*
229 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
230 */
231#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
232#define PT_VSR31 (PT_VSR0 + 2*31)
233#ifdef __KERNEL__
234#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */
235#endif
236#endif /* __powerpc64__ */
237
238/*
239 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
240 * The transfer totals 34 quadword. Quadwords 0-31 contain the
241 * corresponding vector registers. Quadword 32 contains the vscr as the
242 * last word (offset 12) within that quadword. Quadword 33 contains the
243 * vrsave as the first word (offset 0) within the quadword.
244 *
245 * This definition of the VMX state is compatible with the current PPC32
246 * ptrace interface. This allows signal handling and ptrace to use the same
247 * structures. This also simplifies the implementation of a bi-arch
248 * (combined (32- and 64-bit) gdb.
249 */
250#define PTRACE_GETVRREGS 18
251#define PTRACE_SETVRREGS 19
252
253/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
254 * spefscr, in one go */
255#define PTRACE_GETEVRREGS 20
256#define PTRACE_SETEVRREGS 21
257
258/* Get the first 32 128bit VSX registers */
259#define PTRACE_GETVSRREGS 27
260#define PTRACE_SETVSRREGS 28
261
262/*
263 * Get or set a debug register. The first 16 are DABR registers and the
264 * second 16 are IABR registers.
265 */
266#define PTRACE_GET_DEBUGREG 25
267#define PTRACE_SET_DEBUGREG 26
268
269/* (new) PTRACE requests using the same numbers as x86 and the same
270 * argument ordering. Additionally, they support more registers too
271 */
272#define PTRACE_GETREGS 12
273#define PTRACE_SETREGS 13
274#define PTRACE_GETFPREGS 14
275#define PTRACE_SETFPREGS 15
276#define PTRACE_GETREGS64 22
277#define PTRACE_SETREGS64 23
278
279/* (old) PTRACE requests with inverted arguments */
280#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
281#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
282#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
283#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
284
285/* Calls to trace a 64bit program from a 32bit program */
286#define PPC_PTRACE_PEEKTEXT_3264 0x95
287#define PPC_PTRACE_PEEKDATA_3264 0x94
288#define PPC_PTRACE_POKETEXT_3264 0x93
289#define PPC_PTRACE_POKEDATA_3264 0x92
290#define PPC_PTRACE_PEEKUSR_3264 0x91
291#define PPC_PTRACE_POKEUSR_3264 0x90
292
293#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
new file mode 100644
index 000000000000..edee15d269ea
--- /dev/null
+++ b/arch/powerpc/include/asm/qe.h
@@ -0,0 +1,642 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <linux/spinlock.h>
20#include <asm/cpm.h>
21#include <asm/immap_qe.h>
22
23#define QE_NUM_OF_SNUM 28
24#define QE_NUM_OF_BRGS 16
25#define QE_NUM_OF_PORTS 1024
26
27/* Memory partitions
28*/
29#define MEM_PART_SYSTEM 0
30#define MEM_PART_SECONDARY 1
31#define MEM_PART_MURAM 2
32
33/* Clocks and BRGs */
34enum qe_clock {
35 QE_CLK_NONE = 0,
36 QE_BRG1, /* Baud Rate Generator 1 */
37 QE_BRG2, /* Baud Rate Generator 2 */
38 QE_BRG3, /* Baud Rate Generator 3 */
39 QE_BRG4, /* Baud Rate Generator 4 */
40 QE_BRG5, /* Baud Rate Generator 5 */
41 QE_BRG6, /* Baud Rate Generator 6 */
42 QE_BRG7, /* Baud Rate Generator 7 */
43 QE_BRG8, /* Baud Rate Generator 8 */
44 QE_BRG9, /* Baud Rate Generator 9 */
45 QE_BRG10, /* Baud Rate Generator 10 */
46 QE_BRG11, /* Baud Rate Generator 11 */
47 QE_BRG12, /* Baud Rate Generator 12 */
48 QE_BRG13, /* Baud Rate Generator 13 */
49 QE_BRG14, /* Baud Rate Generator 14 */
50 QE_BRG15, /* Baud Rate Generator 15 */
51 QE_BRG16, /* Baud Rate Generator 16 */
52 QE_CLK1, /* Clock 1 */
53 QE_CLK2, /* Clock 2 */
54 QE_CLK3, /* Clock 3 */
55 QE_CLK4, /* Clock 4 */
56 QE_CLK5, /* Clock 5 */
57 QE_CLK6, /* Clock 6 */
58 QE_CLK7, /* Clock 7 */
59 QE_CLK8, /* Clock 8 */
60 QE_CLK9, /* Clock 9 */
61 QE_CLK10, /* Clock 10 */
62 QE_CLK11, /* Clock 11 */
63 QE_CLK12, /* Clock 12 */
64 QE_CLK13, /* Clock 13 */
65 QE_CLK14, /* Clock 14 */
66 QE_CLK15, /* Clock 15 */
67 QE_CLK16, /* Clock 16 */
68 QE_CLK17, /* Clock 17 */
69 QE_CLK18, /* Clock 18 */
70 QE_CLK19, /* Clock 19 */
71 QE_CLK20, /* Clock 20 */
72 QE_CLK21, /* Clock 21 */
73 QE_CLK22, /* Clock 22 */
74 QE_CLK23, /* Clock 23 */
75 QE_CLK24, /* Clock 24 */
76 QE_CLK_DUMMY
77};
78
79static inline bool qe_clock_is_brg(enum qe_clock clk)
80{
81 return clk >= QE_BRG1 && clk <= QE_BRG16;
82}
83
84extern spinlock_t cmxgcr_lock;
85
86/* Export QE common operations */
87extern void __init qe_reset(void);
88
89/* QE PIO */
90#define QE_PIO_PINS 32
91
92struct qe_pio_regs {
93 __be32 cpodr; /* Open drain register */
94 __be32 cpdata; /* Data register */
95 __be32 cpdir1; /* Direction register */
96 __be32 cpdir2; /* Direction register */
97 __be32 cppar1; /* Pin assignment register */
98 __be32 cppar2; /* Pin assignment register */
99#ifdef CONFIG_PPC_85xx
100 u8 pad[8];
101#endif
102};
103
104extern int par_io_init(struct device_node *np);
105extern int par_io_of_config(struct device_node *np);
106#define QE_PIO_DIR_IN 2
107#define QE_PIO_DIR_OUT 1
108extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
109 int dir, int open_drain, int assignment,
110 int has_irq);
111extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
112 int assignment, int has_irq);
113extern int par_io_data_set(u8 port, u8 pin, u8 val);
114
115/* QE internal API */
116int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
117enum qe_clock qe_clock_source(const char *source);
118unsigned int qe_get_brg_clk(void);
119int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
120int qe_get_snum(void);
121void qe_put_snum(u8 snum);
122/* we actually use cpm_muram implementation, define this for convenience */
123#define qe_muram_init cpm_muram_init
124#define qe_muram_alloc cpm_muram_alloc
125#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
126#define qe_muram_free cpm_muram_free
127#define qe_muram_addr cpm_muram_addr
128#define qe_muram_offset cpm_muram_offset
129
130/* Structure that defines QE firmware binary files.
131 *
132 * See Documentation/powerpc/qe-firmware.txt for a description of these
133 * fields.
134 */
135struct qe_firmware {
136 struct qe_header {
137 __be32 length; /* Length of the entire structure, in bytes */
138 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
139 u8 version; /* Version of this layout. First ver is '1' */
140 } header;
141 u8 id[62]; /* Null-terminated identifier string */
142 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
143 u8 count; /* Number of microcode[] structures */
144 struct {
145 __be16 model; /* The SOC model */
146 u8 major; /* The SOC revision major */
147 u8 minor; /* The SOC revision minor */
148 } __attribute__ ((packed)) soc;
149 u8 padding[4]; /* Reserved, for alignment */
150 __be64 extended_modes; /* Extended modes */
151 __be32 vtraps[8]; /* Virtual trap addresses */
152 u8 reserved[4]; /* Reserved, for future expansion */
153 struct qe_microcode {
154 u8 id[32]; /* Null-terminated identifier */
155 __be32 traps[16]; /* Trap addresses, 0 == ignore */
156 __be32 eccr; /* The value for the ECCR register */
157 __be32 iram_offset; /* Offset into I-RAM for the code */
158 __be32 count; /* Number of 32-bit words of the code */
159 __be32 code_offset; /* Offset of the actual microcode */
160 u8 major; /* The microcode version major */
161 u8 minor; /* The microcode version minor */
162 u8 revision; /* The microcode version revision */
163 u8 padding; /* Reserved, for alignment */
164 u8 reserved[4]; /* Reserved, for future expansion */
165 } __attribute__ ((packed)) microcode[1];
166 /* All microcode binaries should be located here */
167 /* CRC32 should be located here, after the microcode binaries */
168} __attribute__ ((packed));
169
170struct qe_firmware_info {
171 char id[64]; /* Firmware name */
172 u32 vtraps[8]; /* Virtual trap addresses */
173 u64 extended_modes; /* Extended modes */
174};
175
176/* Upload a firmware to the QE */
177int qe_upload_firmware(const struct qe_firmware *firmware);
178
179/* Obtain information on the uploaded firmware */
180struct qe_firmware_info *qe_get_firmware_info(void);
181
182/* QE USB */
183int qe_usb_clock_set(enum qe_clock clk, int rate);
184
185/* Buffer descriptors */
186struct qe_bd {
187 __be16 status;
188 __be16 length;
189 __be32 buf;
190} __attribute__ ((packed));
191
192#define BD_STATUS_MASK 0xffff0000
193#define BD_LENGTH_MASK 0x0000ffff
194
195/* Alignment */
196#define QE_INTR_TABLE_ALIGN 16 /* ??? */
197#define QE_ALIGNMENT_OF_BD 8
198#define QE_ALIGNMENT_OF_PRAM 64
199
200/* RISC allocation */
201enum qe_risc_allocation {
202 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
203 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
204 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
205 RISC 1 or RISC 2 */
206};
207
208/* QE extended filtering Table Lookup Key Size */
209enum qe_fltr_tbl_lookup_key_size {
210 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
211 = 0x3f, /* LookupKey parsed by the Generate LookupKey
212 CMD is truncated to 8 bytes */
213 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
214 = 0x5f, /* LookupKey parsed by the Generate LookupKey
215 CMD is truncated to 16 bytes */
216};
217
218/* QE FLTR extended filtering Largest External Table Lookup Key Size */
219enum qe_fltr_largest_external_tbl_lookup_key_size {
220 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
221 = 0x0,/* not used */
222 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
223 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
224 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
225 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
226};
227
228/* structure representing QE parameter RAM */
229struct qe_timer_tables {
230 u16 tm_base; /* QE timer table base adr */
231 u16 tm_ptr; /* QE timer table pointer */
232 u16 r_tmr; /* QE timer mode register */
233 u16 r_tmv; /* QE timer valid register */
234 u32 tm_cmd; /* QE timer cmd register */
235 u32 tm_cnt; /* QE timer internal cnt */
236} __attribute__ ((packed));
237
238#define QE_FLTR_TAD_SIZE 8
239
240/* QE extended filtering Termination Action Descriptor (TAD) */
241struct qe_fltr_tad {
242 u8 serialized[QE_FLTR_TAD_SIZE];
243} __attribute__ ((packed));
244
245/* Communication Direction */
246enum comm_dir {
247 COMM_DIR_NONE = 0,
248 COMM_DIR_RX = 1,
249 COMM_DIR_TX = 2,
250 COMM_DIR_RX_AND_TX = 3
251};
252
253/* QE CMXUCR Registers.
254 * There are two UCCs represented in each of the four CMXUCR registers.
255 * These values are for the UCC in the LSBs
256 */
257#define QE_CMXUCR_MII_ENET_MNG 0x00007000
258#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
259#define QE_CMXUCR_GRANT 0x00008000
260#define QE_CMXUCR_TSA 0x00004000
261#define QE_CMXUCR_BKPT 0x00000100
262#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
263
264/* QE CMXGCR Registers.
265*/
266#define QE_CMXGCR_MII_ENET_MNG 0x00007000
267#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
268#define QE_CMXGCR_USBCS 0x0000000f
269#define QE_CMXGCR_USBCS_CLK3 0x1
270#define QE_CMXGCR_USBCS_CLK5 0x2
271#define QE_CMXGCR_USBCS_CLK7 0x3
272#define QE_CMXGCR_USBCS_CLK9 0x4
273#define QE_CMXGCR_USBCS_CLK13 0x5
274#define QE_CMXGCR_USBCS_CLK17 0x6
275#define QE_CMXGCR_USBCS_CLK19 0x7
276#define QE_CMXGCR_USBCS_CLK21 0x8
277#define QE_CMXGCR_USBCS_BRG9 0x9
278#define QE_CMXGCR_USBCS_BRG10 0xa
279
280/* QE CECR Commands.
281*/
282#define QE_CR_FLG 0x00010000
283#define QE_RESET 0x80000000
284#define QE_INIT_TX_RX 0x00000000
285#define QE_INIT_RX 0x00000001
286#define QE_INIT_TX 0x00000002
287#define QE_ENTER_HUNT_MODE 0x00000003
288#define QE_STOP_TX 0x00000004
289#define QE_GRACEFUL_STOP_TX 0x00000005
290#define QE_RESTART_TX 0x00000006
291#define QE_CLOSE_RX_BD 0x00000007
292#define QE_SWITCH_COMMAND 0x00000007
293#define QE_SET_GROUP_ADDRESS 0x00000008
294#define QE_START_IDMA 0x00000009
295#define QE_MCC_STOP_RX 0x00000009
296#define QE_ATM_TRANSMIT 0x0000000a
297#define QE_HPAC_CLEAR_ALL 0x0000000b
298#define QE_GRACEFUL_STOP_RX 0x0000001a
299#define QE_RESTART_RX 0x0000001b
300#define QE_HPAC_SET_PRIORITY 0x0000010b
301#define QE_HPAC_STOP_TX 0x0000020b
302#define QE_HPAC_STOP_RX 0x0000030b
303#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
304#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
305#define QE_HPAC_START_TX 0x0000060b
306#define QE_HPAC_START_RX 0x0000070b
307#define QE_USB_STOP_TX 0x0000000a
308#define QE_USB_RESTART_TX 0x0000000c
309#define QE_QMC_STOP_TX 0x0000000c
310#define QE_QMC_STOP_RX 0x0000000d
311#define QE_SS7_SU_FIL_RESET 0x0000000e
312/* jonathbr added from here down for 83xx */
313#define QE_RESET_BCS 0x0000000a
314#define QE_MCC_INIT_TX_RX_16 0x00000003
315#define QE_MCC_STOP_TX 0x00000004
316#define QE_MCC_INIT_TX_1 0x00000005
317#define QE_MCC_INIT_RX_1 0x00000006
318#define QE_MCC_RESET 0x00000007
319#define QE_SET_TIMER 0x00000008
320#define QE_RANDOM_NUMBER 0x0000000c
321#define QE_ATM_MULTI_THREAD_INIT 0x00000011
322#define QE_ASSIGN_PAGE 0x00000012
323#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
324#define QE_START_FLOW_CONTROL 0x00000014
325#define QE_STOP_FLOW_CONTROL 0x00000015
326#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
327
328#define QE_ASSIGN_RISC 0x00000010
329#define QE_CR_MCN_NORMAL_SHIFT 6
330#define QE_CR_MCN_USB_SHIFT 4
331#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
332#define QE_CR_SNUM_SHIFT 17
333
334/* QE CECR Sub Block - sub block of QE command.
335*/
336#define QE_CR_SUBBLOCK_INVALID 0x00000000
337#define QE_CR_SUBBLOCK_USB 0x03200000
338#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
339#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
340#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
341#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
342#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
343#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
344#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
345#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
346#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
347#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
348#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
349#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
350#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
351#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
352#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
353#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
354#define QE_CR_SUBBLOCK_MCC1 0x03800000
355#define QE_CR_SUBBLOCK_MCC2 0x03a00000
356#define QE_CR_SUBBLOCK_MCC3 0x03000000
357#define QE_CR_SUBBLOCK_IDMA1 0x02800000
358#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
359#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
360#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
361#define QE_CR_SUBBLOCK_HPAC 0x01e00000
362#define QE_CR_SUBBLOCK_SPI1 0x01400000
363#define QE_CR_SUBBLOCK_SPI2 0x01600000
364#define QE_CR_SUBBLOCK_RAND 0x01c00000
365#define QE_CR_SUBBLOCK_TIMER 0x01e00000
366#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
367
368/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
369#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
370#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
371#define QE_CR_PROTOCOL_QMC 0x02
372#define QE_CR_PROTOCOL_UART 0x04
373#define QE_CR_PROTOCOL_ATM_POS 0x0A
374#define QE_CR_PROTOCOL_ETHERNET 0x0C
375#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
376
377/* BRG configuration register */
378#define QE_BRGC_ENABLE 0x00010000
379#define QE_BRGC_DIVISOR_SHIFT 1
380#define QE_BRGC_DIVISOR_MAX 0xFFF
381#define QE_BRGC_DIV16 1
382
383/* QE Timers registers */
384#define QE_GTCFR1_PCAS 0x80
385#define QE_GTCFR1_STP2 0x20
386#define QE_GTCFR1_RST2 0x10
387#define QE_GTCFR1_GM2 0x08
388#define QE_GTCFR1_GM1 0x04
389#define QE_GTCFR1_STP1 0x02
390#define QE_GTCFR1_RST1 0x01
391
392/* SDMA registers */
393#define QE_SDSR_BER1 0x02000000
394#define QE_SDSR_BER2 0x01000000
395
396#define QE_SDMR_GLB_1_MSK 0x80000000
397#define QE_SDMR_ADR_SEL 0x20000000
398#define QE_SDMR_BER1_MSK 0x02000000
399#define QE_SDMR_BER2_MSK 0x01000000
400#define QE_SDMR_EB1_MSK 0x00800000
401#define QE_SDMR_ER1_MSK 0x00080000
402#define QE_SDMR_ER2_MSK 0x00040000
403#define QE_SDMR_CEN_MASK 0x0000E000
404#define QE_SDMR_SBER_1 0x00000200
405#define QE_SDMR_SBER_2 0x00000200
406#define QE_SDMR_EB1_PR_MASK 0x000000C0
407#define QE_SDMR_ER1_PR 0x00000008
408
409#define QE_SDMR_CEN_SHIFT 13
410#define QE_SDMR_EB1_PR_SHIFT 6
411
412#define QE_SDTM_MSNUM_SHIFT 24
413
414#define QE_SDEBCR_BA_MASK 0x01FFFFFF
415
416/* Communication Processor */
417#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
418#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
419#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
420
421/* I-RAM */
422#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
423#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
424
425/* UPC */
426#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
427#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
428#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
429#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
430#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
431
432/* UCC GUEMR register */
433#define UCC_GUEMR_MODE_MASK_RX 0x02
434#define UCC_GUEMR_MODE_FAST_RX 0x02
435#define UCC_GUEMR_MODE_SLOW_RX 0x00
436#define UCC_GUEMR_MODE_MASK_TX 0x01
437#define UCC_GUEMR_MODE_FAST_TX 0x01
438#define UCC_GUEMR_MODE_SLOW_TX 0x00
439#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
440#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
441 must be set 1 */
442
443/* structure representing UCC SLOW parameter RAM */
444struct ucc_slow_pram {
445 __be16 rbase; /* RX BD base address */
446 __be16 tbase; /* TX BD base address */
447 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
448 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
449 __be16 mrblr; /* Rx buffer length */
450 __be32 rstate; /* Rx internal state */
451 __be32 rptr; /* Rx internal data pointer */
452 __be16 rbptr; /* rb BD Pointer */
453 __be16 rcount; /* Rx internal byte count */
454 __be32 rtemp; /* Rx temp */
455 __be32 tstate; /* Tx internal state */
456 __be32 tptr; /* Tx internal data pointer */
457 __be16 tbptr; /* Tx BD pointer */
458 __be16 tcount; /* Tx byte count */
459 __be32 ttemp; /* Tx temp */
460 __be32 rcrc; /* temp receive CRC */
461 __be32 tcrc; /* temp transmit CRC */
462} __attribute__ ((packed));
463
464/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
465#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
466#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
467#define UCC_SLOW_GUMR_H_REVD 0x00002000
468#define UCC_SLOW_GUMR_H_TRX 0x00001000
469#define UCC_SLOW_GUMR_H_TTX 0x00000800
470#define UCC_SLOW_GUMR_H_CDP 0x00000400
471#define UCC_SLOW_GUMR_H_CTSP 0x00000200
472#define UCC_SLOW_GUMR_H_CDS 0x00000100
473#define UCC_SLOW_GUMR_H_CTSS 0x00000080
474#define UCC_SLOW_GUMR_H_TFL 0x00000040
475#define UCC_SLOW_GUMR_H_RFW 0x00000020
476#define UCC_SLOW_GUMR_H_TXSY 0x00000010
477#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
478#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
479#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
480#define UCC_SLOW_GUMR_H_RTSM 0x00000002
481#define UCC_SLOW_GUMR_H_RSYN 0x00000001
482
483#define UCC_SLOW_GUMR_L_TCI 0x10000000
484#define UCC_SLOW_GUMR_L_RINV 0x02000000
485#define UCC_SLOW_GUMR_L_TINV 0x01000000
486#define UCC_SLOW_GUMR_L_TEND 0x00040000
487#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
488#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
489#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
490#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
491#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
492#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
493#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
494#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
495#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
496#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
497#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
498#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
499#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
500#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
501#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
502#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
503#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
504#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
505#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
506#define UCC_SLOW_GUMR_L_ENR 0x00000020
507#define UCC_SLOW_GUMR_L_ENT 0x00000010
508#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
509#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
510#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
511#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
512#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
513
514/* General UCC FAST Mode Register */
515#define UCC_FAST_GUMR_TCI 0x20000000
516#define UCC_FAST_GUMR_TRX 0x10000000
517#define UCC_FAST_GUMR_TTX 0x08000000
518#define UCC_FAST_GUMR_CDP 0x04000000
519#define UCC_FAST_GUMR_CTSP 0x02000000
520#define UCC_FAST_GUMR_CDS 0x01000000
521#define UCC_FAST_GUMR_CTSS 0x00800000
522#define UCC_FAST_GUMR_TXSY 0x00020000
523#define UCC_FAST_GUMR_RSYN 0x00010000
524#define UCC_FAST_GUMR_RTSM 0x00002000
525#define UCC_FAST_GUMR_REVD 0x00000400
526#define UCC_FAST_GUMR_ENR 0x00000020
527#define UCC_FAST_GUMR_ENT 0x00000010
528
529/* UART Slow UCC Event Register (UCCE) */
530#define UCC_UART_UCCE_AB 0x0200
531#define UCC_UART_UCCE_IDLE 0x0100
532#define UCC_UART_UCCE_GRA 0x0080
533#define UCC_UART_UCCE_BRKE 0x0040
534#define UCC_UART_UCCE_BRKS 0x0020
535#define UCC_UART_UCCE_CCR 0x0008
536#define UCC_UART_UCCE_BSY 0x0004
537#define UCC_UART_UCCE_TX 0x0002
538#define UCC_UART_UCCE_RX 0x0001
539
540/* HDLC Slow UCC Event Register (UCCE) */
541#define UCC_HDLC_UCCE_GLR 0x1000
542#define UCC_HDLC_UCCE_GLT 0x0800
543#define UCC_HDLC_UCCE_IDLE 0x0100
544#define UCC_HDLC_UCCE_BRKE 0x0040
545#define UCC_HDLC_UCCE_BRKS 0x0020
546#define UCC_HDLC_UCCE_TXE 0x0010
547#define UCC_HDLC_UCCE_RXF 0x0008
548#define UCC_HDLC_UCCE_BSY 0x0004
549#define UCC_HDLC_UCCE_TXB 0x0002
550#define UCC_HDLC_UCCE_RXB 0x0001
551
552/* BISYNC Slow UCC Event Register (UCCE) */
553#define UCC_BISYNC_UCCE_GRA 0x0080
554#define UCC_BISYNC_UCCE_TXE 0x0010
555#define UCC_BISYNC_UCCE_RCH 0x0008
556#define UCC_BISYNC_UCCE_BSY 0x0004
557#define UCC_BISYNC_UCCE_TXB 0x0002
558#define UCC_BISYNC_UCCE_RXB 0x0001
559
560/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
561#define UCC_GETH_UCCE_MPD 0x80000000
562#define UCC_GETH_UCCE_SCAR 0x40000000
563#define UCC_GETH_UCCE_GRA 0x20000000
564#define UCC_GETH_UCCE_CBPR 0x10000000
565#define UCC_GETH_UCCE_BSY 0x08000000
566#define UCC_GETH_UCCE_RXC 0x04000000
567#define UCC_GETH_UCCE_TXC 0x02000000
568#define UCC_GETH_UCCE_TXE 0x01000000
569#define UCC_GETH_UCCE_TXB7 0x00800000
570#define UCC_GETH_UCCE_TXB6 0x00400000
571#define UCC_GETH_UCCE_TXB5 0x00200000
572#define UCC_GETH_UCCE_TXB4 0x00100000
573#define UCC_GETH_UCCE_TXB3 0x00080000
574#define UCC_GETH_UCCE_TXB2 0x00040000
575#define UCC_GETH_UCCE_TXB1 0x00020000
576#define UCC_GETH_UCCE_TXB0 0x00010000
577#define UCC_GETH_UCCE_RXB7 0x00008000
578#define UCC_GETH_UCCE_RXB6 0x00004000
579#define UCC_GETH_UCCE_RXB5 0x00002000
580#define UCC_GETH_UCCE_RXB4 0x00001000
581#define UCC_GETH_UCCE_RXB3 0x00000800
582#define UCC_GETH_UCCE_RXB2 0x00000400
583#define UCC_GETH_UCCE_RXB1 0x00000200
584#define UCC_GETH_UCCE_RXB0 0x00000100
585#define UCC_GETH_UCCE_RXF7 0x00000080
586#define UCC_GETH_UCCE_RXF6 0x00000040
587#define UCC_GETH_UCCE_RXF5 0x00000020
588#define UCC_GETH_UCCE_RXF4 0x00000010
589#define UCC_GETH_UCCE_RXF3 0x00000008
590#define UCC_GETH_UCCE_RXF2 0x00000004
591#define UCC_GETH_UCCE_RXF1 0x00000002
592#define UCC_GETH_UCCE_RXF0 0x00000001
593
594/* UPSMR, when used as a UART */
595#define UCC_UART_UPSMR_FLC 0x8000
596#define UCC_UART_UPSMR_SL 0x4000
597#define UCC_UART_UPSMR_CL_MASK 0x3000
598#define UCC_UART_UPSMR_CL_8 0x3000
599#define UCC_UART_UPSMR_CL_7 0x2000
600#define UCC_UART_UPSMR_CL_6 0x1000
601#define UCC_UART_UPSMR_CL_5 0x0000
602#define UCC_UART_UPSMR_UM_MASK 0x0c00
603#define UCC_UART_UPSMR_UM_NORMAL 0x0000
604#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
605#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
606#define UCC_UART_UPSMR_FRZ 0x0200
607#define UCC_UART_UPSMR_RZS 0x0100
608#define UCC_UART_UPSMR_SYN 0x0080
609#define UCC_UART_UPSMR_DRT 0x0040
610#define UCC_UART_UPSMR_PEN 0x0010
611#define UCC_UART_UPSMR_RPM_MASK 0x000c
612#define UCC_UART_UPSMR_RPM_ODD 0x0000
613#define UCC_UART_UPSMR_RPM_LOW 0x0004
614#define UCC_UART_UPSMR_RPM_EVEN 0x0008
615#define UCC_UART_UPSMR_RPM_HIGH 0x000C
616#define UCC_UART_UPSMR_TPM_MASK 0x0003
617#define UCC_UART_UPSMR_TPM_ODD 0x0000
618#define UCC_UART_UPSMR_TPM_LOW 0x0001
619#define UCC_UART_UPSMR_TPM_EVEN 0x0002
620#define UCC_UART_UPSMR_TPM_HIGH 0x0003
621
622/* UCC Transmit On Demand Register (UTODR) */
623#define UCC_SLOW_TOD 0x8000
624#define UCC_FAST_TOD 0x8000
625
626/* UCC Bus Mode Register masks */
627/* Not to be confused with the Bundle Mode Register */
628#define UCC_BMR_GBL 0x20
629#define UCC_BMR_BO_BE 0x10
630#define UCC_BMR_CETM 0x04
631#define UCC_BMR_DTB 0x02
632#define UCC_BMR_BDB 0x01
633
634/* Function code masks */
635#define FC_GBL 0x20
636#define FC_DTB_LCL 0x02
637#define UCC_FAST_FUNCTION_CODE_GBL 0x20
638#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
639#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
640
641#endif /* __KERNEL__ */
642#endif /* _ASM_POWERPC_QE_H */
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h
new file mode 100644
index 000000000000..56a7745ca343
--- /dev/null
+++ b/arch/powerpc/include/asm/qe_ic.h
@@ -0,0 +1,128 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE IC external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_IC_H
16#define _ASM_POWERPC_QE_IC_H
17
18#include <linux/irq.h>
19
20#define NUM_OF_QE_IC_GROUPS 6
21
22/* Flags when we init the QE IC */
23#define QE_IC_SPREADMODE_GRP_W 0x00000001
24#define QE_IC_SPREADMODE_GRP_X 0x00000002
25#define QE_IC_SPREADMODE_GRP_Y 0x00000004
26#define QE_IC_SPREADMODE_GRP_Z 0x00000008
27#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
28#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
29
30#define QE_IC_LOW_SIGNAL 0x00000100
31#define QE_IC_HIGH_SIGNAL 0x00000200
32
33#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
34#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
35#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
36#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
37#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
38#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
39#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
40#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
41#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
42#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
43#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
44#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
45#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
46
47/* QE interrupt sources groups */
48enum qe_ic_grp_id {
49 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
50 QE_IC_GRP_X, /* QE interrupt controller group X */
51 QE_IC_GRP_Y, /* QE interrupt controller group Y */
52 QE_IC_GRP_Z, /* QE interrupt controller group Z */
53 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
54 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
55};
56
57void qe_ic_init(struct device_node *node, unsigned int flags,
58 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
59 void (*high_handler)(unsigned int irq, struct irq_desc *desc));
60void qe_ic_set_highest_priority(unsigned int virq, int high);
61int qe_ic_set_priority(unsigned int virq, unsigned int priority);
62int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
63
64struct qe_ic;
65unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
66unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
67
68static inline void qe_ic_cascade_low_ipic(unsigned int irq,
69 struct irq_desc *desc)
70{
71 struct qe_ic *qe_ic = desc->handler_data;
72 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
73
74 if (cascade_irq != NO_IRQ)
75 generic_handle_irq(cascade_irq);
76}
77
78static inline void qe_ic_cascade_high_ipic(unsigned int irq,
79 struct irq_desc *desc)
80{
81 struct qe_ic *qe_ic = desc->handler_data;
82 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
83
84 if (cascade_irq != NO_IRQ)
85 generic_handle_irq(cascade_irq);
86}
87
88static inline void qe_ic_cascade_low_mpic(unsigned int irq,
89 struct irq_desc *desc)
90{
91 struct qe_ic *qe_ic = desc->handler_data;
92 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
93
94 if (cascade_irq != NO_IRQ)
95 generic_handle_irq(cascade_irq);
96
97 desc->chip->eoi(irq);
98}
99
100static inline void qe_ic_cascade_high_mpic(unsigned int irq,
101 struct irq_desc *desc)
102{
103 struct qe_ic *qe_ic = desc->handler_data;
104 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
105
106 if (cascade_irq != NO_IRQ)
107 generic_handle_irq(cascade_irq);
108
109 desc->chip->eoi(irq);
110}
111
112static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
113 struct irq_desc *desc)
114{
115 struct qe_ic *qe_ic = desc->handler_data;
116 unsigned int cascade_irq;
117
118 cascade_irq = qe_ic_get_high_irq(qe_ic);
119 if (cascade_irq == NO_IRQ)
120 cascade_irq = qe_ic_get_low_irq(qe_ic);
121
122 if (cascade_irq != NO_IRQ)
123 generic_handle_irq(cascade_irq);
124
125 desc->chip->eoi(irq);
126}
127
128#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
new file mode 100644
index 000000000000..c6d1ab650778
--- /dev/null
+++ b/arch/powerpc/include/asm/reg.h
@@ -0,0 +1,788 @@
1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
25#ifdef CONFIG_8xx
26#include <asm/reg_8xx.h>
27#endif /* CONFIG_8xx */
28
29#define MSR_SF_LG 63 /* Enable 64 bit mode */
30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31#define MSR_HV_LG 60 /* Hypervisor state */
32#define MSR_VEC_LG 25 /* Enable AltiVec */
33#define MSR_VSX_LG 23 /* Enable VSX */
34#define MSR_POW_LG 18 /* Enable Power Management */
35#define MSR_WE_LG 18 /* Wait State Enable */
36#define MSR_TGPR_LG 17 /* TLB Update registers in use */
37#define MSR_CE_LG 17 /* Critical Interrupt Enable */
38#define MSR_ILE_LG 16 /* Interrupt Little Endian */
39#define MSR_EE_LG 15 /* External Interrupt Enable */
40#define MSR_PR_LG 14 /* Problem State / Privilege Level */
41#define MSR_FP_LG 13 /* Floating Point enable */
42#define MSR_ME_LG 12 /* Machine Check Enable */
43#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
44#define MSR_SE_LG 10 /* Single Step */
45#define MSR_BE_LG 9 /* Branch Trace */
46#define MSR_DE_LG 9 /* Debug Exception Enable */
47#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
48#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
49#define MSR_IR_LG 5 /* Instruction Relocate */
50#define MSR_DR_LG 4 /* Data Relocate */
51#define MSR_PE_LG 3 /* Protection Enable */
52#define MSR_PX_LG 2 /* Protection Exclusive Mode */
53#define MSR_PMM_LG 2 /* Performance monitor */
54#define MSR_RI_LG 1 /* Recoverable Exception */
55#define MSR_LE_LG 0 /* Little Endian */
56
57#ifdef __ASSEMBLY__
58#define __MASK(X) (1<<(X))
59#else
60#define __MASK(X) (1UL<<(X))
61#endif
62
63#ifdef CONFIG_PPC64
64#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
65#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
66#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
67#else
68/* so tests for these bits fail on 32-bit */
69#define MSR_SF 0
70#define MSR_ISF 0
71#define MSR_HV 0
72#endif
73
74#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
75#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
76#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
77#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
78#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
79#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
80#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
81#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
82#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
83#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
84#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
85#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
86#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
87#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
88#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
89#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
90#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
91#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
92#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
93#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
94#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
95#ifndef MSR_PMM
96#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
97#endif
98#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
100
101#ifdef CONFIG_PPC64
102#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
103#define MSR_KERNEL MSR_ | MSR_SF
104
105#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
106#define MSR_USER64 MSR_USER32 | MSR_SF
107
108#else /* 32-bit */
109/* Default MSR for kernel mode. */
110#ifndef MSR_KERNEL /* reg_booke.h also defines this */
111#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
112#endif
113
114#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
115#endif
116
117/* Floating Point Status and Control Register (FPSCR) Fields */
118#define FPSCR_FX 0x80000000 /* FPU exception summary */
119#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
120#define FPSCR_VX 0x20000000 /* Invalid operation summary */
121#define FPSCR_OX 0x10000000 /* Overflow exception summary */
122#define FPSCR_UX 0x08000000 /* Underflow exception summary */
123#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
124#define FPSCR_XX 0x02000000 /* Inexact exception summary */
125#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
126#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
127#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
128#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
129#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
130#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
131#define FPSCR_FR 0x00040000 /* Fraction rounded */
132#define FPSCR_FI 0x00020000 /* Fraction inexact */
133#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
134#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
135#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
136#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
137#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
138#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
139#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
140#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
141#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
142#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
143#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
144#define FPSCR_RN 0x00000003 /* FPU rounding control */
145
146/* Special Purpose Registers (SPRNs)*/
147#define SPRN_CTR 0x009 /* Count Register */
148#define SPRN_DSCR 0x11
149#define SPRN_CTRLF 0x088
150#define SPRN_CTRLT 0x098
151#define CTRL_CT 0xc0000000 /* current thread */
152#define CTRL_CT0 0x80000000 /* thread 0 */
153#define CTRL_CT1 0x40000000 /* thread 1 */
154#define CTRL_TE 0x00c00000 /* thread enable */
155#define CTRL_RUNLATCH 0x1
156#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
157#define DABR_TRANSLATION (1UL << 2)
158#define SPRN_DABR2 0x13D /* e300 */
159#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
160#define DABRX_USER (1UL << 0)
161#define DABRX_KERNEL (1UL << 1)
162#define SPRN_DAR 0x013 /* Data Address Register */
163#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
164#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
165#define DSISR_NOHPTE 0x40000000 /* no translation found */
166#define DSISR_PROTFAULT 0x08000000 /* protection fault */
167#define DSISR_ISSTORE 0x02000000 /* access was a store */
168#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
169#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
170#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
171#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
172#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
173#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
174#define SPRN_SPURR 0x134 /* Scaled PURR */
175#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
176#define SPRN_LPCR 0x13E /* LPAR Control Register */
177#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
178#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
179#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
180#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
181#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
182#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
183#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
184#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
185#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
186#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
187#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
188#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
189#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
190#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
191#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
192#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
193
194#define SPRN_DEC 0x016 /* Decrement Register */
195#define SPRN_DER 0x095 /* Debug Enable Regsiter */
196#define DER_RSTE 0x40000000 /* Reset Interrupt */
197#define DER_CHSTPE 0x20000000 /* Check Stop */
198#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
199#define DER_EXTIE 0x02000000 /* External Interrupt */
200#define DER_ALIE 0x01000000 /* Alignment Interrupt */
201#define DER_PRIE 0x00800000 /* Program Interrupt */
202#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
203#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
204#define DER_SYSIE 0x00040000 /* System Call Interrupt */
205#define DER_TRE 0x00020000 /* Trace Interrupt */
206#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
207#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
208#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
209#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
210#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
211#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
212#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
213#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
214#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
215#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
216#define SPRN_EAR 0x11A /* External Address Register */
217#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
218#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
219#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
220#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
221#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
222#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
223#define HID0_SBCLK (1<<27)
224#define HID0_EICE (1<<26)
225#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
226#define HID0_ECLK (1<<25)
227#define HID0_PAR (1<<24)
228#define HID0_STEN (1<<24) /* Software table search enable - 745x */
229#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
230#define HID0_DOZE (1<<23)
231#define HID0_NAP (1<<22)
232#define HID0_SLEEP (1<<21)
233#define HID0_DPM (1<<20)
234#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
235#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
236#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
237#define HID0_ICE (1<<15) /* Instruction Cache Enable */
238#define HID0_DCE (1<<14) /* Data Cache Enable */
239#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
240#define HID0_DLOCK (1<<12) /* Data Cache Lock */
241#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
242#define HID0_DCI (1<<10) /* Data Cache Invalidate */
243#define HID0_SPD (1<<9) /* Speculative disable */
244#define HID0_DAPUEN (1<<8) /* Debug APU enable */
245#define HID0_SGE (1<<7) /* Store Gathering Enable */
246#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
247#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
248#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
249#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
250#define HID0_ABE (1<<3) /* Address Broadcast Enable */
251#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
252#define HID0_BHTE (1<<2) /* Branch History Table Enable */
253#define HID0_BTCD (1<<1) /* Branch target cache disable */
254#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
255#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
256
257#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
258#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
259#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
260#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
261#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
262#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
263#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
264#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
265#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
266#define HID1_PS (1<<16) /* 750FX PLL selection */
267#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
268#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
269#define SPRN_IABR2 0x3FA /* 83xx */
270#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
271#define SPRN_HID4 0x3F4 /* 970 HID4 */
272#define SPRN_HID5 0x3F6 /* 970 HID5 */
273#define SPRN_HID6 0x3F9 /* BE HID 6 */
274#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
275#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
276#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
277#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
278#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
279#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
280#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
281#define SPRN_TSC 0x3FD /* Thread switch control on others */
282#define SPRN_TST 0x3FC /* Thread switch timeout on others */
283#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
284#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
285#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
286#endif
287#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
288#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
289#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
290#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
291#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
292#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
293#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
294#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
295#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
296#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
297#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
298#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
299#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
300#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
301#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
302#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
303#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
304#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
305#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
306#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
307#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
308#define ICTRL_EICP 0x00000100 /* enable icache par. check */
309#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
310#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
311#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
312#define SPRN_L2CR2 0x3f8
313#define L2CR_L2E 0x80000000 /* L2 enable */
314#define L2CR_L2PE 0x40000000 /* L2 parity enable */
315#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
316#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
317#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
318#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
319#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
320#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
321#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
322#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
323#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
324#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
325#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
326#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
327#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
328#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
329#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
330#define L2CR_L2DO 0x00400000 /* L2 data only */
331#define L2CR_L2I 0x00200000 /* L2 global invalidate */
332#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
333#define L2CR_L2WT 0x00080000 /* L2 write-through */
334#define L2CR_L2TS 0x00040000 /* L2 test support */
335#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
336#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
337#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
338#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
339#define L2CR_L2DF 0x00004000 /* L2 differential clock */
340#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
341#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
342#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
343#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
344#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
345#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
346#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
347#define L3CR_L3E 0x80000000 /* L3 enable */
348#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
349#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
350#define L3CR_L3SIZ 0x10000000 /* L3 size */
351#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
352#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
353#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
354#define L3CR_L3IO 0x00400000 /* L3 instruction only */
355#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
356#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
357#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
358#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
359#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
360#define L3CR_L3I 0x00000400 /* L3 global invalidate */
361#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
362#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
363#define L3CR_L3DO 0x00000040 /* L3 data only mode */
364#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
365#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
366
367#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
368#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
369#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
370#define SPRN_LDSTDB 0x3f4 /* */
371#define SPRN_LR 0x008 /* Link Register */
372#ifndef SPRN_PIR
373#define SPRN_PIR 0x3FF /* Processor Identification Register */
374#endif
375#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
376#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
377#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
378#define SPRN_PVR 0x11F /* Processor Version Register */
379#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
380#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
381#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
382#define SPRN_ASR 0x118 /* Address Space Register */
383#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
384#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
385#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
386#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
387#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
388#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
389#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
390#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
391#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
392#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
393#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
394#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
395#define SRR1_WAKERESET 0x00380000 /* System reset */
396#define SRR1_WAKESYSERR 0x00300000 /* System error */
397#define SRR1_WAKEEE 0x00200000 /* External interrupt */
398#define SRR1_WAKEMT 0x00280000 /* mtctrl */
399#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
400#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
401#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
402#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
403
404#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
405#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
406#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
407#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
408#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
409
410#ifndef SPRN_SVR
411#define SPRN_SVR 0x11E /* System Version Register */
412#endif
413#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
414/* these bits were defined in inverted endian sense originally, ugh, confusing */
415#define THRM1_TIN (1 << 31)
416#define THRM1_TIV (1 << 30)
417#define THRM1_THRES(x) ((x&0x7f)<<23)
418#define THRM3_SITV(x) ((x&0x3fff)<<1)
419#define THRM1_TID (1<<2)
420#define THRM1_TIE (1<<1)
421#define THRM1_V (1<<0)
422#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
423#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
424#define THRM3_E (1<<0)
425#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
426#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
427#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
428#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
429#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
430#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
431#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
432#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
433#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
434#define SPRN_XER 0x001 /* Fixed Point Exception Register */
435
436#define SPRN_SCOMC 0x114 /* SCOM Access Control */
437#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
438
439/* Performance monitor SPRs */
440#ifdef CONFIG_PPC64
441#define SPRN_MMCR0 795
442#define MMCR0_FC 0x80000000UL /* freeze counters */
443#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
444#define MMCR0_KERNEL_DISABLE MMCR0_FCS
445#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
446#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
447#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
448#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
449#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
450#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
451#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
452#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
453#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
454#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
455#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
456#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
457#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
458#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
459#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
460#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
461#define SPRN_MMCR1 798
462#define SPRN_MMCRA 0x312
463#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
464#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
465#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
466#define MMCRA_SLOT_SHIFT 24
467#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
468#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
469#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
470#define POWER6_MMCRA_THRM 0x00000020UL
471#define POWER6_MMCRA_OTHER 0x0000000EUL
472#define SPRN_PMC1 787
473#define SPRN_PMC2 788
474#define SPRN_PMC3 789
475#define SPRN_PMC4 790
476#define SPRN_PMC5 791
477#define SPRN_PMC6 792
478#define SPRN_PMC7 793
479#define SPRN_PMC8 794
480#define SPRN_SIAR 780
481#define SPRN_SDAR 781
482
483#define SPRN_PA6T_MMCR0 795
484#define PA6T_MMCR0_EN0 0x0000000000000001UL
485#define PA6T_MMCR0_EN1 0x0000000000000002UL
486#define PA6T_MMCR0_EN2 0x0000000000000004UL
487#define PA6T_MMCR0_EN3 0x0000000000000008UL
488#define PA6T_MMCR0_EN4 0x0000000000000010UL
489#define PA6T_MMCR0_EN5 0x0000000000000020UL
490#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
491#define PA6T_MMCR0_PREN 0x0000000000000080UL
492#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
493#define PA6T_MMCR0_FCM0 0x0000000000000200UL
494#define PA6T_MMCR0_FCM1 0x0000000000000400UL
495#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
496#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
497#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
498#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
499#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
500#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
501#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
502#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
503#define PA6T_MMCR0_UOP 0x0000000000080000UL
504#define PA6T_MMCR0_TRG 0x0000000000100000UL
505#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
506#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
507#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
508#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
509#define PA6T_MMCR0_PROEN 0x0000000008000000UL
510#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
511#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
512#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
513#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
514#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
515#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
516#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
517#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
518#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
519#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
520#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
521#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
522#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
523
524#define SPRN_PA6T_MMCR1 798
525#define PA6T_MMCR1_ES2 0x00000000000000ffUL
526#define PA6T_MMCR1_ES3 0x000000000000ff00UL
527#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
528#define PA6T_MMCR1_ES5 0x00000000ff000000UL
529
530#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
531#define SPRN_PA6T_UPMC1 772 /* ... */
532#define SPRN_PA6T_UPMC2 773
533#define SPRN_PA6T_UPMC3 774
534#define SPRN_PA6T_UPMC4 775
535#define SPRN_PA6T_UPMC5 776
536#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
537#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
538#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
539#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
540#define SPRN_PA6T_PMC0 787
541#define SPRN_PA6T_PMC1 788
542#define SPRN_PA6T_PMC2 789
543#define SPRN_PA6T_PMC3 790
544#define SPRN_PA6T_PMC4 791
545#define SPRN_PA6T_PMC5 792
546#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
547#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
548#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
549#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
550
551#define SPRN_PA6T_IER 981 /* Icache Error Register */
552#define SPRN_PA6T_DER 982 /* Dcache Error Register */
553#define SPRN_PA6T_BER 862 /* BIU Error Address Register */
554#define SPRN_PA6T_MER 849 /* MMU Error Register */
555
556#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
557#define SPRN_PA6T_IMA1 881 /* ... */
558#define SPRN_PA6T_IMA2 882
559#define SPRN_PA6T_IMA3 883
560#define SPRN_PA6T_IMA4 884
561#define SPRN_PA6T_IMA5 885
562#define SPRN_PA6T_IMA6 886
563#define SPRN_PA6T_IMA7 887
564#define SPRN_PA6T_IMA8 888
565#define SPRN_PA6T_IMA9 889
566#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
567#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
568#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
569#define SPRN_BKMK 1020 /* Cell Bookmark Register */
570#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
571
572
573#else /* 32-bit */
574#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
575#define MMCR0_FC 0x80000000UL /* freeze counters */
576#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
577#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
578#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
579#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
580#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
581#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
582#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
583#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
584#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
585#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
586#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
587#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
588
589#define SPRN_MMCR1 956
590#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
591#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
592#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
593#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
594#define SPRN_MMCR2 944
595#define SPRN_PMC1 953 /* Performance Counter Register 1 */
596#define SPRN_PMC2 954 /* Performance Counter Register 2 */
597#define SPRN_PMC3 957 /* Performance Counter Register 3 */
598#define SPRN_PMC4 958 /* Performance Counter Register 4 */
599#define SPRN_PMC5 945 /* Performance Counter Register 5 */
600#define SPRN_PMC6 946 /* Performance Counter Register 6 */
601
602#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
603
604/* Bit definitions for MMCR0 and PMC1 / PMC2. */
605#define MMCR0_PMC1_CYCLES (1 << 7)
606#define MMCR0_PMC1_ICACHEMISS (5 << 7)
607#define MMCR0_PMC1_DTLB (6 << 7)
608#define MMCR0_PMC2_DCACHEMISS 0x6
609#define MMCR0_PMC2_CYCLES 0x1
610#define MMCR0_PMC2_ITLB 0x7
611#define MMCR0_PMC2_LOADMISSTIME 0x5
612#endif
613
614/*
615 * An mtfsf instruction with the L bit set. On CPUs that support this a
616 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
617 *
618 * Until binutils gets the new form of mtfsf, hardwire the instruction.
619 */
620#ifdef CONFIG_PPC64
621#define MTFSF_L(REG) \
622 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
623#else
624#define MTFSF_L(REG) mtfsf 0xff, (REG)
625#endif
626
627/* Processor Version Register (PVR) field extraction */
628
629#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
630#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
631
632#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
633
634/*
635 * IBM has further subdivided the standard PowerPC 16-bit version and
636 * revision subfields of the PVR for the PowerPC 403s into the following:
637 */
638
639#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
640#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
641#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
642#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
643#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
644#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
645
646/* Processor Version Numbers */
647
648#define PVR_403GA 0x00200000
649#define PVR_403GB 0x00200100
650#define PVR_403GC 0x00200200
651#define PVR_403GCX 0x00201400
652#define PVR_405GP 0x40110000
653#define PVR_STB03XXX 0x40310000
654#define PVR_NP405H 0x41410000
655#define PVR_NP405L 0x41610000
656#define PVR_601 0x00010000
657#define PVR_602 0x00050000
658#define PVR_603 0x00030000
659#define PVR_603e 0x00060000
660#define PVR_603ev 0x00070000
661#define PVR_603r 0x00071000
662#define PVR_604 0x00040000
663#define PVR_604e 0x00090000
664#define PVR_604r 0x000A0000
665#define PVR_620 0x00140000
666#define PVR_740 0x00080000
667#define PVR_750 PVR_740
668#define PVR_740P 0x10080000
669#define PVR_750P PVR_740P
670#define PVR_7400 0x000C0000
671#define PVR_7410 0x800C0000
672#define PVR_7450 0x80000000
673#define PVR_8540 0x80200000
674#define PVR_8560 0x80200000
675/*
676 * For the 8xx processors, all of them report the same PVR family for
677 * the PowerPC core. The various versions of these processors must be
678 * differentiated by the version number in the Communication Processor
679 * Module (CPM).
680 */
681#define PVR_821 0x00500000
682#define PVR_823 PVR_821
683#define PVR_850 PVR_821
684#define PVR_860 PVR_821
685#define PVR_8240 0x00810100
686#define PVR_8245 0x80811014
687#define PVR_8260 PVR_8240
688
689/* 64-bit processors */
690/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
691#define PV_NORTHSTAR 0x0033
692#define PV_PULSAR 0x0034
693#define PV_POWER4 0x0035
694#define PV_ICESTAR 0x0036
695#define PV_SSTAR 0x0037
696#define PV_POWER4p 0x0038
697#define PV_970 0x0039
698#define PV_POWER5 0x003A
699#define PV_POWER5p 0x003B
700#define PV_970FX 0x003C
701#define PV_630 0x0040
702#define PV_630p 0x0041
703#define PV_970MP 0x0044
704#define PV_970GX 0x0045
705#define PV_BE 0x0070
706#define PV_PA6T 0x0090
707
708/* Macros for setting and retrieving special purpose registers */
709#ifndef __ASSEMBLY__
710#define mfmsr() ({unsigned long rval; \
711 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
712#ifdef CONFIG_PPC64
713#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
714 : : "r" (v))
715#define mtmsrd(v) __mtmsrd((v), 0)
716#define mtmsr(v) mtmsrd(v)
717#else
718#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
719#endif
720
721#define mfspr(rn) ({unsigned long rval; \
722 asm volatile("mfspr %0," __stringify(rn) \
723 : "=r" (rval)); rval;})
724#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
725
726#ifdef __powerpc64__
727#ifdef CONFIG_PPC_CELL
728#define mftb() ({unsigned long rval; \
729 asm volatile( \
730 "90: mftb %0;\n" \
731 "97: cmpwi %0,0;\n" \
732 " beq- 90b;\n" \
733 "99:\n" \
734 ".section __ftr_fixup,\"a\"\n" \
735 ".align 3\n" \
736 "98:\n" \
737 " .llong %1\n" \
738 " .llong %1\n" \
739 " .llong 97b-98b\n" \
740 " .llong 99b-98b\n" \
741 " .llong 0\n" \
742 " .llong 0\n" \
743 ".previous" \
744 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
745#else
746#define mftb() ({unsigned long rval; \
747 asm volatile("mftb %0" : "=r" (rval)); rval;})
748#endif /* !CONFIG_PPC_CELL */
749
750#else /* __powerpc64__ */
751
752#define mftbl() ({unsigned long rval; \
753 asm volatile("mftbl %0" : "=r" (rval)); rval;})
754#define mftbu() ({unsigned long rval; \
755 asm volatile("mftbu %0" : "=r" (rval)); rval;})
756#endif /* !__powerpc64__ */
757
758#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
759#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
760
761#ifdef CONFIG_PPC32
762#define mfsrin(v) ({unsigned int rval; \
763 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
764 rval;})
765#endif
766
767#define proc_trap() asm volatile("trap")
768
769#ifdef CONFIG_PPC64
770
771extern void ppc64_runlatch_on(void);
772extern void ppc64_runlatch_off(void);
773
774extern unsigned long scom970_read(unsigned int address);
775extern void scom970_write(unsigned int address, unsigned long value);
776
777#else
778#define ppc64_runlatch_on()
779#define ppc64_runlatch_off()
780
781#endif /* CONFIG_PPC64 */
782
783#define __get_SP() ({unsigned long sp; \
784 asm volatile("mr %0,1": "=r" (sp)); sp;})
785
786#endif /* __ASSEMBLY__ */
787#endif /* __KERNEL__ */
788#endif /* _ASM_POWERPC_REG_H */
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h
new file mode 100644
index 000000000000..e8ea346b21d3
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_8xx.h
@@ -0,0 +1,42 @@
1/*
2 * Contains register definitions common to PowerPC 8xx CPUs. Notice
3 */
4#ifndef _ASM_POWERPC_REG_8xx_H
5#define _ASM_POWERPC_REG_8xx_H
6
7/* Cache control on the MPC8xx is provided through some additional
8 * special purpose registers.
9 */
10#define SPRN_IC_CST 560 /* Instruction cache control/status */
11#define SPRN_IC_ADR 561 /* Address needed for some commands */
12#define SPRN_IC_DAT 562 /* Read-only data register */
13#define SPRN_DC_CST 568 /* Data cache control/status */
14#define SPRN_DC_ADR 569 /* Address needed for some commands */
15#define SPRN_DC_DAT 570 /* Read-only data register */
16
17/* Commands. Only the first few are available to the instruction cache.
18*/
19#define IDC_ENABLE 0x02000000 /* Cache enable */
20#define IDC_DISABLE 0x04000000 /* Cache disable */
21#define IDC_LDLCK 0x06000000 /* Load and lock */
22#define IDC_UNLINE 0x08000000 /* Unlock line */
23#define IDC_UNALL 0x0a000000 /* Unlock all */
24#define IDC_INVALL 0x0c000000 /* Invalidate all */
25
26#define DC_FLINE 0x0e000000 /* Flush data cache line */
27#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
28#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
29#define DC_SLES 0x05000000 /* Set little endian swap mode */
30#define DC_CLES 0x07000000 /* Clear little endian swap mode */
31
32/* Status.
33*/
34#define IDC_ENABLED 0x80000000 /* Cache is enabled */
35#define IDC_CERR1 0x00200000 /* Cache error 1 */
36#define IDC_CERR2 0x00100000 /* Cache error 2 */
37#define IDC_CERR3 0x00080000 /* Cache error 3 */
38
39#define DC_DFWT 0x40000000 /* Data cache is forced write through */
40#define DC_LES 0x20000000 /* Caches are little endian mode */
41
42#endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
new file mode 100644
index 000000000000..be980f4ee495
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -0,0 +1,501 @@
1/*
2 * Contains register definitions common to the Book E PowerPC
3 * specification. Notice that while the IBM-40x series of CPUs
4 * are not true Book E PowerPCs, they borrowed a number of features
5 * before Book E was finalized, and are included here as well. Unfortunatly,
6 * they sometimes used different locations than true Book E CPUs did.
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_POWERPC_REG_BOOKE_H__
10#define __ASM_POWERPC_REG_BOOKE_H__
11
12/* Machine State Register (MSR) Fields */
13#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
14#define MSR_SPE (1<<25) /* Enable SPE */
15#define MSR_DWE (1<<10) /* Debug Wait Enable */
16#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
17#define MSR_IS MSR_IR /* Instruction Space */
18#define MSR_DS MSR_DR /* Data Space */
19#define MSR_PMM (1<<2) /* Performance monitor mark bit */
20
21/* Default MSR for kernel mode. */
22#if defined (CONFIG_40x)
23#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
24#elif defined(CONFIG_BOOKE)
25#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
26#endif
27
28/* Special Purpose Registers (SPRNs)*/
29#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
30#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
31#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
32#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
33#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
34#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
35#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
36#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
37#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
38#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
39#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
40#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
41#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
42#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
43#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
44#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
45#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
46#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
47#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
48#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
49#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
50#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
51#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
52#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
53#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
54#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
55#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
56#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
57#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
58#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
59#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
60#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
61#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
62#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
63#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
64#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
65#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
66#define SPRN_ATB 0x20E /* Alternate Time Base */
67#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
68#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
69#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
70#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
71#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
72#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
73#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
74#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
75#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
76#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
77#define SPRN_MCSR 0x23C /* Machine Check Status Register */
78#define SPRN_MCAR 0x23D /* Machine Check Address Register */
79#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
80#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
81#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
82#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
83#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
84#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
85#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
86#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
87#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
88#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
89#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
90#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
91#define SPRN_PID1 0x279 /* Process ID Register 1 */
92#define SPRN_PID2 0x27A /* Process ID Register 2 */
93#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
94#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
95#define SPRN_EPR 0x2BE /* External Proxy Register */
96#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
97#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
98#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
99#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
100#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
101#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
102#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
103#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
104#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
105#define SPRN_SLER 0x3BB /* Little-endian real mode */
106#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
107#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
108#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
109#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
112#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
113#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
114#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
115#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
116#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
117#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
118#define SPRN_SVR 0x3FF /* System Version Register */
119
120/*
121 * SPRs which have conflicting definitions on true Book E versus classic,
122 * or IBM 40x.
123 */
124#ifdef CONFIG_BOOKE
125#define SPRN_PID 0x030 /* Process ID */
126#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
127#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
128#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
129#define SPRN_DEAR 0x03D /* Data Error Address Register */
130#define SPRN_ESR 0x03E /* Exception Syndrome Register */
131#define SPRN_PIR 0x11E /* Processor Identification Register */
132#define SPRN_DBSR 0x130 /* Debug Status Register */
133#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
134#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
135#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
136#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
137#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
138#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
139#define SPRN_TSR 0x150 /* Timer Status Register */
140#define SPRN_TCR 0x154 /* Timer Control Register */
141#endif /* Book E */
142#ifdef CONFIG_40x
143#define SPRN_PID 0x3B1 /* Process ID */
144#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
145#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
146#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
147#define SPRN_TSR 0x3D8 /* Timer Status Register */
148#define SPRN_TCR 0x3DA /* Timer Control Register */
149#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
150#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
151#define SPRN_DBSR 0x3F0 /* Debug Status Register */
152#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
153#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
154#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
155#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
156#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
157#endif
158
159/* Bit definitions for CCR1. */
160#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
161#define CCR1_TCS 0x00000080 /* Timer Clock Select */
162
163/* Bit definitions for the MCSR. */
164#define MCSR_MCS 0x80000000 /* Machine Check Summary */
165#define MCSR_IB 0x40000000 /* Instruction PLB Error */
166#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
167#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
168#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
169#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
170#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
171#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
172#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
173
174#ifdef CONFIG_E500
175#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
176#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
177#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
178#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
179#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
180#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
181#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
182#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
183#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
184#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
185#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
186#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
187
188/* e500 parts may set unused bits in MCSR; mask these off */
189#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
190 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
191 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
192 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
193#endif
194#ifdef CONFIG_E200
195#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
196#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
197#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
198#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
199 fetch for an exception handler */
200#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
201#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
202#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
203 store or cache line push */
204
205/* e200 parts may set unused bits in MCSR; mask these off */
206#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
207 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
208 MCSR_BUS_WRERR)
209#endif
210
211/* Bit definitions for the DBSR. */
212/*
213 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
214 */
215#ifdef CONFIG_BOOKE
216#define DBSR_IC 0x08000000 /* Instruction Completion */
217#define DBSR_BT 0x04000000 /* Branch Taken */
218#define DBSR_IRPT 0x02000000 /* Exception Debug Event */
219#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
220#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
221#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
222#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
223#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
224#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
225#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
226#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
227#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
228#define DBSR_RET 0x00008000 /* Return Debug Event */
229#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
230#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
231#endif
232#ifdef CONFIG_40x
233#define DBSR_IC 0x80000000 /* Instruction Completion */
234#define DBSR_BT 0x40000000 /* Branch taken */
235#define DBSR_IRPT 0x20000000 /* Exception Debug Event */
236#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
237#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */
238#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */
239#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */
240#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */
241#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */
242#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */
243#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */
244#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */
245#endif
246
247/* Bit definitions related to the ESR. */
248#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
249#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
250#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
251#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
252#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
253#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
254#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
255#define ESR_PTR 0x02000000 /* Program Exception - Trap */
256#define ESR_FP 0x01000000 /* Floating Point Operation */
257#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
258#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
259#define ESR_ST 0x00800000 /* Store Operation */
260#define ESR_DLK 0x00200000 /* Data Cache Locking */
261#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
262#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
263#define ESR_BO 0x00020000 /* Byte Ordering */
264
265/* Bit definitions related to the DBCR0. */
266#if defined(CONFIG_40x)
267#define DBCR0_EDM 0x80000000 /* External Debug Mode */
268#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
269#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
270#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
271#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
272#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
273#define DBCR0_RST_NONE 0x00000000 /* No Reset */
274#define DBCR0_IC 0x08000000 /* Instruction Completion */
275#define DBCR0_ICMP DBCR0_IC
276#define DBCR0_BT 0x04000000 /* Branch Taken */
277#define DBCR0_BRT DBCR0_BT
278#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
279#define DBCR0_IRPT DBCR0_EDE
280#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
281#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
282#define DBCR0_IAC1 DBCR0_IA1
283#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
284#define DBCR0_IAC2 DBCR0_IA2
285#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
286#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
287#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
288#define DBCR0_IAC3 DBCR0_IA3
289#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
290#define DBCR0_IAC4 DBCR0_IA4
291#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
292#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
293#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
294#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
295#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
296#elif defined(CONFIG_BOOKE)
297#define DBCR0_EDM 0x80000000 /* External Debug Mode */
298#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
299#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
300/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
301#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
302#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
303#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
304#define DBCR0_RST_NONE 0x00000000 /* No Reset */
305#define DBCR0_ICMP 0x08000000 /* Instruction Completion */
306#define DBCR0_IC DBCR0_ICMP
307#define DBCR0_BRT 0x04000000 /* Branch Taken */
308#define DBCR0_BT DBCR0_BRT
309#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */
310#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
311#define DBCR0_TIE DBCR0_TDE
312#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
313#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
314#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
315#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
316#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */
317#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */
318#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */
319#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */
320#define DBCR0_RET 0x00008000 /* Return Debug Event */
321#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
322#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
323#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
324
325/* Bit definitions related to the DBCR1. */
326#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
327#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
328#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
329#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
330#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
331#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
332
333/* Bit definitions related to the DBCR2. */
334#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
335#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
336#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
337#endif
338
339/* Bit definitions related to the TCR. */
340#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
341#define TCR_WP_MASK TCR_WP(3)
342#define WP_2_17 0 /* 2^17 clocks */
343#define WP_2_21 1 /* 2^21 clocks */
344#define WP_2_25 2 /* 2^25 clocks */
345#define WP_2_29 3 /* 2^29 clocks */
346#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
347#define TCR_WRC_MASK TCR_WRC(3)
348#define WRC_NONE 0 /* No reset will occur */
349#define WRC_CORE 1 /* Core reset will occur */
350#define WRC_CHIP 2 /* Chip reset will occur */
351#define WRC_SYSTEM 3 /* System reset will occur */
352#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
353#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
354#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
355#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
356#define TCR_FP_MASK TCR_FP(3)
357#define FP_2_9 0 /* 2^9 clocks */
358#define FP_2_13 1 /* 2^13 clocks */
359#define FP_2_17 2 /* 2^17 clocks */
360#define FP_2_21 3 /* 2^21 clocks */
361#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
362#define TCR_ARE 0x00400000 /* Auto Reload Enable */
363
364/* Bit definitions for the TSR. */
365#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
366#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
367#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
368#define WRS_NONE 0 /* No WDT reset occurred */
369#define WRS_CORE 1 /* WDT forced core reset */
370#define WRS_CHIP 2 /* WDT forced chip reset */
371#define WRS_SYSTEM 3 /* WDT forced system reset */
372#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
373#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
374#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
375
376/* Bit definitions for the DCCR. */
377#define DCCR_NOCACHE 0 /* Noncacheable */
378#define DCCR_CACHE 1 /* Cacheable */
379
380/* Bit definitions for DCWR. */
381#define DCWR_COPY 0 /* Copy-back */
382#define DCWR_WRITE 1 /* Write-through */
383
384/* Bit definitions for ICCR. */
385#define ICCR_NOCACHE 0 /* Noncacheable */
386#define ICCR_CACHE 1 /* Cacheable */
387
388/* Bit definitions for L1CSR0. */
389#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
390#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
391#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
392#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
393
394/* Bit definitions for L1CSR1. */
395#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
396#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
397#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
398
399/* Bit definitions for L2CSR0. */
400#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
401#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
402#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
403#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
404#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
405#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
406#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
407#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
408#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
409#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
410#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
411#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
412
413/* Bit definitions for SGR. */
414#define SGR_NORMAL 0 /* Speculative fetching allowed. */
415#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
416
417/* Bit definitions for SPEFSCR. */
418#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
419#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
420#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
421#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
422#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
423#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
424#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
425#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
426#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
427#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
428#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
429#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
430#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
431#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
432#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
433#define SPEFSCR_OV 0x00004000 /* Integer overflow */
434#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
435#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
436#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
437#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
438#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
439#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
440#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
441#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
442#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
443#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
444#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
445#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
446
447/*
448 * The IBM-403 is an even more odd special case, as it is much
449 * older than the IBM-405 series. We put these down here incase someone
450 * wishes to support these machines again.
451 */
452#ifdef CONFIG_403GCX
453/* Special Purpose Registers (SPRNs)*/
454#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
455#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
456#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
457#define SPRN_TBHI 0x3DC /* Time Base High */
458#define SPRN_TBLO 0x3DD /* Time Base Low */
459#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
460#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
461#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
462#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
463#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
464
465
466/* Bit definitions for the DBCR. */
467#define DBCR_EDM DBCR0_EDM
468#define DBCR_IDM DBCR0_IDM
469#define DBCR_RST(x) (((x) & 0x3) << 28)
470#define DBCR_RST_NONE 0
471#define DBCR_RST_CORE 1
472#define DBCR_RST_CHIP 2
473#define DBCR_RST_SYSTEM 3
474#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
475#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
476#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
477#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
478#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
479#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
480#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
481#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
482#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
483#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
484#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
485#define DAC_BYTE 0
486#define DAC_HALF 1
487#define DAC_WORD 2
488#define DAC_QUAD 3
489#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
490#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
491#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
492#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
493#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
494#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
495#define DBCR_SIA 0x00000008 /* Second IAC Enable */
496#define DBCR_SDA 0x00000004 /* Second DAC Enable */
497#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
498#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
499#endif /* 403GCX */
500#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
501#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h b/arch/powerpc/include/asm/reg_fsl_emb.h
new file mode 100644
index 000000000000..1e180a594589
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -0,0 +1,72 @@
1/*
2 * Contains register definitions for the Freescale Embedded Performance
3 * Monitor.
4 */
5#ifdef __KERNEL__
6#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
7#define __ASM_POWERPC_REG_FSL_EMB_H__
8
9#ifndef __ASSEMBLY__
10/* Performance Monitor Registers */
11#define mfpmr(rn) ({unsigned int rval; \
12 asm volatile("mfpmr %0," __stringify(rn) \
13 : "=r" (rval)); rval;})
14#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
15#endif /* __ASSEMBLY__ */
16
17/* Freescale Book E Performance Monitor APU Registers */
18#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
19#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
20#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
21#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
22#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
23#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
24#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
25#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
26
27#define PMLCA_FC 0x80000000 /* Freeze Counter */
28#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
29#define PMLCA_FCU 0x20000000 /* Freeze in User */
30#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
31#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
32#define PMLCA_CE 0x04000000 /* Condition Enable */
33
34#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
35#define PMLCA_EVENT_SHIFT 16
36
37#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
38#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
39#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
40#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
41
42#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
43#define PMLCB_THRESHMUL_SHIFT 8
44
45#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
46#define PMLCB_THRESHOLD_SHIFT 0
47
48#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
49
50#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
51#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
52#define PMGC0_FCECE 0x20000000 /* Freeze countes on
53 Enabled Condition or
54 Event */
55
56#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
57#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
58#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
59#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
60#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
61#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
62#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
63#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
64#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
65#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
66#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
67#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
68#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
69
70
71#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
72#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/resource.h b/arch/powerpc/include/asm/resource.h
new file mode 100644
index 000000000000..04bc4db8921b
--- /dev/null
+++ b/arch/powerpc/include/asm/resource.h
@@ -0,0 +1 @@
#include <asm-generic/resource.h>
diff --git a/arch/powerpc/include/asm/rheap.h b/arch/powerpc/include/asm/rheap.h
new file mode 100644
index 000000000000..172381769cfc
--- /dev/null
+++ b/arch/powerpc/include/asm/rheap.h
@@ -0,0 +1,89 @@
1/*
2 * include/asm-ppc/rheap.h
3 *
4 * Header file for the implementation of a remote heap.
5 *
6 * Author: Pantelis Antoniou <panto@intracom.gr>
7 *
8 * 2004 (c) INTRACOM S.A. Greece. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __ASM_PPC_RHEAP_H__
15#define __ASM_PPC_RHEAP_H__
16
17#include <linux/list.h>
18
19typedef struct _rh_block {
20 struct list_head list;
21 unsigned long start;
22 int size;
23 const char *owner;
24} rh_block_t;
25
26typedef struct _rh_info {
27 unsigned int alignment;
28 int max_blocks;
29 int empty_slots;
30 rh_block_t *block;
31 struct list_head empty_list;
32 struct list_head free_list;
33 struct list_head taken_list;
34 unsigned int flags;
35} rh_info_t;
36
37#define RHIF_STATIC_INFO 0x1
38#define RHIF_STATIC_BLOCK 0x2
39
40typedef struct _rh_stats {
41 unsigned long start;
42 int size;
43 const char *owner;
44} rh_stats_t;
45
46#define RHGS_FREE 0
47#define RHGS_TAKEN 1
48
49/* Create a remote heap dynamically */
50extern rh_info_t *rh_create(unsigned int alignment);
51
52/* Destroy a remote heap, created by rh_create() */
53extern void rh_destroy(rh_info_t * info);
54
55/* Initialize in place a remote info block */
56extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
57 rh_block_t * block);
58
59/* Attach a free region to manage */
60extern int rh_attach_region(rh_info_t * info, unsigned long start, int size);
61
62/* Detach a free region */
63extern unsigned long rh_detach_region(rh_info_t * info, unsigned long start, int size);
64
65/* Allocate the given size from the remote heap (with alignment) */
66extern unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment,
67 const char *owner);
68
69/* Allocate the given size from the remote heap */
70extern unsigned long rh_alloc(rh_info_t * info, int size, const char *owner);
71
72/* Allocate the given size from the given address */
73extern unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size,
74 const char *owner);
75
76/* Free the allocated area */
77extern int rh_free(rh_info_t * info, unsigned long start);
78
79/* Get stats for debugging purposes */
80extern int rh_get_stats(rh_info_t * info, int what, int max_stats,
81 rh_stats_t * stats);
82
83/* Simple dump of remote heap info */
84extern void rh_dump(rh_info_t * info);
85
86/* Set owner of taken block */
87extern int rh_set_owner(rh_info_t * info, unsigned long start, const char *owner);
88
89#endif /* __ASM_PPC_RHEAP_H__ */
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
new file mode 100644
index 000000000000..0018bf80cb25
--- /dev/null
+++ b/arch/powerpc/include/asm/rio.h
@@ -0,0 +1,18 @@
1/*
2 * RapidIO architecture support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef ASM_PPC_RIO_H
14#define ASM_PPC_RIO_H
15
16extern void platform_rio_init(void);
17
18#endif /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
new file mode 100644
index 000000000000..8eaa7b28d9d0
--- /dev/null
+++ b/arch/powerpc/include/asm/rtas.h
@@ -0,0 +1,247 @@
1#ifndef _POWERPC_RTAS_H
2#define _POWERPC_RTAS_H
3#ifdef __KERNEL__
4
5#include <linux/spinlock.h>
6#include <asm/page.h>
7
8/*
9 * Definitions for talking to the RTAS on CHRP machines.
10 *
11 * Copyright (C) 2001 Peter Bergner
12 * Copyright (C) 2001 PPC 64 Team, IBM Corp
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#define RTAS_UNKNOWN_SERVICE (-1)
21#define RTAS_INSTANTIATE_MAX (1UL<<30) /* Don't instantiate rtas at/above this value */
22
23/* Buffer size for ppc_rtas system call. */
24#define RTAS_RMOBUF_MAX (64 * 1024)
25
26/* RTAS return status codes */
27#define RTAS_NOT_SUSPENDABLE -9004
28#define RTAS_BUSY -2 /* RTAS Busy */
29#define RTAS_EXTENDED_DELAY_MIN 9900
30#define RTAS_EXTENDED_DELAY_MAX 9905
31
32/*
33 * In general to call RTAS use rtas_token("string") to lookup
34 * an RTAS token for the given string (e.g. "event-scan").
35 * To actually perform the call use
36 * ret = rtas_call(token, n_in, n_out, ...)
37 * Where n_in is the number of input parameters and
38 * n_out is the number of output parameters
39 *
40 * If the "string" is invalid on this system, RTAS_UNKNOWN_SERVICE
41 * will be returned as a token. rtas_call() does look for this
42 * token and error out gracefully so rtas_call(rtas_token("str"), ...)
43 * may be safely used for one-shot calls to RTAS.
44 *
45 */
46
47typedef u32 rtas_arg_t;
48
49struct rtas_args {
50 u32 token;
51 u32 nargs;
52 u32 nret;
53 rtas_arg_t args[16];
54 rtas_arg_t *rets; /* Pointer to return values in args[]. */
55};
56
57struct rtas_t {
58 unsigned long entry; /* physical address pointer */
59 unsigned long base; /* physical address pointer */
60 unsigned long size;
61 spinlock_t lock;
62 struct rtas_args args;
63 struct device_node *dev; /* virtual address pointer */
64};
65
66/* RTAS event classes */
67#define RTAS_INTERNAL_ERROR 0x80000000 /* set bit 0 */
68#define RTAS_EPOW_WARNING 0x40000000 /* set bit 1 */
69#define RTAS_POWERMGM_EVENTS 0x20000000 /* set bit 2 */
70#define RTAS_HOTPLUG_EVENTS 0x10000000 /* set bit 3 */
71#define RTAS_EVENT_SCAN_ALL_EVENTS 0xf0000000
72
73/* RTAS event severity */
74#define RTAS_SEVERITY_FATAL 0x5
75#define RTAS_SEVERITY_ERROR 0x4
76#define RTAS_SEVERITY_ERROR_SYNC 0x3
77#define RTAS_SEVERITY_WARNING 0x2
78#define RTAS_SEVERITY_EVENT 0x1
79#define RTAS_SEVERITY_NO_ERROR 0x0
80
81/* RTAS event disposition */
82#define RTAS_DISP_FULLY_RECOVERED 0x0
83#define RTAS_DISP_LIMITED_RECOVERY 0x1
84#define RTAS_DISP_NOT_RECOVERED 0x2
85
86/* RTAS event initiator */
87#define RTAS_INITIATOR_UNKNOWN 0x0
88#define RTAS_INITIATOR_CPU 0x1
89#define RTAS_INITIATOR_PCI 0x2
90#define RTAS_INITIATOR_ISA 0x3
91#define RTAS_INITIATOR_MEMORY 0x4
92#define RTAS_INITIATOR_POWERMGM 0x5
93
94/* RTAS event target */
95#define RTAS_TARGET_UNKNOWN 0x0
96#define RTAS_TARGET_CPU 0x1
97#define RTAS_TARGET_PCI 0x2
98#define RTAS_TARGET_ISA 0x3
99#define RTAS_TARGET_MEMORY 0x4
100#define RTAS_TARGET_POWERMGM 0x5
101
102/* RTAS event type */
103#define RTAS_TYPE_RETRY 0x01
104#define RTAS_TYPE_TCE_ERR 0x02
105#define RTAS_TYPE_INTERN_DEV_FAIL 0x03
106#define RTAS_TYPE_TIMEOUT 0x04
107#define RTAS_TYPE_DATA_PARITY 0x05
108#define RTAS_TYPE_ADDR_PARITY 0x06
109#define RTAS_TYPE_CACHE_PARITY 0x07
110#define RTAS_TYPE_ADDR_INVALID 0x08
111#define RTAS_TYPE_ECC_UNCORR 0x09
112#define RTAS_TYPE_ECC_CORR 0x0a
113#define RTAS_TYPE_EPOW 0x40
114#define RTAS_TYPE_PLATFORM 0xE0
115#define RTAS_TYPE_IO 0xE1
116#define RTAS_TYPE_INFO 0xE2
117#define RTAS_TYPE_DEALLOC 0xE3
118#define RTAS_TYPE_DUMP 0xE4
119/* I don't add PowerMGM events right now, this is a different topic */
120#define RTAS_TYPE_PMGM_POWER_SW_ON 0x60
121#define RTAS_TYPE_PMGM_POWER_SW_OFF 0x61
122#define RTAS_TYPE_PMGM_LID_OPEN 0x62
123#define RTAS_TYPE_PMGM_LID_CLOSE 0x63
124#define RTAS_TYPE_PMGM_SLEEP_BTN 0x64
125#define RTAS_TYPE_PMGM_WAKE_BTN 0x65
126#define RTAS_TYPE_PMGM_BATTERY_WARN 0x66
127#define RTAS_TYPE_PMGM_BATTERY_CRIT 0x67
128#define RTAS_TYPE_PMGM_SWITCH_TO_BAT 0x68
129#define RTAS_TYPE_PMGM_SWITCH_TO_AC 0x69
130#define RTAS_TYPE_PMGM_KBD_OR_MOUSE 0x6a
131#define RTAS_TYPE_PMGM_ENCLOS_OPEN 0x6b
132#define RTAS_TYPE_PMGM_ENCLOS_CLOSED 0x6c
133#define RTAS_TYPE_PMGM_RING_INDICATE 0x6d
134#define RTAS_TYPE_PMGM_LAN_ATTENTION 0x6e
135#define RTAS_TYPE_PMGM_TIME_ALARM 0x6f
136#define RTAS_TYPE_PMGM_CONFIG_CHANGE 0x70
137#define RTAS_TYPE_PMGM_SERVICE_PROC 0x71
138
139struct rtas_error_log {
140 unsigned long version:8; /* Architectural version */
141 unsigned long severity:3; /* Severity level of error */
142 unsigned long disposition:2; /* Degree of recovery */
143 unsigned long extended:1; /* extended log present? */
144 unsigned long /* reserved */ :2; /* Reserved for future use */
145 unsigned long initiator:4; /* Initiator of event */
146 unsigned long target:4; /* Target of failed operation */
147 unsigned long type:8; /* General event or error*/
148 unsigned long extended_log_length:32; /* length in bytes */
149 unsigned char buffer[1];
150};
151
152/*
153 * This can be set by the rtas_flash module so that it can get called
154 * as the absolutely last thing before the kernel terminates.
155 */
156extern void (*rtas_flash_term_hook)(int);
157
158extern struct rtas_t rtas;
159
160extern void enter_rtas(unsigned long);
161extern int rtas_token(const char *service);
162extern int rtas_service_present(const char *service);
163extern int rtas_call(int token, int, int, int *, ...);
164extern void rtas_restart(char *cmd);
165extern void rtas_power_off(void);
166extern void rtas_halt(void);
167extern void rtas_os_term(char *str);
168extern int rtas_get_sensor(int sensor, int index, int *state);
169extern int rtas_get_power_level(int powerdomain, int *level);
170extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
171extern int rtas_set_indicator(int indicator, int index, int new_value);
172extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
173extern void rtas_progress(char *s, unsigned short hex);
174extern void rtas_initialize(void);
175
176struct rtc_time;
177extern unsigned long rtas_get_boot_time(void);
178extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
179extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
180
181extern unsigned int rtas_busy_delay_time(int status);
182extern unsigned int rtas_busy_delay(int status);
183
184extern int early_init_dt_scan_rtas(unsigned long node,
185 const char *uname, int depth, void *data);
186
187extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
188
189/* Error types logged. */
190#define ERR_FLAG_ALREADY_LOGGED 0x0
191#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
192#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */
193#define ERR_TYPE_KERNEL_PANIC 0x4 /* from panic() */
194
195/* All the types and not flags */
196#define ERR_TYPE_MASK (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC)
197
198#define RTAS_DEBUG KERN_DEBUG "RTAS: "
199
200#define RTAS_ERROR_LOG_MAX 2048
201
202/*
203 * Return the firmware-specified size of the error log buffer
204 * for all rtas calls that require an error buffer argument.
205 * This includes 'check-exception' and 'rtas-last-error'.
206 */
207extern int rtas_get_error_log_max(void);
208
209/* Event Scan Parameters */
210#define EVENT_SCAN_ALL_EVENTS 0xf0000000
211#define SURVEILLANCE_TOKEN 9000
212#define LOG_NUMBER 64 /* must be a power of two */
213#define LOG_NUMBER_MASK (LOG_NUMBER-1)
214
215/* Some RTAS ops require a data buffer and that buffer must be < 4G.
216 * Rather than having a memory allocator, just use this buffer
217 * (get the lock first), make the RTAS call. Copy the data instead
218 * of holding the buffer for long.
219 */
220
221#define RTAS_DATA_BUF_SIZE 4096
222extern spinlock_t rtas_data_buf_lock;
223extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
224
225/* RMO buffer reserved for user-space RTAS use */
226extern unsigned long rtas_rmo_buf;
227
228#define GLOBAL_INTERRUPT_QUEUE 9005
229
230/**
231 * rtas_config_addr - Format a busno, devfn and reg for RTAS.
232 * @busno: The bus number.
233 * @devfn: The device and function number as encoded by PCI_DEVFN().
234 * @reg: The register number.
235 *
236 * This function encodes the given busno, devfn and register number as
237 * required for RTAS calls that take a "config_addr" parameter.
238 * See PAPR requirement 7.3.4-1 for more info.
239 */
240static inline u32 rtas_config_addr(int busno, int devfn, int reg)
241{
242 return ((reg & 0xf00) << 20) | ((busno & 0xff) << 16) |
243 (devfn << 8) | (reg & 0xff);
244}
245
246#endif /* __KERNEL__ */
247#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rtc.h b/arch/powerpc/include/asm/rtc.h
new file mode 100644
index 000000000000..f5802926b6c0
--- /dev/null
+++ b/arch/powerpc/include/asm/rtc.h
@@ -0,0 +1,78 @@
1/*
2 * Real-time clock definitions and interfaces
3 *
4 * Author: Tom Rini <trini@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Based on:
12 * include/asm-m68k/rtc.h
13 *
14 * Copyright Richard Zidlicky
15 * implementation details for genrtc/q40rtc driver
16 *
17 * And the old drivers/macintosh/rtc.c which was heavily based on:
18 * Linux/SPARC Real Time Clock Driver
19 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
20 *
21 * With additional work by Paul Mackerras and Franz Sirl.
22 */
23
24#ifndef __ASM_POWERPC_RTC_H__
25#define __ASM_POWERPC_RTC_H__
26
27#ifdef __KERNEL__
28
29#include <linux/rtc.h>
30
31#include <asm/machdep.h>
32#include <asm/time.h>
33
34#define RTC_PIE 0x40 /* periodic interrupt enable */
35#define RTC_AIE 0x20 /* alarm interrupt enable */
36#define RTC_UIE 0x10 /* update-finished interrupt enable */
37
38/* some dummy definitions */
39#define RTC_BATT_BAD 0x100 /* battery bad */
40#define RTC_SQWE 0x08 /* enable square-wave output */
41#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
42#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
43#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
44
45static inline unsigned int get_rtc_time(struct rtc_time *time)
46{
47 if (ppc_md.get_rtc_time)
48 ppc_md.get_rtc_time(time);
49 return RTC_24H;
50}
51
52/* Set the current date and time in the real time clock. */
53static inline int set_rtc_time(struct rtc_time *time)
54{
55 if (ppc_md.set_rtc_time)
56 return ppc_md.set_rtc_time(time);
57 return -EINVAL;
58}
59
60static inline unsigned int get_rtc_ss(void)
61{
62 struct rtc_time h;
63
64 get_rtc_time(&h);
65 return h.tm_sec;
66}
67
68static inline int get_rtc_pll(struct rtc_pll_info *pll)
69{
70 return -EINVAL;
71}
72static inline int set_rtc_pll(struct rtc_pll_info *pll)
73{
74 return -EINVAL;
75}
76
77#endif /* __KERNEL__ */
78#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
new file mode 100644
index 000000000000..24cd9281ec37
--- /dev/null
+++ b/arch/powerpc/include/asm/rwsem.h
@@ -0,0 +1,173 @@
1#ifndef _ASM_POWERPC_RWSEM_H
2#define _ASM_POWERPC_RWSEM_H
3
4#ifndef _LINUX_RWSEM_H
5#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
6#endif
7
8#ifdef __KERNEL__
9
10/*
11 * R/W semaphores for PPC using the stuff in lib/rwsem.c.
12 * Adapted largely from include/asm-i386/rwsem.h
13 * by Paul Mackerras <paulus@samba.org>.
14 */
15
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <asm/atomic.h>
19#include <asm/system.h>
20
21/*
22 * the semaphore definition
23 */
24struct rw_semaphore {
25 /* XXX this should be able to be an atomic_t -- paulus */
26 signed int count;
27#define RWSEM_UNLOCKED_VALUE 0x00000000
28#define RWSEM_ACTIVE_BIAS 0x00000001
29#define RWSEM_ACTIVE_MASK 0x0000ffff
30#define RWSEM_WAITING_BIAS (-0x00010000)
31#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
32#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
33 spinlock_t wait_lock;
34 struct list_head wait_list;
35#ifdef CONFIG_DEBUG_LOCK_ALLOC
36 struct lockdep_map dep_map;
37#endif
38};
39
40#ifdef CONFIG_DEBUG_LOCK_ALLOC
41# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
42#else
43# define __RWSEM_DEP_MAP_INIT(lockname)
44#endif
45
46#define __RWSEM_INITIALIZER(name) \
47 { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
48 LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
49
50#define DECLARE_RWSEM(name) \
51 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
52
53extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
54extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
55extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
56extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
57
58extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
59 struct lock_class_key *key);
60
61#define init_rwsem(sem) \
62 do { \
63 static struct lock_class_key __key; \
64 \
65 __init_rwsem((sem), #sem, &__key); \
66 } while (0)
67
68/*
69 * lock for reading
70 */
71static inline void __down_read(struct rw_semaphore *sem)
72{
73 if (unlikely(atomic_inc_return((atomic_t *)(&sem->count)) <= 0))
74 rwsem_down_read_failed(sem);
75}
76
77static inline int __down_read_trylock(struct rw_semaphore *sem)
78{
79 int tmp;
80
81 while ((tmp = sem->count) >= 0) {
82 if (tmp == cmpxchg(&sem->count, tmp,
83 tmp + RWSEM_ACTIVE_READ_BIAS)) {
84 return 1;
85 }
86 }
87 return 0;
88}
89
90/*
91 * lock for writing
92 */
93static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
94{
95 int tmp;
96
97 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_t *)(&sem->count));
99 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
100 rwsem_down_write_failed(sem);
101}
102
103static inline void __down_write(struct rw_semaphore *sem)
104{
105 __down_write_nested(sem, 0);
106}
107
108static inline int __down_write_trylock(struct rw_semaphore *sem)
109{
110 int tmp;
111
112 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
113 RWSEM_ACTIVE_WRITE_BIAS);
114 return tmp == RWSEM_UNLOCKED_VALUE;
115}
116
117/*
118 * unlock after reading
119 */
120static inline void __up_read(struct rw_semaphore *sem)
121{
122 int tmp;
123
124 tmp = atomic_dec_return((atomic_t *)(&sem->count));
125 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
126 rwsem_wake(sem);
127}
128
129/*
130 * unlock after writing
131 */
132static inline void __up_write(struct rw_semaphore *sem)
133{
134 if (unlikely(atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
135 (atomic_t *)(&sem->count)) < 0))
136 rwsem_wake(sem);
137}
138
139/*
140 * implement atomic add functionality
141 */
142static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
143{
144 atomic_add(delta, (atomic_t *)(&sem->count));
145}
146
147/*
148 * downgrade write lock to read lock
149 */
150static inline void __downgrade_write(struct rw_semaphore *sem)
151{
152 int tmp;
153
154 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
155 if (tmp < 0)
156 rwsem_downgrade_wake(sem);
157}
158
159/*
160 * implement exchange and add functionality
161 */
162static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
163{
164 return atomic_add_return(delta, (atomic_t *)(&sem->count));
165}
166
167static inline int rwsem_is_locked(struct rw_semaphore *sem)
168{
169 return (sem->count != 0);
170}
171
172#endif /* __KERNEL__ */
173#endif /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/scatterlist.h b/arch/powerpc/include/asm/scatterlist.h
new file mode 100644
index 000000000000..fcf7d55afe45
--- /dev/null
+++ b/arch/powerpc/include/asm/scatterlist.h
@@ -0,0 +1,50 @@
1#ifndef _ASM_POWERPC_SCATTERLIST_H
2#define _ASM_POWERPC_SCATTERLIST_H
3/*
4 * Copyright (C) 2001 PPC64 Team, IBM Corp
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifdef __KERNEL__
13#include <linux/types.h>
14#include <asm/dma.h>
15
16struct scatterlist {
17#ifdef CONFIG_DEBUG_SG
18 unsigned long sg_magic;
19#endif
20 unsigned long page_link;
21 unsigned int offset;
22 unsigned int length;
23
24 /* For TCE support */
25 dma_addr_t dma_address;
26 u32 dma_length;
27};
28
29/*
30 * These macros should be used after a dma_map_sg call has been done
31 * to get bus addresses of each of the SG entries and their lengths.
32 * You should only work with the number of sg entries pci_map_sg
33 * returns, or alternatively stop on the first sg_dma_len(sg) which
34 * is 0.
35 */
36#define sg_dma_address(sg) ((sg)->dma_address)
37#ifdef __powerpc64__
38#define sg_dma_len(sg) ((sg)->dma_length)
39#else
40#define sg_dma_len(sg) ((sg)->length)
41#endif
42
43#ifdef __powerpc64__
44#define ISA_DMA_THRESHOLD (~0UL)
45#endif
46
47#define ARCH_HAS_SG_CHAIN
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/arch/powerpc/include/asm/seccomp.h b/arch/powerpc/include/asm/seccomp.h
new file mode 100644
index 000000000000..853765eb1f65
--- /dev/null
+++ b/arch/powerpc/include/asm/seccomp.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_SECCOMP_H
2#define _ASM_POWERPC_SECCOMP_H
3
4#ifdef __KERNEL__
5#include <linux/thread_info.h>
6#endif
7
8#include <linux/unistd.h>
9
10#define __NR_seccomp_read __NR_read
11#define __NR_seccomp_write __NR_write
12#define __NR_seccomp_exit __NR_exit
13#define __NR_seccomp_sigreturn __NR_rt_sigreturn
14
15#define __NR_seccomp_read_32 __NR_read
16#define __NR_seccomp_write_32 __NR_write
17#define __NR_seccomp_exit_32 __NR_exit
18#define __NR_seccomp_sigreturn_32 __NR_sigreturn
19
20#endif /* _ASM_POWERPC_SECCOMP_H */
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
new file mode 100644
index 000000000000..916018e425c4
--- /dev/null
+++ b/arch/powerpc/include/asm/sections.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_POWERPC_SECTIONS_H
2#define _ASM_POWERPC_SECTIONS_H
3#ifdef __KERNEL__
4
5#include <asm-generic/sections.h>
6
7#ifdef __powerpc64__
8
9extern char _end[];
10
11static inline int in_kernel_text(unsigned long addr)
12{
13 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
14 return 1;
15
16 return 0;
17}
18
19#endif
20
21#endif /* __KERNEL__ */
22#endif /* _ASM_POWERPC_SECTIONS_H */
diff --git a/arch/powerpc/include/asm/sembuf.h b/arch/powerpc/include/asm/sembuf.h
new file mode 100644
index 000000000000..99a41938ae3d
--- /dev/null
+++ b/arch/powerpc/include/asm/sembuf.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_POWERPC_SEMBUF_H
2#define _ASM_POWERPC_SEMBUF_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * The semid64_ds structure for PPC architecture.
13 * Note extra padding because this structure is passed back and forth
14 * between kernel and user space.
15 *
16 * Pad space is left for:
17 * - 64-bit time_t to solve y2038 problem
18 * - 2 miscellaneous 32-bit values
19 */
20
21struct semid64_ds {
22 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
23#ifndef __powerpc64__
24 unsigned long __unused1;
25#endif
26 __kernel_time_t sem_otime; /* last semop time */
27#ifndef __powerpc64__
28 unsigned long __unused2;
29#endif
30 __kernel_time_t sem_ctime; /* last change time */
31 unsigned long sem_nsems; /* no. of semaphores in array */
32 unsigned long __unused3;
33 unsigned long __unused4;
34};
35
36#endif /* _ASM_POWERPC_SEMBUF_H */
diff --git a/arch/powerpc/include/asm/serial.h b/arch/powerpc/include/asm/serial.h
new file mode 100644
index 000000000000..3e8589b43cb2
--- /dev/null
+++ b/arch/powerpc/include/asm/serial.h
@@ -0,0 +1,24 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_SERIAL_H
8#define _ASM_POWERPC_SERIAL_H
9
10/*
11 * Serial ports are not listed here, because they are discovered
12 * through the device tree.
13 */
14
15/* Default baud base if not found in device-tree */
16#define BASE_BAUD ( 1843200 / 16 )
17
18#ifdef CONFIG_PPC_UDBG_16550
19extern void find_legacy_serial_ports(void);
20#else
21#define find_legacy_serial_ports() do { } while (0)
22#endif
23
24#endif /* _PPC64_SERIAL_H */
diff --git a/arch/powerpc/include/asm/setjmp.h b/arch/powerpc/include/asm/setjmp.h
new file mode 100644
index 000000000000..279d03a1eec6
--- /dev/null
+++ b/arch/powerpc/include/asm/setjmp.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright © 2008 Michael Neuling IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 */
10#ifndef _ASM_POWERPC_SETJMP_H
11#define _ASM_POWERPC_SETJMP_H
12
13#define JMP_BUF_LEN 23
14
15extern long setjmp(long *);
16extern void longjmp(long *, long);
17
18#endif /* _ASM_POWERPC_SETJMP_H */
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
new file mode 100644
index 000000000000..817fac0a0714
--- /dev/null
+++ b/arch/powerpc/include/asm/setup.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_POWERPC_SETUP_H
2#define _ASM_POWERPC_SETUP_H
3
4#define COMMAND_LINE_SIZE 512
5
6#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/include/asm/shmbuf.h b/arch/powerpc/include/asm/shmbuf.h
new file mode 100644
index 000000000000..8efa39698b6c
--- /dev/null
+++ b/arch/powerpc/include/asm/shmbuf.h
@@ -0,0 +1,59 @@
1#ifndef _ASM_POWERPC_SHMBUF_H
2#define _ASM_POWERPC_SHMBUF_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * The shmid64_ds structure for PPC architecture.
13 *
14 * Note extra padding because this structure is passed back and forth
15 * between kernel and user space.
16 *
17 * Pad space is left for:
18 * - 64-bit time_t to solve y2038 problem
19 * - 2 miscellaneous 32-bit values
20 */
21
22struct shmid64_ds {
23 struct ipc64_perm shm_perm; /* operation perms */
24#ifndef __powerpc64__
25 unsigned long __unused1;
26#endif
27 __kernel_time_t shm_atime; /* last attach time */
28#ifndef __powerpc64__
29 unsigned long __unused2;
30#endif
31 __kernel_time_t shm_dtime; /* last detach time */
32#ifndef __powerpc64__
33 unsigned long __unused3;
34#endif
35 __kernel_time_t shm_ctime; /* last change time */
36#ifndef __powerpc64__
37 unsigned long __unused4;
38#endif
39 size_t shm_segsz; /* size of segment (bytes) */
40 __kernel_pid_t shm_cpid; /* pid of creator */
41 __kernel_pid_t shm_lpid; /* pid of last operator */
42 unsigned long shm_nattch; /* no. of current attaches */
43 unsigned long __unused5;
44 unsigned long __unused6;
45};
46
47struct shminfo64 {
48 unsigned long shmmax;
49 unsigned long shmmin;
50 unsigned long shmmni;
51 unsigned long shmseg;
52 unsigned long shmall;
53 unsigned long __unused1;
54 unsigned long __unused2;
55 unsigned long __unused3;
56 unsigned long __unused4;
57};
58
59#endif /* _ASM_POWERPC_SHMBUF_H */
diff --git a/arch/powerpc/include/asm/shmparam.h b/arch/powerpc/include/asm/shmparam.h
new file mode 100644
index 000000000000..5cda42a6d39e
--- /dev/null
+++ b/arch/powerpc/include/asm/shmparam.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_POWERPC_SHMPARAM_H
2#define _ASM_POWERPC_SHMPARAM_H
3
4#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
5
6#endif /* _ASM_POWERPC_SHMPARAM_H */
diff --git a/arch/powerpc/include/asm/sigcontext.h b/arch/powerpc/include/asm/sigcontext.h
new file mode 100644
index 000000000000..9c1f24fd5d11
--- /dev/null
+++ b/arch/powerpc/include/asm/sigcontext.h
@@ -0,0 +1,87 @@
1#ifndef _ASM_POWERPC_SIGCONTEXT_H
2#define _ASM_POWERPC_SIGCONTEXT_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#include <linux/compiler.h>
11#include <asm/ptrace.h>
12#ifdef __powerpc64__
13#include <asm/elf.h>
14#endif
15
16struct sigcontext {
17 unsigned long _unused[4];
18 int signal;
19#ifdef __powerpc64__
20 int _pad0;
21#endif
22 unsigned long handler;
23 unsigned long oldmask;
24 struct pt_regs __user *regs;
25#ifdef __powerpc64__
26 elf_gregset_t gp_regs;
27 elf_fpregset_t fp_regs;
28/*
29 * To maintain compatibility with current implementations the sigcontext is
30 * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
31 * followed by an unstructured (vmx_reserve) field of 69 doublewords. This
32 * allows the array of vector registers to be quadword aligned independent of
33 * the alignment of the containing sigcontext or ucontext. It is the
34 * responsibility of the code setting the sigcontext to set this pointer to
35 * either NULL (if this processor does not support the VMX feature) or the
36 * address of the first quadword within the allocated (vmx_reserve) area.
37 *
38 * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
39 * an array of 34 quadword entries (elf_vrregset_t). The entries with
40 * indexes 0-31 contain the corresponding vector registers. The entry with
41 * index 32 contains the vscr as the last word (offset 12) within the
42 * quadword. This allows the vscr to be stored as either a quadword (since
43 * it must be copied via a vector register to/from storage) or as a word.
44 * The entry with index 33 contains the vrsave as the first word (offset 0)
45 * within the quadword.
46 *
47 * Part of the VSX data is stored here also by extending vmx_restore
48 * by an additional 32 double words. Architecturally the layout of
49 * the VSR registers and how they overlap on top of the legacy FPR and
50 * VR registers is shown below:
51 *
52 * VSR doubleword 0 VSR doubleword 1
53 * ----------------------------------------------------------------
54 * VSR[0] | FPR[0] | |
55 * ----------------------------------------------------------------
56 * VSR[1] | FPR[1] | |
57 * ----------------------------------------------------------------
58 * | ... | |
59 * | ... | |
60 * ----------------------------------------------------------------
61 * VSR[30] | FPR[30] | |
62 * ----------------------------------------------------------------
63 * VSR[31] | FPR[31] | |
64 * ----------------------------------------------------------------
65 * VSR[32] | VR[0] |
66 * ----------------------------------------------------------------
67 * VSR[33] | VR[1] |
68 * ----------------------------------------------------------------
69 * | ... |
70 * | ... |
71 * ----------------------------------------------------------------
72 * VSR[62] | VR[30] |
73 * ----------------------------------------------------------------
74 * VSR[63] | VR[31] |
75 * ----------------------------------------------------------------
76 *
77 * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
78 * is stored at the start of vmx_reserve. vmx_reserve is extended for
79 * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
80 * registers and vscr/vrsave.
81 */
82 elf_vrreg_t __user *v_regs;
83 long vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
84#endif
85};
86
87#endif /* _ASM_POWERPC_SIGCONTEXT_H */
diff --git a/arch/powerpc/include/asm/siginfo.h b/arch/powerpc/include/asm/siginfo.h
new file mode 100644
index 000000000000..12f1bce037be
--- /dev/null
+++ b/arch/powerpc/include/asm/siginfo.h
@@ -0,0 +1,26 @@
1#ifndef _ASM_POWERPC_SIGINFO_H
2#define _ASM_POWERPC_SIGINFO_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifdef __powerpc64__
12# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
13# define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
14#endif
15
16#include <asm-generic/siginfo.h>
17
18/*
19 * SIGTRAP si_codes
20 */
21#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
22#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint or watchpoint */
23#undef NSIGTRAP
24#define NSIGTRAP 4
25
26#endif /* _ASM_POWERPC_SIGINFO_H */
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
new file mode 100644
index 000000000000..a7360cdd99eb
--- /dev/null
+++ b/arch/powerpc/include/asm/signal.h
@@ -0,0 +1,150 @@
1#ifndef _ASM_POWERPC_SIGNAL_H
2#define _ASM_POWERPC_SIGNAL_H
3
4#include <linux/types.h>
5
6#define _NSIG 64
7#ifdef __powerpc64__
8#define _NSIG_BPW 64
9#else
10#define _NSIG_BPW 32
11#endif
12#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
13
14typedef unsigned long old_sigset_t; /* at least 32 bits */
15
16typedef struct {
17 unsigned long sig[_NSIG_WORDS];
18} sigset_t;
19
20#define SIGHUP 1
21#define SIGINT 2
22#define SIGQUIT 3
23#define SIGILL 4
24#define SIGTRAP 5
25#define SIGABRT 6
26#define SIGIOT 6
27#define SIGBUS 7
28#define SIGFPE 8
29#define SIGKILL 9
30#define SIGUSR1 10
31#define SIGSEGV 11
32#define SIGUSR2 12
33#define SIGPIPE 13
34#define SIGALRM 14
35#define SIGTERM 15
36#define SIGSTKFLT 16
37#define SIGCHLD 17
38#define SIGCONT 18
39#define SIGSTOP 19
40#define SIGTSTP 20
41#define SIGTTIN 21
42#define SIGTTOU 22
43#define SIGURG 23
44#define SIGXCPU 24
45#define SIGXFSZ 25
46#define SIGVTALRM 26
47#define SIGPROF 27
48#define SIGWINCH 28
49#define SIGIO 29
50#define SIGPOLL SIGIO
51/*
52#define SIGLOST 29
53*/
54#define SIGPWR 30
55#define SIGSYS 31
56#define SIGUNUSED 31
57
58/* These should not be considered constants from userland. */
59#define SIGRTMIN 32
60#define SIGRTMAX _NSIG
61
62/*
63 * SA_FLAGS values:
64 *
65 * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
66 * SA_RESTART flag to get restarting signals (which were the default long ago)
67 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
68 * SA_RESETHAND clears the handler when the signal is delivered.
69 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
70 * SA_NODEFER prevents the current signal from being masked in the handler.
71 *
72 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
73 * Unix names RESETHAND and NODEFER respectively.
74 */
75#define SA_NOCLDSTOP 0x00000001U
76#define SA_NOCLDWAIT 0x00000002U
77#define SA_SIGINFO 0x00000004U
78#define SA_ONSTACK 0x08000000U
79#define SA_RESTART 0x10000000U
80#define SA_NODEFER 0x40000000U
81#define SA_RESETHAND 0x80000000U
82
83#define SA_NOMASK SA_NODEFER
84#define SA_ONESHOT SA_RESETHAND
85
86#define SA_RESTORER 0x04000000U
87
88/*
89 * sigaltstack controls
90 */
91#define SS_ONSTACK 1
92#define SS_DISABLE 2
93
94#define MINSIGSTKSZ 2048
95#define SIGSTKSZ 8192
96
97#include <asm-generic/signal.h>
98
99struct old_sigaction {
100 __sighandler_t sa_handler;
101 old_sigset_t sa_mask;
102 unsigned long sa_flags;
103 __sigrestore_t sa_restorer;
104};
105
106struct sigaction {
107 __sighandler_t sa_handler;
108 unsigned long sa_flags;
109 __sigrestore_t sa_restorer;
110 sigset_t sa_mask; /* mask last for extensibility */
111};
112
113struct k_sigaction {
114 struct sigaction sa;
115};
116
117typedef struct sigaltstack {
118 void __user *ss_sp;
119 int ss_flags;
120 size_t ss_size;
121} stack_t;
122
123#ifdef __KERNEL__
124struct pt_regs;
125extern void do_signal(struct pt_regs *regs, unsigned long thread_info_flags);
126#define ptrace_signal_deliver(regs, cookie) do { } while (0)
127#endif /* __KERNEL__ */
128
129#ifndef __powerpc64__
130/*
131 * These are parameters to dbg_sigreturn syscall. They enable or
132 * disable certain debugging things that can be done from signal
133 * handlers. The dbg_sigreturn syscall *must* be called from a
134 * SA_SIGINFO signal so the ucontext can be passed to it. It takes an
135 * array of struct sig_dbg_op, which has the debug operations to
136 * perform before returning from the signal.
137 */
138struct sig_dbg_op {
139 int dbg_type;
140 unsigned long dbg_value;
141};
142
143/* Enable or disable single-stepping. The value sets the state. */
144#define SIG_DBG_SINGLE_STEPPING 1
145
146/* Enable or disable branch tracing. The value sets the state. */
147#define SIG_DBG_BRANCH_TRACING 2
148#endif /* ! __powerpc64__ */
149
150#endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
new file mode 100644
index 000000000000..4d28e1e4521b
--- /dev/null
+++ b/arch/powerpc/include/asm/smp.h
@@ -0,0 +1,127 @@
1/*
2 * smp.h: PowerPC-specific SMP code.
3 *
4 * Original was a copy of sparc smp.h. Now heavily modified
5 * for PPC.
6 *
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef _ASM_POWERPC_SMP_H
17#define _ASM_POWERPC_SMP_H
18#ifdef __KERNEL__
19
20#include <linux/threads.h>
21#include <linux/cpumask.h>
22#include <linux/kernel.h>
23
24#ifndef __ASSEMBLY__
25
26#ifdef CONFIG_PPC64
27#include <asm/paca.h>
28#endif
29#include <asm/percpu.h>
30
31extern int boot_cpuid;
32
33extern void cpu_die(void);
34
35#ifdef CONFIG_SMP
36
37extern void smp_send_debugger_break(int cpu);
38extern void smp_message_recv(int);
39
40DECLARE_PER_CPU(unsigned int, pvr);
41
42#ifdef CONFIG_HOTPLUG_CPU
43extern void fixup_irqs(cpumask_t map);
44int generic_cpu_disable(void);
45int generic_cpu_enable(unsigned int cpu);
46void generic_cpu_die(unsigned int cpu);
47void generic_mach_cpu_die(void);
48#endif
49
50#ifdef CONFIG_PPC64
51#define raw_smp_processor_id() (local_paca->paca_index)
52#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
53#else
54/* 32-bit */
55extern int smp_hw_index[];
56
57#define raw_smp_processor_id() (current_thread_info()->cpu)
58#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
59#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)])
60#define set_hard_smp_processor_id(cpu, phys)\
61 (smp_hw_index[(cpu)] = (phys))
62#endif
63
64DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
65DECLARE_PER_CPU(cpumask_t, cpu_core_map);
66extern int cpu_to_core_id(int cpu);
67
68/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
69 *
70 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
71 * in /proc/interrupts will be wrong!!! --Troy */
72#define PPC_MSG_CALL_FUNCTION 0
73#define PPC_MSG_RESCHEDULE 1
74#define PPC_MSG_CALL_FUNC_SINGLE 2
75#define PPC_MSG_DEBUGGER_BREAK 3
76
77void smp_init_iSeries(void);
78void smp_init_pSeries(void);
79void smp_init_cell(void);
80void smp_init_celleb(void);
81void smp_setup_cpu_maps(void);
82void smp_setup_cpu_sibling_map(void);
83
84extern int __cpu_disable(void);
85extern void __cpu_die(unsigned int cpu);
86
87#else
88/* for UP */
89#define hard_smp_processor_id() 0
90#define smp_setup_cpu_maps()
91
92#endif /* CONFIG_SMP */
93
94#ifdef CONFIG_PPC64
95#define get_hard_smp_processor_id(CPU) (paca[(CPU)].hw_cpu_id)
96#define set_hard_smp_processor_id(CPU, VAL) \
97 do { (paca[(CPU)].hw_cpu_id = (VAL)); } while (0)
98
99extern void smp_release_cpus(void);
100
101#else
102/* 32-bit */
103#ifndef CONFIG_SMP
104extern int boot_cpuid_phys;
105#define get_hard_smp_processor_id(cpu) boot_cpuid_phys
106#define set_hard_smp_processor_id(cpu, phys)
107#endif
108#endif
109
110extern int smt_enabled_at_boot;
111
112extern int smp_mpic_probe(void);
113extern void smp_mpic_setup_cpu(int cpu);
114extern void smp_generic_kick_cpu(int nr);
115
116extern void smp_generic_give_timebase(void);
117extern void smp_generic_take_timebase(void);
118
119extern struct smp_ops_t *smp_ops;
120
121extern void arch_send_call_function_single_ipi(int cpu);
122extern void arch_send_call_function_ipi(cpumask_t mask);
123
124#endif /* __ASSEMBLY__ */
125
126#endif /* __KERNEL__ */
127#endif /* _ASM_POWERPC_SMP_H) */
diff --git a/arch/powerpc/include/asm/smu.h b/arch/powerpc/include/asm/smu.h
new file mode 100644
index 000000000000..7ae2753da565
--- /dev/null
+++ b/arch/powerpc/include/asm/smu.h
@@ -0,0 +1,700 @@
1#ifndef _SMU_H
2#define _SMU_H
3
4/*
5 * Definitions for talking to the SMU chip in newer G5 PowerMacs
6 */
7#ifdef __KERNEL__
8#include <linux/list.h>
9#endif
10#include <linux/types.h>
11
12/*
13 * Known SMU commands
14 *
15 * Most of what is below comes from looking at the Open Firmware driver,
16 * though this is still incomplete and could use better documentation here
17 * or there...
18 */
19
20
21/*
22 * Partition info commands
23 *
24 * These commands are used to retrieve the sdb-partition-XX datas from
25 * the SMU. The length is always 2. First byte is the subcommand code
26 * and second byte is the partition ID.
27 *
28 * The reply is 6 bytes:
29 *
30 * - 0..1 : partition address
31 * - 2 : a byte containing the partition ID
32 * - 3 : length (maybe other bits are rest of header ?)
33 *
34 * The data must then be obtained with calls to another command:
35 * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
36 */
37#define SMU_CMD_PARTITION_COMMAND 0x3e
38#define SMU_CMD_PARTITION_LATEST 0x01
39#define SMU_CMD_PARTITION_BASE 0x02
40#define SMU_CMD_PARTITION_UPDATE 0x03
41
42
43/*
44 * Fan control
45 *
46 * This is a "mux" for fan control commands. The command seem to
47 * act differently based on the number of arguments. With 1 byte
48 * of argument, this seem to be queries for fans status, setpoint,
49 * etc..., while with 0xe arguments, we will set the fans speeds.
50 *
51 * Queries (1 byte arg):
52 * ---------------------
53 *
54 * arg=0x01: read RPM fans status
55 * arg=0x02: read RPM fans setpoint
56 * arg=0x11: read PWM fans status
57 * arg=0x12: read PWM fans setpoint
58 *
59 * the "status" queries return the current speed while the "setpoint" ones
60 * return the programmed/target speed. It _seems_ that the result is a bit
61 * mask in the first byte of active/available fans, followed by 6 words (16
62 * bits) containing the requested speed.
63 *
64 * Setpoint (14 bytes arg):
65 * ------------------------
66 *
67 * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
68 * mask of fans affected by the command. Followed by 6 words containing the
69 * setpoint value for selected fans in the mask (or 0 if mask value is 0)
70 */
71#define SMU_CMD_FAN_COMMAND 0x4a
72
73
74/*
75 * Battery access
76 *
77 * Same command number as the PMU, could it be same syntax ?
78 */
79#define SMU_CMD_BATTERY_COMMAND 0x6f
80#define SMU_CMD_GET_BATTERY_INFO 0x00
81
82/*
83 * Real time clock control
84 *
85 * This is a "mux", first data byte contains the "sub" command.
86 * The "RTC" part of the SMU controls the date, time, powerup
87 * timer, but also a PRAM
88 *
89 * Dates are in BCD format on 7 bytes:
90 * [sec] [min] [hour] [weekday] [month day] [month] [year]
91 * with month being 1 based and year minus 100
92 */
93#define SMU_CMD_RTC_COMMAND 0x8e
94#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
95#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
96#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
97#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
98#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
99#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
100#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
101#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
102#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
103#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
104#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
105#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
106
107 /*
108 * i2c commands
109 *
110 * To issue an i2c command, first is to send a parameter block to the
111 * the SMU. This is a command of type 0x9a with 9 bytes of header
112 * eventually followed by data for a write:
113 *
114 * 0: bus number (from device-tree usually, SMU has lots of busses !)
115 * 1: transfer type/format (see below)
116 * 2: device address. For combined and combined4 type transfers, this
117 * is the "write" version of the address (bit 0x01 cleared)
118 * 3: subaddress length (0..3)
119 * 4: subaddress byte 0 (or only byte for subaddress length 1)
120 * 5: subaddress byte 1
121 * 6: subaddress byte 2
122 * 7: combined address (device address for combined mode data phase)
123 * 8: data length
124 *
125 * The transfer types are the same good old Apple ones it seems,
126 * that is:
127 * - 0x00: Simple transfer
128 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
129 * - 0x02: Combined transfer (addr write + restart + data tx)
130 *
131 * This is then followed by actual data for a write.
132 *
133 * At this point, the OF driver seems to have a limitation on transfer
134 * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
135 * wether this is just an OF limit due to some temporary buffer size
136 * or if this is an SMU imposed limit. This driver has the same limitation
137 * for now as I use a 0x10 bytes temporary buffer as well
138 *
139 * Once that is completed, a response is expected from the SMU. This is
140 * obtained via a command of type 0x9a with a length of 1 byte containing
141 * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
142 * though I can't tell yet if this is actually necessary. Once this command
143 * is complete, at this point, all I can tell is what OF does. OF tests
144 * byte 0 of the reply:
145 * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
146 * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
147 * - on write, < 0 -> failure (immediate exit)
148 * - else, OF just exists (without error, weird)
149 *
150 * So on read, there is this wait-for-busy thing when getting a 0xfc or
151 * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
152 * doing the above again until either the retries expire or the result
153 * is no longer 0xfe or 0xfc
154 *
155 * The Darwin I2C driver is less subtle though. On any non-success status
156 * from the response command, it waits 5ms and tries again up to 20 times,
157 * it doesn't differenciate between fatal errors or "busy" status.
158 *
159 * This driver provides an asynchronous paramblock based i2c command
160 * interface to be used either directly by low level code or by a higher
161 * level driver interfacing to the linux i2c layer. The current
162 * implementation of this relies on working timers & timer interrupts
163 * though, so be careful of calling context for now. This may be "fixed"
164 * in the future by adding a polling facility.
165 */
166#define SMU_CMD_I2C_COMMAND 0x9a
167 /* transfer types */
168#define SMU_I2C_TRANSFER_SIMPLE 0x00
169#define SMU_I2C_TRANSFER_STDSUB 0x01
170#define SMU_I2C_TRANSFER_COMBINED 0x02
171
172/*
173 * Power supply control
174 *
175 * The "sub" command is an ASCII string in the data, the
176 * data length is that of the string.
177 *
178 * The VSLEW command can be used to get or set the voltage slewing.
179 * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
180 * reply at data offset 6, 7 and 8.
181 * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
182 * used to set the voltage slewing point. The SMU replies with "DONE"
183 * I yet have to figure out their exact meaning of those 3 bytes in
184 * both cases. They seem to be:
185 * x = processor mask
186 * y = op. point index
187 * z = processor freq. step index
188 * I haven't yet decyphered result codes
189 *
190 */
191#define SMU_CMD_POWER_COMMAND 0xaa
192#define SMU_CMD_POWER_RESTART "RESTART"
193#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
194#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
195
196/*
197 * Read ADC sensors
198 *
199 * This command takes one byte of parameter: the sensor ID (or "reg"
200 * value in the device-tree) and returns a 16 bits value
201 */
202#define SMU_CMD_READ_ADC 0xd8
203
204
205/* Misc commands
206 *
207 * This command seem to be a grab bag of various things
208 *
209 * Parameters:
210 * 1: subcommand
211 */
212#define SMU_CMD_MISC_df_COMMAND 0xdf
213
214/*
215 * Sets "system ready" status
216 *
217 * I did not yet understand how it exactly works or what it does.
218 *
219 * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
220 * the same codebase for all OF versions. On PowerBooks, this command would
221 * enable the backlight. For the G5s, it only activates the front LED. However,
222 * don't take this for granted.
223 *
224 * Parameters:
225 * 2: status [0x00, 0x01 or 0x02]
226 */
227#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02
228
229/*
230 * Sets mode of power switch.
231 *
232 * What this actually does is not yet known. Maybe it enables some interrupt.
233 *
234 * Parameters:
235 * 2: enable power switch? [0x00 or 0x01]
236 * 3 (optional): enable nmi? [0x00 or 0x01]
237 *
238 * Returns:
239 * If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
240 * NMI is enabled. Otherwise unknown.
241 */
242#define SMU_CMD_MISC_df_NMI_OPTION 0x04
243
244/* Sets LED dimm offset.
245 *
246 * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
247 * frequency) depends on current time. Therefore, the SMU needs to know the
248 * timezone.
249 *
250 * Parameters:
251 * 2-8: unknown (BCD coding)
252 */
253#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99
254
255
256/*
257 * Version info commands
258 *
259 * Parameters:
260 * 1 (optional): Specifies version part to retrieve
261 *
262 * Returns:
263 * Version value
264 */
265#define SMU_CMD_VERSION_COMMAND 0xea
266#define SMU_VERSION_RUNNING 0x00
267#define SMU_VERSION_BASE 0x01
268#define SMU_VERSION_UPDATE 0x02
269
270
271/*
272 * Switches
273 *
274 * These are switches whose status seems to be known to the SMU.
275 *
276 * Parameters:
277 * none
278 *
279 * Result:
280 * Switch bits (ORed, see below)
281 */
282#define SMU_CMD_SWITCHES 0xdc
283
284/* Switches bits */
285#define SMU_SWITCH_CASE_CLOSED 0x01
286#define SMU_SWITCH_AC_POWER 0x04
287#define SMU_SWITCH_POWER_SWITCH 0x08
288
289
290/*
291 * Misc commands
292 *
293 * This command seem to be a grab bag of various things
294 *
295 * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
296 * transfer blocks of data from the SMU. So far, I've decrypted it's
297 * usage to retrieve partition data. In order to do that, you have to
298 * break your transfer in "chunks" since that command cannot transfer
299 * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
300 * but it seems that the darwin driver will let you do 0x1e bytes if
301 * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
302 * either in the last 16 bits of property "smu-version-pmu" or as the 16
303 * bytes at offset 1 of "smu-version-info"
304 *
305 * For each chunk, the command takes 7 bytes of arguments:
306 * byte 0: subcommand code (0x02)
307 * byte 1: 0x04 (always, I don't know what it means, maybe the address
308 * space to use or some other nicety. It's hard coded in OF)
309 * byte 2..5: SMU address of the chunk (big endian 32 bits)
310 * byte 6: size to transfer (up to max chunk size)
311 *
312 * The data is returned directly
313 */
314#define SMU_CMD_MISC_ee_COMMAND 0xee
315#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
316
317/* Retrieves currently used watts.
318 *
319 * Parameters:
320 * 1: 0x03 (Meaning unknown)
321 */
322#define SMU_CMD_MISC_ee_GET_WATTS 0x03
323
324#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
325#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
326
327
328/*
329 * Power related commands
330 *
331 * Parameters:
332 * 1: subcommand
333 */
334#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f
335
336/* SMU_POWER_EVENTS subcommands */
337enum {
338 SMU_PWR_GET_POWERUP_EVENTS = 0x00,
339 SMU_PWR_SET_POWERUP_EVENTS = 0x01,
340 SMU_PWR_CLR_POWERUP_EVENTS = 0x02,
341 SMU_PWR_GET_WAKEUP_EVENTS = 0x03,
342 SMU_PWR_SET_WAKEUP_EVENTS = 0x04,
343 SMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
344
345 /*
346 * Get last shutdown cause
347 *
348 * Returns:
349 * 1 byte (signed char): Last shutdown cause. Exact meaning unknown.
350 */
351 SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07,
352
353 /*
354 * Sets or gets server ID. Meaning or use is unknown.
355 *
356 * Parameters:
357 * 2 (optional): Set server ID (1 byte)
358 *
359 * Returns:
360 * 1 byte (server ID?)
361 */
362 SMU_PWR_SERVER_ID = 0x08,
363};
364
365/* Power events wakeup bits */
366enum {
367 SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
368 SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
369 SMU_PWR_WAKEUP_AC_CHANGE = 0x04,
370 SMU_PWR_WAKEUP_LID_OPEN = 0x08,
371 SMU_PWR_WAKEUP_RING = 0x10,
372};
373
374
375/*
376 * - Kernel side interface -
377 */
378
379#ifdef __KERNEL__
380
381/*
382 * Asynchronous SMU commands
383 *
384 * Fill up this structure and submit it via smu_queue_command(),
385 * and get notified by the optional done() callback, or because
386 * status becomes != 1
387 */
388
389struct smu_cmd;
390
391struct smu_cmd
392{
393 /* public */
394 u8 cmd; /* command */
395 int data_len; /* data len */
396 int reply_len; /* reply len */
397 void *data_buf; /* data buffer */
398 void *reply_buf; /* reply buffer */
399 int status; /* command status */
400 void (*done)(struct smu_cmd *cmd, void *misc);
401 void *misc;
402
403 /* private */
404 struct list_head link;
405};
406
407/*
408 * Queues an SMU command, all fields have to be initialized
409 */
410extern int smu_queue_cmd(struct smu_cmd *cmd);
411
412/*
413 * Simple command wrapper. This structure embeds a small buffer
414 * to ease sending simple SMU commands from the stack
415 */
416struct smu_simple_cmd
417{
418 struct smu_cmd cmd;
419 u8 buffer[16];
420};
421
422/*
423 * Queues a simple command. All fields will be initialized by that
424 * function
425 */
426extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
427 unsigned int data_len,
428 void (*done)(struct smu_cmd *cmd, void *misc),
429 void *misc,
430 ...);
431
432/*
433 * Completion helper. Pass it to smu_queue_simple or as 'done'
434 * member to smu_queue_cmd, it will call complete() on the struct
435 * completion passed in the "misc" argument
436 */
437extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
438
439/*
440 * Synchronous helpers. Will spin-wait for completion of a command
441 */
442extern void smu_spinwait_cmd(struct smu_cmd *cmd);
443
444static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
445{
446 smu_spinwait_cmd(&scmd->cmd);
447}
448
449/*
450 * Poll routine to call if blocked with irqs off
451 */
452extern void smu_poll(void);
453
454
455/*
456 * Init routine, presence check....
457 */
458extern int smu_init(void);
459extern int smu_present(void);
460struct of_device;
461extern struct of_device *smu_get_ofdev(void);
462
463
464/*
465 * Common command wrappers
466 */
467extern void smu_shutdown(void);
468extern void smu_restart(void);
469struct rtc_time;
470extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
471extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
472
473/*
474 * SMU command buffer absolute address, exported by pmac_setup,
475 * this is allocated very early during boot.
476 */
477extern unsigned long smu_cmdbuf_abs;
478
479
480/*
481 * Kenrel asynchronous i2c interface
482 */
483
484#define SMU_I2C_READ_MAX 0x1d
485#define SMU_I2C_WRITE_MAX 0x15
486
487/* SMU i2c header, exactly matches i2c header on wire */
488struct smu_i2c_param
489{
490 u8 bus; /* SMU bus ID (from device tree) */
491 u8 type; /* i2c transfer type */
492 u8 devaddr; /* device address (includes direction) */
493 u8 sublen; /* subaddress length */
494 u8 subaddr[3]; /* subaddress */
495 u8 caddr; /* combined address, filled by SMU driver */
496 u8 datalen; /* length of transfer */
497 u8 data[SMU_I2C_READ_MAX]; /* data */
498};
499
500struct smu_i2c_cmd
501{
502 /* public */
503 struct smu_i2c_param info;
504 void (*done)(struct smu_i2c_cmd *cmd, void *misc);
505 void *misc;
506 int status; /* 1 = pending, 0 = ok, <0 = fail */
507
508 /* private */
509 struct smu_cmd scmd;
510 int read;
511 int stage;
512 int retries;
513 u8 pdata[32];
514 struct list_head link;
515};
516
517/*
518 * Call this to queue an i2c command to the SMU. You must fill info,
519 * including info.data for a write, done and misc.
520 * For now, no polling interface is provided so you have to use completion
521 * callback.
522 */
523extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
524
525
526#endif /* __KERNEL__ */
527
528
529/*
530 * - SMU "sdb" partitions informations -
531 */
532
533
534/*
535 * Partition header format
536 */
537struct smu_sdbp_header {
538 __u8 id;
539 __u8 len;
540 __u8 version;
541 __u8 flags;
542};
543
544
545 /*
546 * demangle 16 and 32 bits integer in some SMU partitions
547 * (currently, afaik, this concerns only the FVT partition
548 * (0x12)
549 */
550#define SMU_U16_MIX(x) le16_to_cpu(x);
551#define SMU_U32_MIX(x) ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
552
553
554/* This is the definition of the SMU sdb-partition-0x12 table (called
555 * CPU F/V/T operating points in Darwin). The definition for all those
556 * SMU tables should be moved to some separate file
557 */
558#define SMU_SDB_FVT_ID 0x12
559
560struct smu_sdbp_fvt {
561 __u32 sysclk; /* Base SysClk frequency in Hz for
562 * this operating point. Value need to
563 * be unmixed with SMU_U32_MIX()
564 */
565 __u8 pad;
566 __u8 maxtemp; /* Max temp. supported by this
567 * operating point
568 */
569
570 __u16 volts[3]; /* CPU core voltage for the 3
571 * PowerTune modes, a mode with
572 * 0V = not supported. Value need
573 * to be unmixed with SMU_U16_MIX()
574 */
575};
576
577/* This partition contains voltage & current sensor calibration
578 * informations
579 */
580#define SMU_SDB_CPUVCP_ID 0x21
581
582struct smu_sdbp_cpuvcp {
583 __u16 volt_scale; /* u4.12 fixed point */
584 __s16 volt_offset; /* s4.12 fixed point */
585 __u16 curr_scale; /* u4.12 fixed point */
586 __s16 curr_offset; /* s4.12 fixed point */
587 __s32 power_quads[3]; /* s4.28 fixed point */
588};
589
590/* This partition contains CPU thermal diode calibration
591 */
592#define SMU_SDB_CPUDIODE_ID 0x18
593
594struct smu_sdbp_cpudiode {
595 __u16 m_value; /* u1.15 fixed point */
596 __s16 b_value; /* s10.6 fixed point */
597
598};
599
600/* This partition contains Slots power calibration
601 */
602#define SMU_SDB_SLOTSPOW_ID 0x78
603
604struct smu_sdbp_slotspow {
605 __u16 pow_scale; /* u4.12 fixed point */
606 __s16 pow_offset; /* s4.12 fixed point */
607};
608
609/* This partition contains machine specific version information about
610 * the sensor/control layout
611 */
612#define SMU_SDB_SENSORTREE_ID 0x25
613
614struct smu_sdbp_sensortree {
615 __u8 model_id;
616 __u8 unknown[3];
617};
618
619/* This partition contains CPU thermal control PID informations. So far
620 * only single CPU machines have been seen with an SMU, so we assume this
621 * carries only informations for those
622 */
623#define SMU_SDB_CPUPIDDATA_ID 0x17
624
625struct smu_sdbp_cpupiddata {
626 __u8 unknown1;
627 __u8 target_temp_delta;
628 __u8 unknown2;
629 __u8 history_len;
630 __s16 power_adj;
631 __u16 max_power;
632 __s32 gp,gr,gd;
633};
634
635
636/* Other partitions without known structures */
637#define SMU_SDB_DEBUG_SWITCHES_ID 0x05
638
639#ifdef __KERNEL__
640/*
641 * This returns the pointer to an SMU "sdb" partition data or NULL
642 * if not found. The data format is described below
643 */
644extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
645 unsigned int *size);
646
647/* Get "sdb" partition data from an SMU satellite */
648extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
649 int id, unsigned int *size);
650
651
652#endif /* __KERNEL__ */
653
654
655/*
656 * - Userland interface -
657 */
658
659/*
660 * A given instance of the device can be configured for 2 different
661 * things at the moment:
662 *
663 * - sending SMU commands (default at open() time)
664 * - receiving SMU events (not yet implemented)
665 *
666 * Commands are written with write() of a command block. They can be
667 * "driver" commands (for example to switch to event reception mode)
668 * or real SMU commands. They are made of a header followed by command
669 * data if any.
670 *
671 * For SMU commands (not for driver commands), you can then read() back
672 * a reply. The reader will be blocked or not depending on how the device
673 * file is opened. poll() isn't implemented yet. The reply will consist
674 * of a header as well, followed by the reply data if any. You should
675 * always provide a buffer large enough for the maximum reply data, I
676 * recommand one page.
677 *
678 * It is illegal to send SMU commands through a file descriptor configured
679 * for events reception
680 *
681 */
682struct smu_user_cmd_hdr
683{
684 __u32 cmdtype;
685#define SMU_CMDTYPE_SMU 0 /* SMU command */
686#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
687#define SMU_CMDTYPE_GET_PARTITION 2 /* retrieve an sdb partition */
688
689 __u8 cmd; /* SMU command byte */
690 __u8 pad[3]; /* padding */
691 __u32 data_len; /* Length of data following */
692};
693
694struct smu_user_reply_hdr
695{
696 __u32 status; /* Command status */
697 __u32 reply_len; /* Length of data follwing */
698};
699
700#endif /* _SMU_H */
diff --git a/arch/powerpc/include/asm/socket.h b/arch/powerpc/include/asm/socket.h
new file mode 100644
index 000000000000..f5a4e168e498
--- /dev/null
+++ b/arch/powerpc/include/asm/socket.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_SOCKET_H
2#define _ASM_POWERPC_SOCKET_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/sockios.h>
12
13/* For setsockopt(2) */
14#define SOL_SOCKET 1
15
16#define SO_DEBUG 1
17#define SO_REUSEADDR 2
18#define SO_TYPE 3
19#define SO_ERROR 4
20#define SO_DONTROUTE 5
21#define SO_BROADCAST 6
22#define SO_SNDBUF 7
23#define SO_RCVBUF 8
24#define SO_SNDBUFFORCE 32
25#define SO_RCVBUFFORCE 33
26#define SO_KEEPALIVE 9
27#define SO_OOBINLINE 10
28#define SO_NO_CHECK 11
29#define SO_PRIORITY 12
30#define SO_LINGER 13
31#define SO_BSDCOMPAT 14
32/* To add :#define SO_REUSEPORT 15 */
33#define SO_RCVLOWAT 16
34#define SO_SNDLOWAT 17
35#define SO_RCVTIMEO 18
36#define SO_SNDTIMEO 19
37#define SO_PASSCRED 20
38#define SO_PEERCRED 21
39
40/* Security levels - as per NRL IPv6 - don't actually do anything */
41#define SO_SECURITY_AUTHENTICATION 22
42#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
43#define SO_SECURITY_ENCRYPTION_NETWORK 24
44
45#define SO_BINDTODEVICE 25
46
47/* Socket filtering */
48#define SO_ATTACH_FILTER 26
49#define SO_DETACH_FILTER 27
50
51#define SO_PEERNAME 28
52#define SO_TIMESTAMP 29
53#define SCM_TIMESTAMP SO_TIMESTAMP
54
55#define SO_ACCEPTCONN 30
56
57#define SO_PEERSEC 31
58#define SO_PASSSEC 34
59#define SO_TIMESTAMPNS 35
60#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
61
62#define SO_MARK 36
63
64#endif /* _ASM_POWERPC_SOCKET_H */
diff --git a/arch/powerpc/include/asm/sockios.h b/arch/powerpc/include/asm/sockios.h
new file mode 100644
index 000000000000..55cef7675a31
--- /dev/null
+++ b/arch/powerpc/include/asm/sockios.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_SOCKIOS_H
2#define _ASM_POWERPC_SOCKIOS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/* Socket-level I/O control calls. */
12#define FIOSETOWN 0x8901
13#define SIOCSPGRP 0x8902
14#define FIOGETOWN 0x8903
15#define SIOCGPGRP 0x8904
16#define SIOCATMARK 0x8905
17#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
18#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
19
20#endif /* _ASM_POWERPC_SOCKIOS_H */
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
new file mode 100644
index 000000000000..54a47ea2c3aa
--- /dev/null
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -0,0 +1,32 @@
1#ifndef _ASM_POWERPC_SPARSEMEM_H
2#define _ASM_POWERPC_SPARSEMEM_H 1
3#ifdef __KERNEL__
4
5#ifdef CONFIG_SPARSEMEM
6/*
7 * SECTION_SIZE_BITS 2^N: how big each section will be
8 * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
9 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
10 */
11#define SECTION_SIZE_BITS 24
12
13#define MAX_PHYSADDR_BITS 44
14#define MAX_PHYSMEM_BITS 44
15
16#endif /* CONFIG_SPARSEMEM */
17
18#ifdef CONFIG_MEMORY_HOTPLUG
19extern void create_section_mapping(unsigned long start, unsigned long end);
20extern int remove_section_mapping(unsigned long start, unsigned long end);
21#ifdef CONFIG_NUMA
22extern int hot_add_scn_to_nid(unsigned long scn_addr);
23#else
24static inline int hot_add_scn_to_nid(unsigned long scn_addr)
25{
26 return 0;
27}
28#endif /* CONFIG_NUMA */
29#endif /* CONFIG_MEMORY_HOTPLUG */
30
31#endif /* __KERNEL__ */
32#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
new file mode 100644
index 000000000000..f56a843f4705
--- /dev/null
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -0,0 +1,295 @@
1#ifndef __ASM_SPINLOCK_H
2#define __ASM_SPINLOCK_H
3#ifdef __KERNEL__
4
5/*
6 * Simple spin lock operations.
7 *
8 * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
11 * Rework to support virtual processors
12 *
13 * Type of int is used as a full 64b word is not necessary.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 * (the type definitions are in asm/spinlock_types.h)
21 */
22#include <linux/irqflags.h>
23#ifdef CONFIG_PPC64
24#include <asm/paca.h>
25#include <asm/hvcall.h>
26#include <asm/iseries/hv_call.h>
27#endif
28#include <asm/asm-compat.h>
29#include <asm/synch.h>
30
31#define __raw_spin_is_locked(x) ((x)->slock != 0)
32
33#ifdef CONFIG_PPC64
34/* use 0x800000yy when locked, where yy == CPU number */
35#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
36#else
37#define LOCK_TOKEN 1
38#endif
39
40#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
41#define CLEAR_IO_SYNC (get_paca()->io_sync = 0)
42#define SYNC_IO do { \
43 if (unlikely(get_paca()->io_sync)) { \
44 mb(); \
45 get_paca()->io_sync = 0; \
46 } \
47 } while (0)
48#else
49#define CLEAR_IO_SYNC
50#define SYNC_IO
51#endif
52
53/*
54 * This returns the old value in the lock, so we succeeded
55 * in getting the lock if the return value is 0.
56 */
57static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
58{
59 unsigned long tmp, token;
60
61 token = LOCK_TOKEN;
62 __asm__ __volatile__(
63"1: lwarx %0,0,%2\n\
64 cmpwi 0,%0,0\n\
65 bne- 2f\n\
66 stwcx. %1,0,%2\n\
67 bne- 1b\n\
68 isync\n\
692:" : "=&r" (tmp)
70 : "r" (token), "r" (&lock->slock)
71 : "cr0", "memory");
72
73 return tmp;
74}
75
76static inline int __raw_spin_trylock(raw_spinlock_t *lock)
77{
78 CLEAR_IO_SYNC;
79 return __spin_trylock(lock) == 0;
80}
81
82/*
83 * On a system with shared processors (that is, where a physical
84 * processor is multiplexed between several virtual processors),
85 * there is no point spinning on a lock if the holder of the lock
86 * isn't currently scheduled on a physical processor. Instead
87 * we detect this situation and ask the hypervisor to give the
88 * rest of our timeslice to the lock holder.
89 *
90 * So that we can tell which virtual processor is holding a lock,
91 * we put 0x80000000 | smp_processor_id() in the lock when it is
92 * held. Conveniently, we have a word in the paca that holds this
93 * value.
94 */
95
96#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
97/* We only yield to the hypervisor if we are in shared processor mode */
98#define SHARED_PROCESSOR (get_lppaca()->shared_proc)
99extern void __spin_yield(raw_spinlock_t *lock);
100extern void __rw_yield(raw_rwlock_t *lock);
101#else /* SPLPAR || ISERIES */
102#define __spin_yield(x) barrier()
103#define __rw_yield(x) barrier()
104#define SHARED_PROCESSOR 0
105#endif
106
107static inline void __raw_spin_lock(raw_spinlock_t *lock)
108{
109 CLEAR_IO_SYNC;
110 while (1) {
111 if (likely(__spin_trylock(lock) == 0))
112 break;
113 do {
114 HMT_low();
115 if (SHARED_PROCESSOR)
116 __spin_yield(lock);
117 } while (unlikely(lock->slock != 0));
118 HMT_medium();
119 }
120}
121
122static inline
123void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
124{
125 unsigned long flags_dis;
126
127 CLEAR_IO_SYNC;
128 while (1) {
129 if (likely(__spin_trylock(lock) == 0))
130 break;
131 local_save_flags(flags_dis);
132 local_irq_restore(flags);
133 do {
134 HMT_low();
135 if (SHARED_PROCESSOR)
136 __spin_yield(lock);
137 } while (unlikely(lock->slock != 0));
138 HMT_medium();
139 local_irq_restore(flags_dis);
140 }
141}
142
143static inline void __raw_spin_unlock(raw_spinlock_t *lock)
144{
145 SYNC_IO;
146 __asm__ __volatile__("# __raw_spin_unlock\n\t"
147 LWSYNC_ON_SMP: : :"memory");
148 lock->slock = 0;
149}
150
151#ifdef CONFIG_PPC64
152extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
153#else
154#define __raw_spin_unlock_wait(lock) \
155 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
156#endif
157
158/*
159 * Read-write spinlocks, allowing multiple readers
160 * but only one writer.
161 *
162 * NOTE! it is quite common to have readers in interrupts
163 * but no interrupt writers. For those circumstances we
164 * can "mix" irq-safe locks - any writer needs to get a
165 * irq-safe write-lock, but readers can get non-irqsafe
166 * read-locks.
167 */
168
169#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
170#define __raw_write_can_lock(rw) (!(rw)->lock)
171
172#ifdef CONFIG_PPC64
173#define __DO_SIGN_EXTEND "extsw %0,%0\n"
174#define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */
175#else
176#define __DO_SIGN_EXTEND
177#define WRLOCK_TOKEN (-1)
178#endif
179
180/*
181 * This returns the old value in the lock + 1,
182 * so we got a read lock if the return value is > 0.
183 */
184static inline long __read_trylock(raw_rwlock_t *rw)
185{
186 long tmp;
187
188 __asm__ __volatile__(
189"1: lwarx %0,0,%1\n"
190 __DO_SIGN_EXTEND
191" addic. %0,%0,1\n\
192 ble- 2f\n"
193 PPC405_ERR77(0,%1)
194" stwcx. %0,0,%1\n\
195 bne- 1b\n\
196 isync\n\
1972:" : "=&r" (tmp)
198 : "r" (&rw->lock)
199 : "cr0", "xer", "memory");
200
201 return tmp;
202}
203
204/*
205 * This returns the old value in the lock,
206 * so we got the write lock if the return value is 0.
207 */
208static inline long __write_trylock(raw_rwlock_t *rw)
209{
210 long tmp, token;
211
212 token = WRLOCK_TOKEN;
213 __asm__ __volatile__(
214"1: lwarx %0,0,%2\n\
215 cmpwi 0,%0,0\n\
216 bne- 2f\n"
217 PPC405_ERR77(0,%1)
218" stwcx. %1,0,%2\n\
219 bne- 1b\n\
220 isync\n\
2212:" : "=&r" (tmp)
222 : "r" (token), "r" (&rw->lock)
223 : "cr0", "memory");
224
225 return tmp;
226}
227
228static inline void __raw_read_lock(raw_rwlock_t *rw)
229{
230 while (1) {
231 if (likely(__read_trylock(rw) > 0))
232 break;
233 do {
234 HMT_low();
235 if (SHARED_PROCESSOR)
236 __rw_yield(rw);
237 } while (unlikely(rw->lock < 0));
238 HMT_medium();
239 }
240}
241
242static inline void __raw_write_lock(raw_rwlock_t *rw)
243{
244 while (1) {
245 if (likely(__write_trylock(rw) == 0))
246 break;
247 do {
248 HMT_low();
249 if (SHARED_PROCESSOR)
250 __rw_yield(rw);
251 } while (unlikely(rw->lock != 0));
252 HMT_medium();
253 }
254}
255
256static inline int __raw_read_trylock(raw_rwlock_t *rw)
257{
258 return __read_trylock(rw) > 0;
259}
260
261static inline int __raw_write_trylock(raw_rwlock_t *rw)
262{
263 return __write_trylock(rw) == 0;
264}
265
266static inline void __raw_read_unlock(raw_rwlock_t *rw)
267{
268 long tmp;
269
270 __asm__ __volatile__(
271 "# read_unlock\n\t"
272 LWSYNC_ON_SMP
273"1: lwarx %0,0,%1\n\
274 addic %0,%0,-1\n"
275 PPC405_ERR77(0,%1)
276" stwcx. %0,0,%1\n\
277 bne- 1b"
278 : "=&r"(tmp)
279 : "r"(&rw->lock)
280 : "cr0", "memory");
281}
282
283static inline void __raw_write_unlock(raw_rwlock_t *rw)
284{
285 __asm__ __volatile__("# write_unlock\n\t"
286 LWSYNC_ON_SMP: : :"memory");
287 rw->lock = 0;
288}
289
290#define _raw_spin_relax(lock) __spin_yield(lock)
291#define _raw_read_relax(lock) __rw_yield(lock)
292#define _raw_write_relax(lock) __rw_yield(lock)
293
294#endif /* __KERNEL__ */
295#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/powerpc/include/asm/spinlock_types.h b/arch/powerpc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..74236c9f05b1
--- /dev/null
+++ b/arch/powerpc/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
2#define _ASM_POWERPC_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int slock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile signed int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/arch/powerpc/include/asm/spu.h b/arch/powerpc/include/asm/spu.h
new file mode 100644
index 000000000000..8b2eb044270a
--- /dev/null
+++ b/arch/powerpc/include/asm/spu.h
@@ -0,0 +1,732 @@
1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/workqueue.h>
28#include <linux/sysdev.h>
29
30#define LS_SIZE (256 * 1024)
31#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flag indicating progress during context switch. */
102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_FAULT_PENDING 1UL
104
105struct spu_context;
106struct spu_runqueue;
107struct spu_lscsa;
108struct device_node;
109
110enum spu_utilization_state {
111 SPU_UTIL_USER,
112 SPU_UTIL_SYSTEM,
113 SPU_UTIL_IOWAIT,
114 SPU_UTIL_IDLE_LOADED,
115 SPU_UTIL_MAX
116};
117
118struct spu {
119 const char *name;
120 unsigned long local_store_phys;
121 u8 *local_store;
122 unsigned long problem_phys;
123 struct spu_problem __iomem *problem;
124 struct spu_priv2 __iomem *priv2;
125 struct list_head cbe_list;
126 struct list_head full_list;
127 enum { SPU_FREE, SPU_USED } alloc_state;
128 int number;
129 unsigned int irqs[3];
130 u32 node;
131 u64 flags;
132 u64 class_0_pending;
133 u64 class_0_dar;
134 u64 class_1_dar;
135 u64 class_1_dsisr;
136 size_t ls_size;
137 unsigned int slb_replace;
138 struct mm_struct *mm;
139 struct spu_context *ctx;
140 struct spu_runqueue *rq;
141 unsigned long long timestamp;
142 pid_t pid;
143 pid_t tgid;
144 spinlock_t register_lock;
145
146 void (* wbox_callback)(struct spu *spu);
147 void (* ibox_callback)(struct spu *spu);
148 void (* stop_callback)(struct spu *spu, int irq);
149 void (* mfc_callback)(struct spu *spu);
150
151 char irq_c0[8];
152 char irq_c1[8];
153 char irq_c2[8];
154
155 u64 spe_id;
156
157 void* pdata; /* platform private data */
158
159 /* of based platforms only */
160 struct device_node *devnode;
161
162 /* native only */
163 struct spu_priv1 __iomem *priv1;
164
165 /* beat only */
166 u64 shadow_int_mask_RW[3];
167
168 struct sys_device sysdev;
169
170 int has_mem_affinity;
171 struct list_head aff_list;
172
173 struct {
174 /* protected by interrupt reentrancy */
175 enum spu_utilization_state util_state;
176 unsigned long long tstamp;
177 unsigned long long times[SPU_UTIL_MAX];
178 unsigned long long vol_ctx_switch;
179 unsigned long long invol_ctx_switch;
180 unsigned long long min_flt;
181 unsigned long long maj_flt;
182 unsigned long long hash_flt;
183 unsigned long long slb_flt;
184 unsigned long long class2_intr;
185 unsigned long long libassist;
186 } stats;
187};
188
189struct cbe_spu_info {
190 struct mutex list_mutex;
191 struct list_head spus;
192 int n_spus;
193 int nr_active;
194 atomic_t busy_spus;
195 atomic_t reserved_spus;
196};
197
198extern struct cbe_spu_info cbe_spu_info[];
199
200void spu_init_channels(struct spu *spu);
201void spu_irq_setaffinity(struct spu *spu, int cpu);
202
203void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
204 void *code, int code_size);
205
206#ifdef CONFIG_KEXEC
207void crash_register_spus(struct list_head *list);
208#else
209static inline void crash_register_spus(struct list_head *list)
210{
211}
212#endif
213
214extern void spu_invalidate_slbs(struct spu *spu);
215extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
216int spu_64k_pages_available(void);
217
218/* Calls from the memory management to the SPU */
219struct mm_struct;
220extern void spu_flush_all_slbs(struct mm_struct *mm);
221
222/* This interface allows a profiler (e.g., OProfile) to store a ref
223 * to spu context information that it creates. This caching technique
224 * avoids the need to recreate this information after a save/restore operation.
225 *
226 * Assumes the caller has already incremented the ref count to
227 * profile_info; then spu_context_destroy must call kref_put
228 * on prof_info_kref.
229 */
230void spu_set_profile_private_kref(struct spu_context *ctx,
231 struct kref *prof_info_kref,
232 void ( * prof_info_release) (struct kref *kref));
233
234void *spu_get_profile_private_kref(struct spu_context *ctx);
235
236/* system callbacks from the SPU */
237struct spu_syscall_block {
238 u64 nr_ret;
239 u64 parm[6];
240};
241extern long spu_sys_callback(struct spu_syscall_block *s);
242
243/* syscalls implemented in spufs */
244struct file;
245struct spufs_calls {
246 long (*create_thread)(const char __user *name,
247 unsigned int flags, mode_t mode,
248 struct file *neighbor);
249 long (*spu_run)(struct file *filp, __u32 __user *unpc,
250 __u32 __user *ustatus);
251 int (*coredump_extra_notes_size)(void);
252 int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
253 void (*notify_spus_active)(void);
254 struct module *owner;
255};
256
257/* return status from spu_run, same as in libspe */
258#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
259#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
260#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
261#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
262#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
263
264/*
265 * Flags for sys_spu_create.
266 */
267#define SPU_CREATE_EVENTS_ENABLED 0x0001
268#define SPU_CREATE_GANG 0x0002
269#define SPU_CREATE_NOSCHED 0x0004
270#define SPU_CREATE_ISOLATE 0x0008
271#define SPU_CREATE_AFFINITY_SPU 0x0010
272#define SPU_CREATE_AFFINITY_MEM 0x0020
273
274#define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
275
276
277int register_spu_syscalls(struct spufs_calls *calls);
278void unregister_spu_syscalls(struct spufs_calls *calls);
279
280int spu_add_sysdev_attr(struct sysdev_attribute *attr);
281void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
282
283int spu_add_sysdev_attr_group(struct attribute_group *attrs);
284void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
285
286int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
287 unsigned long dsisr, unsigned *flt);
288
289/*
290 * Notifier blocks:
291 *
292 * oprofile can get notified when a context switch is performed
293 * on an spe. The notifer function that gets called is passed
294 * a pointer to the SPU structure as well as the object-id that
295 * identifies the binary running on that SPU now.
296 *
297 * For a context save, the object-id that is passed is zero,
298 * identifying that the kernel will run from that moment on.
299 *
300 * For a context restore, the object-id is the value written
301 * to object-id spufs file from user space and the notifer
302 * function can assume that spu->ctx is valid.
303 */
304struct notifier_block;
305int spu_switch_event_register(struct notifier_block * n);
306int spu_switch_event_unregister(struct notifier_block * n);
307
308extern void notify_spus_active(void);
309extern void do_notify_spus_active(void);
310
311/*
312 * This defines the Local Store, Problem Area and Privilege Area of an SPU.
313 */
314
315union mfc_tag_size_class_cmd {
316 struct {
317 u16 mfc_size;
318 u16 mfc_tag;
319 u8 pad;
320 u8 mfc_rclassid;
321 u16 mfc_cmd;
322 } u;
323 struct {
324 u32 mfc_size_tag32;
325 u32 mfc_class_cmd32;
326 } by32;
327 u64 all64;
328};
329
330struct mfc_cq_sr {
331 u64 mfc_cq_data0_RW;
332 u64 mfc_cq_data1_RW;
333 u64 mfc_cq_data2_RW;
334 u64 mfc_cq_data3_RW;
335};
336
337struct spu_problem {
338#define MS_SYNC_PENDING 1L
339 u64 spc_mssync_RW; /* 0x0000 */
340 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
341
342 /* DMA Area */
343 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
344 u32 mfc_lsa_W; /* 0x3004 */
345 u64 mfc_ea_W; /* 0x3008 */
346 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
347 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
348 u32 dma_qstatus_R; /* 0x3104 */
349 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
350 u32 dma_querytype_RW; /* 0x3204 */
351 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
352 u32 dma_querymask_RW; /* 0x321c */
353 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
354 u32 dma_tagstatus_R; /* 0x322c */
355#define DMA_TAGSTATUS_INTR_ANY 1u
356#define DMA_TAGSTATUS_INTR_ALL 2u
357 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
358
359 /* SPU Control Area */
360 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
361 u32 pu_mb_R; /* 0x4004 */
362 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
363 u32 spu_mb_W; /* 0x400c */
364 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
365 u32 mb_stat_R; /* 0x4014 */
366 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
367 u32 spu_runcntl_RW; /* 0x401c */
368#define SPU_RUNCNTL_STOP 0L
369#define SPU_RUNCNTL_RUNNABLE 1L
370#define SPU_RUNCNTL_ISOLATE 2L
371 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
372 u32 spu_status_R; /* 0x4024 */
373#define SPU_STOP_STATUS_SHIFT 16
374#define SPU_STATUS_STOPPED 0x0
375#define SPU_STATUS_RUNNING 0x1
376#define SPU_STATUS_STOPPED_BY_STOP 0x2
377#define SPU_STATUS_STOPPED_BY_HALT 0x4
378#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
379#define SPU_STATUS_SINGLE_STEP 0x10
380#define SPU_STATUS_INVALID_INSTR 0x20
381#define SPU_STATUS_INVALID_CH 0x40
382#define SPU_STATUS_ISOLATED_STATE 0x80
383#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
384#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
385 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
386 u32 spu_spe_R; /* 0x402c */
387 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
388 u32 spu_npc_RW; /* 0x4034 */
389 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
390
391 /* Signal Notification Area */
392 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
393 u32 signal_notify1; /* 0x1400c */
394 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
395 u32 signal_notify2; /* 0x1c00c */
396} __attribute__ ((aligned(0x20000)));
397
398/* SPU Privilege 2 State Area */
399struct spu_priv2 {
400 /* MFC Registers */
401 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
402
403 /* SLB Management Registers */
404 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
405 u64 slb_index_W; /* 0x1108 */
406#define SLB_INDEX_MASK 0x7L
407 u64 slb_esid_RW; /* 0x1110 */
408 u64 slb_vsid_RW; /* 0x1118 */
409#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
410#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
411#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
412#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
413#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
414#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
415#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
416#define SLB_VSID_4K_PAGE (0x0 << 8)
417#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
418#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
419#define SLB_VSID_CLASS_MASK (0x1ull << 7)
420#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
421 u64 slb_invalidate_entry_W; /* 0x1120 */
422 u64 slb_invalidate_all_W; /* 0x1128 */
423 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
424
425 /* Context Save / Restore Area */
426 struct mfc_cq_sr spuq[16]; /* 0x2000 */
427 struct mfc_cq_sr puq[8]; /* 0x2200 */
428 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
429
430 /* MFC Control */
431 u64 mfc_control_RW; /* 0x3000 */
432#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
433#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
434#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
435#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
436#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
437#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
438#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
439#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
440#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
441#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
442#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
443#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
444#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
445#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
446#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
447#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
448#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
449#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
450#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
451#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
452#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
453#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
454#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
455 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
456
457 /* Interrupt Mailbox */
458 u64 puint_mb_R; /* 0x4000 */
459 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
460
461 /* SPU Control */
462 u64 spu_privcntl_RW; /* 0x4040 */
463#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
464#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
465#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
466#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
467#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
468#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
469#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
470#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
471 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
472 u64 spu_lslr_RW; /* 0x4058 */
473 u64 spu_chnlcntptr_RW; /* 0x4060 */
474 u64 spu_chnlcnt_RW; /* 0x4068 */
475 u64 spu_chnldata_RW; /* 0x4070 */
476 u64 spu_cfg_RW; /* 0x4078 */
477 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
478
479 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
480 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
481 u64 spu_tag_status_query_RW; /* 0x5008 */
482#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
483#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
484 u64 spu_cmd_buf1_RW; /* 0x5010 */
485#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
486#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
487 u64 spu_cmd_buf2_RW; /* 0x5018 */
488#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
489#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
490#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
491 u64 spu_atomic_status_RW; /* 0x5020 */
492} __attribute__ ((aligned(0x20000)));
493
494/* SPU Privilege 1 State Area */
495struct spu_priv1 {
496 /* Control and Configuration Area */
497 u64 mfc_sr1_RW; /* 0x000 */
498#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
499#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
500#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
501#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
502#define MFC_STATE1_RELOCATE_MASK 0x10ull
503#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
504#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
505 u64 mfc_lpid_RW; /* 0x008 */
506 u64 spu_idr_RW; /* 0x010 */
507 u64 mfc_vr_RO; /* 0x018 */
508#define MFC_VERSION_BITS (0xffff << 16)
509#define MFC_REVISION_BITS (0xffff)
510#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
511#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
512 u64 spu_vr_RO; /* 0x020 */
513#define SPU_VERSION_BITS (0xffff << 16)
514#define SPU_REVISION_BITS (0xffff)
515#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
516#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
517 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
518
519 /* Interrupt Area */
520 u64 int_mask_RW[3]; /* 0x100 */
521#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
522#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
523#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
524#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
525#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
526#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
527#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
528#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
529#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
530#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
531#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
532#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
533#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
534 u8 pad_0x118_0x140[0x28]; /* 0x118 */
535 u64 int_stat_RW[3]; /* 0x140 */
536#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
537#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
538#define CLASS0_SPU_ERROR_INTR 0x4L
539#define CLASS0_INTR_MASK 0x7L
540#define CLASS1_SEGMENT_FAULT_INTR 0x1L
541#define CLASS1_STORAGE_FAULT_INTR 0x2L
542#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
543#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
544#define CLASS1_INTR_MASK 0xfL
545#define CLASS2_MAILBOX_INTR 0x1L
546#define CLASS2_SPU_STOP_INTR 0x2L
547#define CLASS2_SPU_HALT_INTR 0x4L
548#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
549#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
550#define CLASS2_INTR_MASK 0x1fL
551 u8 pad_0x158_0x180[0x28]; /* 0x158 */
552 u64 int_route_RW; /* 0x180 */
553
554 /* Interrupt Routing */
555 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
556
557 /* Atomic Unit Control Area */
558 u64 mfc_atomic_flush_RW; /* 0x200 */
559#define mfc_atomic_flush_enable 0x1L
560 u8 pad_0x208_0x280[0x78]; /* 0x208 */
561 u64 resource_allocation_groupID_RW; /* 0x280 */
562 u64 resource_allocation_enable_RW; /* 0x288 */
563 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
564
565 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
566
567 u64 smf_sbi_signal_sel; /* 0x3c8 */
568#define smf_sbi_mask_lsb 56
569#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
570#define smf_sbi_mask (0x301LL << smf_sbi_shift)
571#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
572#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
573#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
574#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
575 u64 smf_ato_signal_sel; /* 0x3d0 */
576#define smf_ato_mask_lsb 35
577#define smf_ato_shift (63 - smf_ato_mask_lsb)
578#define smf_ato_mask (0x3LL << smf_ato_shift)
579#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
580#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
581 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
582
583 /* TLB Management Registers */
584 u64 mfc_sdr_RW; /* 0x400 */
585 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
586 u64 tlb_index_hint_RO; /* 0x500 */
587 u64 tlb_index_W; /* 0x508 */
588 u64 tlb_vpn_RW; /* 0x510 */
589 u64 tlb_rpn_RW; /* 0x518 */
590 u8 pad_0x520_0x540[0x20]; /* 0x520 */
591 u64 tlb_invalidate_entry_W; /* 0x540 */
592 u64 tlb_invalidate_all_W; /* 0x548 */
593 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
594
595 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
596 u64 smm_hid; /* 0x580 */
597#define PAGE_SIZE_MASK 0xf000000000000000ull
598#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
599 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
600
601 /* MFC Status/Control Area */
602 u64 mfc_accr_RW; /* 0x600 */
603#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
604#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
605#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
606#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
607 u8 pad_0x608_0x610[0x8]; /* 0x608 */
608 u64 mfc_dsisr_RW; /* 0x610 */
609#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
610#define MFC_DSISR_ACCESS_DENIED (1 << 27)
611#define MFC_DSISR_ATOMIC (1 << 26)
612#define MFC_DSISR_ACCESS_PUT (1 << 25)
613#define MFC_DSISR_ADDR_MATCH (1 << 22)
614#define MFC_DSISR_LS (1 << 17)
615#define MFC_DSISR_L (1 << 16)
616#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
617 u8 pad_0x618_0x620[0x8]; /* 0x618 */
618 u64 mfc_dar_RW; /* 0x620 */
619 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
620
621 /* Replacement Management Table (RMT) Area */
622 u64 rmt_index_RW; /* 0x700 */
623 u8 pad_0x708_0x710[0x8]; /* 0x708 */
624 u64 rmt_data1_RW; /* 0x710 */
625 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
626
627 /* Control/Configuration Registers */
628 u64 mfc_dsir_R; /* 0x800 */
629#define MFC_DSIR_Q (1 << 31)
630#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
631 u64 mfc_lsacr_RW; /* 0x808 */
632#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
633#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
634 u64 mfc_lscrr_R; /* 0x810 */
635#define MFC_LSCRR_Q (1 << 31)
636#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
637#define MFC_LSCRR_QI_SHIFT 32
638#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
639 u8 pad_0x818_0x820[0x8]; /* 0x818 */
640 u64 mfc_tclass_id_RW; /* 0x820 */
641#define MFC_TCLASS_ID_ENABLE (1L << 0L)
642#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
643#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
644#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
645#define MFC_TCLASS_QUOTA_2_SHIFT 8L
646#define MFC_TCLASS_QUOTA_1_SHIFT 16L
647#define MFC_TCLASS_QUOTA_0_SHIFT 24L
648#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
649#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
650#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
651 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
652
653 /* Real Mode Support Registers */
654 u64 mfc_rm_boundary; /* 0x900 */
655 u8 pad_0x908_0x938[0x30]; /* 0x908 */
656 u64 smf_dma_signal_sel; /* 0x938 */
657#define mfc_dma1_mask_lsb 41
658#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
659#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
660#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
661#define mfc_dma2_mask_lsb 43
662#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
663#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
664#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
665 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
666 u64 smm_signal_sel; /* 0xa38 */
667#define smm_sig_mask_lsb 12
668#define smm_sig_shift (63 - smm_sig_mask_lsb)
669#define smm_sig_mask (0x3LL << smm_sig_shift)
670#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
671#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
672 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
673
674 /* DMA Command Error Area */
675 u64 mfc_cer_R; /* 0xc00 */
676#define MFC_CER_Q (1 << 31)
677#define MFC_CER_SPU_QUEUE MFC_CER_Q
678 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
679
680 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
681 /* DMA Command Error Area */
682 u64 spu_ecc_cntl_RW; /* 0x1000 */
683#define SPU_ECC_CNTL_E (1ull << 0ull)
684#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
685#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
686#define SPU_ECC_CNTL_S (1ull << 1ull)
687#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
688#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
689#define SPU_ECC_CNTL_B (1ull << 2ull)
690#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
691#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
692#define SPU_ECC_CNTL_I_SHIFT 3ull
693#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
694#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
695#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
696#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
697#define SPU_ECC_CNTL_D (1ull << 5ull)
698#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
699#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
700 u64 spu_ecc_stat_RW; /* 0x1008 */
701#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
702#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
703#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
704#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
705#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
706#define SPU_ECC_DATA_ERROR (1ull << 5ul)
707#define SPU_ECC_DMA_ERROR (1ull << 6ul)
708#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
709 u64 spu_ecc_addr_RW; /* 0x1010 */
710 u64 spu_err_mask_RW; /* 0x1018 */
711#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
712#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
713 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
714
715 /* SPU Debug-Trace Bus (DTB) Selection Registers */
716 u64 spu_trig0_sel; /* 0x1028 */
717 u64 spu_trig1_sel; /* 0x1030 */
718 u64 spu_trig2_sel; /* 0x1038 */
719 u64 spu_trig3_sel; /* 0x1040 */
720 u64 spu_trace_sel; /* 0x1048 */
721#define spu_trace_sel_mask 0x1f1fLL
722#define spu_trace_sel_bus0_bits 0x1000LL
723#define spu_trace_sel_bus2_bits 0x0010LL
724 u64 spu_event0_sel; /* 0x1050 */
725 u64 spu_event1_sel; /* 0x1058 */
726 u64 spu_event2_sel; /* 0x1060 */
727 u64 spu_event3_sel; /* 0x1068 */
728 u64 spu_trace_cntl; /* 0x1070 */
729} __attribute__ ((aligned(0x2000)));
730
731#endif /* __KERNEL__ */
732#endif
diff --git a/arch/powerpc/include/asm/spu_csa.h b/arch/powerpc/include/asm/spu_csa.h
new file mode 100644
index 000000000000..a40fd491250c
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_csa.h
@@ -0,0 +1,266 @@
1/*
2 * spu_csa.h: Definitions for SPU context save area (CSA).
3 *
4 * (C) Copyright IBM 2005
5 *
6 * Author: Mark Nutter <mnutter@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_CSA_H_
24#define _SPU_CSA_H_
25#ifdef __KERNEL__
26
27/*
28 * Total number of 128-bit registers.
29 */
30#define NR_SPU_GPRS 128
31#define NR_SPU_SPRS 9
32#define NR_SPU_REGS_PAD 7
33#define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */
34#define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16
35
36#define SPU_SAVE_COMPLETE 0x3FFB
37#define SPU_RESTORE_COMPLETE 0x3FFC
38
39/*
40 * Definitions for various 'stopped' status conditions,
41 * to be recreated during context restore.
42 */
43#define SPU_STOPPED_STATUS_P 1
44#define SPU_STOPPED_STATUS_I 2
45#define SPU_STOPPED_STATUS_H 3
46#define SPU_STOPPED_STATUS_S 4
47#define SPU_STOPPED_STATUS_S_I 5
48#define SPU_STOPPED_STATUS_S_P 6
49#define SPU_STOPPED_STATUS_P_H 7
50#define SPU_STOPPED_STATUS_P_I 8
51#define SPU_STOPPED_STATUS_R 9
52
53/*
54 * Definitions for software decrementer status flag.
55 */
56#define SPU_DECR_STATUS_RUNNING 0x1
57#define SPU_DECR_STATUS_WRAPPED 0x2
58
59#ifndef __ASSEMBLY__
60/**
61 * spu_reg128 - generic 128-bit register definition.
62 */
63struct spu_reg128 {
64 u32 slot[4];
65};
66
67/**
68 * struct spu_lscsa - Local Store Context Save Area.
69 * @gprs: Array of saved registers.
70 * @fpcr: Saved floating point status control register.
71 * @decr: Saved decrementer value.
72 * @decr_status: Indicates software decrementer status flags.
73 * @ppu_mb: Saved PPU mailbox data.
74 * @ppuint_mb: Saved PPU interrupting mailbox data.
75 * @tag_mask: Saved tag group mask.
76 * @event_mask: Saved event mask.
77 * @srr0: Saved SRR0.
78 * @stopped_status: Conditions to be recreated by restore.
79 * @ls: Saved contents of Local Storage Area.
80 *
81 * The LSCSA represents state that is primarily saved and
82 * restored by SPU-side code.
83 */
84struct spu_lscsa {
85 struct spu_reg128 gprs[128];
86 struct spu_reg128 fpcr;
87 struct spu_reg128 decr;
88 struct spu_reg128 decr_status;
89 struct spu_reg128 ppu_mb;
90 struct spu_reg128 ppuint_mb;
91 struct spu_reg128 tag_mask;
92 struct spu_reg128 event_mask;
93 struct spu_reg128 srr0;
94 struct spu_reg128 stopped_status;
95
96 /*
97 * 'ls' must be page-aligned on all configurations.
98 * Since we don't want to rely on having the spu-gcc
99 * installed to build the kernel and this structure
100 * is used in the SPU-side code, make it 64k-page
101 * aligned for now.
102 */
103 unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
104};
105
106#ifndef __SPU__
107/*
108 * struct spu_problem_collapsed - condensed problem state area, w/o pads.
109 */
110struct spu_problem_collapsed {
111 u64 spc_mssync_RW;
112 u32 mfc_lsa_W;
113 u32 unused_pad0;
114 u64 mfc_ea_W;
115 union mfc_tag_size_class_cmd mfc_union_W;
116 u32 dma_qstatus_R;
117 u32 dma_querytype_RW;
118 u32 dma_querymask_RW;
119 u32 dma_tagstatus_R;
120 u32 pu_mb_R;
121 u32 spu_mb_W;
122 u32 mb_stat_R;
123 u32 spu_runcntl_RW;
124 u32 spu_status_R;
125 u32 spu_spc_R;
126 u32 spu_npc_RW;
127 u32 signal_notify1;
128 u32 signal_notify2;
129 u32 unused_pad1;
130};
131
132/*
133 * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
134 */
135struct spu_priv1_collapsed {
136 u64 mfc_sr1_RW;
137 u64 mfc_lpid_RW;
138 u64 spu_idr_RW;
139 u64 mfc_vr_RO;
140 u64 spu_vr_RO;
141 u64 int_mask_class0_RW;
142 u64 int_mask_class1_RW;
143 u64 int_mask_class2_RW;
144 u64 int_stat_class0_RW;
145 u64 int_stat_class1_RW;
146 u64 int_stat_class2_RW;
147 u64 int_route_RW;
148 u64 mfc_atomic_flush_RW;
149 u64 resource_allocation_groupID_RW;
150 u64 resource_allocation_enable_RW;
151 u64 mfc_fir_R;
152 u64 mfc_fir_status_or_W;
153 u64 mfc_fir_status_and_W;
154 u64 mfc_fir_mask_R;
155 u64 mfc_fir_mask_or_W;
156 u64 mfc_fir_mask_and_W;
157 u64 mfc_fir_chkstp_enable_RW;
158 u64 smf_sbi_signal_sel;
159 u64 smf_ato_signal_sel;
160 u64 tlb_index_hint_RO;
161 u64 tlb_index_W;
162 u64 tlb_vpn_RW;
163 u64 tlb_rpn_RW;
164 u64 tlb_invalidate_entry_W;
165 u64 tlb_invalidate_all_W;
166 u64 smm_hid;
167 u64 mfc_accr_RW;
168 u64 mfc_dsisr_RW;
169 u64 mfc_dar_RW;
170 u64 rmt_index_RW;
171 u64 rmt_data1_RW;
172 u64 mfc_dsir_R;
173 u64 mfc_lsacr_RW;
174 u64 mfc_lscrr_R;
175 u64 mfc_tclass_id_RW;
176 u64 mfc_rm_boundary;
177 u64 smf_dma_signal_sel;
178 u64 smm_signal_sel;
179 u64 mfc_cer_R;
180 u64 pu_ecc_cntl_RW;
181 u64 pu_ecc_stat_RW;
182 u64 spu_ecc_addr_RW;
183 u64 spu_err_mask_RW;
184 u64 spu_trig0_sel;
185 u64 spu_trig1_sel;
186 u64 spu_trig2_sel;
187 u64 spu_trig3_sel;
188 u64 spu_trace_sel;
189 u64 spu_event0_sel;
190 u64 spu_event1_sel;
191 u64 spu_event2_sel;
192 u64 spu_event3_sel;
193 u64 spu_trace_cntl;
194};
195
196/*
197 * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
198 */
199struct spu_priv2_collapsed {
200 u64 slb_index_W;
201 u64 slb_esid_RW;
202 u64 slb_vsid_RW;
203 u64 slb_invalidate_entry_W;
204 u64 slb_invalidate_all_W;
205 struct mfc_cq_sr spuq[16];
206 struct mfc_cq_sr puq[8];
207 u64 mfc_control_RW;
208 u64 puint_mb_R;
209 u64 spu_privcntl_RW;
210 u64 spu_lslr_RW;
211 u64 spu_chnlcntptr_RW;
212 u64 spu_chnlcnt_RW;
213 u64 spu_chnldata_RW;
214 u64 spu_cfg_RW;
215 u64 spu_tag_status_query_RW;
216 u64 spu_cmd_buf1_RW;
217 u64 spu_cmd_buf2_RW;
218 u64 spu_atomic_status_RW;
219};
220
221/**
222 * struct spu_state
223 * @lscsa: Local Store Context Save Area.
224 * @prob: Collapsed Problem State Area, w/o pads.
225 * @priv1: Collapsed Privileged 1 Area, w/o pads.
226 * @priv2: Collapsed Privileged 2 Area, w/o pads.
227 * @spu_chnlcnt_RW: Array of saved channel counts.
228 * @spu_chnldata_RW: Array of saved channel data.
229 * @suspend_time: Time stamp when decrementer disabled.
230 *
231 * Structure representing the whole of the SPU
232 * context save area (CSA). This struct contains
233 * all of the state necessary to suspend and then
234 * later optionally resume execution of an SPU
235 * context.
236 *
237 * The @lscsa region is by far the largest, and is
238 * allocated separately so that it may either be
239 * pinned or mapped to/from application memory, as
240 * appropriate for the OS environment.
241 */
242struct spu_state {
243 struct spu_lscsa *lscsa;
244#ifdef CONFIG_SPU_FS_64K_LS
245 int use_big_pages;
246 /* One struct page per 64k page */
247#define SPU_LSCSA_NUM_BIG_PAGES (sizeof(struct spu_lscsa) / 0x10000)
248 struct page *lscsa_pages[SPU_LSCSA_NUM_BIG_PAGES];
249#endif
250 struct spu_problem_collapsed prob;
251 struct spu_priv1_collapsed priv1;
252 struct spu_priv2_collapsed priv2;
253 u64 spu_chnlcnt_RW[32];
254 u64 spu_chnldata_RW[32];
255 u32 spu_mailbox_data[4];
256 u32 pu_mailbox_data[1];
257 u64 class_0_dar, class_0_pending;
258 u64 class_1_dar, class_1_dsisr;
259 unsigned long suspend_time;
260 spinlock_t register_lock;
261};
262
263#endif /* !__SPU__ */
264#endif /* __KERNEL__ */
265#endif /* !__ASSEMBLY__ */
266#endif /* _SPU_CSA_H_ */
diff --git a/arch/powerpc/include/asm/spu_info.h b/arch/powerpc/include/asm/spu_info.h
new file mode 100644
index 000000000000..3545efbf9891
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_info.h
@@ -0,0 +1,54 @@
1/*
2 * SPU info structures
3 *
4 * (C) Copyright 2006 IBM Corp.
5 *
6 * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_INFO_H
24#define _SPU_INFO_H
25
26#ifdef __KERNEL__
27#include <asm/spu.h>
28#include <linux/types.h>
29#else
30struct mfc_cq_sr {
31 __u64 mfc_cq_data0_RW;
32 __u64 mfc_cq_data1_RW;
33 __u64 mfc_cq_data2_RW;
34 __u64 mfc_cq_data3_RW;
35};
36#endif /* __KERNEL__ */
37
38struct spu_dma_info {
39 __u64 dma_info_type;
40 __u64 dma_info_mask;
41 __u64 dma_info_status;
42 __u64 dma_info_stall_and_notify;
43 __u64 dma_info_atomic_command_status;
44 struct mfc_cq_sr dma_info_command_data[16];
45};
46
47struct spu_proxydma_info {
48 __u64 proxydma_info_type;
49 __u64 proxydma_info_mask;
50 __u64 proxydma_info_status;
51 struct mfc_cq_sr proxydma_info_command_data[8];
52};
53
54#endif
diff --git a/arch/powerpc/include/asm/spu_priv1.h b/arch/powerpc/include/asm/spu_priv1.h
new file mode 100644
index 000000000000..25020a34ce7f
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_priv1.h
@@ -0,0 +1,236 @@
1/*
2 * Defines an spu hypervisor abstraction layer.
3 *
4 * Copyright 2006 Sony Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(_SPU_PRIV1_H)
21#define _SPU_PRIV1_H
22#if defined(__KERNEL__)
23
24#include <linux/types.h>
25
26struct spu;
27struct spu_context;
28
29/* access to priv1 registers */
30
31struct spu_priv1_ops {
32 void (*int_mask_and) (struct spu *spu, int class, u64 mask);
33 void (*int_mask_or) (struct spu *spu, int class, u64 mask);
34 void (*int_mask_set) (struct spu *spu, int class, u64 mask);
35 u64 (*int_mask_get) (struct spu *spu, int class);
36 void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
37 u64 (*int_stat_get) (struct spu *spu, int class);
38 void (*cpu_affinity_set) (struct spu *spu, int cpu);
39 u64 (*mfc_dar_get) (struct spu *spu);
40 u64 (*mfc_dsisr_get) (struct spu *spu);
41 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
42 void (*mfc_sdr_setup) (struct spu *spu);
43 void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
44 u64 (*mfc_sr1_get) (struct spu *spu);
45 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
46 u64 (*mfc_tclass_id_get) (struct spu *spu);
47 void (*tlb_invalidate) (struct spu *spu);
48 void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
49 u64 (*resource_allocation_groupID_get) (struct spu *spu);
50 void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
51 u64 (*resource_allocation_enable_get) (struct spu *spu);
52};
53
54extern const struct spu_priv1_ops* spu_priv1_ops;
55
56static inline void
57spu_int_mask_and (struct spu *spu, int class, u64 mask)
58{
59 spu_priv1_ops->int_mask_and(spu, class, mask);
60}
61
62static inline void
63spu_int_mask_or (struct spu *spu, int class, u64 mask)
64{
65 spu_priv1_ops->int_mask_or(spu, class, mask);
66}
67
68static inline void
69spu_int_mask_set (struct spu *spu, int class, u64 mask)
70{
71 spu_priv1_ops->int_mask_set(spu, class, mask);
72}
73
74static inline u64
75spu_int_mask_get (struct spu *spu, int class)
76{
77 return spu_priv1_ops->int_mask_get(spu, class);
78}
79
80static inline void
81spu_int_stat_clear (struct spu *spu, int class, u64 stat)
82{
83 spu_priv1_ops->int_stat_clear(spu, class, stat);
84}
85
86static inline u64
87spu_int_stat_get (struct spu *spu, int class)
88{
89 return spu_priv1_ops->int_stat_get (spu, class);
90}
91
92static inline void
93spu_cpu_affinity_set (struct spu *spu, int cpu)
94{
95 spu_priv1_ops->cpu_affinity_set(spu, cpu);
96}
97
98static inline u64
99spu_mfc_dar_get (struct spu *spu)
100{
101 return spu_priv1_ops->mfc_dar_get(spu);
102}
103
104static inline u64
105spu_mfc_dsisr_get (struct spu *spu)
106{
107 return spu_priv1_ops->mfc_dsisr_get(spu);
108}
109
110static inline void
111spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
112{
113 spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
114}
115
116static inline void
117spu_mfc_sdr_setup (struct spu *spu)
118{
119 spu_priv1_ops->mfc_sdr_setup(spu);
120}
121
122static inline void
123spu_mfc_sr1_set (struct spu *spu, u64 sr1)
124{
125 spu_priv1_ops->mfc_sr1_set(spu, sr1);
126}
127
128static inline u64
129spu_mfc_sr1_get (struct spu *spu)
130{
131 return spu_priv1_ops->mfc_sr1_get(spu);
132}
133
134static inline void
135spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
136{
137 spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
138}
139
140static inline u64
141spu_mfc_tclass_id_get (struct spu *spu)
142{
143 return spu_priv1_ops->mfc_tclass_id_get(spu);
144}
145
146static inline void
147spu_tlb_invalidate (struct spu *spu)
148{
149 spu_priv1_ops->tlb_invalidate(spu);
150}
151
152static inline void
153spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
154{
155 spu_priv1_ops->resource_allocation_groupID_set(spu, id);
156}
157
158static inline u64
159spu_resource_allocation_groupID_get (struct spu *spu)
160{
161 return spu_priv1_ops->resource_allocation_groupID_get(spu);
162}
163
164static inline void
165spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
166{
167 spu_priv1_ops->resource_allocation_enable_set(spu, enable);
168}
169
170static inline u64
171spu_resource_allocation_enable_get (struct spu *spu)
172{
173 return spu_priv1_ops->resource_allocation_enable_get(spu);
174}
175
176/* spu management abstraction */
177
178struct spu_management_ops {
179 int (*enumerate_spus)(int (*fn)(void *data));
180 int (*create_spu)(struct spu *spu, void *data);
181 int (*destroy_spu)(struct spu *spu);
182 void (*enable_spu)(struct spu_context *ctx);
183 void (*disable_spu)(struct spu_context *ctx);
184 int (*init_affinity)(void);
185};
186
187extern const struct spu_management_ops* spu_management_ops;
188
189static inline int
190spu_enumerate_spus (int (*fn)(void *data))
191{
192 return spu_management_ops->enumerate_spus(fn);
193}
194
195static inline int
196spu_create_spu (struct spu *spu, void *data)
197{
198 return spu_management_ops->create_spu(spu, data);
199}
200
201static inline int
202spu_destroy_spu (struct spu *spu)
203{
204 return spu_management_ops->destroy_spu(spu);
205}
206
207static inline int
208spu_init_affinity (void)
209{
210 return spu_management_ops->init_affinity();
211}
212
213static inline void
214spu_enable_spu (struct spu_context *ctx)
215{
216 spu_management_ops->enable_spu(ctx);
217}
218
219static inline void
220spu_disable_spu (struct spu_context *ctx)
221{
222 spu_management_ops->disable_spu(ctx);
223}
224
225/*
226 * The declarations folowing are put here for convenience
227 * and only intended to be used by the platform setup code.
228 */
229
230extern const struct spu_priv1_ops spu_priv1_mmio_ops;
231extern const struct spu_priv1_ops spu_priv1_beat_ops;
232
233extern const struct spu_management_ops spu_management_of_ops;
234
235#endif /* __KERNEL__ */
236#endif
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
new file mode 100644
index 000000000000..f593b0f9b627
--- /dev/null
+++ b/arch/powerpc/include/asm/sstep.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10struct pt_regs;
11
12/*
13 * We don't allow single-stepping an mtmsrd that would clear
14 * MSR_RI, since that would make the exception unrecoverable.
15 * Since we need to single-step to proceed from a breakpoint,
16 * we don't allow putting a breakpoint on an mtmsrd instruction.
17 * Similarly we don't allow breakpoints on rfid instructions.
18 * These macros tell us if an instruction is a mtmsrd or rfid.
19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
20 * and an mtmsrd (64-bit).
21 */
22#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
23#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
24#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
25
26/* Emulate instructions that cause a transfer of control. */
27extern int emulate_step(struct pt_regs *regs, unsigned int instr);
diff --git a/arch/powerpc/include/asm/stat.h b/arch/powerpc/include/asm/stat.h
new file mode 100644
index 000000000000..e4edc510b530
--- /dev/null
+++ b/arch/powerpc/include/asm/stat.h
@@ -0,0 +1,81 @@
1#ifndef _ASM_POWERPC_STAT_H
2#define _ASM_POWERPC_STAT_H
3/*
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/types.h>
10
11#define STAT_HAVE_NSEC 1
12
13#ifndef __powerpc64__
14struct __old_kernel_stat {
15 unsigned short st_dev;
16 unsigned short st_ino;
17 unsigned short st_mode;
18 unsigned short st_nlink;
19 unsigned short st_uid;
20 unsigned short st_gid;
21 unsigned short st_rdev;
22 unsigned long st_size;
23 unsigned long st_atime;
24 unsigned long st_mtime;
25 unsigned long st_ctime;
26};
27#endif /* !__powerpc64__ */
28
29struct stat {
30 unsigned long st_dev;
31 ino_t st_ino;
32#ifdef __powerpc64__
33 nlink_t st_nlink;
34 mode_t st_mode;
35#else
36 mode_t st_mode;
37 nlink_t st_nlink;
38#endif
39 uid_t st_uid;
40 gid_t st_gid;
41 unsigned long st_rdev;
42 off_t st_size;
43 unsigned long st_blksize;
44 unsigned long st_blocks;
45 unsigned long st_atime;
46 unsigned long st_atime_nsec;
47 unsigned long st_mtime;
48 unsigned long st_mtime_nsec;
49 unsigned long st_ctime;
50 unsigned long st_ctime_nsec;
51 unsigned long __unused4;
52 unsigned long __unused5;
53#ifdef __powerpc64__
54 unsigned long __unused6;
55#endif
56};
57
58/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
59struct stat64 {
60 unsigned long long st_dev; /* Device. */
61 unsigned long long st_ino; /* File serial number. */
62 unsigned int st_mode; /* File mode. */
63 unsigned int st_nlink; /* Link count. */
64 unsigned int st_uid; /* User ID of the file's owner. */
65 unsigned int st_gid; /* Group ID of the file's group. */
66 unsigned long long st_rdev; /* Device number, if device. */
67 unsigned short __pad2;
68 long long st_size; /* Size of file, in bytes. */
69 int st_blksize; /* Optimal block size for I/O. */
70 long long st_blocks; /* Number 512-byte blocks allocated. */
71 int st_atime; /* Time of last access. */
72 unsigned int st_atime_nsec;
73 int st_mtime; /* Time of last modification. */
74 unsigned int st_mtime_nsec;
75 int st_ctime; /* Time of last status change. */
76 unsigned int st_ctime_nsec;
77 unsigned int __unused4;
78 unsigned int __unused5;
79};
80
81#endif /* _ASM_POWERPC_STAT_H */
diff --git a/arch/powerpc/include/asm/statfs.h b/arch/powerpc/include/asm/statfs.h
new file mode 100644
index 000000000000..67024026c10d
--- /dev/null
+++ b/arch/powerpc/include/asm/statfs.h
@@ -0,0 +1,60 @@
1#ifndef _ASM_POWERPC_STATFS_H
2#define _ASM_POWERPC_STATFS_H
3
4/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
5
6#ifndef __powerpc64__
7#include <asm-generic/statfs.h>
8#else
9
10#ifndef __KERNEL_STRICT_NAMES
11#include <linux/types.h>
12typedef __kernel_fsid_t fsid_t;
13#endif
14
15/*
16 * We're already 64-bit, so duplicate the definition
17 */
18struct statfs {
19 long f_type;
20 long f_bsize;
21 long f_blocks;
22 long f_bfree;
23 long f_bavail;
24 long f_files;
25 long f_ffree;
26 __kernel_fsid_t f_fsid;
27 long f_namelen;
28 long f_frsize;
29 long f_spare[5];
30};
31
32struct statfs64 {
33 long f_type;
34 long f_bsize;
35 long f_blocks;
36 long f_bfree;
37 long f_bavail;
38 long f_files;
39 long f_ffree;
40 __kernel_fsid_t f_fsid;
41 long f_namelen;
42 long f_frsize;
43 long f_spare[5];
44};
45
46struct compat_statfs64 {
47 __u32 f_type;
48 __u32 f_bsize;
49 __u64 f_blocks;
50 __u64 f_bfree;
51 __u64 f_bavail;
52 __u64 f_files;
53 __u64 f_ffree;
54 __kernel_fsid_t f_fsid;
55 __u32 f_namelen;
56 __u32 f_frsize;
57 __u32 f_spare[5];
58};
59#endif /* ! __powerpc64__ */
60#endif
diff --git a/arch/powerpc/include/asm/string.h b/arch/powerpc/include/asm/string.h
new file mode 100644
index 000000000000..e40010abcaf1
--- /dev/null
+++ b/arch/powerpc/include/asm/string.h
@@ -0,0 +1,32 @@
1#ifndef _ASM_POWERPC_STRING_H
2#define _ASM_POWERPC_STRING_H
3
4#ifdef __KERNEL__
5
6#define __HAVE_ARCH_STRCPY
7#define __HAVE_ARCH_STRNCPY
8#define __HAVE_ARCH_STRLEN
9#define __HAVE_ARCH_STRCMP
10#define __HAVE_ARCH_STRNCMP
11#define __HAVE_ARCH_STRCAT
12#define __HAVE_ARCH_MEMSET
13#define __HAVE_ARCH_MEMCPY
14#define __HAVE_ARCH_MEMMOVE
15#define __HAVE_ARCH_MEMCMP
16#define __HAVE_ARCH_MEMCHR
17
18extern char * strcpy(char *,const char *);
19extern char * strncpy(char *,const char *, __kernel_size_t);
20extern __kernel_size_t strlen(const char *);
21extern int strcmp(const char *,const char *);
22extern int strncmp(const char *, const char *, __kernel_size_t);
23extern char * strcat(char *, const char *);
24extern void * memset(void *,int,__kernel_size_t);
25extern void * memcpy(void *,const void *,__kernel_size_t);
26extern void * memmove(void *,const void *,__kernel_size_t);
27extern int memcmp(const void *,const void *,__kernel_size_t);
28extern void * memchr(const void *,int,__kernel_size_t);
29
30#endif /* __KERNEL__ */
31
32#endif /* _ASM_POWERPC_STRING_H */
diff --git a/arch/powerpc/include/asm/suspend.h b/arch/powerpc/include/asm/suspend.h
new file mode 100644
index 000000000000..cbf2c9404c37
--- /dev/null
+++ b/arch/powerpc/include/asm/suspend.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_POWERPC_SUSPEND_H
2#define __ASM_POWERPC_SUSPEND_H
3
4static inline int arch_prepare_suspend(void) { return 0; }
5
6void save_processor_state(void);
7void restore_processor_state(void);
8
9#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
new file mode 100644
index 000000000000..45963e80f557
--- /dev/null
+++ b/arch/powerpc/include/asm/synch.h
@@ -0,0 +1,44 @@
1#ifndef _ASM_POWERPC_SYNCH_H
2#define _ASM_POWERPC_SYNCH_H
3#ifdef __KERNEL__
4
5#include <linux/stringify.h>
6#include <asm/feature-fixups.h>
7
8#ifndef __ASSEMBLY__
9extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
10extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
11 void *fixup_end);
12
13static inline void eieio(void)
14{
15 __asm__ __volatile__ ("eieio" : : : "memory");
16}
17
18static inline void isync(void)
19{
20 __asm__ __volatile__ ("isync" : : : "memory");
21}
22#endif /* __ASSEMBLY__ */
23
24#if defined(__powerpc64__)
25# define LWSYNC lwsync
26#elif defined(CONFIG_E500)
27# define LWSYNC \
28 START_LWSYNC_SECTION(96); \
29 sync; \
30 MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
31#else
32# define LWSYNC sync
33#endif
34
35#ifdef CONFIG_SMP
36#define ISYNC_ON_SMP "\n\tisync\n"
37#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n"
38#else
39#define ISYNC_ON_SMP
40#define LWSYNC_ON_SMP
41#endif
42
43#endif /* __KERNEL__ */
44#endif /* _ASM_POWERPC_SYNCH_H */
diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h
new file mode 100644
index 000000000000..efa7f0b879f3
--- /dev/null
+++ b/arch/powerpc/include/asm/syscall.h
@@ -0,0 +1,84 @@
1/*
2 * Access to user system call parameters and results
3 *
4 * Copyright (C) 2008 Red Hat, Inc. All rights reserved.
5 *
6 * This copyrighted material is made available to anyone wishing to use,
7 * modify, copy, or redistribute it subject to the terms and conditions
8 * of the GNU General Public License v.2.
9 *
10 * See asm-generic/syscall.h for descriptions of what we must do here.
11 */
12
13#ifndef _ASM_SYSCALL_H
14#define _ASM_SYSCALL_H 1
15
16#include <linux/sched.h>
17
18static inline long syscall_get_nr(struct task_struct *task,
19 struct pt_regs *regs)
20{
21 return TRAP(regs) == 0xc00 ? regs->gpr[0] : -1L;
22}
23
24static inline void syscall_rollback(struct task_struct *task,
25 struct pt_regs *regs)
26{
27 regs->gpr[3] = regs->orig_gpr3;
28}
29
30static inline long syscall_get_error(struct task_struct *task,
31 struct pt_regs *regs)
32{
33 return (regs->ccr & 0x1000) ? -regs->gpr[3] : 0;
34}
35
36static inline long syscall_get_return_value(struct task_struct *task,
37 struct pt_regs *regs)
38{
39 return regs->gpr[3];
40}
41
42static inline void syscall_set_return_value(struct task_struct *task,
43 struct pt_regs *regs,
44 int error, long val)
45{
46 if (error) {
47 regs->ccr |= 0x1000L;
48 regs->gpr[3] = -error;
49 } else {
50 regs->ccr &= ~0x1000L;
51 regs->gpr[3] = val;
52 }
53}
54
55static inline void syscall_get_arguments(struct task_struct *task,
56 struct pt_regs *regs,
57 unsigned int i, unsigned int n,
58 unsigned long *args)
59{
60 BUG_ON(i + n > 6);
61#ifdef CONFIG_PPC64
62 if (test_tsk_thread_flag(task, TIF_32BIT)) {
63 /*
64 * Zero-extend 32-bit argument values. The high bits are
65 * garbage ignored by the actual syscall dispatch.
66 */
67 while (n-- > 0)
68 args[n] = (u32) regs->gpr[3 + i + n];
69 return;
70 }
71#endif
72 memcpy(args, &regs->gpr[3 + i], n * sizeof(args[0]));
73}
74
75static inline void syscall_set_arguments(struct task_struct *task,
76 struct pt_regs *regs,
77 unsigned int i, unsigned int n,
78 const unsigned long *args)
79{
80 BUG_ON(i + n > 6);
81 memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));
82}
83
84#endif /* _ASM_SYSCALL_H */
diff --git a/arch/powerpc/include/asm/syscalls.h b/arch/powerpc/include/asm/syscalls.h
new file mode 100644
index 000000000000..eb8eb400c664
--- /dev/null
+++ b/arch/powerpc/include/asm/syscalls.h
@@ -0,0 +1,52 @@
1#ifndef __ASM_POWERPC_SYSCALLS_H
2#define __ASM_POWERPC_SYSCALLS_H
3#ifdef __KERNEL__
4
5#include <linux/compiler.h>
6#include <linux/linkage.h>
7#include <linux/types.h>
8#include <asm/signal.h>
9
10struct new_utsname;
11struct pt_regs;
12struct rtas_args;
13struct sigaction;
14
15asmlinkage unsigned long sys_mmap(unsigned long addr, size_t len,
16 unsigned long prot, unsigned long flags,
17 unsigned long fd, off_t offset);
18asmlinkage unsigned long sys_mmap2(unsigned long addr, size_t len,
19 unsigned long prot, unsigned long flags,
20 unsigned long fd, unsigned long pgoff);
21asmlinkage int sys_execve(unsigned long a0, unsigned long a1,
22 unsigned long a2, unsigned long a3, unsigned long a4,
23 unsigned long a5, struct pt_regs *regs);
24asmlinkage int sys_clone(unsigned long clone_flags, unsigned long usp,
25 int __user *parent_tidp, void __user *child_threadptr,
26 int __user *child_tidp, int p6, struct pt_regs *regs);
27asmlinkage int sys_fork(unsigned long p1, unsigned long p2,
28 unsigned long p3, unsigned long p4, unsigned long p5,
29 unsigned long p6, struct pt_regs *regs);
30asmlinkage int sys_vfork(unsigned long p1, unsigned long p2,
31 unsigned long p3, unsigned long p4, unsigned long p5,
32 unsigned long p6, struct pt_regs *regs);
33asmlinkage long sys_pipe(int __user *fildes);
34asmlinkage long sys_pipe2(int __user *fildes, int flags);
35asmlinkage long sys_rt_sigaction(int sig,
36 const struct sigaction __user *act,
37 struct sigaction __user *oact, size_t sigsetsize);
38asmlinkage int sys_ipc(uint call, int first, unsigned long second,
39 long third, void __user *ptr, long fifth);
40asmlinkage long ppc64_personality(unsigned long personality);
41asmlinkage int ppc_rtas(struct rtas_args __user *uargs);
42asmlinkage time_t sys64_time(time_t __user * tloc);
43asmlinkage long ppc_newuname(struct new_utsname __user * name);
44
45asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
46 size_t sigsetsize);
47asmlinkage long sys_sigaltstack(const stack_t __user *uss,
48 stack_t __user *uoss, unsigned long r5, unsigned long r6,
49 unsigned long r7, unsigned long r8, struct pt_regs *regs);
50
51#endif /* __KERNEL__ */
52#endif /* __ASM_POWERPC_SYSCALLS_H */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
new file mode 100644
index 000000000000..e084272ed1c2
--- /dev/null
+++ b/arch/powerpc/include/asm/systbl.h
@@ -0,0 +1,324 @@
1/*
2 * List of powerpc syscalls. For the meaning of the _SPU suffix see
3 * arch/powerpc/platforms/cell/spu_callbacks.c
4 */
5
6SYSCALL(restart_syscall)
7SYSCALL(exit)
8PPC_SYS(fork)
9SYSCALL_SPU(read)
10SYSCALL_SPU(write)
11COMPAT_SYS_SPU(open)
12SYSCALL_SPU(close)
13COMPAT_SYS_SPU(waitpid)
14COMPAT_SYS_SPU(creat)
15SYSCALL_SPU(link)
16SYSCALL_SPU(unlink)
17COMPAT_SYS(execve)
18SYSCALL_SPU(chdir)
19COMPAT_SYS_SPU(time)
20SYSCALL_SPU(mknod)
21SYSCALL_SPU(chmod)
22SYSCALL_SPU(lchown)
23SYSCALL(ni_syscall)
24OLDSYS(stat)
25SYSX_SPU(sys_lseek,ppc32_lseek,sys_lseek)
26SYSCALL_SPU(getpid)
27COMPAT_SYS(mount)
28SYSX(sys_ni_syscall,sys_oldumount,sys_oldumount)
29SYSCALL_SPU(setuid)
30SYSCALL_SPU(getuid)
31COMPAT_SYS_SPU(stime)
32COMPAT_SYS(ptrace)
33SYSCALL_SPU(alarm)
34OLDSYS(fstat)
35COMPAT_SYS(pause)
36COMPAT_SYS(utime)
37SYSCALL(ni_syscall)
38SYSCALL(ni_syscall)
39COMPAT_SYS_SPU(access)
40COMPAT_SYS_SPU(nice)
41SYSCALL(ni_syscall)
42SYSCALL_SPU(sync)
43COMPAT_SYS_SPU(kill)
44SYSCALL_SPU(rename)
45COMPAT_SYS_SPU(mkdir)
46SYSCALL_SPU(rmdir)
47SYSCALL_SPU(dup)
48SYSCALL_SPU(pipe)
49COMPAT_SYS_SPU(times)
50SYSCALL(ni_syscall)
51SYSCALL_SPU(brk)
52SYSCALL_SPU(setgid)
53SYSCALL_SPU(getgid)
54SYSCALL(signal)
55SYSCALL_SPU(geteuid)
56SYSCALL_SPU(getegid)
57SYSCALL(acct)
58SYSCALL(umount)
59SYSCALL(ni_syscall)
60COMPAT_SYS_SPU(ioctl)
61COMPAT_SYS_SPU(fcntl)
62SYSCALL(ni_syscall)
63COMPAT_SYS_SPU(setpgid)
64SYSCALL(ni_syscall)
65SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
66COMPAT_SYS_SPU(umask)
67SYSCALL_SPU(chroot)
68SYSCALL(ustat)
69SYSCALL_SPU(dup2)
70SYSCALL_SPU(getppid)
71SYSCALL_SPU(getpgrp)
72SYSCALL_SPU(setsid)
73SYS32ONLY(sigaction)
74SYSCALL_SPU(sgetmask)
75COMPAT_SYS_SPU(ssetmask)
76SYSCALL_SPU(setreuid)
77SYSCALL_SPU(setregid)
78SYS32ONLY(sigsuspend)
79COMPAT_SYS(sigpending)
80COMPAT_SYS_SPU(sethostname)
81COMPAT_SYS_SPU(setrlimit)
82COMPAT_SYS(old_getrlimit)
83COMPAT_SYS_SPU(getrusage)
84COMPAT_SYS_SPU(gettimeofday)
85COMPAT_SYS_SPU(settimeofday)
86COMPAT_SYS_SPU(getgroups)
87COMPAT_SYS_SPU(setgroups)
88SYSX(sys_ni_syscall,sys_ni_syscall,ppc_select)
89SYSCALL_SPU(symlink)
90OLDSYS(lstat)
91COMPAT_SYS_SPU(readlink)
92SYSCALL(uselib)
93SYSCALL(swapon)
94SYSCALL(reboot)
95SYSX(sys_ni_syscall,old32_readdir,old_readdir)
96SYSCALL_SPU(mmap)
97SYSCALL_SPU(munmap)
98SYSCALL_SPU(truncate)
99SYSCALL_SPU(ftruncate)
100SYSCALL_SPU(fchmod)
101SYSCALL_SPU(fchown)
102COMPAT_SYS_SPU(getpriority)
103COMPAT_SYS_SPU(setpriority)
104SYSCALL(ni_syscall)
105COMPAT_SYS(statfs)
106COMPAT_SYS(fstatfs)
107SYSCALL(ni_syscall)
108COMPAT_SYS_SPU(socketcall)
109COMPAT_SYS_SPU(syslog)
110COMPAT_SYS_SPU(setitimer)
111COMPAT_SYS_SPU(getitimer)
112COMPAT_SYS_SPU(newstat)
113COMPAT_SYS_SPU(newlstat)
114COMPAT_SYS_SPU(newfstat)
115SYSX(sys_ni_syscall,sys_uname,sys_uname)
116SYSCALL(ni_syscall)
117SYSCALL_SPU(vhangup)
118SYSCALL(ni_syscall)
119SYSCALL(ni_syscall)
120COMPAT_SYS_SPU(wait4)
121SYSCALL(swapoff)
122COMPAT_SYS_SPU(sysinfo)
123COMPAT_SYS(ipc)
124SYSCALL_SPU(fsync)
125SYS32ONLY(sigreturn)
126PPC_SYS(clone)
127COMPAT_SYS_SPU(setdomainname)
128PPC_SYS_SPU(newuname)
129SYSCALL(ni_syscall)
130COMPAT_SYS_SPU(adjtimex)
131SYSCALL_SPU(mprotect)
132SYSX(sys_ni_syscall,compat_sys_sigprocmask,sys_sigprocmask)
133SYSCALL(ni_syscall)
134SYSCALL(init_module)
135SYSCALL(delete_module)
136SYSCALL(ni_syscall)
137SYSCALL(quotactl)
138COMPAT_SYS_SPU(getpgid)
139SYSCALL_SPU(fchdir)
140SYSCALL_SPU(bdflush)
141COMPAT_SYS(sysfs)
142SYSX_SPU(ppc64_personality,ppc64_personality,sys_personality)
143SYSCALL(ni_syscall)
144SYSCALL_SPU(setfsuid)
145SYSCALL_SPU(setfsgid)
146SYSCALL_SPU(llseek)
147COMPAT_SYS_SPU(getdents)
148SYSX_SPU(sys_select,ppc32_select,ppc_select)
149SYSCALL_SPU(flock)
150SYSCALL_SPU(msync)
151COMPAT_SYS_SPU(readv)
152COMPAT_SYS_SPU(writev)
153COMPAT_SYS_SPU(getsid)
154SYSCALL_SPU(fdatasync)
155COMPAT_SYS(sysctl)
156SYSCALL_SPU(mlock)
157SYSCALL_SPU(munlock)
158SYSCALL_SPU(mlockall)
159SYSCALL_SPU(munlockall)
160COMPAT_SYS_SPU(sched_setparam)
161COMPAT_SYS_SPU(sched_getparam)
162COMPAT_SYS_SPU(sched_setscheduler)
163COMPAT_SYS_SPU(sched_getscheduler)
164SYSCALL_SPU(sched_yield)
165COMPAT_SYS_SPU(sched_get_priority_max)
166COMPAT_SYS_SPU(sched_get_priority_min)
167COMPAT_SYS_SPU(sched_rr_get_interval)
168COMPAT_SYS_SPU(nanosleep)
169SYSCALL_SPU(mremap)
170SYSCALL_SPU(setresuid)
171SYSCALL_SPU(getresuid)
172SYSCALL(ni_syscall)
173SYSCALL_SPU(poll)
174COMPAT_SYS(nfsservctl)
175SYSCALL_SPU(setresgid)
176SYSCALL_SPU(getresgid)
177COMPAT_SYS_SPU(prctl)
178COMPAT_SYS(rt_sigreturn)
179COMPAT_SYS(rt_sigaction)
180COMPAT_SYS(rt_sigprocmask)
181COMPAT_SYS(rt_sigpending)
182COMPAT_SYS(rt_sigtimedwait)
183COMPAT_SYS(rt_sigqueueinfo)
184COMPAT_SYS(rt_sigsuspend)
185COMPAT_SYS_SPU(pread64)
186COMPAT_SYS_SPU(pwrite64)
187SYSCALL_SPU(chown)
188SYSCALL_SPU(getcwd)
189SYSCALL_SPU(capget)
190SYSCALL_SPU(capset)
191COMPAT_SYS(sigaltstack)
192SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
193SYSCALL(ni_syscall)
194SYSCALL(ni_syscall)
195PPC_SYS(vfork)
196COMPAT_SYS_SPU(getrlimit)
197COMPAT_SYS_SPU(readahead)
198SYS32ONLY(mmap2)
199SYS32ONLY(truncate64)
200SYS32ONLY(ftruncate64)
201SYSX(sys_ni_syscall,sys_stat64,sys_stat64)
202SYSX(sys_ni_syscall,sys_lstat64,sys_lstat64)
203SYSX(sys_ni_syscall,sys_fstat64,sys_fstat64)
204SYSCALL(pciconfig_read)
205SYSCALL(pciconfig_write)
206SYSCALL(pciconfig_iobase)
207SYSCALL(ni_syscall)
208SYSCALL_SPU(getdents64)
209SYSCALL_SPU(pivot_root)
210SYSX(sys_ni_syscall,compat_sys_fcntl64,sys_fcntl64)
211SYSCALL_SPU(madvise)
212SYSCALL_SPU(mincore)
213SYSCALL_SPU(gettid)
214SYSCALL_SPU(tkill)
215SYSCALL_SPU(setxattr)
216SYSCALL_SPU(lsetxattr)
217SYSCALL_SPU(fsetxattr)
218SYSCALL_SPU(getxattr)
219SYSCALL_SPU(lgetxattr)
220SYSCALL_SPU(fgetxattr)
221SYSCALL_SPU(listxattr)
222SYSCALL_SPU(llistxattr)
223SYSCALL_SPU(flistxattr)
224SYSCALL_SPU(removexattr)
225SYSCALL_SPU(lremovexattr)
226SYSCALL_SPU(fremovexattr)
227COMPAT_SYS_SPU(futex)
228COMPAT_SYS_SPU(sched_setaffinity)
229COMPAT_SYS_SPU(sched_getaffinity)
230SYSCALL(ni_syscall)
231SYSCALL(ni_syscall)
232SYS32ONLY(sendfile64)
233COMPAT_SYS_SPU(io_setup)
234SYSCALL_SPU(io_destroy)
235COMPAT_SYS_SPU(io_getevents)
236COMPAT_SYS_SPU(io_submit)
237SYSCALL_SPU(io_cancel)
238SYSCALL(set_tid_address)
239SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
240SYSCALL(exit_group)
241SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
242SYSCALL_SPU(epoll_create)
243SYSCALL_SPU(epoll_ctl)
244SYSCALL_SPU(epoll_wait)
245SYSCALL_SPU(remap_file_pages)
246SYSX_SPU(sys_timer_create,compat_sys_timer_create,sys_timer_create)
247COMPAT_SYS_SPU(timer_settime)
248COMPAT_SYS_SPU(timer_gettime)
249SYSCALL_SPU(timer_getoverrun)
250SYSCALL_SPU(timer_delete)
251COMPAT_SYS_SPU(clock_settime)
252COMPAT_SYS_SPU(clock_gettime)
253COMPAT_SYS_SPU(clock_getres)
254COMPAT_SYS_SPU(clock_nanosleep)
255SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
256COMPAT_SYS_SPU(tgkill)
257COMPAT_SYS_SPU(utimes)
258COMPAT_SYS_SPU(statfs64)
259COMPAT_SYS_SPU(fstatfs64)
260SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
261PPC_SYS_SPU(rtas)
262OLDSYS(debug_setcontext)
263SYSCALL(ni_syscall)
264COMPAT_SYS(migrate_pages)
265COMPAT_SYS(mbind)
266COMPAT_SYS(get_mempolicy)
267COMPAT_SYS(set_mempolicy)
268COMPAT_SYS(mq_open)
269SYSCALL(mq_unlink)
270COMPAT_SYS(mq_timedsend)
271COMPAT_SYS(mq_timedreceive)
272COMPAT_SYS(mq_notify)
273COMPAT_SYS(mq_getsetattr)
274COMPAT_SYS(kexec_load)
275COMPAT_SYS(add_key)
276COMPAT_SYS(request_key)
277COMPAT_SYS(keyctl)
278COMPAT_SYS(waitid)
279COMPAT_SYS(ioprio_set)
280COMPAT_SYS(ioprio_get)
281SYSCALL(inotify_init)
282SYSCALL(inotify_add_watch)
283SYSCALL(inotify_rm_watch)
284SYSCALL(spu_run)
285SYSCALL(spu_create)
286COMPAT_SYS(pselect6)
287COMPAT_SYS(ppoll)
288SYSCALL_SPU(unshare)
289SYSCALL_SPU(splice)
290SYSCALL_SPU(tee)
291COMPAT_SYS_SPU(vmsplice)
292COMPAT_SYS_SPU(openat)
293SYSCALL_SPU(mkdirat)
294SYSCALL_SPU(mknodat)
295SYSCALL_SPU(fchownat)
296COMPAT_SYS_SPU(futimesat)
297SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
298SYSCALL_SPU(unlinkat)
299SYSCALL_SPU(renameat)
300SYSCALL_SPU(linkat)
301SYSCALL_SPU(symlinkat)
302SYSCALL_SPU(readlinkat)
303SYSCALL_SPU(fchmodat)
304SYSCALL_SPU(faccessat)
305COMPAT_SYS_SPU(get_robust_list)
306COMPAT_SYS_SPU(set_robust_list)
307COMPAT_SYS_SPU(move_pages)
308SYSCALL_SPU(getcpu)
309COMPAT_SYS(epoll_pwait)
310COMPAT_SYS_SPU(utimensat)
311COMPAT_SYS_SPU(signalfd)
312SYSCALL_SPU(timerfd_create)
313SYSCALL_SPU(eventfd)
314COMPAT_SYS_SPU(sync_file_range2)
315COMPAT_SYS(fallocate)
316SYSCALL(subpage_prot)
317COMPAT_SYS_SPU(timerfd_settime)
318COMPAT_SYS_SPU(timerfd_gettime)
319COMPAT_SYS_SPU(signalfd4)
320SYSCALL_SPU(eventfd2)
321SYSCALL_SPU(epoll_create1)
322SYSCALL_SPU(dup3)
323SYSCALL_SPU(pipe2)
324SYSCALL(inotify_init1)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
new file mode 100644
index 000000000000..d6648c143322
--- /dev/null
+++ b/arch/powerpc/include/asm/system.h
@@ -0,0 +1,548 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/kernel.h>
8#include <linux/irqflags.h>
9
10#include <asm/hw_irq.h>
11
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
28 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
29 * architectures.
30 *
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
34 * on SMP since it is only used to order updates to system memory.
35 */
36#define mb() __asm__ __volatile__ ("sync" : : : "memory")
37#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
38#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39#define read_barrier_depends() do { } while(0)
40
41#define set_mb(var, value) do { var = value; mb(); } while (0)
42
43#ifdef __KERNEL__
44#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
45#ifdef CONFIG_SMP
46
47#ifdef __SUBARCH_HAS_LWSYNC
48# define SMPWMB lwsync
49#else
50# define SMPWMB eieio
51#endif
52
53#define smp_mb() mb()
54#define smp_rmb() rmb()
55#define smp_wmb() __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
56#define smp_read_barrier_depends() read_barrier_depends()
57#else
58#define smp_mb() barrier()
59#define smp_rmb() barrier()
60#define smp_wmb() barrier()
61#define smp_read_barrier_depends() do { } while(0)
62#endif /* CONFIG_SMP */
63
64/*
65 * This is a barrier which prevents following instructions from being
66 * started until the value of the argument x is known. For example, if
67 * x is a variable loaded from memory, this prevents following
68 * instructions from being executed until the load has been performed.
69 */
70#define data_barrier(x) \
71 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
72
73struct task_struct;
74struct pt_regs;
75
76#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
77
78extern int (*__debugger)(struct pt_regs *regs);
79extern int (*__debugger_ipi)(struct pt_regs *regs);
80extern int (*__debugger_bpt)(struct pt_regs *regs);
81extern int (*__debugger_sstep)(struct pt_regs *regs);
82extern int (*__debugger_iabr_match)(struct pt_regs *regs);
83extern int (*__debugger_dabr_match)(struct pt_regs *regs);
84extern int (*__debugger_fault_handler)(struct pt_regs *regs);
85
86#define DEBUGGER_BOILERPLATE(__NAME) \
87static inline int __NAME(struct pt_regs *regs) \
88{ \
89 if (unlikely(__ ## __NAME)) \
90 return __ ## __NAME(regs); \
91 return 0; \
92}
93
94DEBUGGER_BOILERPLATE(debugger)
95DEBUGGER_BOILERPLATE(debugger_ipi)
96DEBUGGER_BOILERPLATE(debugger_bpt)
97DEBUGGER_BOILERPLATE(debugger_sstep)
98DEBUGGER_BOILERPLATE(debugger_iabr_match)
99DEBUGGER_BOILERPLATE(debugger_dabr_match)
100DEBUGGER_BOILERPLATE(debugger_fault_handler)
101
102#else
103static inline int debugger(struct pt_regs *regs) { return 0; }
104static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
105static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
106static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
107static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
108static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
109static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
110#endif
111
112extern int set_dabr(unsigned long dabr);
113extern void do_dabr(struct pt_regs *regs, unsigned long address,
114 unsigned long error_code);
115extern void print_backtrace(unsigned long *);
116extern void show_regs(struct pt_regs * regs);
117extern void flush_instruction_cache(void);
118extern void hard_reset_now(void);
119extern void poweroff_now(void);
120
121#ifdef CONFIG_6xx
122extern long _get_L2CR(void);
123extern long _get_L3CR(void);
124extern void _set_L2CR(unsigned long);
125extern void _set_L3CR(unsigned long);
126#else
127#define _get_L2CR() 0L
128#define _get_L3CR() 0L
129#define _set_L2CR(val) do { } while(0)
130#define _set_L3CR(val) do { } while(0)
131#endif
132
133extern void via_cuda_init(void);
134extern void read_rtc_time(void);
135extern void pmac_find_display(void);
136extern void giveup_fpu(struct task_struct *);
137extern void disable_kernel_fp(void);
138extern void enable_kernel_fp(void);
139extern void flush_fp_to_thread(struct task_struct *);
140extern void enable_kernel_altivec(void);
141extern void giveup_altivec(struct task_struct *);
142extern void load_up_altivec(struct task_struct *);
143extern int emulate_altivec(struct pt_regs *);
144extern void __giveup_vsx(struct task_struct *);
145extern void giveup_vsx(struct task_struct *);
146extern void enable_kernel_spe(void);
147extern void giveup_spe(struct task_struct *);
148extern void load_up_spe(struct task_struct *);
149extern int fix_alignment(struct pt_regs *);
150extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
151extern void cvt_df(double *from, float *to, struct thread_struct *thread);
152
153#ifndef CONFIG_SMP
154extern void discard_lazy_cpu_state(void);
155#else
156static inline void discard_lazy_cpu_state(void)
157{
158}
159#endif
160
161#ifdef CONFIG_ALTIVEC
162extern void flush_altivec_to_thread(struct task_struct *);
163#else
164static inline void flush_altivec_to_thread(struct task_struct *t)
165{
166}
167#endif
168
169#ifdef CONFIG_VSX
170extern void flush_vsx_to_thread(struct task_struct *);
171#else
172static inline void flush_vsx_to_thread(struct task_struct *t)
173{
174}
175#endif
176
177#ifdef CONFIG_SPE
178extern void flush_spe_to_thread(struct task_struct *);
179#else
180static inline void flush_spe_to_thread(struct task_struct *t)
181{
182}
183#endif
184
185extern int call_rtas(const char *, int, int, unsigned long *, ...);
186extern void cacheable_memzero(void *p, unsigned int nb);
187extern void *cacheable_memcpy(void *, const void *, unsigned int);
188extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
189extern void bad_page_fault(struct pt_regs *, unsigned long, int);
190extern int die(const char *, struct pt_regs *, long);
191extern void _exception(int, struct pt_regs *, int, unsigned long);
192extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
193
194#ifdef CONFIG_BOOKE_WDT
195extern u32 booke_wdt_enabled;
196extern u32 booke_wdt_period;
197#endif /* CONFIG_BOOKE_WDT */
198
199struct device_node;
200extern void note_scsi_host(struct device_node *, void *);
201
202extern struct task_struct *__switch_to(struct task_struct *,
203 struct task_struct *);
204#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
205
206struct thread_struct;
207extern struct task_struct *_switch(struct thread_struct *prev,
208 struct thread_struct *next);
209
210extern unsigned int rtas_data;
211extern int mem_init_done; /* set on boot once kmalloc can be called */
212extern int init_bootmem_done; /* set on !NUMA once bootmem is available */
213extern unsigned long memory_limit;
214extern unsigned long klimit;
215
216extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
217extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
218
219extern int powersave_nap; /* set if nap mode can be used in idle loop */
220
221/*
222 * Atomic exchange
223 *
224 * Changes the memory location '*ptr' to be val and returns
225 * the previous value stored there.
226 */
227static __always_inline unsigned long
228__xchg_u32(volatile void *p, unsigned long val)
229{
230 unsigned long prev;
231
232 __asm__ __volatile__(
233 LWSYNC_ON_SMP
234"1: lwarx %0,0,%2 \n"
235 PPC405_ERR77(0,%2)
236" stwcx. %3,0,%2 \n\
237 bne- 1b"
238 ISYNC_ON_SMP
239 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
240 : "r" (p), "r" (val)
241 : "cc", "memory");
242
243 return prev;
244}
245
246/*
247 * Atomic exchange
248 *
249 * Changes the memory location '*ptr' to be val and returns
250 * the previous value stored there.
251 */
252static __always_inline unsigned long
253__xchg_u32_local(volatile void *p, unsigned long val)
254{
255 unsigned long prev;
256
257 __asm__ __volatile__(
258"1: lwarx %0,0,%2 \n"
259 PPC405_ERR77(0,%2)
260" stwcx. %3,0,%2 \n\
261 bne- 1b"
262 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
263 : "r" (p), "r" (val)
264 : "cc", "memory");
265
266 return prev;
267}
268
269#ifdef CONFIG_PPC64
270static __always_inline unsigned long
271__xchg_u64(volatile void *p, unsigned long val)
272{
273 unsigned long prev;
274
275 __asm__ __volatile__(
276 LWSYNC_ON_SMP
277"1: ldarx %0,0,%2 \n"
278 PPC405_ERR77(0,%2)
279" stdcx. %3,0,%2 \n\
280 bne- 1b"
281 ISYNC_ON_SMP
282 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
283 : "r" (p), "r" (val)
284 : "cc", "memory");
285
286 return prev;
287}
288
289static __always_inline unsigned long
290__xchg_u64_local(volatile void *p, unsigned long val)
291{
292 unsigned long prev;
293
294 __asm__ __volatile__(
295"1: ldarx %0,0,%2 \n"
296 PPC405_ERR77(0,%2)
297" stdcx. %3,0,%2 \n\
298 bne- 1b"
299 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
300 : "r" (p), "r" (val)
301 : "cc", "memory");
302
303 return prev;
304}
305#endif
306
307/*
308 * This function doesn't exist, so you'll get a linker error
309 * if something tries to do an invalid xchg().
310 */
311extern void __xchg_called_with_bad_pointer(void);
312
313static __always_inline unsigned long
314__xchg(volatile void *ptr, unsigned long x, unsigned int size)
315{
316 switch (size) {
317 case 4:
318 return __xchg_u32(ptr, x);
319#ifdef CONFIG_PPC64
320 case 8:
321 return __xchg_u64(ptr, x);
322#endif
323 }
324 __xchg_called_with_bad_pointer();
325 return x;
326}
327
328static __always_inline unsigned long
329__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
330{
331 switch (size) {
332 case 4:
333 return __xchg_u32_local(ptr, x);
334#ifdef CONFIG_PPC64
335 case 8:
336 return __xchg_u64_local(ptr, x);
337#endif
338 }
339 __xchg_called_with_bad_pointer();
340 return x;
341}
342#define xchg(ptr,x) \
343 ({ \
344 __typeof__(*(ptr)) _x_ = (x); \
345 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
346 })
347
348#define xchg_local(ptr,x) \
349 ({ \
350 __typeof__(*(ptr)) _x_ = (x); \
351 (__typeof__(*(ptr))) __xchg_local((ptr), \
352 (unsigned long)_x_, sizeof(*(ptr))); \
353 })
354
355/*
356 * Compare and exchange - if *p == old, set it to new,
357 * and return the old value of *p.
358 */
359#define __HAVE_ARCH_CMPXCHG 1
360
361static __always_inline unsigned long
362__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
363{
364 unsigned int prev;
365
366 __asm__ __volatile__ (
367 LWSYNC_ON_SMP
368"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
369 cmpw 0,%0,%3\n\
370 bne- 2f\n"
371 PPC405_ERR77(0,%2)
372" stwcx. %4,0,%2\n\
373 bne- 1b"
374 ISYNC_ON_SMP
375 "\n\
3762:"
377 : "=&r" (prev), "+m" (*p)
378 : "r" (p), "r" (old), "r" (new)
379 : "cc", "memory");
380
381 return prev;
382}
383
384static __always_inline unsigned long
385__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
386 unsigned long new)
387{
388 unsigned int prev;
389
390 __asm__ __volatile__ (
391"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
392 cmpw 0,%0,%3\n\
393 bne- 2f\n"
394 PPC405_ERR77(0,%2)
395" stwcx. %4,0,%2\n\
396 bne- 1b"
397 "\n\
3982:"
399 : "=&r" (prev), "+m" (*p)
400 : "r" (p), "r" (old), "r" (new)
401 : "cc", "memory");
402
403 return prev;
404}
405
406#ifdef CONFIG_PPC64
407static __always_inline unsigned long
408__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
409{
410 unsigned long prev;
411
412 __asm__ __volatile__ (
413 LWSYNC_ON_SMP
414"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
415 cmpd 0,%0,%3\n\
416 bne- 2f\n\
417 stdcx. %4,0,%2\n\
418 bne- 1b"
419 ISYNC_ON_SMP
420 "\n\
4212:"
422 : "=&r" (prev), "+m" (*p)
423 : "r" (p), "r" (old), "r" (new)
424 : "cc", "memory");
425
426 return prev;
427}
428
429static __always_inline unsigned long
430__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
431 unsigned long new)
432{
433 unsigned long prev;
434
435 __asm__ __volatile__ (
436"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
437 cmpd 0,%0,%3\n\
438 bne- 2f\n\
439 stdcx. %4,0,%2\n\
440 bne- 1b"
441 "\n\
4422:"
443 : "=&r" (prev), "+m" (*p)
444 : "r" (p), "r" (old), "r" (new)
445 : "cc", "memory");
446
447 return prev;
448}
449#endif
450
451/* This function doesn't exist, so you'll get a linker error
452 if something tries to do an invalid cmpxchg(). */
453extern void __cmpxchg_called_with_bad_pointer(void);
454
455static __always_inline unsigned long
456__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
457 unsigned int size)
458{
459 switch (size) {
460 case 4:
461 return __cmpxchg_u32(ptr, old, new);
462#ifdef CONFIG_PPC64
463 case 8:
464 return __cmpxchg_u64(ptr, old, new);
465#endif
466 }
467 __cmpxchg_called_with_bad_pointer();
468 return old;
469}
470
471static __always_inline unsigned long
472__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
473 unsigned int size)
474{
475 switch (size) {
476 case 4:
477 return __cmpxchg_u32_local(ptr, old, new);
478#ifdef CONFIG_PPC64
479 case 8:
480 return __cmpxchg_u64_local(ptr, old, new);
481#endif
482 }
483 __cmpxchg_called_with_bad_pointer();
484 return old;
485}
486
487#define cmpxchg(ptr, o, n) \
488 ({ \
489 __typeof__(*(ptr)) _o_ = (o); \
490 __typeof__(*(ptr)) _n_ = (n); \
491 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
492 (unsigned long)_n_, sizeof(*(ptr))); \
493 })
494
495
496#define cmpxchg_local(ptr, o, n) \
497 ({ \
498 __typeof__(*(ptr)) _o_ = (o); \
499 __typeof__(*(ptr)) _n_ = (n); \
500 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
501 (unsigned long)_n_, sizeof(*(ptr))); \
502 })
503
504#ifdef CONFIG_PPC64
505/*
506 * We handle most unaligned accesses in hardware. On the other hand
507 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
508 * powers of 2 writes until it reaches sufficient alignment).
509 *
510 * Based on this we disable the IP header alignment in network drivers.
511 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
512 * cacheline alignment of buffers.
513 */
514#define NET_IP_ALIGN 0
515#define NET_SKB_PAD L1_CACHE_BYTES
516
517#define cmpxchg64(ptr, o, n) \
518 ({ \
519 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
520 cmpxchg((ptr), (o), (n)); \
521 })
522#define cmpxchg64_local(ptr, o, n) \
523 ({ \
524 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
525 cmpxchg_local((ptr), (o), (n)); \
526 })
527#else
528#include <asm-generic/cmpxchg-local.h>
529#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
530#endif
531
532#define arch_align_stack(x) (x)
533
534/* Used in very early kernel initialization. */
535extern unsigned long reloc_offset(void);
536extern unsigned long add_reloc_offset(unsigned long);
537extern void reloc_got2(unsigned long);
538
539#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
540
541#ifdef CONFIG_VIRT_CPU_ACCOUNTING
542extern void account_system_vtime(struct task_struct *);
543#endif
544
545extern struct dentry *powerpc_debugfs_root;
546
547#endif /* __KERNEL__ */
548#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
new file mode 100644
index 000000000000..f663634cccc9
--- /dev/null
+++ b/arch/powerpc/include/asm/tce.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TCE_H
22#define _ASM_POWERPC_TCE_H
23#ifdef __KERNEL__
24
25#include <asm/iommu.h>
26
27/*
28 * Tces come in two formats, one for the virtual bus and a different
29 * format for PCI
30 */
31#define TCE_VB 0
32#define TCE_PCI 1
33
34/* TCE page size is 4096 bytes (1 << 12) */
35
36#define TCE_SHIFT 12
37#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
38
39#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
40
41#define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */
42#define TCE_RPN_SHIFT 12
43#define TCE_VALID 0x800 /* TCE valid */
44#define TCE_ALLIO 0x400 /* TCE valid for all lpars */
45#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
46#define TCE_PCI_READ 0x1 /* read from PCI allowed */
47#define TCE_VB_WRITE 0x1 /* write from VB allowed */
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_TCE_H */
diff --git a/arch/powerpc/include/asm/termbits.h b/arch/powerpc/include/asm/termbits.h
new file mode 100644
index 000000000000..6698188ca550
--- /dev/null
+++ b/arch/powerpc/include/asm/termbits.h
@@ -0,0 +1,209 @@
1#ifndef _ASM_POWERPC_TERMBITS_H
2#define _ASM_POWERPC_TERMBITS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11typedef unsigned char cc_t;
12typedef unsigned int speed_t;
13typedef unsigned int tcflag_t;
14
15/*
16 * termios type and macro definitions. Be careful about adding stuff
17 * to this file since it's used in GNU libc and there are strict rules
18 * concerning namespace pollution.
19 */
20
21#define NCCS 19
22struct termios {
23 tcflag_t c_iflag; /* input mode flags */
24 tcflag_t c_oflag; /* output mode flags */
25 tcflag_t c_cflag; /* control mode flags */
26 tcflag_t c_lflag; /* local mode flags */
27 cc_t c_cc[NCCS]; /* control characters */
28 cc_t c_line; /* line discipline (== c_cc[19]) */
29 speed_t c_ispeed; /* input speed */
30 speed_t c_ospeed; /* output speed */
31};
32
33/* For PowerPC the termios and ktermios are the same */
34
35struct ktermios {
36 tcflag_t c_iflag; /* input mode flags */
37 tcflag_t c_oflag; /* output mode flags */
38 tcflag_t c_cflag; /* control mode flags */
39 tcflag_t c_lflag; /* local mode flags */
40 cc_t c_cc[NCCS]; /* control characters */
41 cc_t c_line; /* line discipline (== c_cc[19]) */
42 speed_t c_ispeed; /* input speed */
43 speed_t c_ospeed; /* output speed */
44};
45
46/* c_cc characters */
47#define VINTR 0
48#define VQUIT 1
49#define VERASE 2
50#define VKILL 3
51#define VEOF 4
52#define VMIN 5
53#define VEOL 6
54#define VTIME 7
55#define VEOL2 8
56#define VSWTC 9
57#define VWERASE 10
58#define VREPRINT 11
59#define VSUSP 12
60#define VSTART 13
61#define VSTOP 14
62#define VLNEXT 15
63#define VDISCARD 16
64
65/* c_iflag bits */
66#define IGNBRK 0000001
67#define BRKINT 0000002
68#define IGNPAR 0000004
69#define PARMRK 0000010
70#define INPCK 0000020
71#define ISTRIP 0000040
72#define INLCR 0000100
73#define IGNCR 0000200
74#define ICRNL 0000400
75#define IXON 0001000
76#define IXOFF 0002000
77#define IXANY 0004000
78#define IUCLC 0010000
79#define IMAXBEL 0020000
80#define IUTF8 0040000
81
82/* c_oflag bits */
83#define OPOST 0000001
84#define ONLCR 0000002
85#define OLCUC 0000004
86
87#define OCRNL 0000010
88#define ONOCR 0000020
89#define ONLRET 0000040
90
91#define OFILL 00000100
92#define OFDEL 00000200
93#define NLDLY 00001400
94#define NL0 00000000
95#define NL1 00000400
96#define NL2 00001000
97#define NL3 00001400
98#define TABDLY 00006000
99#define TAB0 00000000
100#define TAB1 00002000
101#define TAB2 00004000
102#define TAB3 00006000
103#define XTABS 00006000 /* required by POSIX to == TAB3 */
104#define CRDLY 00030000
105#define CR0 00000000
106#define CR1 00010000
107#define CR2 00020000
108#define CR3 00030000
109#define FFDLY 00040000
110#define FF0 00000000
111#define FF1 00040000
112#define BSDLY 00100000
113#define BS0 00000000
114#define BS1 00100000
115#define VTDLY 00200000
116#define VT0 00000000
117#define VT1 00200000
118
119/* c_cflag bit meaning */
120#define CBAUD 0000377
121#define B0 0000000 /* hang up */
122#define B50 0000001
123#define B75 0000002
124#define B110 0000003
125#define B134 0000004
126#define B150 0000005
127#define B200 0000006
128#define B300 0000007
129#define B600 0000010
130#define B1200 0000011
131#define B1800 0000012
132#define B2400 0000013
133#define B4800 0000014
134#define B9600 0000015
135#define B19200 0000016
136#define B38400 0000017
137#define EXTA B19200
138#define EXTB B38400
139#define CBAUDEX 0000000
140#define B57600 00020
141#define B115200 00021
142#define B230400 00022
143#define B460800 00023
144#define B500000 00024
145#define B576000 00025
146#define B921600 00026
147#define B1000000 00027
148#define B1152000 00030
149#define B1500000 00031
150#define B2000000 00032
151#define B2500000 00033
152#define B3000000 00034
153#define B3500000 00035
154#define B4000000 00036
155#define BOTHER 00037
156
157#define CIBAUD 077600000
158#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
159
160#define CSIZE 00001400
161#define CS5 00000000
162#define CS6 00000400
163#define CS7 00001000
164#define CS8 00001400
165
166#define CSTOPB 00002000
167#define CREAD 00004000
168#define PARENB 00010000
169#define PARODD 00020000
170#define HUPCL 00040000
171
172#define CLOCAL 00100000
173#define CMSPAR 010000000000 /* mark or space (stick) parity */
174#define CRTSCTS 020000000000 /* flow control */
175
176/* c_lflag bits */
177#define ISIG 0x00000080
178#define ICANON 0x00000100
179#define XCASE 0x00004000
180#define ECHO 0x00000008
181#define ECHOE 0x00000002
182#define ECHOK 0x00000004
183#define ECHONL 0x00000010
184#define NOFLSH 0x80000000
185#define TOSTOP 0x00400000
186#define ECHOCTL 0x00000040
187#define ECHOPRT 0x00000020
188#define ECHOKE 0x00000001
189#define FLUSHO 0x00800000
190#define PENDIN 0x20000000
191#define IEXTEN 0x00000400
192
193/* Values for the ACTION argument to `tcflow'. */
194#define TCOOFF 0
195#define TCOON 1
196#define TCIOFF 2
197#define TCION 3
198
199/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
200#define TCIFLUSH 0
201#define TCOFLUSH 1
202#define TCIOFLUSH 2
203
204/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
205#define TCSANOW 0
206#define TCSADRAIN 1
207#define TCSAFLUSH 2
208
209#endif /* _ASM_POWERPC_TERMBITS_H */
diff --git a/arch/powerpc/include/asm/termios.h b/arch/powerpc/include/asm/termios.h
new file mode 100644
index 000000000000..2c14fea07c8a
--- /dev/null
+++ b/arch/powerpc/include/asm/termios.h
@@ -0,0 +1,85 @@
1#ifndef _ASM_POWERPC_TERMIOS_H
2#define _ASM_POWERPC_TERMIOS_H
3
4/*
5 * Liberally adapted from alpha/termios.h. In particular, the c_cc[]
6 * fields have been reordered so that termio & termios share the
7 * common subset in the same order (for brain dead programs that don't
8 * know or care about the differences).
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <asm/ioctls.h>
17#include <asm/termbits.h>
18
19struct sgttyb {
20 char sg_ispeed;
21 char sg_ospeed;
22 char sg_erase;
23 char sg_kill;
24 short sg_flags;
25};
26
27struct tchars {
28 char t_intrc;
29 char t_quitc;
30 char t_startc;
31 char t_stopc;
32 char t_eofc;
33 char t_brkc;
34};
35
36struct ltchars {
37 char t_suspc;
38 char t_dsuspc;
39 char t_rprntc;
40 char t_flushc;
41 char t_werasc;
42 char t_lnextc;
43};
44
45struct winsize {
46 unsigned short ws_row;
47 unsigned short ws_col;
48 unsigned short ws_xpixel;
49 unsigned short ws_ypixel;
50};
51
52#define NCC 10
53struct termio {
54 unsigned short c_iflag; /* input mode flags */
55 unsigned short c_oflag; /* output mode flags */
56 unsigned short c_cflag; /* control mode flags */
57 unsigned short c_lflag; /* local mode flags */
58 unsigned char c_line; /* line discipline */
59 unsigned char c_cc[NCC]; /* control characters */
60};
61
62/* c_cc characters */
63#define _VINTR 0
64#define _VQUIT 1
65#define _VERASE 2
66#define _VKILL 3
67#define _VEOF 4
68#define _VMIN 5
69#define _VEOL 6
70#define _VTIME 7
71#define _VEOL2 8
72#define _VSWTC 9
73
74#ifdef __KERNEL__
75/* ^C ^\ del ^U ^D 1 0 0 0 0 ^W ^R ^Z ^Q ^S ^V ^U */
76#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
77#endif
78
79#ifdef __KERNEL__
80
81#include <asm-generic/termios.h>
82
83#endif /* __KERNEL__ */
84
85#endif /* _ASM_POWERPC_TERMIOS_H */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
new file mode 100644
index 000000000000..9665a26a253a
--- /dev/null
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -0,0 +1,161 @@
1/* thread_info.h: PowerPC low-level thread information
2 * adapted from the i386 version by Paul Mackerras
3 *
4 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
6 */
7
8#ifndef _ASM_POWERPC_THREAD_INFO_H
9#define _ASM_POWERPC_THREAD_INFO_H
10
11#ifdef __KERNEL__
12
13/* We have 8k stacks on ppc32 and 16k on ppc64 */
14
15#ifdef CONFIG_PPC64
16#define THREAD_SHIFT 14
17#else
18#define THREAD_SHIFT 13
19#endif
20
21#define THREAD_SIZE (1 << THREAD_SHIFT)
22
23#ifndef __ASSEMBLY__
24#include <linux/cache.h>
25#include <asm/processor.h>
26#include <asm/page.h>
27#include <linux/stringify.h>
28
29/*
30 * low level task data.
31 */
32struct thread_info {
33 struct task_struct *task; /* main task structure */
34 struct exec_domain *exec_domain; /* execution domain */
35 int cpu; /* cpu we're on */
36 int preempt_count; /* 0 => preemptable,
37 <0 => BUG */
38 struct restart_block restart_block;
39 unsigned long local_flags; /* private flags for thread */
40
41 /* low level flags - has atomic operations done on it */
42 unsigned long flags ____cacheline_aligned_in_smp;
43};
44
45/*
46 * macros/functions for gaining access to the thread information structure
47 *
48 * preempt_count needs to be 1 initially, until the scheduler is functional.
49 */
50#define INIT_THREAD_INFO(tsk) \
51{ \
52 .task = &tsk, \
53 .exec_domain = &default_exec_domain, \
54 .cpu = 0, \
55 .preempt_count = 1, \
56 .restart_block = { \
57 .fn = do_no_restart_syscall, \
58 }, \
59 .flags = 0, \
60}
61
62#define init_thread_info (init_thread_union.thread_info)
63#define init_stack (init_thread_union.stack)
64
65/* thread information allocation */
66
67#if THREAD_SHIFT >= PAGE_SHIFT
68
69#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
70
71#else /* THREAD_SHIFT < PAGE_SHIFT */
72
73#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
74
75extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
76extern void free_thread_info(struct thread_info *ti);
77
78#endif /* THREAD_SHIFT < PAGE_SHIFT */
79
80/* how to get the thread information struct from C */
81static inline struct thread_info *current_thread_info(void)
82{
83 register unsigned long sp asm("r1");
84
85 /* gcc4, at least, is smart enough to turn this into a single
86 * rlwinm for ppc32 and clrrdi for ppc64 */
87 return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
88}
89
90#endif /* __ASSEMBLY__ */
91
92#define PREEMPT_ACTIVE 0x10000000
93
94/*
95 * thread information flag bit numbers
96 */
97#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
98#define TIF_SIGPENDING 1 /* signal pending */
99#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
100#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
101 TIF_NEED_RESCHED */
102#define TIF_32BIT 4 /* 32 bit binary */
103#define TIF_PERFMON_WORK 5 /* work for pfm_handle_work() */
104#define TIF_PERFMON_CTXSW 6 /* perfmon needs ctxsw calls */
105#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
106#define TIF_SINGLESTEP 8 /* singlestepping active */
107#define TIF_MEMDIE 9
108#define TIF_SECCOMP 10 /* secure computing */
109#define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */
110#define TIF_NOERROR 12 /* Force successful syscall return */
111#define TIF_NOTIFY_RESUME 13 /* callback before returning to user */
112#define TIF_FREEZE 14 /* Freezing for suspend */
113#define TIF_RUNLATCH 15 /* Is the runlatch enabled? */
114#define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */
115
116/* as above, but as bit values */
117#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
118#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
119#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
120#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
121#define _TIF_32BIT (1<<TIF_32BIT)
122#define _TIF_PERFMON_WORK (1<<TIF_PERFMON_WORK)
123#define _TIF_PERFMON_CTXSW (1<<TIF_PERFMON_CTXSW)
124#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
125#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
126#define _TIF_SECCOMP (1<<TIF_SECCOMP)
127#define _TIF_RESTOREALL (1<<TIF_RESTOREALL)
128#define _TIF_NOERROR (1<<TIF_NOERROR)
129#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
130#define _TIF_FREEZE (1<<TIF_FREEZE)
131#define _TIF_RUNLATCH (1<<TIF_RUNLATCH)
132#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
133#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
134
135#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
136 _TIF_NOTIFY_RESUME)
137#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
138
139/* Bits in local_flags */
140/* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
141#define TLF_NAPPING 0 /* idle thread enabled NAP mode */
142#define TLF_SLEEPING 1 /* suspend code enabled SLEEP mode */
143#define TLF_RESTORE_SIGMASK 2 /* Restore signal mask in do_signal */
144
145#define _TLF_NAPPING (1 << TLF_NAPPING)
146#define _TLF_SLEEPING (1 << TLF_SLEEPING)
147#define _TLF_RESTORE_SIGMASK (1 << TLF_RESTORE_SIGMASK)
148
149#ifndef __ASSEMBLY__
150#define HAVE_SET_RESTORE_SIGMASK 1
151static inline void set_restore_sigmask(void)
152{
153 struct thread_info *ti = current_thread_info();
154 ti->local_flags |= _TLF_RESTORE_SIGMASK;
155 set_bit(TIF_SIGPENDING, &ti->flags);
156}
157#endif /* !__ASSEMBLY__ */
158
159#endif /* __KERNEL__ */
160
161#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
new file mode 100644
index 000000000000..febd581ec9b0
--- /dev/null
+++ b/arch/powerpc/include/asm/time.h
@@ -0,0 +1,255 @@
1/*
2 * Common time prototypes and such for all ppc machines.
3 *
4 * Written by Cort Dougan (cort@cs.nmt.edu) to merge
5 * Paul Mackerras' version and mine for PReP and Pmac.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef __POWERPC_TIME_H
14#define __POWERPC_TIME_H
15
16#ifdef __KERNEL__
17#include <linux/types.h>
18#include <linux/percpu.h>
19
20#include <asm/processor.h>
21#ifdef CONFIG_PPC_ISERIES
22#include <asm/paca.h>
23#include <asm/firmware.h>
24#include <asm/iseries/hv_call.h>
25#endif
26
27/* time.c */
28extern unsigned long tb_ticks_per_jiffy;
29extern unsigned long tb_ticks_per_usec;
30extern unsigned long tb_ticks_per_sec;
31extern u64 tb_to_xs;
32extern unsigned tb_to_us;
33
34struct rtc_time;
35extern void to_tm(int tim, struct rtc_time * tm);
36extern void GregorianDay(struct rtc_time *tm);
37extern time_t last_rtc_update;
38
39extern void generic_calibrate_decr(void);
40extern void wakeup_decrementer(void);
41extern void snapshot_timebase(void);
42
43extern void set_dec_cpu6(unsigned int val);
44
45/* Some sane defaults: 125 MHz timebase, 1GHz processor */
46extern unsigned long ppc_proc_freq;
47#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
48extern unsigned long ppc_tb_freq;
49#define DEFAULT_TB_FREQ 125000000UL
50
51/*
52 * By putting all of this stuff into a single struct we
53 * reduce the number of cache lines touched by do_gettimeofday.
54 * Both by collecting all of the data in one cache line and
55 * by touching only one TOC entry on ppc64.
56 */
57struct gettimeofday_vars {
58 u64 tb_to_xs;
59 u64 stamp_xsec;
60 u64 tb_orig_stamp;
61};
62
63struct gettimeofday_struct {
64 unsigned long tb_ticks_per_sec;
65 struct gettimeofday_vars vars[2];
66 struct gettimeofday_vars * volatile varp;
67 unsigned var_idx;
68 unsigned tb_to_us;
69};
70
71struct div_result {
72 u64 result_high;
73 u64 result_low;
74};
75
76/* Accessor functions for the timebase (RTC on 601) registers. */
77/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
78#ifdef CONFIG_6xx
79#define __USE_RTC() (!cpu_has_feature(CPU_FTR_USE_TB))
80#else
81#define __USE_RTC() 0
82#endif
83
84#ifdef CONFIG_PPC64
85
86/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
87#define get_tbl get_tb
88
89#else
90
91static inline unsigned long get_tbl(void)
92{
93#if defined(CONFIG_403GCX)
94 unsigned long tbl;
95 asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
96 return tbl;
97#else
98 return mftbl();
99#endif
100}
101
102static inline unsigned int get_tbu(void)
103{
104#ifdef CONFIG_403GCX
105 unsigned int tbu;
106 asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
107 return tbu;
108#else
109 return mftbu();
110#endif
111}
112#endif /* !CONFIG_PPC64 */
113
114static inline unsigned int get_rtcl(void)
115{
116 unsigned int rtcl;
117
118 asm volatile("mfrtcl %0" : "=r" (rtcl));
119 return rtcl;
120}
121
122static inline u64 get_rtc(void)
123{
124 unsigned int hi, lo, hi2;
125
126 do {
127 asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
128 : "=r" (hi), "=r" (lo), "=r" (hi2));
129 } while (hi2 != hi);
130 return (u64)hi * 1000000000 + lo;
131}
132
133#ifdef CONFIG_PPC64
134static inline u64 get_tb(void)
135{
136 return mftb();
137}
138#else /* CONFIG_PPC64 */
139static inline u64 get_tb(void)
140{
141 unsigned int tbhi, tblo, tbhi2;
142
143 do {
144 tbhi = get_tbu();
145 tblo = get_tbl();
146 tbhi2 = get_tbu();
147 } while (tbhi != tbhi2);
148
149 return ((u64)tbhi << 32) | tblo;
150}
151#endif /* !CONFIG_PPC64 */
152
153static inline u64 get_tb_or_rtc(void)
154{
155 return __USE_RTC() ? get_rtc() : get_tb();
156}
157
158static inline void set_tb(unsigned int upper, unsigned int lower)
159{
160 mtspr(SPRN_TBWL, 0);
161 mtspr(SPRN_TBWU, upper);
162 mtspr(SPRN_TBWL, lower);
163}
164
165/* Accessor functions for the decrementer register.
166 * The 4xx doesn't even have a decrementer. I tried to use the
167 * generic timer interrupt code, which seems OK, with the 4xx PIT
168 * in auto-reload mode. The problem is PIT stops counting when it
169 * hits zero. If it would wrap, we could use it just like a decrementer.
170 */
171static inline unsigned int get_dec(void)
172{
173#if defined(CONFIG_40x)
174 return (mfspr(SPRN_PIT));
175#else
176 return (mfspr(SPRN_DEC));
177#endif
178}
179
180/*
181 * Note: Book E and 4xx processors differ from other PowerPC processors
182 * in when the decrementer generates its interrupt: on the 1 to 0
183 * transition for Book E/4xx, but on the 0 to -1 transition for others.
184 */
185static inline void set_dec(int val)
186{
187#if defined(CONFIG_40x)
188 mtspr(SPRN_PIT, val);
189#elif defined(CONFIG_8xx_CPU6)
190 set_dec_cpu6(val - 1);
191#else
192#ifndef CONFIG_BOOKE
193 --val;
194#endif
195#ifdef CONFIG_PPC_ISERIES
196 if (firmware_has_feature(FW_FEATURE_ISERIES) &&
197 get_lppaca()->shared_proc) {
198 get_lppaca()->virtual_decr = val;
199 if (get_dec() > val)
200 HvCall_setVirtualDecr();
201 return;
202 }
203#endif
204 mtspr(SPRN_DEC, val);
205#endif /* not 40x or 8xx_CPU6 */
206}
207
208static inline unsigned long tb_ticks_since(unsigned long tstamp)
209{
210 if (__USE_RTC()) {
211 int delta = get_rtcl() - (unsigned int) tstamp;
212 return delta < 0 ? delta + 1000000000 : delta;
213 }
214 return get_tbl() - tstamp;
215}
216
217#define mulhwu(x,y) \
218({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
219
220#ifdef CONFIG_PPC64
221#define mulhdu(x,y) \
222({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
223#else
224extern u64 mulhdu(u64, u64);
225#endif
226
227extern void smp_space_timers(unsigned int);
228
229extern unsigned mulhwu_scale_factor(unsigned, unsigned);
230extern void div128_by_32(u64 dividend_high, u64 dividend_low,
231 unsigned divisor, struct div_result *dr);
232
233/* Used to store Processor Utilization register (purr) values */
234
235struct cpu_usage {
236 u64 current_tb; /* Holds the current purr register values */
237};
238
239DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
240
241#if defined(CONFIG_VIRT_CPU_ACCOUNTING)
242extern void calculate_steal_time(void);
243extern void snapshot_timebases(void);
244#define account_process_vtime(tsk) account_process_tick(tsk, 0)
245#else
246#define calculate_steal_time() do { } while (0)
247#define snapshot_timebases() do { } while (0)
248#define account_process_vtime(tsk) do { } while (0)
249#endif
250
251extern void secondary_cpu_time_init(void);
252extern void iSeries_time_init_early(void);
253
254#endif /* __KERNEL__ */
255#endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h
new file mode 100644
index 000000000000..c55e14f7ef44
--- /dev/null
+++ b/arch/powerpc/include/asm/timex.h
@@ -0,0 +1,50 @@
1#ifndef _ASM_POWERPC_TIMEX_H
2#define _ASM_POWERPC_TIMEX_H
3
4#ifdef __KERNEL__
5
6/*
7 * PowerPC architecture timex specifications
8 */
9
10#include <asm/cputable.h>
11#include <asm/reg.h>
12
13#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
14
15typedef unsigned long cycles_t;
16
17static inline cycles_t get_cycles(void)
18{
19#ifdef __powerpc64__
20 return mftb();
21#else
22 cycles_t ret;
23
24 /*
25 * For the "cycle" counter we use the timebase lower half.
26 * Currently only used on SMP.
27 */
28
29 ret = 0;
30
31 __asm__ __volatile__(
32 "97: mftb %0\n"
33 "99:\n"
34 ".section __ftr_fixup,\"a\"\n"
35 ".align 2\n"
36 "98:\n"
37 " .long %1\n"
38 " .long 0\n"
39 " .long 97b-98b\n"
40 " .long 99b-98b\n"
41 " .long 0\n"
42 " .long 0\n"
43 ".previous"
44 : "=r" (ret) : "i" (CPU_FTR_601));
45 return ret;
46#endif
47}
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_TIMEX_H */
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
new file mode 100644
index 000000000000..e20ff7541f36
--- /dev/null
+++ b/arch/powerpc/include/asm/tlb.h
@@ -0,0 +1,81 @@
1/*
2 * TLB shootdown specifics for powerpc
3 *
4 * Copyright (C) 2002 Anton Blanchard, IBM Corp.
5 * Copyright (C) 2002 Paul Mackerras, IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef _ASM_POWERPC_TLB_H
13#define _ASM_POWERPC_TLB_H
14#ifdef __KERNEL__
15
16#ifndef __powerpc64__
17#include <asm/pgtable.h>
18#endif
19#include <asm/pgalloc.h>
20#include <asm/tlbflush.h>
21#ifndef __powerpc64__
22#include <asm/page.h>
23#include <asm/mmu.h>
24#endif
25
26#include <linux/pagemap.h>
27
28struct mmu_gather;
29
30#define tlb_start_vma(tlb, vma) do { } while (0)
31#define tlb_end_vma(tlb, vma) do { } while (0)
32
33#if !defined(CONFIG_PPC_STD_MMU)
34
35#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
36
37#elif defined(__powerpc64__)
38
39extern void pte_free_finish(void);
40
41static inline void tlb_flush(struct mmu_gather *tlb)
42{
43 struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
44
45 /* If there's a TLB batch pending, then we must flush it because the
46 * pages are going to be freed and we really don't want to have a CPU
47 * access a freed page because it has a stale TLB
48 */
49 if (tlbbatch->index)
50 __flush_tlb_pending(tlbbatch);
51
52 pte_free_finish();
53}
54
55#else
56
57extern void tlb_flush(struct mmu_gather *tlb);
58
59#endif
60
61/* Get the generic bits... */
62#include <asm-generic/tlb.h>
63
64#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
65
66#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
67
68#else
69extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
70 unsigned long address);
71
72static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
73 unsigned long address)
74{
75 if (pte_val(*ptep) & _PAGE_HASHPTE)
76 flush_hash_entry(tlb->mm, ptep, address);
77}
78
79#endif
80#endif /* __KERNEL__ */
81#endif /* __ASM_POWERPC_TLB_H */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
new file mode 100644
index 000000000000..361cd5c7a32b
--- /dev/null
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -0,0 +1,166 @@
1#ifndef _ASM_POWERPC_TLBFLUSH_H
2#define _ASM_POWERPC_TLBFLUSH_H
3
4/*
5 * TLB flushing:
6 *
7 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
8 * - flush_tlb_page(vma, vmaddr) flushes one page
9 * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
10 * - flush_tlb_range(vma, start, end) flushes a range of pages
11 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#ifdef __KERNEL__
19
20#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
21/*
22 * TLB flushing for software loaded TLB chips
23 *
24 * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
25 * flush_tlb_kernel_range are best implemented as tlbia vs
26 * specific tlbie's
27 */
28
29#include <linux/mm.h>
30
31extern void _tlbie(unsigned long address, unsigned int pid);
32
33#if defined(CONFIG_40x) || defined(CONFIG_8xx)
34#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
35#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
36extern void _tlbia(void);
37#endif
38
39static inline void flush_tlb_mm(struct mm_struct *mm)
40{
41 _tlbia();
42}
43
44static inline void flush_tlb_page(struct vm_area_struct *vma,
45 unsigned long vmaddr)
46{
47 _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
48}
49
50static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
51 unsigned long vmaddr)
52{
53 _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
54}
55
56static inline void flush_tlb_range(struct vm_area_struct *vma,
57 unsigned long start, unsigned long end)
58{
59 _tlbia();
60}
61
62static inline void flush_tlb_kernel_range(unsigned long start,
63 unsigned long end)
64{
65 _tlbia();
66}
67
68#elif defined(CONFIG_PPC32)
69/*
70 * TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
71 */
72extern void _tlbie(unsigned long address);
73extern void _tlbia(void);
74
75extern void flush_tlb_mm(struct mm_struct *mm);
76extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
77extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
78extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
79 unsigned long end);
80extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
81
82#else
83/*
84 * TLB flushing for 64-bit has-MMU CPUs
85 */
86
87#include <linux/percpu.h>
88#include <asm/page.h>
89
90#define PPC64_TLB_BATCH_NR 192
91
92struct ppc64_tlb_batch {
93 int active;
94 unsigned long index;
95 struct mm_struct *mm;
96 real_pte_t pte[PPC64_TLB_BATCH_NR];
97 unsigned long vaddr[PPC64_TLB_BATCH_NR];
98 unsigned int psize;
99 int ssize;
100};
101DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
102
103extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
104
105extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
106 pte_t *ptep, unsigned long pte, int huge);
107
108#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
109
110static inline void arch_enter_lazy_mmu_mode(void)
111{
112 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
113
114 batch->active = 1;
115}
116
117static inline void arch_leave_lazy_mmu_mode(void)
118{
119 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
120
121 if (batch->index)
122 __flush_tlb_pending(batch);
123 batch->active = 0;
124}
125
126#define arch_flush_lazy_mmu_mode() do {} while (0)
127
128
129extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
130 int ssize, int local);
131extern void flush_hash_range(unsigned long number, int local);
132
133
134static inline void flush_tlb_mm(struct mm_struct *mm)
135{
136}
137
138static inline void flush_tlb_page(struct vm_area_struct *vma,
139 unsigned long vmaddr)
140{
141}
142
143static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
144 unsigned long vmaddr)
145{
146}
147
148static inline void flush_tlb_range(struct vm_area_struct *vma,
149 unsigned long start, unsigned long end)
150{
151}
152
153static inline void flush_tlb_kernel_range(unsigned long start,
154 unsigned long end)
155{
156}
157
158/* Private function for use by PCI IO mapping code */
159extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
160 unsigned long end);
161
162
163#endif
164
165#endif /*__KERNEL__ */
166#endif /* _ASM_POWERPC_TLBFLUSH_H */
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
new file mode 100644
index 000000000000..c32da6f97999
--- /dev/null
+++ b/arch/powerpc/include/asm/topology.h
@@ -0,0 +1,117 @@
1#ifndef _ASM_POWERPC_TOPOLOGY_H
2#define _ASM_POWERPC_TOPOLOGY_H
3#ifdef __KERNEL__
4
5
6struct sys_device;
7struct device_node;
8
9#ifdef CONFIG_NUMA
10
11#include <asm/mmzone.h>
12
13static inline int cpu_to_node(int cpu)
14{
15 return numa_cpu_lookup_table[cpu];
16}
17
18#define parent_node(node) (node)
19
20static inline cpumask_t node_to_cpumask(int node)
21{
22 return numa_cpumask_lookup_table[node];
23}
24
25static inline int node_to_first_cpu(int node)
26{
27 cpumask_t tmp;
28 tmp = node_to_cpumask(node);
29 return first_cpu(tmp);
30}
31
32int of_node_to_nid(struct device_node *device);
33
34struct pci_bus;
35#ifdef CONFIG_PCI
36extern int pcibus_to_node(struct pci_bus *bus);
37#else
38static inline int pcibus_to_node(struct pci_bus *bus)
39{
40 return -1;
41}
42#endif
43
44#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
45 CPU_MASK_ALL : \
46 node_to_cpumask(pcibus_to_node(bus)) \
47 )
48
49/* sched_domains SD_NODE_INIT for PPC64 machines */
50#define SD_NODE_INIT (struct sched_domain) { \
51 .span = CPU_MASK_NONE, \
52 .parent = NULL, \
53 .child = NULL, \
54 .groups = NULL, \
55 .min_interval = 8, \
56 .max_interval = 32, \
57 .busy_factor = 32, \
58 .imbalance_pct = 125, \
59 .cache_nice_tries = 1, \
60 .busy_idx = 3, \
61 .idle_idx = 1, \
62 .newidle_idx = 2, \
63 .wake_idx = 1, \
64 .flags = SD_LOAD_BALANCE \
65 | SD_BALANCE_EXEC \
66 | SD_BALANCE_NEWIDLE \
67 | SD_WAKE_IDLE \
68 | SD_SERIALIZE \
69 | SD_WAKE_BALANCE, \
70 .last_balance = jiffies, \
71 .balance_interval = 1, \
72 .nr_balance_failed = 0, \
73}
74
75extern void __init dump_numa_cpu_topology(void);
76
77extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
78extern void sysfs_remove_device_from_node(struct sys_device *dev, int nid);
79
80#else
81
82static inline int of_node_to_nid(struct device_node *device)
83{
84 return 0;
85}
86
87static inline void dump_numa_cpu_topology(void) {}
88
89static inline int sysfs_add_device_to_node(struct sys_device *dev, int nid)
90{
91 return 0;
92}
93
94static inline void sysfs_remove_device_from_node(struct sys_device *dev,
95 int nid)
96{
97}
98
99#endif /* CONFIG_NUMA */
100
101#include <asm-generic/topology.h>
102
103#ifdef CONFIG_SMP
104#include <asm/cputable.h>
105#define smt_capable() (cpu_has_feature(CPU_FTR_SMT))
106
107#ifdef CONFIG_PPC64
108#include <asm/smp.h>
109
110#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
111#define topology_core_siblings(cpu) (per_cpu(cpu_core_map, cpu))
112#define topology_core_id(cpu) (cpu_to_core_id(cpu))
113#endif
114#endif
115
116#endif /* __KERNEL__ */
117#endif /* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/arch/powerpc/include/asm/tsi108.h b/arch/powerpc/include/asm/tsi108.h
new file mode 100644
index 000000000000..f8b60793b7a9
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108.h
@@ -0,0 +1,121 @@
1/*
2 * common routine and memory layout for Tundra TSI108(Grendel) host bridge
3 * memory controller.
4 *
5 * Author: Jacob Pan (jacob.pan@freescale.com)
6 * Alex Bounine (alexandreb@tundra.com)
7 *
8 * Copyright 2004-2006 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef __PPC_KERNEL_TSI108_H
17#define __PPC_KERNEL_TSI108_H
18
19#include <asm/pci-bridge.h>
20
21/* Size of entire register space */
22#define TSI108_REG_SIZE (0x10000)
23
24/* Sizes of register spaces for individual blocks */
25#define TSI108_HLP_SIZE 0x1000
26#define TSI108_PCI_SIZE 0x1000
27#define TSI108_CLK_SIZE 0x1000
28#define TSI108_PB_SIZE 0x1000
29#define TSI108_SD_SIZE 0x1000
30#define TSI108_DMA_SIZE 0x1000
31#define TSI108_ETH_SIZE 0x1000
32#define TSI108_I2C_SIZE 0x400
33#define TSI108_MPIC_SIZE 0x400
34#define TSI108_UART0_SIZE 0x200
35#define TSI108_GPIO_SIZE 0x200
36#define TSI108_UART1_SIZE 0x200
37
38/* Offsets within Tsi108(A) CSR space for individual blocks */
39#define TSI108_HLP_OFFSET 0x0000
40#define TSI108_PCI_OFFSET 0x1000
41#define TSI108_CLK_OFFSET 0x2000
42#define TSI108_PB_OFFSET 0x3000
43#define TSI108_SD_OFFSET 0x4000
44#define TSI108_DMA_OFFSET 0x5000
45#define TSI108_ETH_OFFSET 0x6000
46#define TSI108_I2C_OFFSET 0x7000
47#define TSI108_MPIC_OFFSET 0x7400
48#define TSI108_UART0_OFFSET 0x7800
49#define TSI108_GPIO_OFFSET 0x7A00
50#define TSI108_UART1_OFFSET 0x7C00
51
52/* Tsi108 registers used by common code components */
53#define TSI108_PCI_CSR (0x004)
54#define TSI108_PCI_IRP_CFG_CTL (0x180)
55#define TSI108_PCI_IRP_STAT (0x184)
56#define TSI108_PCI_IRP_ENABLE (0x188)
57#define TSI108_PCI_IRP_INTAD (0x18C)
58
59#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
60#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
61
62#define TSI108_CG_PWRUP_STATUS (0x234)
63
64#define TSI108_PB_ISR (0x00C)
65#define TSI108_PB_ERRCS (0x404)
66#define TSI108_PB_AERR (0x408)
67
68#define TSI108_PB_ERRCS_ES (1 << 1)
69#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
70
71#define TSI108_PCI_CFG_SIZE (0x01000000)
72
73/*
74 * PHY Configuration Options
75 *
76 * Specify "bcm54xx" in the compatible property of your device tree phy
77 * nodes if your board uses the Broadcom PHYs
78 */
79#define TSI108_PHY_MV88E 0 /* Marvel 88Exxxx PHY */
80#define TSI108_PHY_BCM54XX 1 /* Broardcom BCM54xx PHY */
81
82/* Global variables */
83
84extern u32 tsi108_pci_cfg_base;
85/* Exported functions */
86
87extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
88extern unsigned long tsi108_get_mem_size(void);
89extern unsigned long tsi108_get_cpu_clk(void);
90extern unsigned long tsi108_get_sdc_clk(void);
91extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
92 int offset, int len, u32 val);
93extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
94 int offset, int len, u32 * val);
95extern void tsi108_clear_pci_error(u32 pci_cfg_base);
96
97extern phys_addr_t get_csrbase(void);
98
99typedef struct {
100 u32 regs; /* hw registers base address */
101 u32 phyregs; /* phy registers base address */
102 u16 phy; /* phy address */
103 u16 irq_num; /* irq number */
104 u8 mac_addr[6]; /* phy mac address */
105 u16 phy_type; /* type of phy on board */
106} hw_info;
107
108extern u32 get_vir_csrbase(void);
109extern u32 tsi108_csr_vir_base;
110
111static inline u32 tsi108_read_reg(u32 reg_offset)
112{
113 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
114}
115
116static inline void tsi108_write_reg(u32 reg_offset, u32 val)
117{
118 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
119}
120
121#endif /* __PPC_KERNEL_TSI108_H */
diff --git a/arch/powerpc/include/asm/tsi108_irq.h b/arch/powerpc/include/asm/tsi108_irq.h
new file mode 100644
index 000000000000..6ed93979fbe4
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108_irq.h
@@ -0,0 +1,124 @@
1/*
2 * (C) Copyright 2005 Tundra Semiconductor Corp.
3 * Alex Bounine, <alexandreb at tundra.com).
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * definitions for interrupt controller initialization and external interrupt
26 * demultiplexing on TSI108EMU/SVB boards.
27 */
28
29#ifndef _ASM_POWERPC_TSI108_IRQ_H
30#define _ASM_POWERPC_TSI108_IRQ_H
31
32/*
33 * Tsi108 interrupts
34 */
35#ifndef TSI108_IRQ_REG_BASE
36#define TSI108_IRQ_REG_BASE 0
37#endif
38
39#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
40
41#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
42#define MAX_TASK_PRIO 0xF
43
44#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
45
46#define DEFAULT_PRIO_LVL 10 /* initial priority level */
47
48/* Interrupt vectors assignment to external and internal
49 * sources of requests. */
50
51/* EXTERNAL INTERRUPT SOURCES */
52
53#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
54#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
55#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
56#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
57
58/* INTERNAL INTERRUPT SOURCES */
59
60#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
61#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
62#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
63#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
64#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
65#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
66#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
67#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
68#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
69#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
70#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
71#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
72#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
73#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
74#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
75#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
76#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
77#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
78#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
79#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
80
81#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
82#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
83#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
84#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
85
86#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
87#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
88#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
89#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
90
91#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
92#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
93#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
94#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
95
96/*
97 * PCI bus INTA# - INTD# lines demultiplexor
98 */
99#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
100#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
101#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
102#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
103#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
104#define NUM_PCI_IRQS (4)
105
106/* number of entries in vector dispatch table */
107#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
108
109/* Mapping of MPIC outputs to processors' interrupt pins */
110
111#define IDIR_INT_OUT0 0x1
112#define IDIR_INT_OUT1 0x2
113#define IDIR_INT_OUT2 0x4
114#define IDIR_INT_OUT3 0x8
115
116/*---------------------------------------------------------------
117 * IRQ line configuration parameters */
118
119/* Interrupt delivery modes */
120typedef enum {
121 TSI108_IRQ_DIRECTED,
122 TSI108_IRQ_DISTRIBUTED,
123} TSI108_IRQ_MODE;
124#endif /* _ASM_POWERPC_TSI108_IRQ_H */
diff --git a/arch/powerpc/include/asm/tsi108_pci.h b/arch/powerpc/include/asm/tsi108_pci.h
new file mode 100644
index 000000000000..5653d7cc3e24
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108_pci.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2007 IBM Corp
3 *
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TSI108_PCI_H
22#define _ASM_POWERPC_TSI108_PCI_H
23
24#include <asm/tsi108.h>
25
26/* Register definitions */
27#define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
28#define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
29#define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
30#define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
31#define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
32#define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
33#define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
34#define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
35#define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
36#define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
37#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
38#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
39
40extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
41extern void tsi108_pci_int_init(struct device_node *node);
42extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
43extern void tsi108_clear_pci_cfg_error(void);
44
45#endif /* _ASM_POWERPC_TSI108_PCI_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
new file mode 100644
index 000000000000..d3374bc865ba
--- /dev/null
+++ b/arch/powerpc/include/asm/types.h
@@ -0,0 +1,75 @@
1#ifndef _ASM_POWERPC_TYPES_H
2#define _ASM_POWERPC_TYPES_H
3
4#ifdef __powerpc64__
5# include <asm-generic/int-l64.h>
6#else
7# include <asm-generic/int-ll64.h>
8#endif
9
10#ifndef __ASSEMBLY__
11
12/*
13 * This file is never included by application software unless
14 * explicitly requested (e.g., via linux/types.h) in which case the
15 * application is Linux specific so (user-) name space pollution is
16 * not a major issue. However, for interoperability, libraries still
17 * need to be careful to avoid a name clashes.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24
25#ifdef __powerpc64__
26typedef unsigned int umode_t;
27#else
28typedef unsigned short umode_t;
29#endif
30
31typedef struct {
32 __u32 u[4];
33} __attribute__((aligned(16))) __vector128;
34
35#endif /* __ASSEMBLY__ */
36
37#ifdef __KERNEL__
38/*
39 * These aren't exported outside the kernel to avoid name space clashes
40 */
41#ifdef __powerpc64__
42#define BITS_PER_LONG 64
43#else
44#define BITS_PER_LONG 32
45#endif
46
47#ifndef __ASSEMBLY__
48
49typedef __vector128 vector128;
50
51/* Physical address used by some IO functions */
52#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
53typedef u64 phys_addr_t;
54#else
55typedef u32 phys_addr_t;
56#endif
57
58#ifdef __powerpc64__
59typedef u64 dma_addr_t;
60#else
61typedef u32 dma_addr_t;
62#endif
63typedef u64 dma64_addr_t;
64
65typedef struct {
66 unsigned long entry;
67 unsigned long toc;
68 unsigned long env;
69} func_descr_t;
70
71#endif /* __ASSEMBLY__ */
72
73#endif /* __KERNEL__ */
74
75#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
new file mode 100644
index 000000000000..bd0fb8495154
--- /dev/null
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -0,0 +1,496 @@
1#ifndef _ARCH_POWERPC_UACCESS_H
2#define _ARCH_POWERPC_UACCESS_H
3
4#ifdef __KERNEL__
5#ifndef __ASSEMBLY__
6
7#include <linux/sched.h>
8#include <linux/errno.h>
9#include <asm/asm-compat.h>
10#include <asm/processor.h>
11#include <asm/page.h>
12
13#define VERIFY_READ 0
14#define VERIFY_WRITE 1
15
16/*
17 * The fs value determines whether argument validity checking should be
18 * performed or not. If get_fs() == USER_DS, checking is performed, with
19 * get_fs() == KERNEL_DS, checking is bypassed.
20 *
21 * For historical reasons, these macros are grossly misnamed.
22 *
23 * The fs/ds values are now the highest legal address in the "segment".
24 * This simplifies the checking in the routines below.
25 */
26
27#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
28
29#define KERNEL_DS MAKE_MM_SEG(~0UL)
30#ifdef __powerpc64__
31/* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */
32#define USER_DS MAKE_MM_SEG(TASK_SIZE_USER64 - 1)
33#else
34#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1)
35#endif
36
37#define get_ds() (KERNEL_DS)
38#define get_fs() (current->thread.fs)
39#define set_fs(val) (current->thread.fs = (val))
40
41#define segment_eq(a, b) ((a).seg == (b).seg)
42
43#ifdef __powerpc64__
44/*
45 * This check is sufficient because there is a large enough
46 * gap between user addresses and the kernel addresses
47 */
48#define __access_ok(addr, size, segment) \
49 (((addr) <= (segment).seg) && ((size) <= (segment).seg))
50
51#else
52
53#define __access_ok(addr, size, segment) \
54 (((addr) <= (segment).seg) && \
55 (((size) == 0) || (((size) - 1) <= ((segment).seg - (addr)))))
56
57#endif
58
59#define access_ok(type, addr, size) \
60 (__chk_user_ptr(addr), \
61 __access_ok((__force unsigned long)(addr), (size), get_fs()))
62
63/*
64 * The exception table consists of pairs of addresses: the first is the
65 * address of an instruction that is allowed to fault, and the second is
66 * the address at which the program should continue. No registers are
67 * modified, so it is entirely up to the continuation code to figure out
68 * what to do.
69 *
70 * All the routines below use bits of fixup code that are out of line
71 * with the main instruction path. This means when everything is well,
72 * we don't even have to jump over them. Further, they do not intrude
73 * on our cache or tlb entries.
74 */
75
76struct exception_table_entry {
77 unsigned long insn;
78 unsigned long fixup;
79};
80
81/*
82 * These are the main single-value transfer routines. They automatically
83 * use the right size if we just have the right pointer type.
84 *
85 * This gets kind of ugly. We want to return _two_ values in "get_user()"
86 * and yet we don't want to do any pointers, because that is too much
87 * of a performance impact. Thus we have a few rather ugly macros here,
88 * and hide all the ugliness from the user.
89 *
90 * The "__xxx" versions of the user access functions are versions that
91 * do not verify the address space, that must have been done previously
92 * with a separate "access_ok()" call (this is used when we do multiple
93 * accesses to the same area of user memory).
94 *
95 * As we use the same address space for kernel and user data on the
96 * PowerPC, we can just do these as direct assignments. (Of course, the
97 * exception handling means that it's no longer "just"...)
98 *
99 * The "user64" versions of the user access functions are versions that
100 * allow access of 64-bit data. The "get_user" functions do not
101 * properly handle 64-bit data because the value gets down cast to a long.
102 * The "put_user" functions already handle 64-bit data properly but we add
103 * "user64" versions for completeness
104 */
105#define get_user(x, ptr) \
106 __get_user_check((x), (ptr), sizeof(*(ptr)))
107#define put_user(x, ptr) \
108 __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
109
110#define __get_user(x, ptr) \
111 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
112#define __put_user(x, ptr) \
113 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
114
115#ifndef __powerpc64__
116#define __get_user64(x, ptr) \
117 __get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
118#define __put_user64(x, ptr) __put_user(x, ptr)
119#endif
120
121#define __get_user_inatomic(x, ptr) \
122 __get_user_nosleep((x), (ptr), sizeof(*(ptr)))
123#define __put_user_inatomic(x, ptr) \
124 __put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
125
126#define __get_user_unaligned __get_user
127#define __put_user_unaligned __put_user
128
129extern long __put_user_bad(void);
130
131/*
132 * We don't tell gcc that we are accessing memory, but this is OK
133 * because we do not write to any memory gcc knows about, so there
134 * are no aliasing issues.
135 */
136#define __put_user_asm(x, addr, err, op) \
137 __asm__ __volatile__( \
138 "1: " op " %1,0(%2) # put_user\n" \
139 "2:\n" \
140 ".section .fixup,\"ax\"\n" \
141 "3: li %0,%3\n" \
142 " b 2b\n" \
143 ".previous\n" \
144 ".section __ex_table,\"a\"\n" \
145 PPC_LONG_ALIGN "\n" \
146 PPC_LONG "1b,3b\n" \
147 ".previous" \
148 : "=r" (err) \
149 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
150
151#ifdef __powerpc64__
152#define __put_user_asm2(x, ptr, retval) \
153 __put_user_asm(x, ptr, retval, "std")
154#else /* __powerpc64__ */
155#define __put_user_asm2(x, addr, err) \
156 __asm__ __volatile__( \
157 "1: stw %1,0(%2)\n" \
158 "2: stw %1+1,4(%2)\n" \
159 "3:\n" \
160 ".section .fixup,\"ax\"\n" \
161 "4: li %0,%3\n" \
162 " b 3b\n" \
163 ".previous\n" \
164 ".section __ex_table,\"a\"\n" \
165 PPC_LONG_ALIGN "\n" \
166 PPC_LONG "1b,4b\n" \
167 PPC_LONG "2b,4b\n" \
168 ".previous" \
169 : "=r" (err) \
170 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
171#endif /* __powerpc64__ */
172
173#define __put_user_size(x, ptr, size, retval) \
174do { \
175 retval = 0; \
176 switch (size) { \
177 case 1: __put_user_asm(x, ptr, retval, "stb"); break; \
178 case 2: __put_user_asm(x, ptr, retval, "sth"); break; \
179 case 4: __put_user_asm(x, ptr, retval, "stw"); break; \
180 case 8: __put_user_asm2(x, ptr, retval); break; \
181 default: __put_user_bad(); \
182 } \
183} while (0)
184
185#define __put_user_nocheck(x, ptr, size) \
186({ \
187 long __pu_err; \
188 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
189 if (!is_kernel_addr((unsigned long)__pu_addr)) \
190 might_sleep(); \
191 __chk_user_ptr(ptr); \
192 __put_user_size((x), __pu_addr, (size), __pu_err); \
193 __pu_err; \
194})
195
196#define __put_user_check(x, ptr, size) \
197({ \
198 long __pu_err = -EFAULT; \
199 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
200 might_sleep(); \
201 if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
202 __put_user_size((x), __pu_addr, (size), __pu_err); \
203 __pu_err; \
204})
205
206#define __put_user_nosleep(x, ptr, size) \
207({ \
208 long __pu_err; \
209 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
210 __chk_user_ptr(ptr); \
211 __put_user_size((x), __pu_addr, (size), __pu_err); \
212 __pu_err; \
213})
214
215
216extern long __get_user_bad(void);
217
218#define __get_user_asm(x, addr, err, op) \
219 __asm__ __volatile__( \
220 "1: "op" %1,0(%2) # get_user\n" \
221 "2:\n" \
222 ".section .fixup,\"ax\"\n" \
223 "3: li %0,%3\n" \
224 " li %1,0\n" \
225 " b 2b\n" \
226 ".previous\n" \
227 ".section __ex_table,\"a\"\n" \
228 PPC_LONG_ALIGN "\n" \
229 PPC_LONG "1b,3b\n" \
230 ".previous" \
231 : "=r" (err), "=r" (x) \
232 : "b" (addr), "i" (-EFAULT), "0" (err))
233
234#ifdef __powerpc64__
235#define __get_user_asm2(x, addr, err) \
236 __get_user_asm(x, addr, err, "ld")
237#else /* __powerpc64__ */
238#define __get_user_asm2(x, addr, err) \
239 __asm__ __volatile__( \
240 "1: lwz %1,0(%2)\n" \
241 "2: lwz %1+1,4(%2)\n" \
242 "3:\n" \
243 ".section .fixup,\"ax\"\n" \
244 "4: li %0,%3\n" \
245 " li %1,0\n" \
246 " li %1+1,0\n" \
247 " b 3b\n" \
248 ".previous\n" \
249 ".section __ex_table,\"a\"\n" \
250 PPC_LONG_ALIGN "\n" \
251 PPC_LONG "1b,4b\n" \
252 PPC_LONG "2b,4b\n" \
253 ".previous" \
254 : "=r" (err), "=&r" (x) \
255 : "b" (addr), "i" (-EFAULT), "0" (err))
256#endif /* __powerpc64__ */
257
258#define __get_user_size(x, ptr, size, retval) \
259do { \
260 retval = 0; \
261 __chk_user_ptr(ptr); \
262 if (size > sizeof(x)) \
263 (x) = __get_user_bad(); \
264 switch (size) { \
265 case 1: __get_user_asm(x, ptr, retval, "lbz"); break; \
266 case 2: __get_user_asm(x, ptr, retval, "lhz"); break; \
267 case 4: __get_user_asm(x, ptr, retval, "lwz"); break; \
268 case 8: __get_user_asm2(x, ptr, retval); break; \
269 default: (x) = __get_user_bad(); \
270 } \
271} while (0)
272
273#define __get_user_nocheck(x, ptr, size) \
274({ \
275 long __gu_err; \
276 unsigned long __gu_val; \
277 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
278 __chk_user_ptr(ptr); \
279 if (!is_kernel_addr((unsigned long)__gu_addr)) \
280 might_sleep(); \
281 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
282 (x) = (__typeof__(*(ptr)))__gu_val; \
283 __gu_err; \
284})
285
286#ifndef __powerpc64__
287#define __get_user64_nocheck(x, ptr, size) \
288({ \
289 long __gu_err; \
290 long long __gu_val; \
291 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
292 __chk_user_ptr(ptr); \
293 if (!is_kernel_addr((unsigned long)__gu_addr)) \
294 might_sleep(); \
295 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
296 (x) = (__typeof__(*(ptr)))__gu_val; \
297 __gu_err; \
298})
299#endif /* __powerpc64__ */
300
301#define __get_user_check(x, ptr, size) \
302({ \
303 long __gu_err = -EFAULT; \
304 unsigned long __gu_val = 0; \
305 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
306 might_sleep(); \
307 if (access_ok(VERIFY_READ, __gu_addr, (size))) \
308 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
309 (x) = (__typeof__(*(ptr)))__gu_val; \
310 __gu_err; \
311})
312
313#define __get_user_nosleep(x, ptr, size) \
314({ \
315 long __gu_err; \
316 unsigned long __gu_val; \
317 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
318 __chk_user_ptr(ptr); \
319 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
320 (x) = (__typeof__(*(ptr)))__gu_val; \
321 __gu_err; \
322})
323
324
325/* more complex routines */
326
327extern unsigned long __copy_tofrom_user(void __user *to,
328 const void __user *from, unsigned long size);
329
330#ifndef __powerpc64__
331
332static inline unsigned long copy_from_user(void *to,
333 const void __user *from, unsigned long n)
334{
335 unsigned long over;
336
337 if (access_ok(VERIFY_READ, from, n))
338 return __copy_tofrom_user((__force void __user *)to, from, n);
339 if ((unsigned long)from < TASK_SIZE) {
340 over = (unsigned long)from + n - TASK_SIZE;
341 return __copy_tofrom_user((__force void __user *)to, from,
342 n - over) + over;
343 }
344 return n;
345}
346
347static inline unsigned long copy_to_user(void __user *to,
348 const void *from, unsigned long n)
349{
350 unsigned long over;
351
352 if (access_ok(VERIFY_WRITE, to, n))
353 return __copy_tofrom_user(to, (__force void __user *)from, n);
354 if ((unsigned long)to < TASK_SIZE) {
355 over = (unsigned long)to + n - TASK_SIZE;
356 return __copy_tofrom_user(to, (__force void __user *)from,
357 n - over) + over;
358 }
359 return n;
360}
361
362#else /* __powerpc64__ */
363
364#define __copy_in_user(to, from, size) \
365 __copy_tofrom_user((to), (from), (size))
366
367extern unsigned long copy_from_user(void *to, const void __user *from,
368 unsigned long n);
369extern unsigned long copy_to_user(void __user *to, const void *from,
370 unsigned long n);
371extern unsigned long copy_in_user(void __user *to, const void __user *from,
372 unsigned long n);
373
374#endif /* __powerpc64__ */
375
376static inline unsigned long __copy_from_user_inatomic(void *to,
377 const void __user *from, unsigned long n)
378{
379 if (__builtin_constant_p(n) && (n <= 8)) {
380 unsigned long ret = 1;
381
382 switch (n) {
383 case 1:
384 __get_user_size(*(u8 *)to, from, 1, ret);
385 break;
386 case 2:
387 __get_user_size(*(u16 *)to, from, 2, ret);
388 break;
389 case 4:
390 __get_user_size(*(u32 *)to, from, 4, ret);
391 break;
392 case 8:
393 __get_user_size(*(u64 *)to, from, 8, ret);
394 break;
395 }
396 if (ret == 0)
397 return 0;
398 }
399 return __copy_tofrom_user((__force void __user *)to, from, n);
400}
401
402static inline unsigned long __copy_to_user_inatomic(void __user *to,
403 const void *from, unsigned long n)
404{
405 if (__builtin_constant_p(n) && (n <= 8)) {
406 unsigned long ret = 1;
407
408 switch (n) {
409 case 1:
410 __put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret);
411 break;
412 case 2:
413 __put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret);
414 break;
415 case 4:
416 __put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret);
417 break;
418 case 8:
419 __put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret);
420 break;
421 }
422 if (ret == 0)
423 return 0;
424 }
425 return __copy_tofrom_user(to, (__force const void __user *)from, n);
426}
427
428static inline unsigned long __copy_from_user(void *to,
429 const void __user *from, unsigned long size)
430{
431 might_sleep();
432 return __copy_from_user_inatomic(to, from, size);
433}
434
435static inline unsigned long __copy_to_user(void __user *to,
436 const void *from, unsigned long size)
437{
438 might_sleep();
439 return __copy_to_user_inatomic(to, from, size);
440}
441
442extern unsigned long __clear_user(void __user *addr, unsigned long size);
443
444static inline unsigned long clear_user(void __user *addr, unsigned long size)
445{
446 might_sleep();
447 if (likely(access_ok(VERIFY_WRITE, addr, size)))
448 return __clear_user(addr, size);
449 if ((unsigned long)addr < TASK_SIZE) {
450 unsigned long over = (unsigned long)addr + size - TASK_SIZE;
451 return __clear_user(addr, size - over) + over;
452 }
453 return size;
454}
455
456extern int __strncpy_from_user(char *dst, const char __user *src, long count);
457
458static inline long strncpy_from_user(char *dst, const char __user *src,
459 long count)
460{
461 might_sleep();
462 if (likely(access_ok(VERIFY_READ, src, 1)))
463 return __strncpy_from_user(dst, src, count);
464 return -EFAULT;
465}
466
467/*
468 * Return the size of a string (including the ending 0)
469 *
470 * Return 0 for error
471 */
472extern int __strnlen_user(const char __user *str, long len, unsigned long top);
473
474/*
475 * Returns the length of the string at str (including the null byte),
476 * or 0 if we hit a page we can't access,
477 * or something > len if we didn't find a null byte.
478 *
479 * The `top' parameter to __strnlen_user is to make sure that
480 * we can never overflow from the user area into kernel space.
481 */
482static inline int strnlen_user(const char __user *str, long len)
483{
484 unsigned long top = current->thread.fs.seg;
485
486 if ((unsigned long)str > top)
487 return 0;
488 return __strnlen_user(str, len, top);
489}
490
491#define strlen_user(str) strnlen_user((str), 0x7ffffffe)
492
493#endif /* __ASSEMBLY__ */
494#endif /* __KERNEL__ */
495
496#endif /* _ARCH_POWERPC_UACCESS_H */
diff --git a/arch/powerpc/include/asm/ucc.h b/arch/powerpc/include/asm/ucc.h
new file mode 100644
index 000000000000..46b09ba6bead
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_H__
16#define __UCC_H__
17
18#include <asm/immap_qe.h>
19#include <asm/qe.h>
20
21#define STATISTICS
22
23#define UCC_MAX_NUM 8
24
25/* Slow or fast type for UCCs.
26*/
27enum ucc_speed_type {
28 UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
29 UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
30};
31
32/* ucc_set_type
33 * Sets UCC to slow or fast mode.
34 *
35 * ucc_num - (In) number of UCC (0-7).
36 * speed - (In) slow or fast mode for UCC.
37 */
38int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
39
40int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
41
42int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
43 enum comm_dir mode);
44
45int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
46
47/* QE MUX clock routing for UCC
48*/
49static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
50{
51 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
52}
53
54static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
55{
56 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
57}
58
59static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
60{
61 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
62}
63
64#endif /* __UCC_H__ */
diff --git a/arch/powerpc/include/asm/ucc_fast.h b/arch/powerpc/include/asm/ucc_fast.h
new file mode 100644
index 000000000000..839aab8bf37d
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc_fast.h
@@ -0,0 +1,244 @@
1/*
2 * Internal header file for UCC FAST unit routines.
3 *
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
5 *
6 * Authors: Shlomi Gridish <gridish@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#ifndef __UCC_FAST_H__
15#define __UCC_FAST_H__
16
17#include <linux/kernel.h>
18
19#include <asm/immap_qe.h>
20#include <asm/qe.h>
21
22#include "ucc.h"
23
24/* Receive BD's status */
25#define R_E 0x80000000 /* buffer empty */
26#define R_W 0x20000000 /* wrap bit */
27#define R_I 0x10000000 /* interrupt on reception */
28#define R_L 0x08000000 /* last */
29#define R_F 0x04000000 /* first */
30
31/* transmit BD's status */
32#define T_R 0x80000000 /* ready bit */
33#define T_W 0x20000000 /* wrap bit */
34#define T_I 0x10000000 /* interrupt on completion */
35#define T_L 0x08000000 /* last */
36
37/* Rx Data buffer must be 4 bytes aligned in most cases */
38#define UCC_FAST_RX_ALIGN 4
39#define UCC_FAST_MRBLR_ALIGNMENT 4
40#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
41
42/* Sizes */
43#define UCC_FAST_URFS_MIN_VAL 0x88
44#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
45
46/* ucc_fast_channel_protocol_mode - UCC FAST mode */
47enum ucc_fast_channel_protocol_mode {
48 UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
49 UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
50 UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
51 UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
52 UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
53 UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
54 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
55 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
56 UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
57 UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
58 UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
59 UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
60 UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
61 UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
62 UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
63 UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
64};
65
66/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
67enum ucc_fast_transparent_txrx {
68 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
69 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
70};
71
72/* UCC fast diagnostic mode */
73enum ucc_fast_diag_mode {
74 UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
75 UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
76 UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
77 UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
78};
79
80/* UCC fast Sync length (transparent mode only) */
81enum ucc_fast_sync_len {
82 UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
83 UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
84 UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
85 UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
86};
87
88/* UCC fast RTS mode */
89enum ucc_fast_ready_to_send {
90 UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
91 UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
92};
93
94/* UCC fast receiver decoding mode */
95enum ucc_fast_rx_decoding_method {
96 UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
97 UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
98 UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
99 UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
100};
101
102/* UCC fast transmitter encoding mode */
103enum ucc_fast_tx_encoding_method {
104 UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
105 UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
106 UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
107 UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
108};
109
110/* UCC fast CRC length */
111enum ucc_fast_transparent_tcrc {
112 UCC_FAST_16_BIT_CRC = 0x00000000,
113 UCC_FAST_CRC_RESERVED0 = 0x00000040,
114 UCC_FAST_32_BIT_CRC = 0x00000080,
115 UCC_FAST_CRC_RESERVED1 = 0x000000C0
116};
117
118/* Fast UCC initialization structure */
119struct ucc_fast_info {
120 int ucc_num;
121 enum qe_clock rx_clock;
122 enum qe_clock tx_clock;
123 u32 regs;
124 int irq;
125 u32 uccm_mask;
126 int bd_mem_part;
127 int brkpt_support;
128 int grant_support;
129 int tsa;
130 int cdp;
131 int cds;
132 int ctsp;
133 int ctss;
134 int tci;
135 int txsy;
136 int rtsm;
137 int revd;
138 int rsyn;
139 u16 max_rx_buf_length;
140 u16 urfs;
141 u16 urfet;
142 u16 urfset;
143 u16 utfs;
144 u16 utfet;
145 u16 utftt;
146 u16 ufpt;
147 enum ucc_fast_channel_protocol_mode mode;
148 enum ucc_fast_transparent_txrx ttx_trx;
149 enum ucc_fast_tx_encoding_method tenc;
150 enum ucc_fast_rx_decoding_method renc;
151 enum ucc_fast_transparent_tcrc tcrc;
152 enum ucc_fast_sync_len synl;
153};
154
155struct ucc_fast_private {
156 struct ucc_fast_info *uf_info;
157 struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
158 u32 __iomem *p_ucce; /* a pointer to the event register in memory. */
159 u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
160#ifdef CONFIG_UGETH_TX_ON_DEMAND
161 u16 __iomem *p_utodr; /* pointer to the transmit on demand register */
162#endif
163 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
164 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
165 int stopped_tx; /* Whether channel has been stopped for Tx
166 (STOP_TX, etc.) */
167 int stopped_rx; /* Whether channel has been stopped for Rx */
168 u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
169 virtual fifo */
170 u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
171 virtual fifo */
172#ifdef STATISTICS
173 u32 tx_frames; /* Transmitted frames counter. */
174 u32 rx_frames; /* Received frames counter (only frames
175 passed to application). */
176 u32 tx_discarded; /* Discarded tx frames counter (frames that
177 were discarded by the driver due to errors).
178 */
179 u32 rx_discarded; /* Discarded rx frames counter (frames that
180 were discarded by the driver due to errors).
181 */
182#endif /* STATISTICS */
183 u16 mrblr; /* maximum receive buffer length */
184};
185
186/* ucc_fast_init
187 * Initializes Fast UCC according to user provided parameters.
188 *
189 * uf_info - (In) pointer to the fast UCC info structure.
190 * uccf_ret - (Out) pointer to the fast UCC structure.
191 */
192int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
193
194/* ucc_fast_free
195 * Frees all resources for fast UCC.
196 *
197 * uccf - (In) pointer to the fast UCC structure.
198 */
199void ucc_fast_free(struct ucc_fast_private * uccf);
200
201/* ucc_fast_enable
202 * Enables a fast UCC port.
203 * This routine enables Tx and/or Rx through the General UCC Mode Register.
204 *
205 * uccf - (In) pointer to the fast UCC structure.
206 * mode - (In) TX, RX, or both.
207 */
208void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
209
210/* ucc_fast_disable
211 * Disables a fast UCC port.
212 * This routine disables Tx and/or Rx through the General UCC Mode Register.
213 *
214 * uccf - (In) pointer to the fast UCC structure.
215 * mode - (In) TX, RX, or both.
216 */
217void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
218
219/* ucc_fast_irq
220 * Handles interrupts on fast UCC.
221 * Called from the general interrupt routine to handle interrupts on fast UCC.
222 *
223 * uccf - (In) pointer to the fast UCC structure.
224 */
225void ucc_fast_irq(struct ucc_fast_private * uccf);
226
227/* ucc_fast_transmit_on_demand
228 * Immediately forces a poll of the transmitter for data to be sent.
229 * Typically, the hardware performs a periodic poll for data that the
230 * transmit routine has set up to be transmitted. In cases where
231 * this polling cycle is not soon enough, this optional routine can
232 * be invoked to force a poll right away, instead. Proper use for
233 * each transmission for which this functionality is desired is to
234 * call the transmit routine and then this routine right after.
235 *
236 * uccf - (In) pointer to the fast UCC structure.
237 */
238void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
239
240u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
241
242void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
243
244#endif /* __UCC_FAST_H__ */
diff --git a/arch/powerpc/include/asm/ucc_slow.h b/arch/powerpc/include/asm/ucc_slow.h
new file mode 100644
index 000000000000..0980e6ad335b
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc_slow.h
@@ -0,0 +1,290 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC SLOW unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_SLOW_H__
16#define __UCC_SLOW_H__
17
18#include <linux/kernel.h>
19
20#include <asm/immap_qe.h>
21#include <asm/qe.h>
22
23#include "ucc.h"
24
25/* transmit BD's status */
26#define T_R 0x80000000 /* ready bit */
27#define T_PAD 0x40000000 /* add pads to short frames */
28#define T_W 0x20000000 /* wrap bit */
29#define T_I 0x10000000 /* interrupt on completion */
30#define T_L 0x08000000 /* last */
31
32#define T_A 0x04000000 /* Address - the data transmitted as address
33 chars */
34#define T_TC 0x04000000 /* transmit CRC */
35#define T_CM 0x02000000 /* continuous mode */
36#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
37#define T_P 0x01000000 /* Preamble - send Preamble sequence before
38 data */
39#define T_HB 0x01000000 /* heartbeat */
40#define T_NS 0x00800000 /* No Stop */
41#define T_LC 0x00800000 /* late collision */
42#define T_RL 0x00400000 /* retransmission limit */
43#define T_UN 0x00020000 /* underrun */
44#define T_CT 0x00010000 /* CTS lost */
45#define T_CSL 0x00010000 /* carrier sense lost */
46#define T_RC 0x003c0000 /* retry count */
47
48/* Receive BD's status */
49#define R_E 0x80000000 /* buffer empty */
50#define R_W 0x20000000 /* wrap bit */
51#define R_I 0x10000000 /* interrupt on reception */
52#define R_L 0x08000000 /* last */
53#define R_C 0x08000000 /* the last byte in this buffer is a cntl
54 char */
55#define R_F 0x04000000 /* first */
56#define R_A 0x04000000 /* the first byte in this buffer is address
57 byte */
58#define R_CM 0x02000000 /* continuous mode */
59#define R_ID 0x01000000 /* buffer close on reception of idles */
60#define R_M 0x01000000 /* Frame received because of promiscuous
61 mode */
62#define R_AM 0x00800000 /* Address match */
63#define R_DE 0x00800000 /* Address match */
64#define R_LG 0x00200000 /* Break received */
65#define R_BR 0x00200000 /* Frame length violation */
66#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
67#define R_FR 0x00100000 /* Framing Error (no stop bit) character
68 received */
69#define R_PR 0x00080000 /* Parity Error character received */
70#define R_AB 0x00080000 /* Frame Aborted */
71#define R_SH 0x00080000 /* frame is too short */
72#define R_CR 0x00040000 /* CRC Error */
73#define R_OV 0x00020000 /* Overrun */
74#define R_CD 0x00010000 /* CD lost */
75#define R_CL 0x00010000 /* this frame is closed because of a
76 collision */
77
78/* Rx Data buffer must be 4 bytes aligned in most cases.*/
79#define UCC_SLOW_RX_ALIGN 4
80#define UCC_SLOW_MRBLR_ALIGNMENT 4
81#define UCC_SLOW_PRAM_SIZE 0x100
82#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
83
84/* UCC Slow Channel Protocol Mode */
85enum ucc_slow_channel_protocol_mode {
86 UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
87 UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
88 UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
89};
90
91/* UCC Slow Transparent Transmit CRC (TCRC) */
92enum ucc_slow_transparent_tcrc {
93 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
94 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
95 /* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
96 UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
97 /* 32-bit CCITT CRC (Ethernet and HDLC) */
98 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
99};
100
101/* UCC Slow oversampling rate for transmitter (TDCR) */
102enum ucc_slow_tx_oversampling_rate {
103 /* 1x clock mode */
104 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
105 /* 8x clock mode */
106 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
107 /* 16x clock mode */
108 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
109 /* 32x clock mode */
110 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
111};
112
113/* UCC Slow Oversampling rate for receiver (RDCR)
114*/
115enum ucc_slow_rx_oversampling_rate {
116 /* 1x clock mode */
117 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
118 /* 8x clock mode */
119 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
120 /* 16x clock mode */
121 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
122 /* 32x clock mode */
123 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
124};
125
126/* UCC Slow Transmitter encoding method (TENC)
127*/
128enum ucc_slow_tx_encoding_method {
129 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
130 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
131};
132
133/* UCC Slow Receiver decoding method (RENC)
134*/
135enum ucc_slow_rx_decoding_method {
136 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
137 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
138};
139
140/* UCC Slow Diagnostic mode (DIAG)
141*/
142enum ucc_slow_diag_mode {
143 UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
144 UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
145 UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
146 UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
147};
148
149struct ucc_slow_info {
150 int ucc_num;
151 int protocol; /* QE_CR_PROTOCOL_xxx */
152 enum qe_clock rx_clock;
153 enum qe_clock tx_clock;
154 phys_addr_t regs;
155 int irq;
156 u16 uccm_mask;
157 int data_mem_part;
158 int init_tx;
159 int init_rx;
160 u32 tx_bd_ring_len;
161 u32 rx_bd_ring_len;
162 int rx_interrupts;
163 int brkpt_support;
164 int grant_support;
165 int tsa;
166 int cdp;
167 int cds;
168 int ctsp;
169 int ctss;
170 int rinv;
171 int tinv;
172 int rtsm;
173 int rfw;
174 int tci;
175 int tend;
176 int tfl;
177 int txsy;
178 u16 max_rx_buf_length;
179 enum ucc_slow_transparent_tcrc tcrc;
180 enum ucc_slow_channel_protocol_mode mode;
181 enum ucc_slow_diag_mode diag;
182 enum ucc_slow_tx_oversampling_rate tdcr;
183 enum ucc_slow_rx_oversampling_rate rdcr;
184 enum ucc_slow_tx_encoding_method tenc;
185 enum ucc_slow_rx_decoding_method renc;
186};
187
188struct ucc_slow_private {
189 struct ucc_slow_info *us_info;
190 struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
191 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
192 u32 us_pram_offset;
193 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
194 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
195 int stopped_tx; /* Whether channel has been stopped for Tx
196 (STOP_TX, etc.) */
197 int stopped_rx; /* Whether channel has been stopped for Rx */
198 struct list_head confQ; /* frames passed to chip waiting for tx */
199 u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
200 and length for first BD in a frame */
201 u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
202 u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
203 struct qe_bd *confBd; /* next BD for confirm after Tx */
204 struct qe_bd *tx_bd; /* next BD for new Tx request */
205 struct qe_bd *rx_bd; /* next BD to collect after Rx */
206 void *p_rx_frame; /* accumulating receive frame */
207 u16 *p_ucce; /* a pointer to the event register in memory.
208 */
209 u16 *p_uccm; /* a pointer to the mask register in memory */
210 u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
211#ifdef STATISTICS
212 u32 tx_frames; /* Transmitted frames counters */
213 u32 rx_frames; /* Received frames counters (only frames
214 passed to application) */
215 u32 rx_discarded; /* Discarded frames counters (frames that
216 were discarded by the driver due to
217 errors) */
218#endif /* STATISTICS */
219};
220
221/* ucc_slow_init
222 * Initializes Slow UCC according to provided parameters.
223 *
224 * us_info - (In) pointer to the slow UCC info structure.
225 * uccs_ret - (Out) pointer to the slow UCC structure.
226 */
227int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
228
229/* ucc_slow_free
230 * Frees all resources for slow UCC.
231 *
232 * uccs - (In) pointer to the slow UCC structure.
233 */
234void ucc_slow_free(struct ucc_slow_private * uccs);
235
236/* ucc_slow_enable
237 * Enables a fast UCC port.
238 * This routine enables Tx and/or Rx through the General UCC Mode Register.
239 *
240 * uccs - (In) pointer to the slow UCC structure.
241 * mode - (In) TX, RX, or both.
242 */
243void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
244
245/* ucc_slow_disable
246 * Disables a fast UCC port.
247 * This routine disables Tx and/or Rx through the General UCC Mode Register.
248 *
249 * uccs - (In) pointer to the slow UCC structure.
250 * mode - (In) TX, RX, or both.
251 */
252void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
253
254/* ucc_slow_poll_transmitter_now
255 * Immediately forces a poll of the transmitter for data to be sent.
256 * Typically, the hardware performs a periodic poll for data that the
257 * transmit routine has set up to be transmitted. In cases where
258 * this polling cycle is not soon enough, this optional routine can
259 * be invoked to force a poll right away, instead. Proper use for
260 * each transmission for which this functionality is desired is to
261 * call the transmit routine and then this routine right after.
262 *
263 * uccs - (In) pointer to the slow UCC structure.
264 */
265void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
266
267/* ucc_slow_graceful_stop_tx
268 * Smoothly stops transmission on a specified slow UCC.
269 *
270 * uccs - (In) pointer to the slow UCC structure.
271 */
272void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
273
274/* ucc_slow_stop_tx
275 * Stops transmission on a specified slow UCC.
276 *
277 * uccs - (In) pointer to the slow UCC structure.
278 */
279void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
280
281/* ucc_slow_restart_tx
282 * Restarts transmitting on a specified slow UCC.
283 *
284 * uccs - (In) pointer to the slow UCC structure.
285 */
286void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
287
288u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
289
290#endif /* __UCC_SLOW_H__ */
diff --git a/arch/powerpc/include/asm/ucontext.h b/arch/powerpc/include/asm/ucontext.h
new file mode 100644
index 000000000000..d9a4ddf0cc86
--- /dev/null
+++ b/arch/powerpc/include/asm/ucontext.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_POWERPC_UCONTEXT_H
2#define _ASM_POWERPC_UCONTEXT_H
3
4#ifdef __powerpc64__
5#include <asm/sigcontext.h>
6#else
7#include <asm/elf.h>
8#endif
9#include <asm/signal.h>
10
11#ifndef __powerpc64__
12struct mcontext {
13 elf_gregset_t mc_gregs;
14 elf_fpregset_t mc_fregs;
15 unsigned long mc_pad[2];
16 elf_vrregset_t mc_vregs __attribute__((__aligned__(16)));
17};
18#endif
19
20struct ucontext {
21 unsigned long uc_flags;
22 struct ucontext __user *uc_link;
23 stack_t uc_stack;
24#ifndef __powerpc64__
25 int uc_pad[7];
26 struct mcontext __user *uc_regs;/* points to uc_mcontext field */
27#endif
28 sigset_t uc_sigmask;
29 /* glibc has 1024-bit signal masks, ours are 64-bit */
30#ifdef __powerpc64__
31 sigset_t __unused[15]; /* Allow for uc_sigmask growth */
32 struct sigcontext uc_mcontext; /* last for extensibility */
33#else
34 int uc_maskext[30];
35 int uc_pad2[3];
36 struct mcontext uc_mcontext;
37#endif
38};
39
40#endif /* _ASM_POWERPC_UCONTEXT_H */
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
new file mode 100644
index 000000000000..6418ceea44b7
--- /dev/null
+++ b/arch/powerpc/include/asm/udbg.h
@@ -0,0 +1,55 @@
1/*
2 * (c) 2001, 2006 IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _ASM_POWERPC_UDBG_H
11#define _ASM_POWERPC_UDBG_H
12#ifdef __KERNEL__
13
14#include <linux/compiler.h>
15#include <linux/init.h>
16
17extern void (*udbg_putc)(char c);
18extern int (*udbg_getc)(void);
19extern int (*udbg_getc_poll)(void);
20
21extern void udbg_puts(const char *s);
22extern int udbg_write(const char *s, int n);
23extern int udbg_read(char *buf, int buflen);
24
25extern void register_early_udbg_console(void);
26extern void udbg_printf(const char *fmt, ...)
27 __attribute__ ((format (printf, 1, 2)));
28extern void udbg_progress(char *s, unsigned short hex);
29
30extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
31 unsigned int clock);
32extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
33 unsigned int clock);
34
35struct device_node;
36extern void udbg_scc_init(int force_scc);
37extern int udbg_adb_init(int force_btext);
38extern void udbg_adb_init_early(void);
39
40extern void __init udbg_early_init(void);
41extern void __init udbg_init_debug_lpar(void);
42extern void __init udbg_init_pmac_realmode(void);
43extern void __init udbg_init_maple_realmode(void);
44extern void __init udbg_init_pas_realmode(void);
45extern void __init udbg_init_iseries(void);
46extern void __init udbg_init_rtas_panel(void);
47extern void __init udbg_init_rtas_console(void);
48extern void __init udbg_init_debug_beat(void);
49extern void __init udbg_init_btext(void);
50extern void __init udbg_init_44x_as1(void);
51extern void __init udbg_init_40x_realmode(void);
52extern void __init udbg_init_cpm(void);
53
54#endif /* __KERNEL__ */
55#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/include/asm/uic.h b/arch/powerpc/include/asm/uic.h
new file mode 100644
index 000000000000..597edfcae3d6
--- /dev/null
+++ b/arch/powerpc/include/asm/uic.h
@@ -0,0 +1,21 @@
1/*
2 * IBM PPC4xx UIC external definitions and structure.
3 *
4 * Maintainer: David Gibson <dwg@au1.ibm.com>
5 * Copyright 2007 IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#ifndef _ASM_POWERPC_UIC_H
13#define _ASM_POWERPC_UIC_H
14
15#ifdef __KERNEL__
16
17extern void __init uic_init_tree(void);
18extern unsigned int uic_get_irq(void);
19
20#endif /* __KERNEL__ */
21#endif /* _ASM_POWERPC_UIC_H */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
new file mode 100644
index 000000000000..5f1b1e3c2137
--- /dev/null
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_POWERPC_UNALIGNED_H
2#define _ASM_POWERPC_UNALIGNED_H
3
4#ifdef __KERNEL__
5
6/*
7 * The PowerPC can do unaligned accesses itself in big endian mode.
8 */
9#include <linux/unaligned/access_ok.h>
10#include <linux/unaligned/generic.h>
11
12#define get_unaligned __get_unaligned_be
13#define put_unaligned __put_unaligned_be
14
15#endif /* __KERNEL__ */
16#endif /* _ASM_POWERPC_UNALIGNED_H */
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
new file mode 100644
index 000000000000..f737732c3861
--- /dev/null
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -0,0 +1,229 @@
1/*
2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
5 * machines and U3 (G5)
6 *
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_UNINORTH_H__
10#define __ASM_UNINORTH_H__
11
12/*
13 * Uni-N and U3 config space reg. definitions
14 *
15 * (Little endian)
16 */
17
18/* Address ranges selection. This one should work with Bandit too */
19/* Not U3 */
20#define UNI_N_ADDR_SELECT 0x48
21#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
23
24/* AGP registers */
25/* Not U3 */
26#define UNI_N_CFG_GART_BASE 0x8c
27#define UNI_N_CFG_AGP_BASE 0x90
28#define UNI_N_CFG_GART_CTRL 0x94
29#define UNI_N_CFG_INTERNAL_STATUS 0x98
30#define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
31
32/* UNI_N_CFG_GART_CTRL bits definitions */
33#define UNI_N_CFG_GART_INVAL 0x00000001
34#define UNI_N_CFG_GART_ENABLE 0x00000100
35#define UNI_N_CFG_GART_2xRESET 0x00010000
36#define UNI_N_CFG_GART_DISSBADET 0x00020000
37/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
38#define U3_N_CFG_GART_SYNCMODE 0x00040000
39#define U3_N_CFG_GART_PERFRD 0x00080000
40#define U3_N_CFG_GART_B2BGNT 0x00200000
41#define U3_N_CFG_GART_FASTDDR 0x00400000
42
43/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
44 * revision 1.5 (x4 AGP) may need further changes.
45 *
46 * AGP_BASE register contains the base address of the AGP aperture on
47 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
48 * even if decoding of this address range is enabled in the address select
49 * register. Apparently, the only supported bases are 256Mb multiples
50 * (high 4 bits of that register).
51 *
52 * GART_BASE register appear to contain the physical address of the GART
53 * in system memory in the high address bits (page aligned), and the
54 * GART size in the low order bits (number of GART pages)
55 *
56 * The GART format itself is one 32bits word per physical memory page.
57 * This word contains, in little-endian format (!!!), the physical address
58 * of the page in the high bits, and what appears to be an "enable" bit
59 * in the LSB bit (0) that must be set to 1 when the entry is valid.
60 *
61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself doens't seem to be cache coherent neither.
64 *
65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written,
67 * in order, to the GART_CTRL register:
68 *
69 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
70 * UNI_N_CFG_GART_ENABLE
71 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
72 * UNI_N_CFG_GART_ENABLE
73 *
74 * As far as AGP "features" are concerned, it looks like fast write may
75 * not be supported but this has to be confirmed.
76 *
77 * Turning on AGP seem to require a double invalidate operation, one before
78 * setting the AGP command register, on after.
79 *
80 * Turning off AGP seems to require the following sequence: first wait
81 * for the AGP to be idle by reading the internal status register, then
82 * write in that order to the GART_CTRL register:
83 *
84 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
85 * 0
86 * UNI_N_CFG_GART_2xRESET
87 * 0
88 */
89
90/*
91 * Uni-N memory mapped reg. definitions
92 *
93 * Those registers are Big-Endian !!
94 *
95 * Their meaning come from either Darwin and/or from experiments I made with
96 * the bootrom, I'm not sure about their exact meaning yet
97 *
98 */
99
100/* Version of the UniNorth chip */
101#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
102
103#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
104#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
105#define UNI_N_VERSION_150 0x0011 /* 1.5 */
106#define UNI_N_VERSION_200 0x0024 /* 2.0 */
107#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
108#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
109#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
110
111/* This register is used to enable/disable various clocks */
112#define UNI_N_CLOCK_CNTL 0x0020
113#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
114#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
115#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
116#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
117
118/* Power Management control */
119#define UNI_N_POWER_MGT 0x0030
120#define UNI_N_POWER_MGT_NORMAL 0x00
121#define UNI_N_POWER_MGT_IDLE2 0x01
122#define UNI_N_POWER_MGT_SLEEP 0x02
123
124/* This register is configured by Darwin depending on the UniN
125 * revision
126 */
127#define UNI_N_ARB_CTRL 0x0040
128#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
129#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
130#define UNI_N_ARB_CTRL_QACK_DELAY 0x30
131#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
132
133/* This one _might_ return the CPU number of the CPU reading it;
134 * the bootROM decides whether to boot or to sleep/spinloop depending
135 * on this register beeing 0 or not
136 */
137#define UNI_N_CPU_NUMBER 0x0050
138
139/* This register appear to be read by the bootROM to decide what
140 * to do on a non-recoverable reset (powerup or wakeup)
141 */
142#define UNI_N_HWINIT_STATE 0x0070
143#define UNI_N_HWINIT_STATE_SLEEPING 0x01
144#define UNI_N_HWINIT_STATE_RUNNING 0x02
145/* This last bit appear to be used by the bootROM to know the second
146 * CPU has started and will enter it's sleep loop with IP=0
147 */
148#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
149
150/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
151 * is in low speed mode.
152 */
153#define UNI_N_AACK_DELAY 0x0100
154#define UNI_N_AACK_DELAY_ENABLE 0x00000001
155
156/* Clock status for Intrepid */
157#define UNI_N_CLOCK_STOP_STATUS0 0x0150
158#define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
159#define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
160#define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
161#define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
162#define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
163#define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
164#define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
165#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
167#define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
168#define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
171#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
172#define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
173#define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
174#define UNI_N_CLOCK_STOPPED_USB0 0x00000020
175#define UNI_N_CLOCK_STOPPED_USB1 0x00000010
176#define UNI_N_CLOCK_STOPPED_USB2 0x00000008
177#define UNI_N_CLOCK_STOPPED_32 0x00000004
178#define UNI_N_CLOCK_STOPPED_45 0x00000002
179#define UNI_N_CLOCK_STOPPED_49 0x00000001
180
181#define UNI_N_CLOCK_STOP_STATUS1 0x0160
182#define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
183#define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
184#define UNI_N_CLOCK_STOPPED_CPU 0x00020000
185#define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
186#define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
187#define UNI_N_CLOCK_STOPPED_FW 0x00004000
188#define UNI_N_CLOCK_STOPPED_GB 0x00002000
189#define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
190#define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
191#define UNI_N_CLOCK_STOPPED_MAX 0x00000400
192#define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
193#define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
194#define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
195#define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
196#define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
197#define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
198#define UNI_N_CLOCK_STOPPED_AGP 0x00000004
199#define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
200#define UNI_N_CLOCK_STOPPED_18 0x00000001
201
202/* Intrepid registe to OF do-platform-clockspreading */
203#define UNI_N_CLOCK_SPREADING 0x190
204
205/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
206
207
208/*
209 * U3 specific registers
210 */
211
212
213/* U3 Toggle */
214#define U3_TOGGLE_REG 0x00e0
215#define U3_PMC_START_STOP 0x0001
216#define U3_MPIC_RESET 0x0002
217#define U3_MPIC_OUTPUT_ENABLE 0x0004
218
219/* U3 API PHY Config 1 */
220#define U3_API_PHY_CONFIG_1 0x23030
221
222/* U3 HyperTransport registers */
223#define U3_HT_CONFIG_BASE 0x70000
224#define U3_HT_LINK_COMMAND 0x100
225#define U3_HT_LINK_CONFIG 0x110
226#define U3_HT_LINK_FREQ 0x120
227
228#endif /* __ASM_UNINORTH_H__ */
229#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
new file mode 100644
index 000000000000..e07d0c76ed77
--- /dev/null
+++ b/arch/powerpc/include/asm/unistd.h
@@ -0,0 +1,398 @@
1#ifndef _ASM_POWERPC_UNISTD_H_
2#define _ASM_POWERPC_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define __NR_restart_syscall 0
14#define __NR_exit 1
15#define __NR_fork 2
16#define __NR_read 3
17#define __NR_write 4
18#define __NR_open 5
19#define __NR_close 6
20#define __NR_waitpid 7
21#define __NR_creat 8
22#define __NR_link 9
23#define __NR_unlink 10
24#define __NR_execve 11
25#define __NR_chdir 12
26#define __NR_time 13
27#define __NR_mknod 14
28#define __NR_chmod 15
29#define __NR_lchown 16
30#define __NR_break 17
31#define __NR_oldstat 18
32#define __NR_lseek 19
33#define __NR_getpid 20
34#define __NR_mount 21
35#define __NR_umount 22
36#define __NR_setuid 23
37#define __NR_getuid 24
38#define __NR_stime 25
39#define __NR_ptrace 26
40#define __NR_alarm 27
41#define __NR_oldfstat 28
42#define __NR_pause 29
43#define __NR_utime 30
44#define __NR_stty 31
45#define __NR_gtty 32
46#define __NR_access 33
47#define __NR_nice 34
48#define __NR_ftime 35
49#define __NR_sync 36
50#define __NR_kill 37
51#define __NR_rename 38
52#define __NR_mkdir 39
53#define __NR_rmdir 40
54#define __NR_dup 41
55#define __NR_pipe 42
56#define __NR_times 43
57#define __NR_prof 44
58#define __NR_brk 45
59#define __NR_setgid 46
60#define __NR_getgid 47
61#define __NR_signal 48
62#define __NR_geteuid 49
63#define __NR_getegid 50
64#define __NR_acct 51
65#define __NR_umount2 52
66#define __NR_lock 53
67#define __NR_ioctl 54
68#define __NR_fcntl 55
69#define __NR_mpx 56
70#define __NR_setpgid 57
71#define __NR_ulimit 58
72#define __NR_oldolduname 59
73#define __NR_umask 60
74#define __NR_chroot 61
75#define __NR_ustat 62
76#define __NR_dup2 63
77#define __NR_getppid 64
78#define __NR_getpgrp 65
79#define __NR_setsid 66
80#define __NR_sigaction 67
81#define __NR_sgetmask 68
82#define __NR_ssetmask 69
83#define __NR_setreuid 70
84#define __NR_setregid 71
85#define __NR_sigsuspend 72
86#define __NR_sigpending 73
87#define __NR_sethostname 74
88#define __NR_setrlimit 75
89#define __NR_getrlimit 76
90#define __NR_getrusage 77
91#define __NR_gettimeofday 78
92#define __NR_settimeofday 79
93#define __NR_getgroups 80
94#define __NR_setgroups 81
95#define __NR_select 82
96#define __NR_symlink 83
97#define __NR_oldlstat 84
98#define __NR_readlink 85
99#define __NR_uselib 86
100#define __NR_swapon 87
101#define __NR_reboot 88
102#define __NR_readdir 89
103#define __NR_mmap 90
104#define __NR_munmap 91
105#define __NR_truncate 92
106#define __NR_ftruncate 93
107#define __NR_fchmod 94
108#define __NR_fchown 95
109#define __NR_getpriority 96
110#define __NR_setpriority 97
111#define __NR_profil 98
112#define __NR_statfs 99
113#define __NR_fstatfs 100
114#define __NR_ioperm 101
115#define __NR_socketcall 102
116#define __NR_syslog 103
117#define __NR_setitimer 104
118#define __NR_getitimer 105
119#define __NR_stat 106
120#define __NR_lstat 107
121#define __NR_fstat 108
122#define __NR_olduname 109
123#define __NR_iopl 110
124#define __NR_vhangup 111
125#define __NR_idle 112
126#define __NR_vm86 113
127#define __NR_wait4 114
128#define __NR_swapoff 115
129#define __NR_sysinfo 116
130#define __NR_ipc 117
131#define __NR_fsync 118
132#define __NR_sigreturn 119
133#define __NR_clone 120
134#define __NR_setdomainname 121
135#define __NR_uname 122
136#define __NR_modify_ldt 123
137#define __NR_adjtimex 124
138#define __NR_mprotect 125
139#define __NR_sigprocmask 126
140#define __NR_create_module 127
141#define __NR_init_module 128
142#define __NR_delete_module 129
143#define __NR_get_kernel_syms 130
144#define __NR_quotactl 131
145#define __NR_getpgid 132
146#define __NR_fchdir 133
147#define __NR_bdflush 134
148#define __NR_sysfs 135
149#define __NR_personality 136
150#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
151#define __NR_setfsuid 138
152#define __NR_setfsgid 139
153#define __NR__llseek 140
154#define __NR_getdents 141
155#define __NR__newselect 142
156#define __NR_flock 143
157#define __NR_msync 144
158#define __NR_readv 145
159#define __NR_writev 146
160#define __NR_getsid 147
161#define __NR_fdatasync 148
162#define __NR__sysctl 149
163#define __NR_mlock 150
164#define __NR_munlock 151
165#define __NR_mlockall 152
166#define __NR_munlockall 153
167#define __NR_sched_setparam 154
168#define __NR_sched_getparam 155
169#define __NR_sched_setscheduler 156
170#define __NR_sched_getscheduler 157
171#define __NR_sched_yield 158
172#define __NR_sched_get_priority_max 159
173#define __NR_sched_get_priority_min 160
174#define __NR_sched_rr_get_interval 161
175#define __NR_nanosleep 162
176#define __NR_mremap 163
177#define __NR_setresuid 164
178#define __NR_getresuid 165
179#define __NR_query_module 166
180#define __NR_poll 167
181#define __NR_nfsservctl 168
182#define __NR_setresgid 169
183#define __NR_getresgid 170
184#define __NR_prctl 171
185#define __NR_rt_sigreturn 172
186#define __NR_rt_sigaction 173
187#define __NR_rt_sigprocmask 174
188#define __NR_rt_sigpending 175
189#define __NR_rt_sigtimedwait 176
190#define __NR_rt_sigqueueinfo 177
191#define __NR_rt_sigsuspend 178
192#define __NR_pread64 179
193#define __NR_pwrite64 180
194#define __NR_chown 181
195#define __NR_getcwd 182
196#define __NR_capget 183
197#define __NR_capset 184
198#define __NR_sigaltstack 185
199#define __NR_sendfile 186
200#define __NR_getpmsg 187 /* some people actually want streams */
201#define __NR_putpmsg 188 /* some people actually want streams */
202#define __NR_vfork 189
203#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */
204#define __NR_readahead 191
205#ifndef __powerpc64__ /* these are 32-bit only */
206#define __NR_mmap2 192
207#define __NR_truncate64 193
208#define __NR_ftruncate64 194
209#define __NR_stat64 195
210#define __NR_lstat64 196
211#define __NR_fstat64 197
212#endif
213#define __NR_pciconfig_read 198
214#define __NR_pciconfig_write 199
215#define __NR_pciconfig_iobase 200
216#define __NR_multiplexer 201
217#define __NR_getdents64 202
218#define __NR_pivot_root 203
219#ifndef __powerpc64__
220#define __NR_fcntl64 204
221#endif
222#define __NR_madvise 205
223#define __NR_mincore 206
224#define __NR_gettid 207
225#define __NR_tkill 208
226#define __NR_setxattr 209
227#define __NR_lsetxattr 210
228#define __NR_fsetxattr 211
229#define __NR_getxattr 212
230#define __NR_lgetxattr 213
231#define __NR_fgetxattr 214
232#define __NR_listxattr 215
233#define __NR_llistxattr 216
234#define __NR_flistxattr 217
235#define __NR_removexattr 218
236#define __NR_lremovexattr 219
237#define __NR_fremovexattr 220
238#define __NR_futex 221
239#define __NR_sched_setaffinity 222
240#define __NR_sched_getaffinity 223
241/* 224 currently unused */
242#define __NR_tuxcall 225
243#ifndef __powerpc64__
244#define __NR_sendfile64 226
245#endif
246#define __NR_io_setup 227
247#define __NR_io_destroy 228
248#define __NR_io_getevents 229
249#define __NR_io_submit 230
250#define __NR_io_cancel 231
251#define __NR_set_tid_address 232
252#define __NR_fadvise64 233
253#define __NR_exit_group 234
254#define __NR_lookup_dcookie 235
255#define __NR_epoll_create 236
256#define __NR_epoll_ctl 237
257#define __NR_epoll_wait 238
258#define __NR_remap_file_pages 239
259#define __NR_timer_create 240
260#define __NR_timer_settime 241
261#define __NR_timer_gettime 242
262#define __NR_timer_getoverrun 243
263#define __NR_timer_delete 244
264#define __NR_clock_settime 245
265#define __NR_clock_gettime 246
266#define __NR_clock_getres 247
267#define __NR_clock_nanosleep 248
268#define __NR_swapcontext 249
269#define __NR_tgkill 250
270#define __NR_utimes 251
271#define __NR_statfs64 252
272#define __NR_fstatfs64 253
273#ifndef __powerpc64__
274#define __NR_fadvise64_64 254
275#endif
276#define __NR_rtas 255
277#define __NR_sys_debug_setcontext 256
278/* Number 257 is reserved for vserver */
279#define __NR_migrate_pages 258
280#define __NR_mbind 259
281#define __NR_get_mempolicy 260
282#define __NR_set_mempolicy 261
283#define __NR_mq_open 262
284#define __NR_mq_unlink 263
285#define __NR_mq_timedsend 264
286#define __NR_mq_timedreceive 265
287#define __NR_mq_notify 266
288#define __NR_mq_getsetattr 267
289#define __NR_kexec_load 268
290#define __NR_add_key 269
291#define __NR_request_key 270
292#define __NR_keyctl 271
293#define __NR_waitid 272
294#define __NR_ioprio_set 273
295#define __NR_ioprio_get 274
296#define __NR_inotify_init 275
297#define __NR_inotify_add_watch 276
298#define __NR_inotify_rm_watch 277
299#define __NR_spu_run 278
300#define __NR_spu_create 279
301#define __NR_pselect6 280
302#define __NR_ppoll 281
303#define __NR_unshare 282
304#define __NR_splice 283
305#define __NR_tee 284
306#define __NR_vmsplice 285
307#define __NR_openat 286
308#define __NR_mkdirat 287
309#define __NR_mknodat 288
310#define __NR_fchownat 289
311#define __NR_futimesat 290
312#ifdef __powerpc64__
313#define __NR_newfstatat 291
314#else
315#define __NR_fstatat64 291
316#endif
317#define __NR_unlinkat 292
318#define __NR_renameat 293
319#define __NR_linkat 294
320#define __NR_symlinkat 295
321#define __NR_readlinkat 296
322#define __NR_fchmodat 297
323#define __NR_faccessat 298
324#define __NR_get_robust_list 299
325#define __NR_set_robust_list 300
326#define __NR_move_pages 301
327#define __NR_getcpu 302
328#define __NR_epoll_pwait 303
329#define __NR_utimensat 304
330#define __NR_signalfd 305
331#define __NR_timerfd_create 306
332#define __NR_eventfd 307
333#define __NR_sync_file_range2 308
334#define __NR_fallocate 309
335#define __NR_subpage_prot 310
336#define __NR_timerfd_settime 311
337#define __NR_timerfd_gettime 312
338#define __NR_signalfd4 313
339#define __NR_eventfd2 314
340#define __NR_epoll_create1 315
341#define __NR_dup3 316
342#define __NR_pipe2 317
343#define __NR_inotify_init1 318
344
345#ifdef __KERNEL__
346
347#define __NR_syscalls 319
348
349#define __NR__exit __NR_exit
350#define NR_syscalls __NR_syscalls
351
352#ifndef __ASSEMBLY__
353
354#include <linux/types.h>
355#include <linux/compiler.h>
356#include <linux/linkage.h>
357
358#define __ARCH_WANT_IPC_PARSE_VERSION
359#define __ARCH_WANT_OLD_READDIR
360#define __ARCH_WANT_STAT64
361#define __ARCH_WANT_SYS_ALARM
362#define __ARCH_WANT_SYS_GETHOSTNAME
363#define __ARCH_WANT_SYS_PAUSE
364#define __ARCH_WANT_SYS_SGETMASK
365#define __ARCH_WANT_SYS_SIGNAL
366#define __ARCH_WANT_SYS_TIME
367#define __ARCH_WANT_SYS_UTIME
368#define __ARCH_WANT_SYS_WAITPID
369#define __ARCH_WANT_SYS_SOCKETCALL
370#define __ARCH_WANT_SYS_FADVISE64
371#define __ARCH_WANT_SYS_GETPGRP
372#define __ARCH_WANT_SYS_LLSEEK
373#define __ARCH_WANT_SYS_NICE
374#define __ARCH_WANT_SYS_OLD_GETRLIMIT
375#define __ARCH_WANT_SYS_OLDUMOUNT
376#define __ARCH_WANT_SYS_SIGPENDING
377#define __ARCH_WANT_SYS_SIGPROCMASK
378#define __ARCH_WANT_SYS_RT_SIGACTION
379#define __ARCH_WANT_SYS_RT_SIGSUSPEND
380#ifdef CONFIG_PPC32
381#define __ARCH_WANT_OLD_STAT
382#endif
383#ifdef CONFIG_PPC64
384#define __ARCH_WANT_COMPAT_SYS_TIME
385#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
386#define __ARCH_WANT_SYS_NEWFSTATAT
387#endif
388
389/*
390 * "Conditional" syscalls
391 */
392#define cond_syscall(x) \
393 asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
394
395#endif /* __ASSEMBLY__ */
396#endif /* __KERNEL__ */
397
398#endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/include/asm/user.h b/arch/powerpc/include/asm/user.h
new file mode 100644
index 000000000000..3fd4545dd74e
--- /dev/null
+++ b/arch/powerpc/include/asm/user.h
@@ -0,0 +1,51 @@
1#ifndef _ASM_POWERPC_USER_H
2#define _ASM_POWERPC_USER_H
3
4#include <asm/ptrace.h>
5#include <asm/page.h>
6
7/*
8 * Adapted from <asm-alpha/user.h>
9 *
10 * Core file format: The core file is written in such a way that gdb
11 * can understand it and provide useful information to the user (under
12 * linux we use the `trad-core' bfd, NOT the osf-core). The file contents
13 * are as follows:
14 *
15 * upage: 1 page consisting of a user struct that tells gdb
16 * what is present in the file. Directly after this is a
17 * copy of the task_struct, which is currently not used by gdb,
18 * but it may come in handy at some point. All of the registers
19 * are stored as part of the upage. The upage should always be
20 * only one page long.
21 * data: The data segment follows next. We use current->end_text to
22 * current->brk to pick up all of the user variables, plus any memory
23 * that may have been sbrk'ed. No attempt is made to determine if a
24 * page is demand-zero or if a page is totally unused, we just cover
25 * the entire range. All of the addresses are rounded in such a way
26 * that an integral number of pages is written.
27 * stack: We need the stack information in order to get a meaningful
28 * backtrace. We need to write the data from usp to
29 * current->start_stack, so we round each of these in order to be able
30 * to write an integer number of pages.
31 */
32struct user {
33 struct pt_regs regs; /* entire machine state */
34 size_t u_tsize; /* text size (pages) */
35 size_t u_dsize; /* data size (pages) */
36 size_t u_ssize; /* stack size (pages) */
37 unsigned long start_code; /* text starting address */
38 unsigned long start_data; /* data starting address */
39 unsigned long start_stack; /* stack starting address */
40 long int signal; /* signal causing core dump */
41 unsigned long u_ar0; /* help gdb find registers */
42 unsigned long magic; /* identifies a core file */
43 char u_comm[32]; /* user command name */
44};
45
46#define NBPG PAGE_SIZE
47#define UPAGES 1
48#define HOST_TEXT_START_ADDR (u.start_code)
49#define HOST_DATA_START_ADDR (u.start_data)
50#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
51#endif /* _ASM_POWERPC_USER_H */
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
new file mode 100644
index 000000000000..26fc449bd989
--- /dev/null
+++ b/arch/powerpc/include/asm/vdso.h
@@ -0,0 +1,78 @@
1#ifndef __PPC64_VDSO_H__
2#define __PPC64_VDSO_H__
3
4#ifdef __KERNEL__
5
6/* Default link addresses for the vDSOs */
7#define VDSO32_LBASE 0x100000
8#define VDSO64_LBASE 0x100000
9
10/* Default map addresses */
11#define VDSO32_MBASE VDSO32_LBASE
12#define VDSO64_MBASE VDSO64_LBASE
13
14#define VDSO_VERSION_STRING LINUX_2.6.15
15
16/* Define if 64 bits VDSO has procedure descriptors */
17#undef VDS64_HAS_DESCRIPTORS
18
19#ifndef __ASSEMBLY__
20
21/* Offsets relative to thread->vdso_base */
22extern unsigned long vdso64_rt_sigtramp;
23extern unsigned long vdso32_sigtramp;
24extern unsigned long vdso32_rt_sigtramp;
25
26#else /* __ASSEMBLY__ */
27
28#ifdef __VDSO64__
29#ifdef VDS64_HAS_DESCRIPTORS
30#define V_FUNCTION_BEGIN(name) \
31 .globl name; \
32 .section ".opd","a"; \
33 .align 3; \
34 name: \
35 .quad .name,.TOC.@tocbase,0; \
36 .previous; \
37 .globl .name; \
38 .type .name,@function; \
39 .name: \
40
41#define V_FUNCTION_END(name) \
42 .size .name,.-.name;
43
44#define V_LOCAL_FUNC(name) (.name)
45
46#else /* VDS64_HAS_DESCRIPTORS */
47
48#define V_FUNCTION_BEGIN(name) \
49 .globl name; \
50 name: \
51
52#define V_FUNCTION_END(name) \
53 .size name,.-name;
54
55#define V_LOCAL_FUNC(name) (name)
56
57#endif /* VDS64_HAS_DESCRIPTORS */
58#endif /* __VDSO64__ */
59
60#ifdef __VDSO32__
61
62#define V_FUNCTION_BEGIN(name) \
63 .globl name; \
64 .type name,@function; \
65 name: \
66
67#define V_FUNCTION_END(name) \
68 .size name,.-name;
69
70#define V_LOCAL_FUNC(name) (name)
71
72#endif /* __VDSO32__ */
73
74#endif /* __ASSEMBLY__ */
75
76#endif /* __KERNEL__ */
77
78#endif /* __PPC64_VDSO_H__ */
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
new file mode 100644
index 000000000000..f01393224b52
--- /dev/null
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -0,0 +1,121 @@
1#ifndef _VDSO_DATAPAGE_H
2#define _VDSO_DATAPAGE_H
3#ifdef __KERNEL__
4
5/*
6 * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
7 * Copyright (C) 2005 Benjamin Herrenschmidy <benh@kernel.crashing.org>,
8 * IBM Corp.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16
17/*
18 * Note about this structure:
19 *
20 * This structure was historically called systemcfg and exposed to
21 * userland via /proc/ppc64/systemcfg. Unfortunately, this became an
22 * ABI issue as some proprietary software started relying on being able
23 * to mmap() it, thus we have to keep the base layout at least for a
24 * few kernel versions.
25 *
26 * However, since ppc32 doesn't suffer from this backward handicap,
27 * a simpler version of the data structure is used there with only the
28 * fields actually used by the vDSO.
29 *
30 */
31
32/*
33 * If the major version changes we are incompatible.
34 * Minor version changes are a hint.
35 */
36#define SYSTEMCFG_MAJOR 1
37#define SYSTEMCFG_MINOR 1
38
39#ifndef __ASSEMBLY__
40
41#include <linux/unistd.h>
42
43#define SYSCALL_MAP_SIZE ((__NR_syscalls + 31) / 32)
44
45/*
46 * So here is the ppc64 backward compatible version
47 */
48
49#ifdef CONFIG_PPC64
50
51struct vdso_data {
52 __u8 eye_catcher[16]; /* Eyecatcher: SYSTEMCFG:PPC64 0x00 */
53 struct { /* Systemcfg version numbers */
54 __u32 major; /* Major number 0x10 */
55 __u32 minor; /* Minor number 0x14 */
56 } version;
57
58 /* Note about the platform flags: it now only contains the lpar
59 * bit. The actual platform number is dead and burried
60 */
61 __u32 platform; /* Platform flags 0x18 */
62 __u32 processor; /* Processor type 0x1C */
63 __u64 processorCount; /* # of physical processors 0x20 */
64 __u64 physicalMemorySize; /* Size of real memory(B) 0x28 */
65 __u64 tb_orig_stamp; /* Timebase at boot 0x30 */
66 __u64 tb_ticks_per_sec; /* Timebase tics / sec 0x38 */
67 __u64 tb_to_xs; /* Inverse of TB to 2^20 0x40 */
68 __u64 stamp_xsec; /* 0x48 */
69 __u64 tb_update_count; /* Timebase atomicity ctr 0x50 */
70 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x58 */
71 __u32 tz_dsttime; /* Type of dst correction 0x5C */
72 __u32 dcache_size; /* L1 d-cache size 0x60 */
73 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */
74 __u32 icache_size; /* L1 i-cache size 0x68 */
75 __u32 icache_line_size; /* L1 i-cache line size 0x6C */
76
77 /* those additional ones don't have to be located anywhere
78 * special as they were not part of the original systemcfg
79 */
80 __u32 dcache_block_size; /* L1 d-cache block size */
81 __u32 icache_block_size; /* L1 i-cache block size */
82 __u32 dcache_log_block_size; /* L1 d-cache log block size */
83 __u32 icache_log_block_size; /* L1 i-cache log block size */
84 __s32 wtom_clock_sec; /* Wall to monotonic clock */
85 __s32 wtom_clock_nsec;
86 __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
87 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
88};
89
90#else /* CONFIG_PPC64 */
91
92/*
93 * And here is the simpler 32 bits version
94 */
95struct vdso_data {
96 __u64 tb_orig_stamp; /* Timebase at boot 0x30 */
97 __u64 tb_ticks_per_sec; /* Timebase tics / sec 0x38 */
98 __u64 tb_to_xs; /* Inverse of TB to 2^20 0x40 */
99 __u64 stamp_xsec; /* 0x48 */
100 __u32 tb_update_count; /* Timebase atomicity ctr 0x50 */
101 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x58 */
102 __u32 tz_dsttime; /* Type of dst correction 0x5C */
103 __s32 wtom_clock_sec; /* Wall to monotonic clock */
104 __s32 wtom_clock_nsec;
105 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
106 __u32 dcache_block_size; /* L1 d-cache block size */
107 __u32 icache_block_size; /* L1 i-cache block size */
108 __u32 dcache_log_block_size; /* L1 d-cache log block size */
109 __u32 icache_log_block_size; /* L1 i-cache log block size */
110};
111
112#endif /* CONFIG_PPC64 */
113
114#ifdef __KERNEL__
115extern struct vdso_data *vdso_data;
116#endif
117
118#endif /* __ASSEMBLY__ */
119
120#endif /* __KERNEL__ */
121#endif /* _SYSTEMCFG_H */
diff --git a/arch/powerpc/include/asm/vga.h b/arch/powerpc/include/asm/vga.h
new file mode 100644
index 000000000000..a2eac409c1ec
--- /dev/null
+++ b/arch/powerpc/include/asm/vga.h
@@ -0,0 +1,53 @@
1#ifndef _ASM_POWERPC_VGA_H_
2#define _ASM_POWERPC_VGA_H_
3
4#ifdef __KERNEL__
5
6/*
7 * Access to VGA videoram
8 *
9 * (c) 1998 Martin Mares <mj@ucw.cz>
10 */
11
12
13#include <asm/io.h>
14
15
16#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
17
18#define VT_BUF_HAVE_RW
19/*
20 * These are only needed for supporting VGA or MDA text mode, which use little
21 * endian byte ordering.
22 * In other cases, we can optimize by using native byte ordering and
23 * <linux/vt_buffer.h> has already done the right job for us.
24 */
25
26static inline void scr_writew(u16 val, volatile u16 *addr)
27{
28 st_le16(addr, val);
29}
30
31static inline u16 scr_readw(volatile const u16 *addr)
32{
33 return ld_le16(addr);
34}
35
36#define VT_BUF_HAVE_MEMCPYW
37#define scr_memcpyw memcpy
38
39#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
40
41extern unsigned long vgacon_remap_base;
42
43#ifdef __powerpc64__
44#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
45#else
46#define VGA_MAP_MEM(x,s) (x + vgacon_remap_base)
47#endif
48
49#define vga_readb(x) (*(x))
50#define vga_writeb(x,y) (*(y) = (x))
51
52#endif /* __KERNEL__ */
53#endif /* _ASM_POWERPC_VGA_H_ */
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
new file mode 100644
index 000000000000..0a290a195946
--- /dev/null
+++ b/arch/powerpc/include/asm/vio.h
@@ -0,0 +1,118 @@
1/*
2 * IBM PowerPC Virtual I/O Infrastructure Support.
3 *
4 * Copyright (c) 2003 IBM Corp.
5 * Dave Engebretsen engebret@us.ibm.com
6 * Santiago Leon santil@us.ibm.com
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef _ASM_POWERPC_VIO_H
15#define _ASM_POWERPC_VIO_H
16#ifdef __KERNEL__
17
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mod_devicetable.h>
23
24#include <asm/hvcall.h>
25#include <asm/scatterlist.h>
26
27/*
28 * Architecture-specific constants for drivers to
29 * extract attributes of the device using vio_get_attribute()
30 */
31#define VETH_MAC_ADDR "local-mac-address"
32#define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters"
33
34/* End architecture-specific constants */
35
36#define h_vio_signal(ua, mode) \
37 plpar_hcall_norets(H_VIO_SIGNAL, ua, mode)
38
39#define VIO_IRQ_DISABLE 0UL
40#define VIO_IRQ_ENABLE 1UL
41
42/*
43 * VIO CMO minimum entitlement for all devices and spare entitlement
44 */
45#define VIO_CMO_MIN_ENT 1562624
46
47struct iommu_table;
48
49/**
50 * vio_dev - This structure is used to describe virtual I/O devices.
51 *
52 * @desired: set from return of driver's get_desired_dma() function
53 * @entitled: bytes of IO data that has been reserved for this device.
54 * @allocated: bytes of IO data currently in use by the device.
55 * @allocs_failed: number of DMA failures due to insufficient entitlement.
56 */
57struct vio_dev {
58 const char *name;
59 const char *type;
60 uint32_t unit_address;
61 unsigned int irq;
62 struct {
63 size_t desired;
64 size_t entitled;
65 size_t allocated;
66 atomic_t allocs_failed;
67 } cmo;
68 struct device dev;
69};
70
71struct vio_driver {
72 const struct vio_device_id *id_table;
73 int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
74 int (*remove)(struct vio_dev *dev);
75 /* A driver must have a get_desired_dma() function to
76 * be loaded in a CMO environment if it uses DMA.
77 */
78 unsigned long (*get_desired_dma)(struct vio_dev *dev);
79 struct device_driver driver;
80};
81
82extern int vio_register_driver(struct vio_driver *drv);
83extern void vio_unregister_driver(struct vio_driver *drv);
84
85extern int vio_cmo_entitlement_update(size_t);
86extern void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired);
87
88extern void __devinit vio_unregister_device(struct vio_dev *dev);
89
90struct device_node;
91
92extern struct vio_dev *vio_register_device_node(
93 struct device_node *node_vdev);
94extern const void *vio_get_attribute(struct vio_dev *vdev, char *which,
95 int *length);
96#ifdef CONFIG_PPC_PSERIES
97extern struct vio_dev *vio_find_node(struct device_node *vnode);
98extern int vio_enable_interrupts(struct vio_dev *dev);
99extern int vio_disable_interrupts(struct vio_dev *dev);
100#else
101static inline int vio_enable_interrupts(struct vio_dev *dev)
102{
103 return 0;
104}
105#endif
106
107static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
108{
109 return container_of(drv, struct vio_driver, driver);
110}
111
112static inline struct vio_dev *to_vio_dev(struct device *dev)
113{
114 return container_of(dev, struct vio_dev, dev);
115}
116
117#endif /* __KERNEL__ */
118#endif /* _ASM_POWERPC_VIO_H */
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
new file mode 100644
index 000000000000..343612f8fece
--- /dev/null
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -0,0 +1,20 @@
1/*
2 * Xilinx intc external definitions
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef _ASM_POWERPC_XILINX_INTC_H
12#define _ASM_POWERPC_XILINX_INTC_H
13
14#ifdef __KERNEL__
15
16extern void __init xilinx_intc_init_tree(void);
17extern unsigned int xilinx_intc_get_irq(void);
18
19#endif /* __KERNEL__ */
20#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xmon.h b/arch/powerpc/include/asm/xmon.h
new file mode 100644
index 000000000000..5eb8e599e5cc
--- /dev/null
+++ b/arch/powerpc/include/asm/xmon.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_POWERPC_XMON_H
2#define __ASM_POWERPC_XMON_H
3
4/*
5 * Copyrignt (C) 2006 IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifdef __KERNEL__
14
15#include <linux/irqreturn.h>
16
17#ifdef CONFIG_XMON
18extern void xmon_setup(void);
19extern void xmon_register_spus(struct list_head *list);
20struct pt_regs;
21extern int xmon(struct pt_regs *excp);
22extern irqreturn_t xmon_irq(int, void *);
23#else
24static inline void xmon_setup(void) { };
25static inline void xmon_register_spus(struct list_head *list) { };
26#endif
27
28#if defined(CONFIG_XMON) && defined(CONFIG_SMP)
29extern int cpus_are_in_xmon(void);
30#endif
31
32#endif /* __KERNEL __ */
33#endif /* __ASM_POWERPC_XMON_H */
diff --git a/arch/powerpc/include/asm/xor.h b/arch/powerpc/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/powerpc/include/asm/xor.h
@@ -0,0 +1 @@
#include <asm-generic/xor.h>
diff --git a/arch/powerpc/mm/tlb_64.c b/arch/powerpc/mm/tlb_64.c
index 409fcc7b63ce..be7dd422c0fa 100644
--- a/arch/powerpc/mm/tlb_64.c
+++ b/arch/powerpc/mm/tlb_64.c
@@ -34,7 +34,7 @@
34DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); 34DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
35 35
36/* This is declared as we are using the more or less generic 36/* This is declared as we are using the more or less generic
37 * include/asm-powerpc/tlb.h file -- tgall 37 * arch/powerpc/include/asm/tlb.h file -- tgall
38 */ 38 */
39DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 39DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
40static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur); 40static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
index 835f2dc24dc9..014e26cda08d 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -19,7 +19,7 @@
19#include <asm/page.h> 19#include <asm/page.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/pci-bridge.h> 21#include <asm/pci-bridge.h>
22#include <asm-powerpc/mpic.h> 22#include <asm/mpic.h>
23#include <asm/mpc86xx.h> 23#include <asm/mpc86xx.h>
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25 25