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authorHaiying Wang <Haiying.Wang@freescale.com>2010-05-21 10:16:12 -0400
committerKumar Gala <galak@kernel.crashing.org>2010-05-24 22:29:25 -0400
commit48936a08b85518c22a9467a8eaac35d43af54ab4 (patch)
tree49243b31d948199f5141377c4bb58d1c5224b645 /arch/powerpc
parent710e33832653cccf7fc432023e7dbe8c49a1902f (diff)
powerpc/85xx: Add P1021MDS board support
P1021 is a dual e500v2 core based SOC with: * 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board) * 2 PCIe Controller * 1 USB2.0 controller * eSDHC, eSPI, I2C, DUART * eLBC (NAND, BCSR, PMC0/1) * Security Engine (SEC 3.3.2) * Quicc Engine (QE) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Yu Liu <Yu.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts698
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c102
2 files changed, 797 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
new file mode 100644
index 000000000000..7fad2df25981
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -0,0 +1,698 @@
1/*
2 * P1021 MDS Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@ffe05000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59
60 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
62 0x1 0x0 0x0 0xf8000000 0x00008000
63 0x2 0x0 0x0 0xf8010000 0x00020000
64 0x3 0x0 0x0 0xf8020000 0x00020000>;
65
66 nand@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "fsl,p1021-fcm-nand",
70 "fsl,elbc-fcm-nand";
71 reg = <0x0 0x0 0x40000>;
72
73 partition@0 {
74 /* This location must not be altered */
75 /* 1MB for u-boot Bootloader Image */
76 reg = <0x0 0x00100000>;
77 label = "NAND (RO) U-Boot Image";
78 read-only;
79 };
80
81 partition@100000 {
82 /* 1MB for DTB Image */
83 reg = <0x00100000 0x00100000>;
84 label = "NAND (RO) DTB Image";
85 read-only;
86 };
87
88 partition@200000 {
89 /* 4MB for Linux Kernel Image */
90 reg = <0x00200000 0x00400000>;
91 label = "NAND (RO) Linux Kernel Image";
92 read-only;
93 };
94
95 partition@600000 {
96 /* 5MB for Compressed Root file System Image */
97 reg = <0x00600000 0x00500000>;
98 label = "NAND (RO) Compressed RFS Image";
99 read-only;
100 };
101
102 partition@b00000 {
103 /* 6MB for JFFS2 based Root file System */
104 reg = <0x00a00000 0x00600000>;
105 label = "NAND (RW) JFFS2 Root File System";
106 };
107
108 partition@1100000 {
109 /* 14MB for JFFS2 based Root file System */
110 reg = <0x01100000 0x00e00000>;
111 label = "NAND (RW) Writable User area";
112 };
113
114 partition@1f00000 {
115 /* 1MB for microcode */
116 reg = <0x01f00000 0x00100000>;
117 label = "NAND (RO) QE Ucode";
118 read-only;
119 };
120 };
121
122 bcsr@1,0 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,p1021mds-bcsr";
126 reg = <1 0 0x8000>;
127 ranges = <0 1 0 0x8000>;
128 };
129
130 pib@2,0 {
131 compatible = "fsl,p1021mds-pib";
132 reg = <2 0 0x10000>;
133 };
134
135 pib@3,0 {
136 compatible = "fsl,p1021mds-pib";
137 reg = <3 0 0x10000>;
138 };
139 };
140
141 soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169
170 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 {
180 compatible = "dallas,ds1374";
181 reg = <0x68>;
182 };
183 };
184
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 {
217 cell-index = <0>;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "fsl,espi-flash";
231 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */
234 partition@u-boot {
235 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>;
237 read-only;
238 };
239 partition@kernel {
240 label = "kernel-spi";
241 reg = <0x00100000 0x00500000>;
242 read-only;
243 };
244 partition@dtb {
245 label = "dtb-spi";
246 reg = <0x00600000 0x00100000>;
247 read-only;
248 };
249 partition@fs {
250 label = "file system-spi";
251 reg = <0x00700000 0x00900000>;
252 };
253 };
254 };
255
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi";
319 };
320
321 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>;
329 interrupts = <1 1>;
330 reg = <0x0>;
331 };
332 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>;
334 interrupts = <2 1>;
335 reg = <0x1>;
336 };
337 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>;
340 };
341 };
342
343 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 {
349 reg = <0x11>;
350 device_type = "tbi-phy";
351 };
352 };
353
354 enet0: ethernet@B0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 };
380
381 enet1: ethernet@B1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 };
408
409 enet2: ethernet@B2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 };
488
489 par_io@e0100 {
490 #address-cells = <1>;
491 #size-cells = <1>;
492 reg = <0xe0100 0x60>;
493 ranges = <0x0 0xe0100 0x60>;
494 device_type = "par_io";
495 num-ports = <3>;
496 pio1: ucc_pin@01 {
497 pio-map = <
498 /* port pin dir open_drain assignment has_irq */
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
507 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
508 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
509 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
510 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
511 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
512 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
513 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
514 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
515 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
516 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
517 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
518 };
519
520 pio2: ucc_pin@02 {
521 pio-map = <
522 /* port pin dir open_drain assignment has_irq */
523 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
524 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
525 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
526 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
527 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
528 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
529 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
530 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
531 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
532 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
533 };
534 };
535 };
536
537 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000
565 0x0 0x20000000
566
567 0x1000000 0x0 0x0
568 0x1000000 0x0 0x0
569 0x0 0x100000>;
570 };
571 };
572
573 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000
601 0x0 0x20000000
602
603 0x1000000 0x0 0x0
604 0x1000000 0x0 0x0
605 0x0 0x100000>;
606 };
607 };
608
609 qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>;
617 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620
621 qeic: interrupt-controller@80 {
622 interrupt-controller;
623 compatible = "fsl,qe-ic";
624 #address-cells = <0>;
625 #interrupt-cells = <1>;
626 reg = <0x80 0x80>;
627 interrupts = <63 2 60 2>; //high:47 low:44
628 interrupt-parent = <&mpic>;
629 };
630
631 enet3: ucc@2000 {
632 device_type = "network";
633 compatible = "ucc_geth";
634 cell-index = <1>;
635 reg = <0x2000 0x200>;
636 interrupts = <32>;
637 interrupt-parent = <&qeic>;
638 local-mac-address = [ 00 00 00 00 00 00 ];
639 rx-clock-name = "clk12";
640 tx-clock-name = "clk9";
641 pio-handle = <&pio1>;
642 phy-handle = <&qe_phy0>;
643 phy-connection-type = "mii";
644 };
645
646 mdio@2120 {
647 #address-cells = <1>;
648 #size-cells = <0>;
649 reg = <0x2120 0x18>;
650 compatible = "fsl,ucc-mdio";
651
652 qe_phy0: ethernet-phy@0 {
653 interrupt-parent = <&mpic>;
654 interrupts = <4 1>;
655 reg = <0x0>;
656 device_type = "ethernet-phy";
657 };
658 qe_phy1: ethernet-phy@03 {
659 interrupt-parent = <&mpic>;
660 interrupts = <5 1>;
661 reg = <0x3>;
662 device_type = "ethernet-phy";
663 };
664 tbi-phy@11 {
665 reg = <0x11>;
666 device_type = "tbi-phy";
667 };
668 };
669
670 enet4: ucc@2400 {
671 device_type = "network";
672 compatible = "ucc_geth";
673 cell-index = <5>;
674 reg = <0x2400 0x200>;
675 interrupts = <40>;
676 interrupt-parent = <&qeic>;
677 local-mac-address = [ 00 00 00 00 00 00 ];
678 rx-clock-name = "none";
679 tx-clock-name = "clk13";
680 pio-handle = <&pio2>;
681 phy-handle = <&qe_phy1>;
682 phy-connection-type = "rmii";
683 };
684
685 muram@10000 {
686 #address-cells = <1>;
687 #size-cells = <1>;
688 compatible = "fsl,qe-muram", "fsl,cpm-muram";
689 ranges = <0x0 0x10000 0x6000>;
690
691 data-only@0 {
692 compatible = "fsl,qe-muram-data",
693 "fsl,cpm-muram-data";
694 reg = <0x0 0x6000>;
695 };
696 };
697 };
698};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index f0684c8ac960..8fe87fc61485 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. 2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
3 * 3 *
4 * Author: Andy Fleming <afleming@freescale.com> 4 * Author: Andy Fleming <afleming@freescale.com>
5 * 5 *
@@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
154 * Setup the architecture 154 * Setup the architecture
155 * 155 *
156 */ 156 */
157#ifdef CONFIG_SMP
158extern void __init mpc85xx_smp_init(void);
159#endif
160
157static void __init mpc85xx_mds_setup_arch(void) 161static void __init mpc85xx_mds_setup_arch(void)
158{ 162{
159 struct device_node *np; 163 struct device_node *np;
@@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void)
194 } 198 }
195#endif 199#endif
196 200
201#ifdef CONFIG_SMP
202 mpc85xx_smp_init();
203#endif
204
197#ifdef CONFIG_QUICC_ENGINE 205#ifdef CONFIG_QUICC_ENGINE
198 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 206 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
199 if (!np) { 207 if (!np) {
@@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void)
271 BCSR_UCC_RGMII, BCSR_UCC_RTBI); 279 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
272 } 280 }
273 281
282 } else if (machine_is(p1021_mds)) {
283#define BCSR11_ENET_MICRST (0x1 << 5)
284 /* Reset Micrel PHY */
285 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
286 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
274 } 287 }
288
275 iounmap(bcsr_regs); 289 iounmap(bcsr_regs);
276 } 290 }
291
292 if (machine_is(p1021_mds)) {
293#define MPC85xx_PMUXCR_OFFSET 0x60
294#define MPC85xx_PMUXCR_QE0 0x00008000
295#define MPC85xx_PMUXCR_QE3 0x00001000
296#define MPC85xx_PMUXCR_QE9 0x00000040
297#define MPC85xx_PMUXCR_QE12 0x00000008
298 static __be32 __iomem *pmuxcr;
299
300 np = of_find_node_by_name(NULL, "global-utilities");
301
302 if (np) {
303 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
304
305 if (!pmuxcr)
306 printk(KERN_EMERG "Error: Alternate function"
307 " signal multiplex control register not"
308 " mapped!\n");
309 else
310 /* P1021 has pins muxed for QE and other functions. To
311 * enable QE UEC mode, we need to set bit QE0 for UCC1
312 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
313 * and QE12 for QE MII management singals in PMUXCR
314 * register.
315 */
316 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
317 MPC85xx_PMUXCR_QE3 |
318 MPC85xx_PMUXCR_QE9 |
319 MPC85xx_PMUXCR_QE12);
320
321 of_node_put(np);
322 }
323
324 }
277#endif /* CONFIG_QUICC_ENGINE */ 325#endif /* CONFIG_QUICC_ENGINE */
278 326
279#ifdef CONFIG_SWIOTLB 327#ifdef CONFIG_SWIOTLB
@@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = {
330 {}, 378 {},
331}; 379};
332 380
381static struct of_device_id p1021_ids[] = {
382 { .type = "soc", },
383 { .compatible = "soc", },
384 { .compatible = "simple-bus", },
385 { .type = "qe", },
386 { .compatible = "fsl,qe", },
387 { .compatible = "gianfar", },
388 {},
389};
390
333static int __init mpc85xx_publish_devices(void) 391static int __init mpc85xx_publish_devices(void)
334{ 392{
335 if (machine_is(mpc8568_mds)) 393 if (machine_is(mpc8568_mds))
@@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void)
342 400
343 return 0; 401 return 0;
344} 402}
403
404static int __init p1021_publish_devices(void)
405{
406 /* Publish the QE devices */
407 of_platform_bus_probe(NULL, p1021_ids, NULL);
408
409 return 0;
410}
411
345machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 412machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
346machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 413machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
414machine_device_initcall(p1021_mds, p1021_publish_devices);
347 415
348machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 416machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
349machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 417machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
418machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
350 419
351static void __init mpc85xx_mds_pic_init(void) 420static void __init mpc85xx_mds_pic_init(void)
352{ 421{
@@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void)
366 435
367 mpic = mpic_alloc(np, r.start, 436 mpic = mpic_alloc(np, r.start,
368 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | 437 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
369 MPIC_BROKEN_FRR_NIRQS, 438 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
370 0, 256, " OpenPIC "); 439 0, 256, " OpenPIC ");
371 BUG_ON(mpic == NULL); 440 BUG_ON(mpic == NULL);
372 of_node_put(np); 441 of_node_put(np);
@@ -380,7 +449,11 @@ static void __init mpc85xx_mds_pic_init(void)
380 if (!np) 449 if (!np)
381 return; 450 return;
382 } 451 }
383 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); 452 if (machine_is(p1021_mds))
453 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
454 qe_ic_cascade_high_mpic);
455 else
456 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
384 of_node_put(np); 457 of_node_put(np);
385#endif /* CONFIG_QUICC_ENGINE */ 458#endif /* CONFIG_QUICC_ENGINE */
386} 459}
@@ -426,3 +499,26 @@ define_machine(mpc8569_mds) {
426 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 499 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
427#endif 500#endif
428}; 501};
502
503static int __init p1021_mds_probe(void)
504{
505 unsigned long root = of_get_flat_dt_root();
506
507 return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
508
509}
510
511define_machine(p1021_mds) {
512 .name = "P1021 MDS",
513 .probe = p1021_mds_probe,
514 .setup_arch = mpc85xx_mds_setup_arch,
515 .init_IRQ = mpc85xx_mds_pic_init,
516 .get_irq = mpic_get_irq,
517 .restart = fsl_rstcr_restart,
518 .calibrate_decr = generic_calibrate_decr,
519 .progress = udbg_progress,
520#ifdef CONFIG_PCI
521 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
522#endif
523};
524
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 08:18:27 -0400