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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-10 21:37:49 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-10 21:37:49 -0500
commit6a4d7a90fc452171eabb4b5b23ab780451ae7f5b (patch)
treeddd39820114f1d7e66c47516139ccf2d45a6f019 /arch/powerpc
parentedbc29d76ddbc9bd56e1cbc772188f70c616ffe1 (diff)
parentbdad05489fe5f7487c7a22ef311f005cb62ebbb6 (diff)
Merge commit 'gcl/next' into next
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/Makefile4
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts49
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts254
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts52
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts63
-rw-r--r--arch/powerpc/boot/dts/media5200.dts318
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts42
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts182
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts32
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig12
-rw-r--r--arch/powerpc/platforms/52xx/Makefile3
-rw-r--r--arch/powerpc/platforms/52xx/media5200.c273
-rw-r--r--arch/powerpc/platforms/52xx/mpc5200_simple.c1
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpio.c85
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpt.c435
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_pic.c170
16 files changed, 1462 insertions, 513 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index e84df338ea29..8244813bc5a6 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
235 dtbImage.adder875-redboot 235 dtbImage.adder875-redboot
236 236
237# Board ports in arch/powerpc/platform/52xx/Kconfig 237# Board ports in arch/powerpc/platform/52xx/Kconfig
238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b 238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
239image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
240image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
239 241
240# Board ports in arch/powerpc/platform/82xx/Kconfig 242# Board ports in arch/powerpc/platform/82xx/Kconfig
241image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads 243image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2f74cc4e093e..cee8080aa245 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,84 +74,76 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
111 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 107 };
114 108
115 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
118 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 }; 113 };
121 114
122 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
123 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
124 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
125 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 }; 119 };
128 120
129 gpio@b00 { 121 gpio_simple: gpio@b00 {
130 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
131 reg = <0xb00 0x40>; 123 reg = <0xb00 0x40>;
132 interrupts = <1 7 0>; 124 interrupts = <1 7 0>;
133 interrupt-parent = <&mpc5200_pic>; 125 gpio-controller;
126 #gpio-cells = <2>;
134 }; 127 };
135 128
136 gpio@c00 { 129 gpio_wkup: gpio@c00 {
137 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
138 reg = <0xc00 0x40>; 131 reg = <0xc00 0x40>;
139 interrupts = <1 8 0 0 3 0>; 132 interrupts = <1 8 0 0 3 0>;
140 interrupt-parent = <&mpc5200_pic>; 133 gpio-controller;
134 #gpio-cells = <2>;
141 }; 135 };
142 136
143 spi@f00 { 137 spi@f00 {
144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
145 reg = <0xf00 0x20>; 139 reg = <0xf00 0x20>;
146 interrupts = <2 13 0 2 14 0>; 140 interrupts = <2 13 0 2 14 0>;
147 interrupt-parent = <&mpc5200_pic>;
148 }; 141 };
149 142
150 usb@1000 { 143 usb@1000 {
151 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
152 reg = <0x1000 0xff>; 145 reg = <0x1000 0xff>;
153 interrupts = <2 6 0>; 146 interrupts = <2 6 0>;
154 interrupt-parent = <&mpc5200_pic>;
155 }; 147 };
156 148
157 dma-controller@1200 { 149 dma-controller@1200 {
@@ -161,7 +153,6 @@
161 3 4 0 3 5 0 3 6 0 3 7 0 153 3 4 0 3 5 0 3 6 0 3 7 0
162 3 8 0 3 9 0 3 10 0 3 11 0 154 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>; 155 3 12 0 3 13 0 3 14 0 3 15 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 xlb@1f00 { 158 xlb@1f00 {
@@ -170,48 +161,34 @@
170 }; 161 };
171 162
172 serial@2000 { // PSC1 163 serial@2000 { // PSC1
173 device_type = "serial";
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 port-number = <0>; // Logical port assignment
176 reg = <0x2000 0x100>; 165 reg = <0x2000 0x100>;
177 interrupts = <2 1 0>; 166 interrupts = <2 1 0>;
178 interrupt-parent = <&mpc5200_pic>;
179 }; 167 };
180 168
181 serial@2200 { // PSC2 169 serial@2200 { // PSC2
182 device_type = "serial"; 170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 compatible = "fsl,mpc5200-psc-uart";
184 port-number = <1>; // Logical port assignment
185 reg = <0x2200 0x100>; 171 reg = <0x2200 0x100>;
186 interrupts = <2 2 0>; 172 interrupts = <2 2 0>;
187 interrupt-parent = <&mpc5200_pic>;
188 }; 173 };
189 174
190 serial@2400 { // PSC3 175 serial@2400 { // PSC3
191 device_type = "serial"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
192 compatible = "fsl,mpc5200-psc-uart";
193 port-number = <2>; // Logical port assignment
194 reg = <0x2400 0x100>; 177 reg = <0x2400 0x100>;
195 interrupts = <2 3 0>; 178 interrupts = <2 3 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 179 };
198 180
199 serial@2c00 { // PSC6 181 serial@2c00 { // PSC6
200 device_type = "serial";
201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
202 port-number = <5>; // Logical port assignment
203 reg = <0x2c00 0x100>; 183 reg = <0x2c00 0x100>;
204 interrupts = <2 4 0>; 184 interrupts = <2 4 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 185 };
207 186
208 ethernet@3000 { 187 ethernet@3000 {
209 device_type = "network";
210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
211 reg = <0x3000 0x400>; 189 reg = <0x3000 0x400>;
212 local-mac-address = [ 00 00 00 00 00 00 ]; 190 local-mac-address = [ 00 00 00 00 00 00 ];
213 interrupts = <2 5 0>; 191 interrupts = <2 5 0>;
214 interrupt-parent = <&mpc5200_pic>;
215 phy-handle = <&phy0>; 192 phy-handle = <&phy0>;
216 }; 193 };
217 194
@@ -221,10 +198,8 @@
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 interrupt-parent = <&mpc5200_pic>;
225 201
226 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
227 device_type = "ethernet-phy";
228 reg = <0>; 203 reg = <0>;
229 }; 204 };
230 }; 205 };
@@ -235,7 +210,6 @@
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d40 0x40>; 211 reg = <0x3d40 0x40>;
237 interrupts = <2 16 0>; 212 interrupts = <2 16 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 fsl5200-clocking; 213 fsl5200-clocking;
240 }; 214 };
241 215
@@ -245,9 +219,8 @@
245 }; 219 };
246 }; 220 };
247 221
248 lpb { 222 localbus {
249 model = "fsl,lpb"; 223 compatible = "fsl,mpc5200b-lpb","simple-bus";
250 compatible = "fsl,lpb";
251 #address-cells = <2>; 224 #address-cells = <2>;
252 #size-cells = <1>; 225 #size-cells = <1>;
253 ranges = <0 0 0xfc000000 0x2000000>; 226 ranges = <0 0 0xfc000000 0x2000000>;
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
new file mode 100644
index 000000000000..0e85ebf7e4c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -0,0 +1,254 @@
1/*
2 * Digsy MTC board Device Tree Source
3 *
4 * Copyright (C) 2009 Semihalf
5 *
6 * Based on the CM5200 by M. Balakowicz
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x02000000>; // 32MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt;
72 };
73
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 };
85
86 timer@630 { // General Purpose Timer
87 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <0x640 0x10>;
95 interrupts = <1 13 0>;
96 };
97
98 timer@650 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <0x650 0x10>;
101 interrupts = <1 14 0>;
102 };
103
104 timer@660 { // General Purpose Timer
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 };
109
110 timer@670 { // General Purpose Timer
111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 reg = <0x670 0x10>;
113 interrupts = <1 16 0>;
114 };
115
116 gpio_simple: gpio@b00 {
117 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
118 reg = <0xb00 0x40>;
119 interrupts = <1 7 0>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
124 gpio_wkup: gpio@c00 {
125 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
126 reg = <0xc00 0x40>;
127 interrupts = <1 8 0 0 3 0>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 };
131
132 spi@f00 {
133 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
134 reg = <0xf00 0x20>;
135 interrupts = <2 13 0 2 14 0>;
136 };
137
138 usb@1000 {
139 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
140 reg = <0x1000 0xff>;
141 interrupts = <2 6 0>;
142 };
143
144 dma-controller@1200 {
145 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
146 reg = <0x1200 0x80>;
147 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
148 3 4 0 3 5 0 3 6 0 3 7 0
149 3 8 0 3 9 0 3 10 0 3 11 0
150 3 12 0 3 13 0 3 14 0 3 15 0>;
151 };
152
153 xlb@1f00 {
154 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
155 reg = <0x1f00 0x100>;
156 };
157
158 serial@2400 { // PSC3
159 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x2400 0x100>;
161 interrupts = <2 3 0>;
162 };
163
164 serial@2600 { // PSC4
165 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
166 reg = <0x2600 0x100>;
167 interrupts = <2 11 0>;
168 };
169
170 ethernet@3000 {
171 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
172 reg = <0x3000 0x400>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <2 5 0>;
175 phy-handle = <&phy0>;
176 };
177
178 mdio@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
182 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
183 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
184
185 phy0: ethernet-phy@0 {
186 reg = <0>;
187 };
188 };
189
190 ata@3a00 {
191 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
192 reg = <0x3a00 0x100>;
193 interrupts = <2 7 0>;
194 };
195
196 i2c@3d00 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>;
202 fsl5200-clocking;
203
204 rtc@50 {
205 compatible = "at,24c08";
206 reg = <0x50>;
207 };
208
209 rtc@68 {
210 compatible = "dallas,ds1339";
211 reg = <0x68>;
212 };
213 };
214
215 sram@8000 {
216 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
217 reg = <0x8000 0x4000>;
218 };
219 };
220
221 lpb {
222 compatible = "fsl,mpc5200b-lpb","simple-bus";
223 #address-cells = <2>;
224 #size-cells = <1>;
225 ranges = <0 0 0xff000000 0x1000000>;
226
227 // 16-bit flash device at LocalPlus Bus CS0
228 flash@0,0 {
229 compatible = "cfi-flash";
230 reg = <0 0 0x1000000>;
231 bank-width = <2>;
232 device-width = <2>;
233 #size-cells = <1>;
234 #address-cells = <1>;
235
236 partition@0 {
237 label = "kernel";
238 reg = <0x0 0x00200000>;
239 };
240 partition@200000 {
241 label = "root";
242 reg = <0x00200000 0x00300000>;
243 };
244 partition@500000 {
245 label = "user";
246 reg = <0x00500000 0x00a00000>;
247 };
248 partition@f00000 {
249 label = "u-boot";
250 reg = <0x00f00000 0x100000>;
251 };
252 };
253 };
254};
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 3f7a5dce8de0..de30b3f9eb26 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200"; 17 compatible = "fsl,lite5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,96 +59,74 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
@@ -155,39 +134,33 @@
155 compatible = "fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>;
159 }; 137 };
160 138
161 gpio@c00 { 139 gpio@c00 {
162 compatible = "fsl,mpc5200-gpio-wkup"; 140 compatible = "fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 141 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 142 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>;
166 }; 143 };
167 144
168 spi@f00 { 145 spi@f00 {
169 compatible = "fsl,mpc5200-spi"; 146 compatible = "fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 147 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 148 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 149 };
174 150
175 usb@1000 { 151 usb@1000 {
176 compatible = "fsl,mpc5200-ohci","ohci-be"; 152 compatible = "fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 153 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 154 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 155 };
181 156
182 dma-controller@1200 { 157 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200-bestcomm"; 158 compatible = "fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 159 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 161 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 162 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 163 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 164 };
192 165
193 xlb@1f00 { 166 xlb@1f00 {
@@ -196,13 +169,10 @@
196 }; 169 };
197 170
198 serial@2000 { // PSC1 171 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200-psc-uart"; 172 compatible = "fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 173 cell-index = <0>;
203 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 176 };
207 177
208 // PSC2 in ac97 mode example 178 // PSC2 in ac97 mode example
@@ -211,7 +181,6 @@
211 // cell-index = <1>; 181 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 182 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 183 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 184 //};
216 185
217 // PSC3 in CODEC mode example 186 // PSC3 in CODEC mode example
@@ -220,27 +189,22 @@
220 // cell-index = <2>; 189 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 190 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 191 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 192 //};
225 193
226 // PSC4 in uart mode example 194 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 195 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200-psc-uart"; 196 // compatible = "fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 197 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 198 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 199 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 200 //};
235 201
236 // PSC5 in uart mode example 202 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 203 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200-psc-uart"; 204 // compatible = "fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 205 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 206 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 207 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 208 //};
245 209
246 // PSC6 in spi mode example 210 // PSC6 in spi mode example
@@ -249,16 +213,13 @@
249 // cell-index = <5>; 213 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 214 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 215 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 216 //};
254 217
255 ethernet@3000 { 218 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200-fec"; 219 compatible = "fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 220 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 221 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 222 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 223 phy-handle = <&phy0>;
263 }; 224 };
264 225
@@ -268,30 +229,24 @@
268 compatible = "fsl,mpc5200-mdio"; 229 compatible = "fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 232
273 phy0: ethernet-phy@1 { 233 phy0: ethernet-phy@1 {
274 device_type = "ethernet-phy";
275 reg = <1>; 234 reg = <1>;
276 }; 235 };
277 }; 236 };
278 237
279 ata@3a00 { 238 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200-ata"; 239 compatible = "fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 240 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 241 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 242 };
286 243
287 i2c@3d00 { 244 i2c@3d00 {
288 #address-cells = <1>; 245 #address-cells = <1>;
289 #size-cells = <0>; 246 #size-cells = <0>;
290 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 248 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 249 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 250 fsl5200-clocking;
296 }; 251 };
297 252
@@ -299,14 +254,12 @@
299 #address-cells = <1>; 254 #address-cells = <1>;
300 #size-cells = <0>; 255 #size-cells = <0>;
301 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 256 compatible = "fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 257 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 258 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 259 fsl5200-clocking;
307 }; 260 };
308 sram@8000 { 261 sram@8000 {
309 compatible = "fsl,mpc5200-sram","sram"; 262 compatible = "fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 263 reg = <0x8000 0x4000>;
311 }; 264 };
312 }; 265 };
@@ -325,7 +278,6 @@
325 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 278 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
326 clock-frequency = <0>; // From boot loader 279 clock-frequency = <0>; // From boot loader
327 interrupts = <2 8 0 2 9 0 2 10 0>; 280 interrupts = <2 8 0 2 9 0 2 10 0>;
328 interrupt-parent = <&mpc5200_pic>;
329 bus-range = <0 0>; 281 bus-range = <0 0>;
330 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 282 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
331 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 283 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 63e3bb48e843..c63e3566479e 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,136 +59,112 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
154 gpio@b00 { 133 gpio_simple: gpio@b00 {
155 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>; 137 gpio-controller;
138 #gpio-cells = <2>;
159 }; 139 };
160 140
161 gpio@c00 { 141 gpio_wkup: gpio@c00 {
162 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 143 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 144 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>; 145 gpio-controller;
146 #gpio-cells = <2>;
166 }; 147 };
167 148
168 spi@f00 { 149 spi@f00 {
169 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 151 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 152 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 153 };
174 154
175 usb@1000 { 155 usb@1000 {
176 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 157 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 158 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 159 };
181 160
182 dma-controller@1200 { 161 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 163 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 166 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 167 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 168 };
192 169
193 xlb@1f00 { 170 xlb@1f00 {
@@ -196,13 +173,10 @@
196 }; 173 };
197 174
198 serial@2000 { // PSC1 175 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 177 cell-index = <0>;
203 reg = <0x2000 0x100>; 178 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 179 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 180 };
207 181
208 // PSC2 in ac97 mode example 182 // PSC2 in ac97 mode example
@@ -211,7 +185,6 @@
211 // cell-index = <1>; 185 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 186 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 187 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 188 //};
216 189
217 // PSC3 in CODEC mode example 190 // PSC3 in CODEC mode example
@@ -220,27 +193,22 @@
220 // cell-index = <2>; 193 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 194 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 195 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 196 //};
225 197
226 // PSC4 in uart mode example 198 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 199 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 201 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 202 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 203 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 204 //};
235 205
236 // PSC5 in uart mode example 206 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 207 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 209 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 210 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 211 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 212 //};
245 213
246 // PSC6 in spi mode example 214 // PSC6 in spi mode example
@@ -249,49 +217,40 @@
249 // cell-index = <5>; 217 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 218 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 219 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 220 //};
254 221
255 ethernet@3000 { 222 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 224 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 225 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 226 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 227 phy-handle = <&phy0>;
263 }; 228 };
264 229
265 mdio@3000 { 230 mdio@3000 {
266 #address-cells = <1>; 231 #address-cells = <1>;
267 #size-cells = <0>; 232 #size-cells = <0>;
268 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 236
273 phy0: ethernet-phy@0 { 237 phy0: ethernet-phy@0 {
274 device_type = "ethernet-phy";
275 reg = <0>; 238 reg = <0>;
276 }; 239 };
277 }; 240 };
278 241
279 ata@3a00 { 242 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 244 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 245 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 246 };
286 247
287 i2c@3d00 { 248 i2c@3d00 {
288 #address-cells = <1>; 249 #address-cells = <1>;
289 #size-cells = <0>; 250 #size-cells = <0>;
290 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 252 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 253 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 254 fsl5200-clocking;
296 }; 255 };
297 256
@@ -299,14 +258,13 @@
299 #address-cells = <1>; 258 #address-cells = <1>;
300 #size-cells = <0>; 259 #size-cells = <0>;
301 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 261 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 262 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 263 fsl5200-clocking;
307 }; 264 };
265
308 sram@8000 { 266 sram@8000 {
309 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 267 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 268 reg = <0x8000 0x4000>;
311 }; 269 };
312 }; 270 };
@@ -330,7 +288,6 @@
330 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 288 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
331 clock-frequency = <0>; // From boot loader 289 clock-frequency = <0>; // From boot loader
332 interrupts = <2 8 0 2 9 0 2 10 0>; 290 interrupts = <2 8 0 2 9 0 2 10 0>;
333 interrupt-parent = <&mpc5200_pic>;
334 bus-range = <0 0>; 291 bus-range = <0 0>;
335 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 292 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
336 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 293 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
new file mode 100644
index 000000000000..e297d8b41875
--- /dev/null
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -0,0 +1,318 @@
1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,media5200";
18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 aliases {
24 console = &console;
25 ethernet0 = &eth0;
26 };
27
28 chosen {
29 linux,stdout-path = &console;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM
52 };
53
54 soc@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75
76 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt;
81 };
82
83 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 };
136
137 can@980 {
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 };
142
143 gpio_simple: gpio@b00 {
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpio_wkup: gpio@c00 {
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158
159 spi@f00 {
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 };
184
185 // PSC6 in uart mode
186 console: serial@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 cell-index = <5>;
189 port-number = <0>; // Logical port assignment
190 reg = <0x2c00 0x100>;
191 interrupts = <2 4 0>;
192 };
193
194 eth0: ethernet@3000 {
195 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
196 reg = <0x3000 0x400>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <2 5 0>;
199 phy-handle = <&phy0>;
200 };
201
202 mdio@3000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
206 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
207 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
208
209 phy0: ethernet-phy@0 {
210 reg = <0>;
211 };
212 };
213
214 ata@3a00 {
215 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
216 reg = <0x3a00 0x100>;
217 interrupts = <2 7 0>;
218 };
219
220 i2c@3d00 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>;
226 fsl5200-clocking;
227 };
228
229 i2c@3d40 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
233 reg = <0x3d40 0x40>;
234 interrupts = <2 16 0>;
235 fsl5200-clocking;
236 };
237
238 sram@8000 {
239 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
240 reg = <0x8000 0x4000>;
241 };
242 };
243
244 pci@f0000d00 {
245 #interrupt-cells = <1>;
246 #size-cells = <2>;
247 #address-cells = <3>;
248 device_type = "pci";
249 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
250 reg = <0xf0000d00 0x100>;
251 interrupt-map-mask = <0xf800 0 0 7>;
252 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
253 0xc000 0 0 2 &media5200_fpga 0 3
254 0xc000 0 0 3 &media5200_fpga 0 4
255 0xc000 0 0 4 &media5200_fpga 0 5
256
257 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
258 0xc800 0 0 2 &media5200_fpga 0 4
259 0xc800 0 0 3 &media5200_fpga 0 5
260 0xc800 0 0 4 &media5200_fpga 0 2
261
262 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
263 0xd000 0 0 2 &media5200_fpga 0 5
264
265 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
266 >;
267 clock-frequency = <0>; // From boot loader
268 interrupts = <2 8 0 2 9 0 2 10 0>;
269 interrupt-parent = <&mpc5200_pic>;
270 bus-range = <0 0>;
271 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
272 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
273 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
274 };
275
276 localbus {
277 compatible = "fsl,mpc5200b-lpb","simple-bus";
278 #address-cells = <2>;
279 #size-cells = <1>;
280
281 ranges = < 0 0 0xfc000000 0x02000000
282 1 0 0xfe000000 0x02000000
283 2 0 0xf0010000 0x00010000
284 3 0 0xf0020000 0x00010000 >;
285
286 flash@0,0 {
287 compatible = "amd,am29lv28ml", "cfi-flash";
288 reg = <0 0x0 0x2000000>; // 32 MB
289 bank-width = <4>; // Width in bytes of the flash bank
290 device-width = <2>; // Two devices on each bank
291 };
292
293 flash@1,0 {
294 compatible = "amd,am29lv28ml", "cfi-flash";
295 reg = <1 0 0x2000000>; // 32 MB
296 bank-width = <4>; // Width in bytes of the flash bank
297 device-width = <2>; // Two devices on each bank
298 };
299
300 media5200_fpga: fpga@2,0 {
301 compatible = "fsl,media5200-fpga";
302 interrupt-controller;
303 #interrupt-cells = <2>; // 0:bank 1:id; no type field
304 reg = <2 0 0x10000>;
305
306 interrupt-parent = <&mpc5200_pic>;
307 interrupts = <0 0 3 // IRQ bank 0
308 1 1 3>; // IRQ bank 1
309 };
310
311 uart@3,0 {
312 compatible = "ti,tl16c752bpt";
313 reg = <3 0 0x10000>;
314 interrupt-parent = <&media5200_fpga>;
315 interrupts = <0 0 0 1>; // 2 irqs
316 };
317 };
318};
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 52ba6f98b273..7be8ca038676 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -17,6 +17,7 @@
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,35 +74,30 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 motionpro-led@660 { // Motion-PRO status LED 103 motionpro-led@660 { // Motion-PRO status LED
@@ -110,7 +105,6 @@
110 label = "motionpro-statusled"; 105 label = "motionpro-statusled";
111 reg = <0x660 0x10>; 106 reg = <0x660 0x10>;
112 interrupts = <1 15 0>; 107 interrupts = <1 15 0>;
113 interrupt-parent = <&mpc5200_pic>;
114 blink-delay = <100>; // 100 msec 108 blink-delay = <100>; // 100 msec
115 }; 109 };
116 110
@@ -119,49 +113,46 @@
119 label = "motionpro-readyled"; 113 label = "motionpro-readyled";
120 reg = <0x670 0x10>; 114 reg = <0x670 0x10>;
121 interrupts = <1 16 0>; 115 interrupts = <1 16 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 116 };
124 117
125 rtc@800 { // Real time clock 118 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>; 120 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>; 121 interrupts = <1 5 0 1 6 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 }; 122 };
131 123
132 can@980 { 124 can@980 {
133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>; 126 interrupts = <2 18 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 reg = <0x980 0x80>; 127 reg = <0x980 0x80>;
137 }; 128 };
138 129
139 gpio@b00 { 130 gpio_simple: gpio@b00 {
140 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
141 reg = <0xb00 0x40>; 132 reg = <0xb00 0x40>;
142 interrupts = <1 7 0>; 133 interrupts = <1 7 0>;
143 interrupt-parent = <&mpc5200_pic>; 134 gpio-controller;
135 #gpio-cells = <2>;
144 }; 136 };
145 137
146 gpio@c00 { 138 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>; 140 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 3 0>; 141 interrupts = <1 8 0 0 3 0>;
150 interrupt-parent = <&mpc5200_pic>; 142 gpio-controller;
143 #gpio-cells = <2>;
151 }; 144 };
152 145
153 spi@f00 { 146 spi@f00 {
154 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
155 reg = <0xf00 0x20>; 148 reg = <0xf00 0x20>;
156 interrupts = <2 13 0 2 14 0>; 149 interrupts = <2 13 0 2 14 0>;
157 interrupt-parent = <&mpc5200_pic>;
158 }; 150 };
159 151
160 usb@1000 { 152 usb@1000 {
161 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
162 reg = <0x1000 0xff>; 154 reg = <0x1000 0xff>;
163 interrupts = <2 6 0>; 155 interrupts = <2 6 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 dma-controller@1200 { 158 dma-controller@1200 {
@@ -171,7 +162,6 @@
171 3 4 0 3 5 0 3 6 0 3 7 0 162 3 4 0 3 5 0 3 6 0 3 7 0
172 3 8 0 3 9 0 3 10 0 3 11 0 163 3 8 0 3 9 0 3 10 0 3 11 0
173 3 12 0 3 13 0 3 14 0 3 15 0>; 164 3 12 0 3 13 0 3 14 0 3 15 0>;
174 interrupt-parent = <&mpc5200_pic>;
175 }; 165 };
176 166
177 xlb@1f00 { 167 xlb@1f00 {
@@ -180,12 +170,9 @@
180 }; 170 };
181 171
182 serial@2000 { // PSC1 172 serial@2000 { // PSC1
183 device_type = "serial";
184 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
185 port-number = <0>; // Logical port assignment
186 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
187 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
188 interrupt-parent = <&mpc5200_pic>;
189 }; 176 };
190 177
191 // PSC2 in spi master mode 178 // PSC2 in spi master mode
@@ -194,26 +181,20 @@
194 cell-index = <1>; 181 cell-index = <1>;
195 reg = <0x2200 0x100>; 182 reg = <0x2200 0x100>;
196 interrupts = <2 2 0>; 183 interrupts = <2 2 0>;
197 interrupt-parent = <&mpc5200_pic>;
198 }; 184 };
199 185
200 // PSC5 in uart mode 186 // PSC5 in uart mode
201 serial@2800 { // PSC5 187 serial@2800 { // PSC5
202 device_type = "serial";
203 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
204 port-number = <4>; // Logical port assignment
205 reg = <0x2800 0x100>; 189 reg = <0x2800 0x100>;
206 interrupts = <2 12 0>; 190 interrupts = <2 12 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 191 };
209 192
210 ethernet@3000 { 193 ethernet@3000 {
211 device_type = "network";
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>; 195 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ]; 196 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>; 197 interrupts = <2 5 0>;
216 interrupt-parent = <&mpc5200_pic>;
217 phy-handle = <&phy0>; 198 phy-handle = <&phy0>;
218 }; 199 };
219 200
@@ -223,10 +204,8 @@
223 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
224 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
225 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
226 interrupt-parent = <&mpc5200_pic>;
227 207
228 phy0: ethernet-phy@2 { 208 phy0: ethernet-phy@2 {
229 device_type = "ethernet-phy";
230 reg = <2>; 209 reg = <2>;
231 }; 210 };
232 }; 211 };
@@ -235,7 +214,6 @@
235 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
236 reg = <0x3a00 0x100>; 215 reg = <0x3a00 0x100>;
237 interrupts = <2 7 0>; 216 interrupts = <2 7 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 }; 217 };
240 218
241 i2c@3d40 { 219 i2c@3d40 {
@@ -244,7 +222,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d40 0x40>; 223 reg = <0x3d40 0x40>;
246 interrupts = <2 16 0>; 224 interrupts = <2 16 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 fsl5200-clocking; 225 fsl5200-clocking;
249 226
250 rtc@68 { 227 rtc@68 {
@@ -259,8 +236,8 @@
259 }; 236 };
260 }; 237 };
261 238
262 lpb { 239 localbus {
263 compatible = "fsl,lpb"; 240 compatible = "fsl,mpc5200b-lpb","simple-bus";
264 #address-cells = <2>; 241 #address-cells = <2>;
265 #size-cells = <1>; 242 #size-cells = <1>;
266 ranges = <0 0 0xff000000 0x01000000 243 ranges = <0 0 0xff000000 0x01000000
@@ -273,7 +250,6 @@
273 compatible = "promess,motionpro-kollmorgen"; 250 compatible = "promess,motionpro-kollmorgen";
274 reg = <1 0 0x10000>; 251 reg = <1 0 0x10000>;
275 interrupts = <1 1 0>; 252 interrupts = <1 1 0>;
276 interrupt-parent = <&mpc5200_pic>;
277 }; 253 };
278 254
279 // 8-bit board CPLD on LocalPlus Bus CS2 255 // 8-bit board CPLD on LocalPlus Bus CS2
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index be2c11ca0594..895834713894 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -19,6 +19,7 @@
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
22 23
23 cpus { 24 cpus {
24 #address-cells = <1>; 25 #address-cells = <1>;
@@ -29,26 +30,26 @@
29 reg = <0>; 30 reg = <0>;
30 d-cache-line-size = <32>; 31 d-cache-line-size = <32>;
31 i-cache-line-size = <32>; 32 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */ 33 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; /* L1, 16K */ 34 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; /* From Bootloader */ 35 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; /* From Bootloader */ 36 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; /* From Bootloader */ 37 clock-frequency = <0>; // from bootloader
37 }; 38 };
38 }; 39 };
39 40
40 memory { 41 memory {
41 device_type = "memory"; 42 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */ 43 reg = <0x00000000 0x04000000>; // 64MB
43 }; 44 };
44 45
45 soc5200@f0000000 { 46 soc5200@f0000000 {
46 #address-cells = <1>; 47 #address-cells = <1>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr"; 49 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>; 50 ranges = <0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */ 51 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; /* From bootloader */ 52 system-frequency = <0>; // from bootloader
52 53
53 cdm@200 { 54 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
@@ -56,87 +57,70 @@
56 }; 57 };
57 58
58 mpc5200_pic: interrupt-controller@500 { 59 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */ 60 // 5200 interrupts are encoded into two levels;
60 interrupt-controller; 61 interrupt-controller;
61 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { /* General Purpose Timer */ 67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>; 69 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>; 70 interrupts = <1 9 0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt; 71 fsl,has-wdt;
74 }; 72 };
75 73
76 timer@610 { /* General Purpose Timer */ 74 timer@610 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>; 76 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>; 77 interrupts = <1 10 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 }; 78 };
83 79
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>; 82 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>; 83 interrupts = <1 11 0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller; 84 gpio-controller;
91 #gpio-cells = <2>; 85 #gpio-cells = <2>;
92 }; 86 };
93 87
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>; 90 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>; 91 interrupts = <1 12 0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller; 92 gpio-controller;
101 #gpio-cells = <2>; 93 #gpio-cells = <2>;
102 }; 94 };
103 95
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>; 98 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>; 99 interrupts = <1 13 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller; 100 gpio-controller;
111 #gpio-cells = <2>; 101 #gpio-cells = <2>;
112 }; 102 };
113 103
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>; 107 interrupts = <1 14 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller; 108 gpio-controller;
121 #gpio-cells = <2>; 109 #gpio-cells = <2>;
122 }; 110 };
123 111
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>; 114 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>; 115 interrupts = <1 15 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller; 116 gpio-controller;
131 #gpio-cells = <2>; 117 #gpio-cells = <2>;
132 }; 118 };
133 119
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>; 122 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>; 123 interrupts = <1 16 0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller; 124 gpio-controller;
141 #gpio-cells = <2>; 125 #gpio-cells = <2>;
142 }; 126 };
@@ -144,40 +128,33 @@
144 rtc@800 { // Real time clock 128 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 reg = <0x800 0x100>; 130 reg = <0x800 0x100>;
147 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; 131 interrupts = <1 5 0 1 6 0>;
148 interrupt-parent = <&mpc5200_pic>;
149 }; 132 };
150 133
151 can@900 { 134 can@900 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <0>; 136 interrupts = <2 17 0>;
154 interrupts = <0x2 0x11 0x0>;
155 interrupt-parent = <&mpc5200_pic>;
156 reg = <0x900 0x80>; 137 reg = <0x900 0x80>;
157 }; 138 };
158 139
159 can@980 { 140 can@980 {
160 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
161 cell-index = <1>; 142 interrupts = <2 18 0>;
162 interrupts = <0x2 0x12 0x0>;
163 interrupt-parent = <&mpc5200_pic>;
164 reg = <0x980 0x80>; 143 reg = <0x980 0x80>;
165 }; 144 };
166 145
167 gpio_simple: gpio@b00 { 146 gpio_simple: gpio@b00 {
168 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
169 reg = <0xb00 0x40>; 148 reg = <0xb00 0x40>;
170 interrupts = <0x1 0x7 0x0>; 149 interrupts = <1 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 gpio-controller; 150 gpio-controller;
173 #gpio-cells = <2>; 151 #gpio-cells = <2>;
174 }; 152 };
175 153
176 gpio_wkup: gpio-wkup@c00 { 154 gpio_wkup: gpio@c00 {
177 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
178 reg = <0xc00 0x40>; 156 reg = <0xc00 0x40>;
179 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; 157 interrupts = <1 8 0 0 3 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 gpio-controller; 158 gpio-controller;
182 #gpio-cells = <2>; 159 #gpio-cells = <2>;
183 }; 160 };
@@ -185,26 +162,22 @@
185 spi@f00 { 162 spi@f00 {
186 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
187 reg = <0xf00 0x20>; 164 reg = <0xf00 0x20>;
188 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; 165 interrupts = <2 13 0 2 14 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 }; 166 };
191 167
192 usb@1000 { 168 usb@1000 {
193 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
194 reg = <0x1000 0xff>; 170 reg = <0x1000 0xff>;
195 interrupts = <0x2 0x6 0x0>; 171 interrupts = <2 6 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 172 };
198 173
199 dma-controller@1200 { 174 dma-controller@1200 {
200 device_type = "dma-controller";
201 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
202 reg = <0x1200 0x80>; 176 reg = <0x1200 0x80>;
203 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
204 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 178 3 4 0 3 5 0 3 6 0 3 7 0
205 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 179 3 8 0 3 9 0 3 10 0 3 11 0
206 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 180 3 12 0 3 13 0 3 14 0 3 15 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 181 };
209 182
210 xlb@1f00 { 183 xlb@1f00 {
@@ -213,24 +186,19 @@
213 }; 186 };
214 187
215 ac97@2000 { /* PSC1 in ac97 mode */ 188 ac97@2000 { /* PSC1 in ac97 mode */
216 device_type = "sound";
217 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
218 cell-index = <0>; 190 cell-index = <0>;
219 reg = <0x2000 0x100>; 191 reg = <0x2000 0x100>;
220 interrupts = <0x2 0x2 0x0>; 192 interrupts = <2 1 0>;
221 interrupt-parent = <&mpc5200_pic>;
222 }; 193 };
223 194
224 /* PSC2 port is used by CAN1/2 */ 195 /* PSC2 port is used by CAN1/2 */
225 196
226 serial@2400 { /* PSC3 in UART mode */ 197 serial@2400 { /* PSC3 in UART mode */
227 device_type = "serial";
228 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
229 port-number = <0>;
230 cell-index = <2>; 199 cell-index = <2>;
231 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
232 interrupts = <0x2 0x3 0x0>; 201 interrupts = <2 3 0>;
233 interrupt-parent = <&mpc5200_pic>;
234 }; 202 };
235 203
236 /* PSC4 is ??? */ 204 /* PSC4 is ??? */
@@ -238,55 +206,44 @@
238 /* PSC5 is ??? */ 206 /* PSC5 is ??? */
239 207
240 serial@2c00 { /* PSC6 in UART mode */ 208 serial@2c00 { /* PSC6 in UART mode */
241 device_type = "serial";
242 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
243 port-number = <1>;
244 cell-index = <5>; 210 cell-index = <5>;
245 reg = <0x2c00 0x100>; 211 reg = <0x2c00 0x100>;
246 interrupts = <0x2 0x4 0x0>; 212 interrupts = <2 4 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 }; 213 };
249 214
250 ethernet@3000 { 215 ethernet@3000 {
251 device_type = "network";
252 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
253 reg = <0x3000 0x400>; 217 reg = <0x3000 0x400>;
254 local-mac-address = [00 00 00 00 00 00]; 218 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <0x2 0x5 0x0>; 219 interrupts = <2 5 0>;
256 interrupt-parent = <&mpc5200_pic>;
257 phy-handle = <&phy0>; 220 phy-handle = <&phy0>;
258 }; 221 };
259 222
260 mdio@3000 { 223 mdio@3000 {
261 #address-cells = <1>; 224 #address-cells = <1>;
262 #size-cells = <0>; 225 #size-cells = <0>;
263 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
264 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
265 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
266 interrupt-parent = <&mpc5200_pic>; 229
267 230 phy0: ethernet-phy@0 {
268 phy0:ethernet-phy@0 { 231 reg = <0>;
269 device_type = "ethernet-phy";
270 reg = <0x0>;
271 }; 232 };
272 }; 233 };
273 234
274 ata@3a00 { 235 ata@3a00 {
275 device_type = "ata";
276 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
277 reg = <0x3a00 0x100>; 237 reg = <0x3a00 0x100>;
278 interrupts = <0x2 0x7 0x0>; 238 interrupts = <2 7 0>;
279 interrupt-parent = <&mpc5200_pic>;
280 }; 239 };
281 240
282 i2c@3d00 { 241 i2c@3d00 {
283 #address-cells = <1>; 242 #address-cells = <1>;
284 #size-cells = <0>; 243 #size-cells = <0>;
285 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <0>;
287 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
288 interrupts = <0x2 0xf 0x0>; 246 interrupts = <2 15 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking; 247 fsl5200-clocking;
291 }; 248 };
292 249
@@ -294,10 +251,8 @@
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <0>; 252 #size-cells = <0>;
296 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
297 cell-index = <1>;
298 reg = <0x3d40 0x40>; 254 reg = <0x3d40 0x40>;
299 interrupts = <0x2 0x10 0x0>; 255 interrupts = <2 16 0>;
300 interrupt-parent = <&mpc5200_pic>;
301 fsl5200-clocking; 256 fsl5200-clocking;
302 rtc@51 { 257 rtc@51 {
303 compatible = "nxp,pcf8563"; 258 compatible = "nxp,pcf8563";
@@ -307,7 +262,7 @@
307 }; 262 };
308 263
309 sram@8000 { 264 sram@8000 {
310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
311 reg = <0x8000 0x4000>; 266 reg = <0x8000 0x4000>;
312 }; 267 };
313 268
@@ -340,22 +295,21 @@
340 device_type = "pci"; 295 device_type = "pci";
341 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 296 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
342 reg = <0xf0000d00 0x100>; 297 reg = <0xf0000d00 0x100>;
343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 298 interrupt-map-mask = <0xf800 0 0 7>;
344 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ 299 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
345 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 300 0xc000 0 0 2 &mpc5200_pic 1 1 3
346 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 301 0xc000 0 0 3 &mpc5200_pic 1 2 3
347 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 302 0xc000 0 0 4 &mpc5200_pic 1 3 3
348 303
349 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 304 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
350 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 305 0xc800 0 0 2 &mpc5200_pic 1 2 3
351 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 306 0xc800 0 0 3 &mpc5200_pic 1 3 3
352 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 307 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
353 clock-frequency = <0>; // From boot loader 308 clock-frequency = <0>; // From boot loader
354 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; 309 interrupts = <2 8 0 2 9 0 2 10 0>;
355 interrupt-parent = <&mpc5200_pic>;
356 bus-range = <0 0>; 310 bus-range = <0 0>;
357 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 311 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
358 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 312 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
359 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 313 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
360 }; 314 };
361}; 315};
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 906302e26a62..c9590b58b7b0 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,36 +67,33 @@
66 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
73 can@900 { 73 can@900 {
74 compatible = "fsl,mpc5200-mscan"; 74 compatible = "fsl,mpc5200-mscan";
75 interrupts = <2 17 0>; 75 interrupts = <2 17 0>;
76 interrupt-parent = <&mpc5200_pic>;
77 reg = <0x900 0x80>; 76 reg = <0x900 0x80>;
78 }; 77 };
79 78
80 can@980 { 79 can@980 {
81 compatible = "fsl,mpc5200-mscan"; 80 compatible = "fsl,mpc5200-mscan";
82 interrupts = <2 18 0>; 81 interrupts = <2 18 0>;
83 interrupt-parent = <&mpc5200_pic>;
84 reg = <0x980 0x80>; 82 reg = <0x980 0x80>;
85 }; 83 };
86 84
87 gpio@b00 { 85 gpio_simple: gpio@b00 {
88 compatible = "fsl,mpc5200-gpio"; 86 compatible = "fsl,mpc5200-gpio";
89 reg = <0xb00 0x40>; 87 reg = <0xb00 0x40>;
90 interrupts = <1 7 0>; 88 interrupts = <1 7 0>;
91 interrupt-parent = <&mpc5200_pic>; 89 gpio-controller;
90 #gpio-cells = <2>;
92 }; 91 };
93 92
94 usb@1000 { 93 usb@1000 {
95 compatible = "fsl,mpc5200-ohci","ohci-be"; 94 compatible = "fsl,mpc5200-ohci","ohci-be";
96 reg = <0x1000 0xff>; 95 reg = <0x1000 0xff>;
97 interrupts = <2 6 0>; 96 interrupts = <2 6 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 97 };
100 98
101 dma-controller@1200 { 99 dma-controller@1200 {
@@ -105,7 +103,6 @@
105 3 4 0 3 5 0 3 6 0 3 7 0 103 3 4 0 3 5 0 3 6 0 3 7 0
106 3 8 0 3 9 0 3 10 0 3 11 0 104 3 8 0 3 9 0 3 10 0 3 11 0
107 3 12 0 3 13 0 3 14 0 3 15 0>; 105 3 12 0 3 13 0 3 14 0 3 15 0>;
108 interrupt-parent = <&mpc5200_pic>;
109 }; 106 };
110 107
111 xlb@1f00 { 108 xlb@1f00 {
@@ -114,39 +111,28 @@
114 }; 111 };
115 112
116 serial@2000 { // PSC1 113 serial@2000 { // PSC1
117 device_type = "serial";
118 compatible = "fsl,mpc5200-psc-uart"; 114 compatible = "fsl,mpc5200-psc-uart";
119 port-number = <0>; // Logical port assignment
120 reg = <0x2000 0x100>; 115 reg = <0x2000 0x100>;
121 interrupts = <2 1 0>; 116 interrupts = <2 1 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 117 };
124 118
125 serial@2200 { // PSC2 119 serial@2200 { // PSC2
126 device_type = "serial";
127 compatible = "fsl,mpc5200-psc-uart"; 120 compatible = "fsl,mpc5200-psc-uart";
128 port-number = <1>; // Logical port assignment
129 reg = <0x2200 0x100>; 121 reg = <0x2200 0x100>;
130 interrupts = <2 2 0>; 122 interrupts = <2 2 0>;
131 interrupt-parent = <&mpc5200_pic>;
132 }; 123 };
133 124
134 serial@2400 { // PSC3 125 serial@2400 { // PSC3
135 device_type = "serial";
136 compatible = "fsl,mpc5200-psc-uart"; 126 compatible = "fsl,mpc5200-psc-uart";
137 port-number = <2>; // Logical port assignment
138 reg = <0x2400 0x100>; 127 reg = <0x2400 0x100>;
139 interrupts = <2 3 0>; 128 interrupts = <2 3 0>;
140 interrupt-parent = <&mpc5200_pic>;
141 }; 129 };
142 130
143 ethernet@3000 { 131 ethernet@3000 {
144 device_type = "network";
145 compatible = "fsl,mpc5200-fec"; 132 compatible = "fsl,mpc5200-fec";
146 reg = <0x3000 0x400>; 133 reg = <0x3000 0x400>;
147 local-mac-address = [ 00 00 00 00 00 00 ]; 134 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <2 5 0>; 135 interrupts = <2 5 0>;
149 interrupt-parent = <&mpc5200_pic>;
150 phy-handle = <&phy0>; 136 phy-handle = <&phy0>;
151 }; 137 };
152 138
@@ -156,10 +142,8 @@
156 compatible = "fsl,mpc5200-mdio"; 142 compatible = "fsl,mpc5200-mdio";
157 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
158 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
159 interrupt-parent = <&mpc5200_pic>;
160 145
161 phy0: ethernet-phy@0 { 146 phy0: ethernet-phy@0 {
162 device_type = "ethernet-phy";
163 reg = <0>; 147 reg = <0>;
164 }; 148 };
165 }; 149 };
@@ -168,7 +152,6 @@
168 compatible = "fsl,mpc5200-ata"; 152 compatible = "fsl,mpc5200-ata";
169 reg = <0x3a00 0x100>; 153 reg = <0x3a00 0x100>;
170 interrupts = <2 7 0>; 154 interrupts = <2 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 }; 155 };
173 156
174 i2c@3d40 { 157 i2c@3d40 {
@@ -177,7 +160,6 @@
177 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>; 161 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>; 162 interrupts = <2 16 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 fsl5200-clocking; 163 fsl5200-clocking;
182 164
183 rtc@68 { 165 rtc@68 {
@@ -192,9 +174,8 @@
192 }; 174 };
193 }; 175 };
194 176
195 lpb { 177 localbus {
196 model = "fsl,lpb"; 178 compatible = "fsl,mpc5200-lpb","simple-bus";
197 compatible = "fsl,lpb";
198 #address-cells = <2>; 179 #address-cells = <2>;
199 #size-cells = <1>; 180 #size-cells = <1>;
200 ranges = <0 0 0xfc000000 0x02000000>; 181 ranges = <0 0 0xfc000000 0x02000000>;
@@ -223,7 +204,6 @@
223 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 204 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
224 clock-frequency = <0>; // From boot loader 205 clock-frequency = <0>; // From boot loader
225 interrupts = <2 8 0 2 9 0 2 10 0>; 206 interrupts = <2 8 0 2 9 0 2 10 0>;
226 interrupt-parent = <&mpc5200_pic>;
227 bus-range = <0 0>; 207 bus-range = <0 0>;
228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 208 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
229 0x02000000 0 0x90000000 0x90000000 0 0x10000000 209 0x02000000 0 0x90000000 0x90000000 0 0x10000000
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 696a5ee4962d..0465e5b36e6a 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -21,7 +21,12 @@ config PPC_MPC5200_SIMPLE
21 and if there is a PCI bus node defined in the device tree. 21 and if there is a PCI bus node defined in the device tree.
22 22
23 Boards that are compatible with this generic platform support 23 Boards that are compatible with this generic platform support
24 are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200'. 24 are:
25 intercontrol,digsy-mtc
26 phytec,pcm030
27 promess,motionpro
28 schindler,cm5200
29 tqc,tqm5200
25 30
26config PPC_EFIKA 31config PPC_EFIKA
27 bool "bPlan Efika 5k2. MPC5200B based computer" 32 bool "bPlan Efika 5k2. MPC5200B based computer"
@@ -35,6 +40,11 @@ config PPC_LITE5200
35 depends on PPC_MPC52xx 40 depends on PPC_MPC52xx
36 select DEFAULT_UIMAGE 41 select DEFAULT_UIMAGE
37 42
43config PPC_MEDIA5200
44 bool "Freescale Media5200 Eval Board"
45 depends on PPC_MPC52xx
46 select DEFAULT_UIMAGE
47
38config PPC_MPC5200_BUGFIX 48config PPC_MPC5200_BUGFIX
39 bool "MPC5200 (L25R) bugfix support" 49 bool "MPC5200 (L25R) bugfix support"
40 depends on PPC_MPC52xx 50 depends on PPC_MPC52xx
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index b8a52062738a..bfd4f52cf3dd 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -1,12 +1,13 @@
1# 1#
2# Makefile for 52xx based boards 2# Makefile for 52xx based boards
3# 3#
4obj-y += mpc52xx_pic.o mpc52xx_common.o 4obj-y += mpc52xx_pic.o mpc52xx_common.o mpc52xx_gpt.o
5obj-$(CONFIG_PCI) += mpc52xx_pci.o 5obj-$(CONFIG_PCI) += mpc52xx_pci.o
6 6
7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o 7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
8obj-$(CONFIG_PPC_EFIKA) += efika.o 8obj-$(CONFIG_PPC_EFIKA) += efika.o
9obj-$(CONFIG_PPC_LITE5200) += lite5200.o 9obj-$(CONFIG_PPC_LITE5200) += lite5200.o
10obj-$(CONFIG_PPC_MEDIA5200) += media5200.o
10 11
11obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o 12obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
12ifeq ($(CONFIG_PPC_LITE5200),y) 13ifeq ($(CONFIG_PPC_LITE5200),y)
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
new file mode 100644
index 000000000000..68e4f1696d14
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -0,0 +1,273 @@
1/*
2 * Support for 'media5200-platform' compatible boards.
3 *
4 * Copyright (C) 2008 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Description:
12 * This code implements support for the Freescape Media5200 platform
13 * (built around the MPC5200 SoC).
14 *
15 * Notable characteristic of the Media5200 is the presence of an FPGA
16 * that has all external IRQ lines routed through it. This file implements
17 * a cascaded interrupt controller driver which attaches itself to the
18 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
19 * is initialized.
20 *
21 */
22
23#undef DEBUG
24
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <asm/time.h>
29#include <asm/prom.h>
30#include <asm/machdep.h>
31#include <asm/mpc52xx.h>
32
33static struct of_device_id mpc5200_gpio_ids[] __initdata = {
34 { .compatible = "fsl,mpc5200-gpio", },
35 { .compatible = "mpc5200-gpio", },
36 {}
37};
38
39/* FPGA register set */
40#define MEDIA5200_IRQ_ENABLE (0x40c)
41#define MEDIA5200_IRQ_STATUS (0x410)
42#define MEDIA5200_NUM_IRQS (6)
43#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
44
45struct media5200_irq {
46 void __iomem *regs;
47 spinlock_t lock;
48 struct irq_host *irqhost;
49};
50struct media5200_irq media5200_irq;
51
52static void media5200_irq_unmask(unsigned int virq)
53{
54 unsigned long flags;
55 u32 val;
56
57 spin_lock_irqsave(&media5200_irq.lock, flags);
58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
59 val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
60 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
61 spin_unlock_irqrestore(&media5200_irq.lock, flags);
62}
63
64static void media5200_irq_mask(unsigned int virq)
65{
66 unsigned long flags;
67 u32 val;
68
69 spin_lock_irqsave(&media5200_irq.lock, flags);
70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
71 val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
72 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
73 spin_unlock_irqrestore(&media5200_irq.lock, flags);
74}
75
76static struct irq_chip media5200_irq_chip = {
77 .typename = "Media5200 FPGA",
78 .unmask = media5200_irq_unmask,
79 .mask = media5200_irq_mask,
80 .mask_ack = media5200_irq_mask,
81};
82
83void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
84{
85 int sub_virq, val;
86 u32 status, enable;
87
88 /* Mask off the cascaded IRQ */
89 spin_lock(&desc->lock);
90 desc->chip->mask(virq);
91 spin_unlock(&desc->lock);
92
93 /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
94 * are pending. 'ffs()' is 1 based */
95 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
96 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
97 val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
98 if (val) {
99 sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
100 /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
101 * __func__, virq, status, enable, val - 1, sub_virq);
102 */
103 generic_handle_irq(sub_virq);
104 }
105
106 /* Processing done; can reenable the cascade now */
107 spin_lock(&desc->lock);
108 desc->chip->ack(virq);
109 if (!(desc->status & IRQ_DISABLED))
110 desc->chip->unmask(virq);
111 spin_unlock(&desc->lock);
112}
113
114static int media5200_irq_map(struct irq_host *h, unsigned int virq,
115 irq_hw_number_t hw)
116{
117 struct irq_desc *desc = get_irq_desc(virq);
118
119 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
120 set_irq_chip_data(virq, &media5200_irq);
121 set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
122 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
123 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
124 desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
125
126 return 0;
127}
128
129static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
130 u32 *intspec, unsigned int intsize,
131 irq_hw_number_t *out_hwirq,
132 unsigned int *out_flags)
133{
134 if (intsize != 2)
135 return -1;
136
137 pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
138 *out_hwirq = intspec[1];
139 *out_flags = IRQ_TYPE_NONE;
140 return 0;
141}
142
143static struct irq_host_ops media5200_irq_ops = {
144 .map = media5200_irq_map,
145 .xlate = media5200_irq_xlate,
146};
147
148/*
149 * Setup Media5200 IRQ mapping
150 */
151static void __init media5200_init_irq(void)
152{
153 struct device_node *fpga_np;
154 int cascade_virq;
155
156 /* First setup the regular MPC5200 interrupt controller */
157 mpc52xx_init_irq();
158
159 /* Now find the FPGA IRQ */
160 fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
161 if (!fpga_np)
162 goto out;
163 pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
164
165 media5200_irq.regs = of_iomap(fpga_np, 0);
166 if (!media5200_irq.regs)
167 goto out;
168 pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
169
170 cascade_virq = irq_of_parse_and_map(fpga_np, 0);
171 if (!cascade_virq)
172 goto out;
173 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
174
175 /* Disable all FPGA IRQs */
176 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
177
178 spin_lock_init(&media5200_irq.lock);
179
180 media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
181 MEDIA5200_NUM_IRQS,
182 &media5200_irq_ops, -1);
183 if (!media5200_irq.irqhost)
184 goto out;
185 pr_debug("%s: allocated irqhost\n", __func__);
186
187 media5200_irq.irqhost->host_data = &media5200_irq;
188
189 set_irq_data(cascade_virq, &media5200_irq);
190 set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
191
192 return;
193
194 out:
195 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
196}
197
198/*
199 * Setup the architecture
200 */
201static void __init media5200_setup_arch(void)
202{
203
204 struct device_node *np;
205 struct mpc52xx_gpio __iomem *gpio;
206 u32 port_config;
207
208 if (ppc_md.progress)
209 ppc_md.progress("media5200_setup_arch()", 0);
210
211 /* Map important registers from the internal memory map */
212 mpc52xx_map_common_devices();
213
214 /* Some mpc5200 & mpc5200b related configuration */
215 mpc5200_setup_xlb_arbiter();
216
217 mpc52xx_setup_pci();
218
219 np = of_find_matching_node(NULL, mpc5200_gpio_ids);
220 gpio = of_iomap(np, 0);
221 of_node_put(np);
222 if (!gpio) {
223 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
224 __func__);
225 return;
226 }
227
228 /* Set port config */
229 port_config = in_be32(&gpio->port_config);
230
231 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
232 port_config |= 0x01000000;
233
234 out_be32(&gpio->port_config, port_config);
235
236 /* Unmap zone */
237 iounmap(gpio);
238
239}
240
241/* list of the supported boards */
242static char *board[] __initdata = {
243 "fsl,media5200",
244 NULL
245};
246
247/*
248 * Called very early, MMU is off, device-tree isn't unflattened
249 */
250static int __init media5200_probe(void)
251{
252 unsigned long node = of_get_flat_dt_root();
253 int i = 0;
254
255 while (board[i]) {
256 if (of_flat_dt_is_compatible(node, board[i]))
257 break;
258 i++;
259 }
260
261 return (board[i] != NULL);
262}
263
264define_machine(media5200_platform) {
265 .name = "media5200-platform",
266 .probe = media5200_probe,
267 .setup_arch = media5200_setup_arch,
268 .init = mpc52xx_declare_of_platform_devices,
269 .init_IRQ = media5200_init_irq,
270 .get_irq = mpc52xx_get_irq,
271 .restart = mpc52xx_restart,
272 .calibrate_decr = generic_calibrate_decr,
273};
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index a3bda0b9f1ff..d5e1471e51f7 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void)
50 50
51/* list of the supported boards */ 51/* list of the supported boards */
52static char *board[] __initdata = { 52static char *board[] __initdata = {
53 "intercontrol,digsy-mtc",
53 "promess,motionpro", 54 "promess,motionpro",
54 "phytec,pcm030", 55 "phytec,pcm030",
55 "schindler,cm5200", 56 "schindler,cm5200",
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
index 07f89ae46d04..2b8d8ef32e4e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
@@ -354,88 +354,6 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = {
354 .remove = mpc52xx_gpiochip_remove, 354 .remove = mpc52xx_gpiochip_remove,
355}; 355};
356 356
357/*
358 * GPIO LIB API implementation for gpt GPIOs.
359 *
360 * Each gpt only has a single GPIO.
361 */
362static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
363{
364 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
365 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
366
367 return (in_be32(&regs->status) & (1 << (31 - 23))) ? 1 : 0;
368}
369
370static void
371mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
372{
373 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
374 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
375
376 if (val)
377 out_be32(&regs->mode, 0x34);
378 else
379 out_be32(&regs->mode, 0x24);
380
381 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
382}
383
384static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
385{
386 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
387 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
388
389 out_be32(&regs->mode, 0x04);
390
391 return 0;
392}
393
394static int
395mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
396{
397 mpc52xx_gpt_gpio_set(gc, gpio, val);
398 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
399
400 return 0;
401}
402
403static int __devinit mpc52xx_gpt_gpiochip_probe(struct of_device *ofdev,
404 const struct of_device_id *match)
405{
406 struct of_mm_gpio_chip *mmchip;
407 struct of_gpio_chip *chip;
408
409 mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL);
410 if (!mmchip)
411 return -ENOMEM;
412
413 chip = &mmchip->of_gc;
414
415 chip->gpio_cells = 2;
416 chip->gc.ngpio = 1;
417 chip->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
418 chip->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
419 chip->gc.get = mpc52xx_gpt_gpio_get;
420 chip->gc.set = mpc52xx_gpt_gpio_set;
421
422 return of_mm_gpiochip_add(ofdev->node, mmchip);
423}
424
425static const struct of_device_id mpc52xx_gpt_gpiochip_match[] = {
426 {
427 .compatible = "fsl,mpc5200-gpt-gpio",
428 },
429 {}
430};
431
432static struct of_platform_driver mpc52xx_gpt_gpiochip_driver = {
433 .name = "gpio_gpt",
434 .match_table = mpc52xx_gpt_gpiochip_match,
435 .probe = mpc52xx_gpt_gpiochip_probe,
436 .remove = mpc52xx_gpiochip_remove,
437};
438
439static int __init mpc52xx_gpio_init(void) 357static int __init mpc52xx_gpio_init(void)
440{ 358{
441 if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver)) 359 if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver))
@@ -444,9 +362,6 @@ static int __init mpc52xx_gpio_init(void)
444 if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver)) 362 if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver))
445 printk(KERN_ERR "Unable to register simple GPIO driver\n"); 363 printk(KERN_ERR "Unable to register simple GPIO driver\n");
446 364
447 if (of_register_platform_driver(&mpc52xx_gpt_gpiochip_driver))
448 printk(KERN_ERR "Unable to register gpt GPIO driver\n");
449
450 return 0; 365 return 0;
451} 366}
452 367
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
new file mode 100644
index 000000000000..cb038dc67a85
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -0,0 +1,435 @@
1/*
2 * MPC5200 General Purpose Timer device driver
3 *
4 * Copyright (c) 2009 Secret Lab Technologies Ltd.
5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This file is a driver for the the General Purpose Timer (gpt) devices
13 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
14 * for GPIO or can be used to raise interrupts. The timer function can
15 * be used independently from the IO pin, or it can be used to control
16 * output signals or measure input signals.
17 *
18 * This driver supports the GPIO and IRQ controller functions of the GPT
19 * device. Timer functions are not yet supported, nor is the watchdog
20 * timer.
21 *
22 * To use the GPIO function, the following two properties must be added
23 * to the device tree node for the gpt device (typically in the .dts file
24 * for the board):
25 * gpio-controller;
26 * #gpio-cells = < 2 >;
27 * This driver will register the GPIO pin if it finds the gpio-controller
28 * property in the device tree.
29 *
30 * To use the IRQ controller function, the following two properties must
31 * be added to the device tree node for the gpt device:
32 * interrupt-controller;
33 * #interrupt-cells = < 1 >;
34 * The IRQ controller binding only uses one cell to specify the interrupt,
35 * and the IRQ flags are encoded in the cell. A cell is not used to encode
36 * the IRQ number because the GPT only has a single IRQ source. For flags,
37 * a value of '1' means rising edge sensitive and '2' means falling edge.
38 *
39 * The GPIO and the IRQ controller functions can be used at the same time,
40 * but in this use case the IO line will only work as an input. Trying to
41 * use it as a GPIO output will not work.
42 *
43 * When using the GPIO line as an output, it can either be driven as normal
44 * IO, or it can be an Open Collector (OC) output. At the moment it is the
45 * responsibility of either the bootloader or the platform setup code to set
46 * the output mode. This driver does not change the output mode setting.
47 */
48
49#include <linux/irq.h>
50#include <linux/interrupt.h>
51#include <linux/io.h>
52#include <linux/of.h>
53#include <linux/of_platform.h>
54#include <linux/of_gpio.h>
55#include <linux/kernel.h>
56#include <asm/mpc52xx.h>
57
58MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
59MODULE_AUTHOR("Sascha Hauer, Grant Likely");
60MODULE_LICENSE("GPL");
61
62/**
63 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
64 * @dev: pointer to device structure
65 * @regs: virtual address of GPT registers
66 * @lock: spinlock to coordinate between different functions.
67 * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
68 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
69 */
70struct mpc52xx_gpt_priv {
71 struct device *dev;
72 struct mpc52xx_gpt __iomem *regs;
73 spinlock_t lock;
74 struct irq_host *irqhost;
75
76#if defined(CONFIG_GPIOLIB)
77 struct of_gpio_chip of_gc;
78#endif
79};
80
81#define MPC52xx_GPT_MODE_MS_MASK (0x07)
82#define MPC52xx_GPT_MODE_MS_IC (0x01)
83#define MPC52xx_GPT_MODE_MS_OC (0x02)
84#define MPC52xx_GPT_MODE_MS_PWM (0x03)
85#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
86
87#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
88#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
89#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
90
91#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
92
93#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
94#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
95#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
96#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
97
98#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
99
100/* ---------------------------------------------------------------------
101 * Cascaded interrupt controller hooks
102 */
103
104static void mpc52xx_gpt_irq_unmask(unsigned int virq)
105{
106 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
107 unsigned long flags;
108
109 spin_lock_irqsave(&gpt->lock, flags);
110 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
111 spin_unlock_irqrestore(&gpt->lock, flags);
112}
113
114static void mpc52xx_gpt_irq_mask(unsigned int virq)
115{
116 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
117 unsigned long flags;
118
119 spin_lock_irqsave(&gpt->lock, flags);
120 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
121 spin_unlock_irqrestore(&gpt->lock, flags);
122}
123
124static void mpc52xx_gpt_irq_ack(unsigned int virq)
125{
126 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
127
128 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
129}
130
131static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
132{
133 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
134 unsigned long flags;
135 u32 reg;
136
137 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type);
138
139 spin_lock_irqsave(&gpt->lock, flags);
140 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
141 if (flow_type & IRQF_TRIGGER_RISING)
142 reg |= MPC52xx_GPT_MODE_ICT_RISING;
143 if (flow_type & IRQF_TRIGGER_FALLING)
144 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
145 out_be32(&gpt->regs->mode, reg);
146 spin_unlock_irqrestore(&gpt->lock, flags);
147
148 return 0;
149}
150
151static struct irq_chip mpc52xx_gpt_irq_chip = {
152 .typename = "MPC52xx GPT",
153 .unmask = mpc52xx_gpt_irq_unmask,
154 .mask = mpc52xx_gpt_irq_mask,
155 .ack = mpc52xx_gpt_irq_ack,
156 .set_type = mpc52xx_gpt_irq_set_type,
157};
158
159void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
160{
161 struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
162 int sub_virq;
163 u32 status;
164
165 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
166 if (status) {
167 sub_virq = irq_linear_revmap(gpt->irqhost, 0);
168 generic_handle_irq(sub_virq);
169 }
170}
171
172static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
173 irq_hw_number_t hw)
174{
175 struct mpc52xx_gpt_priv *gpt = h->host_data;
176
177 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
178 set_irq_chip_data(virq, gpt);
179 set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
180
181 return 0;
182}
183
184static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
185 u32 *intspec, unsigned int intsize,
186 irq_hw_number_t *out_hwirq,
187 unsigned int *out_flags)
188{
189 struct mpc52xx_gpt_priv *gpt = h->host_data;
190
191 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
192
193 if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) {
194 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
195 return -EINVAL;
196 }
197
198 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
199 *out_flags = intspec[0];
200
201 return 0;
202}
203
204static struct irq_host_ops mpc52xx_gpt_irq_ops = {
205 .map = mpc52xx_gpt_irq_map,
206 .xlate = mpc52xx_gpt_irq_xlate,
207};
208
209static void
210mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
211{
212 int cascade_virq;
213 unsigned long flags;
214
215 /* Only setup cascaded IRQ if device tree claims the GPT is
216 * an interrupt controller */
217 if (!of_find_property(node, "interrupt-controller", NULL))
218 return;
219
220 cascade_virq = irq_of_parse_and_map(node, 0);
221
222 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
223 &mpc52xx_gpt_irq_ops, -1);
224 if (!gpt->irqhost) {
225 dev_err(gpt->dev, "irq_alloc_host() failed\n");
226 return;
227 }
228
229 gpt->irqhost->host_data = gpt;
230
231 set_irq_data(cascade_virq, gpt);
232 set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
233
234 /* Set to Input Capture mode */
235 spin_lock_irqsave(&gpt->lock, flags);
236 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
237 MPC52xx_GPT_MODE_MS_IC);
238 spin_unlock_irqrestore(&gpt->lock, flags);
239
240 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
241}
242
243
244/* ---------------------------------------------------------------------
245 * GPIOLIB hooks
246 */
247#if defined(CONFIG_GPIOLIB)
248static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
249{
250 return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc);
251}
252
253static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
254{
255 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
256
257 return (in_be32(&gpt->regs->status) >> 8) & 1;
258}
259
260static void
261mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
262{
263 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
264 unsigned long flags;
265 u32 r;
266
267 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
268 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
269
270 spin_lock_irqsave(&gpt->lock, flags);
271 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
272 spin_unlock_irqrestore(&gpt->lock, flags);
273}
274
275static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
276{
277 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
278 unsigned long flags;
279
280 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
281
282 spin_lock_irqsave(&gpt->lock, flags);
283 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
284 spin_unlock_irqrestore(&gpt->lock, flags);
285
286 return 0;
287}
288
289static int
290mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
291{
292 mpc52xx_gpt_gpio_set(gc, gpio, val);
293 return 0;
294}
295
296static void
297mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
298{
299 int rc;
300
301 /* Only setup GPIO if the device tree claims the GPT is
302 * a GPIO controller */
303 if (!of_find_property(node, "gpio-controller", NULL))
304 return;
305
306 gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL);
307 if (!gpt->of_gc.gc.label) {
308 dev_err(gpt->dev, "out of memory\n");
309 return;
310 }
311
312 gpt->of_gc.gpio_cells = 2;
313 gpt->of_gc.gc.ngpio = 1;
314 gpt->of_gc.gc.direction_input = mpc52xx_gpt_gpio_dir_in;
315 gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out;
316 gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get;
317 gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set;
318 gpt->of_gc.gc.base = -1;
319 gpt->of_gc.xlate = of_gpio_simple_xlate;
320 node->data = &gpt->of_gc;
321 of_node_get(node);
322
323 /* Setup external pin in GPIO mode */
324 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
325 MPC52xx_GPT_MODE_MS_GPIO);
326
327 rc = gpiochip_add(&gpt->of_gc.gc);
328 if (rc)
329 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
330
331 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
332}
333#else /* defined(CONFIG_GPIOLIB) */
334static void
335mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
336#endif /* defined(CONFIG_GPIOLIB) */
337
338/***********************************************************************
339 * SYSFS attributes
340 */
341#if defined(CONFIG_SYSFS)
342static ssize_t mpc52xx_gpt_show_regs(struct device *dev,
343 struct device_attribute *attr, char *buf)
344{
345 struct mpc52xx_gpt_priv *gpt = dev_get_drvdata(dev);
346 int i, len = 0;
347 u32 __iomem *regs = (void __iomem *) gpt->regs;
348
349 for (i = 0; i < 4; i++)
350 len += sprintf(buf + len, "%.8x ", in_be32(regs + i));
351 len += sprintf(buf + len, "\n");
352
353 return len;
354}
355
356static struct device_attribute mpc52xx_gpt_attrib[] = {
357 __ATTR(regs, S_IRUGO | S_IWUSR, mpc52xx_gpt_show_regs, NULL),
358};
359
360static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *gpt)
361{
362 int i, err = 0;
363
364 for (i = 0; i < ARRAY_SIZE(mpc52xx_gpt_attrib); i++) {
365 err = device_create_file(gpt->dev, &mpc52xx_gpt_attrib[i]);
366 if (err)
367 dev_err(gpt->dev, "error creating attribute %i\n", i);
368 }
369
370}
371
372#else /* defined(CONFIG_SYSFS) */
373static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *) { return 0; }
374#endif /* defined(CONFIG_SYSFS) */
375
376/* ---------------------------------------------------------------------
377 * of_platform bus binding code
378 */
379static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
380 const struct of_device_id *match)
381{
382 struct mpc52xx_gpt_priv *gpt;
383
384 gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
385 if (!gpt)
386 return -ENOMEM;
387
388 spin_lock_init(&gpt->lock);
389 gpt->dev = &ofdev->dev;
390 gpt->regs = of_iomap(ofdev->node, 0);
391 if (!gpt->regs) {
392 kfree(gpt);
393 return -ENOMEM;
394 }
395
396 dev_set_drvdata(&ofdev->dev, gpt);
397
398 mpc52xx_gpt_create_attribs(gpt);
399 mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
400 mpc52xx_gpt_irq_setup(gpt, ofdev->node);
401
402 return 0;
403}
404
405static int mpc52xx_gpt_remove(struct of_device *ofdev)
406{
407 return -EBUSY;
408}
409
410static const struct of_device_id mpc52xx_gpt_match[] = {
411 { .compatible = "fsl,mpc5200-gpt", },
412
413 /* Depreciated compatible values; don't use for new dts files */
414 { .compatible = "fsl,mpc5200-gpt-gpio", },
415 { .compatible = "mpc5200-gpt", },
416 {}
417};
418
419static struct of_platform_driver mpc52xx_gpt_driver = {
420 .name = "mpc52xx-gpt",
421 .match_table = mpc52xx_gpt_match,
422 .probe = mpc52xx_gpt_probe,
423 .remove = mpc52xx_gpt_remove,
424};
425
426static int __init mpc52xx_gpt_init(void)
427{
428 if (of_register_platform_driver(&mpc52xx_gpt_driver))
429 pr_err("error registering MPC52xx GPT driver\n");
430
431 return 0;
432}
433
434/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
435subsys_initcall(mpc52xx_gpt_init);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 0a093f03c758..480f806fd0a9 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -163,8 +163,6 @@ static void mpc52xx_extirq_mask(unsigned int virq)
163 irq = irq_map[virq].hwirq; 163 irq = irq_map[virq].hwirq;
164 l2irq = irq & MPC52xx_IRQ_L2_MASK; 164 l2irq = irq & MPC52xx_IRQ_L2_MASK;
165 165
166 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
167
168 io_be_clrbit(&intr->ctrl, 11 - l2irq); 166 io_be_clrbit(&intr->ctrl, 11 - l2irq);
169} 167}
170 168
@@ -176,8 +174,6 @@ static void mpc52xx_extirq_unmask(unsigned int virq)
176 irq = irq_map[virq].hwirq; 174 irq = irq_map[virq].hwirq;
177 l2irq = irq & MPC52xx_IRQ_L2_MASK; 175 l2irq = irq & MPC52xx_IRQ_L2_MASK;
178 176
179 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
180
181 io_be_setbit(&intr->ctrl, 11 - l2irq); 177 io_be_setbit(&intr->ctrl, 11 - l2irq);
182} 178}
183 179
@@ -189,17 +185,15 @@ static void mpc52xx_extirq_ack(unsigned int virq)
189 irq = irq_map[virq].hwirq; 185 irq = irq_map[virq].hwirq;
190 l2irq = irq & MPC52xx_IRQ_L2_MASK; 186 l2irq = irq & MPC52xx_IRQ_L2_MASK;
191 187
192 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
193
194 io_be_setbit(&intr->ctrl, 27-l2irq); 188 io_be_setbit(&intr->ctrl, 27-l2irq);
195} 189}
196 190
197static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) 191static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
198{ 192{
199 struct irq_desc *desc = get_irq_desc(virq);
200 u32 ctrl_reg, type; 193 u32 ctrl_reg, type;
201 int irq; 194 int irq;
202 int l2irq; 195 int l2irq;
196 void *handler = handle_level_irq;
203 197
204 irq = irq_map[virq].hwirq; 198 irq = irq_map[virq].hwirq;
205 l2irq = irq & MPC52xx_IRQ_L2_MASK; 199 l2irq = irq & MPC52xx_IRQ_L2_MASK;
@@ -207,32 +201,21 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
207 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); 201 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
208 202
209 switch (flow_type) { 203 switch (flow_type) {
210 case IRQF_TRIGGER_HIGH: 204 case IRQF_TRIGGER_HIGH: type = 0; break;
211 type = 0; 205 case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
212 break; 206 case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
213 case IRQF_TRIGGER_RISING: 207 case IRQF_TRIGGER_LOW: type = 3; break;
214 type = 1;
215 break;
216 case IRQF_TRIGGER_FALLING:
217 type = 2;
218 break;
219 case IRQF_TRIGGER_LOW:
220 type = 3;
221 break;
222 default: 208 default:
223 type = 0; 209 type = 0;
224 } 210 }
225 211
226 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
227 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
228 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
229 desc->status |= IRQ_LEVEL;
230
231 ctrl_reg = in_be32(&intr->ctrl); 212 ctrl_reg = in_be32(&intr->ctrl);
232 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); 213 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
233 ctrl_reg |= (type << (22 - (l2irq * 2))); 214 ctrl_reg |= (type << (22 - (l2irq * 2)));
234 out_be32(&intr->ctrl, ctrl_reg); 215 out_be32(&intr->ctrl, ctrl_reg);
235 216
217 __set_irq_handler_unlocked(virq, handler);
218
236 return 0; 219 return 0;
237} 220}
238 221
@@ -247,6 +230,11 @@ static struct irq_chip mpc52xx_extirq_irqchip = {
247/* 230/*
248 * Main interrupt irq_chip 231 * Main interrupt irq_chip
249 */ 232 */
233static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
234{
235 return 0; /* Do nothing so that the sense mask will get updated */
236}
237
250static void mpc52xx_main_mask(unsigned int virq) 238static void mpc52xx_main_mask(unsigned int virq)
251{ 239{
252 int irq; 240 int irq;
@@ -255,8 +243,6 @@ static void mpc52xx_main_mask(unsigned int virq)
255 irq = irq_map[virq].hwirq; 243 irq = irq_map[virq].hwirq;
256 l2irq = irq & MPC52xx_IRQ_L2_MASK; 244 l2irq = irq & MPC52xx_IRQ_L2_MASK;
257 245
258 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
259
260 io_be_setbit(&intr->main_mask, 16 - l2irq); 246 io_be_setbit(&intr->main_mask, 16 - l2irq);
261} 247}
262 248
@@ -268,8 +254,6 @@ static void mpc52xx_main_unmask(unsigned int virq)
268 irq = irq_map[virq].hwirq; 254 irq = irq_map[virq].hwirq;
269 l2irq = irq & MPC52xx_IRQ_L2_MASK; 255 l2irq = irq & MPC52xx_IRQ_L2_MASK;
270 256
271 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
272
273 io_be_clrbit(&intr->main_mask, 16 - l2irq); 257 io_be_clrbit(&intr->main_mask, 16 - l2irq);
274} 258}
275 259
@@ -278,6 +262,7 @@ static struct irq_chip mpc52xx_main_irqchip = {
278 .mask = mpc52xx_main_mask, 262 .mask = mpc52xx_main_mask,
279 .mask_ack = mpc52xx_main_mask, 263 .mask_ack = mpc52xx_main_mask,
280 .unmask = mpc52xx_main_unmask, 264 .unmask = mpc52xx_main_unmask,
265 .set_type = mpc52xx_null_set_type,
281}; 266};
282 267
283/* 268/*
@@ -291,8 +276,6 @@ static void mpc52xx_periph_mask(unsigned int virq)
291 irq = irq_map[virq].hwirq; 276 irq = irq_map[virq].hwirq;
292 l2irq = irq & MPC52xx_IRQ_L2_MASK; 277 l2irq = irq & MPC52xx_IRQ_L2_MASK;
293 278
294 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
295
296 io_be_setbit(&intr->per_mask, 31 - l2irq); 279 io_be_setbit(&intr->per_mask, 31 - l2irq);
297} 280}
298 281
@@ -304,8 +287,6 @@ static void mpc52xx_periph_unmask(unsigned int virq)
304 irq = irq_map[virq].hwirq; 287 irq = irq_map[virq].hwirq;
305 l2irq = irq & MPC52xx_IRQ_L2_MASK; 288 l2irq = irq & MPC52xx_IRQ_L2_MASK;
306 289
307 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
308
309 io_be_clrbit(&intr->per_mask, 31 - l2irq); 290 io_be_clrbit(&intr->per_mask, 31 - l2irq);
310} 291}
311 292
@@ -314,6 +295,7 @@ static struct irq_chip mpc52xx_periph_irqchip = {
314 .mask = mpc52xx_periph_mask, 295 .mask = mpc52xx_periph_mask,
315 .mask_ack = mpc52xx_periph_mask, 296 .mask_ack = mpc52xx_periph_mask,
316 .unmask = mpc52xx_periph_unmask, 297 .unmask = mpc52xx_periph_unmask,
298 .set_type = mpc52xx_null_set_type,
317}; 299};
318 300
319/* 301/*
@@ -327,8 +309,6 @@ static void mpc52xx_sdma_mask(unsigned int virq)
327 irq = irq_map[virq].hwirq; 309 irq = irq_map[virq].hwirq;
328 l2irq = irq & MPC52xx_IRQ_L2_MASK; 310 l2irq = irq & MPC52xx_IRQ_L2_MASK;
329 311
330 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
331
332 io_be_setbit(&sdma->IntMask, l2irq); 312 io_be_setbit(&sdma->IntMask, l2irq);
333} 313}
334 314
@@ -340,8 +320,6 @@ static void mpc52xx_sdma_unmask(unsigned int virq)
340 irq = irq_map[virq].hwirq; 320 irq = irq_map[virq].hwirq;
341 l2irq = irq & MPC52xx_IRQ_L2_MASK; 321 l2irq = irq & MPC52xx_IRQ_L2_MASK;
342 322
343 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
344
345 io_be_clrbit(&sdma->IntMask, l2irq); 323 io_be_clrbit(&sdma->IntMask, l2irq);
346} 324}
347 325
@@ -353,8 +331,6 @@ static void mpc52xx_sdma_ack(unsigned int virq)
353 irq = irq_map[virq].hwirq; 331 irq = irq_map[virq].hwirq;
354 l2irq = irq & MPC52xx_IRQ_L2_MASK; 332 l2irq = irq & MPC52xx_IRQ_L2_MASK;
355 333
356 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
357
358 out_be32(&sdma->IntPend, 1 << l2irq); 334 out_be32(&sdma->IntPend, 1 << l2irq);
359} 335}
360 336
@@ -363,9 +339,19 @@ static struct irq_chip mpc52xx_sdma_irqchip = {
363 .mask = mpc52xx_sdma_mask, 339 .mask = mpc52xx_sdma_mask,
364 .unmask = mpc52xx_sdma_unmask, 340 .unmask = mpc52xx_sdma_unmask,
365 .ack = mpc52xx_sdma_ack, 341 .ack = mpc52xx_sdma_ack,
342 .set_type = mpc52xx_null_set_type,
366}; 343};
367 344
368/** 345/**
346 * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
347 */
348static int mpc52xx_is_extirq(int l1, int l2)
349{
350 return ((l1 == 0) && (l2 == 0)) ||
351 ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
352}
353
354/**
369 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property 355 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
370 */ 356 */
371static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, 357static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
@@ -383,38 +369,23 @@ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
383 369
384 intrvect_l1 = (int)intspec[0]; 370 intrvect_l1 = (int)intspec[0];
385 intrvect_l2 = (int)intspec[1]; 371 intrvect_l2 = (int)intspec[1];
386 intrvect_type = (int)intspec[2]; 372 intrvect_type = (int)intspec[2] & 0x3;
387 373
388 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & 374 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
389 MPC52xx_IRQ_L1_MASK; 375 MPC52xx_IRQ_L1_MASK;
390 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK; 376 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
391 377
392 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
393 intrvect_l2);
394
395 *out_hwirq = intrvect_linux; 378 *out_hwirq = intrvect_linux;
396 *out_flags = mpc52xx_map_senses[intrvect_type]; 379 *out_flags = IRQ_TYPE_LEVEL_LOW;
380 if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
381 *out_flags = mpc52xx_map_senses[intrvect_type];
397 382
383 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
384 intrvect_l2);
398 return 0; 385 return 0;
399} 386}
400 387
401/** 388/**
402 * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge)
403 *
404 * Only external IRQs need this.
405 */
406static int mpc52xx_irqx_gettype(int irq)
407{
408 int type;
409 u32 ctrl_reg;
410
411 ctrl_reg = in_be32(&intr->ctrl);
412 type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
413
414 return mpc52xx_map_senses[type];
415}
416
417/**
418 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure 389 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
419 */ 390 */
420static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, 391static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
@@ -422,68 +393,46 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
422{ 393{
423 int l1irq; 394 int l1irq;
424 int l2irq; 395 int l2irq;
425 struct irq_chip *good_irqchip; 396 struct irq_chip *irqchip;
426 void *good_handle; 397 void *hndlr;
427 int type; 398 int type;
399 u32 reg;
428 400
429 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET; 401 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
430 l2irq = irq & MPC52xx_IRQ_L2_MASK; 402 l2irq = irq & MPC52xx_IRQ_L2_MASK;
431 403
432 /* 404 /*
433 * Most of ours IRQs will be level low 405 * External IRQs are handled differently by the hardware so they are
434 * Only external IRQs on some platform may be others 406 * handled by a dedicated irq_chip structure.
435 */ 407 */
436 type = IRQ_TYPE_LEVEL_LOW; 408 if (mpc52xx_is_extirq(l1irq, l2irq)) {
409 reg = in_be32(&intr->ctrl);
410 type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
411 if ((type == IRQ_TYPE_EDGE_FALLING) ||
412 (type == IRQ_TYPE_EDGE_RISING))
413 hndlr = handle_edge_irq;
414 else
415 hndlr = handle_level_irq;
416
417 set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
418 pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
419 __func__, l2irq, virq, (int)irq, type);
420 return 0;
421 }
437 422
423 /* It is an internal SOC irq. Choose the correct irq_chip */
438 switch (l1irq) { 424 switch (l1irq) {
439 case MPC52xx_IRQ_L1_CRIT: 425 case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
440 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq); 426 case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
441 427 case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
442 BUG_ON(l2irq != 0);
443
444 type = mpc52xx_irqx_gettype(l2irq);
445 good_irqchip = &mpc52xx_extirq_irqchip;
446 break;
447
448 case MPC52xx_IRQ_L1_MAIN:
449 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
450
451 if ((l2irq >= 1) && (l2irq <= 3)) {
452 type = mpc52xx_irqx_gettype(l2irq);
453 good_irqchip = &mpc52xx_extirq_irqchip;
454 } else {
455 good_irqchip = &mpc52xx_main_irqchip;
456 }
457 break;
458
459 case MPC52xx_IRQ_L1_PERP:
460 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
461 good_irqchip = &mpc52xx_periph_irqchip;
462 break;
463
464 case MPC52xx_IRQ_L1_SDMA:
465 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
466 good_irqchip = &mpc52xx_sdma_irqchip;
467 break;
468
469 default: 428 default:
470 pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq); 429 pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
430 __func__, virq, l1irq, l2irq);
471 return -EINVAL; 431 return -EINVAL;
472 } 432 }
473 433
474 switch (type) { 434 set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
475 case IRQ_TYPE_EDGE_FALLING: 435 pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
476 case IRQ_TYPE_EDGE_RISING:
477 good_handle = handle_edge_irq;
478 break;
479 default:
480 good_handle = handle_level_irq;
481 }
482
483 set_irq_chip_and_handler(virq, good_irqchip, good_handle);
484
485 pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
486 (int)irq, type);
487 436
488 return 0; 437 return 0;
489} 438}
@@ -522,6 +471,8 @@ void __init mpc52xx_init_irq(void)
522 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " 471 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
523 "Check node !"); 472 "Check node !");
524 473
474 pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
475
525 /* Disable all interrupt sources. */ 476 /* Disable all interrupt sources. */
526 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ 477 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
527 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ 478 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
@@ -613,8 +564,5 @@ unsigned int mpc52xx_get_irq(void)
613 } 564 }
614 } 565 }
615 566
616 pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
617 irq_linear_revmap(mpc52xx_irqhost, irq));
618
619 return irq_linear_revmap(mpc52xx_irqhost, irq); 567 return irq_linear_revmap(mpc52xx_irqhost, irq);
620} 568}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 11:32:09 -0500