powerpc: Merge i8259.c into arch/powerpc/sysdev

This changes the parameters for i8259_init so that it takes two
parameters: a physical address for generating an interrupt
acknowledge cycle, and an interrupt number offset.  i8259_init
now sets the irq_desc[] for its interrupts; all the callers
were doing this, and that code is gone now.  This also defines
a CONFIG_PPC_I8259 symbol to select i8259.o for inclusion, and
makes the platforms that need it select that symbol.

Signed-off-by: Paul Mackerras <paulus@samba.org>

5 files changed, 241 insertions, 15 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a3451d5bb788..9f279e0d84f2 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -275,11 +275,13 @@ endchoice
 config PPC_PSERIES
         depends on PPC_MULTIPLATFORM && PPC64
         bool "  IBM pSeries & new (POWER5-based) iSeries"
+        select PPC_I8259
         default y
 
 config PPC_CHRP
         bool "  Common Hardware Reference Platform (CHRP) based machines"
         depends on PPC_MULTIPLATFORM && PPC32
+        select PPC_I8259
         select PPC_INDIRECT_PCI
         default y
 
@@ -298,6 +300,7 @@ config PPC_PMAC64
 config PPC_PREP
         bool "  PowerPC Reference Platform (PReP) based machines"
         depends on PPC_MULTIPLATFORM && PPC32
+        select PPC_I8259
         select PPC_INDIRECT_PCI
         default y
 
@@ -628,6 +631,7 @@ menu "Bus options"
 config ISA
         bool "Support for ISA-bus hardware"
         depends on PPC_PREP || PPC_CHRP
+        select PPC_I8259
         help
           Find out whether you have ISA slots on your motherboard.  ISA is the
           name of a bus system, i.e. the way the CPU talks to the other stuff
@@ -640,6 +644,11 @@ config GENERIC_ISA_DMA
         depends on PPC64 || POWER4 || 6xx && !CPM2
         default y
 
+config PPC_I8259
+        bool
+        default y if 85xx
+        default n
+
 config PPC_INDIRECT_PCI
         bool
         depends on PCI
@@ -679,6 +688,7 @@ config MPC83xx_PCI2
 config PCI_QSPAN
         bool "QSpan PCI"
         depends on !4xx && !CPM2 && 8xx
+        select PPC_I8259
         help
           Say Y here if you have a system based on a Motorola 8xx-series
           embedded processor with a QSPAN PCI interface, otherwise say N.
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 784b41e19465..81250090f98d 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -48,6 +48,7 @@ config EV64260
 
 config LOPEC
         bool "Motorola-LoPEC"
+        select PPC_I8259
 
 config MVME5100
         bool "Motorola-MVME5100"
@@ -55,6 +56,7 @@ config MVME5100
 
 config PPLUS
         bool "Motorola-PowerPlus"
+        select PPC_I8259
         select PPC_INDIRECT_PCI
 
 config PRPMC750
@@ -67,12 +69,14 @@ config PRPMC800
 
 config SANDPOINT
         bool "Motorola-Sandpoint"
+        select PPC_I8259
         help
           Select SANDPOINT if configuring for a Motorola Sandpoint X3
           (any flavor).
 
 config RADSTONE_PPC7D
         bool "Radstone Technology PPC7D board"
+        select PPC_I8259
 
 config PAL4
         bool "SBS-Palomar4"
@@ -307,6 +311,7 @@ config HARRIER_STORE_GATHERING
 config MVME5100_IPMC761_PRESENT
         bool "MVME5100 configured with an IPMC761"
         depends on MVME5100
+        select PPC_I8259
 
 config SPRUCE_BAUD_33M
         bool "Spruce baud clock support"
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 92d18003f152..0fa5beae6d1b 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -87,7 +87,6 @@ extern int pSeries_machine_check_exception(struct pt_regs *regs);
 static void pseries_shared_idle(void);
 static void pseries_dedicated_idle(void);
 
-static volatile void __iomem * chrp_int_ack_special;
 struct mpic *pSeries_mpic;
 
 void pSeries_show_cpuinfo(struct seq_file *m)
@@ -119,19 +118,11 @@ static void __init fwnmi_init(void)
                 fwnmi_active = 1;
 }
 
-static int pSeries_irq_cascade(struct pt_regs *regs, void *data)
-{
-        if (chrp_int_ack_special)
-                return readb(chrp_int_ack_special);
-        else
-                return i8259_irq(regs);
-}
-
 static void __init pSeries_init_mpic(void)
 {
         unsigned int *addrp;
         struct device_node *np;
-        int i;
+        unsigned long intack = 0;
 
         /* All ISUs are setup, complete initialization */
         mpic_init(pSeries_mpic);
@@ -142,16 +133,14 @@ static void __init pSeries_init_mpic(void)
                  get_property(np, "8259-interrupt-acknowledge", NULL)))
                 printk(KERN_ERR "Cannot find pci to get ack address\n");
         else
-                chrp_int_ack_special = ioremap(addrp[prom_n_addr_cells(np)-1], 1);
+                intack = addrp[prom_n_addr_cells(np)-1];
         of_node_put(np);
 
         /* Setup the legacy interrupts & controller */
-        for (i = 0; i < NUM_ISA_INTERRUPTS; i++)
-                irq_desc[i].handler = &i8259_pic;
-        i8259_init(0);
+        i8259_init(intack, 0);
 
         /* Hook cascade to mpic */
-        mpic_setup_cascade(NUM_ISA_INTERRUPTS, pSeries_irq_cascade, NULL);
+        mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
 }
 
 static void __init pSeries_setup_mpic(void)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index e66fef652fac..f3c9e61c3910 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_MPIC)              += mpic.o
 obj-$(CONFIG_PPC_INDIRECT_PCI)  += indirect_pci.o
+obj-$(CONFIG_PPC_I8259)         += i8259.o
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
new file mode 100644
index 000000000000..90bce6e0c191
--- /dev/null
+++ b/arch/powerpc/sysdev/i8259.c
@@ -0,0 +1,221 @@
+/*
+ * i8259 interrupt controller driver.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <asm/io.h>
+#include <asm/i8259.h>
+
+static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
+
+static unsigned char cached_8259[2] = { 0xff, 0xff };
+#define cached_A1 (cached_8259[0])
+#define cached_21 (cached_8259[1])
+
+static DEFINE_SPINLOCK(i8259_lock);
+
+static int i8259_pic_irq_offset;
+
+/*
+ * Acknowledge the IRQ using either the PCI host bridge's interrupt
+ * acknowledge feature or poll.  How i8259_init() is called determines
+ * which is called.  It should be noted that polling is broken on some
+ * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
+ */
+int i8259_irq(struct pt_regs *regs)
+{
+        int irq;
+
+        spin_lock(&i8259_lock);
+
+        /* Either int-ack or poll for the IRQ */
+        if (pci_intack)
+                irq = readb(pci_intack);
+        else {
+                /* Perform an interrupt acknowledge cycle on controller 1. */
+                outb(0x0C, 0x20);               /* prepare for poll */
+                irq = inb(0x20) & 7;
+                if (irq == 2 ) {
+                        /*
+                         * Interrupt is cascaded so perform interrupt
+                         * acknowledge on controller 2.
+                         */
+                        outb(0x0C, 0xA0);       /* prepare for poll */
+                        irq = (inb(0xA0) & 7) + 8;
+                }
+        }
+
+        if (irq == 7) {
+                /*
+                 * This may be a spurious interrupt.
+                 *
+                 * Read the interrupt status register (ISR). If the most
+                 * significant bit is not set then there is no valid
+                 * interrupt.
+                 */
+                if (!pci_intack)
+                        outb(0x0B, 0x20);       /* ISR register */
+                if(~inb(0x20) & 0x80)
+                        irq = -1;
+        }
+
+        spin_unlock(&i8259_lock);
+        return irq + i8259_pic_irq_offset;
+}
+
+int i8259_irq_cascade(struct pt_regs *regs, void *unused)
+{
+        return i8259_irq(regs);
+}
+
+static void i8259_mask_and_ack_irq(unsigned int irq_nr)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259_lock, flags);
+        irq_nr -= i8259_pic_irq_offset;
+        if (irq_nr > 7) {
+                cached_A1 |= 1 << (irq_nr-8);
+                inb(0xA1);      /* DUMMY */
+                outb(cached_A1, 0xA1);
+                outb(0x20, 0xA0);       /* Non-specific EOI */
+                outb(0x20, 0x20);       /* Non-specific EOI to cascade */
+        } else {
+                cached_21 |= 1 << irq_nr;
+                inb(0x21);      /* DUMMY */
+                outb(cached_21, 0x21);
+                outb(0x20, 0x20);       /* Non-specific EOI */
+        }
+        spin_unlock_irqrestore(&i8259_lock, flags);
+}
+
+static void i8259_set_irq_mask(int irq_nr)
+{
+        outb(cached_A1,0xA1);
+        outb(cached_21,0x21);
+}
+
+static void i8259_mask_irq(unsigned int irq_nr)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259_lock, flags);
+        irq_nr -= i8259_pic_irq_offset;
+        if (irq_nr < 8)
+                cached_21 |= 1 << irq_nr;
+        else
+                cached_A1 |= 1 << (irq_nr-8);
+        i8259_set_irq_mask(irq_nr);
+        spin_unlock_irqrestore(&i8259_lock, flags);
+}
+
+static void i8259_unmask_irq(unsigned int irq_nr)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259_lock, flags);
+        irq_nr -= i8259_pic_irq_offset;
+        if (irq_nr < 8)
+                cached_21 &= ~(1 << irq_nr);
+        else
+                cached_A1 &= ~(1 << (irq_nr-8));
+        i8259_set_irq_mask(irq_nr);
+        spin_unlock_irqrestore(&i8259_lock, flags);
+}
+
+static void i8259_end_irq(unsigned int irq)
+{
+        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
+            && irq_desc[irq].action)
+                i8259_unmask_irq(irq);
+}
+
+struct hw_interrupt_type i8259_pic = {
+        .typename = " i8259    ",
+        .enable = i8259_unmask_irq,
+        .disable = i8259_mask_irq,
+        .ack = i8259_mask_and_ack_irq,
+        .end = i8259_end_irq,
+};
+
+static struct resource pic1_iores = {
+        .name = "8259 (master)",
+        .start = 0x20,
+        .end = 0x21,
+        .flags = IORESOURCE_BUSY,
+};
+
+static struct resource pic2_iores = {
+        .name = "8259 (slave)",
+        .start = 0xa0,
+        .end = 0xa1,
+        .flags = IORESOURCE_BUSY,
+};
+
+static struct resource pic_edgectrl_iores = {
+        .name = "8259 edge control",
+        .start = 0x4d0,
+        .end = 0x4d1,
+        .flags = IORESOURCE_BUSY,
+};
+
+static struct irqaction i8259_irqaction = {
+        .handler = no_action,
+        .flags = SA_INTERRUPT,
+        .mask = CPU_MASK_NONE,
+        .name = "82c59 secondary cascade",
+};
+
+/*
+ * i8259_init()
+ * intack_addr - PCI interrupt acknowledge (real) address which will return
+ *               the active irq from the 8259
+ */
+void __init i8259_init(unsigned long intack_addr, int offset)
+{
+        unsigned long flags;
+        int i;
+
+        spin_lock_irqsave(&i8259_lock, flags);
+        i8259_pic_irq_offset = offset;
+
+        /* init master interrupt controller */
+        outb(0x11, 0x20); /* Start init sequence */
+        outb(0x00, 0x21); /* Vector base */
+        outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
+        outb(0x01, 0x21); /* Select 8086 mode */
+
+        /* init slave interrupt controller */
+        outb(0x11, 0xA0); /* Start init sequence */
+        outb(0x08, 0xA1); /* Vector base */
+        outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
+        outb(0x01, 0xA1); /* Select 8086 mode */
+
+        /* always read ISR */
+        outb(0x0B, 0x20);
+        outb(0x0B, 0xA0);
+
+        /* Mask all interrupts */
+        outb(cached_A1, 0xA1);
+        outb(cached_21, 0x21);
+
+        spin_unlock_irqrestore(&i8259_lock, flags);
+
+        /* reserve our resources */
+        setup_irq(offset + 2, &i8259_irqaction);
+        request_resource(&ioport_resource, &pic1_iores);
+        request_resource(&ioport_resource, &pic2_iores);
+        request_resource(&ioport_resource, &pic_edgectrl_iores);
+
+        if (intack_addr != 0)
+                pci_intack = ioremap(intack_addr, 1);
+
+        for (i = 0; i < NUM_ISA_INTERRUPTS; ++i)
+                irq_desc[offset + i].handler = &i8259_pic;
+}