diff options
author | Michael Neuling <mikey@neuling.org> | 2013-05-26 14:30:56 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-05-31 18:29:23 -0400 |
commit | b75c100ef24894bd2c8b52e123bcc5f191c5d9fd (patch) | |
tree | ec15563f8fb0aeb0f8dc97066a06c9261ce0c94f /arch/powerpc | |
parent | 6ce6c629fd8254b3177650de99699682ff7f6707 (diff) |
powerpc/tm: Move TM abort cause codes to uapi
These cause codes are usable by userspace, so let's export to uapi.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Cc: <stable@vger.kernel.org> # v3.9
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 14 | ||||
-rw-r--r-- | arch/powerpc/include/asm/tm.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/uapi/asm/Kbuild | 1 | ||||
-rw-r--r-- | arch/powerpc/include/uapi/asm/tm.h | 18 |
4 files changed, 21 insertions, 14 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index d0528e0d6db8..4a9e408644fe 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -111,20 +111,6 @@ | |||
111 | #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) | 111 | #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) |
112 | #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) | 112 | #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) |
113 | 113 | ||
114 | /* Reason codes describing kernel causes for transaction aborts. By | ||
115 | convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if | ||
116 | the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor. | ||
117 | */ | ||
118 | #define TM_CAUSE_PERSISTENT 0x01 | ||
119 | #define TM_CAUSE_RESCHED 0xde | ||
120 | #define TM_CAUSE_TLBI 0xdc | ||
121 | #define TM_CAUSE_FAC_UNAV 0xda | ||
122 | #define TM_CAUSE_SYSCALL 0xd8 /* future use */ | ||
123 | #define TM_CAUSE_MISC 0xd6 /* future use */ | ||
124 | #define TM_CAUSE_SIGNAL 0xd4 | ||
125 | #define TM_CAUSE_ALIGNMENT 0xd2 | ||
126 | #define TM_CAUSE_EMULATE 0xd0 | ||
127 | |||
128 | #if defined(CONFIG_PPC_BOOK3S_64) | 114 | #if defined(CONFIG_PPC_BOOK3S_64) |
129 | #define MSR_64BIT MSR_SF | 115 | #define MSR_64BIT MSR_SF |
130 | 116 | ||
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h index 4b4449abf3f8..9dfbc34bdbf5 100644 --- a/arch/powerpc/include/asm/tm.h +++ b/arch/powerpc/include/asm/tm.h | |||
@@ -5,6 +5,8 @@ | |||
5 | * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. | 5 | * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. |
6 | */ | 6 | */ |
7 | 7 | ||
8 | #include <uapi/asm/tm.h> | ||
9 | |||
8 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | 10 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
9 | extern void do_load_up_transact_fpu(struct thread_struct *thread); | 11 | extern void do_load_up_transact_fpu(struct thread_struct *thread); |
10 | extern void do_load_up_transact_altivec(struct thread_struct *thread); | 12 | extern void do_load_up_transact_altivec(struct thread_struct *thread); |
diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild index f7bca6370745..5182c8622b54 100644 --- a/arch/powerpc/include/uapi/asm/Kbuild +++ b/arch/powerpc/include/uapi/asm/Kbuild | |||
@@ -40,6 +40,7 @@ header-y += statfs.h | |||
40 | header-y += swab.h | 40 | header-y += swab.h |
41 | header-y += termbits.h | 41 | header-y += termbits.h |
42 | header-y += termios.h | 42 | header-y += termios.h |
43 | header-y += tm.h | ||
43 | header-y += types.h | 44 | header-y += types.h |
44 | header-y += ucontext.h | 45 | header-y += ucontext.h |
45 | header-y += unistd.h | 46 | header-y += unistd.h |
diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h new file mode 100644 index 000000000000..85059a00f560 --- /dev/null +++ b/arch/powerpc/include/uapi/asm/tm.h | |||
@@ -0,0 +1,18 @@ | |||
1 | #ifndef _ASM_POWERPC_TM_H | ||
2 | #define _ASM_POWERPC_TM_H | ||
3 | |||
4 | /* Reason codes describing kernel causes for transaction aborts. By | ||
5 | * convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if | ||
6 | * the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor. | ||
7 | */ | ||
8 | #define TM_CAUSE_PERSISTENT 0x01 | ||
9 | #define TM_CAUSE_RESCHED 0xde | ||
10 | #define TM_CAUSE_TLBI 0xdc | ||
11 | #define TM_CAUSE_FAC_UNAV 0xda | ||
12 | #define TM_CAUSE_SYSCALL 0xd8 /* future use */ | ||
13 | #define TM_CAUSE_MISC 0xd6 /* future use */ | ||
14 | #define TM_CAUSE_SIGNAL 0xd4 | ||
15 | #define TM_CAUSE_ALIGNMENT 0xd2 | ||
16 | #define TM_CAUSE_EMULATE 0xd0 | ||
17 | |||
18 | #endif | ||