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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:07:18 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:07:18 -0500
commit4bcec913d0a98d991c750034a04675443d1f10b5 (patch)
treece2e960ba26d50f09b6a7bd864b2b4d3c275e69b /arch/powerpc
parent03c7287dd22c18815964219c9a2e75054cd004df (diff)
parentf878f84373aefda7f041a74b24a83b8b7dec1cf0 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull more powerpc bits from Ben Herrenschmidt: "Here are a few more powerpc bits for this merge window. The bulk is made of two pull requests from Scott and Anatolij that I had missed previously (they arrived while I was away). Since both their branches are in -next independently, and the content has been around for a little while, they can still go in. The rest is mostly bug and regression fixes, a small series of cleanups to our pseries cpuidle code (including moving it to the right place), and one new cpuidle bakend for the powernv platform. I also wired up the new sched_attr syscalls" * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (37 commits) powerpc: Wire up sched_setattr and sched_getattr syscalls powerpc/hugetlb: Replace __get_cpu_var with get_cpu_var powerpc: Make sure "cache" directory is removed when offlining cpu powerpc/mm: Fix mmap errno when MAP_FIXED is set and mapping exceeds the allowed address space powerpc/powernv/cpuidle: Back-end cpuidle driver for powernv platform. powerpc/pseries/cpuidle: smt-snooze-delay cleanup. powerpc/pseries/cpuidle: Remove MAX_IDLE_STATE macro. powerpc/pseries/cpuidle: Make cpuidle-pseries backend driver a non-module. powerpc/pseries/cpuidle: Use cpuidle_register() for initialisation. powerpc/pseries/cpuidle: Move processor_idle.c to drivers/cpuidle. powerpc: Fix 32-bit frames for signals delivered when transactional powerpc/iommu: Fix initialisation of DART iommu table powerpc/numa: Fix decimal permissions powerpc/mm: Fix compile error of pgtable-ppc64.h powerpc: Fix hw breakpoints on !HAVE_HW_BREAKPOINT configurations clk: corenet: Adds the clock binding powerpc/booke64: Guard e6500 tlb handler with CONFIG_PPC_FSL_BOOK3E powerpc/512x: dts: add MPC5125 clock specs powerpc/512x: clk: support MPC5121/5123/5125 SoC variants powerpc/512x: clk: enforce even SDHC divider values ...
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig6
-rw-r--r--arch/powerpc/boot/dts/ac14xx.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi113
-rw-r--r--arch/powerpc/boot/dts/mpc5125twr.dts53
-rw-r--r--arch/powerpc/include/asm/clk_interface.h20
-rw-r--r--arch/powerpc/include/asm/mpc5121.h7
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h6
-rw-r--r--arch/powerpc/include/asm/processor.h7
-rw-r--r--arch/powerpc/include/asm/systbl.h2
-rw-r--r--arch/powerpc/include/asm/unistd.h2
-rw-r--r--arch/powerpc/include/uapi/asm/unistd.h3
-rw-r--r--arch/powerpc/kernel/Makefile1
-rw-r--r--arch/powerpc/kernel/cacheinfo.c3
-rw-r--r--arch/powerpc/kernel/clock.c82
-rw-r--r--arch/powerpc/kernel/process.c2
-rw-r--r--arch/powerpc/kernel/signal_32.c19
-rw-r--r--arch/powerpc/kernel/sysfs.c2
-rw-r--r--arch/powerpc/mm/hugetlbpage.c4
-rw-r--r--arch/powerpc/mm/numa.c2
-rw-r--r--arch/powerpc/mm/slice.c2
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S3
-rw-r--r--arch/powerpc/mm/tlb_nohash.c2
-rw-r--r--arch/powerpc/platforms/512x/Kconfig2
-rw-r--r--arch/powerpc/platforms/512x/Makefile3
-rw-r--r--arch/powerpc/platforms/512x/clock-commonclk.c1221
-rw-r--r--arch/powerpc/platforms/512x/clock.c754
-rw-r--r--arch/powerpc/platforms/512x/mpc512x_shared.c169
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/powernv/setup.c13
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig9
-rw-r--r--arch/powerpc/platforms/pseries/Makefile1
-rw-r--r--arch/powerpc/platforms/pseries/processor_idle.c308
-rw-r--r--arch/powerpc/sysdev/dart_iommu.c1
33 files changed, 1536 insertions, 1295 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 25493a0b174c..a5e5d2ec380b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -532,6 +532,7 @@ config PPC_16K_PAGES
532 532
533config PPC_64K_PAGES 533config PPC_64K_PAGES
534 bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64 534 bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
535 depends on !PPC_FSL_BOOK3E
535 select PPC_HAS_HASH_64K if PPC_STD_MMU_64 536 select PPC_HAS_HASH_64K if PPC_STD_MMU_64
536 537
537config PPC_256K_PAGES 538config PPC_256K_PAGES
@@ -1045,11 +1046,6 @@ config KEYS_COMPAT
1045 1046
1046source "crypto/Kconfig" 1047source "crypto/Kconfig"
1047 1048
1048config PPC_CLOCK
1049 bool
1050 default n
1051 select HAVE_CLK
1052
1053config PPC_LIB_RHEAP 1049config PPC_LIB_RHEAP
1054 bool 1050 bool
1055 1051
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c4088cba..a1b883730b31 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
139 }; 139 };
140 }; 140 };
141 141
142 clocks {
143 osc {
144 clock-frequency = <25000000>;
145 };
146 };
147
142 soc@80000000 { 148 soc@80000000 {
149 bus-frequency = <80000000>; /* 80 MHz ips bus */
143 150
144 clock@f00 { 151 clock@f00 {
145 compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock"; 152 compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 2d7cb04ac962..2c0e1552d20b 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12#include <dt-bindings/clock/mpc512x-clock.h>
13
12/dts-v1/; 14/dts-v1/;
13 15
14/ { 16/ {
@@ -49,6 +51,10 @@
49 compatible = "fsl,mpc5121-mbx"; 51 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>; 52 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>; 53 interrupts = <66 0x8>;
54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
57 clock-names = "mbx-bus", "mbx-3d", "mbx";
52 }; 58 };
53 59
54 sram@30000000 { 60 sram@30000000 {
@@ -62,6 +68,8 @@
62 interrupts = <6 8>; 68 interrupts = <6 8>;
63 #address-cells = <1>; 69 #address-cells = <1>;
64 #size-cells = <1>; 70 #size-cells = <1>;
71 clocks = <&clks MPC512x_CLK_NFC>;
72 clock-names = "ipg";
65 }; 73 };
66 74
67 localbus@80000020 { 75 localbus@80000020 {
@@ -73,6 +81,17 @@
73 ranges = <0x0 0x0 0xfc000000 0x04000000>; 81 ranges = <0x0 0x0 0xfc000000 0x04000000>;
74 }; 82 };
75 83
84 clocks {
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 osc: osc {
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <33000000>;
92 };
93 };
94
76 soc@80000000 { 95 soc@80000000 {
77 compatible = "fsl,mpc5121-immr"; 96 compatible = "fsl,mpc5121-immr";
78 #address-cells = <1>; 97 #address-cells = <1>;
@@ -117,9 +136,12 @@
117 }; 136 };
118 137
119 /* Clock control */ 138 /* Clock control */
120 clock@f00 { 139 clks: clock@f00 {
121 compatible = "fsl,mpc5121-clock"; 140 compatible = "fsl,mpc5121-clock";
122 reg = <0xf00 0x100>; 141 reg = <0xf00 0x100>;
142 #clock-cells = <1>;
143 clocks = <&osc>;
144 clock-names = "osc";
123 }; 145 };
124 146
125 /* Power Management Controller */ 147 /* Power Management Controller */
@@ -139,12 +161,24 @@
139 compatible = "fsl,mpc5121-mscan"; 161 compatible = "fsl,mpc5121-mscan";
140 reg = <0x1300 0x80>; 162 reg = <0x1300 0x80>;
141 interrupts = <12 0x8>; 163 interrupts = <12 0x8>;
164 clocks = <&clks MPC512x_CLK_BDLC>,
165 <&clks MPC512x_CLK_IPS>,
166 <&clks MPC512x_CLK_SYS>,
167 <&clks MPC512x_CLK_REF>,
168 <&clks MPC512x_CLK_MSCAN0_MCLK>;
169 clock-names = "ipg", "ips", "sys", "ref", "mclk";
142 }; 170 };
143 171
144 can@1380 { 172 can@1380 {
145 compatible = "fsl,mpc5121-mscan"; 173 compatible = "fsl,mpc5121-mscan";
146 reg = <0x1380 0x80>; 174 reg = <0x1380 0x80>;
147 interrupts = <13 0x8>; 175 interrupts = <13 0x8>;
176 clocks = <&clks MPC512x_CLK_BDLC>,
177 <&clks MPC512x_CLK_IPS>,
178 <&clks MPC512x_CLK_SYS>,
179 <&clks MPC512x_CLK_REF>,
180 <&clks MPC512x_CLK_MSCAN1_MCLK>;
181 clock-names = "ipg", "ips", "sys", "ref", "mclk";
148 }; 182 };
149 183
150 sdhc@1500 { 184 sdhc@1500 {
@@ -153,6 +187,9 @@
153 interrupts = <8 0x8>; 187 interrupts = <8 0x8>;
154 dmas = <&dma0 30>; 188 dmas = <&dma0 30>;
155 dma-names = "rx-tx"; 189 dma-names = "rx-tx";
190 clocks = <&clks MPC512x_CLK_IPS>,
191 <&clks MPC512x_CLK_SDHC>;
192 clock-names = "ipg", "per";
156 }; 193 };
157 194
158 i2c@1700 { 195 i2c@1700 {
@@ -161,6 +198,8 @@
161 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 198 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
162 reg = <0x1700 0x20>; 199 reg = <0x1700 0x20>;
163 interrupts = <9 0x8>; 200 interrupts = <9 0x8>;
201 clocks = <&clks MPC512x_CLK_I2C>;
202 clock-names = "ipg";
164 }; 203 };
165 204
166 i2c@1720 { 205 i2c@1720 {
@@ -169,6 +208,8 @@
169 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 208 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
170 reg = <0x1720 0x20>; 209 reg = <0x1720 0x20>;
171 interrupts = <10 0x8>; 210 interrupts = <10 0x8>;
211 clocks = <&clks MPC512x_CLK_I2C>;
212 clock-names = "ipg";
172 }; 213 };
173 214
174 i2c@1740 { 215 i2c@1740 {
@@ -177,6 +218,8 @@
177 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 218 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
178 reg = <0x1740 0x20>; 219 reg = <0x1740 0x20>;
179 interrupts = <11 0x8>; 220 interrupts = <11 0x8>;
221 clocks = <&clks MPC512x_CLK_I2C>;
222 clock-names = "ipg";
180 }; 223 };
181 224
182 i2ccontrol@1760 { 225 i2ccontrol@1760 {
@@ -188,30 +231,48 @@
188 compatible = "fsl,mpc5121-axe"; 231 compatible = "fsl,mpc5121-axe";
189 reg = <0x2000 0x100>; 232 reg = <0x2000 0x100>;
190 interrupts = <42 0x8>; 233 interrupts = <42 0x8>;
234 clocks = <&clks MPC512x_CLK_AXE>;
235 clock-names = "ipg";
191 }; 236 };
192 237
193 display@2100 { 238 display@2100 {
194 compatible = "fsl,mpc5121-diu"; 239 compatible = "fsl,mpc5121-diu";
195 reg = <0x2100 0x100>; 240 reg = <0x2100 0x100>;
196 interrupts = <64 0x8>; 241 interrupts = <64 0x8>;
242 clocks = <&clks MPC512x_CLK_DIU>;
243 clock-names = "ipg";
197 }; 244 };
198 245
199 can@2300 { 246 can@2300 {
200 compatible = "fsl,mpc5121-mscan"; 247 compatible = "fsl,mpc5121-mscan";
201 reg = <0x2300 0x80>; 248 reg = <0x2300 0x80>;
202 interrupts = <90 0x8>; 249 interrupts = <90 0x8>;
250 clocks = <&clks MPC512x_CLK_BDLC>,
251 <&clks MPC512x_CLK_IPS>,
252 <&clks MPC512x_CLK_SYS>,
253 <&clks MPC512x_CLK_REF>,
254 <&clks MPC512x_CLK_MSCAN2_MCLK>;
255 clock-names = "ipg", "ips", "sys", "ref", "mclk";
203 }; 256 };
204 257
205 can@2380 { 258 can@2380 {
206 compatible = "fsl,mpc5121-mscan"; 259 compatible = "fsl,mpc5121-mscan";
207 reg = <0x2380 0x80>; 260 reg = <0x2380 0x80>;
208 interrupts = <91 0x8>; 261 interrupts = <91 0x8>;
262 clocks = <&clks MPC512x_CLK_BDLC>,
263 <&clks MPC512x_CLK_IPS>,
264 <&clks MPC512x_CLK_SYS>,
265 <&clks MPC512x_CLK_REF>,
266 <&clks MPC512x_CLK_MSCAN3_MCLK>;
267 clock-names = "ipg", "ips", "sys", "ref", "mclk";
209 }; 268 };
210 269
211 viu@2400 { 270 viu@2400 {
212 compatible = "fsl,mpc5121-viu"; 271 compatible = "fsl,mpc5121-viu";
213 reg = <0x2400 0x400>; 272 reg = <0x2400 0x400>;
214 interrupts = <67 0x8>; 273 interrupts = <67 0x8>;
274 clocks = <&clks MPC512x_CLK_VIU>;
275 clock-names = "ipg";
215 }; 276 };
216 277
217 mdio@2800 { 278 mdio@2800 {
@@ -219,6 +280,8 @@
219 reg = <0x2800 0x800>; 280 reg = <0x2800 0x800>;
220 #address-cells = <1>; 281 #address-cells = <1>;
221 #size-cells = <0>; 282 #size-cells = <0>;
283 clocks = <&clks MPC512x_CLK_FEC>;
284 clock-names = "per";
222 }; 285 };
223 286
224 eth0: ethernet@2800 { 287 eth0: ethernet@2800 {
@@ -227,6 +290,8 @@
227 reg = <0x2800 0x800>; 290 reg = <0x2800 0x800>;
228 local-mac-address = [ 00 00 00 00 00 00 ]; 291 local-mac-address = [ 00 00 00 00 00 00 ];
229 interrupts = <4 0x8>; 292 interrupts = <4 0x8>;
293 clocks = <&clks MPC512x_CLK_FEC>;
294 clock-names = "per";
230 }; 295 };
231 296
232 /* USB1 using external ULPI PHY */ 297 /* USB1 using external ULPI PHY */
@@ -238,6 +303,8 @@
238 interrupts = <43 0x8>; 303 interrupts = <43 0x8>;
239 dr_mode = "otg"; 304 dr_mode = "otg";
240 phy_type = "ulpi"; 305 phy_type = "ulpi";
306 clocks = <&clks MPC512x_CLK_USB1>;
307 clock-names = "ipg";
241 }; 308 };
242 309
243 /* USB0 using internal UTMI PHY */ 310 /* USB0 using internal UTMI PHY */
@@ -249,6 +316,8 @@
249 interrupts = <44 0x8>; 316 interrupts = <44 0x8>;
250 dr_mode = "otg"; 317 dr_mode = "otg";
251 phy_type = "utmi_wide"; 318 phy_type = "utmi_wide";
319 clocks = <&clks MPC512x_CLK_USB2>;
320 clock-names = "ipg";
252 }; 321 };
253 322
254 /* IO control */ 323 /* IO control */
@@ -267,6 +336,8 @@
267 compatible = "fsl,mpc5121-pata"; 336 compatible = "fsl,mpc5121-pata";
268 reg = <0x10200 0x100>; 337 reg = <0x10200 0x100>;
269 interrupts = <5 0x8>; 338 interrupts = <5 0x8>;
339 clocks = <&clks MPC512x_CLK_PATA>;
340 clock-names = "ipg";
270 }; 341 };
271 342
272 /* 512x PSCs are not 52xx PSC compatible */ 343 /* 512x PSCs are not 52xx PSC compatible */
@@ -278,6 +349,9 @@
278 interrupts = <40 0x8>; 349 interrupts = <40 0x8>;
279 fsl,rx-fifo-size = <16>; 350 fsl,rx-fifo-size = <16>;
280 fsl,tx-fifo-size = <16>; 351 fsl,tx-fifo-size = <16>;
352 clocks = <&clks MPC512x_CLK_PSC0>,
353 <&clks MPC512x_CLK_PSC0_MCLK>;
354 clock-names = "ipg", "mclk";
281 }; 355 };
282 356
283 /* PSC1 */ 357 /* PSC1 */
@@ -287,6 +361,9 @@
287 interrupts = <40 0x8>; 361 interrupts = <40 0x8>;
288 fsl,rx-fifo-size = <16>; 362 fsl,rx-fifo-size = <16>;
289 fsl,tx-fifo-size = <16>; 363 fsl,tx-fifo-size = <16>;
364 clocks = <&clks MPC512x_CLK_PSC1>,
365 <&clks MPC512x_CLK_PSC1_MCLK>;
366 clock-names = "ipg", "mclk";
290 }; 367 };
291 368
292 /* PSC2 */ 369 /* PSC2 */
@@ -296,6 +373,9 @@
296 interrupts = <40 0x8>; 373 interrupts = <40 0x8>;
297 fsl,rx-fifo-size = <16>; 374 fsl,rx-fifo-size = <16>;
298 fsl,tx-fifo-size = <16>; 375 fsl,tx-fifo-size = <16>;
376 clocks = <&clks MPC512x_CLK_PSC2>,
377 <&clks MPC512x_CLK_PSC2_MCLK>;
378 clock-names = "ipg", "mclk";
299 }; 379 };
300 380
301 /* PSC3 */ 381 /* PSC3 */
@@ -305,6 +385,9 @@
305 interrupts = <40 0x8>; 385 interrupts = <40 0x8>;
306 fsl,rx-fifo-size = <16>; 386 fsl,rx-fifo-size = <16>;
307 fsl,tx-fifo-size = <16>; 387 fsl,tx-fifo-size = <16>;
388 clocks = <&clks MPC512x_CLK_PSC3>,
389 <&clks MPC512x_CLK_PSC3_MCLK>;
390 clock-names = "ipg", "mclk";
308 }; 391 };
309 392
310 /* PSC4 */ 393 /* PSC4 */
@@ -314,6 +397,9 @@
314 interrupts = <40 0x8>; 397 interrupts = <40 0x8>;
315 fsl,rx-fifo-size = <16>; 398 fsl,rx-fifo-size = <16>;
316 fsl,tx-fifo-size = <16>; 399 fsl,tx-fifo-size = <16>;
400 clocks = <&clks MPC512x_CLK_PSC4>,
401 <&clks MPC512x_CLK_PSC4_MCLK>;
402 clock-names = "ipg", "mclk";
317 }; 403 };
318 404
319 /* PSC5 */ 405 /* PSC5 */
@@ -323,6 +409,9 @@
323 interrupts = <40 0x8>; 409 interrupts = <40 0x8>;
324 fsl,rx-fifo-size = <16>; 410 fsl,rx-fifo-size = <16>;
325 fsl,tx-fifo-size = <16>; 411 fsl,tx-fifo-size = <16>;
412 clocks = <&clks MPC512x_CLK_PSC5>,
413 <&clks MPC512x_CLK_PSC5_MCLK>;
414 clock-names = "ipg", "mclk";
326 }; 415 };
327 416
328 /* PSC6 */ 417 /* PSC6 */
@@ -332,6 +421,9 @@
332 interrupts = <40 0x8>; 421 interrupts = <40 0x8>;
333 fsl,rx-fifo-size = <16>; 422 fsl,rx-fifo-size = <16>;
334 fsl,tx-fifo-size = <16>; 423 fsl,tx-fifo-size = <16>;
424 clocks = <&clks MPC512x_CLK_PSC6>,
425 <&clks MPC512x_CLK_PSC6_MCLK>;
426 clock-names = "ipg", "mclk";
335 }; 427 };
336 428
337 /* PSC7 */ 429 /* PSC7 */
@@ -341,6 +433,9 @@
341 interrupts = <40 0x8>; 433 interrupts = <40 0x8>;
342 fsl,rx-fifo-size = <16>; 434 fsl,rx-fifo-size = <16>;
343 fsl,tx-fifo-size = <16>; 435 fsl,tx-fifo-size = <16>;
436 clocks = <&clks MPC512x_CLK_PSC7>,
437 <&clks MPC512x_CLK_PSC7_MCLK>;
438 clock-names = "ipg", "mclk";
344 }; 439 };
345 440
346 /* PSC8 */ 441 /* PSC8 */
@@ -350,6 +445,9 @@
350 interrupts = <40 0x8>; 445 interrupts = <40 0x8>;
351 fsl,rx-fifo-size = <16>; 446 fsl,rx-fifo-size = <16>;
352 fsl,tx-fifo-size = <16>; 447 fsl,tx-fifo-size = <16>;
448 clocks = <&clks MPC512x_CLK_PSC8>,
449 <&clks MPC512x_CLK_PSC8_MCLK>;
450 clock-names = "ipg", "mclk";
353 }; 451 };
354 452
355 /* PSC9 */ 453 /* PSC9 */
@@ -359,6 +457,9 @@
359 interrupts = <40 0x8>; 457 interrupts = <40 0x8>;
360 fsl,rx-fifo-size = <16>; 458 fsl,rx-fifo-size = <16>;
361 fsl,tx-fifo-size = <16>; 459 fsl,tx-fifo-size = <16>;
460 clocks = <&clks MPC512x_CLK_PSC9>,
461 <&clks MPC512x_CLK_PSC9_MCLK>;
462 clock-names = "ipg", "mclk";
362 }; 463 };
363 464
364 /* PSC10 */ 465 /* PSC10 */
@@ -368,6 +469,9 @@
368 interrupts = <40 0x8>; 469 interrupts = <40 0x8>;
369 fsl,rx-fifo-size = <16>; 470 fsl,rx-fifo-size = <16>;
370 fsl,tx-fifo-size = <16>; 471 fsl,tx-fifo-size = <16>;
472 clocks = <&clks MPC512x_CLK_PSC10>,
473 <&clks MPC512x_CLK_PSC10_MCLK>;
474 clock-names = "ipg", "mclk";
371 }; 475 };
372 476
373 /* PSC11 */ 477 /* PSC11 */
@@ -377,12 +481,17 @@
377 interrupts = <40 0x8>; 481 interrupts = <40 0x8>;
378 fsl,rx-fifo-size = <16>; 482 fsl,rx-fifo-size = <16>;
379 fsl,tx-fifo-size = <16>; 483 fsl,tx-fifo-size = <16>;
484 clocks = <&clks MPC512x_CLK_PSC11>,
485 <&clks MPC512x_CLK_PSC11_MCLK>;
486 clock-names = "ipg", "mclk";
380 }; 487 };
381 488
382 pscfifo@11f00 { 489 pscfifo@11f00 {
383 compatible = "fsl,mpc5121-psc-fifo"; 490 compatible = "fsl,mpc5121-psc-fifo";
384 reg = <0x11f00 0x100>; 491 reg = <0x11f00 0x100>;
385 interrupts = <40 0x8>; 492 interrupts = <40 0x8>;
493 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
494 clock-names = "ipg";
386 }; 495 };
387 496
388 dma0: dma@14000 { 497 dma0: dma@14000 {
@@ -400,6 +509,8 @@
400 #address-cells = <3>; 509 #address-cells = <3>;
401 #size-cells = <2>; 510 #size-cells = <2>;
402 #interrupt-cells = <1>; 511 #interrupt-cells = <1>;
512 clocks = <&clks MPC512x_CLK_PCI>;
513 clock-names = "ipg";
403 514
404 reg = <0x80008500 0x100 /* internal registers */ 515 reg = <0x80008500 0x100 /* internal registers */
405 0x80008300 0x8>; /* config space access registers */ 516 0x80008300 0x8>; /* config space access registers */
diff --git a/arch/powerpc/boot/dts/mpc5125twr.dts b/arch/powerpc/boot/dts/mpc5125twr.dts
index a618dfc13e4c..e4f297471748 100644
--- a/arch/powerpc/boot/dts/mpc5125twr.dts
+++ b/arch/powerpc/boot/dts/mpc5125twr.dts
@@ -12,6 +12,8 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15#include <dt-bindings/clock/mpc512x-clock.h>
16
15/dts-v1/; 17/dts-v1/;
16 18
17/ { 19/ {
@@ -54,6 +56,17 @@
54 reg = <0x30000000 0x08000>; // 32K at 0x30000000 56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
55 }; 57 };
56 58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 osc: osc {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <33000000>;
67 };
68 };
69
57 soc@80000000 { 70 soc@80000000 {
58 compatible = "fsl,mpc5121-immr"; 71 compatible = "fsl,mpc5121-immr";
59 #address-cells = <1>; 72 #address-cells = <1>;
@@ -87,9 +100,12 @@
87 reg = <0xe00 0x100>; 100 reg = <0xe00 0x100>;
88 }; 101 };
89 102
90 clock@f00 { // Clock control 103 clks: clock@f00 { // Clock control
91 compatible = "fsl,mpc5121-clock"; 104 compatible = "fsl,mpc5121-clock";
92 reg = <0xf00 0x100>; 105 reg = <0xf00 0x100>;
106 #clock-cells = <1>;
107 clocks = <&osc>;
108 clock-names = "osc";
93 }; 109 };
94 110
95 pmc@1000{ // Power Management Controller 111 pmc@1000{ // Power Management Controller
@@ -114,18 +130,33 @@
114 compatible = "fsl,mpc5121-mscan"; 130 compatible = "fsl,mpc5121-mscan";
115 interrupts = <12 0x8>; 131 interrupts = <12 0x8>;
116 reg = <0x1300 0x80>; 132 reg = <0x1300 0x80>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
138 clock-names = "ipg", "ips", "sys", "ref", "mclk";
117 }; 139 };
118 140
119 can@1380 { 141 can@1380 {
120 compatible = "fsl,mpc5121-mscan"; 142 compatible = "fsl,mpc5121-mscan";
121 interrupts = <13 0x8>; 143 interrupts = <13 0x8>;
122 reg = <0x1380 0x80>; 144 reg = <0x1380 0x80>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
149 <&clks MPC512x_CLK_MSCAN1_MCLK>;
150 clock-names = "ipg", "ips", "sys", "ref", "mclk";
123 }; 151 };
124 152
125 sdhc@1500 { 153 sdhc@1500 {
126 compatible = "fsl,mpc5121-sdhc"; 154 compatible = "fsl,mpc5121-sdhc";
127 interrupts = <8 0x8>; 155 interrupts = <8 0x8>;
128 reg = <0x1500 0x100>; 156 reg = <0x1500 0x100>;
157 clocks = <&clks MPC512x_CLK_IPS>,
158 <&clks MPC512x_CLK_SDHC>;
159 clock-names = "ipg", "per";
129 }; 160 };
130 161
131 i2c@1700 { 162 i2c@1700 {
@@ -134,6 +165,8 @@
134 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 165 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
135 reg = <0x1700 0x20>; 166 reg = <0x1700 0x20>;
136 interrupts = <0x9 0x8>; 167 interrupts = <0x9 0x8>;
168 clocks = <&clks MPC512x_CLK_I2C>;
169 clock-names = "ipg";
137 }; 170 };
138 171
139 i2c@1720 { 172 i2c@1720 {
@@ -142,6 +175,8 @@
142 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 175 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
143 reg = <0x1720 0x20>; 176 reg = <0x1720 0x20>;
144 interrupts = <0xa 0x8>; 177 interrupts = <0xa 0x8>;
178 clocks = <&clks MPC512x_CLK_I2C>;
179 clock-names = "ipg";
145 }; 180 };
146 181
147 i2c@1740 { 182 i2c@1740 {
@@ -150,6 +185,8 @@
150 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 185 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
151 reg = <0x1740 0x20>; 186 reg = <0x1740 0x20>;
152 interrupts = <0xb 0x8>; 187 interrupts = <0xb 0x8>;
188 clocks = <&clks MPC512x_CLK_I2C>;
189 clock-names = "ipg";
153 }; 190 };
154 191
155 i2ccontrol@1760 { 192 i2ccontrol@1760 {
@@ -161,6 +198,8 @@
161 compatible = "fsl,mpc5121-diu"; 198 compatible = "fsl,mpc5121-diu";
162 reg = <0x2100 0x100>; 199 reg = <0x2100 0x100>;
163 interrupts = <64 0x8>; 200 interrupts = <64 0x8>;
201 clocks = <&clks MPC512x_CLK_DIU>;
202 clock-names = "ipg";
164 }; 203 };
165 204
166 mdio@2800 { 205 mdio@2800 {
@@ -180,6 +219,8 @@
180 interrupts = <4 0x8>; 219 interrupts = <4 0x8>;
181 phy-handle = < &phy0 >; 220 phy-handle = < &phy0 >;
182 phy-connection-type = "rmii"; 221 phy-connection-type = "rmii";
222 clocks = <&clks MPC512x_CLK_FEC>;
223 clock-names = "per";
183 }; 224 };
184 225
185 // IO control 226 // IO control
@@ -200,6 +241,8 @@
200 interrupts = <43 0x8>; 241 interrupts = <43 0x8>;
201 dr_mode = "host"; 242 dr_mode = "host";
202 phy_type = "ulpi"; 243 phy_type = "ulpi";
244 clocks = <&clks MPC512x_CLK_USB1>;
245 clock-names = "ipg";
203 status = "disabled"; 246 status = "disabled";
204 }; 247 };
205 248
@@ -211,6 +254,9 @@
211 interrupts = <40 0x8>; 254 interrupts = <40 0x8>;
212 fsl,rx-fifo-size = <16>; 255 fsl,rx-fifo-size = <16>;
213 fsl,tx-fifo-size = <16>; 256 fsl,tx-fifo-size = <16>;
257 clocks = <&clks MPC512x_CLK_PSC1>,
258 <&clks MPC512x_CLK_PSC1_MCLK>;
259 clock-names = "ipg", "mclk";
214 }; 260 };
215 261
216 // PSC9 uart1 aka ttyPSC1 262 // PSC9 uart1 aka ttyPSC1
@@ -220,12 +266,17 @@
220 interrupts = <40 0x8>; 266 interrupts = <40 0x8>;
221 fsl,rx-fifo-size = <16>; 267 fsl,rx-fifo-size = <16>;
222 fsl,tx-fifo-size = <16>; 268 fsl,tx-fifo-size = <16>;
269 clocks = <&clks MPC512x_CLK_PSC9>,
270 <&clks MPC512x_CLK_PSC9_MCLK>;
271 clock-names = "ipg", "mclk";
223 }; 272 };
224 273
225 pscfifo@11f00 { 274 pscfifo@11f00 {
226 compatible = "fsl,mpc5121-psc-fifo"; 275 compatible = "fsl,mpc5121-psc-fifo";
227 reg = <0x11f00 0x100>; 276 reg = <0x11f00 0x100>;
228 interrupts = <40 0x8>; 277 interrupts = <40 0x8>;
278 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
279 clock-names = "ipg";
229 }; 280 };
230 281
231 dma@14000 { 282 dma@14000 {
diff --git a/arch/powerpc/include/asm/clk_interface.h b/arch/powerpc/include/asm/clk_interface.h
deleted file mode 100644
index ab1882c1e176..000000000000
--- a/arch/powerpc/include/asm/clk_interface.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_POWERPC_CLK_INTERFACE_H
2#define __ASM_POWERPC_CLK_INTERFACE_H
3
4#include <linux/clk.h>
5
6struct clk_interface {
7 struct clk* (*clk_get) (struct device *dev, const char *id);
8 int (*clk_enable) (struct clk *clk);
9 void (*clk_disable) (struct clk *clk);
10 unsigned long (*clk_get_rate) (struct clk *clk);
11 void (*clk_put) (struct clk *clk);
12 long (*clk_round_rate) (struct clk *clk, unsigned long rate);
13 int (*clk_set_rate) (struct clk *clk, unsigned long rate);
14 int (*clk_set_parent) (struct clk *clk, struct clk *parent);
15 struct clk* (*clk_get_parent) (struct clk *clk);
16};
17
18extern struct clk_interface clk_functions;
19
20#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 887d3d6133e3..4a69cd1d5041 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -37,7 +37,12 @@ struct mpc512x_ccm {
37 u32 cccr; /* CFM Clock Control Register */ 37 u32 cccr; /* CFM Clock Control Register */
38 u32 dccr; /* DIU Clock Control Register */ 38 u32 dccr; /* DIU Clock Control Register */
39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */ 39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
40 u8 res[0x98]; /* Reserved */ 40 u32 out_ccr[4]; /* OUT CLK Configure Registers */
41 u32 rsv0[2]; /* Reserved */
42 u32 scfr3; /* System Clock Frequency Register 3 */
43 u32 rsv1[3]; /* Reserved */
44 u32 spll_lock_cnt; /* System PLL Lock Counter */
45 u8 res[0x6c]; /* Reserved */
41}; 46};
42 47
43/* 48/*
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index d27960c89a71..bc141c950b1e 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -560,9 +560,9 @@ extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
560 pmd_t *pmdp); 560 pmd_t *pmdp);
561 561
562#define pmd_move_must_withdraw pmd_move_must_withdraw 562#define pmd_move_must_withdraw pmd_move_must_withdraw
563typedef struct spinlock spinlock_t; 563struct spinlock;
564static inline int pmd_move_must_withdraw(spinlock_t *new_pmd_ptl, 564static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
565 spinlock_t *old_pmd_ptl) 565 struct spinlock *old_pmd_ptl)
566{ 566{
567 /* 567 /*
568 * Archs like ppc64 use pgtable to store per pmd 568 * Archs like ppc64 use pgtable to store per pmd
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8ca20ac28dc2..b62de43ae5f3 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -450,13 +450,6 @@ enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
450 450
451extern int powersave_nap; /* set if nap mode can be used in idle loop */ 451extern int powersave_nap; /* set if nap mode can be used in idle loop */
452extern void power7_nap(void); 452extern void power7_nap(void);
453
454#ifdef CONFIG_PSERIES_IDLE
455extern void update_smt_snooze_delay(int cpu, int residency);
456#else
457static inline void update_smt_snooze_delay(int cpu, int residency) {}
458#endif
459
460extern void flush_instruction_cache(void); 453extern void flush_instruction_cache(void);
461extern void hard_reset_now(void); 454extern void hard_reset_now(void);
462extern void poweroff_now(void); 455extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 43523fe0d8b4..3ddf70276706 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -359,3 +359,5 @@ COMPAT_SYS(process_vm_readv)
359COMPAT_SYS(process_vm_writev) 359COMPAT_SYS(process_vm_writev)
360SYSCALL(finit_module) 360SYSCALL(finit_module)
361SYSCALL(ni_syscall) /* sys_kcmp */ 361SYSCALL(ni_syscall) /* sys_kcmp */
362SYSCALL_SPU(sched_setattr)
363SYSCALL_SPU(sched_getattr)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3ca819f541bf..4494f029b632 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
12#include <uapi/asm/unistd.h> 12#include <uapi/asm/unistd.h>
13 13
14 14
15#define __NR_syscalls 355 15#define __NR_syscalls 357
16 16
17#define __NR__exit __NR_exit 17#define __NR__exit __NR_exit
18#define NR_syscalls __NR_syscalls 18#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h
index 74cb4d72d673..881bf2e2560d 100644
--- a/arch/powerpc/include/uapi/asm/unistd.h
+++ b/arch/powerpc/include/uapi/asm/unistd.h
@@ -377,6 +377,7 @@
377#define __NR_process_vm_writev 352 377#define __NR_process_vm_writev 352
378#define __NR_finit_module 353 378#define __NR_finit_module 353
379#define __NR_kcmp 354 379#define __NR_kcmp 354
380 380#define __NR_sched_setattr 355
381#define __NR_sched_getattr 356
381 382
382#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */ 383#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 904d713366ff..fcc9a89a4695 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -48,7 +48,6 @@ obj-$(CONFIG_ALTIVEC) += vecemu.o
48obj-$(CONFIG_PPC_970_NAP) += idle_power4.o 48obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
49obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o 49obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o
50obj-$(CONFIG_PPC_OF) += of_platform.o prom_parse.o 50obj-$(CONFIG_PPC_OF) += of_platform.o prom_parse.o
51obj-$(CONFIG_PPC_CLOCK) += clock.o
52procfs-y := proc_powerpc.o 51procfs-y := proc_powerpc.o
53obj-$(CONFIG_PROC_FS) += $(procfs-y) 52obj-$(CONFIG_PROC_FS) += $(procfs-y)
54rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o 53rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index abfa011344d9..2912b8787aa4 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -793,6 +793,9 @@ static void remove_cache_dir(struct cache_dir *cache_dir)
793{ 793{
794 remove_index_dirs(cache_dir); 794 remove_index_dirs(cache_dir);
795 795
796 /* Remove cache dir from sysfs */
797 kobject_del(cache_dir->kobj);
798
796 kobject_put(cache_dir->kobj); 799 kobject_put(cache_dir->kobj);
797 800
798 kfree(cache_dir); 801 kfree(cache_dir);
diff --git a/arch/powerpc/kernel/clock.c b/arch/powerpc/kernel/clock.c
deleted file mode 100644
index a764b47791e8..000000000000
--- a/arch/powerpc/kernel/clock.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Dummy clk implementations for powerpc.
3 * These need to be overridden in platform code.
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/errno.h>
9#include <linux/export.h>
10#include <asm/clk_interface.h>
11
12struct clk_interface clk_functions;
13
14struct clk *clk_get(struct device *dev, const char *id)
15{
16 if (clk_functions.clk_get)
17 return clk_functions.clk_get(dev, id);
18 return ERR_PTR(-ENOSYS);
19}
20EXPORT_SYMBOL(clk_get);
21
22void clk_put(struct clk *clk)
23{
24 if (clk_functions.clk_put)
25 clk_functions.clk_put(clk);
26}
27EXPORT_SYMBOL(clk_put);
28
29int clk_enable(struct clk *clk)
30{
31 if (clk_functions.clk_enable)
32 return clk_functions.clk_enable(clk);
33 return -ENOSYS;
34}
35EXPORT_SYMBOL(clk_enable);
36
37void clk_disable(struct clk *clk)
38{
39 if (clk_functions.clk_disable)
40 clk_functions.clk_disable(clk);
41}
42EXPORT_SYMBOL(clk_disable);
43
44unsigned long clk_get_rate(struct clk *clk)
45{
46 if (clk_functions.clk_get_rate)
47 return clk_functions.clk_get_rate(clk);
48 return 0;
49}
50EXPORT_SYMBOL(clk_get_rate);
51
52long clk_round_rate(struct clk *clk, unsigned long rate)
53{
54 if (clk_functions.clk_round_rate)
55 return clk_functions.clk_round_rate(clk, rate);
56 return -ENOSYS;
57}
58EXPORT_SYMBOL(clk_round_rate);
59
60int clk_set_rate(struct clk *clk, unsigned long rate)
61{
62 if (clk_functions.clk_set_rate)
63 return clk_functions.clk_set_rate(clk, rate);
64 return -ENOSYS;
65}
66EXPORT_SYMBOL(clk_set_rate);
67
68struct clk *clk_get_parent(struct clk *clk)
69{
70 if (clk_functions.clk_get_parent)
71 return clk_functions.clk_get_parent(clk);
72 return ERR_PTR(-ENOSYS);
73}
74EXPORT_SYMBOL(clk_get_parent);
75
76int clk_set_parent(struct clk *clk, struct clk *parent)
77{
78 if (clk_functions.clk_set_parent)
79 return clk_functions.clk_set_parent(clk, parent);
80 return -ENOSYS;
81}
82EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 64b7a6e61dd1..8d4c247f1738 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -811,7 +811,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
811 * schedule DABR 811 * schedule DABR
812 */ 812 */
813#ifndef CONFIG_HAVE_HW_BREAKPOINT 813#ifndef CONFIG_HAVE_HW_BREAKPOINT
814 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) 814 if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
815 set_breakpoint(&new->thread.hw_brk); 815 set_breakpoint(&new->thread.hw_brk);
816#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 816#endif /* CONFIG_HAVE_HW_BREAKPOINT */
817#endif 817#endif
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 6ce69e6f1fcb..a67e00aa3caa 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -1022,29 +1022,24 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
1022#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1022#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1023 tm_frame = &rt_sf->uc_transact.uc_mcontext; 1023 tm_frame = &rt_sf->uc_transact.uc_mcontext;
1024 if (MSR_TM_ACTIVE(regs->msr)) { 1024 if (MSR_TM_ACTIVE(regs->msr)) {
1025 if (__put_user((unsigned long)&rt_sf->uc_transact,
1026 &rt_sf->uc.uc_link) ||
1027 __put_user((unsigned long)tm_frame,
1028 &rt_sf->uc_transact.uc_regs))
1029 goto badframe;
1025 if (save_tm_user_regs(regs, frame, tm_frame, sigret)) 1030 if (save_tm_user_regs(regs, frame, tm_frame, sigret))
1026 goto badframe; 1031 goto badframe;
1027 } 1032 }
1028 else 1033 else
1029#endif 1034#endif
1030 { 1035 {
1036 if (__put_user(0, &rt_sf->uc.uc_link))
1037 goto badframe;
1031 if (save_user_regs(regs, frame, tm_frame, sigret, 1)) 1038 if (save_user_regs(regs, frame, tm_frame, sigret, 1))
1032 goto badframe; 1039 goto badframe;
1033 } 1040 }
1034 regs->link = tramp; 1041 regs->link = tramp;
1035 1042
1036#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1037 if (MSR_TM_ACTIVE(regs->msr)) {
1038 if (__put_user((unsigned long)&rt_sf->uc_transact,
1039 &rt_sf->uc.uc_link)
1040 || __put_user((unsigned long)tm_frame, &rt_sf->uc_transact.uc_regs))
1041 goto badframe;
1042 }
1043 else
1044#endif
1045 if (__put_user(0, &rt_sf->uc.uc_link))
1046 goto badframe;
1047
1048 current->thread.fp_state.fpscr = 0; /* turn off all fp exceptions */ 1043 current->thread.fp_state.fpscr = 0; /* turn off all fp exceptions */
1049 1044
1050 /* create a stack frame for the caller of the handler */ 1045 /* create a stack frame for the caller of the handler */
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index d4a43e64a6a9..97e1dc917683 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -51,8 +51,6 @@ static ssize_t store_smt_snooze_delay(struct device *dev,
51 return -EINVAL; 51 return -EINVAL;
52 52
53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze; 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
54 update_smt_snooze_delay(cpu->dev.id, snooze);
55
56 return count; 54 return count;
57} 55}
58 56
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 90bb6d9409bf..eb923654ba80 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -472,12 +472,13 @@ static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
472{ 472{
473 struct hugepd_freelist **batchp; 473 struct hugepd_freelist **batchp;
474 474
475 batchp = &__get_cpu_var(hugepd_freelist_cur); 475 batchp = &get_cpu_var(hugepd_freelist_cur);
476 476
477 if (atomic_read(&tlb->mm->mm_users) < 2 || 477 if (atomic_read(&tlb->mm->mm_users) < 2 ||
478 cpumask_equal(mm_cpumask(tlb->mm), 478 cpumask_equal(mm_cpumask(tlb->mm),
479 cpumask_of(smp_processor_id()))) { 479 cpumask_of(smp_processor_id()))) {
480 kmem_cache_free(hugepte_cache, hugepte); 480 kmem_cache_free(hugepte_cache, hugepte);
481 put_cpu_var(hugepd_freelist_cur);
481 return; 482 return;
482 } 483 }
483 484
@@ -491,6 +492,7 @@ static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
491 call_rcu_sched(&(*batchp)->rcu, hugepd_free_rcu_callback); 492 call_rcu_sched(&(*batchp)->rcu, hugepd_free_rcu_callback);
492 *batchp = NULL; 493 *batchp = NULL;
493 } 494 }
495 put_cpu_var(hugepd_freelist_cur);
494} 496}
495#endif 497#endif
496 498
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 86a63de072c6..30a42e24bf14 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1785,7 +1785,7 @@ static const struct file_operations topology_ops = {
1785static int topology_update_init(void) 1785static int topology_update_init(void)
1786{ 1786{
1787 start_topology_update(); 1787 start_topology_update();
1788 proc_create("powerpc/topology_updates", 644, NULL, &topology_ops); 1788 proc_create("powerpc/topology_updates", 0644, NULL, &topology_ops);
1789 1789
1790 return 0; 1790 return 0;
1791} 1791}
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 7ce9cf3b6988..b0c75cc15efc 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -408,7 +408,7 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
408 if (fixed && (addr & ((1ul << pshift) - 1))) 408 if (fixed && (addr & ((1ul << pshift) - 1)))
409 return -EINVAL; 409 return -EINVAL;
410 if (fixed && addr > (mm->task_size - len)) 410 if (fixed && addr > (mm->task_size - len))
411 return -EINVAL; 411 return -ENOMEM;
412 412
413 /* If hint, make sure it matches our alignment restrictions */ 413 /* If hint, make sure it matches our alignment restrictions */
414 if (!fixed && addr) { 414 if (!fixed && addr) {
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 16250b162375..c95eb323e9ae 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -240,6 +240,7 @@ itlb_miss_fault_bolted:
240 beq tlb_miss_common_bolted 240 beq tlb_miss_common_bolted
241 b itlb_miss_kernel_bolted 241 b itlb_miss_kernel_bolted
242 242
243#ifdef CONFIG_PPC_FSL_BOOK3E
243/* 244/*
244 * TLB miss handling for e6500 and derivatives, using hardware tablewalk. 245 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
245 * 246 *
@@ -409,7 +410,7 @@ itlb_miss_fault_e6500:
409 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 410 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
410 tlb_epilog_bolted 411 tlb_epilog_bolted
411 b exc_instruction_storage_book3e 412 b exc_instruction_storage_book3e
412 413#endif /* CONFIG_PPC_FSL_BOOK3E */
413 414
414/********************************************************************** 415/**********************************************************************
415 * * 416 * *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 735839b74dc5..b37a58e1c92d 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -557,10 +557,12 @@ static void setup_mmu_htw(void)
557 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e); 557 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
558 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); 558 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
559 break; 559 break;
560#ifdef CONFIG_PPC_FSL_BOOK3E
560 case PPC_HTW_E6500: 561 case PPC_HTW_E6500:
561 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); 562 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
562 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); 563 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
563 break; 564 break;
565#endif
564 } 566 }
565 pr_info("MMU: Book3E HW tablewalk %s\n", 567 pr_info("MMU: Book3E HW tablewalk %s\n",
566 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported"); 568 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cbfcb1d..5aa3f4b5332c 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,9 @@
1config PPC_MPC512x 1config PPC_MPC512x
2 bool "512x-based boards" 2 bool "512x-based boards"
3 depends on 6xx 3 depends on 6xx
4 select COMMON_CLK
4 select FSL_SOC 5 select FSL_SOC
5 select IPIC 6 select IPIC
6 select PPC_CLOCK
7 select PPC_PCI_CHOICE 7 select PPC_PCI_CHOICE
8 select FSL_PCI if PCI 8 select FSL_PCI if PCI
9 select ARCH_WANT_OPTIONAL_GPIOLIB 9 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb9340e09f..01693121a2b1 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,8 @@
1# 1#
2# Makefile for the Freescale PowerPC 512x linux kernel. 2# Makefile for the Freescale PowerPC 512x linux kernel.
3# 3#
4obj-y += clock.o mpc512x_shared.o 4obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
5obj-y += mpc512x_shared.o
5obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o 6obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
6obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o 7obj-$(CONFIG_MPC512x_GENERIC) += mpc512x_generic.o
7obj-$(CONFIG_PDM360NG) += pdm360ng.o 8obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 000000000000..6eb614a271fb
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,1221 @@
1/*
2 * Copyright (C) 2013 DENX Software Engineering
3 *
4 * Gerhard Sittig, <gsi@denx.de>
5 *
6 * common clock driver support for the MPC512x platform
7 *
8 * This is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk-provider.h>
16#include <linux/clkdev.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22
23#include <asm/mpc5121.h>
24#include <dt-bindings/clock/mpc512x-clock.h>
25
26#include "mpc512x.h" /* our public mpc5121_clk_init() API */
27
28/* helpers to keep the MCLK intermediates "somewhere" in our table */
29enum {
30 MCLK_IDX_MUX0,
31 MCLK_IDX_EN0,
32 MCLK_IDX_DIV0,
33 MCLK_MAX_IDX,
34};
35
36#define NR_PSCS 12
37#define NR_MSCANS 4
38#define NR_SPDIFS 1
39#define NR_OUTCLK 4
40#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS + NR_OUTCLK)
41
42/* extend the public set of clocks by adding internal slots for management */
43enum {
44 /* arrange for adjacent numbers after the public set */
45 MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
46 /* clocks which aren't announced to the public */
47 MPC512x_CLK_DDR,
48 MPC512x_CLK_MEM,
49 MPC512x_CLK_IIM,
50 /* intermediates in div+gate combos or fractional dividers */
51 MPC512x_CLK_DDR_UG,
52 MPC512x_CLK_SDHC_x4,
53 MPC512x_CLK_SDHC_UG,
54 MPC512x_CLK_SDHC2_UG,
55 MPC512x_CLK_DIU_x4,
56 MPC512x_CLK_DIU_UG,
57 MPC512x_CLK_MBX_BUS_UG,
58 MPC512x_CLK_MBX_UG,
59 MPC512x_CLK_MBX_3D_UG,
60 MPC512x_CLK_PCI_UG,
61 MPC512x_CLK_NFC_UG,
62 MPC512x_CLK_LPC_UG,
63 MPC512x_CLK_SPDIF_TX_IN,
64 /* intermediates for the mux+gate+div+mux MCLK generation */
65 MPC512x_CLK_MCLKS_FIRST,
66 MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
67 + NR_MCLKS * MCLK_MAX_IDX,
68 /* internal, symbolic spec for the number of slots */
69 MPC512x_CLK_LAST_PRIVATE,
70};
71
72/* data required for the OF clock provider registration */
73static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
74static struct clk_onecell_data clk_data;
75
76/* CCM register access */
77static struct mpc512x_ccm __iomem *clkregs;
78static DEFINE_SPINLOCK(clklock);
79
80/* SoC variants {{{ */
81
82/*
83 * tell SoC variants apart as they are rather similar yet not identical,
84 * cache the result in an enum to not repeatedly run the expensive OF test
85 *
86 * MPC5123 is an MPC5121 without the MBX graphics accelerator
87 *
88 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF,
89 * no PATA, no SATA, no PCI, two FECs (of different compatibility name),
90 * only 10 PSCs (of different compatibility name), two SDHCs, different
91 * NFC IP block, output clocks, system PLL status query, different CPMF
92 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
93 * those differences can get folded into this clock provider support
94 * code and don't warrant a separate highly redundant implementation
95 */
96
97static enum soc_type {
98 MPC512x_SOC_MPC5121,
99 MPC512x_SOC_MPC5123,
100 MPC512x_SOC_MPC5125,
101} soc;
102
103static void mpc512x_clk_determine_soc(void)
104{
105 if (of_machine_is_compatible("fsl,mpc5121")) {
106 soc = MPC512x_SOC_MPC5121;
107 return;
108 }
109 if (of_machine_is_compatible("fsl,mpc5123")) {
110 soc = MPC512x_SOC_MPC5123;
111 return;
112 }
113 if (of_machine_is_compatible("fsl,mpc5125")) {
114 soc = MPC512x_SOC_MPC5125;
115 return;
116 }
117}
118
119static bool soc_has_mbx(void)
120{
121 if (soc == MPC512x_SOC_MPC5121)
122 return true;
123 return false;
124}
125
126static bool soc_has_axe(void)
127{
128 if (soc == MPC512x_SOC_MPC5125)
129 return false;
130 return true;
131}
132
133static bool soc_has_viu(void)
134{
135 if (soc == MPC512x_SOC_MPC5125)
136 return false;
137 return true;
138}
139
140static bool soc_has_spdif(void)
141{
142 if (soc == MPC512x_SOC_MPC5125)
143 return false;
144 return true;
145}
146
147static bool soc_has_pata(void)
148{
149 if (soc == MPC512x_SOC_MPC5125)
150 return false;
151 return true;
152}
153
154static bool soc_has_sata(void)
155{
156 if (soc == MPC512x_SOC_MPC5125)
157 return false;
158 return true;
159}
160
161static bool soc_has_pci(void)
162{
163 if (soc == MPC512x_SOC_MPC5125)
164 return false;
165 return true;
166}
167
168static bool soc_has_fec2(void)
169{
170 if (soc == MPC512x_SOC_MPC5125)
171 return true;
172 return false;
173}
174
175static int soc_max_pscnum(void)
176{
177 if (soc == MPC512x_SOC_MPC5125)
178 return 10;
179 return 12;
180}
181
182static bool soc_has_sdhc2(void)
183{
184 if (soc == MPC512x_SOC_MPC5125)
185 return true;
186 return false;
187}
188
189static bool soc_has_nfc_5125(void)
190{
191 if (soc == MPC512x_SOC_MPC5125)
192 return true;
193 return false;
194}
195
196static bool soc_has_outclk(void)
197{
198 if (soc == MPC512x_SOC_MPC5125)
199 return true;
200 return false;
201}
202
203static bool soc_has_cpmf_0_bypass(void)
204{
205 if (soc == MPC512x_SOC_MPC5125)
206 return true;
207 return false;
208}
209
210static bool soc_has_mclk_mux0_canin(void)
211{
212 if (soc == MPC512x_SOC_MPC5125)
213 return true;
214 return false;
215}
216
217/* }}} SoC variants */
218/* common clk API wrappers {{{ */
219
220/* convenience wrappers around the common clk API */
221static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
222{
223 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
224}
225
226static inline struct clk *mpc512x_clk_factor(
227 const char *name, const char *parent_name,
228 int mul, int div)
229{
230 int clkflags;
231
232 clkflags = CLK_SET_RATE_PARENT;
233 return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
234 mul, div);
235}
236
237static inline struct clk *mpc512x_clk_divider(
238 const char *name, const char *parent_name, u8 clkflags,
239 u32 __iomem *reg, u8 pos, u8 len, int divflags)
240{
241 return clk_register_divider(NULL, name, parent_name, clkflags,
242 reg, pos, len, divflags, &clklock);
243}
244
245static inline struct clk *mpc512x_clk_divtable(
246 const char *name, const char *parent_name,
247 u32 __iomem *reg, u8 pos, u8 len,
248 const struct clk_div_table *divtab)
249{
250 u8 divflags;
251
252 divflags = 0;
253 return clk_register_divider_table(NULL, name, parent_name, 0,
254 reg, pos, len, divflags,
255 divtab, &clklock);
256}
257
258static inline struct clk *mpc512x_clk_gated(
259 const char *name, const char *parent_name,
260 u32 __iomem *reg, u8 pos)
261{
262 int clkflags;
263
264 clkflags = CLK_SET_RATE_PARENT;
265 return clk_register_gate(NULL, name, parent_name, clkflags,
266 reg, pos, 0, &clklock);
267}
268
269static inline struct clk *mpc512x_clk_muxed(const char *name,
270 const char **parent_names, int parent_count,
271 u32 __iomem *reg, u8 pos, u8 len)
272{
273 int clkflags;
274 u8 muxflags;
275
276 clkflags = CLK_SET_RATE_PARENT;
277 muxflags = 0;
278 return clk_register_mux(NULL, name,
279 parent_names, parent_count, clkflags,
280 reg, pos, len, muxflags, &clklock);
281}
282
283/* }}} common clk API wrappers */
284
285/* helper to isolate a bit field from a register */
286static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
287{
288 uint32_t val;
289
290 val = in_be32(reg);
291 val >>= pos;
292 val &= (1 << len) - 1;
293 return val;
294}
295
296/* get the SPMF and translate it into the "sys pll" multiplier */
297static int get_spmf_mult(void)
298{
299 static int spmf_to_mult[] = {
300 68, 1, 12, 16, 20, 24, 28, 32,
301 36, 40, 44, 48, 52, 56, 60, 64,
302 };
303 int spmf;
304
305 spmf = get_bit_field(&clkregs->spmr, 24, 4);
306 return spmf_to_mult[spmf];
307}
308
309/*
310 * get the SYS_DIV value and translate it into a divide factor
311 *
312 * values returned from here are a multiple of the real factor since the
313 * divide ratio is fractional
314 */
315static int get_sys_div_x2(void)
316{
317 static int sysdiv_code_to_x2[] = {
318 4, 5, 6, 7, 8, 9, 10, 14,
319 12, 16, 18, 22, 20, 24, 26, 30,
320 28, 32, 34, 38, 36, 40, 42, 46,
321 44, 48, 50, 54, 52, 56, 58, 62,
322 60, 64, 66,
323 };
324 int divcode;
325
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6);
327 return sysdiv_code_to_x2[divcode];
328}
329
330/*
331 * get the CPMF value and translate it into a multiplier factor
332 *
333 * values returned from here are a multiple of the real factor since the
334 * multiplier ratio is fractional
335 */
336static int get_cpmf_mult_x2(void)
337{
338 static int cpmf_to_mult_x36[] = {
339 /* 0b000 is "times 36" */
340 72, 2, 2, 3, 4, 5, 6, 7,
341 };
342 static int cpmf_to_mult_0by[] = {
343 /* 0b000 is "bypass" */
344 2, 2, 2, 3, 4, 5, 6, 7,
345 };
346
347 int *cpmf_to_mult;
348 int cpmf;
349
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4);
351 if (soc_has_cpmf_0_bypass())
352 cpmf_to_mult = cpmf_to_mult_0by;
353 else
354 cpmf_to_mult = cpmf_to_mult_x36;
355 return cpmf_to_mult[cpmf];
356}
357
358/*
359 * some of the clock dividers do scale in a linear way, yet not all of
360 * their bit combinations are legal; use a divider table to get a
361 * resulting set of applicable divider values
362 */
363
364/* applies to the IPS_DIV, and PCI_DIV values */
365static struct clk_div_table divtab_2346[] = {
366 { .val = 2, .div = 2, },
367 { .val = 3, .div = 3, },
368 { .val = 4, .div = 4, },
369 { .val = 6, .div = 6, },
370 { .div = 0, },
371};
372
373/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
374static struct clk_div_table divtab_1234[] = {
375 { .val = 1, .div = 1, },
376 { .val = 2, .div = 2, },
377 { .val = 3, .div = 3, },
378 { .val = 4, .div = 4, },
379 { .div = 0, },
380};
381
382static int get_freq_from_dt(char *propname)
383{
384 struct device_node *np;
385 const unsigned int *prop;
386 int val;
387
388 val = 0;
389 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
390 if (np) {
391 prop = of_get_property(np, propname, NULL);
392 if (prop)
393 val = *prop;
394 of_node_put(np);
395 }
396 return val;
397}
398
399static void mpc512x_clk_preset_data(void)
400{
401 size_t i;
402
403 for (i = 0; i < ARRAY_SIZE(clks); i++)
404 clks[i] = ERR_PTR(-ENODEV);
405}
406
407/*
408 * - receives the "bus frequency" from the caller (that's the IPS clock
409 * rate, the historical source of clock information)
410 * - fetches the system PLL multiplier and divider values as well as the
411 * IPS divider value from hardware
412 * - determines the REF clock rate either from the XTAL/OSC spec (if
413 * there is a device tree node describing the oscillator) or from the
414 * IPS bus clock (supported for backwards compatibility, such that
415 * setups without XTAL/OSC specs keep working)
416 * - creates the "ref" clock item in the clock tree, such that
417 * subsequent code can create the remainder of the hierarchy (REF ->
418 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
419 * values
420 */
421static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq,
422 int *sys_mul, int *sys_div,
423 int *ips_div)
424{
425 struct clk *osc_clk;
426 int calc_freq;
427
428 /* fetch mul/div factors from the hardware */
429 *sys_mul = get_spmf_mult();
430 *sys_mul *= 2; /* compensate for the fractional divider */
431 *sys_div = get_sys_div_x2();
432 *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
433
434 /* lookup the oscillator clock for its rate */
435 osc_clk = of_clk_get_by_name(np, "osc");
436
437 /*
438 * either descend from OSC to REF (and in bypassing verify the
439 * IPS rate), or backtrack from IPS and multiplier values that
440 * were fetched from hardware to REF and thus to the OSC value
441 *
442 * in either case the REF clock gets created here and the
443 * remainder of the clock tree can get spanned from there
444 */
445 if (!IS_ERR(osc_clk)) {
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
448 calc_freq *= *sys_mul;
449 calc_freq /= *sys_div;
450 calc_freq /= 2;
451 calc_freq /= *ips_div;
452 if (bus_freq && calc_freq != bus_freq)
453 pr_warn("calc rate %d != OF spec %d\n",
454 calc_freq, bus_freq);
455 } else {
456 calc_freq = bus_freq; /* start with IPS */
457 calc_freq *= *ips_div; /* IPS -> CSB */
458 calc_freq *= 2; /* CSB -> SYS */
459 calc_freq *= *sys_div; /* SYS -> PLL out */
460 calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
462 }
463}
464
465/* MCLK helpers {{{ */
466
467/*
468 * helper code for the MCLK subtree setup
469 *
470 * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
471 * suggests that all instances of the "PSC clock generation" are equal,
472 * and that one might re-use the PSC setup for MSCAN clock generation
473 * (section 5.2.5) as well, at least the logic if not the data for
474 * description
475 *
476 * the details (starting at page 5-20) show differences in the specific
477 * inputs of the first mux stage ("can clk in", "spdif tx"), and the
478 * factual non-availability of the second mux stage (it's present yet
479 * only one input is valid)
480 *
481 * the MSCAN clock related registers (starting at page 5-35) all
482 * reference "spdif clk" at the first mux stage and don't mention any
483 * "can clk" at all, which somehow is unexpected
484 *
485 * TODO re-check the document, and clarify whether the RM is correct in
486 * the overview or in the details, and whether the difference is a
487 * clipboard induced error or results from chip revisions
488 *
489 * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
490 * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
491 * first a doc update is required which better reflects reality in the
492 * SoC before the implementation should follow while no questions remain
493 */
494
495/*
496 * note that this declaration raises a checkpatch warning, but
497 * it's the very data type dictated by <linux/clk-provider.h>,
498 * "fixing" this warning will break compilation
499 */
500static const char *parent_names_mux0_spdif[] = {
501 "sys", "ref", "psc-mclk-in", "spdif-tx",
502};
503
504static const char *parent_names_mux0_canin[] = {
505 "sys", "ref", "psc-mclk-in", "can-clk-in",
506};
507
508enum mclk_type {
509 MCLK_TYPE_PSC,
510 MCLK_TYPE_MSCAN,
511 MCLK_TYPE_SPDIF,
512 MCLK_TYPE_OUTCLK,
513};
514
515struct mclk_setup_data {
516 enum mclk_type type;
517 bool has_mclk1;
518 const char *name_mux0;
519 const char *name_en0;
520 const char *name_div0;
521 const char *parent_names_mux1[2];
522 const char *name_mclk;
523};
524
525#define MCLK_SETUP_DATA_PSC(id) { \
526 MCLK_TYPE_PSC, 0, \
527 "psc" #id "-mux0", \
528 "psc" #id "-en0", \
529 "psc" #id "_mclk_div", \
530 { "psc" #id "_mclk_div", "dummy", }, \
531 "psc" #id "_mclk", \
532}
533
534#define MCLK_SETUP_DATA_MSCAN(id) { \
535 MCLK_TYPE_MSCAN, 0, \
536 "mscan" #id "-mux0", \
537 "mscan" #id "-en0", \
538 "mscan" #id "_mclk_div", \
539 { "mscan" #id "_mclk_div", "dummy", }, \
540 "mscan" #id "_mclk", \
541}
542
543#define MCLK_SETUP_DATA_SPDIF { \
544 MCLK_TYPE_SPDIF, 1, \
545 "spdif-mux0", \
546 "spdif-en0", \
547 "spdif_mclk_div", \
548 { "spdif_mclk_div", "spdif-rx", }, \
549 "spdif_mclk", \
550}
551
552#define MCLK_SETUP_DATA_OUTCLK(id) { \
553 MCLK_TYPE_OUTCLK, 0, \
554 "out" #id "-mux0", \
555 "out" #id "-en0", \
556 "out" #id "_mclk_div", \
557 { "out" #id "_mclk_div", "dummy", }, \
558 "out" #id "_clk", \
559}
560
561static struct mclk_setup_data mclk_psc_data[] = {
562 MCLK_SETUP_DATA_PSC(0),
563 MCLK_SETUP_DATA_PSC(1),
564 MCLK_SETUP_DATA_PSC(2),
565 MCLK_SETUP_DATA_PSC(3),
566 MCLK_SETUP_DATA_PSC(4),
567 MCLK_SETUP_DATA_PSC(5),
568 MCLK_SETUP_DATA_PSC(6),
569 MCLK_SETUP_DATA_PSC(7),
570 MCLK_SETUP_DATA_PSC(8),
571 MCLK_SETUP_DATA_PSC(9),
572 MCLK_SETUP_DATA_PSC(10),
573 MCLK_SETUP_DATA_PSC(11),
574};
575
576static struct mclk_setup_data mclk_mscan_data[] = {
577 MCLK_SETUP_DATA_MSCAN(0),
578 MCLK_SETUP_DATA_MSCAN(1),
579 MCLK_SETUP_DATA_MSCAN(2),
580 MCLK_SETUP_DATA_MSCAN(3),
581};
582
583static struct mclk_setup_data mclk_spdif_data[] = {
584 MCLK_SETUP_DATA_SPDIF,
585};
586
587static struct mclk_setup_data mclk_outclk_data[] = {
588 MCLK_SETUP_DATA_OUTCLK(0),
589 MCLK_SETUP_DATA_OUTCLK(1),
590 MCLK_SETUP_DATA_OUTCLK(2),
591 MCLK_SETUP_DATA_OUTCLK(3),
592};
593
594/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
595static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx)
596{
597 size_t clks_idx_pub, clks_idx_int;
598 u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
599 int div;
600
601 /* derive a few parameters from the component type and index */
602 switch (entry->type) {
603 case MCLK_TYPE_PSC:
604 clks_idx_pub = MPC512x_CLK_PSC0_MCLK + idx;
605 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
606 + (idx) * MCLK_MAX_IDX;
607 mccr_reg = &clkregs->psc_ccr[idx];
608 break;
609 case MCLK_TYPE_MSCAN:
610 clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + idx;
611 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
612 + (NR_PSCS + idx) * MCLK_MAX_IDX;
613 mccr_reg = &clkregs->mscan_ccr[idx];
614 break;
615 case MCLK_TYPE_SPDIF:
616 clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
617 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
618 + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
619 mccr_reg = &clkregs->spccr;
620 break;
621 case MCLK_TYPE_OUTCLK:
622 clks_idx_pub = MPC512x_CLK_OUT0_CLK + idx;
623 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
624 + (NR_PSCS + NR_MSCANS + NR_SPDIFS + idx)
625 * MCLK_MAX_IDX;
626 mccr_reg = &clkregs->out_ccr[idx];
627 break;
628 default:
629 return;
630 }
631
632 /*
633 * this was grabbed from the PPC_CLOCK implementation, which
634 * enforced a specific MCLK divider while the clock was gated
635 * during setup (that's a documented hardware requirement)
636 *
637 * the PPC_CLOCK implementation might even have violated the
638 * "MCLK <= IPS" constraint, the fixed divider value of 1
639 * results in a divider of 2 and thus MCLK = SYS/2 which equals
640 * CSB which is greater than IPS; the serial port setup may have
641 * adjusted the divider which the clock setup might have left in
642 * an undesirable state
643 *
644 * initial setup is:
645 * - MCLK 0 from SYS
646 * - MCLK DIV such to not exceed the IPS clock
647 * - MCLK 0 enabled
648 * - MCLK 1 from MCLK DIV
649 */
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]);
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
652 out_be32(mccr_reg, (0 << 16));
653 out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
654 out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
655
656 /*
657 * create the 'struct clk' items of the MCLK's clock subtree
658 *
659 * note that by design we always create all nodes and won't take
660 * shortcuts here, because
661 * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
662 * selectable inputs to the CFM while those who "actually use"
663 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
664 * for their bitrate
665 * - in the absence of "aliases" for clocks we need to create
666 * individial 'struct clk' items for whatever might get
667 * referenced or looked up, even if several of those items are
668 * identical from the logical POV (their rate value)
669 * - for easier future maintenance and for better reflection of
670 * the SoC's documentation, it appears appropriate to generate
671 * clock items even for those muxers which actually are NOPs
672 * (those with two inputs of which one is reserved)
673 */
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
675 entry->name_mux0,
676 soc_has_mclk_mux0_canin()
677 ? &parent_names_mux0_canin[0]
678 : &parent_names_mux0_spdif[0],
679 ARRAY_SIZE(parent_names_mux0_spdif),
680 mccr_reg, 14, 2);
681 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
682 entry->name_en0, entry->name_mux0,
683 mccr_reg, 16);
684 clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
685 entry->name_div0,
686 entry->name_en0, CLK_SET_RATE_GATE,
687 mccr_reg, 17, 15, 0);
688 if (entry->has_mclk1) {
689 clks[clks_idx_pub] = mpc512x_clk_muxed(
690 entry->name_mclk,
691 &entry->parent_names_mux1[0],
692 ARRAY_SIZE(entry->parent_names_mux1),
693 mccr_reg, 7, 1);
694 } else {
695 clks[clks_idx_pub] = mpc512x_clk_factor(
696 entry->name_mclk,
697 entry->parent_names_mux1[0],
698 1, 1);
699 }
700}
701
702/* }}} MCLK helpers */
703
704static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq)
705{
706 int sys_mul, sys_div, ips_div;
707 int mul, div;
708 size_t mclk_idx;
709 int freq;
710
711 /*
712 * developer's notes:
713 * - consider whether to handle clocks which have both gates and
714 * dividers via intermediates or by means of composites
715 * - fractional dividers appear to not map well to composites
716 * since they can be seen as a fixed multiplier and an
717 * adjustable divider, while composites can only combine at
718 * most one of a mux, div, and gate each into one 'struct clk'
719 * item
720 * - PSC/MSCAN/SPDIF clock generation OTOH already is very
721 * specific and cannot get mapped to componsites (at least not
722 * a single one, maybe two of them, but then some of these
723 * intermediate clock signals get referenced elsewhere (e.g.
724 * in the clock frequency measurement, CFM) and thus need
725 * publicly available names
726 * - the current source layout appropriately reflects the
727 * hardware setup, and it works, so it's questionable whether
728 * further changes will result in big enough a benefit
729 */
730
731 /* regardless of whether XTAL/OSC exists, have REF created */
732 mpc512x_clk_setup_ref_clock(np, busfreq, &sys_mul, &sys_div, &ips_div);
733
734 /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
735 clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
736 sys_mul, sys_div);
737 clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
738 clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
739 &clkregs->scfr1, 23, 3,
740 divtab_2346);
741 /* now setup anything below SYS and CSB and IPS */
742
743 clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
744
745 /*
746 * the Reference Manual discusses that for SDHC only even divide
747 * ratios are supported because clock domain synchronization
748 * between 'per' and 'ipg' is broken;
749 * keep the divider's bit 0 cleared (per reset value), and only
750 * allow to setup the divider's bits 7:1, which results in that
751 * only even divide ratios can get configured upon rate changes;
752 * keep the "x4" name because this bit shift hack is an internal
753 * implementation detail, the "fractional divider with quarters"
754 * semantics remains
755 */
756 clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1);
757 clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
758 &clkregs->scfr2, 1, 7,
759 CLK_DIVIDER_ONE_BASED);
760 if (soc_has_sdhc2()) {
761 clks[MPC512x_CLK_SDHC2_UG] = mpc512x_clk_divider(
762 "sdhc2-ug", "sdhc-x4", 0, &clkregs->scfr2,
763 9, 7, CLK_DIVIDER_ONE_BASED);
764 }
765
766 clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
767 clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
768 &clkregs->scfr1, 0, 8,
769 CLK_DIVIDER_ONE_BASED);
770
771 /*
772 * the "power architecture PLL" was setup from data which was
773 * sampled from the reset config word, at this point in time the
774 * configuration can be considered fixed and read only (i.e. no
775 * longer adjustable, or no longer in need of adjustment), which
776 * is why we don't register a PLL here but assume fixed factors
777 */
778 mul = get_cpmf_mult_x2();
779 div = 2; /* compensate for the fractional factor */
780 clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
781
782 if (soc_has_mbx()) {
783 clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor(
784 "mbx-bus-ug", "csb", 1, 2);
785 clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable(
786 "mbx-ug", "mbx-bus-ug", &clkregs->scfr1,
787 14, 3, divtab_1234);
788 clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor(
789 "mbx-3d-ug", "mbx-ug", 1, 1);
790 }
791 if (soc_has_pci()) {
792 clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable(
793 "pci-ug", "csb", &clkregs->scfr1,
794 20, 3, divtab_2346);
795 }
796 if (soc_has_nfc_5125()) {
797 /*
798 * XXX TODO implement 5125 NFC clock setup logic,
799 * with high/low period counters in clkregs->scfr3,
800 * currently there are no users so it's ENOIMPL
801 */
802 clks[MPC512x_CLK_NFC_UG] = ERR_PTR(-ENOTSUPP);
803 } else {
804 clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable(
805 "nfc-ug", "ips", &clkregs->scfr1,
806 8, 3, divtab_1234);
807 }
808 clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
809 &clkregs->scfr1, 11, 3,
810 divtab_1234);
811
812 clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
813 &clkregs->sccr1, 30);
814 clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
815 &clkregs->sccr1, 29);
816 if (soc_has_pata()) {
817 clks[MPC512x_CLK_PATA] = mpc512x_clk_gated(
818 "pata", "ips", &clkregs->sccr1, 28);
819 }
820 /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */
821 for (mclk_idx = 0; mclk_idx < soc_max_pscnum(); mclk_idx++) {
822 char name[12];
823 snprintf(name, sizeof(name), "psc%d", mclk_idx);
824 clks[MPC512x_CLK_PSC0 + mclk_idx] = mpc512x_clk_gated(
825 name, "ips", &clkregs->sccr1, 27 - mclk_idx);
826 mpc512x_clk_setup_mclk(&mclk_psc_data[mclk_idx], mclk_idx);
827 }
828 clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
829 &clkregs->sccr1, 15);
830 if (soc_has_sata()) {
831 clks[MPC512x_CLK_SATA] = mpc512x_clk_gated(
832 "sata", "ips", &clkregs->sccr1, 14);
833 }
834 clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
835 &clkregs->sccr1, 13);
836 if (soc_has_pci()) {
837 clks[MPC512x_CLK_PCI] = mpc512x_clk_gated(
838 "pci", "pci-ug", &clkregs->sccr1, 11);
839 }
840 clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
841 &clkregs->sccr1, 10);
842 if (soc_has_fec2()) {
843 clks[MPC512x_CLK_FEC2] = mpc512x_clk_gated(
844 "fec2", "ips", &clkregs->sccr1, 9);
845 }
846
847 clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
848 &clkregs->sccr2, 31);
849 if (soc_has_axe()) {
850 clks[MPC512x_CLK_AXE] = mpc512x_clk_gated(
851 "axe", "csb", &clkregs->sccr2, 30);
852 }
853 clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
854 &clkregs->sccr2, 29);
855 clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
856 &clkregs->sccr2, 28);
857 clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
858 &clkregs->sccr2, 27);
859 clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
860 &clkregs->sccr2, 26);
861 /* MSCAN differs from PSC with just one gate for multiple components */
862 clks[MPC512x_CLK_BDLC] = mpc512x_clk_gated("bdlc", "ips",
863 &clkregs->sccr2, 25);
864 for (mclk_idx = 0; mclk_idx < ARRAY_SIZE(mclk_mscan_data); mclk_idx++)
865 mpc512x_clk_setup_mclk(&mclk_mscan_data[mclk_idx], mclk_idx);
866 clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
867 &clkregs->sccr2, 24);
868 /* there is only one SPDIF component, which shares MCLK support code */
869 if (soc_has_spdif()) {
870 clks[MPC512x_CLK_SPDIF] = mpc512x_clk_gated(
871 "spdif", "ips", &clkregs->sccr2, 23);
872 mpc512x_clk_setup_mclk(&mclk_spdif_data[0], 0);
873 }
874 if (soc_has_mbx()) {
875 clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated(
876 "mbx-bus", "mbx-bus-ug", &clkregs->sccr2, 22);
877 clks[MPC512x_CLK_MBX] = mpc512x_clk_gated(
878 "mbx", "mbx-ug", &clkregs->sccr2, 21);
879 clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated(
880 "mbx-3d", "mbx-3d-ug", &clkregs->sccr2, 20);
881 }
882 clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
883 &clkregs->sccr2, 19);
884 if (soc_has_viu()) {
885 clks[MPC512x_CLK_VIU] = mpc512x_clk_gated(
886 "viu", "csb", &clkregs->sccr2, 18);
887 }
888 if (soc_has_sdhc2()) {
889 clks[MPC512x_CLK_SDHC2] = mpc512x_clk_gated(
890 "sdhc-2", "sdhc2-ug", &clkregs->sccr2, 17);
891 }
892
893 if (soc_has_outclk()) {
894 size_t idx; /* used as mclk_idx, just to trim line length */
895 for (idx = 0; idx < ARRAY_SIZE(mclk_outclk_data); idx++)
896 mpc512x_clk_setup_mclk(&mclk_outclk_data[idx], idx);
897 }
898
899 /*
900 * externally provided clocks (when implemented in hardware,
901 * device tree may specify values which otherwise were unknown)
902 */
903 freq = get_freq_from_dt("psc_mclk_in");
904 if (!freq)
905 freq = 25000000;
906 clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
907 if (soc_has_mclk_mux0_canin()) {
908 freq = get_freq_from_dt("can_clk_in");
909 clks[MPC512x_CLK_CAN_CLK_IN] = mpc512x_clk_fixed(
910 "can_clk_in", freq);
911 } else {
912 freq = get_freq_from_dt("spdif_tx_in");
913 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
914 "spdif_tx_in", freq);
915 freq = get_freq_from_dt("spdif_rx_in");
916 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
917 "spdif_rx_in", freq);
918 }
919
920 /* fixed frequency for AC97, always 24.567MHz */
921 clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
922
923 /*
924 * pre-enable those "internal" clock items which never get
925 * claimed by any peripheral driver, to not have the clock
926 * subsystem disable them late at startup
927 */
928 clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
929 clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
930 clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
931 clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
932 clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
933 clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
934}
935
936/*
937 * registers the set of public clocks (those listed in the dt-bindings/
938 * header file) for OF lookups, keeps the intermediates private to us
939 */
940static void mpc5121_clk_register_of_provider(struct device_node *np)
941{
942 clk_data.clks = clks;
943 clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
944 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
945}
946
947/*
948 * temporary support for the period of time between introduction of CCF
949 * support and the adjustment of peripheral drivers to OF based lookups
950 */
951static void mpc5121_clk_provide_migration_support(void)
952{
953
954 /*
955 * pre-enable those clock items which are not yet appropriately
956 * acquired by their peripheral driver
957 *
958 * the PCI clock cannot get acquired by its peripheral driver,
959 * because for this platform the driver won't probe(), instead
960 * initialization is done from within the .setup_arch() routine
961 * at a point in time where the clock provider has not been
962 * setup yet and thus isn't available yet
963 *
964 * so we "pre-enable" the clock here, to not have the clock
965 * subsystem automatically disable this item in a late init call
966 *
967 * this PCI clock pre-enable workaround only applies when there
968 * are device tree nodes for PCI and thus the peripheral driver
969 * has attached to bridges, otherwise the PCI clock remains
970 * unused and so it gets disabled
971 */
972 clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
973 if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci"))
974 clk_prepare_enable(clks[MPC512x_CLK_PCI]);
975}
976
977/*
978 * those macros are not exactly pretty, but they encapsulate a lot
979 * of copy'n'paste heavy code which is even more ugly, and reduce
980 * the potential for inconsistencies in those many code copies
981 */
982#define FOR_NODES(compatname) \
983 for_each_compatible_node(np, NULL, compatname)
984
985#define NODE_PREP do { \
986 of_address_to_resource(np, 0, &res); \
987 snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \
988} while (0)
989
990#define NODE_CHK(clkname, clkitem, regnode, regflag) do { \
991 struct clk *clk; \
992 clk = of_clk_get_by_name(np, clkname); \
993 if (IS_ERR(clk)) { \
994 clk = clkitem; \
995 clk_register_clkdev(clk, clkname, devname); \
996 if (regnode) \
997 clk_register_clkdev(clk, clkname, np->name); \
998 did_register |= DID_REG_ ## regflag; \
999 pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \
1000 clkname, devname, clk); \
1001 } else { \
1002 clk_put(clk); \
1003 } \
1004} while (0)
1005
1006/*
1007 * register source code provided fallback results for clock lookups,
1008 * these get consulted when OF based clock lookup fails (that is in the
1009 * case of not yet adjusted device tree data, where clock related specs
1010 * are missing)
1011 */
1012static void mpc5121_clk_provide_backwards_compat(void)
1013{
1014 enum did_reg_flags {
1015 DID_REG_PSC = BIT(0),
1016 DID_REG_PSCFIFO = BIT(1),
1017 DID_REG_NFC = BIT(2),
1018 DID_REG_CAN = BIT(3),
1019 DID_REG_I2C = BIT(4),
1020 DID_REG_DIU = BIT(5),
1021 DID_REG_VIU = BIT(6),
1022 DID_REG_FEC = BIT(7),
1023 DID_REG_USB = BIT(8),
1024 DID_REG_PATA = BIT(9),
1025 };
1026
1027 int did_register;
1028 struct device_node *np;
1029 struct resource res;
1030 int idx;
1031 char devname[32];
1032
1033 did_register = 0;
1034
1035 FOR_NODES(mpc512x_select_psc_compat()) {
1036 NODE_PREP;
1037 idx = (res.start >> 8) & 0xf;
1038 NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC);
1039 NODE_CHK("mclk", clks[MPC512x_CLK_PSC0_MCLK + idx], 0, PSC);
1040 }
1041
1042 FOR_NODES("fsl,mpc5121-psc-fifo") {
1043 NODE_PREP;
1044 NODE_CHK("ipg", clks[MPC512x_CLK_PSC_FIFO], 1, PSCFIFO);
1045 }
1046
1047 FOR_NODES("fsl,mpc5121-nfc") {
1048 NODE_PREP;
1049 NODE_CHK("ipg", clks[MPC512x_CLK_NFC], 0, NFC);
1050 }
1051
1052 FOR_NODES("fsl,mpc5121-mscan") {
1053 NODE_PREP;
1054 idx = 0;
1055 idx += (res.start & 0x2000) ? 2 : 0;
1056 idx += (res.start & 0x0080) ? 1 : 0;
1057 NODE_CHK("ipg", clks[MPC512x_CLK_BDLC], 0, CAN);
1058 NODE_CHK("mclk", clks[MPC512x_CLK_MSCAN0_MCLK + idx], 0, CAN);
1059 }
1060
1061 /*
1062 * do register the 'ips', 'sys', and 'ref' names globally
1063 * instead of inside each individual CAN node, as there is no
1064 * potential for a name conflict (in contrast to 'ipg' and 'mclk')
1065 */
1066 if (did_register & DID_REG_CAN) {
1067 clk_register_clkdev(clks[MPC512x_CLK_IPS], "ips", NULL);
1068 clk_register_clkdev(clks[MPC512x_CLK_SYS], "sys", NULL);
1069 clk_register_clkdev(clks[MPC512x_CLK_REF], "ref", NULL);
1070 }
1071
1072 FOR_NODES("fsl,mpc5121-i2c") {
1073 NODE_PREP;
1074 NODE_CHK("ipg", clks[MPC512x_CLK_I2C], 0, I2C);
1075 }
1076
1077 /*
1078 * workaround for the fact that the I2C driver does an "anonymous"
1079 * lookup (NULL name spec, which yields the first clock spec) for
1080 * which we cannot register an alias -- a _global_ 'ipg' alias that
1081 * is not bound to any device name and returns the I2C clock item
1082 * is not a good idea
1083 *
1084 * so we have the lookup in the peripheral driver fail, which is
1085 * silent and non-fatal, and pre-enable the clock item here such
1086 * that register access is possible
1087 *
1088 * see commit b3bfce2b "i2c: mpc: cleanup clock API use" for
1089 * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this
1090 * workaround obsolete
1091 */
1092 if (did_register & DID_REG_I2C)
1093 clk_prepare_enable(clks[MPC512x_CLK_I2C]);
1094
1095 FOR_NODES("fsl,mpc5121-diu") {
1096 NODE_PREP;
1097 NODE_CHK("ipg", clks[MPC512x_CLK_DIU], 1, DIU);
1098 }
1099
1100 FOR_NODES("fsl,mpc5121-viu") {
1101 NODE_PREP;
1102 NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU);
1103 }
1104
1105 /*
1106 * note that 2771399a "fs_enet: cleanup clock API use" did use the
1107 * "per" string for the clock lookup in contrast to the "ipg" name
1108 * which most other nodes are using -- this is not a fatal thing
1109 * but just something to keep in mind when doing compatibility
1110 * registration, it's a non-issue with up-to-date device tree data
1111 */
1112 FOR_NODES("fsl,mpc5121-fec") {
1113 NODE_PREP;
1114 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
1115 }
1116 FOR_NODES("fsl,mpc5121-fec-mdio") {
1117 NODE_PREP;
1118 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
1119 }
1120 /*
1121 * MPC5125 has two FECs: FEC1 at 0x2800, FEC2 at 0x4800;
1122 * the clock items don't "form an array" since FEC2 was
1123 * added only later and was not allowed to shift all other
1124 * clock item indices, so the numbers aren't adjacent
1125 */
1126 FOR_NODES("fsl,mpc5125-fec") {
1127 NODE_PREP;
1128 if (res.start & 0x4000)
1129 idx = MPC512x_CLK_FEC2;
1130 else
1131 idx = MPC512x_CLK_FEC;
1132 NODE_CHK("per", clks[idx], 0, FEC);
1133 }
1134
1135 FOR_NODES("fsl,mpc5121-usb2-dr") {
1136 NODE_PREP;
1137 idx = (res.start & 0x4000) ? 1 : 0;
1138 NODE_CHK("ipg", clks[MPC512x_CLK_USB1 + idx], 0, USB);
1139 }
1140
1141 FOR_NODES("fsl,mpc5121-pata") {
1142 NODE_PREP;
1143 NODE_CHK("ipg", clks[MPC512x_CLK_PATA], 0, PATA);
1144 }
1145
1146 /*
1147 * try to collapse diagnostics into a single line of output yet
1148 * provide a full list of what is missing, to avoid noise in the
1149 * absence of up-to-date device tree data -- backwards
1150 * compatibility to old DTBs is a requirement, updates may be
1151 * desirable or preferrable but are not at all mandatory
1152 */
1153 if (did_register) {
1154 pr_notice("device tree lacks clock specs, adding fallbacks (0x%x,%s%s%s%s%s%s%s%s%s%s)\n",
1155 did_register,
1156 (did_register & DID_REG_PSC) ? " PSC" : "",
1157 (did_register & DID_REG_PSCFIFO) ? " PSCFIFO" : "",
1158 (did_register & DID_REG_NFC) ? " NFC" : "",
1159 (did_register & DID_REG_CAN) ? " CAN" : "",
1160 (did_register & DID_REG_I2C) ? " I2C" : "",
1161 (did_register & DID_REG_DIU) ? " DIU" : "",
1162 (did_register & DID_REG_VIU) ? " VIU" : "",
1163 (did_register & DID_REG_FEC) ? " FEC" : "",
1164 (did_register & DID_REG_USB) ? " USB" : "",
1165 (did_register & DID_REG_PATA) ? " PATA" : "");
1166 } else {
1167 pr_debug("device tree has clock specs, no fallbacks added\n");
1168 }
1169}
1170
1171int __init mpc5121_clk_init(void)
1172{
1173 struct device_node *clk_np;
1174 int busfreq;
1175
1176 /* map the clock control registers */
1177 clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
1178 if (!clk_np)
1179 return -ENODEV;
1180 clkregs = of_iomap(clk_np, 0);
1181 WARN_ON(!clkregs);
1182
1183 /* determine the SoC variant we run on */
1184 mpc512x_clk_determine_soc();
1185
1186 /* invalidate all not yet registered clock slots */
1187 mpc512x_clk_preset_data();
1188
1189 /*
1190 * have the device tree scanned for "fixed-clock" nodes (which
1191 * includes the oscillator node if the board's DT provides one)
1192 */
1193 of_clk_init(NULL);
1194
1195 /*
1196 * add a dummy clock for those situations where a clock spec is
1197 * required yet no real clock is involved
1198 */
1199 clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
1200
1201 /*
1202 * have all the real nodes in the clock tree populated from REF
1203 * down to all leaves, either starting from the OSC node or from
1204 * a REF root that was created from the IPS bus clock input
1205 */
1206 busfreq = get_freq_from_dt("bus-frequency");
1207 mpc512x_clk_setup_clock_tree(clk_np, busfreq);
1208
1209 /* register as an OF clock provider */
1210 mpc5121_clk_register_of_provider(clk_np);
1211
1212 /*
1213 * unbreak not yet adjusted peripheral drivers during migration
1214 * towards fully operational common clock support, and allow
1215 * operation in the absence of clock related device tree specs
1216 */
1217 mpc5121_clk_provide_migration_support();
1218 mpc5121_clk_provide_backwards_compat();
1219
1220 return 0;
1221}
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index fd8a37653417..000000000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
1/*
2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: John Rigby <jrigby@freescale.com>
5 *
6 * Implements the clk api defined in include/linux/clk.h
7 *
8 * Original based on linux/arch/arm/mach-integrator/clock.c
9 *
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/module.h>
22#include <linux/string.h>
23#include <linux/clk.h>
24#include <linux/mutex.h>
25#include <linux/io.h>
26
27#include <linux/of_address.h>
28#include <linux/of_platform.h>
29#include <asm/mpc5xxx.h>
30#include <asm/mpc5121.h>
31#include <asm/clk_interface.h>
32
33#include "mpc512x.h"
34
35#undef CLK_DEBUG
36
37static int clocks_initialized;
38
39#define CLK_HAS_RATE 0x1 /* has rate in MHz */
40#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
41
42struct clk {
43 struct list_head node;
44 char name[32];
45 int flags;
46 struct device *dev;
47 unsigned long rate;
48 struct module *owner;
49 void (*calc) (struct clk *);
50 struct clk *parent;
51 int reg, bit; /* CLK_HAS_CTRL */
52 int div_shift; /* only used by generic_div_clk_calc */
53};
54
55static LIST_HEAD(clocks);
56static DEFINE_MUTEX(clocks_mutex);
57
58static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
59{
60 struct clk *p, *clk = ERR_PTR(-ENOENT);
61 int dev_match;
62 int id_match;
63
64 if (dev == NULL || id == NULL)
65 return clk;
66
67 mutex_lock(&clocks_mutex);
68 list_for_each_entry(p, &clocks, node) {
69 dev_match = id_match = 0;
70
71 if (dev == p->dev)
72 dev_match++;
73 if (strcmp(id, p->name) == 0)
74 id_match++;
75 if ((dev_match || id_match) && try_module_get(p->owner)) {
76 clk = p;
77 break;
78 }
79 }
80 mutex_unlock(&clocks_mutex);
81
82 return clk;
83}
84
85#ifdef CLK_DEBUG
86static void dump_clocks(void)
87{
88 struct clk *p;
89
90 mutex_lock(&clocks_mutex);
91 printk(KERN_INFO "CLOCKS:\n");
92 list_for_each_entry(p, &clocks, node) {
93 pr_info(" %s=%ld", p->name, p->rate);
94 if (p->parent)
95 pr_cont(" %s=%ld", p->parent->name,
96 p->parent->rate);
97 if (p->flags & CLK_HAS_CTRL)
98 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
99 pr_cont("\n");
100 }
101 mutex_unlock(&clocks_mutex);
102}
103#define DEBUG_CLK_DUMP() dump_clocks()
104#else
105#define DEBUG_CLK_DUMP()
106#endif
107
108
109static void mpc5121_clk_put(struct clk *clk)
110{
111 module_put(clk->owner);
112}
113
114#define NRPSC 12
115
116struct mpc512x_clockctl {
117 u32 spmr; /* System PLL Mode Reg */
118 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
119 u32 scfr1; /* System Clk Freq Reg 1 */
120 u32 scfr2; /* System Clk Freq Reg 2 */
121 u32 reserved;
122 u32 bcr; /* Bread Crumb Reg */
123 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
124 u32 spccr; /* SPDIF Clk Ctrl Reg */
125 u32 cccr; /* CFM Clk Ctrl Reg */
126 u32 dccr; /* DIU Clk Cnfg Reg */
127};
128
129static struct mpc512x_clockctl __iomem *clockctl;
130
131static int mpc5121_clk_enable(struct clk *clk)
132{
133 unsigned int mask;
134
135 if (clk->flags & CLK_HAS_CTRL) {
136 mask = in_be32(&clockctl->sccr[clk->reg]);
137 mask |= 1 << clk->bit;
138 out_be32(&clockctl->sccr[clk->reg], mask);
139 }
140 return 0;
141}
142
143static void mpc5121_clk_disable(struct clk *clk)
144{
145 unsigned int mask;
146
147 if (clk->flags & CLK_HAS_CTRL) {
148 mask = in_be32(&clockctl->sccr[clk->reg]);
149 mask &= ~(1 << clk->bit);
150 out_be32(&clockctl->sccr[clk->reg], mask);
151 }
152}
153
154static unsigned long mpc5121_clk_get_rate(struct clk *clk)
155{
156 if (clk->flags & CLK_HAS_RATE)
157 return clk->rate;
158 else
159 return 0;
160}
161
162static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
163{
164 return rate;
165}
166
167static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
168{
169 return 0;
170}
171
172static int clk_register(struct clk *clk)
173{
174 mutex_lock(&clocks_mutex);
175 list_add(&clk->node, &clocks);
176 mutex_unlock(&clocks_mutex);
177 return 0;
178}
179
180static unsigned long spmf_mult(void)
181{
182 /*
183 * Convert spmf to multiplier
184 */
185 static int spmf_to_mult[] = {
186 68, 1, 12, 16,
187 20, 24, 28, 32,
188 36, 40, 44, 48,
189 52, 56, 60, 64
190 };
191 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
192 return spmf_to_mult[spmf];
193}
194
195static unsigned long sysdiv_div_x_2(void)
196{
197 /*
198 * Convert sysdiv to divisor x 2
199 * Some divisors have fractional parts so
200 * multiply by 2 then divide by this value
201 */
202 static int sysdiv_to_div_x_2[] = {
203 4, 5, 6, 7,
204 8, 9, 10, 14,
205 12, 16, 18, 22,
206 20, 24, 26, 30,
207 28, 32, 34, 38,
208 36, 40, 42, 46,
209 44, 48, 50, 54,
210 52, 56, 58, 62,
211 60, 64, 66,
212 };
213 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
214 return sysdiv_to_div_x_2[sysdiv];
215}
216
217static unsigned long ref_to_sys(unsigned long rate)
218{
219 rate *= spmf_mult();
220 rate *= 2;
221 rate /= sysdiv_div_x_2();
222
223 return rate;
224}
225
226static unsigned long sys_to_ref(unsigned long rate)
227{
228 rate *= sysdiv_div_x_2();
229 rate /= 2;
230 rate /= spmf_mult();
231
232 return rate;
233}
234
235static long ips_to_ref(unsigned long rate)
236{
237 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
238
239 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
240 rate *= 2; /* sys_clk = csb_clk * 2 */
241 return sys_to_ref(rate);
242}
243
244static unsigned long devtree_getfreq(char *clockname)
245{
246 struct device_node *np;
247 const unsigned int *prop;
248 unsigned int val = 0;
249
250 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
251 if (np) {
252 prop = of_get_property(np, clockname, NULL);
253 if (prop)
254 val = *prop;
255 of_node_put(np);
256 }
257 return val;
258}
259
260static void ref_clk_calc(struct clk *clk)
261{
262 unsigned long rate;
263
264 rate = devtree_getfreq("bus-frequency");
265 if (rate == 0) {
266 printk(KERN_ERR "No bus-frequency in dev tree\n");
267 clk->rate = 0;
268 return;
269 }
270 clk->rate = ips_to_ref(rate);
271}
272
273static struct clk ref_clk = {
274 .name = "ref_clk",
275 .calc = ref_clk_calc,
276};
277
278
279static void sys_clk_calc(struct clk *clk)
280{
281 clk->rate = ref_to_sys(ref_clk.rate);
282}
283
284static struct clk sys_clk = {
285 .name = "sys_clk",
286 .calc = sys_clk_calc,
287};
288
289static void diu_clk_calc(struct clk *clk)
290{
291 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
292 unsigned long rate;
293
294 rate = sys_clk.rate;
295
296 rate *= 2;
297 rate /= diudiv_x_2;
298
299 clk->rate = rate;
300}
301
302static void viu_clk_calc(struct clk *clk)
303{
304 unsigned long rate;
305
306 rate = sys_clk.rate;
307 rate /= 2;
308 clk->rate = rate;
309}
310
311static void half_clk_calc(struct clk *clk)
312{
313 clk->rate = clk->parent->rate / 2;
314}
315
316static void generic_div_clk_calc(struct clk *clk)
317{
318 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
319
320 clk->rate = clk->parent->rate / div;
321}
322
323static void unity_clk_calc(struct clk *clk)
324{
325 clk->rate = clk->parent->rate;
326}
327
328static struct clk csb_clk = {
329 .name = "csb_clk",
330 .calc = half_clk_calc,
331 .parent = &sys_clk,
332};
333
334static void e300_clk_calc(struct clk *clk)
335{
336 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
337 int ratex2 = clk->parent->rate * spmf;
338
339 clk->rate = ratex2 / 2;
340}
341
342static struct clk e300_clk = {
343 .name = "e300_clk",
344 .calc = e300_clk_calc,
345 .parent = &csb_clk,
346};
347
348static struct clk ips_clk = {
349 .name = "ips_clk",
350 .calc = generic_div_clk_calc,
351 .parent = &csb_clk,
352 .div_shift = 23,
353};
354
355/*
356 * Clocks controlled by SCCR1 (.reg = 0)
357 */
358static struct clk lpc_clk = {
359 .name = "lpc_clk",
360 .flags = CLK_HAS_CTRL,
361 .reg = 0,
362 .bit = 30,
363 .calc = generic_div_clk_calc,
364 .parent = &ips_clk,
365 .div_shift = 11,
366};
367
368static struct clk nfc_clk = {
369 .name = "nfc_clk",
370 .flags = CLK_HAS_CTRL,
371 .reg = 0,
372 .bit = 29,
373 .calc = generic_div_clk_calc,
374 .parent = &ips_clk,
375 .div_shift = 8,
376};
377
378static struct clk pata_clk = {
379 .name = "pata_clk",
380 .flags = CLK_HAS_CTRL,
381 .reg = 0,
382 .bit = 28,
383 .calc = unity_clk_calc,
384 .parent = &ips_clk,
385};
386
387/*
388 * PSC clocks (bits 27 - 16)
389 * are setup elsewhere
390 */
391
392static struct clk sata_clk = {
393 .name = "sata_clk",
394 .flags = CLK_HAS_CTRL,
395 .reg = 0,
396 .bit = 14,
397 .calc = unity_clk_calc,
398 .parent = &ips_clk,
399};
400
401static struct clk fec_clk = {
402 .name = "fec_clk",
403 .flags = CLK_HAS_CTRL,
404 .reg = 0,
405 .bit = 13,
406 .calc = unity_clk_calc,
407 .parent = &ips_clk,
408};
409
410static struct clk pci_clk = {
411 .name = "pci_clk",
412 .flags = CLK_HAS_CTRL,
413 .reg = 0,
414 .bit = 11,
415 .calc = generic_div_clk_calc,
416 .parent = &csb_clk,
417 .div_shift = 20,
418};
419
420/*
421 * Clocks controlled by SCCR2 (.reg = 1)
422 */
423static struct clk diu_clk = {
424 .name = "diu_clk",
425 .flags = CLK_HAS_CTRL,
426 .reg = 1,
427 .bit = 31,
428 .calc = diu_clk_calc,
429};
430
431static struct clk viu_clk = {
432 .name = "viu_clk",
433 .flags = CLK_HAS_CTRL,
434 .reg = 1,
435 .bit = 18,
436 .calc = viu_clk_calc,
437};
438
439static struct clk axe_clk = {
440 .name = "axe_clk",
441 .flags = CLK_HAS_CTRL,
442 .reg = 1,
443 .bit = 30,
444 .calc = unity_clk_calc,
445 .parent = &csb_clk,
446};
447
448static struct clk usb1_clk = {
449 .name = "usb1_clk",
450 .flags = CLK_HAS_CTRL,
451 .reg = 1,
452 .bit = 28,
453 .calc = unity_clk_calc,
454 .parent = &csb_clk,
455};
456
457static struct clk usb2_clk = {
458 .name = "usb2_clk",
459 .flags = CLK_HAS_CTRL,
460 .reg = 1,
461 .bit = 27,
462 .calc = unity_clk_calc,
463 .parent = &csb_clk,
464};
465
466static struct clk i2c_clk = {
467 .name = "i2c_clk",
468 .flags = CLK_HAS_CTRL,
469 .reg = 1,
470 .bit = 26,
471 .calc = unity_clk_calc,
472 .parent = &ips_clk,
473};
474
475static struct clk mscan_clk = {
476 .name = "mscan_clk",
477 .flags = CLK_HAS_CTRL,
478 .reg = 1,
479 .bit = 25,
480 .calc = unity_clk_calc,
481 .parent = &ips_clk,
482};
483
484static struct clk sdhc_clk = {
485 .name = "sdhc_clk",
486 .flags = CLK_HAS_CTRL,
487 .reg = 1,
488 .bit = 24,
489 .calc = unity_clk_calc,
490 .parent = &ips_clk,
491};
492
493static struct clk mbx_bus_clk = {
494 .name = "mbx_bus_clk",
495 .flags = CLK_HAS_CTRL,
496 .reg = 1,
497 .bit = 22,
498 .calc = half_clk_calc,
499 .parent = &csb_clk,
500};
501
502static struct clk mbx_clk = {
503 .name = "mbx_clk",
504 .flags = CLK_HAS_CTRL,
505 .reg = 1,
506 .bit = 21,
507 .calc = unity_clk_calc,
508 .parent = &csb_clk,
509};
510
511static struct clk mbx_3d_clk = {
512 .name = "mbx_3d_clk",
513 .flags = CLK_HAS_CTRL,
514 .reg = 1,
515 .bit = 20,
516 .calc = generic_div_clk_calc,
517 .parent = &mbx_bus_clk,
518 .div_shift = 14,
519};
520
521static void psc_mclk_in_calc(struct clk *clk)
522{
523 clk->rate = devtree_getfreq("psc_mclk_in");
524 if (!clk->rate)
525 clk->rate = 25000000;
526}
527
528static struct clk psc_mclk_in = {
529 .name = "psc_mclk_in",
530 .calc = psc_mclk_in_calc,
531};
532
533static struct clk spdif_txclk = {
534 .name = "spdif_txclk",
535 .flags = CLK_HAS_CTRL,
536 .reg = 1,
537 .bit = 23,
538};
539
540static struct clk spdif_rxclk = {
541 .name = "spdif_rxclk",
542 .flags = CLK_HAS_CTRL,
543 .reg = 1,
544 .bit = 23,
545};
546
547static void ac97_clk_calc(struct clk *clk)
548{
549 /* ac97 bit clock is always 24.567 MHz */
550 clk->rate = 24567000;
551}
552
553static struct clk ac97_clk = {
554 .name = "ac97_clk_in",
555 .calc = ac97_clk_calc,
556};
557
558static struct clk *rate_clks[] = {
559 &ref_clk,
560 &sys_clk,
561 &diu_clk,
562 &viu_clk,
563 &csb_clk,
564 &e300_clk,
565 &ips_clk,
566 &fec_clk,
567 &sata_clk,
568 &pata_clk,
569 &nfc_clk,
570 &lpc_clk,
571 &mbx_bus_clk,
572 &mbx_clk,
573 &mbx_3d_clk,
574 &axe_clk,
575 &usb1_clk,
576 &usb2_clk,
577 &i2c_clk,
578 &mscan_clk,
579 &sdhc_clk,
580 &pci_clk,
581 &psc_mclk_in,
582 &spdif_txclk,
583 &spdif_rxclk,
584 &ac97_clk,
585 NULL
586};
587
588static void rate_clk_init(struct clk *clk)
589{
590 if (clk->calc) {
591 clk->calc(clk);
592 clk->flags |= CLK_HAS_RATE;
593 clk_register(clk);
594 } else {
595 printk(KERN_WARNING
596 "Could not initialize clk %s without a calc routine\n",
597 clk->name);
598 }
599}
600
601static void rate_clks_init(void)
602{
603 struct clk **cpp, *clk;
604
605 cpp = rate_clks;
606 while ((clk = *cpp++))
607 rate_clk_init(clk);
608}
609
610/*
611 * There are two clk enable registers with 32 enable bits each
612 * psc clocks and device clocks are all stored in dev_clks
613 */
614static struct clk dev_clks[2][32];
615
616/*
617 * Given a psc number return the dev_clk
618 * associated with it
619 */
620static struct clk *psc_dev_clk(int pscnum)
621{
622 int reg, bit;
623 struct clk *clk;
624
625 reg = 0;
626 bit = 27 - pscnum;
627
628 clk = &dev_clks[reg][bit];
629 clk->reg = 0;
630 clk->bit = bit;
631 return clk;
632}
633
634/*
635 * PSC clock rate calculation
636 */
637static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
638{
639 unsigned long mclk_src = sys_clk.rate;
640 unsigned long mclk_div;
641
642 /*
643 * Can only change value of mclk divider
644 * when the divider is disabled.
645 *
646 * Zero is not a valid divider so minimum
647 * divider is 1
648 *
649 * disable/set divider/enable
650 */
651 out_be32(&clockctl->pccr[pscnum], 0);
652 out_be32(&clockctl->pccr[pscnum], 0x00020000);
653 out_be32(&clockctl->pccr[pscnum], 0x00030000);
654
655 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
656 clk->rate = spdif_rxclk.rate;
657 return;
658 }
659
660 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
661 case 0:
662 mclk_src = sys_clk.rate;
663 break;
664 case 1:
665 mclk_src = ref_clk.rate;
666 break;
667 case 2:
668 mclk_src = psc_mclk_in.rate;
669 break;
670 case 3:
671 mclk_src = spdif_txclk.rate;
672 break;
673 }
674
675 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
676 clk->rate = mclk_src / mclk_div;
677}
678
679/*
680 * Find all psc nodes in device tree and assign a clock
681 * with name "psc%d_mclk" and dev pointing at the device
682 * returned from of_find_device_by_node
683 */
684static void psc_clks_init(void)
685{
686 struct device_node *np;
687 struct platform_device *ofdev;
688 u32 reg;
689 const char *psc_compat;
690
691 psc_compat = mpc512x_select_psc_compat();
692 if (!psc_compat)
693 return;
694
695 for_each_compatible_node(np, NULL, psc_compat) {
696 if (!of_property_read_u32(np, "reg", &reg)) {
697 int pscnum = (reg & 0xf00) >> 8;
698 struct clk *clk = psc_dev_clk(pscnum);
699
700 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
701 ofdev = of_find_device_by_node(np);
702 clk->dev = &ofdev->dev;
703 /*
704 * AC97 is special rate clock does
705 * not go through normal path
706 */
707 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
708 clk->rate = ac97_clk.rate;
709 else
710 psc_calc_rate(clk, pscnum, np);
711 sprintf(clk->name, "psc%d_mclk", pscnum);
712 clk_register(clk);
713 clk_enable(clk);
714 }
715 }
716}
717
718static struct clk_interface mpc5121_clk_functions = {
719 .clk_get = mpc5121_clk_get,
720 .clk_enable = mpc5121_clk_enable,
721 .clk_disable = mpc5121_clk_disable,
722 .clk_get_rate = mpc5121_clk_get_rate,
723 .clk_put = mpc5121_clk_put,
724 .clk_round_rate = mpc5121_clk_round_rate,
725 .clk_set_rate = mpc5121_clk_set_rate,
726 .clk_set_parent = NULL,
727 .clk_get_parent = NULL,
728};
729
730int __init mpc5121_clk_init(void)
731{
732 struct device_node *np;
733
734 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
735 if (np) {
736 clockctl = of_iomap(np, 0);
737 of_node_put(np);
738 }
739
740 if (!clockctl) {
741 printk(KERN_ERR "Could not map clock control registers\n");
742 return 0;
743 }
744
745 rate_clks_init();
746 psc_clks_init();
747
748 /* leave clockctl mapped forever */
749 /*iounmap(clockctl); */
750 DEBUG_CLK_DUMP();
751 clocks_initialized++;
752 clk_functions = mpc5121_clk_functions;
753 return 0;
754}
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 36b5652aada2..adb95f03d4d4 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15#include <linux/clk.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/irq.h> 18#include <linux/irq.h>
@@ -68,98 +69,112 @@ struct fsl_diu_shared_fb {
68 bool in_use; 69 bool in_use;
69}; 70};
70 71
71#define DIU_DIV_MASK 0x000000ff 72/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
72static void mpc512x_set_pixel_clock(unsigned int pixclock) 73static void mpc512x_set_pixel_clock(unsigned int pixclock)
73{ 74{
74 unsigned long bestval, bestfreq, speed, busfreq;
75 unsigned long minpixclock, maxpixclock, pixval;
76 struct mpc512x_ccm __iomem *ccm;
77 struct device_node *np; 75 struct device_node *np;
78 u32 temp; 76 struct clk *clk_diu;
79 long err; 77 unsigned long epsilon, minpixclock, maxpixclock;
80 int i; 78 unsigned long offset, want, got, delta;
81 79
82 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock"); 80 /* lookup and enable the DIU clock */
81 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
83 if (!np) { 82 if (!np) {
84 pr_err("Can't find clock control module.\n"); 83 pr_err("Could not find DIU device tree node.\n");
85 return; 84 return;
86 } 85 }
87 86 clk_diu = of_clk_get(np, 0);
88 ccm = of_iomap(np, 0); 87 if (IS_ERR(clk_diu)) {
88 /* backwards compat with device trees that lack clock specs */
89 clk_diu = clk_get_sys(np->name, "ipg");
90 }
89 of_node_put(np); 91 of_node_put(np);
90 if (!ccm) { 92 if (IS_ERR(clk_diu)) {
91 pr_err("Can't map clock control module reg.\n"); 93 pr_err("Could not lookup DIU clock.\n");
92 return; 94 return;
93 } 95 }
94 96 if (clk_prepare_enable(clk_diu)) {
95 np = of_find_node_by_type(NULL, "cpu"); 97 pr_err("Could not enable DIU clock.\n");
96 if (np) {
97 const unsigned int *prop =
98 of_get_property(np, "bus-frequency", NULL);
99
100 of_node_put(np);
101 if (prop) {
102 busfreq = *prop;
103 } else {
104 pr_err("Can't get bus-frequency property\n");
105 return;
106 }
107 } else {
108 pr_err("Can't find 'cpu' node.\n");
109 return; 98 return;
110 } 99 }
111 100
112 /* Pixel Clock configuration */ 101 /*
113 pr_debug("DIU: Bus Frequency = %lu\n", busfreq); 102 * convert the picoseconds spec into the desired clock rate,
114 speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */ 103 * determine the acceptable clock range for the monitor (+/- 5%),
115 104 * do the calculation in steps to avoid integer overflow
116 /* Calculate the pixel clock with the smallest error */ 105 */
117 /* calculate the following in steps to avoid overflow */ 106 pr_debug("DIU pixclock in ps - %u\n", pixclock);
118 pr_debug("DIU pixclock in ps - %d\n", pixclock); 107 pixclock = (1000000000 / pixclock) * 1000;
119 temp = (1000000000 / pixclock) * 1000; 108 pr_debug("DIU pixclock freq - %u\n", pixclock);
120 pixclock = temp; 109 epsilon = pixclock / 20; /* pixclock * 0.05 */
121 pr_debug("DIU pixclock freq - %u\n", pixclock); 110 pr_debug("DIU deviation - %lu\n", epsilon);
122 111 minpixclock = pixclock - epsilon;
123 temp = temp / 20; /* pixclock * 0.05 */ 112 maxpixclock = pixclock + epsilon;
124 pr_debug("deviation = %d\n", temp); 113 pr_debug("DIU minpixclock - %lu\n", minpixclock);
125 minpixclock = pixclock - temp; 114 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
126 maxpixclock = pixclock + temp; 115
127 pr_debug("DIU minpixclock - %lu\n", minpixclock); 116 /*
128 pr_debug("DIU maxpixclock - %lu\n", maxpixclock); 117 * check whether the DIU supports the desired pixel clock
129 pixval = speed/pixclock; 118 *
130 pr_debug("DIU pixval = %lu\n", pixval); 119 * - simply request the desired clock and see what the
131 120 * platform's clock driver will make of it, assuming that it
132 err = LONG_MAX; 121 * will setup the best approximation of the requested value
133 bestval = pixval; 122 * - try other candidate frequencies in the order of decreasing
134 pr_debug("DIU bestval = %lu\n", bestval); 123 * preference (i.e. with increasing distance from the desired
135 124 * pixel clock, and checking the lower frequency before the
136 bestfreq = 0; 125 * higher frequency to not overload the hardware) until the
137 for (i = -1; i <= 1; i++) { 126 * first match is found -- any potential subsequent match
138 temp = speed / (pixval+i); 127 * would only be as good as the former match or typically
139 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n", 128 * would be less preferrable
140 i, pixval, temp); 129 *
141 if ((temp < minpixclock) || (temp > maxpixclock)) 130 * the offset increment of pixelclock divided by 64 is an
142 pr_debug("DIU exceeds monitor range (%lu to %lu)\n", 131 * arbitrary choice -- it's simple to calculate, in the typical
143 minpixclock, maxpixclock); 132 * case we expect the first check to succeed already, in the
144 else if (abs(temp - pixclock) < err) { 133 * worst case seven frequencies get tested (the exact center and
145 pr_debug("Entered the else if block %d\n", i); 134 * three more values each to the left and to the right) before
146 err = abs(temp - pixclock); 135 * the 5% tolerance window is exceeded, resulting in fast enough
147 bestval = pixval + i; 136 * execution yet high enough probability of finding a suitable
148 bestfreq = temp; 137 * value, while the error rate will be in the order of single
149 } 138 * percents
139 */
140 for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
141 want = pixclock - offset;
142 pr_debug("DIU checking clock - %lu\n", want);
143 clk_set_rate(clk_diu, want);
144 got = clk_get_rate(clk_diu);
145 delta = abs(pixclock - got);
146 if (delta < epsilon)
147 break;
148 if (!offset)
149 continue;
150 want = pixclock + offset;
151 pr_debug("DIU checking clock - %lu\n", want);
152 clk_set_rate(clk_diu, want);
153 got = clk_get_rate(clk_diu);
154 delta = abs(pixclock - got);
155 if (delta < epsilon)
156 break;
150 } 157 }
158 if (offset <= epsilon) {
159 pr_debug("DIU clock accepted - %lu\n", want);
160 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
161 pixclock, got, delta, epsilon);
162 return;
163 }
164 pr_warn("DIU pixclock auto search unsuccessful\n");
151 165
152 pr_debug("DIU chose = %lx\n", bestval); 166 /*
153 pr_debug("DIU error = %ld\n NomPixClk ", err); 167 * what is the most appropriate action to take when the search
154 pr_debug("DIU: Best Freq = %lx\n", bestfreq); 168 * for an available pixel clock which is acceptable to the
155 /* Modify DIU_DIV in CCM SCFR1 */ 169 * monitor has failed? disable the DIU (clock) or just provide
156 temp = in_be32(&ccm->scfr1); 170 * a "best effort"? we go with the latter
157 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp); 171 */
158 temp &= ~DIU_DIV_MASK; 172 pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
159 temp |= (bestval & DIU_DIV_MASK); 173 clk_set_rate(clk_diu, pixclock);
160 out_be32(&ccm->scfr1, temp); 174 got = clk_get_rate(clk_diu);
161 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp); 175 delta = abs(pixclock - got);
162 iounmap(ccm); 176 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
177 pixclock, got, delta, epsilon);
163} 178}
164 179
165static enum fsl_diu_monitor_port 180static enum fsl_diu_monitor_port
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index af54174801f7..b625a2c6f4f2 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -1,7 +1,7 @@
1config PPC_MPC52xx 1config PPC_MPC52xx
2 bool "52xx-based boards" 2 bool "52xx-based boards"
3 depends on 6xx 3 depends on 6xx
4 select PPC_CLOCK 4 select COMMON_CLK
5 select PPC_PCI_CHOICE 5 select PPC_PCI_CHOICE
6 6
7config PPC_MPC5200_SIMPLE 7config PPC_MPC5200_SIMPLE
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index a932feb2901c..21166f65c97c 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -26,6 +26,7 @@
26#include <linux/of_fdt.h> 26#include <linux/of_fdt.h>
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/bug.h> 28#include <linux/bug.h>
29#include <linux/cpuidle.h>
29 30
30#include <asm/machdep.h> 31#include <asm/machdep.h>
31#include <asm/firmware.h> 32#include <asm/firmware.h>
@@ -216,6 +217,16 @@ static int __init pnv_probe(void)
216 return 1; 217 return 1;
217} 218}
218 219
220void powernv_idle(void)
221{
222 /* Hook to cpuidle framework if available, else
223 * call on default platform idle code
224 */
225 if (cpuidle_idle_call()) {
226 power7_idle();
227 }
228}
229
219define_machine(powernv) { 230define_machine(powernv) {
220 .name = "PowerNV", 231 .name = "PowerNV",
221 .probe = pnv_probe, 232 .probe = pnv_probe,
@@ -225,7 +236,7 @@ define_machine(powernv) {
225 .show_cpuinfo = pnv_show_cpuinfo, 236 .show_cpuinfo = pnv_show_cpuinfo,
226 .progress = pnv_progress, 237 .progress = pnv_progress,
227 .machine_shutdown = pnv_shutdown, 238 .machine_shutdown = pnv_shutdown,
228 .power_save = power7_idle, 239 .power_save = powernv_idle,
229 .calibrate_decr = generic_calibrate_decr, 240 .calibrate_decr = generic_calibrate_decr,
230#ifdef CONFIG_KEXEC 241#ifdef CONFIG_KEXEC
231 .kexec_cpu_down = pnv_kexec_cpu_down, 242 .kexec_cpu_down = pnv_kexec_cpu_down,
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index e66643250fee..37300f6ee244 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -119,12 +119,3 @@ config DTL
119 which are accessible through a debugfs file. 119 which are accessible through a debugfs file.
120 120
121 Say N if you are unsure. 121 Say N if you are unsure.
122
123config PSERIES_IDLE
124 bool "Cpuidle driver for pSeries platforms"
125 depends on CPU_IDLE
126 depends on PPC_PSERIES
127 default y
128 help
129 Select this option to enable processor idle state management
130 through cpuidle subsystem.
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index fbccac9cd2dc..03480796af9a 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_HCALL_STATS) += hvCall_inst.o
21obj-$(CONFIG_CMM) += cmm.o 21obj-$(CONFIG_CMM) += cmm.o
22obj-$(CONFIG_DTL) += dtl.o 22obj-$(CONFIG_DTL) += dtl.o
23obj-$(CONFIG_IO_EVENT_IRQ) += io_event_irq.o 23obj-$(CONFIG_IO_EVENT_IRQ) += io_event_irq.o
24obj-$(CONFIG_PSERIES_IDLE) += processor_idle.o
25obj-$(CONFIG_LPARCFG) += lparcfg.o 24obj-$(CONFIG_LPARCFG) += lparcfg.o
26 25
27ifeq ($(CONFIG_PPC_PSERIES),y) 26ifeq ($(CONFIG_PPC_PSERIES),y)
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
deleted file mode 100644
index 002d5b4112f2..000000000000
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * processor_idle - idle state cpuidle driver.
3 * Adapted from drivers/idle/intel_idle.c and
4 * drivers/acpi/processor_idle.c
5 *
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/moduleparam.h>
12#include <linux/cpuidle.h>
13#include <linux/cpu.h>
14#include <linux/notifier.h>
15
16#include <asm/paca.h>
17#include <asm/reg.h>
18#include <asm/machdep.h>
19#include <asm/firmware.h>
20#include <asm/plpar_wrappers.h>
21
22struct cpuidle_driver pseries_idle_driver = {
23 .name = "pseries_idle",
24 .owner = THIS_MODULE,
25};
26
27#define MAX_IDLE_STATE_COUNT 2
28
29static int max_idle_state = MAX_IDLE_STATE_COUNT - 1;
30static struct cpuidle_state *cpuidle_state_table;
31
32static inline void idle_loop_prolog(unsigned long *in_purr)
33{
34 *in_purr = mfspr(SPRN_PURR);
35 /*
36 * Indicate to the HV that we are idle. Now would be
37 * a good time to find other work to dispatch.
38 */
39 get_lppaca()->idle = 1;
40}
41
42static inline void idle_loop_epilog(unsigned long in_purr)
43{
44 u64 wait_cycles;
45
46 wait_cycles = be64_to_cpu(get_lppaca()->wait_state_cycles);
47 wait_cycles += mfspr(SPRN_PURR) - in_purr;
48 get_lppaca()->wait_state_cycles = cpu_to_be64(wait_cycles);
49 get_lppaca()->idle = 0;
50}
51
52static int snooze_loop(struct cpuidle_device *dev,
53 struct cpuidle_driver *drv,
54 int index)
55{
56 unsigned long in_purr;
57 int cpu = dev->cpu;
58
59 idle_loop_prolog(&in_purr);
60 local_irq_enable();
61 set_thread_flag(TIF_POLLING_NRFLAG);
62
63 while ((!need_resched()) && cpu_online(cpu)) {
64 HMT_low();
65 HMT_very_low();
66 }
67
68 HMT_medium();
69 clear_thread_flag(TIF_POLLING_NRFLAG);
70 smp_mb();
71
72 idle_loop_epilog(in_purr);
73
74 return index;
75}
76
77static void check_and_cede_processor(void)
78{
79 /*
80 * Ensure our interrupt state is properly tracked,
81 * also checks if no interrupt has occurred while we
82 * were soft-disabled
83 */
84 if (prep_irq_for_idle()) {
85 cede_processor();
86#ifdef CONFIG_TRACE_IRQFLAGS
87 /* Ensure that H_CEDE returns with IRQs on */
88 if (WARN_ON(!(mfmsr() & MSR_EE)))
89 __hard_irq_enable();
90#endif
91 }
92}
93
94static int dedicated_cede_loop(struct cpuidle_device *dev,
95 struct cpuidle_driver *drv,
96 int index)
97{
98 unsigned long in_purr;
99
100 idle_loop_prolog(&in_purr);
101 get_lppaca()->donate_dedicated_cpu = 1;
102
103 HMT_medium();
104 check_and_cede_processor();
105
106 get_lppaca()->donate_dedicated_cpu = 0;
107
108 idle_loop_epilog(in_purr);
109
110 return index;
111}
112
113static int shared_cede_loop(struct cpuidle_device *dev,
114 struct cpuidle_driver *drv,
115 int index)
116{
117 unsigned long in_purr;
118
119 idle_loop_prolog(&in_purr);
120
121 /*
122 * Yield the processor to the hypervisor. We return if
123 * an external interrupt occurs (which are driven prior
124 * to returning here) or if a prod occurs from another
125 * processor. When returning here, external interrupts
126 * are enabled.
127 */
128 check_and_cede_processor();
129
130 idle_loop_epilog(in_purr);
131
132 return index;
133}
134
135/*
136 * States for dedicated partition case.
137 */
138static struct cpuidle_state dedicated_states[MAX_IDLE_STATE_COUNT] = {
139 { /* Snooze */
140 .name = "snooze",
141 .desc = "snooze",
142 .flags = CPUIDLE_FLAG_TIME_VALID,
143 .exit_latency = 0,
144 .target_residency = 0,
145 .enter = &snooze_loop },
146 { /* CEDE */
147 .name = "CEDE",
148 .desc = "CEDE",
149 .flags = CPUIDLE_FLAG_TIME_VALID,
150 .exit_latency = 10,
151 .target_residency = 100,
152 .enter = &dedicated_cede_loop },
153};
154
155/*
156 * States for shared partition case.
157 */
158static struct cpuidle_state shared_states[MAX_IDLE_STATE_COUNT] = {
159 { /* Shared Cede */
160 .name = "Shared Cede",
161 .desc = "Shared Cede",
162 .flags = CPUIDLE_FLAG_TIME_VALID,
163 .exit_latency = 0,
164 .target_residency = 0,
165 .enter = &shared_cede_loop },
166};
167
168void update_smt_snooze_delay(int cpu, int residency)
169{
170 struct cpuidle_driver *drv = cpuidle_get_driver();
171 struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
172
173 if (cpuidle_state_table != dedicated_states)
174 return;
175
176 if (residency < 0) {
177 /* Disable the Nap state on that cpu */
178 if (dev)
179 dev->states_usage[1].disable = 1;
180 } else
181 if (drv)
182 drv->states[1].target_residency = residency;
183}
184
185static int pseries_cpuidle_add_cpu_notifier(struct notifier_block *n,
186 unsigned long action, void *hcpu)
187{
188 int hotcpu = (unsigned long)hcpu;
189 struct cpuidle_device *dev =
190 per_cpu_ptr(cpuidle_devices, hotcpu);
191
192 if (dev && cpuidle_get_driver()) {
193 switch (action) {
194 case CPU_ONLINE:
195 case CPU_ONLINE_FROZEN:
196 cpuidle_pause_and_lock();
197 cpuidle_enable_device(dev);
198 cpuidle_resume_and_unlock();
199 break;
200
201 case CPU_DEAD:
202 case CPU_DEAD_FROZEN:
203 cpuidle_pause_and_lock();
204 cpuidle_disable_device(dev);
205 cpuidle_resume_and_unlock();
206 break;
207
208 default:
209 return NOTIFY_DONE;
210 }
211 }
212 return NOTIFY_OK;
213}
214
215static struct notifier_block setup_hotplug_notifier = {
216 .notifier_call = pseries_cpuidle_add_cpu_notifier,
217};
218
219/*
220 * pseries_cpuidle_driver_init()
221 */
222static int pseries_cpuidle_driver_init(void)
223{
224 int idle_state;
225 struct cpuidle_driver *drv = &pseries_idle_driver;
226
227 drv->state_count = 0;
228
229 for (idle_state = 0; idle_state < MAX_IDLE_STATE_COUNT; ++idle_state) {
230
231 if (idle_state > max_idle_state)
232 break;
233
234 /* is the state not enabled? */
235 if (cpuidle_state_table[idle_state].enter == NULL)
236 continue;
237
238 drv->states[drv->state_count] = /* structure copy */
239 cpuidle_state_table[idle_state];
240
241 drv->state_count += 1;
242 }
243
244 return 0;
245}
246
247/*
248 * pseries_idle_probe()
249 * Choose state table for shared versus dedicated partition
250 */
251static int pseries_idle_probe(void)
252{
253
254 if (!firmware_has_feature(FW_FEATURE_SPLPAR))
255 return -ENODEV;
256
257 if (cpuidle_disable != IDLE_NO_OVERRIDE)
258 return -ENODEV;
259
260 if (max_idle_state == 0) {
261 printk(KERN_DEBUG "pseries processor idle disabled.\n");
262 return -EPERM;
263 }
264
265 if (lppaca_shared_proc(get_lppaca()))
266 cpuidle_state_table = shared_states;
267 else
268 cpuidle_state_table = dedicated_states;
269
270 return 0;
271}
272
273static int __init pseries_processor_idle_init(void)
274{
275 int retval;
276
277 retval = pseries_idle_probe();
278 if (retval)
279 return retval;
280
281 pseries_cpuidle_driver_init();
282 retval = cpuidle_register(&pseries_idle_driver, NULL);
283 if (retval) {
284 printk(KERN_DEBUG "Registration of pseries driver failed.\n");
285 return retval;
286 }
287
288 register_cpu_notifier(&setup_hotplug_notifier);
289 printk(KERN_DEBUG "pseries_idle_driver registered\n");
290
291 return 0;
292}
293
294static void __exit pseries_processor_idle_exit(void)
295{
296
297 unregister_cpu_notifier(&setup_hotplug_notifier);
298 cpuidle_unregister(&pseries_idle_driver);
299
300 return;
301}
302
303module_init(pseries_processor_idle_init);
304module_exit(pseries_processor_idle_exit);
305
306MODULE_AUTHOR("Deepthi Dharwar <deepthi@linux.vnet.ibm.com>");
307MODULE_DESCRIPTION("Cpuidle driver for POWER");
308MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index bd968a43a48b..62c47bb76517 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -292,6 +292,7 @@ static void iommu_table_dart_setup(void)
292 iommu_table_dart.it_offset = 0; 292 iommu_table_dart.it_offset = 0;
293 /* it_size is in number of entries */ 293 /* it_size is in number of entries */
294 iommu_table_dart.it_size = dart_tablesize / sizeof(u32); 294 iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
295 iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;
295 296
296 /* Initialize the common IOMMU code */ 297 /* Initialize the common IOMMU code */
297 iommu_table_dart.it_base = (unsigned long)dart_vbase; 298 iommu_table_dart.it_base = (unsigned long)dart_vbase;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 04:41:19 -0500