diff options
author | Becky Bruce <beckyb@kernel.crashing.org> | 2011-06-28 15:54:47 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2011-07-08 01:21:34 -0400 |
commit | 3160b09796129abc9523ea3cd1633b0faba64a02 (patch) | |
tree | 53713f22a00a100d8d1e3e2a677da26f206d9fd6 /arch/powerpc | |
parent | f6ad160e6f4f4d6933eeb82a2bfa25ea008585f0 (diff) |
powerpc: Create next_tlbcam_idx percpu variable for FSL_BOOKE
This is used to round-robin TLBCAM entries.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/include/asm/mmu.h | 5 | ||||
-rw-r--r-- | arch/powerpc/kernel/smp.c | 4 | ||||
-rw-r--r-- | arch/powerpc/mm/mem.c | 9 | ||||
-rw-r--r-- | arch/powerpc/mm/tlb_nohash.c | 6 |
4 files changed, 24 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 4138b21ae80a..b427a55ce2ab 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h | |||
@@ -115,6 +115,11 @@ | |||
115 | #ifndef __ASSEMBLY__ | 115 | #ifndef __ASSEMBLY__ |
116 | #include <asm/cputable.h> | 116 | #include <asm/cputable.h> |
117 | 117 | ||
118 | #ifdef CONFIG_PPC_FSL_BOOK3E | ||
119 | #include <asm/percpu.h> | ||
120 | DECLARE_PER_CPU(int, next_tlbcam_idx); | ||
121 | #endif | ||
122 | |||
118 | static inline int mmu_has_feature(unsigned long feature) | 123 | static inline int mmu_has_feature(unsigned long feature) |
119 | { | 124 | { |
120 | return (cur_cpu_spec->mmu_features & feature); | 125 | return (cur_cpu_spec->mmu_features & feature); |
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 6c8e739a12da..567a1746ed74 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c | |||
@@ -305,6 +305,10 @@ struct thread_info *current_set[NR_CPUS]; | |||
305 | static void __devinit smp_store_cpu_info(int id) | 305 | static void __devinit smp_store_cpu_info(int id) |
306 | { | 306 | { |
307 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); | 307 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
308 | #ifdef CONFIG_PPC_FSL_BOOK3E | ||
309 | per_cpu(next_tlbcam_idx, id) | ||
310 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | ||
311 | #endif | ||
308 | } | 312 | } |
309 | 313 | ||
310 | void __init smp_prepare_cpus(unsigned int max_cpus) | 314 | void __init smp_prepare_cpus(unsigned int max_cpus) |
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index a3841bb75cbb..457dc84154ba 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c | |||
@@ -353,6 +353,15 @@ void __init mem_init(void) | |||
353 | } | 353 | } |
354 | #endif /* CONFIG_HIGHMEM */ | 354 | #endif /* CONFIG_HIGHMEM */ |
355 | 355 | ||
356 | #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP) | ||
357 | /* | ||
358 | * If smp is enabled, next_tlbcam_idx is initialized in the cpu up | ||
359 | * functions.... do it here for the non-smp case. | ||
360 | */ | ||
361 | per_cpu(next_tlbcam_idx, smp_processor_id()) = | ||
362 | (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | ||
363 | #endif | ||
364 | |||
356 | printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " | 365 | printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " |
357 | "%luk reserved, %luk data, %luk bss, %luk init)\n", | 366 | "%luk reserved, %luk data, %luk bss, %luk init)\n", |
358 | nr_free_pages() << (PAGE_SHIFT-10), | 367 | nr_free_pages() << (PAGE_SHIFT-10), |
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 3722185d1865..e80ed1093e2f 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c | |||
@@ -102,6 +102,12 @@ unsigned long linear_map_top; /* Top of linear mapping */ | |||
102 | 102 | ||
103 | #endif /* CONFIG_PPC64 */ | 103 | #endif /* CONFIG_PPC64 */ |
104 | 104 | ||
105 | #ifdef CONFIG_PPC_FSL_BOOK3E | ||
106 | /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ | ||
107 | DEFINE_PER_CPU(int, next_tlbcam_idx); | ||
108 | EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); | ||
109 | #endif | ||
110 | |||
105 | /* | 111 | /* |
106 | * Base TLB flushing operations: | 112 | * Base TLB flushing operations: |
107 | * | 113 | * |