diff options
author | Al Viro <viro@ftp.linux.org.uk> | 2008-04-28 01:59:45 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-28 13:03:31 -0400 |
commit | 24caa6a0c7cde9309026880f8cc7eba587e1272a (patch) | |
tree | 784d57ab89cf1aceada1d7019beb5cbb603a84ef /arch/powerpc | |
parent | fd05e720099e8eeddb378305d1a41c1445344b91 (diff) |
celleb_scc_pciex __iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/platforms/cell/celleb_scc_pciex.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c index ab24d94baab6..31da84c458d2 100644 --- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c +++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c | |||
@@ -36,8 +36,8 @@ | |||
36 | #include "celleb_scc.h" | 36 | #include "celleb_scc.h" |
37 | #include "celleb_pci.h" | 37 | #include "celleb_pci.h" |
38 | 38 | ||
39 | #define PEX_IN(base, off) in_be32((void *)(base) + (off)) | 39 | #define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off)) |
40 | #define PEX_OUT(base, off, data) out_be32((void *)(base) + (off), (data)) | 40 | #define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data)) |
41 | 41 | ||
42 | static void scc_pciex_io_flush(struct iowa_bus *bus) | 42 | static void scc_pciex_io_flush(struct iowa_bus *bus) |
43 | { | 43 | { |
@@ -304,7 +304,7 @@ static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data) | |||
304 | ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT) | 304 | ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT) |
305 | #define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size)) | 305 | #define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size)) |
306 | 306 | ||
307 | static uint32_t config_read_pciex_dev(unsigned int *base, | 307 | static uint32_t config_read_pciex_dev(unsigned int __iomem *base, |
308 | uint64_t bus_no, uint64_t dev_no, uint64_t func_no, | 308 | uint64_t bus_no, uint64_t dev_no, uint64_t func_no, |
309 | uint64_t off, uint64_t size) | 309 | uint64_t off, uint64_t size) |
310 | { | 310 | { |
@@ -320,7 +320,7 @@ static uint32_t config_read_pciex_dev(unsigned int *base, | |||
320 | return ret; | 320 | return ret; |
321 | } | 321 | } |
322 | 322 | ||
323 | static void config_write_pciex_dev(unsigned int *base, uint64_t bus_no, | 323 | static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no, |
324 | uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size, | 324 | uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size, |
325 | uint32_t data) | 325 | uint32_t data) |
326 | { | 326 | { |
@@ -338,7 +338,7 @@ static void config_write_pciex_dev(unsigned int *base, uint64_t bus_no, | |||
338 | ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT) | 338 | ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT) |
339 | #define MK_PEXCADRS(cmd, addr, size) \ | 339 | #define MK_PEXCADRS(cmd, addr, size) \ |
340 | ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3)) | 340 | ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3)) |
341 | static uint32_t config_read_pciex_rc(unsigned int *base, | 341 | static uint32_t config_read_pciex_rc(unsigned int __iomem *base, |
342 | uint32_t where, uint32_t size) | 342 | uint32_t where, uint32_t size) |
343 | { | 343 | { |
344 | PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size)); | 344 | PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size)); |
@@ -346,7 +346,7 @@ static uint32_t config_read_pciex_rc(unsigned int *base, | |||
346 | >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1); | 346 | >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1); |
347 | } | 347 | } |
348 | 348 | ||
349 | static void config_write_pciex_rc(unsigned int *base, uint32_t where, | 349 | static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where, |
350 | uint32_t size, uint32_t val) | 350 | uint32_t size, uint32_t val) |
351 | { | 351 | { |
352 | uint32_t data; | 352 | uint32_t data; |
@@ -410,7 +410,7 @@ static struct pci_ops scc_pciex_pci_ops = { | |||
410 | scc_pciex_write_config, | 410 | scc_pciex_write_config, |
411 | }; | 411 | }; |
412 | 412 | ||
413 | static void pciex_clear_intr_all(unsigned int *base) | 413 | static void pciex_clear_intr_all(unsigned int __iomem *base) |
414 | { | 414 | { |
415 | PEX_OUT(base, PEXAERRSTS, 0xffffffff); | 415 | PEX_OUT(base, PEXAERRSTS, 0xffffffff); |
416 | PEX_OUT(base, PEXPRERRSTS, 0xffffffff); | 416 | PEX_OUT(base, PEXPRERRSTS, 0xffffffff); |
@@ -427,7 +427,7 @@ static void pciex_disable_intr_all(unsigned int *base) | |||
427 | } | 427 | } |
428 | #endif | 428 | #endif |
429 | 429 | ||
430 | static void pciex_enable_intr_all(unsigned int *base) | 430 | static void pciex_enable_intr_all(unsigned int __iomem *base) |
431 | { | 431 | { |
432 | PEX_OUT(base, PEXINTMASK, 0x0000e7f1); | 432 | PEX_OUT(base, PEXINTMASK, 0x0000e7f1); |
433 | PEX_OUT(base, PEXAERRMASK, 0x03ff01ff); | 433 | PEX_OUT(base, PEXAERRMASK, 0x03ff01ff); |
@@ -435,7 +435,7 @@ static void pciex_enable_intr_all(unsigned int *base) | |||
435 | PEX_OUT(base, PEXVDMASK, 0x00000001); | 435 | PEX_OUT(base, PEXVDMASK, 0x00000001); |
436 | } | 436 | } |
437 | 437 | ||
438 | static void pciex_check_status(unsigned int *base) | 438 | static void pciex_check_status(unsigned int __iomem *base) |
439 | { | 439 | { |
440 | uint32_t err = 0; | 440 | uint32_t err = 0; |
441 | uint32_t intsts, aerr, prerr, rcvcp, lenerr; | 441 | uint32_t intsts, aerr, prerr, rcvcp, lenerr; |