Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (134 commits)
  powerpc/nvram: Enable use Generic NVRAM driver for different size chips
  powerpc/iseries: Fix oops reading from /proc/iSeries/mf/*/cmdline
  powerpc/ps3: Workaround for flash memory I/O error
  powerpc/booke: Don't set DABR on 64-bit BookE, use DAC1 instead
  powerpc/perf_counters: Reduce stack usage of power_check_constraints
  powerpc: Fix bug where perf_counters breaks oprofile
  powerpc/85xx: Fix SMP compile error and allow NULL for smp_ops
  powerpc/irq: Improve nanodoc
  powerpc: Fix some late PowerMac G5 with PCIe ATI graphics
  powerpc/fsl-booke: Use HW PTE format if CONFIG_PTE_64BIT
  powerpc/book3e: Add missing page sizes
  powerpc/pseries: Fix to handle slb resize across migration
  powerpc/powermac: Thermal control turns system off too eagerly
  powerpc/pci: Merge ppc32 and ppc64 versions of phb_scan()
  powerpc/405ex: support cuImage via included dtb
  powerpc/405ex: provide necessary fixup function to support cuImage
  powerpc/40x: Add support for the ESTeem 195E (PPC405EP) SBC
  powerpc/44x: Add Eiger AMCC (AppliedMicro) PPC460SX evaluation board support.
  powerpc/44x: Update Arches defconfig
  powerpc/44x: Update Arches dts
  ...

Fix up conflicts in drivers/char/agp/uninorth-agp.c

206 files changed, 11125 insertions, 2422 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2c42e1526d03..8250902265c6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -123,7 +123,8 @@ config PPC
         select HAVE_KRETPROBES
         select HAVE_ARCH_TRACEHOOK
         select HAVE_LMB
-        select HAVE_DMA_ATTRS if PPC64
+        select HAVE_DMA_ATTRS
+        select HAVE_DMA_API_DEBUG
         select USE_GENERIC_SMP_HELPERS if SMP
         select HAVE_OPROFILE
         select HAVE_SYSCALL_WRAPPERS if PPC64
@@ -310,10 +311,6 @@ config SWIOTLB
           platforms where the size of a physical address is larger
           than the bus address.  Not all platforms support this.
 
-config PPC_NEED_DMA_SYNC_OPS
-        def_bool y
-        depends on (NOT_COHERENT_CACHE || SWIOTLB)
-
 config HOTPLUG_CPU
         bool "Support for enabling/disabling CPUs"
         depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC)
@@ -475,7 +472,7 @@ config PPC_16K_PAGES
         bool "16k page size" if 44x
 
 config PPC_64K_PAGES
-        bool "64k page size" if 44x || PPC_STD_MMU_64
+        bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
         select PPC_HAS_HASH_64K if PPC_STD_MMU_64
 
 config PPC_256K_PAGES
@@ -495,16 +492,16 @@ endchoice
 
 config FORCE_MAX_ZONEORDER
         int "Maximum zone order"
-        range 9 64 if PPC_STD_MMU_64 && PPC_64K_PAGES
-        default "9" if PPC_STD_MMU_64 && PPC_64K_PAGES
-        range 13 64 if PPC_STD_MMU_64 && !PPC_64K_PAGES
-        default "13" if PPC_STD_MMU_64 && !PPC_64K_PAGES
-        range 9 64 if PPC_STD_MMU_32 && PPC_16K_PAGES
-        default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
-        range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
-        default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
-        range 5 64 if PPC_STD_MMU_32 && PPC_256K_PAGES
-        default "5" if PPC_STD_MMU_32 && PPC_256K_PAGES
+        range 9 64 if PPC64 && PPC_64K_PAGES
+        default "9" if PPC64 && PPC_64K_PAGES
+        range 13 64 if PPC64 && !PPC_64K_PAGES
+        default "13" if PPC64 && !PPC_64K_PAGES
+        range 9 64 if PPC32 && PPC_16K_PAGES
+        default "9" if PPC32 && PPC_16K_PAGES
+        range 7 64 if PPC32 && PPC_64K_PAGES
+        default "7" if PPC32 && PPC_64K_PAGES
+        range 5 64 if PPC32 && PPC_256K_PAGES
+        default "5" if PPC32 && PPC_256K_PAGES
         range 11 64
         default "11"
         help
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index bc35f4e2b81c..952a3963e9e8 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -77,7 +77,7 @@ CPP		= $(CC) -E $(KBUILD_CFLAGS)
 CHECKFLAGS      += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
 
 ifeq ($(CONFIG_PPC64),y)
-GCC_BROKEN_VEC  := $(shell if [ $(call cc-version) -lt 0400 ] ; then echo "y"; fi)
+GCC_BROKEN_VEC  := $(call cc-ifversion, -lt, 0400, y)
 
 ifeq ($(CONFIG_POWER4_ONLY),y)
 ifeq ($(CONFIG_ALTIVEC),y)
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 325b310573b9..27db8938827a 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -8,6 +8,10 @@
  *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  *   Copyright (c) 2003, 2004 Zultys Technologies
  *
+ * Copyright (C) 2009 Wind River Systems, Inc.
+ *   Updated for supporting PPC405EX on Kilauea.
+ *   Tiejun Chen <tiejun.chen@windriver.com>
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
@@ -659,3 +663,141 @@ void ibm405ep_fixup_clocks(unsigned int sys_clk)
         dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
         dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
 }
+
+static u8 ibm405ex_fwdv_multi_bits[] = {
+        /* values for:  1 - 16 */
+        0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
+        0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
+};
+
+u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
+{
+        u32 index;
+
+        for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
+                if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
+                        return index + 1;
+
+        return 0;
+}
+
+static u8 ibm405ex_fbdv_multi_bits[] = {
+        /* values for:  1 - 100 */
+        0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
+        0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
+        0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
+        0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
+        0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
+        0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
+        0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
+        0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
+        0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
+        0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
+        /* values for:  101 - 200 */
+        0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
+        0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
+        0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
+        0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
+        0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
+        0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
+        0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
+        0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
+        0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
+        0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
+        /* values for:  201 - 255 */
+        0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
+        0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
+        0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
+        0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
+        0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
+        0x03, 0x87, 0x0f, 0x9f, 0x3f  /* END */
+};
+
+u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
+{
+        u32 index;
+
+        for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
+                if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
+                        return index + 1;
+
+        return 0;
+}
+
+void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
+{
+        /* PLL config */
+        u32 pllc  = CPR0_READ(DCRN_CPR0_PLLC);
+        u32 plld  = CPR0_READ(DCRN_CPR0_PLLD);
+        u32 cpud  = CPR0_READ(DCRN_CPR0_PRIMAD);
+        u32 plbd  = CPR0_READ(DCRN_CPR0_PRIMBD);
+        u32 opbd  = CPR0_READ(DCRN_CPR0_OPBD);
+        u32 perd  = CPR0_READ(DCRN_CPR0_PERD);
+
+        /* Dividers */
+        u32 fbdv   = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
+
+        u32 fwdva  = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
+
+        u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
+
+        /* PLBDV0 is hardwared to 010. */
+        u32 plbdv0 = 2;
+        u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
+
+        u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
+
+        u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
+
+        /* Resulting clocks */
+        u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
+
+        /* PLL's VCO is the source for primary forward ? */
+        if (pllc & 0x40000000) {
+                u32 m;
+
+                /* Feedback path */
+                switch ((pllc >> 24) & 7) {
+                case 0:
+                        /* PLLOUTx */
+                        m = fbdv;
+                        break;
+                case 1:
+                        /* CPU */
+                        m = fbdv * fwdva * cpudv0;
+                        break;
+                case 5:
+                        /* PERClk */
+                        m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
+                        break;
+                default:
+                        printf("WARNING ! Invalid PLL feedback source !\n");
+                        goto bypass;
+                }
+
+                vco = (unsigned int)(sys_clk * m);
+        } else {
+bypass:
+                /* Bypass system PLL */
+                vco = 0;
+        }
+
+        /* CPU = VCO / ( FWDVA x CPUDV0) */
+        cpu = vco / (fwdva * cpudv0);
+        /* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
+        plb = vco / (fwdva * plb2xdv0 * plbdv0);
+        /* OPB = PLB / OPBDV0 */
+        opb = plb / opbdv0;
+        /* EBC = OPB / PERDV0 */
+        ebc = opb / perdv0;
+
+        tb = cpu;
+        uart0 = uart1 = uart_clk;
+
+        dt_fixup_cpu_clocks(cpu, tb, 0);
+        dt_fixup_clock("/plb", plb);
+        dt_fixup_clock("/plb/opb", opb);
+        dt_fixup_clock("/plb/opb/ebc", ebc);
+        dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
+        dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
+}
diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h
index 2606e64f0c4b..7dc5d45361bc 100644
--- a/arch/powerpc/boot/4xx.h
+++ b/arch/powerpc/boot/4xx.h
@@ -21,6 +21,7 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc);
 
 void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
 void ibm405ep_fixup_clocks(unsigned int sys_clk);
+void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
 void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
 void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
                            unsigned int tmr_clk);
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 9ae7b7e2ba71..7bfc8ad87798 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -39,6 +39,7 @@ DTS_FLAGS	?= -p 1024
 
 $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
+$(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
@@ -67,7 +68,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
                 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
                 fsl-soc.c mpc8xx.c pq2.c
 src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
-                cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
+                cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
                 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
                 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
                 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
@@ -75,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
-                cuboot-acadia.c cuboot-amigaone.c
+                cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -190,6 +191,7 @@ image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
 
 # Board ports in arch/powerpc/platform/40x/Kconfig
 image-$(CONFIG_EP405)                   += dtbImage.ep405
+image-$(CONFIG_HOTFOOT)                 += cuImage.hotfoot
 image-$(CONFIG_WALNUT)                  += treeImage.walnut
 image-$(CONFIG_ACADIA)                  += cuImage.acadia
 
diff --git a/arch/powerpc/boot/cuboot-hotfoot.c b/arch/powerpc/boot/cuboot-hotfoot.c
new file mode 100644
index 000000000000..8f697b958e45
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-hotfoot.c
@@ -0,0 +1,142 @@
+/*
+ * Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
+ *
+ * Author: Solomon Peachy <solomon@linux-wlan.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "reg.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_HOTFOOT
+
+#include "ppcboot-hotfoot.h"
+
+static bd_t bd;
+
+#define NUM_REGS 3
+
+static void hotfoot_fixups(void)
+{
+        u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;
+
+        dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); 
+
+        dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);
+        dt_fixup_clock("/plb", bd.bi_plb_busfreq);
+        dt_fixup_clock("/plb/opb", bd.bi_opbfreq);
+        dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);
+        dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart); 
+        dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart); 
+        
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+
+        /* Is this a single eth/serial board? */
+        if ((bd.bi_enet1addr[0] == 0) && 
+            (bd.bi_enet1addr[1] == 0) &&
+            (bd.bi_enet1addr[2] == 0) &&
+            (bd.bi_enet1addr[3] == 0) &&
+            (bd.bi_enet1addr[4] == 0) &&
+            (bd.bi_enet1addr[5] == 0)) {
+                void *devp;
+
+                printf("Trimming devtree for single serial/eth board\n");
+
+                devp = finddevice("/plb/opb/serial@ef600300");
+                if (!devp)
+                        fatal("Can't find node for /plb/opb/serial@ef600300");
+                del_node(devp);
+
+                devp = finddevice("/plb/opb/ethernet@ef600900");
+                if (!devp)
+                        fatal("Can't find node for /plb/opb/ethernet@ef600900");
+                del_node(devp);
+        }
+
+        ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);
+
+        /* Fix up flash size in fdt for 4M boards. */
+        if (bd.bi_flashsize < 0x800000) {
+                u32 regs[NUM_REGS];
+                void *devp = finddevice("/plb/ebc/nor_flash@0");
+                if (!devp)
+                        fatal("Can't find FDT node for nor_flash!??");
+
+                printf("Fixing devtree for 4M Flash\n");
+                
+                /* First fix up the base addresse */
+                getprop(devp, "reg", regs, sizeof(regs));
+                regs[0] = 0;
+                regs[1] = 0xffc00000;
+                regs[2] = 0x00400000;
+                setprop(devp, "reg", regs, sizeof(regs));
+                
+                /* Then the offsets */
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@0");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@0");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@1");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@1");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@2");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@2");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@3");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@3");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@4");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@4");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@6");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@6");
+                getprop(devp, "reg", regs, 2*sizeof(u32));
+                regs[0] -= 0x400000;
+                setprop(devp, "reg", regs,  2*sizeof(u32));
+
+                /* Delete the FeatFS node */
+                devp = finddevice("/plb/ebc/nor_flash@0/partition@5");
+                if (!devp)
+                        fatal("Can't find FDT node for partition@5");
+                del_node(devp);
+        }
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+                   unsigned long r6, unsigned long r7)
+{
+        CUBOOT_INIT();
+        platform_ops.fixups = hotfoot_fixups;
+        platform_ops.exit = ibm40x_dbcr_reset;
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/cuboot-kilauea.c b/arch/powerpc/boot/cuboot-kilauea.c
new file mode 100644
index 000000000000..80cdad6bbc3f
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-kilauea.c
@@ -0,0 +1,49 @@
+/*
+ * Old U-boot compatibility for PPC405EX. This image is already included
+ * a dtb.
+ *
+ * Author: Tiejun Chen <tiejun.chen@windriver.com>
+ *
+ * Copyright (C) 2009 Wind River Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "io.h"
+#include "dcr.h"
+#include "stdio.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+#define KILAUEA_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk */
+
+static bd_t bd;
+
+static void kilauea_fixups(void)
+{
+        unsigned long sysclk = 33333333;
+
+        ibm405ex_fixup_clocks(sysclk, KILAUEA_SYS_EXT_SERIAL_CLOCK);
+        dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+        ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+                unsigned long r6, unsigned long r7)
+{
+        CUBOOT_INIT();
+        platform_ops.fixups = kilauea_fixups;
+        platform_ops.exit = ibm40x_dbcr_reset;
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 95b9f5344016..645a7c964e5f 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -153,9 +153,7 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
 #define DCRN_CPC0_PLLMR1  0xf4
 #define DCRN_CPC0_UCR     0xf5
 
-/* 440GX Clock control etc */
-
-
+/* 440GX/405EX Clock Control reg */
 #define DCRN_CPR0_CLKUPD                                0x020
 #define DCRN_CPR0_PLLC                                  0x040
 #define DCRN_CPR0_PLLD                                  0x060
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index d9113b1e8c1d..414ef8b7e575 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -124,6 +124,16 @@
                 dcr-reg = <0x00c 0x002>;
         };
 
+        L2C0: l2c {
+                compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+                dcr-reg = <0x020 0x008          /* Internal SRAM DCR's */
+                           0x030 0x008>;        /* L2 cache DCR's */
+                cache-line-size = <32>;         /* 32 bytes */
+                cache-size = <262144>;          /* L2, 256K */
+                interrupt-parent = <&UIC1>;
+                interrupts = <11 1>;
+        };
+
         plb {
                 compatible = "ibm,plb-460gt", "ibm,plb4";
                 #address-cells = <2>;
@@ -168,6 +178,38 @@
                                 /* ranges property is supplied by U-Boot */
                                 interrupts = <0x6 0x4>;
                                 interrupt-parent = <&UIC1>;
+
+                                nor_flash@0,0 {
+                                        compatible = "amd,s29gl256n", "cfi-flash";
+                                        bank-width = <2>;
+                                        reg = <0x00000000 0x00000000 0x02000000>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        partition@0 {
+                                                label = "kernel";
+                                                reg = <0x00000000 0x001e0000>;
+                                        };
+                                        partition@1e0000 {
+                                                label = "dtb";
+                                                reg = <0x001e0000 0x00020000>;
+                                        };
+                                        partition@200000 {
+                                                label = "root";
+                                                reg = <0x00200000 0x00200000>;
+                                        };
+                                        partition@400000 {
+                                                label = "user";
+                                                reg = <0x00400000 0x01b60000>;
+                                        };
+                                        partition@1f60000 {
+                                                label = "env";
+                                                reg = <0x01f60000 0x00040000>;
+                                        };
+                                        partition@1fa0000 {
+                                                label = "u-boot";
+                                                reg = <0x01fa0000 0x00060000>;
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600300 {
@@ -186,6 +228,14 @@
                                 reg = <0xef600700 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sttm@4a {
+                                        compatible = "ad,ad7414";
+                                        reg = <0x4a>;
+                                        interrupt-parent = <&UIC1>;
+                                        interrupts = <0x0 0x8>;
+                                };
                         };
 
                         IIC1: i2c@ef600800 {
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 5fd1ad09bdf2..c920170b7dfe 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Canyonlands (460EX)
  *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -149,19 +149,19 @@
                                         /*RXDE*/  0x5 0x4>;
                 };
 
-                USB0: ehci@bffd0400 {
-                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
-                        interrupt-parent = <&UIC2>;
-                        interrupts = <0x1d 4>;
-                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
-                };
+                USB0: ehci@bffd0400 {
+                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <0x1d 4>;
+                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
+                };
 
-                USB1: usb@bffd0000 {
-                        compatible = "ohci-le";
-                        reg = <4 0xbffd0000 0x60>;
-                        interrupt-parent = <&UIC2>;
-                        interrupts = <0x1e 4>;
-                };
+                USB1: usb@bffd0000 {
+                        compatible = "ohci-le";
+                        reg = <4 0xbffd0000 0x60>;
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <0x1e 4>;
+                };
 
                 POB0: opb {
                         compatible = "ibm,opb-460ex", "ibm,opb";
@@ -215,6 +215,29 @@
                                                 reg = <0x03fa0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@3,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000003 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00100000>;
+                                                };
+                                                partition@100000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x03f00000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600300 {
diff --git a/arch/powerpc/boot/dts/eiger.dts b/arch/powerpc/boot/dts/eiger.dts
new file mode 100644
index 000000000000..c4a934f2e886
--- /dev/null
+++ b/arch/powerpc/boot/dts/eiger.dts
@@ -0,0 +1,421 @@
+/*
+ * Device Tree Source for AMCC (AppliedMicro) Eiger(460SX)
+ *
+ * Copyright 2009 AMCC (AppliedMicro) <ttnguyen@amcc.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        model = "amcc,eiger";
+        compatible = "amcc,eiger";
+        dcr-parent = <&{/cpus/cpu@0}>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                ethernet2 = &EMAC2;
+                ethernet3 = &EMAC3;
+                serial0 = &UART0;
+                serial1 = &UART1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,460SX";
+                        reg = <0x00000000>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+                        timebase-frequency = <0>; /* Filled in by U-Boot */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+        };
+
+        UIC0: interrupt-controller0 {
+                compatible = "ibm,uic-460sx","ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0x0c0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic-460sx","ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0x0d0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic-460sx","ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0x0e0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC3: interrupt-controller3 {
+                compatible = "ibm,uic-460sx","ibm,uic";
+                interrupt-controller;
+                cell-index = <3>;
+                dcr-reg = <0x0f0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        SDR0: sdr {
+                compatible = "ibm,sdr-460sx";
+                dcr-reg = <0x00e 0x002>;
+        };
+
+        CPR0: cpr {
+                compatible = "ibm,cpr-460sx";
+                dcr-reg = <0x00c 0x002>;
+        };
+
+        plb {
+                compatible = "ibm,plb-460sx", "ibm,plb4";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+
+                SDRAM0: sdram {
+                        compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
+                        dcr-reg = <0x010 0x002>;
+                };
+
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
+                        dcr-reg = <0x180 0x62>;
+                        num-tx-chans = <4>;
+                        num-rx-chans = <32>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&UIC1>;
+                        interrupts = <  /*TXEOB*/ 0x6 0x4
+                                        /*RXEOB*/ 0x7 0x4
+                                        /*SERR*/  0x1 0x4
+                                        /*TXDE*/  0x2 0x4
+                                        /*RXDE*/  0x3 0x4
+                                        /*COAL TX0*/ 0x18 0x2
+                                        /*COAL TX1*/ 0x19 0x2
+                                        /*COAL TX2*/ 0x1a 0x2
+                                        /*COAL TX3*/ 0x1b 0x2
+                                        /*COAL RX0*/ 0x1c 0x2
+                                        /*COAL RX1*/ 0x1d 0x2
+                                        /*COAL RX2*/ 0x1e 0x2
+                                        /*COAL RX3*/ 0x1f 0x2>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb-460sx", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+
+                        EBC0: ebc {
+                                compatible = "ibm,ebc-460sx", "ibm,ebc";
+                                dcr-reg = <0x012 0x002>;
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                /* ranges property is supplied by U-Boot */
+                                interrupts = <0x6 0x4>;
+                                interrupt-parent = <&UIC1>;
+
+                                nor_flash@0,0 {
+                                        compatible = "amd,s29gl512n", "cfi-flash";
+                                        bank-width = <2>;
+                                        /* reg property is supplied in by U-Boot */
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        partition@0 {
+                                                label = "kernel";
+                                                reg = <0x00000000 0x001e0000>;
+                                        };
+                                        partition@1e0000 {
+                                                label = "dtb";
+                                                reg = <0x001e0000 0x00020000>;
+                                        };
+                                        partition@200000 {
+                                                label = "ramdisk";
+                                                reg = <0x00200000 0x01400000>;
+                                        };
+                                        partition@1600000 {
+                                                label = "jffs2";
+                                                reg = <0x01600000 0x00400000>;
+                                        };
+                                        partition@1a00000 {
+                                                label = "user";
+                                                reg = <0x01a00000 0x02560000>;
+                                        };
+                                        partition@3f60000 {
+                                                label = "env";
+                                                reg = <0x03f60000 0x00040000>;
+                                        };
+                                        partition@3fa0000 {
+                                                label = "u-boot";
+                                                reg = <0x03fa0000 0x00060000>;
+                                        };
+                                };
+
+                                ndfc@1,0 {
+                                        compatible = "ibm,ndfc";
+                                        /* reg property is supplied by U-boot */
+                                        ccr = <0x00003000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+                                                partition@0 {
+                                                        label = "uboot";
+                                                        reg = <0x00000000 0x00200000>;
+                                                };
+                                                partition@200000 {
+                                                        label = "uboot-environment";
+                                                        reg = <0x00200000 0x00100000>;
+                                                };
+                                                partition@300000 {
+                                                        label = "linux";
+                                                        reg = <0x00300000 0x00300000>;
+                                                };
+                                                partition@600000 {
+                                                        label = "root-file-system";
+                                                        reg = <0x00600000 0x01900000>;
+                                                };
+                                                partition@1f00000 {
+                                                        label = "device-tree";
+                                                        reg = <0x01f00000 0x00020000>;
+                                                };
+                                                partition@1f20000 {
+                                                        label = "data";
+                                                        reg = <0x01f20000 0x060E0000>;
+                                                };
+                                        };
+                                };
+                        };
+
+                        UART0: serial@ef600200 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600200 0x00000008>;
+                                virtual-reg = <0xef600200>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x0 0x4>;
+                        };
+
+                        UART1: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600300 0x00000008>;
+                                virtual-reg = <0xef600300>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x1 0x4>;
+                        };
+
+                        IIC0: i2c@ef600400 {
+                                compatible = "ibm,iic-460sx", "ibm,iic";
+                                reg = <0xef600400 0x00000014>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                index = <0>;
+                        };
+
+                        IIC1: i2c@ef600500 {
+                                compatible = "ibm,iic-460sx", "ibm,iic";
+                                reg = <0xef600500 0x00000014>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x3 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                index = <1>;
+                        };
+
+                        RGMII0: emac-rgmii@ef600900 {
+                                compatible = "ibm,rgmii-460sx", "ibm,rgmii";
+                                reg = <0xef600900 0x00000008>;
+                                has-mdio;
+                        };
+
+                        RGMII1: emac-rgmii@ef600920 {
+                                compatible = "ibm,rgmii-460sx", "ibm,rgmii";
+                                reg = <0xef600920 0x00000008>;
+                                has-mdio;
+                        };
+
+                        TAH0: emac-tah@ef600e50 {
+                                compatible = "ibm,tah-460sx", "ibm,tah";
+                                reg = <0xef600e50 0x00000030>;
+                        };
+
+                        TAH1: emac-tah@ef600f50 {
+                                compatible = "ibm,tah-460sx", "ibm,tah";
+                                reg = <0xef600f50 0x00000030>;
+                        };
+
+                        EMAC0: ethernet@ef600a00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460sx", "ibm,emac4";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
+                                                 /*Wake*/   0x1 &UIC2 0x1d 0x4>;
+                                reg = <0xef600a00 0x00000070>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+
+                        EMAC1: ethernet@ef600b00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460sx", "ibm,emac4";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4
+                                                 /*Wake*/   0x1 &UIC2 0x1d 0x4>;
+                                reg = <0xef600b00 0x00000070>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <8>;
+                                cell-index = <1>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+
+                        EMAC2: ethernet@ef600c00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460sx", "ibm,emac4";
+                                interrupt-parent = <&EMAC2>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x15 0x4
+                                                 /*Wake*/   0x1 &UIC2 0x1d 0x4>;
+                                reg = <0xef600c00 0x00000070>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <2>;
+                                mal-rx-channel = <16>;
+                                cell-index = <2>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII1>;
+                                rgmii-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+
+                        EMAC3: ethernet@ef600d00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460sx", "ibm,emac4";
+                                interrupt-parent = <&EMAC3>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x16 0x4
+                                                 /*Wake*/   0x1 &UIC2 0x1d 0x4>;
+                                reg = <0xef600d00 0x00000070>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <3>;
+                                mal-rx-channel = <24>;
+                                cell-index = <3>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII1>;
+                                rgmii-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+                };
+
+        };
+        chosen {
+                linux,stdout-path = "/plb/opb/serial@ef600200";
+        };
+
+};
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 0f4c9ec2c3a6..2107d3c7cfe1 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
 
                 /* flash@0,0 is a mirror of part of the memory in flash@1,0
                 flash@0,0 {
-                        compatible = "cfi-flash";
-                        reg = <0 0 0x01000000>;
+                        compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
+                        reg = <0x0 0x0 0x01000000>;
                         bank-width = <2>;
                         device-width = <2>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         partition@0 {
                                 label = "firmware";
-                                reg = <0x00000000 0x01000000>;
+                                reg = <0x0 0x01000000>;
                                 read-only;
                         };
                 };
                 */
 
                 flash@1,0 {
-                        compatible = "cfi-flash";
-                        reg = <1 0 0x8000000>;
+                        compatible = "gef,sbc310-paged-flash", "cfi-flash";
+                        reg = <0x1 0x0 0x8000000>;
                         bank-width = <2>;
                         device-width = <2>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         partition@0 {
                                 label = "user";
-                                reg = <0x00000000 0x07800000>;
+                                reg = <0x0 0x7800000>;
                         };
                         partition@7800000 {
                                 label = "firmware";
-                                reg = <0x07800000 0x00800000>;
+                                reg = <0x7800000 0x800000>;
                                 read-only;
                         };
                 };
@@ -121,18 +121,16 @@
                 };
 
                 wdt@4,2000 {
-                        #interrupt-cells = <2>;
-                        device_type = "watchdog";
-                        compatible = "gef,fpga-wdt";
+                        compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
                         reg = <0x4 0x2000 0x8>;
                         interrupts = <0x1a 0x4>;
                         interrupt-parent = <&gef_pic>;
                 };
 /*
                 wdt@4,2010 {
-                        #interrupt-cells = <2>;
-                        device_type = "watchdog";
-                        compatible = "gef,fpga-wdt";
+                        compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
                         reg = <0x4 0x2010 0x8>;
                         interrupts = <0x1b 0x4>;
                         interrupt-parent = <&gef_pic>;
@@ -141,7 +139,7 @@
                 gef_pic: pic@4,4000 {
                         #interrupt-cells = <1>;
                         interrupt-controller;
-                        compatible = "gef,fpga-pic";
+                        compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
                         reg = <0x4 0x4000 0x20>;
                         interrupts = <0x8
                                       0x9>;
@@ -161,7 +159,7 @@
                 #size-cells = <1>;
                 #interrupt-cells = <2>;
                 device_type = "soc";
-                compatible = "simple-bus";
+                compatible = "fsl,mpc8641-soc", "simple-bus";
                 ranges = <0x0 0xfef00000 0x00100000>;
                 bus-frequency = <33333333>;
 
@@ -376,4 +374,40 @@
                                   0x0 0x00400000>;
                 };
         };
+
+        pci1: pcie@fef09000 {
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xfef09000 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <0x19 0x2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
+                        0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
+                        0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
+                        0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0xc0000000
+                                  0x02000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00400000>;
+                };
+        };
 };
diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts
new file mode 100644
index 000000000000..cad9c3840afc
--- /dev/null
+++ b/arch/powerpc/boot/dts/hotfoot.dts
@@ -0,0 +1,294 @@
+/*
+ * Device Tree Source for ESTeem 195E Hotfoot
+ *
+ * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        model = "est,hotfoot";
+        compatible = "est,hotfoot";
+        dcr-parent = <&{/cpus/cpu@0}>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                serial0 = &UART0;
+                serial1 = &UART1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,405EP";
+                        reg = <0x00000000>;
+                        clock-frequency = <0>; /* Filled in by zImage */
+                        timebase-frequency = <0>; /* Filled in by zImage */
+                        i-cache-line-size = <0x20>;
+                        d-cache-line-size = <0x20>;
+                        i-cache-size = <0x4000>;
+                        d-cache-size = <0x4000>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000>; /* Filled in by zImage */
+        };
+
+        UIC0: interrupt-controller {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0x0c0 0x009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        plb {
+                compatible = "ibm,plb3";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by zImage */
+
+                SDRAM0: memory-controller {
+                        compatible = "ibm,sdram-405ep";
+                        dcr-reg = <0x010 0x002>;
+                };
+
+                MAL: mcmal {
+                        compatible = "ibm,mcmal-405ep", "ibm,mcmal";
+                        dcr-reg = <0x180 0x062>;
+                        num-tx-chans = <4>;
+                        num-rx-chans = <2>;
+                        interrupt-parent = <&UIC0>;
+                        interrupts = <
+                                0xb 0x4 /* TXEOB */
+                                0xc 0x4 /* RXEOB */
+                                0xa 0x4 /* SERR */
+                                0xd 0x4 /* TXDE */
+                                0xe 0x4 /* RXDE */>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb-405ep", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xef600000 0xef600000 0x00a00000>;
+                        dcr-reg = <0x0a0 0x005>;
+                        clock-frequency = <0>; /* Filled in by zImage */
+
+                        /* Hotfoot has UART0/UART1 swapped */
+
+                        UART0: serial@ef600400 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600400 0x00000008>;
+                                virtual-reg = <0xef600400>;
+                                clock-frequency = <0>; /* Filled in by zImage */
+                                current-speed = <0x9600>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x1 0x4>;
+                        };
+
+                        UART1: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600300 0x00000008>;
+                                virtual-reg = <0xef600300>;
+                                clock-frequency = <0>; /* Filled in by zImage */
+                                current-speed = <0x9600>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x0 0x4>;
+                        };
+
+                        IIC: i2c@ef600500 {
+                                compatible = "ibm,iic-405ep", "ibm,iic";
+                                reg = <0xef600500 0x00000011>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x2 0x4>;
+
+                                rtc@68 {
+                                        /* Actually a DS1339 */
+                                        compatible = "dallas,ds1307";
+                                        reg = <0x68>;
+                                };
+
+                                temp@4a {
+                                        /* Not present on all boards */
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+
+                        GPIO: gpio@ef600700 {
+                                #gpio-cells = <2>;
+                                compatible = "ibm,ppc4xx-gpio";
+                                reg = <0xef600700 0x00000020>;
+                                gpio-controller;
+                        };
+
+                        gpio-leds {
+                                compatible = "gpio-leds";
+                                status {
+                                        label = "Status";
+                                        gpios = <&GPIO 1 0>;
+                                };
+                                radiorx {
+                                        label = "Rx";
+                                        gpios = <&GPIO 0xe 0>;
+                                };
+                        };
+
+                        EMAC0: ethernet@ef600800 {
+                                linux,network-index = <0x0>;
+                                device_type = "network";
+                                compatible = "ibm,emac-405ep", "ibm,emac";
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <
+                                        0xf 0x4 /* Ethernet */
+                                        0x9 0x4 /* Ethernet Wake Up */>;
+                                local-mac-address = [000000000000]; /* Filled in by zImage */
+                                reg = <0xef600800 0x00000070>;
+                                mal-device = <&MAL>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <0x5dc>;
+                                rx-fifo-size = <0x1000>;
+                                tx-fifo-size = <0x800>;
+                                phy-mode = "mii";
+                                phy-map = <0x00000000>;
+                        };
+
+                        EMAC1: ethernet@ef600900 {
+                                linux,network-index = <0x1>;
+                                device_type = "network";
+                                compatible = "ibm,emac-405ep", "ibm,emac";
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <
+                                        0x11 0x4 /* Ethernet */
+                                        0x9 0x4 /* Ethernet Wake Up */>;
+                                local-mac-address = [000000000000]; /* Filled in by zImage */
+                                reg = <0xef600900 0x00000070>;
+                                mal-device = <&MAL>;
+                                mal-tx-channel = <2>;
+                                mal-rx-channel = <1>;
+                                cell-index = <1>;
+                                max-frame-size = <0x5dc>;
+                                rx-fifo-size = <0x1000>;
+                                tx-fifo-size = <0x800>;
+                                mdio-device = <&EMAC0>;
+                                phy-mode = "mii";
+                                phy-map = <0x0000001>;
+                        };
+                };
+
+                EBC0: ebc {
+                        compatible = "ibm,ebc-405ep", "ibm,ebc";
+                        dcr-reg = <0x012 0x002>;
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+
+                        /* The ranges property is supplied by the bootwrapper
+                         * and is based on the firmware's configuration of the
+                         * EBC bridge
+                         */
+                        clock-frequency = <0>; /* Filled in by zImage */
+
+                        nor_flash@0 {
+                                compatible = "cfi-flash";
+                                bank-width = <2>;
+                                reg = <0x0 0xff800000 0x00800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                /* This mapping is for the 8M flash
+                                   4M flash has all ofssets -= 4M,
+                                   and FeatFS partition is not present */
+                                partition@0 {
+                                        label = "Bootloader";
+                                        reg = <0x7c0000 0x40000>;
+                                        /* read-only; */
+                                };
+                                partition@1 {
+                                        label = "Env_and_Config_Primary";
+                                        reg = <0x400000 0x10000>;
+                                };
+                                partition@2 {
+                                        label = "Kernel";
+                                        reg = <0x420000 0x100000>;
+                                };
+                                partition@3 {
+                                        label = "Filesystem";
+                                        reg = <0x520000 0x2a0000>;
+                                };
+                                partition@4 {
+                                        label = "Env_and_Config_Secondary";
+                                        reg = <0x410000 0x10000>;
+                                };
+                                partition@5 {
+                                        label = "FeatFS";
+                                        reg = <0x000000 0x400000>;
+                                };
+                                partition@6 {
+                                        label = "Bootloader_Env";
+                                        reg = <0x7d0000 0x10000>;
+                                };
+                        };
+                };
+
+                PCI0: pci@ec000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
+                        primary;
+                        reg = <0xeec00000 0x00000008    /* Config space access */
+                                0xeed80000 0x00000004    /* IACK */
+                                0xeed80000 0x00000004    /* Special cycle */
+                                0xef480000 0x00000040>;  /* Internal registers */
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed. Chip supports a second
+                         * IO range but we don't use it for now
+                         */
+                        ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
+                                0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
+
+                        interrupt-parent = <&UIC0>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                /* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */
+                                0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
+                                0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
+
+                                /* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */
+                                0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
+                                0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8
+                                >;
+                };
+        };
+
+        chosen {
+                linux,stdout-path = &UART0;
+        };
+};
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 5e6b08ff6f67..c46561456ede 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Kilauea (405EX)
  *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -150,7 +150,11 @@
                                         #size-cells = <1>;
                                         partition@0 {
                                                 label = "kernel";
-                                                reg = <0x00000000 0x00200000>;
+                                                reg = <0x00000000 0x001e0000>;
+                                        };
+                                        partition@1e0000 {
+                                                label = "dtb";
+                                                reg = <0x001e0000 0x00020000>;
                                         };
                                         partition@200000 {
                                                 label = "root";
@@ -169,6 +173,29 @@
                                                 reg = <0x03fa0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@1,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000001 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00100000>;
+                                                };
+                                                partition@100000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x03f00000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600200 {
@@ -198,6 +225,18 @@
                                 reg = <0xef600400 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1338";
+                                        reg = <0x68>;
+                                };
+
+                                dtt@48 {
+                                        compatible = "dallas,ds1775";
+                                        reg = <0x48>;
+                                };
                         };
 
                         IIC1: i2c@ef600500 {
@@ -207,7 +246,6 @@
                                 interrupts = <0x7 0x4>;
                         };
 
-
                         RGMII0: emac-rgmii@ef600b00 {
                                 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
                                 reg = <0xef600b00 0x00000104>;
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index 633255a97557..0ce96644176d 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -162,6 +162,59 @@
                                 fixed-link = <0 0 10 0 0>;
                         };
 
+                        i2c@11860 {
+                                compatible = "fsl,mpc8272-i2c",
+                                             "fsl,cpm2-i2c";
+                                reg = <0x11860 0x20 0x8afc 0x2>;
+                                interrupts = <1 8>;
+                                interrupt-parent = <&PIC>;
+                                fsl,cpm-command = <0x29600000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        mdio@10d40 {
+                                compatible = "fsl,cpm2-mdio-bitbang";
+                                reg = <0x10d00 0x14>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                fsl,mdio-pin = <12>;
+                                fsl,mdc-pin = <13>;
+
+                                phy0: ethernet-phy@0 {
+                                        reg = <0x0>;
+                                };
+
+                                phy1: ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
+                        };
+
+                        /* FCC1 management to switch */
+                        ethernet@11300 {
+                                device_type = "network";
+                                compatible = "fsl,cpm2-fcc-enet";
+                                reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
+                                local-mac-address = [ 00 01 02 03 04 07 ];
+                                interrupts = <32 8>;
+                                interrupt-parent = <&PIC>;
+                                phy-handle = <&phy0>;
+                                linux,network-index = <1>;
+                                fsl,cpm-command = <0x12000300>;
+                        };
+
+                        /* FCC2 to redundant core unit over backplane */
+                        ethernet@11320 {
+                                device_type = "network";
+                                compatible = "fsl,cpm2-fcc-enet";
+                                reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
+                                local-mac-address = [ 00 01 02 03 04 08 ];
+                                interrupts = <33 8>;
+                                interrupt-parent = <&PIC>;
+                                phy-handle = <&phy1>;
+                                linux,network-index = <2>;
+                                fsl,cpm-command = <0x16200300>;
+                        };
                 };
 
                 PIC: interrupt-controller@10c00 {
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 60f332778e41..e802ebd88cb1 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -173,6 +173,14 @@
                                 fsl,cpm-command = <0xce00000>;
                         };
 
+                        usb@11b60 {
+                                compatible = "fsl,mpc8272-cpm-usb";
+                                reg = <0x11b60 0x40 0x8b00 0x100>;
+                                interrupts = <11 8>;
+                                interrupt-parent = <&PIC>;
+                                mode = "peripheral";
+                        };
+
                         mdio@10d40 {
                                 device_type = "mdio";
                                 compatible = "fsl,mpc8272ads-mdio-bitbang",
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 4f06dbc0d27e..28e022ac4179 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -174,7 +174,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
new file mode 100644
index 000000000000..3febc4e91b10
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -0,0 +1,464 @@
+/*
+ * MPC8377E WLAN Device Tree Source
+ *
+ * Copyright 2007-2009 Freescale Semiconductor Inc.
+ * Copyright 2009 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,mpc8377wlan";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8377@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;  // 512MB at 0
+        };
+
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 0x8>;
+                interrupt-parent = <&ipic>;
+                ranges = <0x0 0x0 0xfc000000 0x04000000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x4000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                reg = <0 0x8000>;
+                                label = "u-boot";
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                reg = <0xa0000 0x300000>;
+                                label = "kernel";
+                        };
+
+                        partition@3a0000 {
+                                reg = <0x3a0000 0x3c60000>;
+                                label = "rootfs";
+                        };
+                };
+        };
+
+        immr@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xe0000000 0x00100000>;
+                reg = <0xe0000000 0x00000200>;
+                bus-frequency = <0>;
+
+                wdt@200 {
+                        device_type = "watchdog";
+                        compatible = "mpc83xx_wdt";
+                        reg = <0x200 0x100>;
+                };
+
+                gpio1: gpio-controller@c00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xc00 0x100>;
+                        interrupts = <74 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                gpio2: gpio-controller@d00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xd00 0x100>;
+                        interrupts = <75 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                sleep-nexus {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x0c000000>;
+                        ranges;
+
+                        i2c@3000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3000 0x100>;
+                                interrupts = <14 0x8>;
+                                interrupt-parent = <&ipic>;
+                                dfsrr;
+
+                                at24@50 {
+                                        compatible = "at24,24c256";
+                                        reg = <0x50>;
+                                };
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1339";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        sdhci@2e000 {
+                                compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
+                                reg = <0x2e000 0x1000>;
+                                interrupts = <42 0x8>;
+                                interrupt-parent = <&ipic>;
+                                clock-frequency = <133333333>;
+                        };
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <15 0x8>;
+                        interrupt-parent = <&ipic>;
+                        dfsrr;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        compatible = "fsl,spi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <16 0x8>;
+                        interrupt-parent = <&ipic>;
+                        mode = "cpu";
+                };
+
+                dma@82a8 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
+                        reg = <0x82a8 4>;
+                        ranges = <0 0x8100 0x1a8>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x180 0x28>;
+                                cell-index = <3>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                };
+
+                usb@23000 {
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <38 0x8>;
+                        phy_type = "ulpi";
+                        sleep = <&pmc 0x00c00000>;
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <32 0x8 33 0x8 34 0x8>;
+                        phy-connection-type = "mii";
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy2>;
+                        sleep = <&pmc 0xc0000000>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <17 0x8>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+
+                                phy3: ethernet-phy@3 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <18 0x8>;
+                                        reg = <0x3>;
+                                        device_type = "ethernet-phy";
+                                };
+
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 0x8 36 0x8 37 0x8>;
+                        phy-connection-type = "mii";
+                        interrupt-parent = <&ipic>;
+                        phy-handle = <&phy3>;
+                        tbi-handle = <&tbi1>;
+                        sleep = <&pmc 0x30000000>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <9 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <10 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                     "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <11 0x8>;
+                        interrupt-parent = <&ipic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x9fe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                        sleep = <&pmc 0x03000000>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        interrupts = <44 0x8>;
+                        interrupt-parent = <&ipic>;
+                        sleep = <&pmc 0x000000c0>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        interrupts = <45 0x8>;
+                        interrupt-parent = <&ipic>;
+                        sleep = <&pmc 0x00000030>;
+                };
+
+                /* IPIC
+                 * interrupts cell = <intr #, sense>
+                 * sense values match linux IORESOURCE_IRQ_* defines:
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                ipic: interrupt-controller@700 {
+                        compatible = "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x700 0x100>;
+                };
+
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+        };
+
+        pci0: pci@e0008500 {
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                                /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
+
+                                /* IDSEL AD14 IRQ6 inta */
+                                 0x7000 0x0 0x0 0x1 &ipic 22 0x8
+
+                                /* IDSEL AD15 IRQ5 inta */
+                                 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
+                interrupt-parent = <&ipic>;
+                interrupts = <66 0x8>;
+                bus-range = <0 0>;
+                ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+                          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+                          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
+                sleep = <&pmc 0x00010000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0008500 0x100         /* internal registers */
+                       0xe0008300 0x8>;         /* config space access registers */
+                compatible = "fsl,mpc8349-pci";
+                device_type = "pci";
+        };
+
+        pci1: pcie@e0009000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe0009000 0x00001000>;
+                ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
+                bus-range = <0 255>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 1 8
+                                 0 0 0 2 &ipic 1 8
+                                 0 0 0 3 &ipic 1 8
+                                 0 0 0 4 &ipic 1 8>;
+                sleep = <&pmc 0x00300000>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xa8000000
+                                  0x02000000 0 0xa8000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+
+        pci2: pcie@e000a000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe000a000 0x00001000>;
+                ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
+                bus-range = <0 255>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 2 8
+                                 0 0 0 2 &ipic 2 8
+                                 0 0 0 3 &ipic 2 8
+                                 0 0 0 4 &ipic 2 8>;
+                sleep = <&pmc 0x000c0000>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xc8000000
+                                  0x02000000 0 0xc8000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index aabf3437cadf..a11ead8214b4 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -174,7 +174,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 9b1da864d890..e35dfba587c8 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -172,7 +172,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index e781ad2f1f8a..815cebb2e3e5 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -14,8 +14,8 @@
 / {
         model = "fsl,mpc8536ds";
         compatible = "fsl,mpc8536ds";
-        #address-cells = <1>;
-        #size-cells = <1>;
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         aliases {
                 ethernet0 = &enet0;
@@ -42,7 +42,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 00000000>;      // Filled by U-Boot
+                reg = <0 0 0 0>;        // Filled by U-Boot
         };
 
         soc@ffe00000 {
@@ -50,7 +50,7 @@
                 #size-cells = <1>;
                 device_type = "soc";
                 compatible = "simple-bus";
-                ranges = <0x0 0xffe00000 0x100000>;
+                ranges = <0x0 0 0xffe00000 0x100000>;
                 bus-frequency = <0>;            // Filled out by uboot.
 
                 ecm-law@0 {
@@ -250,6 +250,14 @@
                         phy_type = "ulpi";
                 };
 
+                sdhci@2e000 {
+                        compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        clock-frequency = <250000000>;
+                };
+
                 serial0: serial@4500 {
                         cell-index = <0>;
                         device_type = "serial";
@@ -347,13 +355,13 @@
                 interrupt-parent = <&mpic>;
                 interrupts = <24 0x2>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
-                          0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
+                ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
+                          0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
                 clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe08000 0x1000>;
+                reg = <0 0xffe08000 0 0x1000>;
         };
 
         pci1: pcie@ffe09000 {
@@ -362,10 +370,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe09000 0x1000>;
+                reg = <0 0xffe09000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
-                          0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
+                ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
+                          0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <25 0x2>;
@@ -398,10 +406,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe0a000 0x1000>;
+                reg = <0 0xffe0a000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
-                          0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
+                ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
+                          0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <26 0x2>;
@@ -434,10 +442,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe0b000 0x1000>;
+                reg = <0 0xffe0b000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
-                          0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
+                ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
+                          0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <27 0x2>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
new file mode 100644
index 000000000000..d95b26021e62
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -0,0 +1,475 @@
+/*
+ * MPC8536 DS Device Tree Source
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "fsl,mpc8536ds";
+        compatible = "fsl,mpc8536ds";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+        };
+
+        cpus {
+                #cpus = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8536@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0 0>;        // Filled by U-Boot
+        };
+
+        soc@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,mpc8536-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8536-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 0x2>;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8536-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 0x2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0 0x1>;
+                                interrupt-parent = <&mpic>;
+                        };
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 4>;
+                        ranges = <0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                        reg = <0x22000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                usb@23000 {
+                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <46 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy0: ethernet-phy@0 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 0x1>;
+                                        reg = <0>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy1: ethernet-phy@1 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 0x1>;
+                                        reg = <1>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                usb@2b000 {
+                        compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
+                        reg = <0x2b000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <60 0x2>;
+                        dr_mode = "peripheral";
+                        phy_type = "ulpi";
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        clock-frequency = <250000000>;
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                     "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x9fe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        cell-index = <1>;
+                        interrupts = <74 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        cell-index = <2>;
+                        interrupts = <41 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,mpc8548-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+
+                mpic: pic@40000 {
+                        clock-frequency = <0>;
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                        big-endian;
+                };
+
+                msi@41600 {
+                        compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+        };
+
+        pci0: pci@fffe08000 {
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x11 J17 Slot 1 */
+                        0x8800 0 0 1 &mpic 1 1
+                        0x8800 0 0 2 &mpic 2 1
+                        0x8800 0 0 3 &mpic 3 1
+                        0x8800 0 0 4 &mpic 4 1>;
+
+                interrupt-parent = <&mpic>;
+                interrupts = <24 0x2>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe08000 0 0x1000>;
+        };
+
+        pci1: pcie@fffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
+                          0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 4 1
+                        0000 0 0 2 &mpic 5 1
+                        0000 0 0 3 &mpic 6 1
+                        0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xf8000000
+                                  0x02000000 0 0xf8000000
+                                  0 0x08000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci2: pcie@fffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
+                          0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 0 1
+                        0000 0 0 2 &mpic 1 1
+                        0000 0 0 3 &mpic 2 1
+                        0000 0 0 4 &mpic 3 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xf8000000
+                                  0x02000000 0 0xf8000000
+                                  0 0x08000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci3: pcie@fffe0b000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0b000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <27 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 8 1
+                        0000 0 0 2 &mpic 9 1
+                        0000 0 0 3 &mpic 10 1
+                        0000 0 0 4 &mpic 11 1
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 475be1433fe1..4173af387c63 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -100,6 +100,21 @@
                         interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
+
+                        eeprom@50 {
+                                compatible = "atmel,24c64";
+                                reg = <0x50>;
+                        };
+
+                        eeprom@56 {
+                                compatible = "atmel,24c64";
+                                reg = <0x56>;
+                        };
+
+                        eeprom@57 {
+                                compatible = "atmel,24c64";
+                                reg = <0x57>;
+                        };
                 };
 
                 i2c@3100 {
@@ -111,6 +126,11 @@
                         interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
+
+                        eeprom@50 {
+                                compatible = "atmel,24c64";
+                                reg = <0x50>;
+                        };
                 };
 
                 dma@21300 {
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 9e4ce99e1613..06332d61830a 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -99,8 +99,18 @@
                 };
 
                 bcsr@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
                         compatible = "fsl,mpc8569mds-bcsr";
                         reg = <1 0 0x8000>;
+                        ranges = <0 1 0 0x8000>;
+
+                        bcsr17: gpio-controller@11 {
+                                #gpio-cells = <2>;
+                                compatible = "fsl,mpc8569mds-bcsr-gpio";
+                                reg = <0x11 0x1>;
+                                gpio-controller;
+                        };
                 };
 
                 nand@3,0 {
@@ -315,6 +325,14 @@
                                 gpio-controller;
                         };
 
+                        qe_pio_f: gpio-controller@a0 {
+                                #gpio-cells = <2>;
+                                compatible = "fsl,mpc8569-qe-pario-bank",
+                                             "fsl,mpc8323-qe-pario-bank";
+                                reg = <0xa0 0x18>;
+                                gpio-controller;
+                        };
+
                         pio1: ucc_pin@01 {
                                 pio-map = <
                         /* port  pin  dir  open_drain  assignment  has_irq */
@@ -419,6 +437,16 @@
                         interrupt-parent = <&mpic>;
                 };
 
+                timer@440 {
+                        compatible = "fsl,mpc8569-qe-gtm",
+                                     "fsl,qe-gtm", "fsl,gtm";
+                        reg = <0x440 0x40>;
+                        interrupts = <12 13 14 15>;
+                        interrupt-parent = <&qeic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
                 spi@4c0 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -446,6 +474,23 @@
                         mode = "cpu";
                 };
 
+                usb@6c0 {
+                        compatible = "fsl,mpc8569-qe-usb",
+                                     "fsl,mpc8323-qe-usb";
+                        reg = <0x6c0 0x40 0x8b00 0x100>;
+                        interrupts = <11>;
+                        interrupt-parent = <&qeic>;
+                        fsl,fullspeed-clock = "clk5";
+                        fsl,lowspeed-clock = "brg10";
+                        gpios = <&qe_pio_f 3 0   /* USBOE */
+                                 &qe_pio_f 4 0   /* USBTP */
+                                 &qe_pio_f 5 0   /* USBTN */
+                                 &qe_pio_f 6 0   /* USBRP */
+                                 &qe_pio_f 8 0   /* USBRN */
+                                 &bcsr17   6 0   /* SPEED */
+                                 &bcsr17   5 1>; /* POWER */
+                };
+
                 enet0: ucc@2000 {
                         device_type = "network";
                         compatible = "ucc_geth";
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000000000000..da4cb0d8d215
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P2020";
+        compatible = "fsl,P2020RDB";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P2020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+
+                PowerPC,P2020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@ffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
+                reg = <0 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+
+                /* NOR and NAND Flashes */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xffa00000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x1000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 256KB for Vitesse 7385 Switch firmware */
+                                reg = <0x0 0x00040000>;
+                                label = "NOR (RO) Vitesse-7385 Firmware";
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                /* 256KB for DTB Image */
+                                reg = <0x00040000 0x00040000>;
+                                label = "NOR (RO) DTB Image";
+                                read-only;
+                        };
+
+                        partition@80000 {
+                                /* 3.5 MB for Linux Kernel Image */
+                                reg = <0x00080000 0x00380000>;
+                                label = "NOR (RO) Linux Kernel Image";
+                                read-only;
+                        };
+
+                        partition@400000 {
+                                /* 11MB for JFFS2 based Root file System */
+                                reg = <0x00400000 0x00b00000>;
+                                label = "NOR (RW) JFFS2 Root File System";
+                        };
+
+                        partition@f00000 {
+                                /* This location must not be altered  */
+                                /* 512KB for u-boot Bootloader Image */
+                                /* 512KB for u-boot Environment Variables */
+                                reg = <0x00f00000 0x00100000>;
+                                label = "NOR (RO) U-Boot Image";
+                                read-only;
+                        };
+                };
+
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,p2020-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x1 0x0 0x40000>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 1MB for u-boot Bootloader Image */
+                                reg = <0x0 0x00100000>;
+                                label = "NAND (RO) U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                /* 1MB for DTB Image */
+                                reg = <0x00100000 0x00100000>;
+                                label = "NAND (RO) DTB Image";
+                                read-only;
+                        };
+
+                        partition@200000 {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00200000 0x00400000>;
+                                label = "NAND (RO) Linux Kernel Image";
+                                read-only;
+                        };
+
+                        partition@600000 {
+                                /* 4MB for Compressed Root file System Image */
+                                reg = <0x00600000 0x00400000>;
+                                label = "NAND (RO) Compressed RFS Image";
+                                read-only;
+                        };
+
+                        partition@a00000 {
+                                /* 7MB for JFFS2 based Root file System */
+                                reg = <0x00a00000 0x00700000>;
+                                label = "NAND (RW) JFFS2 Root File System";
+                        };
+
+                        partition@1100000 {
+                                /* 15MB for JFFS2 based Root file System */
+                                reg = <0x01100000 0x00f00000>;
+                                label = "NAND (RW) Writable User area";
+                        };
+                };
+
+                L2switch@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "vitesse-7385";
+                        reg = <0x2 0x0 0x20000>;
+                };
+
+        };
+
+        soc@ffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p2020-immr", "simple-bus";
+                ranges = <0x0  0x0 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,p2020-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,p2020-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        interrupt-parent = <&mpic>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                modal = "s25sl128b";
+                                spi-max-frequency = <50000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        /* 512KB for u-boot Bootloader Image */
+                                        reg = <0x0 0x00080000>;
+                                        label = "SPI (RO) U-Boot Image";
+                                        read-only;
+                                };
+
+                                partition@80000 {
+                                        /* 512KB for DTB Image */
+                                        reg = <0x00080000 0x00080000>;
+                                        label = "SPI (RO) DTB Image";
+                                        read-only;
+                                };
+
+                                partition@100000 {
+                                        /* 4MB for Linux Kernel Image */
+                                        reg = <0x00100000 0x00400000>;
+                                        label = "SPI (RO) Linux Kernel Image";
+                                        read-only;
+                                };
+
+                                partition@500000 {
+                                        /* 4MB for Compressed RFS Image */
+                                        reg = <0x00500000 0x00400000>;
+                                        label = "SPI (RO) Compressed RFS Image";
+                                        read-only;
+                                };
+
+                                partition@900000 {
+                                        /* 7MB for JFFS2 based RFS */
+                                        reg = <0x00900000 0x00700000>;
+                                        label = "SPI (RW) JFFS2 RFS";
+                                };
+                        };
+                };
+
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <76 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <79 2>;
+                        };
+                };
+
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        interrupt-parent = <&mpic>;
+                        gpio-controller;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p2020-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2,512K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-connection-type = "rgmii-id";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy0: ethernet-phy@0 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <3 1>;
+                                        reg = <0x0>;
+                                };
+                                phy1: ethernet-phy@1 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <3 1>;
+                                        reg = <0x1>;
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "sgmii";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet2: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0xbfe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                msi@41600 {
+                        compatible = "fsl,p2020-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,p2020-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 2>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 2d9fa68f641c..0dc90f9bd814 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -146,18 +146,6 @@
                         phy_type = "ulpi";
                         port0;
                 };
-                /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
-                usb@23000 {
-                        device_type = "usb";
-                        compatible = "fsl-usb2-dr";
-                        reg = <0x23000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupt-parent = <&ipic>;
-                        interrupts = <38 0x8>;
-                        dr_mode = "otg";
-                        phy_type = "ulpi";
-                };
 
                 enet0: ethernet@24000 {
                         #address-cells = <1>;
@@ -277,15 +265,55 @@
                 };
         };
 
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8349-localbus", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 0x8>;
+                interrupt-parent = <&ipic>;
+                ranges = <0x0 0x0 0xff800000 0x00800000         /* 8MB Flash */
+                          0x1 0x0 0xf8000000 0x00002000         /* 8KB EEPROM */
+                          0x2 0x0 0x10000000 0x04000000         /* 64MB SDRAM */
+                          0x3 0x0 0x10000000 0x04000000>;       /* 64MB SDRAM */
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "intel,28F640J3A", "cfi-flash";
+                        reg = <0x0 0x0 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00040000>;
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                label = "user";
+                                reg = <0x00040000 0x006c0000>;
+                        };
+
+                        partition@700000 {
+                                label = "legacy u-boot";
+                                reg = <0x00700000 0x00100000>;
+                                read-only;
+                        };
+
+                };
+        };
+
         pci0: pci@e0008500 {
                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                                 /* IDSEL 0x11 */
-                                 0x8800 0x0 0x0 0x1 &ipic 20 0x8
-                                 0x8800 0x0 0x0 0x2 &ipic 21 0x8
-                                 0x8800 0x0 0x0 0x3 &ipic 22 0x8
-                                 0x8800 0x0 0x0 0x4 &ipic 23 0x8>;
+                                 0x8800 0x0 0x0 0x1 &ipic 48 0x8
+                                 0x8800 0x0 0x0 0x2 &ipic 17 0x8
+                                 0x8800 0x0 0x0 0x3 &ipic 18 0x8
+                                 0x8800 0x0 0x0 0x4 &ipic 19 0x8>;
 
                 interrupt-parent = <&ipic>;
                 interrupts = <0x42 0x8>;
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 239d57a55cf4..9e13ed8a1193 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -303,7 +303,6 @@
                 global-utilities@e0000 {
                         compatible = "fsl,mpc8560-guts";
                         reg = <0xe0000 0x1000>;
-                        fsl,has-rstcr;
                 };
         };
 
diff --git a/arch/powerpc/boot/mktree.c b/arch/powerpc/boot/mktree.c
index c2baae0a3d89..e2ae24340fc8 100644
--- a/arch/powerpc/boot/mktree.c
+++ b/arch/powerpc/boot/mktree.c
@@ -36,7 +36,7 @@ typedef struct boot_block {
 } boot_block_t;
 
 #define IMGBLK  512
-char    tmpbuf[IMGBLK];
+unsigned int    tmpbuf[IMGBLK / sizeof(unsigned int)];
 
 int main(int argc, char *argv[])
 {
@@ -95,13 +95,13 @@ int main(int argc, char *argv[])
 
         /* Assume zImage is an ELF file, and skip the 64K header.
         */
-        if (read(in_fd, tmpbuf, IMGBLK) != IMGBLK) {
+        if (read(in_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
                 fprintf(stderr, "%s is too small to be an ELF image\n",
                                 argv[1]);
                 exit(4);
         }
 
-        if ((*(unsigned int *)tmpbuf) != htonl(0x7f454c46)) {
+        if (tmpbuf[0] != htonl(0x7f454c46)) {
                 fprintf(stderr, "%s is not an ELF image\n", argv[1]);
                 exit(4);
         }
@@ -121,11 +121,11 @@ int main(int argc, char *argv[])
         }
 
         while (nblks-- > 0) {
-                if (read(in_fd, tmpbuf, IMGBLK) < 0) {
+                if (read(in_fd, tmpbuf, sizeof(tmpbuf)) < 0) {
                         perror("zImage read");
                         exit(5);
                 }
-                cp = (unsigned int *)tmpbuf;
+                cp = tmpbuf;
                 for (i = 0; i < sizeof(tmpbuf) / sizeof(unsigned int); i++)
                         cksum += *cp++;
                 if (write(out_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
diff --git a/arch/powerpc/boot/ppcboot-hotfoot.h b/arch/powerpc/boot/ppcboot-hotfoot.h
new file mode 100644
index 000000000000..1a3e80b533da
--- /dev/null
+++ b/arch/powerpc/boot/ppcboot-hotfoot.h
@@ -0,0 +1,133 @@
+/*
+ * This interface is used for compatibility with old U-boots *ONLY*.
+ * Please do not imitate or extend this.
+ */
+
+/* 
+ * Unfortunately, the ESTeem Hotfoot board uses a mangled version of 
+ * ppcboot.h for historical reasons, and in the interest of having a 
+ * mainline kernel boot on the production board+bootloader, this was the 
+ * least-offensive solution.  Please direct all flames to:
+ *
+ *  Solomon Peachy <solomon@linux-wlan.com>
+ *
+ * (This header is identical to ppcboot.h except for the 
+ *  TARGET_HOTFOOT bits)
+ */
+
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PPCBOOT_H__
+#define __PPCBOOT_H__
+
+/*
+ * Board information passed to kernel from PPCBoot
+ *
+ * include/asm-ppc/ppcboot.h
+ */
+
+#include "types.h"
+
+typedef struct bd_info {
+        unsigned long   bi_memstart;    /* start of DRAM memory */
+        unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
+        unsigned long   bi_flashstart;  /* start of FLASH memory */
+        unsigned long   bi_flashsize;   /* size  of FLASH memory */
+        unsigned long   bi_flashoffset; /* reserved area for startup monitor */
+        unsigned long   bi_sramstart;   /* start of SRAM memory */
+        unsigned long   bi_sramsize;    /* size  of SRAM memory */
+#if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\
+        defined(TARGET_83xx)
+        unsigned long   bi_immr_base;   /* base of IMMR register */
+#endif
+#if defined(TARGET_PPC_MPC52xx)
+        unsigned long   bi_mbar_base;   /* base of internal registers */
+#endif
+        unsigned long   bi_bootflags;   /* boot / reboot flag (for LynxOS) */
+        unsigned long   bi_ip_addr;     /* IP Address */
+        unsigned char   bi_enetaddr[6]; /* Ethernet address */
+#if defined(TARGET_HOTFOOT)
+        /* second onboard ethernet port */
+        unsigned char   bi_enet1addr[6];
+#define HAVE_ENET1ADDR
+#endif /* TARGET_HOOTFOOT */
+        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
+        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
+        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
+#if defined(TARGET_CPM2)
+        unsigned long   bi_cpmfreq;     /* CPM_CLK Freq, in MHz */
+        unsigned long   bi_brgfreq;     /* BRG_CLK Freq, in MHz */
+        unsigned long   bi_sccfreq;     /* SCC_CLK Freq, in MHz */
+        unsigned long   bi_vco;         /* VCO Out from PLL, in MHz */
+#endif
+#if defined(TARGET_PPC_MPC52xx)
+        unsigned long   bi_ipbfreq;     /* IPB Bus Freq, in MHz */
+        unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
+#endif
+        unsigned long   bi_baudrate;    /* Console Baudrate */
+#if defined(TARGET_4xx)
+        unsigned char   bi_s_version[4];        /* Version of this structure */
+        unsigned char   bi_r_version[32];       /* Version of the ROM (IBM) */
+        unsigned int    bi_procfreq;    /* CPU (Internal) Freq, in Hz */
+        unsigned int    bi_plb_busfreq; /* PLB Bus speed, in Hz */
+        unsigned int    bi_pci_busfreq; /* PCI Bus speed, in Hz */
+        unsigned char   bi_pci_enetaddr[6];     /* PCI Ethernet MAC address */
+#endif
+#if defined(TARGET_HOTFOOT)
+        unsigned int     bi_pllouta_freq;       /* PLL OUTA speed, in Hz */
+#endif
+#if defined(TARGET_HYMOD)
+        hymod_conf_t    bi_hymod_conf;  /* hymod configuration information */
+#endif
+#if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
+        defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
+        /* second onboard ethernet port */
+        unsigned char   bi_enet1addr[6];
+#define HAVE_ENET1ADDR
+#endif
+#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
+    defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
+        /* third onboard ethernet ports */
+        unsigned char   bi_enet2addr[6];
+#define HAVE_ENET2ADDR
+#endif
+#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
+        /* fourth onboard ethernet ports */
+        unsigned char   bi_enet3addr[6];
+#define HAVE_ENET3ADDR
+#endif
+#if defined(TARGET_HOTFOOT)
+        int             bi_phynum[2];           /* Determines phy mapping */
+        int             bi_phymode[2];          /* Determines phy mode */
+#endif
+#if defined(TARGET_4xx)
+        unsigned int    bi_opbfreq;             /* OB clock in Hz */
+        int             bi_iic_fast[2];         /* Use fast i2c mode */
+#endif
+#if defined(TARGET_440GX)
+        int             bi_phynum[4];           /* phy mapping */
+        int             bi_phymode[4];          /* phy mode */
+#endif
+} bd_t;
+
+#define bi_tbfreq       bi_intfreq
+
+#endif  /* __PPCBOOT_H__ */
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 4db487d1d2a8..ac9e9a58b2b0 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -46,6 +46,7 @@ CROSS=
 # directory for object and other files used by this script
 object=arch/powerpc/boot
 objbin=$object
+dtc=scripts/dtc/dtc
 
 # directory for working files
 tmpdir=.
@@ -124,7 +125,7 @@ if [ -n "$dts" ]; then
     if [ -z "$dtb" ]; then
         dtb="$platform.dtb"
     fi
-    $object/dtc -O dtb -o "$dtb" -b 0 "$dts"
+    $dtc -O dtb -o "$dtb" -b 0 "$dts"
 fi
 
 if [ -z "$kernel" ]; then
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 865725effe93..9a05ec0ec312 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc7
-# Wed Jun  3 10:18:16 2009
+# Linux kernel version: 2.6.31-rc4
+# Wed Jul 29 13:28:37 2009
 #
 # CONFIG_PPC64 is not set
 
 #
 # Processor support
 #
-# CONFIG_6xx is not set
+# CONFIG_PPC_BOOK3S_32 is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 CONFIG_40x=y
@@ -32,11 +32,11 @@ CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
 CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_ARCH_NO_VIRT_TO_BUS is not set
 CONFIG_PPC=y
@@ -57,6 +57,7 @@ CONFIG_PPC_DCR_NATIVE=y
 CONFIG_PPC_DCR=y
 CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -108,7 +109,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -121,9 +121,16 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
@@ -137,6 +144,11 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
@@ -149,7 +161,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBD=y
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -220,6 +232,7 @@ CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_MATH_EMULATION is not set
 # CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
 CONFIG_PPC_NEED_DMA_SYNC_OPS=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -239,9 +252,9 @@ CONFIG_MIGRATION=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
@@ -344,6 +357,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -393,9 +407,8 @@ CONFIG_MTD_OF_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -452,7 +465,17 @@ CONFIG_MTD_PHYSMAP_OF=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -465,6 +488,7 @@ CONFIG_MTD_PHYSMAP_OF=y
 #
 # CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_FD is not set
@@ -504,14 +528,17 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -546,6 +573,7 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -621,20 +649,150 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
 CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -649,24 +807,15 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -691,10 +840,69 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -708,11 +916,12 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -818,6 +1027,7 @@ CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
 CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
 
 #
 # Kernel hacking
@@ -848,6 +1058,9 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -859,7 +1072,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -873,16 +1085,15 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
@@ -891,6 +1102,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig
index f7fd32c09424..6f976b51cdd0 100644
--- a/arch/powerpc/configs/44x/arches_defconfig
+++ b/arch/powerpc/configs/44x/arches_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
-# Tue Jan 20 08:22:31 2009
+# Linux kernel version: 2.6.31-rc5
+# Thu Aug 13 14:14:07 2009
 #
 # CONFIG_PPC64 is not set
 
 #
 # Processor support
 #
-# CONFIG_6xx is not set
+# CONFIG_PPC_BOOK3S_32 is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 # CONFIG_40x is not set
@@ -31,15 +31,16 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
 CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_ARCH_NO_VIRT_TO_BUS is not set
 CONFIG_PPC=y
@@ -53,11 +54,14 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -71,9 +75,19 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_GROUP_SCHED is not set
@@ -84,8 +98,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
@@ -95,23 +113,30 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -119,6 +144,12 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -130,8 +161,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -147,11 +177,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_FREEZER is not set
 CONFIG_PPC4xx_PCI_EXPRESS=y
 
@@ -172,6 +197,7 @@ CONFIG_PPC4xx_PCI_EXPRESS=y
 CONFIG_ARCHES=y
 # CONFIG_CANYONLANDS is not set
 # CONFIG_GLACIER is not set
+# CONFIG_REDWOOD is not set
 # CONFIG_YOSEMITE is not set
 # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
 CONFIG_PPC44x_SIMPLE=y
@@ -214,6 +240,7 @@ CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_MATH_EMULATION is not set
 # CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
 CONFIG_PPC_NEED_DMA_SYNC_OPS=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -233,10 +260,14 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_STDBINUTILS=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 CONFIG_CMDLINE_BOOL=y
@@ -261,6 +292,7 @@ CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -278,14 +310,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -335,6 +365,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -347,7 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -371,8 +402,92 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_FD is not set
@@ -412,7 +527,11 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -433,6 +552,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -451,6 +572,7 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -461,7 +583,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -533,13 +654,143 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+CONFIG_SENSORS_AD7414=y
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
 # CONFIG_THERMAL is not set
 # CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
@@ -556,24 +807,15 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -600,7 +842,12 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -614,11 +861,12 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -628,6 +876,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -660,6 +913,17 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -670,6 +934,7 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -681,7 +946,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -697,6 +961,7 @@ CONFIG_SUNRPC=y
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
@@ -711,11 +976,14 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
 
 #
 # Kernel hacking
@@ -733,6 +1001,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -743,6 +1014,9 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -754,7 +1028,6 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -762,27 +1035,36 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-
-#
-# Tracers
-#
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PPC_EMULATED_STATS is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index 5e85412eb9fa..b312b166be66 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc3
-# Mon Feb  2 13:13:04 2009
+# Linux kernel version: 2.6.31-rc4
+# Wed Jul 29 17:27:20 2009
 #
 # CONFIG_PPC64 is not set
 
 #
 # Processor support
 #
-# CONFIG_6xx is not set
+# CONFIG_PPC_BOOK3S_32 is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 # CONFIG_40x is not set
@@ -31,15 +31,16 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
 CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_ARCH_NO_VIRT_TO_BUS is not set
 CONFIG_PPC=y
@@ -53,11 +54,14 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -71,6 +75,7 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
@@ -93,8 +98,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
@@ -104,23 +113,30 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -128,6 +144,12 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -139,8 +161,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -176,6 +197,7 @@ CONFIG_PPC4xx_PCI_EXPRESS=y
 # CONFIG_ARCHES is not set
 CONFIG_CANYONLANDS=y
 # CONFIG_GLACIER is not set
+# CONFIG_REDWOOD is not set
 # CONFIG_YOSEMITE is not set
 # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
 CONFIG_PPC44x_SIMPLE=y
@@ -218,6 +240,7 @@ CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_MATH_EMULATION is not set
 # CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
 CONFIG_PPC_NEED_DMA_SYNC_OPS=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -237,10 +260,14 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_STDBINUTILS=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 CONFIG_CMDLINE_BOOL=y
@@ -265,6 +292,7 @@ CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -282,14 +310,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -339,6 +365,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -351,7 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -375,7 +402,101 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 CONFIG_OF_I2C=y
 # CONFIG_PARPORT is not set
@@ -418,7 +539,11 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -439,6 +564,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -457,6 +584,7 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -467,7 +595,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -542,7 +669,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -608,14 +734,17 @@ CONFIG_I2C_IBM_IIC=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
@@ -640,6 +769,7 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -654,11 +784,14 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
 # CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_SIS5595 is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -666,6 +799,7 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_VT8231 is not set
@@ -700,24 +834,9 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -759,6 +878,7 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
 CONFIG_USB_EHCI_HCD=m
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
@@ -767,9 +887,9 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PPC_OF=y
 CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
 CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_OHCI_HCD_PPC_OF=y
 CONFIG_USB_OHCI_HCD_PCI=y
 CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
 CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
@@ -789,11 +909,11 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_LIBUSUAL=y
 
@@ -821,7 +941,6 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -837,6 +956,7 @@ CONFIG_USB_LIBUSUAL=y
 #
 # OTG and related infrastructure
 #
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_UWB is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -844,9 +964,70 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -860,11 +1041,12 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -874,6 +1056,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -906,6 +1093,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -916,6 +1104,7 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -927,7 +1116,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -941,8 +1129,48 @@ CONFIG_SUNRPC=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
@@ -957,11 +1185,13 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
 
 #
 # Kernel hacking
@@ -979,6 +1209,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -989,6 +1222,9 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -1000,7 +1236,6 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -1008,27 +1243,36 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-
-#
-# Tracers
-#
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PPC_EMULATED_STATS is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
diff --git a/arch/powerpc/configs/44x/eiger_defconfig b/arch/powerpc/configs/44x/eiger_defconfig
new file mode 100644
index 000000000000..007f3bd939e7
--- /dev/null
+++ b/arch/powerpc/configs/44x/eiger_defconfig
@@ -0,0 +1,1252 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc6
+# Wed Aug 19 13:06:50 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_PPC_BOOK3S_32 is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_4xx=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_MMU_NOHASH_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_BAMBOO is not set
+# CONFIG_EBONY is not set
+# CONFIG_SAM440EP is not set
+# CONFIG_SEQUOIA is not set
+# CONFIG_TAISHAN is not set
+# CONFIG_KATMAI is not set
+# CONFIG_RAINIER is not set
+# CONFIG_WARP is not set
+# CONFIG_ARCHES is not set
+# CONFIG_CANYONLANDS is not set
+# CONFIG_GLACIER is not set
+# CONFIG_REDWOOD is not set
+CONFIG_EIGER=y
+# CONFIG_YOSEMITE is not set
+# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
+CONFIG_PPC44x_SIMPLE=y
+# CONFIG_PPC4xx_GPIO is not set
+CONFIG_460SX=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_PPC_NEED_DMA_SYNC_OPS=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_STDBINUTILS=y
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_EXTRA_TARGETS=""
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_4xx_SOC=y
+CONFIG_PPC_PCI_CHOICE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIE_ECRC is not set
+# CONFIG_PCIEAER_INJECT is not set
+# CONFIG_PCIEASPM is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_FUSION=y
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+CONFIG_FUSION_SAS=y
+CONFIG_FUSION_MAX_SGE=128
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LOGGING is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+CONFIG_I2O=y
+CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y
+CONFIG_I2O_EXT_ADAPTEC=y
+# CONFIG_I2O_CONFIG is not set
+# CONFIG_I2O_BUS is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=256
+CONFIG_IBM_NEW_EMAC_TXB=256
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+CONFIG_IBM_NEW_EMAC_TAH=y
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=y
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_XILINX_LL_TEMAC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_I2C_DEBUG_CORE=y
+CONFIG_I2C_DEBUG_ALGO=y
+CONFIG_I2C_DEBUG_BUS=y
+CONFIG_I2C_DEBUG_CHIP=y
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_PPC_EMULATED_STATS is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_PPC4XX is not set
+# CONFIG_PPC_CLOCK is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/83xx/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig
index a592b5efdc4d..3a68f861b1bd 100644
--- a/arch/powerpc/configs/83xx/sbc834x_defconfig
+++ b/arch/powerpc/configs/83xx/sbc834x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc4
-# Wed Jul 29 23:32:13 2009
+# Linux kernel version: 2.6.31-rc5
+# Tue Aug 11 19:57:51 2009
 #
 # CONFIG_PPC64 is not set
 
@@ -420,7 +420,90 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 CONFIG_OF_I2C=y
 CONFIG_OF_MDIO=y
@@ -436,6 +519,7 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=32768
@@ -468,9 +552,38 @@ CONFIG_HAVE_IDE=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
@@ -578,11 +691,21 @@ CONFIG_GIANFAR=y
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -633,9 +756,9 @@ CONFIG_DEVKMEM=y
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 # CONFIG_SERIAL_8250_EXTENDED is not set
 
 #
@@ -700,6 +823,7 @@ CONFIG_I2C_MPC=y
 #
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Graphics adapter I2C/DDC channel drivers
@@ -814,6 +938,11 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_PCIPCWATCHDOG is not set
 # CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
 #
@@ -856,12 +985,134 @@ CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
 # CONFIG_HID_PID is not set
 
 #
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
 # Special HID drivers
 #
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PPC_OF=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_UWB is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -882,9 +1133,14 @@ CONFIG_HID=y
 #
 # File systems
 #
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
 # CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
@@ -940,6 +1196,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -977,7 +1234,46 @@ CONFIG_RPCSEC_GSS_KRB5=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
 # CONFIG_BINARY_PRINTF is not set
 
diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig
index e9491c1c3f31..30b68bfacebf 100644
--- a/arch/powerpc/configs/mgcoge_defconfig
+++ b/arch/powerpc/configs/mgcoge_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc4
-# Wed Jul 29 23:31:51 2009
+# Linux kernel version: 2.6.31-rc5
+# Fri Aug  7 08:19:15 2009
 #
 # CONFIG_PPC64 is not set
 
@@ -158,6 +158,7 @@ CONFIG_BASE_SMALL=0
 # CONFIG_MODULES is not set
 CONFIG_BLOCK=y
 CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
@@ -506,6 +507,7 @@ CONFIG_MTD_PHYSMAP_OF=y
 # CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
 CONFIG_OF_MDIO=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
@@ -582,7 +584,8 @@ CONFIG_PHYLIB=y
 # CONFIG_STE10XP is not set
 # CONFIG_LSI_ET1011C_PHY is not set
 CONFIG_FIXED_PHY=y
-# CONFIG_MDIO_BITBANG is not set
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_GPIO is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_MACE is not set
@@ -608,8 +611,8 @@ CONFIG_MII=y
 # CONFIG_ATL2 is not set
 CONFIG_FS_ENET=y
 CONFIG_FS_ENET_HAS_SCC=y
-# CONFIG_FS_ENET_HAS_FCC is not set
-# CONFIG_FS_ENET_MDIO_FCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_FS_ENET_MDIO_FCC=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
@@ -680,7 +683,68 @@ CONFIG_HW_RANDOM=y
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# Mac SMBus host controller drivers
+#
+# CONFIG_I2C_POWERMAC is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_CPM=y
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_PCF8575 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
 
 #
@@ -699,6 +763,9 @@ CONFIG_GPIOLIB=y
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
 
 #
 # PCI GPIO expanders:
@@ -727,7 +794,14 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index ada595898af1..ee6acc6557f8 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -203,6 +203,7 @@ CONFIG_MPC85xx_CDS=y
 CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
+CONFIG_MPC85xx_RDB=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 # CONFIG_XES_MPC85xx is not set
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 897eade3afbe..56f2f2ea5631 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -56,174 +56,102 @@
 #define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
 #define BITOP_LE_SWIZZLE        ((BITS_PER_LONG-1) & ~0x7)
 
+/* Macro for generating the ***_bits() functions */
+#define DEFINE_BITOP(fn, op, prefix, postfix)   \
+static __inline__ void fn(unsigned long mask,   \
+                volatile unsigned long *_p)     \
+{                                               \
+        unsigned long old;                      \
+        unsigned long *p = (unsigned long *)_p; \
+        __asm__ __volatile__ (                  \
+        prefix                                  \
+"1:"    PPC_LLARX "%0,0,%3\n"                   \
+        stringify_in_c(op) "%0,%0,%2\n"         \
+        PPC405_ERR77(0,%3)                      \
+        PPC_STLCX "%0,0,%3\n"                   \
+        "bne- 1b\n"                             \
+        postfix                                 \
+        : "=&r" (old), "+m" (*p)                \
+        : "r" (mask), "r" (p)                   \
+        : "cc", "memory");                      \
+}
+
+DEFINE_BITOP(set_bits, or, "", "")
+DEFINE_BITOP(clear_bits, andc, "", "")
+DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "")
+DEFINE_BITOP(change_bits, xor, "", "")
+
 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # set_bit\n"
-        "or     %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # clear_bit\n"
-        "andc   %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3      # clear_bit_unlock\n"
-        "andc   %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
+        clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void change_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # change_bit\n"
-        "xor    %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
+}
+
+/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
+ * operands. */
+#define DEFINE_TESTOP(fn, op, prefix, postfix)  \
+static __inline__ unsigned long fn(             \
+                unsigned long mask,             \
+                volatile unsigned long *_p)     \
+{                                               \
+        unsigned long old, t;                   \
+        unsigned long *p = (unsigned long *)_p; \
+        __asm__ __volatile__ (                  \
+        prefix                                  \
+"1:"    PPC_LLARX "%0,0,%3\n"                   \
+        stringify_in_c(op) "%1,%0,%2\n"         \
+        PPC405_ERR77(0,%3)                      \
+        PPC_STLCX "%1,0,%3\n"                   \
+        "bne- 1b\n"                             \
+        postfix                                 \
+        : "=&r" (old), "=&r" (t)                \
+        : "r" (mask), "r" (p)                   \
+        : "cc", "memory");                      \
+        return (old & mask);                    \
 }
 
+DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+
 static __inline__ int test_and_set_bit(unsigned long nr,
                                        volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit\n"
-        "or     %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_set_bit_lock(unsigned long nr,
                                        volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit_lock\n"
-        "or     %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_set_bits_lock(BITOP_MASK(nr),
+                                addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_clear_bit(unsigned long nr,
                                          volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_clear_bit\n"
-        "andc   %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_change_bit(unsigned long nr,
                                           volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_change_bit\n"
-        "xor    %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
-}
-
-static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
-{
-        unsigned long old;
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3         # set_bits\n"
-        "or     %0,%0,%2\n"
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*addr)
-        : "r" (mask), "r" (addr)
-        : "cc");
+        return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 #include <asm-generic/bitops/non-atomic.h>
diff --git a/arch/powerpc/include/asm/cell-regs.h b/arch/powerpc/include/asm/cell-regs.h
index fd6fd00434ef..fdf64fd25950 100644
--- a/arch/powerpc/include/asm/cell-regs.h
+++ b/arch/powerpc/include/asm/cell-regs.h
@@ -303,6 +303,17 @@ struct cbe_mic_tm_regs {
 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 
+
+/* Cell page table entries */
+#define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
+#define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
+#define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
+#define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
+#define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
+#define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
+#define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
+#define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
+
 /* some utility functions to deal with SMT */
 extern u32 cbe_get_hw_thread_id(int cpu);
 extern u32 cbe_cpu_to_node(int cpu);
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index fb11b0c459b8..a8e18447c62b 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -5,6 +5,15 @@
 
 /*
  * Mapping of threads to cores
+ *
+ * Note: This implementation is limited to a power of 2 number of
+ * threads per core and the same number for each core in the system
+ * (though it would work if some processors had less threads as long
+ * as the CPU numbers are still allocated, just not brought offline).
+ *
+ * However, the API allows for a different implementation in the future
+ * if needed, as long as you only use the functions and not the variables
+ * directly.
  */
 
 #ifdef CONFIG_SMP
@@ -67,5 +76,12 @@ static inline int cpu_first_thread_in_core(int cpu)
         return cpu & ~(threads_per_core - 1);
 }
 
+static inline int cpu_last_thread_in_core(int cpu)
+{
+        return cpu | (threads_per_core - 1);
+}
+
+
+
 #endif /* _ASM_POWERPC_CPUTHREADS_H */
 
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index e3e06e0f7fc0..9dade15d1ab4 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -6,7 +6,7 @@
 #ifndef _ASM_POWERPC_DEVICE_H
 #define _ASM_POWERPC_DEVICE_H
 
-struct dma_mapping_ops;
+struct dma_map_ops;
 struct device_node;
 
 struct dev_archdata {
@@ -14,8 +14,11 @@ struct dev_archdata {
         struct device_node      *of_node;
 
         /* DMA operations on that device */
-        struct dma_mapping_ops  *dma_ops;
+        struct dma_map_ops      *dma_ops;
         void                    *dma_data;
+#ifdef CONFIG_SWIOTLB
+        dma_addr_t              max_direct_dma_addr;
+#endif
 };
 
 static inline void dev_archdata_set_node(struct dev_archdata *ad,
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 0c34371ec49c..cb2ca41dd526 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
 #include <linux/dma-attrs.h>
+#include <linux/dma-debug.h>
 #include <asm/io.h>
 #include <asm/swiotlb.h>
 
@@ -64,58 +65,14 @@ static inline unsigned long device_to_mask(struct device *dev)
 }
 
 /*
- * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
- */
-struct dma_mapping_ops {
-        void *          (*alloc_coherent)(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t flag);
-        void            (*free_coherent)(struct device *dev, size_t size,
-                                void *vaddr, dma_addr_t dma_handle);
-        int             (*map_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction,
-                                struct dma_attrs *attrs);
-        void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction,
-                                struct dma_attrs *attrs);
-        int             (*dma_supported)(struct device *dev, u64 mask);
-        int             (*set_dma_mask)(struct device *dev, u64 dma_mask);
-        dma_addr_t      (*map_page)(struct device *dev, struct page *page,
-                                unsigned long offset, size_t size,
-                                enum dma_data_direction direction,
-                                struct dma_attrs *attrs);
-        void            (*unmap_page)(struct device *dev,
-                                dma_addr_t dma_address, size_t size,
-                                enum dma_data_direction direction,
-                                struct dma_attrs *attrs);
-        int             (*addr_needs_map)(struct device *dev, dma_addr_t addr,
-                                size_t size);
-#ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS
-        void            (*sync_single_range_for_cpu)(struct device *hwdev,
-                                dma_addr_t dma_handle, unsigned long offset,
-                                size_t size,
-                                enum dma_data_direction direction);
-        void            (*sync_single_range_for_device)(struct device *hwdev,
-                                dma_addr_t dma_handle, unsigned long offset,
-                                size_t size,
-                                enum dma_data_direction direction);
-        void            (*sync_sg_for_cpu)(struct device *hwdev,
-                                struct scatterlist *sg, int nelems,
-                                enum dma_data_direction direction);
-        void            (*sync_sg_for_device)(struct device *hwdev,
-                                struct scatterlist *sg, int nelems,
-                                enum dma_data_direction direction);
-#endif
-};
-
-/*
  * Available generic sets of operations
  */
 #ifdef CONFIG_PPC64
-extern struct dma_mapping_ops dma_iommu_ops;
+extern struct dma_map_ops dma_iommu_ops;
 #endif
-extern struct dma_mapping_ops dma_direct_ops;
+extern struct dma_map_ops dma_direct_ops;
 
-static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 {
         /* We don't handle the NULL dev case for ISA for now. We could
          * do it via an out of line call but it is not needed for now. The
@@ -128,14 +85,19 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
         return dev->archdata.dma_ops;
 }
 
-static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
+static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
 {
         dev->archdata.dma_ops = ops;
 }
 
+/* this will be removed soon */
+#define flush_write_buffers()
+
+#include <asm-generic/dma-mapping-common.h>
+
 static inline int dma_supported(struct device *dev, u64 mask)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
         if (unlikely(dma_ops == NULL))
                 return 0;
@@ -149,7 +111,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
 
 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
         if (unlikely(dma_ops == NULL))
                 return -EIO;
@@ -161,262 +123,40 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
         return 0;
 }
 
-/*
- * map_/unmap_single actually call through to map/unmap_page now that all the
- * dma_mapping_ops have been converted over. We just have to get the page and
- * offset to pass through to map_page
- */
-static inline dma_addr_t dma_map_single_attrs(struct device *dev,
-                                              void *cpu_addr,
-                                              size_t size,
-                                              enum dma_data_direction direction,
-                                              struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        return dma_ops->map_page(dev, virt_to_page(cpu_addr),
-                                 (unsigned long)cpu_addr % PAGE_SIZE, size,
-                                 direction, attrs);
-}
-
-static inline void dma_unmap_single_attrs(struct device *dev,
-                                          dma_addr_t dma_addr,
-                                          size_t size,
-                                          enum dma_data_direction direction,
-                                          struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        dma_ops->unmap_page(dev, dma_addr, size, direction, attrs);
-}
-
-static inline dma_addr_t dma_map_page_attrs(struct device *dev,
-                                            struct page *page,
-                                            unsigned long offset, size_t size,
-                                            enum dma_data_direction direction,
-                                            struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        return dma_ops->map_page(dev, page, offset, size, direction, attrs);
-}
-
-static inline void dma_unmap_page_attrs(struct device *dev,
-                                        dma_addr_t dma_address,
-                                        size_t size,
-                                        enum dma_data_direction direction,
-                                        struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        dma_ops->unmap_page(dev, dma_address, size, direction, attrs);
-}
-
-static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
-                                   int nents, enum dma_data_direction direction,
-                                   struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        return dma_ops->map_sg(dev, sg, nents, direction, attrs);
-}
-
-static inline void dma_unmap_sg_attrs(struct device *dev,
-                                      struct scatterlist *sg,
-                                      int nhwentries,
-                                      enum dma_data_direction direction,
-                                      struct dma_attrs *attrs)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
-}
-
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
                                        dma_addr_t *dma_handle, gfp_t flag)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
-}
-
-static inline void dma_free_coherent(struct device *dev, size_t size,
-                                     void *cpu_addr, dma_addr_t dma_handle)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
-}
-
-static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
-                                        size_t size,
-                                        enum dma_data_direction direction)
-{
-        return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
-}
-
-static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                                    size_t size,
-                                    enum dma_data_direction direction)
-{
-        dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
-}
-
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction direction)
-{
-        return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
-}
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-                                  size_t size,
-                                  enum dma_data_direction direction)
-{
-        dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
-}
-
-static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
-                             int nents, enum dma_data_direction direction)
-{
-        return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
-}
-
-static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                                int nhwentries,
-                                enum dma_data_direction direction)
-{
-        dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
-}
-
-#ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS
-static inline void dma_sync_single_for_cpu(struct device *dev,
-                dma_addr_t dma_handle, size_t size,
-                enum dma_data_direction direction)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        if (dma_ops->sync_single_range_for_cpu)
-                dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0,
-                                           size, direction);
-}
-
-static inline void dma_sync_single_for_device(struct device *dev,
-                dma_addr_t dma_handle, size_t size,
-                enum dma_data_direction direction)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        if (dma_ops->sync_single_range_for_device)
-                dma_ops->sync_single_range_for_device(dev, dma_handle,
-                                              0, size, direction);
-}
-
-static inline void dma_sync_sg_for_cpu(struct device *dev,
-                struct scatterlist *sgl, int nents,
-                enum dma_data_direction direction)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
+        void *cpu_addr;
 
         BUG_ON(!dma_ops);
 
-        if (dma_ops->sync_sg_for_cpu)
-                dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction);
-}
-
-static inline void dma_sync_sg_for_device(struct device *dev,
-                struct scatterlist *sgl, int nents,
-                enum dma_data_direction direction)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
-
-        BUG_ON(!dma_ops);
-
-        if (dma_ops->sync_sg_for_device)
-                dma_ops->sync_sg_for_device(dev, sgl, nents, direction);
-}
-
-static inline void dma_sync_single_range_for_cpu(struct device *dev,
-                dma_addr_t dma_handle, unsigned long offset, size_t size,
-                enum dma_data_direction direction)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        cpu_addr = dma_ops->alloc_coherent(dev, size, dma_handle, flag);
 
-        BUG_ON(!dma_ops);
+        debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
 
-        if (dma_ops->sync_single_range_for_cpu)
-                dma_ops->sync_single_range_for_cpu(dev, dma_handle,
-                                           offset, size, direction);
+        return cpu_addr;
 }
 
-static inline void dma_sync_single_range_for_device(struct device *dev,
-                dma_addr_t dma_handle, unsigned long offset, size_t size,
-                enum dma_data_direction direction)
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *cpu_addr, dma_addr_t dma_handle)
 {
-        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
         BUG_ON(!dma_ops);
 
-        if (dma_ops->sync_single_range_for_device)
-                dma_ops->sync_single_range_for_device(dev, dma_handle, offset,
-                                              size, direction);
-}
-#else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */
-static inline void dma_sync_single_for_cpu(struct device *dev,
-                dma_addr_t dma_handle, size_t size,
-                enum dma_data_direction direction)
-{
-}
-
-static inline void dma_sync_single_for_device(struct device *dev,
-                dma_addr_t dma_handle, size_t size,
-                enum dma_data_direction direction)
-{
-}
-
-static inline void dma_sync_sg_for_cpu(struct device *dev,
-                struct scatterlist *sgl, int nents,
-                enum dma_data_direction direction)
-{
-}
+        debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
 
-static inline void dma_sync_sg_for_device(struct device *dev,
-                struct scatterlist *sgl, int nents,
-                enum dma_data_direction direction)
-{
+        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
 }
 
-static inline void dma_sync_single_range_for_cpu(struct device *dev,
-                dma_addr_t dma_handle, unsigned long offset, size_t size,
-                enum dma_data_direction direction)
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
-}
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
-static inline void dma_sync_single_range_for_device(struct device *dev,
-                dma_addr_t dma_handle, unsigned long offset, size_t size,
-                enum dma_data_direction direction)
-{
-}
-#endif
+        if (dma_ops->mapping_error)
+                return dma_ops->mapping_error(dev, dma_addr);
 
-static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
 #ifdef CONFIG_PPC64
         return (dma_addr == DMA_ERROR_CODE);
 #else
@@ -426,10 +166,12 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 
 static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
 {
-        struct dma_mapping_ops *ops = get_dma_ops(dev);
+#ifdef CONFIG_SWIOTLB
+        struct dev_archdata *sd = &dev->archdata;
 
-        if (ops->addr_needs_map && ops->addr_needs_map(dev, addr, size))
+        if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
                 return 0;
+#endif
 
         if (!dev->dma_mask)
                 return 0;
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
new file mode 100644
index 000000000000..6d53f311d942
--- /dev/null
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -0,0 +1,205 @@
+/*
+ *  Definitions for use by exception code on Book3-E
+ *
+ *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_EXCEPTION_64E_H
+#define _ASM_POWERPC_EXCEPTION_64E_H
+
+/*
+ * SPRGs usage an other considerations...
+ *
+ * Since TLB miss and other standard exceptions can be interrupted by
+ * critical exceptions which can themselves be interrupted by machine
+ * checks, and since the two later can themselves cause a TLB miss when
+ * hitting the linear mapping for the kernel stacks, we need to be a bit
+ * creative on how we use SPRGs.
+ *
+ * The base idea is that we have one SRPG reserved for critical and one
+ * for machine check interrupts. Those are used to save a GPR that can
+ * then be used to get the PACA, and store as much context as we need
+ * to save in there. That includes saving the SPRGs used by the TLB miss
+ * handler for linear mapping misses and the associated SRR0/1 due to
+ * the above re-entrancy issue.
+ *
+ * So here's the current usage pattern. It's done regardless of which
+ * SPRGs are user-readable though, thus we might have to change some of
+ * this later. In order to do that more easily, we use special constants
+ * for naming them
+ *
+ * WARNING: Some of these SPRGs are user readable. We need to do something
+ * about it as some point by making sure they can't be used to leak kernel
+ * critical data
+ */
+
+
+/* We are out of SPRGs so we save some things in the PACA. The normal
+ * exception frame is smaller than the CRIT or MC one though
+ */
+#define EX_R1           (0 * 8)
+#define EX_CR           (1 * 8)
+#define EX_R10          (2 * 8)
+#define EX_R11          (3 * 8)
+#define EX_R14          (4 * 8)
+#define EX_R15          (5 * 8)
+
+/* The TLB miss exception uses different slots */
+
+#define EX_TLB_R10      ( 0 * 8)
+#define EX_TLB_R11      ( 1 * 8)
+#define EX_TLB_R12      ( 2 * 8)
+#define EX_TLB_R13      ( 3 * 8)
+#define EX_TLB_R14      ( 4 * 8)
+#define EX_TLB_R15      ( 5 * 8)
+#define EX_TLB_R16      ( 6 * 8)
+#define EX_TLB_CR       ( 7 * 8)
+#define EX_TLB_DEAR     ( 8 * 8) /* Level 0 and 2 only */
+#define EX_TLB_ESR      ( 9 * 8) /* Level 0 and 2 only */
+#define EX_TLB_SRR0     (10 * 8)
+#define EX_TLB_SRR1     (11 * 8)
+#define EX_TLB_MMUCR0   (12 * 8) /* Level 0 */
+#define EX_TLB_MAS1     (12 * 8) /* Level 0 */
+#define EX_TLB_MAS2     (13 * 8) /* Level 0 */
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+#define EX_TLB_R8       (14 * 8)
+#define EX_TLB_R9       (15 * 8)
+#define EX_TLB_LR       (16 * 8)
+#define EX_TLB_SIZE     (17 * 8)
+#else
+#define EX_TLB_SIZE     (14 * 8)
+#endif
+
+#define START_EXCEPTION(label)                                          \
+        .globl exc_##label##_book3e;                                    \
+exc_##label##_book3e:
+
+/* TLB miss exception prolog
+ *
+ * This prolog handles re-entrancy (up to 3 levels supported in the PACA
+ * though we currently don't test for overflow). It provides you with a
+ * re-entrancy safe working space of r10...r16 and CR with r12 being used
+ * as the exception area pointer in the PACA for that level of re-entrancy
+ * and r13 containing the PACA pointer.
+ *
+ * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
+ * as-is for instruction exceptions. It's up to the actual exception code
+ * to save them as well if required.
+ */
+#define TLB_MISS_PROLOG                                                     \
+        mtspr   SPRN_SPRG_TLB_SCRATCH,r12;                                  \
+        mfspr   r12,SPRN_SPRG_TLB_EXFRAME;                                  \
+        std     r10,EX_TLB_R10(r12);                                        \
+        mfcr    r10;                                                        \
+        std     r11,EX_TLB_R11(r12);                                        \
+        mfspr   r11,SPRN_SPRG_TLB_SCRATCH;                                  \
+        std     r13,EX_TLB_R13(r12);                                        \
+        mfspr   r13,SPRN_SPRG_PACA;                                         \
+        std     r14,EX_TLB_R14(r12);                                        \
+        addi    r14,r12,EX_TLB_SIZE;                                        \
+        std     r15,EX_TLB_R15(r12);                                        \
+        mfspr   r15,SPRN_SRR1;                                              \
+        std     r16,EX_TLB_R16(r12);                                        \
+        mfspr   r16,SPRN_SRR0;                                              \
+        std     r10,EX_TLB_CR(r12);                                         \
+        std     r11,EX_TLB_R12(r12);                                        \
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r14;                                  \
+        std     r15,EX_TLB_SRR1(r12);                                       \
+        std     r16,EX_TLB_SRR0(r12);                                       \
+        TLB_MISS_PROLOG_STATS
+
+/* And these are the matching epilogs that restores things
+ *
+ * There are 3 epilogs:
+ *
+ * - SUCCESS       : Unwinds one level
+ * - ERROR         : restore from level 0 and reset
+ * - ERROR_SPECIAL : restore from current level and reset
+ *
+ * Normal errors use ERROR, that is, they restore the initial fault context
+ * and trigger a fault. However, there is a special case for linear mapping
+ * errors. Those should basically never happen, but if they do happen, we
+ * want the error to point out the context that did that linear mapping
+ * fault, not the initial level 0 (basically, we got a bogus PGF or something
+ * like that). For userland errors on the linear mapping, there is no
+ * difference since those are always level 0 anyway
+ */
+
+#define TLB_MISS_RESTORE(freg)                                              \
+        ld      r14,EX_TLB_CR(r12);                                         \
+        ld      r10,EX_TLB_R10(r12);                                        \
+        ld      r15,EX_TLB_SRR0(r12);                                       \
+        ld      r16,EX_TLB_SRR1(r12);                                       \
+        mtspr   SPRN_SPRG_TLB_EXFRAME,freg;                                 \
+        ld      r11,EX_TLB_R11(r12);                                        \
+        mtcr    r14;                                                        \
+        ld      r13,EX_TLB_R13(r12);                                        \
+        ld      r14,EX_TLB_R14(r12);                                        \
+        mtspr   SPRN_SRR0,r15;                                              \
+        ld      r15,EX_TLB_R15(r12);                                        \
+        mtspr   SPRN_SRR1,r16;                                              \
+        TLB_MISS_RESTORE_STATS                                              \
+        ld      r16,EX_TLB_R16(r12);                                        \
+        ld      r12,EX_TLB_R12(r12);                                        \
+
+#define TLB_MISS_EPILOG_SUCCESS                                             \
+        TLB_MISS_RESTORE(r12)
+
+#define TLB_MISS_EPILOG_ERROR                                               \
+        addi    r12,r13,PACA_EXTLB;                                         \
+        TLB_MISS_RESTORE(r12)
+
+#define TLB_MISS_EPILOG_ERROR_SPECIAL                                       \
+        addi    r11,r13,PACA_EXTLB;                                         \
+        TLB_MISS_RESTORE(r11)
+
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+#define TLB_MISS_PROLOG_STATS                                               \
+        mflr    r10;                                                        \
+        std     r8,EX_TLB_R8(r12);                                          \
+        std     r9,EX_TLB_R9(r12);                                          \
+        std     r10,EX_TLB_LR(r12);
+#define TLB_MISS_RESTORE_STATS                                              \
+        ld      r16,EX_TLB_LR(r12);                                         \
+        ld      r9,EX_TLB_R9(r12);                                          \
+        ld      r8,EX_TLB_R8(r12);                                          \
+        mtlr    r16;
+#define TLB_MISS_STATS_D(name)                                              \
+        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
+        bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_I(name)                                              \
+        addi    r9,r13,MMSTAT_ISTATS+name;                                  \
+        bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_X(name)                                              \
+        ld      r8,PACA_EXTLB+EX_TLB_ESR(r13);                              \
+        cmpdi   cr2,r8,-1;                                                  \
+        beq     cr2,61f;                                                    \
+        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
+        b       62f;                                                        \
+61:     addi    r9,r13,MMSTAT_ISTATS+name;                                  \
+62:     bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_SAVE_INFO                                            \
+        std     r14,EX_TLB_ESR(r12);    /* save ESR */                      \
+
+
+#else
+#define TLB_MISS_PROLOG_STATS
+#define TLB_MISS_RESTORE_STATS
+#define TLB_MISS_STATS_D(name)
+#define TLB_MISS_STATS_I(name)
+#define TLB_MISS_STATS_X(name)
+#define TLB_MISS_STATS_Y(name)
+#define TLB_MISS_STATS_SAVE_INFO
+#endif
+
+#define SET_IVOR(vector_number, vector_offset)  \
+        li      r3,vector_offset@l;             \
+        ori     r3,r3,interrupt_base_book3e@l;  \
+        mtspr   SPRN_IVOR##vector_number,r3;
+
+#endif /* _ASM_POWERPC_EXCEPTION_64E_H */
+
diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception-64s.h
index d3d4534e3c74..a98653b26231 100644
--- a/arch/powerpc/include/asm/exception.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -57,17 +57,16 @@
         addi    reg,reg,(label)-_stext; /* virt addr of handler ... */
 
 #define EXCEPTION_PROLOG_1(area)                                \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
         std     r10,area+EX_R10(r13);                                   \
         std     r11,area+EX_R11(r13);                                   \
         std     r12,area+EX_R12(r13);                                   \
-        mfspr   r9,SPRN_SPRG1;                                          \
+        mfspr   r9,SPRN_SPRG_SCRATCH0;                                  \
         std     r9,area+EX_R13(r13);                                    \
         mfcr    r9
 
-#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
-        EXCEPTION_PROLOG_1(area);                                       \
+#define EXCEPTION_PROLOG_PSERIES_1(label)                               \
         ld      r12,PACAKBASE(r13);     /* get high part of &label */   \
         ld      r10,PACAKMSR(r13);      /* get MSR value for kernel */  \
         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
@@ -78,6 +77,10 @@
         rfid;                                                           \
         b       .       /* prevent speculative execution */
 
+#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
+        EXCEPTION_PROLOG_1(area);                                       \
+        EXCEPTION_PROLOG_PSERIES_1(label);
+
 /*
  * The common exception prolog is used for all except a few exceptions
  * such as a segment miss on a kernel address.  We have to be prepared
@@ -144,7 +147,7 @@
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 
 #define HSTD_EXCEPTION_PSERIES(n, label)                \
@@ -152,13 +155,13 @@ label##_pSeries:					\
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r20; /* save r20 */  \
         mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
         mtspr   SPRN_SRR0,r20;                          \
         mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
         mtspr   SPRN_SRR1,r20;                          \
-        mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mfspr   r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 
 
@@ -167,15 +170,15 @@ label##_pSeries:					\
         .globl label##_pSeries;                                         \
 label##_pSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
         std     r10,PACA_EXGEN+EX_R10(r13);                             \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         mfcr    r9;                                                     \
         cmpwi   r10,0;                                                  \
         beq     masked_interrupt;                                       \
-        mfspr   r10,SPRN_SPRG1;                                         \
+        mfspr   r10,SPRN_SPRG_SCRATCH0;                                 \
         std     r10,PACA_EXGEN+EX_R13(r13);                             \
         std     r11,PACA_EXGEN+EX_R11(r13);                             \
         std     r12,PACA_EXGEN+EX_R12(r13);                             \
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 288e14d53b7f..fb3c05a0cbbf 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -1,29 +1 @@
-#ifndef _ASM_POWERPC_HARDIRQ_H
-#define _ASM_POWERPC_HARDIRQ_H
-#ifdef __KERNEL__
-
-#include <asm/irq.h>
-#include <asm/bug.h>
-
-/* The __last_jiffy_stamp field is needed to ensure that no decrementer
- * interrupt is lost on SMP machines. Since on most CPUs it is in the same
- * cache line as local_irq_count, it is cheap to access and is also used on UP
- * for uniformity.
- */
-typedef struct {
-        unsigned int __softirq_pending; /* set_bit is used on this */
-        unsigned int __last_jiffy_stamp;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
-
-static inline void ack_bad_irq(int irq)
-{
-        printk(KERN_CRIT "illegal vector %d received!\n", irq);
-        BUG();
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_HARDIRQ_H */
+#include <asm-generic/hardirq.h>
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 8b505eaaa38a..e73d554538dd 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -49,8 +49,13 @@ extern void iseries_handle_interrupts(void);
 #define raw_irqs_disabled()             (local_get_flags() == 0)
 #define raw_irqs_disabled_flags(flags)  ((flags) == 0)
 
+#ifdef CONFIG_PPC_BOOK3E
+#define __hard_irq_enable()     __asm__ __volatile__("wrteei 1": : :"memory");
+#define __hard_irq_disable()    __asm__ __volatile__("wrteei 0": : :"memory");
+#else
 #define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
 #define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
+#endif
 
 #define  hard_irq_disable()                     \
         do {                                    \
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 7ead7c16fb7c..7464c0daddd1 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -35,16 +35,6 @@
 #define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
 #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
 
-/* Cell page table entries */
-#define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
-#define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
-#define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
-#define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
-#define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
-#define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
-#define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
-#define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
-
 /* Boot time flags */
 extern int iommu_is_off;
 extern int iommu_force_on;
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index 0a5137676e1b..bbcd1aaf3dfd 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -302,7 +302,8 @@ extern void irq_free_virt(unsigned int virq, unsigned int count);
 
 /* -- OF helpers -- */
 
-/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
+/**
+ * irq_create_of_mapping - Map a hardware interrupt into linux virq space
  * @controller: Device node of the interrupt controller
  * @inspec: Interrupt specifier from the device-tree
  * @intsize: Size of the interrupt specifier from the device-tree
@@ -314,8 +315,8 @@ extern void irq_free_virt(unsigned int virq, unsigned int count);
 extern unsigned int irq_create_of_mapping(struct device_node *controller,
                                           u32 *intspec, unsigned int intsize);
 
-
-/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
+/**
+ * irq_of_parse_and_map - Parse and Map an interrupt into linux virq space
  * @device: Device node of the device whose interrupt is to be mapped
  * @index: Index of the interrupt to map
  *
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 11d1fc3a8962..9efa2be78331 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -209,14 +209,14 @@ struct machdep_calls {
         /*
          * optional PCI "hooks"
          */
-        /* Called in indirect_* to avoid touching devices */
-        int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
-
         /* Called at then very end of pcibios_init() */
         void (*pcibios_after_init)(void);
 
 #endif /* CONFIG_PPC32 */
 
+        /* Called in indirect_* to avoid touching devices */
+        int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
+
         /* Called after PPC generic resource fixup to perform
            machine specific fixups */
         void (*pcibios_fixup_resources)(struct pci_dev *);
diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/mmu-40x.h
index 776f415a36aa..34916865eaef 100644
--- a/arch/powerpc/include/asm/mmu-40x.h
+++ b/arch/powerpc/include/asm/mmu-40x.h
@@ -61,4 +61,7 @@ typedef struct {
 
 #endif /* !__ASSEMBLY__ */
 
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
index 3c86576bfefa..0372669383a8 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -79,16 +79,22 @@ typedef struct {
 
 #if (PAGE_SHIFT == 12)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_4K
+#define mmu_virtual_psize       MMU_PAGE_4K
 #elif (PAGE_SHIFT == 14)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_16K
+#define mmu_virtual_psize       MMU_PAGE_16K
 #elif (PAGE_SHIFT == 16)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_64K
+#define mmu_virtual_psize       MMU_PAGE_64K
 #elif (PAGE_SHIFT == 18)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_256K
+#define mmu_virtual_psize       MMU_PAGE_256K
 #else
 #error "Unsupported PAGE_SIZE"
 #endif
 
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #define PPC44x_PGD_OFF_SHIFT    (32 - PGDIR_SHIFT + PGD_T_LOG2)
 #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
 #define PPC44x_PTE_ADD_SHIFT    (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index 07865a357848..3d11d3ce79ec 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -143,4 +143,7 @@ typedef struct {
 } mm_context_t;
 #endif /* !__ASSEMBLY__ */
 
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_8M
+
 #endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 7e74cff81d86..74695816205c 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -38,58 +38,140 @@
 #define BOOK3E_PAGESZ_1TB       30
 #define BOOK3E_PAGESZ_2TB       31
 
-#define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
-#define MAS0_NV(x)      ((x) & 0x00000FFF)
-
-#define MAS1_VALID      0x80000000
-#define MAS1_IPROT      0x40000000
-#define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
-#define MAS1_IND        0x00002000
-#define MAS1_TS         0x00001000
-#define MAS1_TSIZE(x)   ((x << 7) & 0x00000F80)
-
-#define MAS2_EPN        0xFFFFF000
-#define MAS2_X0         0x00000040
-#define MAS2_X1         0x00000020
-#define MAS2_W          0x00000010
-#define MAS2_I          0x00000008
-#define MAS2_M          0x00000004
-#define MAS2_G          0x00000002
-#define MAS2_E          0x00000001
+/* MAS registers bit definitions */
+
+#define MAS0_TLBSEL(x)          ((x << 28) & 0x30000000)
+#define MAS0_ESEL(x)            ((x << 16) & 0x0FFF0000)
+#define MAS0_NV(x)              ((x) & 0x00000FFF)
+#define MAS0_HES                0x00004000
+#define MAS0_WQ_ALLWAYS         0x00000000
+#define MAS0_WQ_COND            0x00001000
+#define MAS0_WQ_CLR_RSRV        0x00002000
+
+#define MAS1_VALID              0x80000000
+#define MAS1_IPROT              0x40000000
+#define MAS1_TID(x)             ((x << 16) & 0x3FFF0000)
+#define MAS1_IND                0x00002000
+#define MAS1_TS                 0x00001000
+#define MAS1_TSIZE_MASK         0x00000f80
+#define MAS1_TSIZE_SHIFT        7
+#define MAS1_TSIZE(x)           ((x << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
+
+#define MAS2_EPN                0xFFFFF000
+#define MAS2_X0                 0x00000040
+#define MAS2_X1                 0x00000020
+#define MAS2_W                  0x00000010
+#define MAS2_I                  0x00000008
+#define MAS2_M                  0x00000004
+#define MAS2_G                  0x00000002
+#define MAS2_E                  0x00000001
 #define MAS2_EPN_MASK(size)             (~0 << (size + 10))
 #define MAS2_VAL(addr, size, flags)     ((addr) & MAS2_EPN_MASK(size) | (flags))
 
-#define MAS3_RPN        0xFFFFF000
-#define MAS3_U0         0x00000200
-#define MAS3_U1         0x00000100
-#define MAS3_U2         0x00000080
-#define MAS3_U3         0x00000040
-#define MAS3_UX         0x00000020
-#define MAS3_SX         0x00000010
-#define MAS3_UW         0x00000008
-#define MAS3_SW         0x00000004
-#define MAS3_UR         0x00000002
-#define MAS3_SR         0x00000001
-
-#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
-#define MAS4_INDD       0x00008000
-#define MAS4_TSIZED(x)  MAS1_TSIZE(x)
-#define MAS4_X0D        0x00000040
-#define MAS4_X1D        0x00000020
-#define MAS4_WD         0x00000010
-#define MAS4_ID         0x00000008
-#define MAS4_MD         0x00000004
-#define MAS4_GD         0x00000002
-#define MAS4_ED         0x00000001
-
-#define MAS6_SPID0      0x3FFF0000
-#define MAS6_SPID1      0x00007FFE
-#define MAS6_ISIZE(x)   MAS1_TSIZE(x)
-#define MAS6_SAS        0x00000001
-#define MAS6_SPID       MAS6_SPID0
-
-#define MAS7_RPN        0xFFFFFFFF
+#define MAS3_RPN                0xFFFFF000
+#define MAS3_U0                 0x00000200
+#define MAS3_U1                 0x00000100
+#define MAS3_U2                 0x00000080
+#define MAS3_U3                 0x00000040
+#define MAS3_UX                 0x00000020
+#define MAS3_SX                 0x00000010
+#define MAS3_UW                 0x00000008
+#define MAS3_SW                 0x00000004
+#define MAS3_UR                 0x00000002
+#define MAS3_SR                 0x00000001
+#define MAS3_SPSIZE             0x0000003e
+#define MAS3_SPSIZE_SHIFT       1
+
+#define MAS4_TLBSELD(x)         MAS0_TLBSEL(x)
+#define MAS4_INDD               0x00008000      /* Default IND */
+#define MAS4_TSIZED(x)          MAS1_TSIZE(x)
+#define MAS4_X0D                0x00000040
+#define MAS4_X1D                0x00000020
+#define MAS4_WD                 0x00000010
+#define MAS4_ID                 0x00000008
+#define MAS4_MD                 0x00000004
+#define MAS4_GD                 0x00000002
+#define MAS4_ED                 0x00000001
+#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
+#define MAS4_WIMGED_SHIFT       0
+#define MAS4_VLED               MAS4_X1D        /* Default VLE */
+#define MAS4_ACMD               0x000000c0      /* Default ACM */
+#define MAS4_ACMD_SHIFT         6
+#define MAS4_TSIZED_MASK        0x00000f80      /* Default TSIZE */
+#define MAS4_TSIZED_SHIFT       7
+
+#define MAS6_SPID0              0x3FFF0000
+#define MAS6_SPID1              0x00007FFE
+#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
+#define MAS6_SAS                0x00000001
+#define MAS6_SPID               MAS6_SPID0
+#define MAS6_SIND               0x00000002      /* Indirect page */
+#define MAS6_SIND_SHIFT         1
+#define MAS6_SPID_MASK          0x3fff0000
+#define MAS6_SPID_SHIFT         16
+#define MAS6_ISIZE_MASK         0x00000f80
+#define MAS6_ISIZE_SHIFT        7
+
+#define MAS7_RPN                0xFFFFFFFF
+
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
+#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
+                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
+#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
+#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
+#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
+#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
+
+/* TLBnCFG encoding */
+#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
+#define TLBnCFG_HES             0x00002000      /* HW select supported */
+#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
+#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
+#define TLBnCFG_IND             0x00020000      /* IND entries supported */
+#define TLBnCFG_PT              0x00040000      /* Can load from page table */
+#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
+
+/* TLBnPS encoding */
+#define TLBnPS_4K               0x00000004
+#define TLBnPS_8K               0x00000008
+#define TLBnPS_16K              0x00000010
+#define TLBnPS_32K              0x00000020
+#define TLBnPS_64K              0x00000040
+#define TLBnPS_128K             0x00000080
+#define TLBnPS_256K             0x00000100
+#define TLBnPS_512K             0x00000200
+#define TLBnPS_1M               0x00000400
+#define TLBnPS_2M               0x00000800
+#define TLBnPS_4M               0x00001000
+#define TLBnPS_8M               0x00002000
+#define TLBnPS_16M              0x00004000
+#define TLBnPS_32M              0x00008000
+#define TLBnPS_64M              0x00010000
+#define TLBnPS_128M             0x00020000
+#define TLBnPS_256M             0x00040000
+#define TLBnPS_512M             0x00080000
+#define TLBnPS_1G               0x00100000
+#define TLBnPS_2G               0x00200000
+#define TLBnPS_4G               0x00400000
+#define TLBnPS_8G               0x00800000
+#define TLBnPS_16G              0x01000000
+#define TLBnPS_32G              0x02000000
+#define TLBnPS_64G              0x04000000
+#define TLBnPS_128G             0x08000000
+#define TLBnPS_256G             0x10000000
+
+/* tlbilx action encoding */
+#define TLBILX_T_ALL                    0
+#define TLBILX_T_TID                    1
+#define TLBILX_T_FULLMATCH              3
+#define TLBILX_T_CLASS0                 4
+#define TLBILX_T_CLASS1                 5
+#define TLBILX_T_CLASS2                 6
+#define TLBILX_T_CLASS3                 7
 
 #ifndef __ASSEMBLY__
 
@@ -100,6 +182,34 @@ typedef struct {
         unsigned int    active;
         unsigned long   vdso_base;
 } mm_context_t;
+
+/* Page size definitions, common between 32 and 64-bit
+ *
+ *    shift : is the "PAGE_SHIFT" value for that page size
+ *    penc  : is the pte encoding mask
+ *
+ */
+struct mmu_psize_def
+{
+        unsigned int    shift;  /* number of bits */
+        unsigned int    enc;    /* PTE encoding */
+};
+extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+
+/* The page sizes use the same names as 64-bit hash but are
+ * constants
+ */
+#if defined(CONFIG_PPC_4K_PAGES)
+#define mmu_virtual_psize       MMU_PAGE_4K
+#elif defined(CONFIG_PPC_64K_PAGES)
+#define mmu_virtual_psize       MMU_PAGE_64K
+#else
+#error Unsupported page size
+#endif
+
+extern int mmu_linear_psize;
+extern int mmu_vmemmap_psize;
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
index 16b1a1e77e64..16f513e5cbd7 100644
--- a/arch/powerpc/include/asm/mmu-hash32.h
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -55,21 +55,25 @@ struct ppc_bat {
 
 #ifndef __ASSEMBLY__
 
-/* Hardware Page Table Entry */
+/*
+ * Hardware Page Table Entry
+ * Note that the xpn and x bitfields are used only by processors that
+ * support extended addressing; otherwise, those bits are reserved.
+ */
 struct hash_pte {
         unsigned long v:1;      /* Entry is valid */
         unsigned long vsid:24;  /* Virtual segment identifier */
         unsigned long h:1;      /* Hash algorithm indicator */
         unsigned long api:6;    /* Abbreviated page index */
         unsigned long rpn:20;   /* Real (physical) page number */
-        unsigned long    :3;    /* Unused */
+        unsigned long xpn:3;    /* Real page number bits 0-2, optional */
         unsigned long r:1;      /* Referenced */
         unsigned long c:1;      /* Changed */
         unsigned long w:1;      /* Write-thru cache mode */
         unsigned long i:1;      /* Cache inhibited */
         unsigned long m:1;      /* Memory coherence */
         unsigned long g:1;      /* Guarded */
-        unsigned long  :1;      /* Unused */
+        unsigned long x:1;      /* Real page number bit 3, optional */
         unsigned long pp:2;     /* Page protection */
 };
 
@@ -80,4 +84,10 @@ typedef struct {
 
 #endif /* !__ASSEMBLY__ */
 
+/* We happily ignore the smaller BATs on 601, we don't actually use
+ * those definitions on hash32 at the moment anyway
+ */
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 98c104a09961..bebe31c2e907 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -41,6 +41,7 @@ extern char initial_stab[];
 
 #define SLB_NUM_BOLTED          3
 #define SLB_CACHE_ENTRIES       8
+#define SLB_MIN_SIZE            32
 
 /* Bits in the SLB ESID word */
 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
@@ -139,26 +140,6 @@ struct mmu_psize_def
 #endif /* __ASSEMBLY__ */
 
 /*
- * The kernel use the constants below to index in the page sizes array.
- * The use of fixed constants for this purpose is better for performances
- * of the low level hash refill handlers.
- *
- * A non supported page size has a "shift" field set to 0
- *
- * Any new page size being implemented can get a new entry in here. Whether
- * the kernel will use it or not is a different matter though. The actual page
- * size used by hugetlbfs is not defined here and may be made variable
- */
-
-#define MMU_PAGE_4K             0       /* 4K */
-#define MMU_PAGE_64K            1       /* 64K */
-#define MMU_PAGE_64K_AP         2       /* 64K Admixed (in a 4K segment) */
-#define MMU_PAGE_1M             3       /* 1M */
-#define MMU_PAGE_16M            4       /* 16M */
-#define MMU_PAGE_16G            5       /* 16G */
-#define MMU_PAGE_COUNT          6
-
-/*
  * Segment sizes.
  * These are the values used by hardware in the B field of
  * SLB entries and the first dword of MMU hashtable entries.
@@ -296,6 +277,7 @@ extern void slb_flush_and_rebolt(void);
 extern void stab_initialize(unsigned long stab);
 
 extern void slb_vmalloc_update(void);
+extern void slb_set_size(u16 size);
 #endif /* __ASSEMBLY__ */
 
 /*
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index fb57ded592f9..7ffbb65ff7a9 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -17,6 +17,7 @@
 #define MMU_FTR_TYPE_40x                ASM_CONST(0x00000004)
 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
+#define MMU_FTR_TYPE_3E                 ASM_CONST(0x00000020)
 
 /*
  * This is individual features
@@ -57,6 +58,15 @@
  */
 #define MMU_FTR_TLBIE_206               ASM_CONST(0x00400000)
 
+/* Enable use of TLB reservation.  Processor should support tlbsrx.
+ * instruction and MAS0[WQ].
+ */
+#define MMU_FTR_USE_TLBRSRV             ASM_CONST(0x00800000)
+
+/* Use paired MAS registers (MAS7||MAS3, etc.)
+ */
+#define MMU_FTR_USE_PAIRED_MAS          ASM_CONST(0x01000000)
+
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
 
@@ -73,6 +83,41 @@ extern void early_init_mmu_secondary(void);
 
 #endif /* !__ASSEMBLY__ */
 
+/* The kernel use the constants below to index in the page sizes array.
+ * The use of fixed constants for this purpose is better for performances
+ * of the low level hash refill handlers.
+ *
+ * A non supported page size has a "shift" field set to 0
+ *
+ * Any new page size being implemented can get a new entry in here. Whether
+ * the kernel will use it or not is a different matter though. The actual page
+ * size used by hugetlbfs is not defined here and may be made variable
+ *
+ * Note: This array ended up being a false good idea as it's growing to the
+ * point where I wonder if we should replace it with something different,
+ * to think about, feedback welcome. --BenH.
+ */
+
+/* There are #define as they have to be used in assembly
+ *
+ * WARNING: If you change this list, make sure to update the array of
+ * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
+ * happen
+ */
+#define MMU_PAGE_4K     0
+#define MMU_PAGE_16K    1
+#define MMU_PAGE_64K    2
+#define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
+#define MMU_PAGE_256K   4
+#define MMU_PAGE_1M     5
+#define MMU_PAGE_8M     6
+#define MMU_PAGE_16M    7
+#define MMU_PAGE_256M   8
+#define MMU_PAGE_1G     9
+#define MMU_PAGE_16G    10
+#define MMU_PAGE_64G    11
+#define MMU_PAGE_COUNT  12
+
 
 #if defined(CONFIG_PPC_STD_MMU_64)
 /* 64-bit classic hash table MMU */
@@ -94,5 +139,6 @@ extern void early_init_mmu_secondary(void);
 #  include <asm/mmu-8xx.h>
 #endif
 
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index b7063669f972..b34e94d94435 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -14,7 +14,6 @@
 /*
  * Most if the context management is out of line
  */
-extern void mmu_context_init(void);
 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 extern void destroy_context(struct mm_struct *mm);
 
@@ -23,6 +22,12 @@ extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
 extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
 extern void set_context(unsigned long id, pgd_t *pgd);
 
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void mmu_context_init(void) { }
+#else
+extern void mmu_context_init(void);
+#endif
+
 /*
  * switch_mm is the entry point called from the architecture independent
  * code in kernel/sched.c
@@ -38,6 +43,10 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         tsk->thread.pgdir = next->pgd;
 #endif /* CONFIG_PPC32 */
 
+        /* 64-bit Book3E keeps track of current PGD in the PACA */
+#ifdef CONFIG_PPC_BOOK3E_64
+        get_paca()->pgd = next->pgd;
+#endif
         /* Nothing else to do if we aren't actually switching */
         if (prev == next)
                 return;
@@ -84,6 +93,10 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
 static inline void enter_lazy_tlb(struct mm_struct *mm,
                                   struct task_struct *tsk)
 {
+        /* 64-bit Book3E keeps track of current PGD in the PACA */
+#ifdef CONFIG_PPC_BOOK3E_64
+        get_paca()->pgd = NULL;
+#endif
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index efde5ac82f7b..6c587eddee59 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -107,6 +107,9 @@ extern void	pmac_xpram_write(int xpaddr, u8 data);
 /* Synchronize NVRAM */
 extern void     nvram_sync(void);
 
+/* Determine NVRAM size */
+extern ssize_t nvram_get_size(void);
+
 /* Normal access to NVRAM */
 extern unsigned char nvram_read_byte(int i);
 extern void nvram_write_byte(unsigned char c, int i);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index c8a3cbfe02ff..b634456ea893 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -14,9 +14,11 @@
 #define _ASM_POWERPC_PACA_H
 #ifdef __KERNEL__
 
-#include        <asm/types.h>
-#include        <asm/lppaca.h>
-#include        <asm/mmu.h>
+#include <asm/types.h>
+#include <asm/lppaca.h>
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/exception-64e.h>
 
 register struct paca_struct *local_paca asm("r13");
 
@@ -91,6 +93,21 @@ struct paca_struct {
         u16 slb_cache[SLB_CACHE_ENTRIES];
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
+#ifdef CONFIG_PPC_BOOK3E
+        pgd_t *pgd;                     /* Current PGD */
+        pgd_t *kernel_pgd;              /* Kernel PGD */
+        u64 exgen[8] __attribute__((aligned(0x80)));
+        u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
+        u64 exmc[8];            /* used for machine checks */
+        u64 excrit[8];          /* used for crit interrupts */
+        u64 exdbg[8];           /* used for debug interrupts */
+
+        /* Kernel stack pointers for use by special exceptions */
+        void *mc_kstack;
+        void *crit_kstack;
+        void *dbg_kstack;
+#endif /* CONFIG_PPC_BOOK3E */
+
         mm_context_t context;
 
         /*
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 4940662ee87e..ff24254990e1 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -139,7 +139,11 @@ extern phys_addr_t kernstart_addr;
  * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
  * "kernelness", use is_kernel_addr() - it should do what you want.
  */
+#ifdef CONFIG_PPC_BOOK3E_64
+#define is_kernel_addr(x)       ((x) >= 0x8000000000000000ul)
+#else
 #define is_kernel_addr(x)       ((x) >= PAGE_OFFSET)
+#endif
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 5817a3b747e5..3f17b83f55a1 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -135,12 +135,22 @@ extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
 #endif /* __ASSEMBLY__ */
 #else
 #define slice_init()
+#ifdef CONFIG_PPC_STD_MMU_64
 #define get_slice_psize(mm, addr)       ((mm)->context.user_psize)
 #define slice_set_user_psize(mm, psize)         \
 do {                                            \
         (mm)->context.user_psize = (psize);     \
         (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
 } while (0)
+#else /* CONFIG_PPC_STD_MMU_64 */
+#ifdef CONFIG_PPC_64K_PAGES
+#define get_slice_psize(mm, addr)       MMU_PAGE_64K
+#else /* CONFIG_PPC_64K_PAGES */
+#define get_slice_psize(mm, addr)       MMU_PAGE_4K
+#endif /* !CONFIG_PPC_64K_PAGES */
+#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
+#endif /* !CONFIG_PPC_STD_MMU_64 */
+
 #define slice_set_range_psize(mm, start, len, psize)    \
         slice_set_user_psize((mm), (psize))
 #define slice_mm_new_context(mm)        1
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 4c61fa0b8d75..76e1f313a58e 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -77,9 +77,7 @@ struct pci_controller {
 
         int first_busno;
         int last_busno;
-#ifndef CONFIG_PPC64
         int self_busno;
-#endif
 
         void __iomem *io_base_virt;
 #ifdef CONFIG_PPC64
@@ -104,7 +102,6 @@ struct pci_controller {
         unsigned int __iomem *cfg_addr;
         void __iomem *cfg_data;
 
-#ifndef CONFIG_PPC64
         /*
          * Used for variants of PCI indirect handling and possible quirks:
          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
@@ -128,7 +125,6 @@ struct pci_controller {
 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
         u32 indirect_type;
-#endif  /* !CONFIG_PPC64 */
         /* Currently, we limit ourselves to 1 IO range and 3 mem
          * ranges since the common pci_bus structure can't handle more
          */
@@ -146,21 +142,6 @@ struct pci_controller {
 #endif  /* CONFIG_PPC64 */
 };
 
-#ifndef CONFIG_PPC64
-
-static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
-{
-        return bus->sysdata;
-}
-
-static inline int isa_vaddr_is_ioport(void __iomem *address)
-{
-        /* No specific ISA handling on ppc32 at this stage, it
-         * all goes through PCI
-         */
-        return 0;
-}
-
 /* These are used for config access before all the PCI probing
    has been done. */
 extern int early_read_config_byte(struct pci_controller *hose, int bus,
@@ -182,6 +163,22 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
 extern void setup_indirect_pci(struct pci_controller* hose,
                                resource_size_t cfg_addr,
                                resource_size_t cfg_data, u32 flags);
+
+#ifndef CONFIG_PPC64
+
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
+{
+        return bus->sysdata;
+}
+
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+        /* No specific ISA handling on ppc32 at this stage, it
+         * all goes through PCI
+         */
+        return 0;
+}
+
 #else   /* CONFIG_PPC64 */
 
 /*
@@ -284,11 +281,6 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 extern int pcibios_map_io_space(struct pci_bus *bus);
 
-/* Return values for ppc_md.pci_probe_mode function */
-#define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
-#define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
-#define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
-
 #ifdef CONFIG_NUMA
 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 #else
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index d9483c504d2d..7aca4839387b 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -22,6 +22,11 @@
 
 #include <asm-generic/pci-dma-compat.h>
 
+/* Return values for ppc_md.pci_probe_mode function */
+#define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
+#define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
+#define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
+
 #define PCIBIOS_MIN_IO          0x1000
 #define PCIBIOS_MIN_MEM         0x10000000
 
@@ -61,8 +66,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 }
 
 #ifdef CONFIG_PCI
-extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
-extern struct dma_mapping_ops *get_pci_dma_ops(void);
+extern void set_pci_dma_ops(struct dma_map_ops *dma_ops);
+extern struct dma_map_ops *get_pci_dma_ops(void);
 #else   /* CONFIG_PCI */
 #define set_pci_dma_ops(d)
 #define get_pci_dma_ops()       NULL
@@ -228,6 +233,8 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 
 extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
+extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
+extern void pcibios_scan_phb(struct pci_controller *hose, void *sysdata);
 
 #endif  /* __KERNEL__ */
 #endif /* __ASM_POWERPC_PCI_H */
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index 1730e5e298d6..f2e812de7c3c 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -4,6 +4,15 @@
 
 #include <linux/mm.h>
 
+#ifdef CONFIG_PPC_BOOK3E
+extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
+#else /* CONFIG_PPC_BOOK3E */
+static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
+                                     unsigned long address)
+{
+}
+#endif /* !CONFIG_PPC_BOOK3E */
+
 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
 {
         free_page((unsigned long)pte);
@@ -19,7 +28,12 @@ typedef struct pgtable_free {
         unsigned long val;
 } pgtable_free_t;
 
-#define PGF_CACHENUM_MASK       0x7
+/* This needs to be big enough to allow for MMU_PAGE_COUNT + 2 to be stored
+ * and small enough to fit in the low bits of any naturally aligned page
+ * table cache entry. Arbitrarily set to 0x1f, that should give us some
+ * room to grow
+ */
+#define PGF_CACHENUM_MASK       0x1f
 
 static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
                                                 unsigned long mask)
@@ -35,19 +49,27 @@ static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
 #include <asm/pgalloc-32.h>
 #endif
 
-extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
-
 #ifdef CONFIG_SMP
-#define __pte_free_tlb(tlb,ptepage,address)             \
-do { \
-        pgtable_page_dtor(ptepage); \
-        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
-                                        PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
-} while (0)
-#else
-#define __pte_free_tlb(tlb, pte, address)       pte_free((tlb)->mm, (pte))
-#endif
+extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+extern void pte_free_finish(void);
+#else /* CONFIG_SMP */
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
+{
+        pgtable_free(pgf);
+}
+static inline void pte_free_finish(void) { }
+#endif /* !CONFIG_SMP */
 
+static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
+                                  unsigned long address)
+{
+        pgtable_free_t pgf = pgtable_free_cache(page_address(ptepage),
+                                                PTE_NONCACHE_NUM,
+                                                PTE_TABLE_SIZE-1);
+        tlb_flush_pgtable(tlb, address);
+        pgtable_page_dtor(ptepage);
+        pgtable_free_tlb(tlb, pgf);
+}
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index c9ff9d75990e..55646adfa843 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -111,6 +111,8 @@ extern int icache_44x_need_flush;
 #include <asm/pte-40x.h>
 #elif defined(CONFIG_44x)
 #include <asm/pte-44x.h>
+#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
+#include <asm/pte-book3e.h>
 #elif defined(CONFIG_FSL_BOOKE)
 #include <asm/pte-fsl-booke.h>
 #elif defined(CONFIG_8xx)
@@ -186,7 +188,7 @@ static inline unsigned long pte_update(pte_t *p,
 #endif /* !PTE_ATOMIC_UPDATES */
 
 #ifdef CONFIG_44x
-        if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
+        if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
                 icache_44x_need_flush = 1;
 #endif
         return old;
@@ -217,7 +219,7 @@ static inline unsigned long long pte_update(pte_t *p,
 #endif /* !PTE_ATOMIC_UPDATES */
 
 #ifdef CONFIG_44x
-        if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
+        if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
                 icache_44x_need_flush = 1;
 #endif
         return old;
@@ -267,8 +269,7 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 {
         unsigned long bits = pte_val(entry) &
-                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
-                 _PAGE_HWEXEC | _PAGE_EXEC);
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
         pte_update(ptep, 0, bits);
 }
 
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 6cc085b945a5..90533ddcd703 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -10,10 +10,10 @@
 #define PGD_INDEX_SIZE  4
 
 #ifndef __ASSEMBLY__
-
 #define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
 #define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
+#endif  /* __ASSEMBLY__ */
 
 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
@@ -32,8 +32,6 @@
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
-#endif  /* __ASSEMBLY__ */
-
 /* Bits to mask out from a PMD to get to the PTE page */
 #define PMD_MASKED_BITS         0x1ff
 /* Bits to mask out from a PGD/PUD to get to the PMD page */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 8cd083c61503..806abe7a3fa5 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -5,11 +5,6 @@
  * the ppc64 hashed page table.
  */
 
-#ifndef __ASSEMBLY__
-#include <linux/stddef.h>
-#include <asm/tlbflush.h>
-#endif /* __ASSEMBLY__ */
-
 #ifdef CONFIG_PPC_64K_PAGES
 #include <asm/pgtable-ppc64-64k.h>
 #else
@@ -38,26 +33,47 @@
 #endif
 
 /*
- * Define the address range of the vmalloc VM area.
+ * Define the address range of the kernel non-linear virtual area
+ */
+
+#ifdef CONFIG_PPC_BOOK3E
+#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
+#else
+#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
+#endif
+#define KERN_VIRT_SIZE  PGTABLE_RANGE
+
+/*
+ * The vmalloc space starts at the beginning of that region, and
+ * occupies half of it on hash CPUs and a quarter of it on Book3E
+ * (we keep a quarter for the virtual memmap)
  */
-#define VMALLOC_START ASM_CONST(0xD000000000000000)
-#define VMALLOC_SIZE  (PGTABLE_RANGE >> 1)
-#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
+#define VMALLOC_START   KERN_VIRT_START
+#ifdef CONFIG_PPC_BOOK3E
+#define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 2)
+#else
+#define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 1)
+#endif
+#define VMALLOC_END     (VMALLOC_START + VMALLOC_SIZE)
 
 /*
- * Define the address ranges for MMIO and IO space :
+ * The second half of the kernel virtual space is used for IO mappings,
+ * it's itself carved into the PIO region (ISA and PHB IO space) and
+ * the ioremap space
  *
- *  ISA_IO_BASE = VMALLOC_END, 64K reserved area
+ *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
  *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
  * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
  */
+#define KERN_IO_START   (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
 #define FULL_IO_SIZE    0x80000000ul
-#define  ISA_IO_BASE    (VMALLOC_END)
-#define  ISA_IO_END     (VMALLOC_END + 0x10000ul)
+#define  ISA_IO_BASE    (KERN_IO_START)
+#define  ISA_IO_END     (KERN_IO_START + 0x10000ul)
 #define  PHB_IO_BASE    (ISA_IO_END)
-#define  PHB_IO_END     (VMALLOC_END + FULL_IO_SIZE)
+#define  PHB_IO_END     (KERN_IO_START + FULL_IO_SIZE)
 #define IOREMAP_BASE    (PHB_IO_END)
-#define IOREMAP_END     (VMALLOC_START + PGTABLE_RANGE)
+#define IOREMAP_END     (KERN_VIRT_START + KERN_VIRT_SIZE)
+
 
 /*
  * Region IDs
@@ -68,23 +84,32 @@
 
 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
-#define VMEMMAP_REGION_ID       (0xfUL)
+#define VMEMMAP_REGION_ID       (0xfUL) /* Server only */
 #define USER_REGION_ID          (0UL)
 
 /*
- * Defines the address of the vmemap area, in its own region
+ * Defines the address of the vmemap area, in its own region on
+ * hash table CPUs and after the vmalloc space on Book3E
  */
+#ifdef CONFIG_PPC_BOOK3E
+#define VMEMMAP_BASE            VMALLOC_END
+#define VMEMMAP_END             KERN_IO_START
+#else
 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
+#endif
 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
 
 
 /*
  * Include the PTE bits definitions
  */
+#ifdef CONFIG_PPC_BOOK3S
 #include <asm/pte-hash64.h>
+#else
+#include <asm/pte-book3e.h>
+#endif
 #include <asm/pte-common.h>
 
-
 #ifdef CONFIG_PPC_MM_SLICES
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
@@ -92,6 +117,9 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/stddef.h>
+#include <asm/tlbflush.h>
+
 /*
  * This is the default implementation of various PTE accessors, it's
  * used in all cases except Book3S with 64K pages where we have a
@@ -285,8 +313,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 {
         unsigned long bits = pte_val(entry) &
-                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
-                 _PAGE_EXEC | _PAGE_HWEXEC);
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
 
 #ifdef PTE_ATOMIC_UPDATES
         unsigned long old, tmp;
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
index d6a616a1b3ea..ccc68b50d05d 100644
--- a/arch/powerpc/include/asm/pmc.h
+++ b/arch/powerpc/include/asm/pmc.h
@@ -27,10 +27,22 @@ extern perf_irq_t perf_irq;
 
 int reserve_pmc_hardware(perf_irq_t new_perf_irq);
 void release_pmc_hardware(void);
+void ppc_enable_pmcs(void);
 
 #ifdef CONFIG_PPC64
-void power4_enable_pmcs(void);
-void pasemi_enable_pmcs(void);
+#include <asm/lppaca.h>
+
+static inline void ppc_set_pmu_inuse(int inuse)
+{
+        get_lppaca()->pmcregs_in_use = inuse;
+}
+
+extern void power4_enable_pmcs(void);
+
+#else /* CONFIG_PPC64 */
+
+static inline void ppc_set_pmu_inuse(int inuse) { }
+
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index b74f16d45cb4..ef9aa84cac5a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -48,6 +48,8 @@
 #define PPC_INST_TLBIE                  0x7c000264
 #define PPC_INST_TLBILX                 0x7c000024
 #define PPC_INST_WAIT                   0x7c00007c
+#define PPC_INST_TLBIVAX                0x7c000624
+#define PPC_INST_TLBSRX_DOT             0x7c0006a5
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
@@ -76,6 +78,10 @@
                                         __PPC_WC(w))
 #define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
                                                __PPC_RB(a) | __PPC_RS(lp))
+#define PPC_TLBSRX_DOT(a,b)     stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
+                                        __PPC_RA(a) | __PPC_RB(b))
+#define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
+                                        __PPC_RA(a) | __PPC_RB(b))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 854ab713f56c..2828f9d0f66d 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -39,7 +39,6 @@ void *traverse_pci_devices(struct device_node *start, traverse_func pre,
 
 extern void pci_devs_phb_init(void);
 extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
-extern void scan_phb(struct pci_controller *hose);
 
 /* From rtas_pci.h */
 extern void init_pci_config_tokens (void);
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index f9729529c20d..498fe09263d3 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -98,13 +98,13 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 
-#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
+#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,base,b
 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
+#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,base,b
 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
@@ -112,26 +112,26 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
 /* Save the lower 32 VSRs in the thread VSR region */
-#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,b,base)
+#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,base,b)
 #define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 #define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 #define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 #define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 #define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
-#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
+#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
 #define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 #define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 #define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 #define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 #define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,b,base)
+#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,base,b)
 #define SAVE_2VSRSU(n,b,base)   SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
 #define SAVE_4VSRSU(n,b,base)   SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
 #define SAVE_8VSRSU(n,b,base)   SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
 #define SAVE_16VSRSU(n,b,base)  SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
 #define SAVE_32VSRSU(n,b,base)  SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
+#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
 #define REST_2VSRSU(n,b,base)   REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
 #define REST_4VSRSU(n,b,base)   REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
 #define REST_8VSRSU(n,b,base)   REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
@@ -375,8 +375,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define PPC440EP_ERR42
 #endif
 
-
-#if defined(CONFIG_BOOKE)
+/*
+ * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
+ * keep the address intact to be compatible with code shared with
+ * 32-bit classic.
+ *
+ * On the other hand, I find it useful to have them behave as expected
+ * by their name (ie always do the addition) on 64-bit BookE
+ */
+#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 #define toreal(rd)
 #define fromreal(rd)
 
@@ -426,10 +433,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
         .previous
 #endif
 
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #define RFI             rfid
 #define MTMSRD(r)       mtmsrd  r
-
 #else
 #define FIX_SRR1(ra, rb)
 #ifndef CONFIG_40x
diff --git a/arch/powerpc/include/asm/pte-40x.h b/arch/powerpc/include/asm/pte-40x.h
index 07630faae029..6c3e1f4378d4 100644
--- a/arch/powerpc/include/asm/pte-40x.h
+++ b/arch/powerpc/include/asm/pte-40x.h
@@ -46,7 +46,7 @@
 #define _PAGE_RW        0x040   /* software: Writes permitted */
 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
-#define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
+#define _PAGE_EXEC      0x200   /* hardware: EX permission */
 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 
 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
diff --git a/arch/powerpc/include/asm/pte-44x.h b/arch/powerpc/include/asm/pte-44x.h
index 37e98bcf83e0..4192b9bad901 100644
--- a/arch/powerpc/include/asm/pte-44x.h
+++ b/arch/powerpc/include/asm/pte-44x.h
@@ -78,7 +78,7 @@
 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 #define _PAGE_RW        0x00000002              /* S: Write permission */
 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
-#define _PAGE_HWEXEC    0x00000004              /* H: Execute permission */
+#define _PAGE_EXEC      0x00000004              /* H: Execute permission */
 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 #define _PAGE_DIRTY     0x00000010              /* S: Page dirty */
 #define _PAGE_SPECIAL   0x00000020              /* S: Special page */
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index 8c6e31251034..94e979718dcf 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -36,7 +36,6 @@
 /* These five software bits must be masked out when the entry is loaded
  * into the TLB.
  */
-#define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 #define _PAGE_RW        0x0040  /* software: user write access allowed */
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
new file mode 100644
index 000000000000..082d515930a2
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -0,0 +1,84 @@
+#ifndef _ASM_POWERPC_PTE_BOOK3E_H
+#define _ASM_POWERPC_PTE_BOOK3E_H
+#ifdef __KERNEL__
+
+/* PTE bit definitions for processors compliant to the Book3E
+ * architecture 2.06 or later. The position of the PTE bits
+ * matches the HW definition of the optional Embedded Page Table
+ * category.
+ */
+
+/* Architected bits */
+#define _PAGE_PRESENT   0x000001 /* software: pte contains a translation */
+#define _PAGE_FILE      0x000002 /* (!present only) software: pte holds file offset */
+#define _PAGE_SW1       0x000002
+#define _PAGE_BAP_SR    0x000004
+#define _PAGE_BAP_UR    0x000008
+#define _PAGE_BAP_SW    0x000010
+#define _PAGE_BAP_UW    0x000020
+#define _PAGE_BAP_SX    0x000040
+#define _PAGE_BAP_UX    0x000080
+#define _PAGE_PSIZE_MSK 0x000f00
+#define _PAGE_PSIZE_4K  0x000200
+#define _PAGE_PSIZE_8K  0x000300
+#define _PAGE_PSIZE_16K 0x000400
+#define _PAGE_PSIZE_32K 0x000500
+#define _PAGE_PSIZE_64K 0x000600
+#define _PAGE_PSIZE_128K        0x000700
+#define _PAGE_PSIZE_256K        0x000800
+#define _PAGE_PSIZE_512K        0x000900
+#define _PAGE_PSIZE_1M  0x000a00
+#define _PAGE_PSIZE_2M  0x000b00
+#define _PAGE_PSIZE_4M  0x000c00
+#define _PAGE_PSIZE_8M  0x000d00
+#define _PAGE_PSIZE_16M 0x000e00
+#define _PAGE_PSIZE_32M 0x000f00
+#define _PAGE_DIRTY     0x001000 /* C: page changed */
+#define _PAGE_SW0       0x002000
+#define _PAGE_U3        0x004000
+#define _PAGE_U2        0x008000
+#define _PAGE_U1        0x010000
+#define _PAGE_U0        0x020000
+#define _PAGE_ACCESSED  0x040000
+#define _PAGE_LENDIAN   0x080000
+#define _PAGE_GUARDED   0x100000
+#define _PAGE_COHERENT  0x200000 /* M: enforce memory coherence */
+#define _PAGE_NO_CACHE  0x400000 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
+
+/* "Higher level" linux bit combinations */
+#define _PAGE_EXEC              _PAGE_BAP_UX /* .. and was cache cleaned */
+#define _PAGE_RW                (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
+#define _PAGE_KERNEL_RW         (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
+#define _PAGE_KERNEL_RO         (_PAGE_BAP_SR)
+#define _PAGE_KERNEL_RWX        (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
+#define _PAGE_KERNEL_ROX        (_PAGE_BAP_SR | _PAGE_BAP_SX)
+#define _PAGE_USER              (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
+
+#define _PAGE_HASHPTE   0
+#define _PAGE_BUSY      0
+
+#define _PAGE_SPECIAL   _PAGE_SW0
+
+/* Flags to be preserved on PTE modifications */
+#define _PAGE_HPTEFLAGS _PAGE_BUSY
+
+/* Base page size */
+#ifdef CONFIG_PPC_64K_PAGES
+#define _PAGE_PSIZE     _PAGE_PSIZE_64K
+#define PTE_RPN_SHIFT   (28)
+#else
+#define _PAGE_PSIZE     _PAGE_PSIZE_4K
+#define PTE_RPN_SHIFT   (24)
+#endif
+
+/* On 32-bit, we never clear the top part of the PTE */
+#ifdef CONFIG_PPC32
+#define _PTE_NONE_MASK  0xffffffff00000000ULL
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index a7e210b6b48c..c3b65076a263 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -13,9 +13,6 @@
 #ifndef _PAGE_HWWRITE
 #define _PAGE_HWWRITE   0
 #endif
-#ifndef _PAGE_HWEXEC
-#define _PAGE_HWEXEC    0
-#endif
 #ifndef _PAGE_EXEC
 #define _PAGE_EXEC      0
 #endif
@@ -34,6 +31,9 @@
 #ifndef _PAGE_4K_PFN
 #define _PAGE_4K_PFN            0
 #endif
+#ifndef _PAGE_SAO
+#define _PAGE_SAO       0
+#endif
 #ifndef _PAGE_PSIZE
 #define _PAGE_PSIZE             0
 #endif
@@ -45,10 +45,16 @@
 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 #endif
 #ifndef _PAGE_KERNEL_RO
-#define _PAGE_KERNEL_RO 0
+#define _PAGE_KERNEL_RO         0
+#endif
+#ifndef _PAGE_KERNEL_ROX
+#define _PAGE_KERNEL_ROX        (_PAGE_EXEC)
 #endif
 #ifndef _PAGE_KERNEL_RW
-#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
+#define _PAGE_KERNEL_RW         (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
+#endif
+#ifndef _PAGE_KERNEL_RWX
+#define _PAGE_KERNEL_RWX        (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE | _PAGE_EXEC)
 #endif
 #ifndef _PAGE_HPTEFLAGS
 #define _PAGE_HPTEFLAGS _PAGE_HASHPTE
@@ -93,8 +99,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 #define PAGE_PROT_BITS  (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
                          _PAGE_WRITETHRU | _PAGE_ENDIAN | _PAGE_4K_PFN | \
                          _PAGE_USER | _PAGE_ACCESSED | \
-                         _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
-                         _PAGE_EXEC | _PAGE_HWEXEC)
+                         _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
 
 /*
  * We define 2 sets of base prot bits, one for basic pages (ie,
@@ -151,11 +156,9 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
                                  _PAGE_NO_CACHE)
 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
                                  _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define PAGE_KERNEL_X   __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW | _PAGE_EXEC | \
-                                 _PAGE_HWEXEC)
+#define PAGE_KERNEL_X   __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
 #define PAGE_KERNEL_RO  __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
-#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO | _PAGE_EXEC | \
-                                 _PAGE_HWEXEC)
+#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
 
 /* Protection used for kernel text. We want the debuggers to be able to
  * set breakpoints anywhere, so don't write protect the kernel text
diff --git a/arch/powerpc/include/asm/pte-fsl-booke.h b/arch/powerpc/include/asm/pte-fsl-booke.h
index 10820f58acf5..2c12be5f677a 100644
--- a/arch/powerpc/include/asm/pte-fsl-booke.h
+++ b/arch/powerpc/include/asm/pte-fsl-booke.h
@@ -23,7 +23,7 @@
 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
 #define _PAGE_RW        0x00004 /* S: Write permission (SW) */
 #define _PAGE_DIRTY     0x00008 /* S: Page dirty */
-#define _PAGE_HWEXEC    0x00010 /* H: SX permission */
+#define _PAGE_EXEC      0x00010 /* H: SX permission */
 #define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
 
 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
@@ -33,13 +33,6 @@
 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 #define _PAGE_SPECIAL   0x00800 /* S: Special page */
 
-#ifdef CONFIG_PTE_64BIT
-/* ERPN in a PTE never gets cleared, ignore it */
-#define _PTE_NONE_MASK  0xffffffffffff0000ULL
-/* We extend the size of the PTE flags area when using 64-bit PTEs */
-#define PTE_RPN_SHIFT   (PAGE_SHIFT + 8)
-#endif
-
 #define _PMD_PRESENT    0
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
diff --git a/arch/powerpc/include/asm/pte-hash32.h b/arch/powerpc/include/asm/pte-hash32.h
index 16e571c7f9ef..4aad4132d0a8 100644
--- a/arch/powerpc/include/asm/pte-hash32.h
+++ b/arch/powerpc/include/asm/pte-hash32.h
@@ -26,7 +26,6 @@
 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 #define _PAGE_DIRTY     0x080   /* C: page changed */
 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
-#define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 #define _PAGE_RW        0x400   /* software: user write access allowed */
 #define _PAGE_SPECIAL   0x800   /* software: Special page */
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1170267736d3..6315edc205d8 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -98,19 +98,15 @@
 #define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
 
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PPC_BOOK3S_64)
+/* Server variant */
 #define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
 #define MSR_KERNEL      MSR_ | MSR_SF
-
 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE
 #define MSR_USER64      MSR_USER32 | MSR_SF
-
-#else /* 32-bit */
+#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
 /* Default MSR for kernel mode. */
-#ifndef MSR_KERNEL      /* reg_booke.h also defines this */
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
-#endif
-
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 #endif
 
@@ -646,6 +642,137 @@
 #endif
 
 /*
+ * SPRG usage:
+ *
+ * All 64-bit:
+ *      - SPRG1 stores PACA pointer
+ *
+ * 64-bit server:
+ *      - SPRG0 unused (reserved for HV on Power4)
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG3 unused (user visible)
+ *
+ * 64-bit embedded
+ *      - SPRG0 generic exception scratch
+ *      - SPRG2 TLB exception stack
+ *      - SPRG3 unused (user visible)
+ *      - SPRG4 unused (user visible)
+ *      - SPRG6 TLB miss scratch (user visible, sorry !)
+ *      - SPRG7 critical exception scratch
+ *      - SPRG8 machine check exception scratch
+ *      - SPRG9 debug exception scratch
+ *
+ * All 32-bit:
+ *      - SPRG3 current thread_info pointer
+ *        (virtual on BookE, physical on others)
+ *
+ * 32-bit classic:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 indicator that we are in RTAS
+ *      - SPRG4 (603 only) pseudo TLB LRU data
+ *
+ * 32-bit 40x:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG4 scratch for exception vectors (not 403)
+ *      - SPRG5 scratch for exception vectors (not 403)
+ *      - SPRG6 scratch for exception vectors (not 403)
+ *      - SPRG7 scratch for exception vectors (not 403)
+ *
+ * 32-bit 440 and FSL BookE:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors (*)
+ *      - SPRG2 scratch for crit interrupts handler
+ *      - SPRG4 scratch for exception vectors
+ *      - SPRG5 scratch for exception vectors
+ *      - SPRG6 scratch for machine check handler
+ *      - SPRG7 scratch for exception vectors
+ *      - SPRG9 scratch for debug vectors (e500 only)
+ *
+ *      Additionally, BookE separates "read" and "write"
+ *      of those registers. That allows to use the userspace
+ *      readable variant for reads, which can avoid a fault
+ *      with KVM type virtualization.
+ *
+ *      (*) Under KVM, the host SPRG1 is used to point to
+ *      the current VCPU data structure
+ *
+ * 32-bit 8xx:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 apparently unused but initialized
+ *
+ */
+#ifdef CONFIG_PPC64
+#define SPRN_SPRG_PACA          SPRN_SPRG1
+#else
+#define SPRN_SPRG_THREAD        SPRN_SPRG3
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_64
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
+#endif
+
+#ifdef CONFIG_PPC_BOOK3E_64
+#define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
+#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG7
+#define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
+#define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
+#define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
+#define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_32
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_RTAS          SPRN_SPRG2
+#define SPRN_SPRG_603_LRU       SPRN_SPRG4
+#endif
+
+#ifdef CONFIG_40x
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
+#define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
+#define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
+#define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
+#define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
+#endif
+
+#ifdef CONFIG_BOOKE
+#define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
+#define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
+#define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
+#define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
+#define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG6W
+#define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
+#define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
+#ifdef CONFIG_E200
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
+#else
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
+#endif
+#define SPRN_SPRG_RVCPU         SPRN_SPRG1
+#define SPRN_SPRG_WVCPU         SPRN_SPRG1
+#endif
+
+#ifdef CONFIG_8xx
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#endif
+
+/*
  * An mtfsf instruction with the L bit set. On CPUs that support this a
  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
  *
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 6bcf364cbb2f..3bf783505528 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -18,18 +18,26 @@
 #define MSR_IS          MSR_IR  /* Instruction Space */
 #define MSR_DS          MSR_DR  /* Data Space */
 #define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
+#define MSR_CM          (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
 
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
+#if defined(CONFIG_PPC_BOOK3E_64)
+#define MSR_            MSR_ME | MSR_CE
+#define MSR_KERNEL      MSR_ | MSR_CM
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
+#define MSR_USER64      MSR_USER32 | MSR_CM
+#elif defined (CONFIG_40x)
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+#else
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 #endif
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
 #define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
 #define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
+#define SPRN_SPRG3R     0x103   /* Special Purpose Register General 3 Read */
 #define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
 #define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
 #define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
@@ -38,11 +46,18 @@
 #define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
 #define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
 #define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
+#define SPRN_EPCR       0x133   /* Embedded Processor Control Register */
 #define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
 #define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
 #define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
 #define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
 #define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
+#define SPRN_MAS8       0x155   /* MMU Assist Register 8 */
+#define SPRN_TLB0PS     0x158   /* TLB 0 Page Size Register */
+#define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
+#define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
+#define SPRN_MAS7_MAS3  0x174   /* MMU Assist Register 7 || 3 */
+#define SPRN_MAS0_MAS1  0x175   /* MMU Assist Register 0 || 1 */
 #define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
 #define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
 #define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
@@ -93,6 +108,8 @@
 #define SPRN_PID2       0x27A   /* Process ID Register 2 */
 #define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
 #define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
+#define SPRN_TLB2CFG    0x2B2   /* TLB 2 Config Register */
+#define SPRN_TLB3CFG    0x2B3   /* TLB 3 Config Register */
 #define SPRN_EPR        0x2BE   /* External Proxy Register */
 #define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
 #define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
@@ -415,16 +432,31 @@
 #define L2CSR0_L2LOA    0x00000080      /* L2 Cache Lock Overflow Allocate */
 #define L2CSR0_L2LO     0x00000020      /* L2 Cache Lock Overflow */
 
-/* Bit definitions for MMUCSR0 */
-#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
-#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
-#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
-#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
-
 /* Bit definitions for SGR. */
 #define SGR_NORMAL      0               /* Speculative fetching allowed. */
 #define SGR_GUARDED     1               /* Speculative fetching disallowed. */
 
+/* Bit definitions for EPCR */
+#define SPRN_EPCR_EXTGS         0x80000000      /* External Input interrupt
+                                                 * directed to Guest state */
+#define SPRN_EPCR_DTLBGS        0x40000000      /* Data TLB Error interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_ITLBGS        0x20000000      /* Instr. TLB error interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_DSIGS         0x10000000      /* Data Storage interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_ISIGS         0x08000000      /* Instr. Storage interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_DUVD          0x04000000      /* Disable Hypervisor Debug */
+#define SPRN_EPCR_ICM           0x02000000      /* Interrupt computation mode
+                                                 * (copied to MSR:CM on intr) */
+#define SPRN_EPCR_GICM          0x01000000      /* Guest Interrupt Comp. mode */
+#define SPRN_EPCR_DGTMI         0x00800000      /* Disable TLB Guest Management
+                                                 * instructions */
+#define SPRN_EPCR_DMIUH         0x00400000      /* Disable MAS Interrupt updates
+                                                 * for hypervisor */
+
+
 /*
  * The IBM-403 is an even more odd special case, as it is much
  * older than the IBM-405 series.  We put these down here incase someone
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 817fac0a0714..dae19342f0b9 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -1,6 +1,6 @@
 #ifndef _ASM_POWERPC_SETUP_H
 #define _ASM_POWERPC_SETUP_H
 
-#define COMMAND_LINE_SIZE       512
+#include <asm-generic/setup.h>
 
 #endif  /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index c25f73d1d842..c0d3b8af9319 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -148,6 +148,16 @@ extern struct smp_ops_t *smp_ops;
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi(cpumask_t mask);
 
+/* Definitions relative to the secondary CPU spin loop
+ * and entry point. Not all of them exist on both 32 and
+ * 64-bit but defining them all here doesn't harm
+ */
+extern void generic_secondary_smp_init(void);
+extern void generic_secondary_thread_init(void);
+extern unsigned long __secondary_hold_spinloop;
+extern unsigned long __secondary_hold_acknowledge;
+extern char __secondary_hold;
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/swiotlb.h b/arch/powerpc/include/asm/swiotlb.h
index 30891d6e2bc1..8979d4cd3d70 100644
--- a/arch/powerpc/include/asm/swiotlb.h
+++ b/arch/powerpc/include/asm/swiotlb.h
@@ -13,15 +13,13 @@
 
 #include <linux/swiotlb.h>
 
-extern struct dma_mapping_ops swiotlb_dma_ops;
-extern struct dma_mapping_ops swiotlb_pci_dma_ops;
-
-int swiotlb_arch_address_needs_mapping(struct device *, dma_addr_t,
-                                       size_t size);
+extern struct dma_map_ops swiotlb_dma_ops;
 
 static inline void dma_mark_clean(void *addr, size_t size) {}
 
 extern unsigned int ppc_swiotlb_enable;
 int __init swiotlb_setup_bus_notifier(void);
 
+extern void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev);
+
 #endif /* __ASM_SWIOTLB_H */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 370600ca2765..ed24bd92fe49 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -95,8 +95,8 @@ SYSCALL(reboot)
 SYSX(sys_ni_syscall,compat_sys_old_readdir,sys_old_readdir)
 SYSCALL_SPU(mmap)
 SYSCALL_SPU(munmap)
-SYSCALL_SPU(truncate)
-SYSCALL_SPU(ftruncate)
+COMPAT_SYS_SPU(truncate)
+COMPAT_SYS_SPU(ftruncate)
 SYSCALL_SPU(fchmod)
 SYSCALL_SPU(fchown)
 COMPAT_SYS_SPU(getpriority)
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
index e20ff7541f36..e2b428b0f7ba 100644
--- a/arch/powerpc/include/asm/tlb.h
+++ b/arch/powerpc/include/asm/tlb.h
@@ -25,57 +25,25 @@
 
 #include <linux/pagemap.h>
 
-struct mmu_gather;
-
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma)   do { } while (0)
 
-#if !defined(CONFIG_PPC_STD_MMU)
-
-#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
-
-#elif defined(__powerpc64__)
-
-extern void pte_free_finish(void);
-
-static inline void tlb_flush(struct mmu_gather *tlb)
-{
-        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
-
-        /* If there's a TLB batch pending, then we must flush it because the
-         * pages are going to be freed and we really don't want to have a CPU
-         * access a freed page because it has a stale TLB
-         */
-        if (tlbbatch->index)
-                __flush_tlb_pending(tlbbatch);
-
-        pte_free_finish();
-}
-
-#else
-
 extern void tlb_flush(struct mmu_gather *tlb);
 
-#endif
-
 /* Get the generic bits... */
 #include <asm-generic/tlb.h>
 
-#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
-
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-
-#else
 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
                              unsigned long address);
 
 static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
-                                        unsigned long address)
+                                          unsigned long address)
 {
+#ifdef CONFIG_PPC_STD_MMU_32
         if (pte_val(*ptep) & _PAGE_HASHPTE)
                 flush_hash_entry(tlb->mm, ptep, address);
+#endif
 }
 
-#endif
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_TLB_H */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index abbe3419d1dd..d50a380b2b6f 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -6,7 +6,7 @@
  *
  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
  *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - local_flush_tlb_mm(mm) flushes the specified mm context on
+ *  - local_flush_tlb_mm(mm, full) flushes the specified mm context on
  *                           the local processor
  *  - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
  *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
@@ -29,7 +29,8 @@
  * specific tlbie's
  */
 
-#include <linux/mm.h>
+struct vm_area_struct;
+struct mm_struct;
 
 #define MMU_NO_CONTEXT          ((unsigned int)-1)
 
@@ -40,12 +41,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 extern void local_flush_tlb_mm(struct mm_struct *mm);
 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 
+extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                                   int tsize, int ind);
+
 #ifdef CONFIG_SMP
 extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
+extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                             int tsize, int ind);
 #else
 #define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
 #define flush_tlb_page(vma,addr)        local_flush_tlb_page(vma,addr)
+#define __flush_tlb_page(mm,addr,p,i)   __local_flush_tlb_page(mm,addr,p,i)
 #endif
 #define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr)
 
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 26fc449bd989..dc0419b66f17 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -7,9 +7,8 @@
 #define VDSO32_LBASE    0x100000
 #define VDSO64_LBASE    0x100000
 
-/* Default map addresses */
+/* Default map addresses for 32bit vDSO */
 #define VDSO32_MBASE    VDSO32_LBASE
-#define VDSO64_MBASE    VDSO64_LBASE
 
 #define VDSO_VERSION_STRING     LINUX_2.6.15
 
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9619285f64e8..569f79ccd310 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -33,10 +33,10 @@ obj-y				:= cputable.o ptrace.o syscalls.o \
 obj-y                           += vdso32/
 obj-$(CONFIG_PPC64)             += setup_64.o sys_ppc32.o \
                                    signal_64.o ptrace32.o \
-                                   paca.o cpu_setup_ppc970.o \
-                                   cpu_setup_pa6t.o \
-                                   firmware.o nvram_64.o
+                                   paca.o nvram_64.o firmware.o
+obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o
 obj-$(CONFIG_PPC64)             += vdso64/
 obj-$(CONFIG_ALTIVEC)           += vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
@@ -63,8 +63,8 @@ obj-$(CONFIG_MODULES)		+= module.o module_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_44x)               += cpu_setup_44x.o
 obj-$(CONFIG_FSL_BOOKE)         += cpu_setup_fsl_booke.o dbell.o
 
-extra-$(CONFIG_PPC_STD_MMU)     := head_32.o
-extra-$(CONFIG_PPC64)           := head_64.o
+extra-y                         := head_$(CONFIG_WORD_SIZE).o
+extra-$(CONFIG_PPC_BOOK3E_32)   := head_new_booke.o
 extra-$(CONFIG_40x)             := head_40x.o
 extra-$(CONFIG_44x)             := head_44x.o
 extra-$(CONFIG_FSL_BOOKE)       := head_fsl_booke.o
@@ -88,7 +88,7 @@ obj-$(CONFIG_SWIOTLB)		+= dma-swiotlb.o
 
 pci64-$(CONFIG_PPC64)           += pci_dn.o isa-bridge.o
 obj-$(CONFIG_PCI)               += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
-                                   pci-common.o
+                                   pci-common.o pci_of_scan.o
 obj-$(CONFIG_PCI_MSI)           += msi.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o crash.o \
                                    machine_kexec_$(CONFIG_WORD_SIZE).o
@@ -115,6 +115,13 @@ ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),)
 obj-y                           += ppc_save_regs.o
 endif
 
+# Disable GCOV in odd or sensitive code
+GCOV_PROFILE_prom_init.o := n
+GCOV_PROFILE_ftrace.o := n
+GCOV_PROFILE_machine_kexec_64.o := n
+GCOV_PROFILE_machine_kexec_32.o := n
+GCOV_PROFILE_kprobes.o := n
+
 extra-$(CONFIG_PPC_FPU)         += fpu.o
 extra-$(CONFIG_ALTIVEC)         += vector.o
 extra-$(CONFIG_PPC64)           += entry_64.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 197b15646eeb..f0df285f0f87 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -52,9 +52,11 @@
 #include <linux/kvm_host.h>
 #endif
 
+#ifdef CONFIG_PPC32
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include "head_booke.h"
 #endif
+#endif
 
 #if defined(CONFIG_FSL_BOOKE)
 #include "../mm/mmu_decl.h"
@@ -140,6 +142,20 @@ int main(void)
                                             context.high_slices_psize));
         DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
 #endif /* CONFIG_PPC_MM_SLICES */
+
+#ifdef CONFIG_PPC_BOOK3E
+        DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
+        DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
+        DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
+        DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
+        DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
+        DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
+        DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
+        DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
+        DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
+        DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
+#endif /* CONFIG_PPC_BOOK3E */
+
 #ifdef CONFIG_PPC_STD_MMU_64
         DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
         DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
@@ -262,6 +278,7 @@ int main(void)
         DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
 #endif /* CONFIG_PPC64 */
 
+#if defined(CONFIG_PPC32)
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
         DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
         DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
@@ -280,7 +297,7 @@ int main(void)
         DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
         DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
 #endif
-
+#endif
         DEFINE(CLONE_VM, CLONE_VM);
         DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
 
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 1e9949e68856..55cba4a8a959 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -21,7 +21,7 @@ _GLOBAL(__setup_cpu_603)
         mflr    r4
 BEGIN_MMU_FTR_SECTION
         li      r10,0
-        mtspr   SPRN_SPRG4,r10          /* init SW LRU tracking */
+        mtspr   SPRN_SPRG_603_LRU,r10           /* init SW LRU tracking */
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 BEGIN_FTR_SECTION
         bl      __init_fpu_registers
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 4a24a2fc4574..0b9c9135922e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -89,11 +89,15 @@ extern void __restore_cpu_power7(void);
 #define COMMON_USER_PA6T        (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
                                  PPC_FEATURE_TRUE_LE | \
                                  PPC_FEATURE_HAS_ALTIVEC_COMP)
+#ifdef CONFIG_PPC_BOOK3E_64
+#define COMMON_USER_BOOKE       (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
+#else
 #define COMMON_USER_BOOKE       (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
                                  PPC_FEATURE_BOOKE)
+#endif
 
 static struct cpu_spec __initdata cpu_specs[] = {
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
         {       /* Power3 */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x00400000,
@@ -508,7 +512,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_generic,
                 .platform               = "power4",
         }
-#endif  /* CONFIG_PPC64 */
+#endif  /* CONFIG_PPC_BOOK3S_64 */
+
 #ifdef CONFIG_PPC32
 #if CLASSIC_PPC
         {       /* 601 */
@@ -1630,7 +1635,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .platform               = "ppc440",
         },
         { /* 460EX */
-                .pvr_mask               = 0xffff0002,
+                .pvr_mask               = 0xffff0006,
                 .pvr_value              = 0x13020002,
                 .cpu_name               = "460EX",
                 .cpu_features           = CPU_FTRS_440x6,
@@ -1642,8 +1647,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_440A,
                 .platform               = "ppc440",
         },
+        { /* 460EX Rev B */
+                .pvr_mask               = 0xffff0007,
+                .pvr_value              = 0x13020004,
+                .cpu_name               = "460EX Rev. B",
+                .cpu_features           = CPU_FTRS_440x6,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_44x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460ex,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
         { /* 460GT */
-                .pvr_mask               = 0xffff0002,
+                .pvr_mask               = 0xffff0006,
                 .pvr_value              = 0x13020000,
                 .cpu_name               = "460GT",
                 .cpu_features           = CPU_FTRS_440x6,
@@ -1655,6 +1673,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_440A,
                 .platform               = "ppc440",
         },
+        { /* 460GT Rev B */
+                .pvr_mask               = 0xffff0007,
+                .pvr_value              = 0x13020005,
+                .cpu_name               = "460GT Rev. B",
+                .cpu_features           = CPU_FTRS_440x6,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_44x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460gt,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
         { /* 460SX */
                 .pvr_mask               = 0xffffff00,
                 .pvr_value              = 0x13541800,
@@ -1797,6 +1828,29 @@ static struct cpu_spec __initdata cpu_specs[] = {
         }
 #endif /* CONFIG_E500 */
 #endif /* CONFIG_PPC32 */
+
+#ifdef CONFIG_PPC_BOOK3E_64
+        {       /* This is a default entry to get going, to be replaced by
+                 * a real one at some stage
+                 */
+#define CPU_FTRS_BASE_BOOK3E    (CPU_FTR_USE_TB | \
+            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
+            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
+                .pvr_mask               = 0x00000000,
+                .pvr_value              = 0x00000000,
+                .cpu_name               = "Book3E",
+                .cpu_features           = CPU_FTRS_BASE_BOOK3E,
+                .cpu_user_features      = COMMON_USER_PPC64,
+                .mmu_features           = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
+                                          MMU_FTR_USE_TLBIVAX_BCAST |
+                                          MMU_FTR_LOCK_BCAST_INVAL,
+                .icache_bsize           = 64,
+                .dcache_bsize           = 64,
+                .num_pmcs               = 0,
+                .machine_check          = machine_check_generic,
+                .platform               = "power6",
+        },
+#endif
 };
 
 static struct cpu_spec the_cpu_spec;
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 2983adac8cc3..87ddb3fb948c 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -89,7 +89,7 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask)
                 return 1;
 }
 
-struct dma_mapping_ops dma_iommu_ops = {
+struct dma_map_ops dma_iommu_ops = {
         .alloc_coherent = dma_iommu_alloc_coherent,
         .free_coherent  = dma_iommu_free_coherent,
         .map_sg         = dma_iommu_map_sg,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index e8a57de85bcf..e96cbbd9b449 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -25,33 +25,13 @@ int swiotlb __read_mostly;
 unsigned int ppc_swiotlb_enable;
 
 /*
- * Determine if an address is reachable by a pci device, or if we must bounce.
- */
-static int
-swiotlb_pci_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
-{
-        dma_addr_t max;
-        struct pci_controller *hose;
-        struct pci_dev *pdev = to_pci_dev(hwdev);
-
-        hose = pci_bus_to_host(pdev->bus);
-        max = hose->dma_window_base_cur + hose->dma_window_size;
-
-        /* check that we're within mapped pci window space */
-        if ((addr + size > max) | (addr < hose->dma_window_base_cur))
-                return 1;
-
-        return 0;
-}
-
-/*
  * At the moment, all platforms that use this code only require
  * swiotlb to be used if we're operating on HIGHMEM.  Since
  * we don't ever call anything other than map_sg, unmap_sg,
  * map_page, and unmap_page on highmem, use normal dma_ops
  * for everything else.
  */
-struct dma_mapping_ops swiotlb_dma_ops = {
+struct dma_map_ops swiotlb_dma_ops = {
         .alloc_coherent = dma_direct_alloc_coherent,
         .free_coherent = dma_direct_free_coherent,
         .map_sg = swiotlb_map_sg_attrs,
@@ -62,33 +42,34 @@ struct dma_mapping_ops swiotlb_dma_ops = {
         .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu,
         .sync_single_range_for_device = swiotlb_sync_single_range_for_device,
         .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
-        .sync_sg_for_device = swiotlb_sync_sg_for_device
+        .sync_sg_for_device = swiotlb_sync_sg_for_device,
+        .mapping_error = swiotlb_dma_mapping_error,
 };
 
-struct dma_mapping_ops swiotlb_pci_dma_ops = {
-        .alloc_coherent = dma_direct_alloc_coherent,
-        .free_coherent = dma_direct_free_coherent,
-        .map_sg = swiotlb_map_sg_attrs,
-        .unmap_sg = swiotlb_unmap_sg_attrs,
-        .dma_supported = swiotlb_dma_supported,
-        .map_page = swiotlb_map_page,
-        .unmap_page = swiotlb_unmap_page,
-        .addr_needs_map = swiotlb_pci_addr_needs_map,
-        .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu,
-        .sync_single_range_for_device = swiotlb_sync_single_range_for_device,
-        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
-        .sync_sg_for_device = swiotlb_sync_sg_for_device
-};
+void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)
+{
+        struct pci_controller *hose;
+        struct dev_archdata *sd;
+
+        hose = pci_bus_to_host(pdev->bus);
+        sd = &pdev->dev.archdata;
+        sd->max_direct_dma_addr =
+                hose->dma_window_base_cur + hose->dma_window_size;
+}
 
 static int ppc_swiotlb_bus_notify(struct notifier_block *nb,
                                   unsigned long action, void *data)
 {
         struct device *dev = data;
+        struct dev_archdata *sd;
 
         /* We are only intereted in device addition */
         if (action != BUS_NOTIFY_ADD_DEVICE)
                 return 0;
 
+        sd = &dev->archdata;
+        sd->max_direct_dma_addr = 0;
+
         /* May need to bounce if the device can't address all of DRAM */
         if (dma_get_mask(dev) < lmb_end_of_DRAM())
                 set_dma_ops(dev, &swiotlb_dma_ops);
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index ccf129d47d84..21b784d7e7d0 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -7,6 +7,7 @@
 
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/dma-debug.h>
 #include <linux/lmb.h>
 #include <asm/bug.h>
 #include <asm/abs_addr.h>
@@ -140,7 +141,7 @@ static inline void dma_direct_sync_single_range(struct device *dev,
 }
 #endif
 
-struct dma_mapping_ops dma_direct_ops = {
+struct dma_map_ops dma_direct_ops = {
         .alloc_coherent = dma_direct_alloc_coherent,
         .free_coherent  = dma_direct_free_coherent,
         .map_sg         = dma_direct_map_sg,
@@ -156,3 +157,13 @@ struct dma_mapping_ops dma_direct_ops = {
 #endif
 };
 EXPORT_SYMBOL(dma_direct_ops);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init dma_init(void)
+{
+       dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+       return 0;
+}
+fs_initcall(dma_init);
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 3cadba60a4b6..1175a8539e6c 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -88,7 +88,7 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,_SRR1(r11)
 
-        mfspr   r8,SPRN_SPRG3
+        mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,SAVED_KSP_LIMIT(r11)
         rlwimi  r0,r1,0,0,(31-THREAD_SHIFT)
@@ -108,7 +108,7 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,crit_srr1@l(0)
 
-        mfspr   r8,SPRN_SPRG3
+        mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,saved_ksp_limit@l(0)
         rlwimi  r0,r1,0,0,(31-THREAD_SHIFT)
@@ -138,7 +138,7 @@ transfer_to_handler:
         mfspr   r2,SPRN_XER
         stw     r12,_CTR(r11)
         stw     r2,_XER(r11)
-        mfspr   r12,SPRN_SPRG3
+        mfspr   r12,SPRN_SPRG_THREAD
         addi    r2,r12,-THREAD
         tovirt(r2,r2)                   /* set r2 to current */
         beq     2f                      /* if from user, fix up THREAD.regs */
@@ -680,7 +680,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE)
 
         tophys(r0,r4)
         CLR_TOP32(r0)
-        mtspr   SPRN_SPRG3,r0   /* Update current THREAD phys addr */
+        mtspr   SPRN_SPRG_THREAD,r0     /* Update current THREAD phys addr */
         lwz     r1,KSP(r4)      /* Load new stack pointer */
 
         /* save the old current 'last' for return value */
@@ -1057,7 +1057,7 @@ exc_exit_restart_end:
 #ifdef CONFIG_40x
         .globl  ret_from_crit_exc
 ret_from_crit_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lis     r10,saved_ksp_limit@ha;
         lwz     r10,saved_ksp_limit@l(r10);
         tovirt(r9,r9);
@@ -1074,7 +1074,7 @@ ret_from_crit_exc:
 #ifdef CONFIG_BOOKE
         .globl  ret_from_crit_exc
 ret_from_crit_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         RESTORE_xSRR(SRR0,SRR1);
@@ -1083,7 +1083,7 @@ ret_from_crit_exc:
 
         .globl  ret_from_debug_exc
 ret_from_debug_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         lwz     r9,THREAD_INFO-THREAD(r9)
@@ -1097,7 +1097,7 @@ ret_from_debug_exc:
 
         .globl  ret_from_mcheck_exc
 ret_from_mcheck_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         RESTORE_xSRR(SRR0,SRR1);
@@ -1255,7 +1255,7 @@ _GLOBAL(enter_rtas)
         MTMSRD(r0)              /* don't get trashed */
         li      r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
         mtlr    r6
-        mtspr   SPRN_SPRG2,r7
+        mtspr   SPRN_SPRG_RTAS,r7
         mtspr   SPRN_SRR0,r8
         mtspr   SPRN_SRR1,r9
         RFI
@@ -1265,7 +1265,7 @@ _GLOBAL(enter_rtas)
         FIX_SRR1(r9,r0)
         addi    r1,r1,INT_FRAME_SIZE
         li      r0,0
-        mtspr   SPRN_SPRG2,r0
+        mtspr   SPRN_SPRG_RTAS,r0
         mtspr   SPRN_SRR0,r8
         mtspr   SPRN_SRR1,r9
         RFI                     /* return to caller */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 43e073477c34..66bcda34a6bb 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -120,9 +120,15 @@ BEGIN_FW_FTR_SECTION
 2:
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
+
+        /* Hard enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         mfmsr   r11
         ori     r11,r11,MSR_EE
         mtmsrd  r11,1
+#endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef SHOW_SYSCALLS
         bl      .do_show_syscall
@@ -168,15 +174,25 @@ syscall_exit:
 #endif
         clrrdi  r12,r1,THREAD_SHIFT
 
-        /* disable interrupts so current_thread_info()->flags can't change,
-           and so that we don't get interrupted after loading SRR0/1. */
         ld      r8,_MSR(r1)
+#ifdef CONFIG_PPC_BOOK3S
+        /* No MSR:RI on BookE */
         andi.   r10,r8,MSR_RI
         beq-    unrecov_restore
+#endif
+
+        /* Disable interrupts so current_thread_info()->flags can't change,
+         * and so that we don't get interrupted after loading SRR0/1.
+         */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  0
+#else
         mfmsr   r10
         rldicl  r10,r10,48,1
         rotldi  r10,r10,16
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
+
         ld      r9,TI_FLAGS(r12)
         li      r11,-_LAST_ERRNO
         andi.   r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
@@ -194,9 +210,13 @@ syscall_error_cont:
          * userspace and we take an exception after restoring r13,
          * we end up corrupting the userspace r13 value.
          */
+#ifdef CONFIG_PPC_BOOK3S
+        /* No MSR:RI on BookE */
         li      r12,MSR_RI
         andc    r11,r10,r12
         mtmsrd  r11,1                   /* clear MSR.RI */
+#endif /* CONFIG_PPC_BOOK3S */
+
         beq-    1f
         ACCOUNT_CPU_USER_EXIT(r11, r12)
         ld      r13,GPR13(r1)   /* only restore r13 if returning to usermode */
@@ -206,7 +226,7 @@ syscall_error_cont:
         mtcr    r5
         mtspr   SPRN_SRR0,r7
         mtspr   SPRN_SRR1,r8
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
 
 syscall_error:  
@@ -276,9 +296,13 @@ syscall_exit_work:
         beq     .ret_from_except_lite
 
         /* Re-enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         mfmsr   r10
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
 
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -380,7 +404,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         and.    r0,r0,r22
         beq+    1f
         andc    r22,r22,r0
-        mtmsrd  r22
+        MTMSRD(r22)
         isync
 1:      std     r20,_NIP(r1)
         mfcr    r23
@@ -399,6 +423,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         std     r6,PACACURRENT(r13)     /* Set new 'current' */
 
         ld      r8,KSP(r4)      /* new stack pointer */
+#ifdef CONFIG_PPC_BOOK3S
 BEGIN_FTR_SECTION
   BEGIN_FTR_SECTION_NESTED(95)
         clrrdi  r6,r8,28        /* get its ESID */
@@ -445,8 +470,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
         slbie   r6              /* Workaround POWER5 < DD2.1 issue */
         slbmte  r7,r0
         isync
-
 2:
+#endif /* !CONFIG_PPC_BOOK3S */
+
         clrrdi  r7,r8,THREAD_SHIFT      /* base of new stack */
         /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
            because we don't need to leave the 288-byte ABI gap at the
@@ -490,10 +516,14 @@ _GLOBAL(ret_from_except_lite)
          * can't change between when we test it and when we return
          * from the interrupt.
          */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  0
+#else
         mfmsr   r10             /* Get current interrupt state */
         rldicl  r9,r10,48,1     /* clear MSR_EE */
         rotldi  r9,r9,16
         mtmsrd  r9,1            /* Update machine state */
+#endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef CONFIG_PREEMPT
         clrrdi  r9,r1,THREAD_SHIFT      /* current_thread_info() */
@@ -540,6 +570,9 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
         rldicl  r4,r3,49,63             /* r0 = (r3 >> 15) & 1 */
         stb     r4,PACAHARDIRQEN(r13)
 
+#ifdef CONFIG_PPC_BOOK3E
+        b       .exception_return_book3e
+#else
         ld      r4,_CTR(r1)
         ld      r0,_LINK(r1)
         mtctr   r4
@@ -588,6 +621,8 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
         rfid
         b       .       /* prevent speculative execution */
 
+#endif /* CONFIG_PPC_BOOK3E */
+
 iseries_check_pending_irqs:
 #ifdef CONFIG_PPC_ISERIES
         ld      r5,SOFTE(r1)
@@ -638,6 +673,11 @@ do_work:
         li      r0,1
         stb     r0,PACASOFTIRQEN(r13)
         stb     r0,PACAHARDIRQEN(r13)
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+        bl      .preempt_schedule
+        wrteei  0
+#else
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1           /* reenable interrupts */
         bl      .preempt_schedule
@@ -646,6 +686,7 @@ do_work:
         rldicl  r10,r10,48,1    /* disable interrupts again */
         rotldi  r10,r10,16
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
         ld      r4,TI_FLAGS(r9)
         andi.   r0,r4,_TIF_NEED_RESCHED
         bne     1b
@@ -654,8 +695,12 @@ do_work:
 user_work:
 #endif
         /* Enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
 
         andi.   r0,r4,_TIF_NEED_RESCHED
         beq     1f
@@ -762,7 +807,7 @@ _GLOBAL(enter_rtas)
 
 _STATIC(rtas_return_loc)
         /* relocation is off at this point */
-        mfspr   r4,SPRN_SPRG3           /* Get PACA */
+        mfspr   r4,SPRN_SPRG_PACA       /* Get PACA */
         clrldi  r4,r4,2                 /* convert to realmode address */
 
         bcl     20,31,$+4
@@ -793,7 +838,7 @@ _STATIC(rtas_restore_regs)
         REST_8GPRS(14, r1)              /* Restore the non-volatiles */
         REST_10GPRS(22, r1)             /* ditto */
 
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
 
         ld      r4,_CCR(r1)
         mtcr    r4
@@ -823,33 +868,24 @@ _GLOBAL(enter_prom)
          * of all registers that it saves.  We therefore save those registers
          * PROM might touch to the stack.  (r0, r3-r13 are caller saved)
          */
-        SAVE_8GPRS(2, r1)
+        SAVE_GPR(2, r1)
         SAVE_GPR(13, r1)
         SAVE_8GPRS(14, r1)
         SAVE_10GPRS(22, r1)
-        mfcr    r4
-        std     r4,_CCR(r1)
-        mfctr   r5
-        std     r5,_CTR(r1)
-        mfspr   r6,SPRN_XER
-        std     r6,_XER(r1)
-        mfdar   r7
-        std     r7,_DAR(r1)
-        mfdsisr r8
-        std     r8,_DSISR(r1)
-        mfsrr0  r9
-        std     r9,_SRR0(r1)
-        mfsrr1  r10
-        std     r10,_SRR1(r1)
+        mfcr    r10
         mfmsr   r11
+        std     r10,_CCR(r1)
         std     r11,_MSR(r1)
 
         /* Get the PROM entrypoint */
-        ld      r0,GPR4(r1)
-        mtlr    r0
+        mtlr    r4
 
         /* Switch MSR to 32 bits mode
          */
+#ifdef CONFIG_PPC_BOOK3E
+        rlwinm  r11,r11,0,1,31
+        mtmsr   r11
+#else /* CONFIG_PPC_BOOK3E */
         mfmsr   r11
         li      r12,1
         rldicr  r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
@@ -858,10 +894,10 @@ _GLOBAL(enter_prom)
         rldicr  r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
         andc    r11,r11,r12
         mtmsrd  r11
+#endif /* CONFIG_PPC_BOOK3E */
         isync
 
-        /* Restore arguments & enter PROM here... */
-        ld      r3,GPR3(r1)
+        /* Enter PROM here... */
         blrl
 
         /* Just make sure that r1 top 32 bits didn't get
@@ -871,7 +907,7 @@ _GLOBAL(enter_prom)
 
         /* Restore the MSR (back to 64 bits) */
         ld      r0,_MSR(r1)
-        mtmsrd  r0
+        MTMSRD(r0)
         isync
 
         /* Restore other registers */
@@ -881,18 +917,6 @@ _GLOBAL(enter_prom)
         REST_10GPRS(22, r1)
         ld      r4,_CCR(r1)
         mtcr    r4
-        ld      r5,_CTR(r1)
-        mtctr   r5
-        ld      r6,_XER(r1)
-        mtspr   SPRN_XER,r6
-        ld      r7,_DAR(r1)
-        mtdar   r7
-        ld      r8,_DSISR(r1)
-        mtdsisr r8
-        ld      r9,_SRR0(r1)
-        mtsrr0  r9
-        ld      r10,_SRR1(r1)
-        mtsrr1  r10
         
         addi    r1,r1,PROM_FRAME_SIZE
         ld      r0,16(r1)
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
new file mode 100644
index 000000000000..9048f96237f6
--- /dev/null
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -0,0 +1,1001 @@
+/*
+ *  Boot code and exception vectors for Book3E processors
+ *
+ *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cputable.h>
+#include <asm/setup.h>
+#include <asm/thread_info.h>
+#include <asm/reg.h>
+#include <asm/exception-64e.h>
+#include <asm/bug.h>
+#include <asm/irqflags.h>
+#include <asm/ptrace.h>
+#include <asm/ppc-opcode.h>
+#include <asm/mmu.h>
+
+/* XXX This will ultimately add space for a special exception save
+ *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
+ *     when taking special interrupts. For now we don't support that,
+ *     special interrupts from within a non-standard level will probably
+ *     blow you up
+ */
+#define SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
+
+/* Exception prolog code for all exceptions */
+#define EXCEPTION_PROLOG(n, type, addition)                                 \
+        mtspr   SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */   \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
+        std     r10,PACA_EX##type+EX_R10(r13);                              \
+        std     r11,PACA_EX##type+EX_R11(r13);                              \
+        mfcr    r10;                    /* save CR */                       \
+        addition;                       /* additional code for that exc. */ \
+        std     r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
+        stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
+        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
+        type##_SET_KSTACK;              /* get special stack if necessary */\
+        andi.   r10,r11,MSR_PR;         /* save stack pointer */            \
+        beq     1f;                     /* branch around if supervisor */   \
+        ld      r1,PACAKSAVE(r13);      /* get kernel stack coming from usr */\
+1:      cmpdi   cr1,r1,0;               /* check if SP makes sense */       \
+        bge-    cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
+        mfspr   r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
+
+/* Exception type-specific macros */
+#define GEN_SET_KSTACK                                                      \
+        subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack */
+#define SPRN_GEN_SRR0   SPRN_SRR0
+#define SPRN_GEN_SRR1   SPRN_SRR1
+
+#define CRIT_SET_KSTACK                                                     \
+        ld      r1,PACA_CRIT_STACK(r13);                                    \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_CRIT_SRR0  SPRN_CSRR0
+#define SPRN_CRIT_SRR1  SPRN_CSRR1
+
+#define DBG_SET_KSTACK                                                      \
+        ld      r1,PACA_DBG_STACK(r13);                                     \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_DBG_SRR0   SPRN_DSRR0
+#define SPRN_DBG_SRR1   SPRN_DSRR1
+
+#define MC_SET_KSTACK                                                       \
+        ld      r1,PACA_MC_STACK(r13);                                      \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_MC_SRR0    SPRN_MCSRR0
+#define SPRN_MC_SRR1    SPRN_MCSRR1
+
+#define NORMAL_EXCEPTION_PROLOG(n, addition)                                \
+        EXCEPTION_PROLOG(n, GEN, addition##_GEN)
+
+#define CRIT_EXCEPTION_PROLOG(n, addition)                                  \
+        EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
+
+#define DBG_EXCEPTION_PROLOG(n, addition)                                   \
+        EXCEPTION_PROLOG(n, DBG, addition##_DBG)
+
+#define MC_EXCEPTION_PROLOG(n, addition)                                    \
+        EXCEPTION_PROLOG(n, MC, addition##_MC)
+
+
+/* Variants of the "addition" argument for the prolog
+ */
+#define PROLOG_ADDITION_NONE_GEN
+#define PROLOG_ADDITION_NONE_CRIT
+#define PROLOG_ADDITION_NONE_DBG
+#define PROLOG_ADDITION_NONE_MC
+
+#define PROLOG_ADDITION_MASKABLE_GEN                                        \
+        lbz     r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
+        cmpwi   cr0,r11,0;              /* yes -> go out of line */         \
+        beq     masked_interrupt_book3e;
+
+#define PROLOG_ADDITION_2REGS_GEN                                           \
+        std     r14,PACA_EXGEN+EX_R14(r13);                                 \
+        std     r15,PACA_EXGEN+EX_R15(r13)
+
+#define PROLOG_ADDITION_1REG_GEN                                            \
+        std     r14,PACA_EXGEN+EX_R14(r13);
+
+#define PROLOG_ADDITION_2REGS_CRIT                                          \
+        std     r14,PACA_EXCRIT+EX_R14(r13);                                \
+        std     r15,PACA_EXCRIT+EX_R15(r13)
+
+#define PROLOG_ADDITION_2REGS_DBG                                           \
+        std     r14,PACA_EXDBG+EX_R14(r13);                                 \
+        std     r15,PACA_EXDBG+EX_R15(r13)
+
+#define PROLOG_ADDITION_2REGS_MC                                            \
+        std     r14,PACA_EXMC+EX_R14(r13);                                  \
+        std     r15,PACA_EXMC+EX_R15(r13)
+
+/* Core exception code for all exceptions except TLB misses.
+ * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
+ */
+#define EXCEPTION_COMMON(n, excf, ints)                                     \
+        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
+        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
+        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
+        std     r10,_NIP(r1);           /* save SRR0 to stackframe */       \
+        std     r11,_MSR(r1);           /* save SRR1 to stackframe */       \
+        ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */      \
+        ld      r3,excf+EX_R10(r13);    /* get back r10 */                  \
+        ld      r4,excf+EX_R11(r13);    /* get back r11 */                  \
+        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */                 \
+        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
+        ld      r2,PACATOC(r13);        /* get kernel TOC into r2 */        \
+        mflr    r6;                     /* save LR in stackframe */         \
+        mfctr   r7;                     /* save CTR in stackframe */        \
+        mfspr   r8,SPRN_XER;            /* save XER in stackframe */        \
+        ld      r9,excf+EX_R1(r13);     /* load orig r1 back from PACA */   \
+        lwz     r10,excf+EX_CR(r13);    /* load orig CR back from PACA  */  \
+        lbz     r11,PACASOFTIRQEN(r13); /* get current IRQ softe */         \
+        ld      r12,exception_marker@toc(r2);                               \
+        li      r0,0;                                                       \
+        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
+        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
+        std     r5,GPR13(r1);           /* save it to stackframe */         \
+        std     r6,_LINK(r1);                                               \
+        std     r7,_CTR(r1);                                                \
+        std     r8,_XER(r1);                                                \
+        li      r3,(n)+1;               /* indicate partial regs in trap */ \
+        std     r9,0(r1);               /* store stack frame back link */   \
+        std     r10,_CCR(r1);           /* store orig CR in stackframe */   \
+        std     r9,GPR1(r1);            /* store stack frame back link */   \
+        std     r11,SOFTE(r1);          /* and save it to stackframe */     \
+        std     r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */       \
+        std     r3,_TRAP(r1);           /* set trap number              */  \
+        std     r0,RESULT(r1);          /* clear regs->result */            \
+        ints;
+
+/* Variants for the "ints" argument */
+#define INTS_KEEP
+#define INTS_DISABLE_SOFT                                                   \
+        stb     r0,PACASOFTIRQEN(r13);  /* mark interrupts soft-disabled */ \
+        TRACE_DISABLE_INTS;
+#define INTS_DISABLE_HARD                                                   \
+        stb     r0,PACAHARDIRQEN(r13); /* and hard disabled */
+#define INTS_DISABLE_ALL                                                    \
+        INTS_DISABLE_SOFT                                                   \
+        INTS_DISABLE_HARD
+
+/* This is called by exceptions that used INTS_KEEP (that is did not clear
+ * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
+ * to it's previous value
+ *
+ * XXX In the long run, we may want to open-code it in order to separate the
+ *     load from the wrtee, thus limiting the latency caused by the dependency
+ *     but at this point, I'll favor code clarity until we have a near to final
+ *     implementation
+ */
+#define INTS_RESTORE_HARD                                                   \
+        ld      r11,_MSR(r1);                                               \
+        wrtee   r11;
+
+/* XXX FIXME: Restore r14/r15 when necessary */
+#define BAD_STACK_TRAMPOLINE(n)                                             \
+exc_##n##_bad_stack:                                                        \
+        li      r1,(n);                 /* get exception number */          \
+        sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
+        b       bad_stack_book3e;       /* bad stack error */
+
+#define EXCEPTION_STUB(loc, label)                                      \
+        . = interrupt_base_book3e + loc;                                \
+        nop;    /* To make debug interrupts happy */                    \
+        b       exc_##label##_book3e;
+
+#define ACK_NONE(r)
+#define ACK_DEC(r)                                                      \
+        lis     r,TSR_DIS@h;                                            \
+        mtspr   SPRN_TSR,r
+#define ACK_FIT(r)                                                      \
+        lis     r,TSR_FIS@h;                                            \
+        mtspr   SPRN_TSR,r
+
+#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
+        START_EXCEPTION(label);                                         \
+        NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
+        EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL)         \
+        ack(r8);                                                        \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
+        bl      hdlr;                                                   \
+        b       .ret_from_except_lite;
+
+/* This value is used to mark exception frames on the stack. */
+        .section        ".toc","aw"
+exception_marker:
+        .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
+
+
+/*
+ * And here we have the exception vectors !
+ */
+
+        .text
+        .balign 0x1000
+        .globl interrupt_base_book3e
+interrupt_base_book3e:                                  /* fake trap */
+        /* Note: If real debug exceptions are supported by the HW, the vector
+         * below will have to be patched up to point to an appropriate handler
+         */
+        EXCEPTION_STUB(0x000, machine_check)            /* 0x0200 */
+        EXCEPTION_STUB(0x020, critical_input)           /* 0x0580 */
+        EXCEPTION_STUB(0x040, debug_crit)               /* 0x0d00 */
+        EXCEPTION_STUB(0x060, data_storage)             /* 0x0300 */
+        EXCEPTION_STUB(0x080, instruction_storage)      /* 0x0400 */
+        EXCEPTION_STUB(0x0a0, external_input)           /* 0x0500 */
+        EXCEPTION_STUB(0x0c0, alignment)                /* 0x0600 */
+        EXCEPTION_STUB(0x0e0, program)                  /* 0x0700 */
+        EXCEPTION_STUB(0x100, fp_unavailable)           /* 0x0800 */
+        EXCEPTION_STUB(0x120, system_call)              /* 0x0c00 */
+        EXCEPTION_STUB(0x140, ap_unavailable)           /* 0x0f20 */
+        EXCEPTION_STUB(0x160, decrementer)              /* 0x0900 */
+        EXCEPTION_STUB(0x180, fixed_interval)           /* 0x0980 */
+        EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
+        EXCEPTION_STUB(0x1c0, data_tlb_miss)
+        EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
+
+#if 0
+        EXCEPTION_STUB(0x280, processor_doorbell)
+        EXCEPTION_STUB(0x220, processor_doorbell_crit)
+#endif
+        .globl interrupt_end_book3e
+interrupt_end_book3e:
+
+/* Critical Input Interrupt */
+        START_EXCEPTION(critical_input);
+        CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .critical_exception
+//      b       ret_from_crit_except
+        b       .
+
+/* Machine Check Interrupt */
+        START_EXCEPTION(machine_check);
+        CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
+//      bl      special_reg_save_mc
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .machine_check_exception
+//      b       ret_from_mc_except
+        b       .
+
+/* Data Storage Interrupt */
+        START_EXCEPTION(data_storage)
+        NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
+        mfspr   r14,SPRN_DEAR
+        mfspr   r15,SPRN_ESR
+        EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
+        b       storage_fault_common
+
+/* Instruction Storage Interrupt */
+        START_EXCEPTION(instruction_storage);
+        NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
+        li      r15,0
+        mr      r14,r10
+        EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
+        b       storage_fault_common
+
+/* External Input Interrupt */
+        MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
+
+/* Alignment */
+        START_EXCEPTION(alignment);
+        NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
+        mfspr   r14,SPRN_DEAR
+        mfspr   r15,SPRN_ESR
+        EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
+        b       alignment_more  /* no room, go out of line */
+
+/* Program Interrupt */
+        START_EXCEPTION(program);
+        NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
+        mfspr   r14,SPRN_ESR
+        EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
+        std     r14,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .program_check_exception
+        b       .ret_from_except
+
+/* Floating Point Unavailable Interrupt */
+        START_EXCEPTION(fp_unavailable);
+        NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
+        /* we can probably do a shorter exception entry for that one... */
+        EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
+        bne     1f                      /* if from user, just load it up */
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        INTS_RESTORE_HARD
+        bl      .kernel_fp_unavailable_exception
+        BUG_OPCODE
+1:      ld      r12,_MSR(r1)
+        bl      .load_up_fpu
+        b       fast_exception_return
+
+/* Decrementer Interrupt */
+        MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
+
+/* Fixed Interval Timer Interrupt */
+        MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
+
+/* Watchdog Timer Interrupt */
+        START_EXCEPTION(watchdog);
+        CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .unknown_exception
+//      b       ret_from_crit_except
+        b       .
+
+/* System Call Interrupt */
+        START_EXCEPTION(system_call)
+        mr      r9,r13                  /* keep a copy of userland r13 */
+        mfspr   r11,SPRN_SRR0           /* get return address */
+        mfspr   r12,SPRN_SRR1           /* get previous MSR */
+        mfspr   r13,SPRN_SPRG_PACA      /* get our PACA */
+        b       system_call_common
+
+/* Auxillary Processor Unavailable Interrupt */
+        START_EXCEPTION(ap_unavailable);
+        NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
+
+/* Debug exception as a critical interrupt*/
+        START_EXCEPTION(debug_crit);
+        CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+
+        /*
+         * If there is a single step or branch-taken exception in an
+         * exception entry sequence, it was probably meant to apply to
+         * the code where the exception occurred (since exception entry
+         * doesn't turn off DE automatically).  We simulate the effect
+         * of turning off DE on entry to an exception handler by turning
+         * off DE in the CSRR1 value and clearing the debug status.
+         */
+
+        mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
+        andis.  r15,r14,DBSR_IC@h
+        beq+    1f
+
+        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
+        LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
+        cmpld   cr0,r10,r14
+        cmpld   cr1,r10,r15
+        blt+    cr0,1f
+        bge+    cr1,1f
+
+        /* here it looks like we got an inappropriate debug exception. */
+        lis     r14,DBSR_IC@h           /* clear the IC event */
+        rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the CSRR1 value */
+        mtspr   SPRN_DBSR,r14
+        mtspr   SPRN_CSRR1,r11
+        lwz     r10,PACA_EXCRIT+EX_CR(r13)      /* restore registers */
+        ld      r1,PACA_EXCRIT+EX_R1(r13)
+        ld      r14,PACA_EXCRIT+EX_R14(r13)
+        ld      r15,PACA_EXCRIT+EX_R15(r13)
+        mtcr    r10
+        ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
+        ld      r11,PACA_EXCRIT+EX_R11(r13)
+        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
+        rfci
+
+        /* Normal debug exception */
+        /* XXX We only handle coming from userspace for now since we can't
+         *     quite save properly an interrupted kernel state yet
+         */
+1:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
+        beq     kernel_dbg_exc;         /* if from kernel mode */
+
+        /* Now we mash up things to make it look like we are coming on a
+         * normal exception
+         */
+        mfspr   r15,SPRN_SPRG_CRIT_SCRATCH
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r15
+        mfspr   r14,SPRN_DBSR
+        EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
+        std     r14,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        mr      r4,r14
+        ld      r14,PACA_EXCRIT+EX_R14(r13)
+        ld      r15,PACA_EXCRIT+EX_R15(r13)
+        bl      .save_nvgprs
+        bl      .DebugException
+        b       .ret_from_except
+
+kernel_dbg_exc:
+        b       .       /* NYI */
+
+
+/*
+ * An interrupt came in while soft-disabled; clear EE in SRR1,
+ * clear paca->hard_enabled and return.
+ */
+masked_interrupt_book3e:
+        mtcr    r10
+        stb     r11,PACAHARDIRQEN(r13)
+        mfspr   r10,SPRN_SRR1
+        rldicl  r11,r10,48,1            /* clear MSR_EE */
+        rotldi  r10,r11,16
+        mtspr   SPRN_SRR1,r10
+        ld      r10,PACA_EXGEN+EX_R10(r13);     /* restore registers */
+        ld      r11,PACA_EXGEN+EX_R11(r13);
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH;
+        rfi
+        b       .
+
+/*
+ * This is called from 0x300 and 0x400 handlers after the prologs with
+ * r14 and r15 containing the fault address and error code, with the
+ * original values stashed away in the PACA
+ */
+storage_fault_common:
+        std     r14,_DAR(r1)
+        std     r15,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        mr      r4,r14
+        mr      r5,r15
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        ld      r15,PACA_EXGEN+EX_R15(r13)
+        INTS_RESTORE_HARD
+        bl      .do_page_fault
+        cmpdi   r3,0
+        bne-    1f
+        b       .ret_from_except_lite
+1:      bl      .save_nvgprs
+        mr      r5,r3
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r4,_DAR(r1)
+        bl      .bad_page_fault
+        b       .ret_from_except
+
+/*
+ * Alignment exception doesn't fit entirely in the 0x100 bytes so it
+ * continues here.
+ */
+alignment_more:
+        std     r14,_DAR(r1)
+        std     r15,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        ld      r15,PACA_EXGEN+EX_R15(r13)
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .alignment_exception
+        b       .ret_from_except
+
+/*
+ * We branch here from entry_64.S for the last stage of the exception
+ * return code path. MSR:EE is expected to be off at that point
+ */
+_GLOBAL(exception_return_book3e)
+        b       1f
+
+/* This is the return from load_up_fpu fast path which could do with
+ * less GPR restores in fact, but for now we have a single return path
+ */
+        .globl fast_exception_return
+fast_exception_return:
+        wrteei  0
+1:      mr      r0,r13
+        ld      r10,_MSR(r1)
+        REST_4GPRS(2, r1)
+        andi.   r6,r10,MSR_PR
+        REST_2GPRS(6, r1)
+        beq     1f
+        ACCOUNT_CPU_USER_EXIT(r10, r11)
+        ld      r0,GPR13(r1)
+
+1:      stdcx.  r0,0,r1         /* to clear the reservation */
+
+        ld      r8,_CCR(r1)
+        ld      r9,_LINK(r1)
+        ld      r10,_CTR(r1)
+        ld      r11,_XER(r1)
+        mtcr    r8
+        mtlr    r9
+        mtctr   r10
+        mtxer   r11
+        REST_2GPRS(8, r1)
+        ld      r10,GPR10(r1)
+        ld      r11,GPR11(r1)
+        ld      r12,GPR12(r1)
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r0
+
+        std     r10,PACA_EXGEN+EX_R10(r13);
+        std     r11,PACA_EXGEN+EX_R11(r13);
+        ld      r10,_NIP(r1)
+        ld      r11,_MSR(r1)
+        ld      r0,GPR0(r1)
+        ld      r1,GPR1(r1)
+        mtspr   SPRN_SRR0,r10
+        mtspr   SPRN_SRR1,r11
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        ld      r11,PACA_EXGEN+EX_R11(r13)
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
+        rfi
+
+/*
+ * Trampolines used when spotting a bad kernel stack pointer in
+ * the exception entry code.
+ *
+ * TODO: move some bits like SRR0 read to trampoline, pass PACA
+ * index around, etc... to handle crit & mcheck
+ */
+BAD_STACK_TRAMPOLINE(0x000)
+BAD_STACK_TRAMPOLINE(0x100)
+BAD_STACK_TRAMPOLINE(0x200)
+BAD_STACK_TRAMPOLINE(0x300)
+BAD_STACK_TRAMPOLINE(0x400)
+BAD_STACK_TRAMPOLINE(0x500)
+BAD_STACK_TRAMPOLINE(0x600)
+BAD_STACK_TRAMPOLINE(0x700)
+BAD_STACK_TRAMPOLINE(0x800)
+BAD_STACK_TRAMPOLINE(0x900)
+BAD_STACK_TRAMPOLINE(0x980)
+BAD_STACK_TRAMPOLINE(0x9f0)
+BAD_STACK_TRAMPOLINE(0xa00)
+BAD_STACK_TRAMPOLINE(0xb00)
+BAD_STACK_TRAMPOLINE(0xc00)
+BAD_STACK_TRAMPOLINE(0xd00)
+BAD_STACK_TRAMPOLINE(0xe00)
+BAD_STACK_TRAMPOLINE(0xf00)
+BAD_STACK_TRAMPOLINE(0xf20)
+
+        .globl  bad_stack_book3e
+bad_stack_book3e:
+        /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
+        mfspr   r10,SPRN_SRR0;            /* read SRR0 before touching stack */
+        ld      r1,PACAEMERGSP(r13)
+        subi    r1,r1,64+INT_FRAME_SIZE
+        std     r10,_NIP(r1)
+        std     r11,_MSR(r1)
+        ld      r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
+        lwz     r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
+        std     r10,GPR1(r1)
+        std     r11,_CCR(r1)
+        mfspr   r10,SPRN_DEAR
+        mfspr   r11,SPRN_ESR
+        std     r10,_DAR(r1)
+        std     r11,_DSISR(r1)
+        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
+        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
+        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
+        ld      r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */                \
+        ld      r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */                \
+        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
+        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
+        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
+        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
+        std     r5,GPR13(r1);           /* save it to stackframe */         \
+        mflr    r10
+        mfctr   r11
+        mfxer   r12
+        std     r10,_LINK(r1)
+        std     r11,_CTR(r1)
+        std     r12,_XER(r1)
+        SAVE_10GPRS(14,r1)
+        SAVE_8GPRS(24,r1)
+        lhz     r12,PACA_TRAP_SAVE(r13)
+        std     r12,_TRAP(r1)
+        addi    r11,r1,INT_FRAME_SIZE
+        std     r11,0(r1)
+        li      r12,0
+        std     r12,0(r11)
+        ld      r2,PACATOC(r13)
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .kernel_bad_stack
+        b       1b
+
+/*
+ * Setup the initial TLB for a core. This current implementation
+ * assume that whatever we are running off will not conflict with
+ * the new mapping at PAGE_OFFSET.
+ */
+_GLOBAL(initial_tlb_book3e)
+
+        /* Look for the first TLB with IPROT set */
+        mfspr   r4,SPRN_TLB0CFG
+        andi.   r3,r4,TLBnCFG_IPROT
+        lis     r3,MAS0_TLBSEL(0)@h
+        bne     found_iprot
+
+        mfspr   r4,SPRN_TLB1CFG
+        andi.   r3,r4,TLBnCFG_IPROT
+        lis     r3,MAS0_TLBSEL(1)@h
+        bne     found_iprot
+
+        mfspr   r4,SPRN_TLB2CFG
+        andi.   r3,r4,TLBnCFG_IPROT
+        lis     r3,MAS0_TLBSEL(2)@h
+        bne     found_iprot
+
+        lis     r3,MAS0_TLBSEL(3)@h
+        mfspr   r4,SPRN_TLB3CFG
+        /* fall through */
+
+found_iprot:
+        andi.   r5,r4,TLBnCFG_HES
+        bne     have_hes
+
+        mflr    r8                              /* save LR */
+/* 1. Find the index of the entry we're executing in
+ *
+ * r3 = MAS0_TLBSEL (for the iprot array)
+ * r4 = SPRN_TLBnCFG
+ */
+        bl      invstr                          /* Find our address */
+invstr: mflr    r6                              /* Make it accessible */
+        mfmsr   r7
+        rlwinm  r5,r7,27,31,31                  /* extract MSR[IS] */
+        mfspr   r7,SPRN_PID
+        slwi    r7,r7,16
+        or      r7,r7,r5
+        mtspr   SPRN_MAS6,r7
+        tlbsx   0,r6                            /* search MSR[IS], SPID=PID */
+
+        mfspr   r3,SPRN_MAS0
+        rlwinm  r5,r3,16,20,31                  /* Extract MAS0(Entry) */
+
+        mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
+        oris    r7,r7,MAS1_IPROT@h
+        mtspr   SPRN_MAS1,r7
+        tlbwe
+
+/* 2. Invalidate all entries except the entry we're executing in
+ *
+ * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
+ * r4 = SPRN_TLBnCFG
+ * r5 = ESEL of entry we are running in
+ */
+        andi.   r4,r4,TLBnCFG_N_ENTRY           /* Extract # entries */
+        li      r6,0                            /* Set Entry counter to 0 */
+1:      mr      r7,r3                           /* Set MAS0(TLBSEL) */
+        rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
+        mtspr   SPRN_MAS0,r7
+        tlbre
+        mfspr   r7,SPRN_MAS1
+        rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
+        cmpw    r5,r6
+        beq     skpinv                          /* Dont update the current execution TLB */
+        mtspr   SPRN_MAS1,r7
+        tlbwe
+        isync
+skpinv: addi    r6,r6,1                         /* Increment */
+        cmpw    r6,r4                           /* Are we done? */
+        bne     1b                              /* If not, repeat */
+
+        /* Invalidate all TLBs */
+        PPC_TLBILX_ALL(0,0)
+        sync
+        isync
+
+/* 3. Setup a temp mapping and jump to it
+ *
+ * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
+ * r5 = ESEL of entry we are running in
+ */
+        andi.   r7,r5,0x1       /* Find an entry not used and is non-zero */
+        addi    r7,r7,0x1
+        mr      r4,r3           /* Set MAS0(TLBSEL) = 1 */
+        mtspr   SPRN_MAS0,r4
+        tlbre
+
+        rlwimi  r4,r7,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r7) */
+        mtspr   SPRN_MAS0,r4
+
+        mfspr   r7,SPRN_MAS1
+        xori    r6,r7,MAS1_TS           /* Setup TMP mapping in the other Address space */
+        mtspr   SPRN_MAS1,r6
+
+        tlbwe
+
+        mfmsr   r6
+        xori    r6,r6,MSR_IS
+        mtspr   SPRN_SRR1,r6
+        bl      1f              /* Find our address */
+1:      mflr    r6
+        addi    r6,r6,(2f - 1b)
+        mtspr   SPRN_SRR0,r6
+        rfi
+2:
+
+/* 4. Clear out PIDs & Search info
+ *
+ * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
+ * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
+ * r5 = MAS3
+ */
+        li      r6,0
+        mtspr   SPRN_MAS6,r6
+        mtspr   SPRN_PID,r6
+
+/* 5. Invalidate mapping we started in
+ *
+ * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
+ * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
+ * r5 = MAS3
+ */
+        mtspr   SPRN_MAS0,r3
+        tlbre
+        mfspr   r6,SPRN_MAS1
+        rlwinm  r6,r6,0,2,0     /* clear IPROT */
+        mtspr   SPRN_MAS1,r6
+        tlbwe
+
+        /* Invalidate TLB1 */
+        PPC_TLBILX_ALL(0,0)
+        sync
+        isync
+
+/* The mapping only needs to be cache-coherent on SMP */
+#ifdef CONFIG_SMP
+#define M_IF_SMP        MAS2_M
+#else
+#define M_IF_SMP        0
+#endif
+
+/* 6. Setup KERNELBASE mapping in TLB[0]
+ *
+ * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
+ * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
+ * r5 = MAS3
+ */
+        rlwinm  r3,r3,0,16,3    /* clear ESEL */
+        mtspr   SPRN_MAS0,r3
+        lis     r6,(MAS1_VALID|MAS1_IPROT)@h
+        ori     r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
+        mtspr   SPRN_MAS1,r6
+
+        LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
+        mtspr   SPRN_MAS2,r6
+
+        rlwinm  r5,r5,0,0,25
+        ori     r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
+        mtspr   SPRN_MAS3,r5
+        li      r5,-1
+        rlwinm  r5,r5,0,0,25
+
+        tlbwe
+
+/* 7. Jump to KERNELBASE mapping
+ *
+ * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
+ */
+        /* Now we branch the new virtual address mapped by this entry */
+        LOAD_REG_IMMEDIATE(r6,2f)
+        lis     r7,MSR_KERNEL@h
+        ori     r7,r7,MSR_KERNEL@l
+        mtspr   SPRN_SRR0,r6
+        mtspr   SPRN_SRR1,r7
+        rfi                             /* start execution out of TLB1[0] entry */
+2:
+
+/* 8. Clear out the temp mapping
+ *
+ * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
+ */
+        mtspr   SPRN_MAS0,r4
+        tlbre
+        mfspr   r5,SPRN_MAS1
+        rlwinm  r5,r5,0,2,0     /* clear IPROT */
+        mtspr   SPRN_MAS1,r5
+        tlbwe
+
+        /* Invalidate TLB1 */
+        PPC_TLBILX_ALL(0,0)
+        sync
+        isync
+
+        /* We translate LR and return */
+        tovirt(r8,r8)
+        mtlr    r8
+        blr
+
+have_hes:
+        /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
+         * kernel linear mapping. We also set MAS8 once for all here though
+         * that will have to be made dependent on whether we are running under
+         * a hypervisor I suppose.
+         */
+        ori     r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
+        mtspr   SPRN_MAS0,r3
+        lis     r3,(MAS1_VALID | MAS1_IPROT)@h
+        ori     r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
+        mtspr   SPRN_MAS1,r3
+        LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
+        mtspr   SPRN_MAS2,r3
+        li      r3,MAS3_SR | MAS3_SW | MAS3_SX
+        mtspr   SPRN_MAS7_MAS3,r3
+        li      r3,0
+        mtspr   SPRN_MAS8,r3
+
+        /* Write the TLB entry */
+        tlbwe
+
+        /* Now we branch the new virtual address mapped by this entry */
+        LOAD_REG_IMMEDIATE(r3,1f)
+        mtctr   r3
+        bctr
+
+1:      /* We are now running at PAGE_OFFSET, clean the TLB of everything
+         * else (XXX we should scan for bolted crap from the firmware too)
+         */
+        PPC_TLBILX(0,0,0)
+        sync
+        isync
+
+        /* We translate LR and return */
+        mflr    r3
+        tovirt(r3,r3)
+        mtlr    r3
+        blr
+
+/*
+ * Main entry (boot CPU, thread 0)
+ *
+ * We enter here from head_64.S, possibly after the prom_init trampoline
+ * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
+ * mode. Anything else is as it was left by the bootloader
+ *
+ * Initial requirements of this port:
+ *
+ * - Kernel loaded at 0 physical
+ * - A good lump of memory mapped 0:0 by UTLB entry 0
+ * - MSR:IS & MSR:DS set to 0
+ *
+ * Note that some of the above requirements will be relaxed in the future
+ * as the kernel becomes smarter at dealing with different initial conditions
+ * but for now you have to be careful
+ */
+_GLOBAL(start_initialization_book3e)
+        mflr    r28
+
+        /* First, we need to setup some initial TLBs to map the kernel
+         * text, data and bss at PAGE_OFFSET. We don't have a real mode
+         * and always use AS 0, so we just set it up to match our link
+         * address and never use 0 based addresses.
+         */
+        bl      .initial_tlb_book3e
+
+        /* Init global core bits */
+        bl      .init_core_book3e
+
+        /* Init per-thread bits */
+        bl      .init_thread_book3e
+
+        /* Return to common init code */
+        tovirt(r28,r28)
+        mtlr    r28
+        blr
+
+
+/*
+ * Secondary core/processor entry
+ *
+ * This is entered for thread 0 of a secondary core, all other threads
+ * are expected to be stopped. It's similar to start_initialization_book3e
+ * except that it's generally entered from the holding loop in head_64.S
+ * after CPUs have been gathered by Open Firmware.
+ *
+ * We assume we are in 32 bits mode running with whatever TLB entry was
+ * set for us by the firmware or POR engine.
+ */
+_GLOBAL(book3e_secondary_core_init_tlb_set)
+        li      r4,1
+        b       .generic_secondary_smp_init
+
+_GLOBAL(book3e_secondary_core_init)
+        mflr    r28
+
+        /* Do we need to setup initial TLB entry ? */
+        cmplwi  r4,0
+        bne     2f
+
+        /* Setup TLB for this core */
+        bl      .initial_tlb_book3e
+
+        /* We can return from the above running at a different
+         * address, so recalculate r2 (TOC)
+         */
+        bl      .relative_toc
+
+        /* Init global core bits */
+2:      bl      .init_core_book3e
+
+        /* Init per-thread bits */
+3:      bl      .init_thread_book3e
+
+        /* Return to common init code at proper virtual address.
+         *
+         * Due to various previous assumptions, we know we entered this
+         * function at either the final PAGE_OFFSET mapping or using a
+         * 1:1 mapping at 0, so we don't bother doing a complicated check
+         * here, we just ensure the return address has the right top bits.
+         *
+         * Note that if we ever want to be smarter about where we can be
+         * started from, we have to be careful that by the time we reach
+         * the code below we may already be running at a different location
+         * than the one we were called from since initial_tlb_book3e can
+         * have moved us already.
+         */
+        cmpdi   cr0,r28,0
+        blt     1f
+        lis     r3,PAGE_OFFSET@highest
+        sldi    r3,r3,32
+        or      r28,r28,r3
+1:      mtlr    r28
+        blr
+
+_GLOBAL(book3e_secondary_thread_init)
+        mflr    r28
+        b       3b
+
+_STATIC(init_core_book3e)
+        /* Establish the interrupt vector base */
+        LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
+        mtspr   SPRN_IVPR,r3
+        sync
+        blr
+
+_STATIC(init_thread_book3e)
+        lis     r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
+        mtspr   SPRN_EPCR,r3
+
+        /* Make sure interrupts are off */
+        wrteei  0
+
+        /* disable all timers and clear out status */
+        li      r3,0
+        mtspr   SPRN_TCR,r3
+        mfspr   r3,SPRN_TSR
+        mtspr   SPRN_TSR,r3
+
+        blr
+
+_GLOBAL(__setup_base_ivors)
+        SET_IVOR(0, 0x020) /* Critical Input */
+        SET_IVOR(1, 0x000) /* Machine Check */
+        SET_IVOR(2, 0x060) /* Data Storage */ 
+        SET_IVOR(3, 0x080) /* Instruction Storage */
+        SET_IVOR(4, 0x0a0) /* External Input */ 
+        SET_IVOR(5, 0x0c0) /* Alignment */ 
+        SET_IVOR(6, 0x0e0) /* Program */ 
+        SET_IVOR(7, 0x100) /* FP Unavailable */ 
+        SET_IVOR(8, 0x120) /* System Call */ 
+        SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 
+        SET_IVOR(10, 0x160) /* Decrementer */ 
+        SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 
+        SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 
+        SET_IVOR(13, 0x1c0) /* Data TLB Error */ 
+        SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
+        SET_IVOR(15, 0x040) /* Debug */
+
+        sync
+
+        blr
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 8ac85e08ffae..1808876edcc9 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -12,6 +12,8 @@
  *
  */
 
+#include <asm/exception-64s.h>
+
 /*
  * We layout physical memory as follows:
  * 0x0000 - 0x00ff : Secondary processor spin code
@@ -22,18 +24,6 @@
  * 0x8000 -        : Early init and support code
  */
 
-
-/*
- *   SPRG Usage
- *
- *   Register   Definition
- *
- *   SPRG0      reserved for hypervisor
- *   SPRG1      temp - used to save gpr
- *   SPRG2      temp - used to save gpr
- *   SPRG3      virt addr of paca
- */
-
 /*
  * This is the start of the interrupt handlers for pSeries
  * This code runs with relocation off.
@@ -51,34 +41,44 @@ __start_interrupts:
         . = 0x200
 _machine_check_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 
         . = 0x300
         .globl data_access_pSeries
 data_access_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
+        mtspr   SPRN_SPRG_SCRATCH0,r13
 BEGIN_FTR_SECTION
-        mtspr   SPRN_SPRG2,r12
-        mfspr   r13,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        srdi    r13,r13,60
-        rlwimi  r13,r12,16,0x20
-        mfcr    r12
-        cmpwi   r13,0x2c
+        mfspr   r13,SPRN_SPRG_PACA
+        std     r9,PACA_EXSLB+EX_R9(r13)
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        mfspr   r10,SPRN_DAR
+        mfspr   r9,SPRN_DSISR
+        srdi    r10,r10,60
+        rlwimi  r10,r9,16,0x20
+        mfcr    r9
+        cmpwi   r10,0x2c
         beq     do_stab_bolted_pSeries
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        ld      r11,PACA_EXSLB+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r12,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R13(r13)
+        EXCEPTION_PROLOG_PSERIES_1(data_access_common)
+FTR_SECTION_ELSE
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
 
         . = 0x380
         .globl data_access_slb_pSeries
 data_access_slb_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13
+        mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_DAR
         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
@@ -91,7 +91,7 @@ data_access_slb_pSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 #ifndef CONFIG_RELOCATABLE
@@ -115,8 +115,8 @@ data_access_slb_pSeries:
         .globl instruction_access_slb_pSeries
 instruction_access_slb_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13
+        mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
@@ -129,7 +129,7 @@ instruction_access_slb_pSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 #ifndef CONFIG_RELOCATABLE
@@ -159,7 +159,7 @@ BEGIN_FTR_SECTION
         beq-    1f
 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
         mr      r9,r13
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
         mfspr   r11,SPRN_SRR0
         ld      r12,PACAKBASE(r13)
         ld      r10,PACAKMSR(r13)
@@ -228,15 +228,17 @@ masked_interrupt:
         rotldi  r10,r10,16
         mtspr   SPRN_SRR1,r10
         ld      r10,PACA_EXGEN+EX_R10(r13)
-        mfspr   r13,SPRN_SPRG1
+        mfspr   r13,SPRN_SPRG_SCRATCH0
         rfid
         b       .
 
         .align  7
 do_stab_bolted_pSeries:
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-        EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXSLB+EX_R13(r13)
+        EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted)
 
 #ifdef CONFIG_PPC_PSERIES
 /*
@@ -246,14 +248,14 @@ do_stab_bolted_pSeries:
       .align 7
 system_reset_fwnmi:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
 
         .globl machine_check_fwnmi
       .align 7
 machine_check_fwnmi:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 
 #endif /* CONFIG_PPC_PSERIES */
@@ -268,7 +270,7 @@ slb_miss_user_pseries:
         std     r10,PACA_EXGEN+EX_R10(r13)
         std     r11,PACA_EXGEN+EX_R11(r13)
         std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG1
+        mfspr   r10,SPRG_SCRATCH0
         ld      r11,PACA_EXSLB+EX_R9(r13)
         ld      r12,PACA_EXSLB+EX_R3(r13)
         std     r10,PACA_EXGEN+EX_R13(r13)
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 2436df33c6f4..fc8f5b14019c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -91,7 +91,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif /* CONFIG_SMP */
         /* enable use of FP after return */
 #ifdef CONFIG_PPC32
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD             /* current task's THREAD (phys) */
         lwz     r4,THREAD_FPEXC_MODE(r5)
         ori     r9,r9,MSR_FP            /* enable FP for current */
         or      r9,r9,r4
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index fc2132942754..829c3fe7c5a2 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -244,8 +244,8 @@ __secondary_hold_acknowledge:
  * task's thread_struct.
  */
 #define EXCEPTION_PROLOG        \
-        mtspr   SPRN_SPRG0,r10; \
-        mtspr   SPRN_SPRG1,r11; \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; \
+        mtspr   SPRN_SPRG_SCRATCH1,r11; \
         mfcr    r10;            \
         EXCEPTION_PROLOG_1;     \
         EXCEPTION_PROLOG_2
@@ -255,7 +255,7 @@ __secondary_hold_acknowledge:
         andi.   r11,r11,MSR_PR; \
         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
         beq     1f;             \
-        mfspr   r11,SPRN_SPRG3; \
+        mfspr   r11,SPRN_SPRG_THREAD;   \
         lwz     r11,THREAD_INFO-THREAD(r11);    \
         addi    r11,r11,THREAD_SIZE;    \
         tophys(r11,r11);        \
@@ -267,9 +267,9 @@ __secondary_hold_acknowledge:
         stw     r10,_CCR(r11);          /* save registers */ \
         stw     r12,GPR12(r11); \
         stw     r9,GPR9(r11);   \
-        mfspr   r10,SPRN_SPRG0; \
+        mfspr   r10,SPRN_SPRG_SCRATCH0; \
         stw     r10,GPR10(r11); \
-        mfspr   r12,SPRN_SPRG1; \
+        mfspr   r12,SPRN_SPRG_SCRATCH1; \
         stw     r12,GPR11(r11); \
         mflr    r10;            \
         stw     r10,_LINK(r11); \
@@ -355,11 +355,11 @@ i##n:								\
  *      -- paulus.
  */
         . = 0x200
-        mtspr   SPRN_SPRG0,r10
-        mtspr   SPRN_SPRG1,r11
+        mtspr   SPRN_SPRG_SCRATCH0,r10
+        mtspr   SPRN_SPRG_SCRATCH1,r11
         mfcr    r10
 #ifdef CONFIG_PPC_CHRP
-        mfspr   r11,SPRN_SPRG2
+        mfspr   r11,SPRN_SPRG_RTAS
         cmpwi   0,r11,0
         bne     7f
 #endif /* CONFIG_PPC_CHRP */
@@ -367,7 +367,7 @@ i##n:								\
 7:      EXCEPTION_PROLOG_2
         addi    r3,r1,STACK_FRAME_OVERHEAD
 #ifdef CONFIG_PPC_CHRP
-        mfspr   r4,SPRN_SPRG2
+        mfspr   r4,SPRN_SPRG_RTAS
         cmpwi   cr1,r4,0
         bne     cr1,1f
 #endif
@@ -485,7 +485,7 @@ InstructionTLBMiss:
         mfspr   r3,SPRN_IMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -559,7 +559,7 @@ DataLoadTLBMiss:
         mfspr   r3,SPRN_DMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -598,12 +598,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
         mtcrf   0x80,r2
 BEGIN_MMU_FTR_SECTION
         li      r0,1
-        mfspr   r1,SPRN_SPRG4
+        mfspr   r1,SPRN_SPRG_603_LRU
         rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
         slw     r0,r0,r2
         xor     r1,r0,r1
         srw     r0,r1,r2
-        mtspr   SPRN_SPRG4,r1
+        mtspr   SPRN_SPRG_603_LRU,r1
         mfspr   r2,SPRN_SRR1
         rlwimi  r2,r0,31-14,14,14
         mtspr   SPRN_SRR1,r2
@@ -643,7 +643,7 @@ DataStoreTLBMiss:
         mfspr   r3,SPRN_DMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -678,12 +678,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
         mtcrf   0x80,r2
 BEGIN_MMU_FTR_SECTION
         li      r0,1
-        mfspr   r1,SPRN_SPRG4
+        mfspr   r1,SPRN_SPRG_603_LRU
         rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
         slw     r0,r0,r2
         xor     r1,r0,r1
         srw     r0,r1,r2
-        mtspr   SPRN_SPRG4,r1
+        mtspr   SPRN_SPRG_603_LRU,r1
         mfspr   r2,SPRN_SRR1
         rlwimi  r2,r0,31-14,14,14
         mtspr   SPRN_SRR1,r2
@@ -864,9 +864,9 @@ __secondary_start:
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* phys address of our thread_struct */
         CLR_TOP32(r4)
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
-        mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
+        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 
         /* enable MMU and jump to start_secondary */
         li      r4,MSR_KERNEL
@@ -947,9 +947,9 @@ start_here:
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
         CLR_TOP32(r4)
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
-        mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
+        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 
         /* stack */
         lis     r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 0c96911d4299..a90625f9b485 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -103,21 +103,21 @@ _ENTRY(saved_ksp_limit)
 
 /*
  * Exception vector entry code. This code runs with address translation
- * turned off (i.e. using physical addresses). We assume SPRG3 has the
- * physical address of the current task thread_struct.
+ * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
+ * the physical address of the current task thread_struct.
  * Note that we have to have decremented r1 before we write to any fields
  * of the exception frame, since a critical interrupt could occur at any
  * time, and it will write to the area immediately below the current r1.
  */
 #define NORMAL_EXCEPTION_PROLOG                                              \
-        mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
-        mtspr   SPRN_SPRG1,r11;                                              \
-        mtspr   SPRN_SPRG2,r1;                                               \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
+        mtspr   SPRN_SPRG_SCRATCH1,r11;                                      \
+        mtspr   SPRN_SPRG_SCRATCH2,r1;                                       \
         mfcr    r10;                    /* save CR in r10 for now          */\
         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
         andi.   r11,r11,MSR_PR;                                              \
         beq     1f;                                                          \
-        mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
+        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
         addi    r1,r1,THREAD_SIZE;                                           \
 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
@@ -125,13 +125,13 @@ _ENTRY(saved_ksp_limit)
         stw     r10,_CCR(r11);          /* save various registers          */\
         stw     r12,GPR12(r11);                                              \
         stw     r9,GPR9(r11);                                                \
-        mfspr   r10,SPRN_SPRG0;                                              \
+        mfspr   r10,SPRN_SPRG_SCRATCH0;                                      \
         stw     r10,GPR10(r11);                                              \
-        mfspr   r12,SPRN_SPRG1;                                              \
+        mfspr   r12,SPRN_SPRG_SCRATCH1;                                      \
         stw     r12,GPR11(r11);                                              \
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
-        mfspr   r10,SPRN_SPRG2;                                              \
+        mfspr   r10,SPRN_SPRG_SCRATCH2;                                      \
         mfspr   r12,SPRN_SRR0;                                               \
         stw     r10,GPR1(r11);                                               \
         mfspr   r9,SPRN_SRR1;                                                \
@@ -160,7 +160,7 @@ _ENTRY(saved_ksp_limit)
         lwz     r11,critirq_ctx@l(r11);                                      \
         beq     1f;                                                          \
         /* COMING FROM USER MODE */                                          \
-        mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
+        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 1:      addi    r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm  */\
         tophys(r11,r11);                                                     \
@@ -265,8 +265,8 @@ label:
  * and exit.  Otherwise, we call heavywight functions to do the work.
  */
         START_EXCEPTION(0x0300, DataStorage)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -275,12 +275,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
 
         /* First, check if it was a zone fault (which means a user
@@ -308,7 +308,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -355,15 +355,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         PPC405_ERR77_SYNC
         rfi                     /* Should sync shadow TLBs */
         b       .               /* prevent prefetch past rfi */
@@ -380,15 +380,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       DataAccess
 
 /*
@@ -466,8 +466,8 @@ label:
  * load TLB entries from the page table if they exist.
  */
         START_EXCEPTION(0x1100, DTLBMiss)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -476,12 +476,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
@@ -500,7 +500,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -550,15 +550,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       DataAccess
 
 /* 0x1200 - Instruction TLB Miss Exception
@@ -566,8 +566,8 @@ label:
  * registers and bailout to a different point.
  */
         START_EXCEPTION(0x1200, ITLBMiss)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10  /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -576,12 +576,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
@@ -600,7 +600,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -650,15 +650,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       InstructionAccess
 
         EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
@@ -803,15 +803,15 @@ finish_tlb_load:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         PPC405_ERR77_SYNC
         rfi                     /* Should sync shadow TLBs */
         b       .               /* prevent prefetch past rfi */
@@ -835,7 +835,7 @@ start_here:
         /* ptr to phys current thread */
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 18d8a1677c4d..711368b993f2 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -239,7 +239,7 @@ skpinv:	addi	r4,r4,1				/* Increment */
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@h
@@ -350,12 +350,12 @@ interrupt_base:
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10                /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -374,7 +374,7 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
         /* Load PID into MMUCR TID */
@@ -446,12 +446,12 @@ tlb_44x_patch_hwater_D:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       DataStorage
 
         /* Instruction TLB Error Interrupt */
@@ -461,12 +461,12 @@ tlb_44x_patch_hwater_D:
          * to a different point.
          */
         START_EXCEPTION(InstructionTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -485,7 +485,7 @@ tlb_44x_patch_hwater_D:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
         /* Load PID into MMUCR TID */
@@ -497,7 +497,7 @@ tlb_44x_patch_hwater_D:
         mtspr   SPRN_MMUCR,r12
 
         /* Make up the required permissions */
-        li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
+        li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
 
         /* Compute pgdir/pmd offset */
         rlwinm  r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
@@ -542,12 +542,12 @@ tlb_44x_patch_hwater_I:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       InstructionStorage
 
         /* Debug Interrupt */
@@ -593,12 +593,12 @@ finish_tlb_load:
 
         /* Done...restore registers and get out of here.
         */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         rfi                                     /* Force context change */
 
 /*
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 012505ebd9f9..c38afdb45d7b 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -36,7 +36,6 @@
 #include <asm/thread_info.h>
 #include <asm/firmware.h>
 #include <asm/page_64.h>
-#include <asm/exception.h>
 #include <asm/irqflags.h>
 
 /* The physical memory is layed out such that the secondary processor
@@ -122,10 +121,11 @@ __run_at_load:
  */
         .globl  __secondary_hold
 __secondary_hold:
+#ifndef CONFIG_PPC_BOOK3E
         mfmsr   r24
         ori     r24,r24,MSR_RI
         mtmsrd  r24                     /* RI on */
-
+#endif
         /* Grab our physical cpu number */
         mr      r24,r3
 
@@ -144,6 +144,7 @@ __secondary_hold:
         ld      r4,0(r4)                /* deref function descriptor */
         mtctr   r4
         mr      r3,r24
+        li      r4,0
         bctr
 #else
         BUG_OPCODE
@@ -164,21 +165,49 @@ exception_marker:
 #include "exceptions-64s.S"
 #endif
 
+_GLOBAL(generic_secondary_thread_init)
+        mr      r24,r3
+
+        /* turn on 64-bit mode */
+        bl      .enable_64b_mode
+
+        /* get a valid TOC pointer, wherever we're mapped at */
+        bl      .relative_toc
+
+#ifdef CONFIG_PPC_BOOK3E
+        /* Book3E initialization */
+        mr      r3,r24
+        bl      .book3e_secondary_thread_init
+#endif
+        b       generic_secondary_common_init
 
 /*
  * On pSeries and most other platforms, secondary processors spin
  * in the following code.
  * At entry, r3 = this processor's number (physical cpu id)
+ *
+ * On Book3E, r4 = 1 to indicate that the initial TLB entry for
+ * this core already exists (setup via some other mechanism such
+ * as SCOM before entry).
  */
 _GLOBAL(generic_secondary_smp_init)
         mr      r24,r3
-        
+        mr      r25,r4
+
         /* turn on 64-bit mode */
         bl      .enable_64b_mode
 
-        /* get the TOC pointer (real address) */
+        /* get a valid TOC pointer, wherever we're mapped at */
         bl      .relative_toc
 
+#ifdef CONFIG_PPC_BOOK3E
+        /* Book3E initialization */
+        mr      r3,r24
+        mr      r4,r25
+        bl      .book3e_secondary_core_init
+#endif
+
+generic_secondary_common_init:
         /* Set up a paca value for this processor. Since we have the
          * physical cpu id in r24, we need to search the pacas to find
          * which logical id maps to our physical one.
@@ -196,7 +225,12 @@ _GLOBAL(generic_secondary_smp_init)
         mr      r3,r24                  /* not found, copy phys to r3    */
         b       .kexec_wait             /* next kernel might do better   */
 
-2:      mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3   */
+2:      mtspr   SPRN_SPRG_PACA,r13      /* Save vaddr of paca in an SPRG */
+#ifdef CONFIG_PPC_BOOK3E
+        addi    r12,r13,PACA_EXTLB      /* and TLB exc frame in another  */
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r12
+#endif
+
         /* From now on, r24 is expected to be logical cpuid */
         mr      r24,r5
 3:      HMT_LOW
@@ -232,6 +266,7 @@ _GLOBAL(generic_secondary_smp_init)
  * Turn the MMU off.
  * Assumes we're mapped EA == RA if the MMU is on.
  */
+#ifdef CONFIG_PPC_BOOK3S
 _STATIC(__mmu_off)
         mfmsr   r3
         andi.   r0,r3,MSR_IR|MSR_DR
@@ -243,6 +278,7 @@ _STATIC(__mmu_off)
         sync
         rfid
         b       .       /* prevent speculative execution */
+#endif
 
 
 /*
@@ -280,6 +316,10 @@ _GLOBAL(__start_initialization_multiplatform)
         mr      r31,r3
         mr      r30,r4
 
+#ifdef CONFIG_PPC_BOOK3E
+        bl      .start_initialization_book3e
+        b       .__after_prom_start
+#else
         /* Setup some critical 970 SPRs before switching MMU off */
         mfspr   r0,SPRN_PVR
         srwi    r0,r0,16
@@ -297,6 +337,7 @@ _GLOBAL(__start_initialization_multiplatform)
         /* Switch off MMU if not already off */
         bl      .__mmu_off
         b       .__after_prom_start
+#endif /* CONFIG_PPC_BOOK3E */
 
 _INIT_STATIC(__boot_from_prom)
 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
@@ -359,10 +400,16 @@ _STATIC(__after_prom_start)
  * Note: This process overwrites the OF exception vectors.
  */
         li      r3,0                    /* target addr */
+#ifdef CONFIG_PPC_BOOK3E
+        tovirt(r3,r3)                   /* on booke, we already run at PAGE_OFFSET */
+#endif
         mr.     r4,r26                  /* In some cases the loader may  */
         beq     9f                      /* have already put us at zero */
         li      r6,0x100                /* Start offset, the first 0x100 */
                                         /* bytes were copied earlier.    */
+#ifdef CONFIG_PPC_BOOK3E
+        tovirt(r6,r6)                   /* on booke, we already run at PAGE_OFFSET */
+#endif
 
 #ifdef CONFIG_CRASH_DUMP
 /*
@@ -485,7 +532,7 @@ _GLOBAL(pmac_secondary_start)
         LOAD_REG_ADDR(r4,paca)          /* Get base vaddr of paca array */
         mulli   r13,r24,PACA_SIZE       /* Calculate vaddr of right paca */
         add     r13,r13,r4              /* for this processor.          */
-        mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3  */
+        mtspr   SPRN_SPRG_PACA,r13      /* Save vaddr of paca in an SPRG*/
 
         /* Create a temp kernel stack for use before relocation is on.  */
         ld      r1,PACAEMERGSP(r13)
@@ -503,11 +550,14 @@ _GLOBAL(pmac_secondary_start)
  *   1. Processor number
  *   2. Segment table pointer (virtual address)
  * On entry the following are set:
- *   r1 = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
- *   r24   = cpu# (in Linux terms)
- *   r13   = paca virtual address
- *   SPRG3 = paca virtual address
+ *   r1        = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
+ *   r24       = cpu# (in Linux terms)
+ *   r13       = paca virtual address
+ *   SPRG_PACA = paca virtual address
  */
+        .section ".text";
+        .align 2 ;
+
         .globl  __secondary_start
 __secondary_start:
         /* Set thread priority to MEDIUM */
@@ -544,7 +594,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
 
 /* 
@@ -565,11 +615,16 @@ _GLOBAL(start_secondary_prolog)
  */
 _GLOBAL(enable_64b_mode)
         mfmsr   r11                     /* grab the current MSR */
+#ifdef CONFIG_PPC_BOOK3E
+        oris    r11,r11,0x8000          /* CM bit set, we'll set ICM later */
+        mtmsr   r11
+#else /* CONFIG_PPC_BOOK3E */
         li      r12,(MSR_SF | MSR_ISF)@highest
         sldi    r12,r12,48
         or      r11,r11,r12
         mtmsrd  r11
         isync
+#endif
         blr
 
 /*
@@ -613,9 +668,11 @@ _INIT_STATIC(start_here_multiplatform)
         bdnz    3b
 4:
 
+#ifndef CONFIG_PPC_BOOK3E
         mfmsr   r6
         ori     r6,r6,MSR_RI
         mtmsrd  r6                      /* RI on */
+#endif
 
 #ifdef CONFIG_RELOCATABLE
         /* Save the physical address we're running at in kernstart_addr */
@@ -642,13 +699,13 @@ _INIT_STATIC(start_here_multiplatform)
 
         /* Restore parameters passed from prom_init/kexec */
         mr      r3,r31
-        bl      .early_setup            /* also sets r13 and SPRG3 */
+        bl      .early_setup            /* also sets r13 and SPRG_PACA */
 
         LOAD_REG_ADDR(r3, .start_here_common)
         ld      r4,PACAKMSR(r13)
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
         
         /* This is where all platforms converge execution */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 52ff8c53b93c..6ded19d01891 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -110,8 +110,8 @@ turn_on_mmu:
  * task's thread_struct.
  */
 #define EXCEPTION_PROLOG        \
-        mtspr   SPRN_SPRG0,r10; \
-        mtspr   SPRN_SPRG1,r11; \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; \
+        mtspr   SPRN_SPRG_SCRATCH1,r11; \
         mfcr    r10;            \
         EXCEPTION_PROLOG_1;     \
         EXCEPTION_PROLOG_2
@@ -121,7 +121,7 @@ turn_on_mmu:
         andi.   r11,r11,MSR_PR; \
         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
         beq     1f;             \
-        mfspr   r11,SPRN_SPRG3; \
+        mfspr   r11,SPRN_SPRG_THREAD;   \
         lwz     r11,THREAD_INFO-THREAD(r11);    \
         addi    r11,r11,THREAD_SIZE;    \
         tophys(r11,r11);        \
@@ -133,9 +133,9 @@ turn_on_mmu:
         stw     r10,_CCR(r11);          /* save registers */ \
         stw     r12,GPR12(r11); \
         stw     r9,GPR9(r11);   \
-        mfspr   r10,SPRN_SPRG0; \
+        mfspr   r10,SPRN_SPRG_SCRATCH0; \
         stw     r10,GPR10(r11); \
-        mfspr   r12,SPRN_SPRG1; \
+        mfspr   r12,SPRN_SPRG_SCRATCH1; \
         stw     r12,GPR11(r11); \
         mflr    r10;            \
         stw     r10,_LINK(r11); \
@@ -603,8 +603,9 @@ start_here:
         /* ptr to phys current thread */
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
+        /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
         mtspr   SPRN_SPRG2,r3   /* 0 => r1 has kernel sp */
 
         /* stack */
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 5f9febc8d143..50504ae39cb7 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -20,14 +20,14 @@
 #endif
 
 #define NORMAL_EXCEPTION_PROLOG                                              \
-        mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
-        mtspr   SPRN_SPRG1,r11;                                              \
-        mtspr   SPRN_SPRG4W,r1;                                              \
+        mtspr   SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\
+        mtspr   SPRN_SPRG_WSCRATCH1,r11;                                     \
+        mtspr   SPRN_SPRG_WSCRATCH2,r1;                                      \
         mfcr    r10;                    /* save CR in r10 for now          */\
         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
         andi.   r11,r11,MSR_PR;                                              \
         beq     1f;                                                          \
-        mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
+        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
         ALLOC_STACK_FRAME(r1, THREAD_SIZE);                                  \
 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
@@ -35,13 +35,13 @@
         stw     r10,_CCR(r11);          /* save various registers          */\
         stw     r12,GPR12(r11);                                              \
         stw     r9,GPR9(r11);                                                \
-        mfspr   r10,SPRN_SPRG0;                                              \
+        mfspr   r10,SPRN_SPRG_RSCRATCH0;                                        \
         stw     r10,GPR10(r11);                                              \
-        mfspr   r12,SPRN_SPRG1;                                              \
+        mfspr   r12,SPRN_SPRG_RSCRATCH1;                                     \
         stw     r12,GPR11(r11);                                              \
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
-        mfspr   r10,SPRN_SPRG4R;                                             \
+        mfspr   r10,SPRN_SPRG_RSCRATCH2;                                     \
         mfspr   r12,SPRN_SRR0;                                               \
         stw     r10,GPR1(r11);                                               \
         mfspr   r9,SPRN_SRR1;                                                \
@@ -69,21 +69,11 @@
  * providing configurations that micro-optimize space usage.
  */
 
-/* CRIT_SPRG only used in critical exception handling */
-#define CRIT_SPRG       SPRN_SPRG2
-/* MCHECK_SPRG only used in machine check exception handling */
-#define MCHECK_SPRG     SPRN_SPRG6W
-
-#define MCHECK_STACK_BASE       mcheckirq_ctx
+#define MC_STACK_BASE           mcheckirq_ctx
 #define CRIT_STACK_BASE         critirq_ctx
 
 /* only on e500mc/e200 */
-#define DEBUG_STACK_BASE        dbgirq_ctx
-#ifdef CONFIG_E200
-#define DEBUG_SPRG              SPRN_SPRG6W
-#else
-#define DEBUG_SPRG              SPRN_SPRG9
-#endif
+#define DBG_STACK_BASE          dbgirq_ctx
 
 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
 
@@ -110,7 +100,7 @@
  * critical/machine check exception stack at low physical addresses.
  */
 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
-        mtspr   exc_level##_SPRG,r8;                                         \
+        mtspr   SPRN_SPRG_WSCRATCH_##exc_level,r8;                           \
         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
         stw     r9,GPR9(r8);            /* save various registers          */\
         mfcr    r9;                     /* save CR in r9 for now           */\
@@ -119,7 +109,7 @@
         stw     r9,_CCR(r8);            /* save CR on stack                */\
         mfspr   r10,exc_level_srr1;     /* check whether user or kernel    */\
         andi.   r10,r10,MSR_PR;                                              \
-        mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
+        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
         beq     1f;                                                          \
@@ -140,7 +130,7 @@
         lwz     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);                      \
         stw     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);                       \
         mr      r11,r8;                                                      \
-2:      mfspr   r8,exc_level##_SPRG;                                         \
+2:      mfspr   r8,SPRN_SPRG_RSCRATCH_##exc_level;                           \
         stw     r12,GPR12(r11);         /* save various registers          */\
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
@@ -161,9 +151,9 @@
 #define CRITICAL_EXCEPTION_PROLOG \
                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
 #define DEBUG_EXCEPTION_PROLOG \
-                EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
+                EXC_LEVEL_EXCEPTION_PROLOG(DBG, SPRN_DSRR0, SPRN_DSRR1)
 #define MCHECK_EXCEPTION_PROLOG \
-                EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
+                EXC_LEVEL_EXCEPTION_PROLOG(MC, SPRN_MCSRR0, SPRN_MCSRR1)
 
 /*
  * Exception vectors.
@@ -282,13 +272,13 @@ label:
         mtspr   SPRN_DSRR1,r9;                                                \
         lwz     r9,GPR9(r11);                                                 \
         lwz     r12,GPR12(r11);                                               \
-        mtspr   DEBUG_SPRG,r8;                                                \
-        BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
+        mtspr   SPRN_SPRG_WSCRATCH_DBG,r8;                                    \
+        BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
         lwz     r10,GPR10(r8);                                                \
         lwz     r11,GPR11(r8);                                                \
-        mfspr   r8,DEBUG_SPRG;                                                \
+        mfspr   r8,SPRN_SPRG_RSCRATCH_DBG;                                    \
                                                                               \
-        PPC_RFDI;                                                                     \
+        PPC_RFDI;                                                             \
         b       .;                                                            \
                                                                               \
         /* continue normal handling for a debug exception... */               \
@@ -335,11 +325,11 @@ label:
         mtspr   SPRN_CSRR1,r9;                                                \
         lwz     r9,GPR9(r11);                                                 \
         lwz     r12,GPR12(r11);                                               \
-        mtspr   CRIT_SPRG,r8;                                                 \
+        mtspr   SPRN_SPRG_WSCRATCH_CRIT,r8;                                   \
         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
         lwz     r10,GPR10(r8);                                                \
         lwz     r11,GPR11(r8);                                                \
-        mfspr   r8,CRIT_SPRG;                                                 \
+        mfspr   r8,SPRN_SPRG_RSCRATCH_CRIT;                                   \
                                                                               \
         rfci;                                                                 \
         b       .;                                                            \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 5bdcc06d294c..975788ca05d2 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -361,7 +361,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@h
@@ -532,12 +532,12 @@ interrupt_base:
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -557,7 +557,7 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
 4:
@@ -575,7 +575,12 @@ interrupt_base:
          *       place or can we save a couple of instructions here ?
          */
         mfspr   r12,SPRN_ESR
+#ifdef CONFIG_PTE_64BIT
+        li      r13,_PAGE_PRESENT
+        oris    r13,r13,_PAGE_ACCESSED@h
+#else
         li      r13,_PAGE_PRESENT|_PAGE_ACCESSED
+#endif
         rlwimi  r13,r12,11,29,29
 
         FIND_PTE
@@ -598,12 +603,12 @@ interrupt_base:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       DataStorage
 
         /* Instruction TLB Error Interrupt */
@@ -613,12 +618,12 @@ interrupt_base:
          * to a different point.
          */
         START_EXCEPTION(InstructionTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -638,12 +643,17 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
 4:
         /* Make up the required permissions */
-        li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
+#ifdef CONFIG_PTE_64BIT
+        li      r13,_PAGE_PRESENT | _PAGE_EXEC
+        oris    r13,r13,_PAGE_ACCESSED@h
+#else
+        li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
+#endif
 
         FIND_PTE
         andc.   r13,r13,r11             /* Check permission */
@@ -666,12 +676,12 @@ interrupt_base:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       InstructionStorage
 
 #ifdef CONFIG_SPE
@@ -733,7 +743,7 @@ finish_tlb_load:
 
         mfspr   r12, SPRN_MAS2
 #ifdef CONFIG_PTE_64BIT
-        rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
+        rlwimi  r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
 #else
         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 #endif
@@ -742,23 +752,27 @@ finish_tlb_load:
 #endif
         mtspr   SPRN_MAS2, r12
 
-        li      r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
-        rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
-        and     r12, r11, r10
-        andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
-        slwi    r10, r12, 1
-        or      r10, r10, r12
-        iseleq  r12, r12, r10
-        
 #ifdef CONFIG_PTE_64BIT
-        rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
-        rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
+        rlwinm  r12, r11, 32-2, 26, 31  /* Move in perm bits */
+        andi.   r10, r11, _PAGE_DIRTY
+        bne     1f
+        li      r10, MAS3_SW | MAS3_UW
+        andc    r12, r12, r10
+1:      rlwimi  r12, r13, 20, 0, 11     /* grab RPN[32:43] */
+        rlwimi  r12, r11, 20, 12, 19    /* grab RPN[44:51] */
         mtspr   SPRN_MAS3, r12
 BEGIN_MMU_FTR_SECTION
-        srwi    r10, r13, 8             /* grab RPN[8:31] */
+        srwi    r10, r13, 12            /* grab RPN[12:31] */
         mtspr   SPRN_MAS7, r10
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
 #else
+        li      r10, (_PAGE_EXEC | _PAGE_PRESENT)
+        rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
+        and     r12, r11, r10
+        andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
+        slwi    r10, r12, 1
+        or      r10, r10, r12
+        iseleq  r12, r12, r10
         rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
         mtspr   SPRN_MAS3, r11
 #endif
@@ -790,12 +804,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
         tlbwe
 
         /* Done...restore registers and get out of here.  */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         rfi                                     /* Force context change */
 
 #ifdef CONFIG_SPE
@@ -839,7 +853,7 @@ load_up_spe:
 #endif /* !CONFIG_SMP */
         /* enable use of SPE after return */
         oris    r9,r9,MSR_SPE@h
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
         li      r4,1
         li      r10,THREAD_ACC
         stw     r4,THREAD_USED_SPE(r5)
@@ -1118,7 +1132,7 @@ __secondary_start:
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* address of our thread_struct */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* Setup the defaults for TLB entries */
         li      r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index 6e3f62493659..a4c8b38b0ba1 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -127,7 +127,7 @@ static int ibmebus_dma_supported(struct device *dev, u64 mask)
         return 1;
 }
 
-static struct dma_mapping_ops ibmebus_dma_ops = {
+static struct dma_map_ops ibmebus_dma_ops = {
         .alloc_coherent = ibmebus_alloc_coherent,
         .free_coherent  = ibmebus_free_coherent,
         .map_sg         = ibmebus_map_sg,
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 2419cc706ff1..ed0ac4e4b8d8 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -35,6 +35,7 @@
 #include <asm/prom.h>
 #include <asm/vdso_datapage.h>
 #include <asm/vio.h>
+#include <asm/mmu.h>
 
 #define MODULE_VERS "1.8"
 #define MODULE_NAME "lparcfg"
@@ -537,6 +538,8 @@ static int pseries_lparcfg_data(struct seq_file *m, void *v)
 
         seq_printf(m, "shared_processor_mode=%d\n", lppaca[0].shared_proc);
 
+        seq_printf(m, "slb_size=%d\n", mmu_slb_size);
+
         return 0;
 }
 
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 15f28e0de78d..da9c0c4c10f3 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -342,10 +342,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         addi    r3,r3,L1_CACHE_BYTES
         bdnz    1b
         sync                            /* wait for dcbst's to get to ram */
+#ifndef CONFIG_44x
         mtctr   r4
 2:      icbi    0,r6
         addi    r6,r6,L1_CACHE_BYTES
         bdnz    2b
+#else
+        /* Flash invalidate on 44x because we are passed kmapped addresses and
+           this doesn't work for userspace pages due to the virtually tagged
+           icache.  Sigh. */
+        iccci   0, r0
+#endif
         sync                            /* additional sync needed on g4 */
         isync
         blr
diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c
index 87df428e3588..1a4fc0d11a03 100644
--- a/arch/powerpc/kernel/of_platform.c
+++ b/arch/powerpc/kernel/of_platform.c
@@ -276,7 +276,7 @@ static int __devinit of_pci_phb_probe(struct of_device *dev,
 #endif /* CONFIG_EEH */
 
         /* Scan the bus */
-        scan_phb(phb);
+        pcibios_scan_phb(phb, dev->node);
         if (phb->bus == NULL)
                 return -ENXIO;
 
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index e9962c7f8a09..d16b1ea55d44 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -13,6 +13,7 @@
 #include <asm/lppaca.h>
 #include <asm/paca.h>
 #include <asm/sections.h>
+#include <asm/pgtable.h>
 
 /* This symbol is provided by the linker - let it fill in the paca
  * field correctly */
@@ -87,6 +88,8 @@ void __init initialise_pacas(void)
 
 #ifdef CONFIG_PPC_BOOK3S
                 new_paca->lppaca_ptr = &lppaca[cpu];
+#else
+                new_paca->kernel_pgd = swapper_pg_dir;
 #endif
                 new_paca->lock_token = 0x8000;
                 new_paca->paca_index = cpu;
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 5a56e97c5ac0..e9f4840096b3 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -50,14 +50,14 @@ resource_size_t isa_mem_base;
 unsigned int ppc_pci_flags = 0;
 
 
-static struct dma_mapping_ops *pci_dma_ops = &dma_direct_ops;
+static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
-void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
+void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 {
         pci_dma_ops = dma_ops;
 }
 
-struct dma_mapping_ops *get_pci_dma_ops(void)
+struct dma_map_ops *get_pci_dma_ops(void)
 {
         return pci_dma_ops;
 }
@@ -176,8 +176,6 @@ int pci_domain_nr(struct pci_bus *bus)
 }
 EXPORT_SYMBOL(pci_domain_nr);
 
-#ifdef CONFIG_PPC_OF
-
 /* This routine is meant to be used early during boot, when the
  * PCI bus numbers have not yet been assigned, and you need to
  * issue PCI config cycles to an OF device.
@@ -210,17 +208,11 @@ static ssize_t pci_show_devspec(struct device *dev,
         return sprintf(buf, "%s", np->full_name);
 }
 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
-#endif /* CONFIG_PPC_OF */
 
 /* Add sysfs properties */
 int pcibios_add_platform_entries(struct pci_dev *pdev)
 {
-#ifdef CONFIG_PPC_OF
         return device_create_file(&pdev->dev, &dev_attr_devspec);
-#else
-        return 0;
-#endif /* CONFIG_PPC_OF */
-
 }
 
 char __devinit *pcibios_setup(char *str)
@@ -1626,3 +1618,122 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
 
 }
 
+/*
+ * Null PCI config access functions, for the case when we can't
+ * find a hose.
+ */
+#define NULL_PCI_OP(rw, size, type)                                     \
+static int                                                              \
+null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
+{                                                                       \
+        return PCIBIOS_DEVICE_NOT_FOUND;                                \
+}
+
+static int
+null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
+                 int len, u32 *val)
+{
+        return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static int
+null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
+                  int len, u32 val)
+{
+        return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static struct pci_ops null_pci_ops =
+{
+        .read = null_read_config,
+        .write = null_write_config,
+};
+
+/*
+ * These functions are used early on before PCI scanning is done
+ * and all of the pci_dev and pci_bus structures have been created.
+ */
+static struct pci_bus *
+fake_pci_bus(struct pci_controller *hose, int busnr)
+{
+        static struct pci_bus bus;
+
+        if (hose == 0) {
+                printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
+        }
+        bus.number = busnr;
+        bus.sysdata = hose;
+        bus.ops = hose? hose->ops: &null_pci_ops;
+        return &bus;
+}
+
+#define EARLY_PCI_OP(rw, size, type)                                    \
+int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
+                               int devfn, int offset, type value)       \
+{                                                                       \
+        return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
+                                            devfn, offset, value);      \
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, word, u16 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, word, u16)
+EARLY_PCI_OP(write, dword, u32)
+
+extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
+int early_find_capability(struct pci_controller *hose, int bus, int devfn,
+                          int cap)
+{
+        return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
+}
+
+/**
+ * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
+ * @hose: Pointer to the PCI host controller instance structure
+ * @sysdata: value to use for sysdata pointer.  ppc32 and ppc64 differ here
+ *
+ * Note: the 'data' pointer is a temporary measure.  As 32 and 64 bit
+ * pci code gets merged, this parameter should become unnecessary because
+ * both will use the same value.
+ */
+void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata)
+{
+        struct pci_bus *bus;
+        struct device_node *node = hose->dn;
+        int mode;
+
+        pr_debug("PCI: Scanning PHB %s\n",
+                 node ? node->full_name : "<NO NAME>");
+
+        /* Create an empty bus for the toplevel */
+        bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops,
+                             sysdata);
+        if (bus == NULL) {
+                pr_err("Failed to create bus for PCI domain %04x\n",
+                        hose->global_number);
+                return;
+        }
+        bus->secondary = hose->first_busno;
+        hose->bus = bus;
+
+        /* Get some IO space for the new PHB */
+        pcibios_setup_phb_io_space(hose);
+
+        /* Wire up PHB bus resources */
+        pcibios_setup_phb_resources(hose);
+
+        /* Get probe mode and perform scan */
+        mode = PCI_PROBE_NORMAL;
+        if (node && ppc_md.pci_probe_mode)
+                mode = ppc_md.pci_probe_mode(bus);
+        pr_debug("    probe mode: %d\n", mode);
+        if (mode == PCI_PROBE_DEVTREE) {
+                bus->subordinate = hose->last_busno;
+                of_scan_bus(node, bus);
+        }
+
+        if (mode == PCI_PROBE_NORMAL)
+                hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
+}
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index 3ae1c666ff92..c13668cf36d9 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -34,9 +34,7 @@ int pcibios_assign_bus_offset = 1;
 void pcibios_make_OF_bus_map(void);
 
 static void fixup_cpc710_pci64(struct pci_dev* dev);
-#ifdef CONFIG_PPC_OF
 static u8* pci_to_OF_bus_map;
-#endif
 
 /* By default, we don't re-assign bus numbers. We do this only on
  * some pmacs
@@ -83,7 +81,6 @@ fixup_cpc710_pci64(struct pci_dev* dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
 
-#ifdef CONFIG_PPC_OF
 /*
  * Functions below are used on OpenFirmware machines.
  */
@@ -357,42 +354,15 @@ pci_create_OF_bus_map(void)
         }
 }
 
-#else /* CONFIG_PPC_OF */
-void pcibios_make_OF_bus_map(void)
+void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
 {
-}
-#endif /* CONFIG_PPC_OF */
-
-static void __devinit pcibios_scan_phb(struct pci_controller *hose)
-{
-        struct pci_bus *bus;
-        struct device_node *node = hose->dn;
         unsigned long io_offset;
         struct resource *res = &hose->io_resource;
 
-        pr_debug("PCI: Scanning PHB %s\n",
-                 node ? node->full_name : "<NO NAME>");
-
-        /* Create an empty bus for the toplevel */
-        bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
-        if (bus == NULL) {
-                printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
-                       hose->global_number);
-                return;
-        }
-        bus->secondary = hose->first_busno;
-        hose->bus = bus;
-
         /* Fixup IO space offset */
         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
         res->start = (res->start + io_offset) & 0xffffffffu;
         res->end = (res->end + io_offset) & 0xffffffffu;
-
-        /* Wire up PHB bus resources */
-        pcibios_setup_phb_resources(hose);
-
-        /* Scan children */
-        hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
 }
 
 static int __init pcibios_init(void)
@@ -410,7 +380,7 @@ static int __init pcibios_init(void)
                 if (pci_assign_all_buses)
                         hose->first_busno = next_busno;
                 hose->last_busno = 0xff;
-                pcibios_scan_phb(hose);
+                pcibios_scan_phb(hose, hose);
                 pci_bus_add_devices(hose->bus);
                 if (pci_assign_all_buses || next_busno <= hose->last_busno)
                         next_busno = hose->last_busno + pcibios_assign_bus_offset;
@@ -478,75 +448,4 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
         return result;
 }
 
-/*
- * Null PCI config access functions, for the case when we can't
- * find a hose.
- */
-#define NULL_PCI_OP(rw, size, type)                                     \
-static int                                                              \
-null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
-{                                                                       \
-        return PCIBIOS_DEVICE_NOT_FOUND;                                \
-}
 
-static int
-null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                 int len, u32 *val)
-{
-        return PCIBIOS_DEVICE_NOT_FOUND;
-}
-
-static int
-null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                  int len, u32 val)
-{
-        return PCIBIOS_DEVICE_NOT_FOUND;
-}
-
-static struct pci_ops null_pci_ops =
-{
-        .read = null_read_config,
-        .write = null_write_config,
-};
-
-/*
- * These functions are used early on before PCI scanning is done
- * and all of the pci_dev and pci_bus structures have been created.
- */
-static struct pci_bus *
-fake_pci_bus(struct pci_controller *hose, int busnr)
-{
-        static struct pci_bus bus;
-
-        if (hose == 0) {
-                hose = pci_bus_to_hose(busnr);
-                if (hose == 0)
-                        printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
-        }
-        bus.number = busnr;
-        bus.sysdata = hose;
-        bus.ops = hose? hose->ops: &null_pci_ops;
-        return &bus;
-}
-
-#define EARLY_PCI_OP(rw, size, type)                                    \
-int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
-                               int devfn, int offset, type value)       \
-{                                                                       \
-        return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
-                                            devfn, offset, value);      \
-}
-
-EARLY_PCI_OP(read, byte, u8 *)
-EARLY_PCI_OP(read, word, u16 *)
-EARLY_PCI_OP(read, dword, u32 *)
-EARLY_PCI_OP(write, byte, u8)
-EARLY_PCI_OP(write, word, u16)
-EARLY_PCI_OP(write, dword, u32)
-
-extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
-int early_find_capability(struct pci_controller *hose, int bus, int devfn,
-                          int cap)
-{
-        return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
-}
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 9e8902fa14c7..ba949a2c93ac 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -43,334 +43,6 @@ unsigned long pci_probe_only = 1;
 unsigned long pci_io_base = ISA_IO_BASE;
 EXPORT_SYMBOL(pci_io_base);
 
-static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
-{
-        const u32 *prop;
-        int len;
-
-        prop = of_get_property(np, name, &len);
-        if (prop && len >= 4)
-                return *prop;
-        return def;
-}
-
-static unsigned int pci_parse_of_flags(u32 addr0, int bridge)
-{
-        unsigned int flags = 0;
-
-        if (addr0 & 0x02000000) {
-                flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
-                flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
-                flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
-                if (addr0 & 0x40000000)
-                        flags |= IORESOURCE_PREFETCH
-                                 | PCI_BASE_ADDRESS_MEM_PREFETCH;
-                /* Note: We don't know whether the ROM has been left enabled
-                 * by the firmware or not. We mark it as disabled (ie, we do
-                 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
-                 * do a config space read, it will be force-enabled if needed
-                 */
-                if (!bridge && (addr0 & 0xff) == 0x30)
-                        flags |= IORESOURCE_READONLY;
-        } else if (addr0 & 0x01000000)
-                flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
-        if (flags)
-                flags |= IORESOURCE_SIZEALIGN;
-        return flags;
-}
-
-
-static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
-{
-        u64 base, size;
-        unsigned int flags;
-        struct resource *res;
-        const u32 *addrs;
-        u32 i;
-        int proplen;
-
-        addrs = of_get_property(node, "assigned-addresses", &proplen);
-        if (!addrs)
-                return;
-        pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
-        for (; proplen >= 20; proplen -= 20, addrs += 5) {
-                flags = pci_parse_of_flags(addrs[0], 0);
-                if (!flags)
-                        continue;
-                base = of_read_number(&addrs[1], 2);
-                size = of_read_number(&addrs[3], 2);
-                if (!size)
-                        continue;
-                i = addrs[0] & 0xff;
-                pr_debug("  base: %llx, size: %llx, i: %x\n",
-                         (unsigned long long)base,
-                         (unsigned long long)size, i);
-
-                if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
-                        res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
-                } else if (i == dev->rom_base_reg) {
-                        res = &dev->resource[PCI_ROM_RESOURCE];
-                        flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
-                } else {
-                        printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
-                        continue;
-                }
-                res->start = base;
-                res->end = base + size - 1;
-                res->flags = flags;
-                res->name = pci_name(dev);
-        }
-}
-
-struct pci_dev *of_create_pci_dev(struct device_node *node,
-                                 struct pci_bus *bus, int devfn)
-{
-        struct pci_dev *dev;
-        const char *type;
-
-        dev = alloc_pci_dev();
-        if (!dev)
-                return NULL;
-        type = of_get_property(node, "device_type", NULL);
-        if (type == NULL)
-                type = "";
-
-        pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
-
-        dev->bus = bus;
-        dev->sysdata = node;
-        dev->dev.parent = bus->bridge;
-        dev->dev.bus = &pci_bus_type;
-        dev->devfn = devfn;
-        dev->multifunction = 0;         /* maybe a lie? */
-
-        dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
-        dev->device = get_int_prop(node, "device-id", 0xffff);
-        dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
-        dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
-
-        dev->cfg_size = pci_cfg_space_size(dev);
-
-        dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
-                dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
-        dev->class = get_int_prop(node, "class-code", 0);
-        dev->revision = get_int_prop(node, "revision-id", 0);
-
-        pr_debug("    class: 0x%x\n", dev->class);
-        pr_debug("    revision: 0x%x\n", dev->revision);
-
-        dev->current_state = 4;         /* unknown power state */
-        dev->error_state = pci_channel_io_normal;
-        dev->dma_mask = 0xffffffff;
-
-        if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
-                /* a PCI-PCI bridge */
-                dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
-                dev->rom_base_reg = PCI_ROM_ADDRESS1;
-        } else if (!strcmp(type, "cardbus")) {
-                dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
-        } else {
-                dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
-                dev->rom_base_reg = PCI_ROM_ADDRESS;
-                /* Maybe do a default OF mapping here */
-                dev->irq = NO_IRQ;
-        }
-
-        pci_parse_of_addrs(node, dev);
-
-        pr_debug("    adding to system ...\n");
-
-        pci_device_add(dev, bus);
-
-        return dev;
-}
-EXPORT_SYMBOL(of_create_pci_dev);
-
-static void __devinit __of_scan_bus(struct device_node *node,
-                                    struct pci_bus *bus, int rescan_existing)
-{
-        struct device_node *child;
-        const u32 *reg;
-        int reglen, devfn;
-        struct pci_dev *dev;
-
-        pr_debug("of_scan_bus(%s) bus no %d... \n",
-                 node->full_name, bus->number);
-
-        /* Scan direct children */
-        for_each_child_of_node(node, child) {
-                pr_debug("  * %s\n", child->full_name);
-                reg = of_get_property(child, "reg", &reglen);
-                if (reg == NULL || reglen < 20)
-                        continue;
-                devfn = (reg[0] >> 8) & 0xff;
-
-                /* create a new pci_dev for this device */
-                dev = of_create_pci_dev(child, bus, devfn);
-                if (!dev)
-                        continue;
-                pr_debug("    dev header type: %x\n", dev->hdr_type);
-        }
-
-        /* Apply all fixups necessary. We don't fixup the bus "self"
-         * for an existing bridge that is being rescanned
-         */
-        if (!rescan_existing)
-                pcibios_setup_bus_self(bus);
-        pcibios_setup_bus_devices(bus);
-
-        /* Now scan child busses */
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
-                    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
-                        struct device_node *child = pci_device_to_OF_node(dev);
-                        if (dev)
-                                of_scan_pci_bridge(child, dev);
-                }
-        }
-}
-
-void __devinit of_scan_bus(struct device_node *node,
-                           struct pci_bus *bus)
-{
-        __of_scan_bus(node, bus, 0);
-}
-EXPORT_SYMBOL_GPL(of_scan_bus);
-
-void __devinit of_rescan_bus(struct device_node *node,
-                             struct pci_bus *bus)
-{
-        __of_scan_bus(node, bus, 1);
-}
-EXPORT_SYMBOL_GPL(of_rescan_bus);
-
-void __devinit of_scan_pci_bridge(struct device_node *node,
-                                  struct pci_dev *dev)
-{
-        struct pci_bus *bus;
-        const u32 *busrange, *ranges;
-        int len, i, mode;
-        struct resource *res;
-        unsigned int flags;
-        u64 size;
-
-        pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
-
-        /* parse bus-range property */
-        busrange = of_get_property(node, "bus-range", &len);
-        if (busrange == NULL || len != 8) {
-                printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
-                       node->full_name);
-                return;
-        }
-        ranges = of_get_property(node, "ranges", &len);
-        if (ranges == NULL) {
-                printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
-                       node->full_name);
-                return;
-        }
-
-        bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
-        if (!bus) {
-                printk(KERN_ERR "Failed to create pci bus for %s\n",
-                       node->full_name);
-                return;
-        }
-
-        bus->primary = dev->bus->number;
-        bus->subordinate = busrange[1];
-        bus->bridge_ctl = 0;
-        bus->sysdata = node;
-
-        /* parse ranges property */
-        /* PCI #address-cells == 3 and #size-cells == 2 always */
-        res = &dev->resource[PCI_BRIDGE_RESOURCES];
-        for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
-                res->flags = 0;
-                bus->resource[i] = res;
-                ++res;
-        }
-        i = 1;
-        for (; len >= 32; len -= 32, ranges += 8) {
-                flags = pci_parse_of_flags(ranges[0], 1);
-                size = of_read_number(&ranges[6], 2);
-                if (flags == 0 || size == 0)
-                        continue;
-                if (flags & IORESOURCE_IO) {
-                        res = bus->resource[0];
-                        if (res->flags) {
-                                printk(KERN_ERR "PCI: ignoring extra I/O range"
-                                       " for bridge %s\n", node->full_name);
-                                continue;
-                        }
-                } else {
-                        if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
-                                printk(KERN_ERR "PCI: too many memory ranges"
-                                       " for bridge %s\n", node->full_name);
-                                continue;
-                        }
-                        res = bus->resource[i];
-                        ++i;
-                }
-                res->start = of_read_number(&ranges[1], 2);
-                res->end = res->start + size - 1;
-                res->flags = flags;
-        }
-        sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
-                bus->number);
-        pr_debug("    bus name: %s\n", bus->name);
-
-        mode = PCI_PROBE_NORMAL;
-        if (ppc_md.pci_probe_mode)
-                mode = ppc_md.pci_probe_mode(bus);
-        pr_debug("    probe mode: %d\n", mode);
-
-        if (mode == PCI_PROBE_DEVTREE)
-                of_scan_bus(node, bus);
-        else if (mode == PCI_PROBE_NORMAL)
-                pci_scan_child_bus(bus);
-}
-EXPORT_SYMBOL(of_scan_pci_bridge);
-
-void __devinit scan_phb(struct pci_controller *hose)
-{
-        struct pci_bus *bus;
-        struct device_node *node = hose->dn;
-        int mode;
-
-        pr_debug("PCI: Scanning PHB %s\n",
-                 node ? node->full_name : "<NO NAME>");
-
-        /* Create an empty bus for the toplevel */
-        bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
-        if (bus == NULL) {
-                printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
-                       hose->global_number);
-                return;
-        }
-        bus->secondary = hose->first_busno;
-        hose->bus = bus;
-
-        /* Get some IO space for the new PHB */
-        pcibios_map_io_space(bus);
-
-        /* Wire up PHB bus resources */
-        pcibios_setup_phb_resources(hose);
-
-        /* Get probe mode and perform scan */
-        mode = PCI_PROBE_NORMAL;
-        if (node && ppc_md.pci_probe_mode)
-                mode = ppc_md.pci_probe_mode(bus);
-        pr_debug("    probe mode: %d\n", mode);
-        if (mode == PCI_PROBE_DEVTREE) {
-                bus->subordinate = hose->last_busno;
-                of_scan_bus(node, bus);
-        }
-
-        if (mode == PCI_PROBE_NORMAL)
-                hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
-}
-
 static int __init pcibios_init(void)
 {
         struct pci_controller *hose, *tmp;
@@ -392,7 +64,7 @@ static int __init pcibios_init(void)
 
         /* Scan all of the recorded PCI controllers.  */
         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
-                scan_phb(hose);
+                pcibios_scan_phb(hose, hose->dn);
                 pci_bus_add_devices(hose->bus);
         }
 
@@ -526,6 +198,11 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
 }
 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 
+void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
+{
+        pcibios_map_io_space(hose->bus);
+}
+
 #define IOBASE_BRIDGE_NUMBER    0
 #define IOBASE_MEMORY           1
 #define IOBASE_IO               2
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
new file mode 100644
index 000000000000..72c31bcb7aa4
--- /dev/null
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -0,0 +1,358 @@
+/*
+ * Helper routines to scan the device tree for PCI devices and busses
+ *
+ * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
+ * <grant.likely@secretlab.ca> so that these routines are available for
+ * 32 bit also.
+ *
+ * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
+ *   Rework, based on alpha PCI code.
+ * Copyright (c) 2009 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <asm/pci-bridge.h>
+#include <asm/prom.h>
+
+/**
+ * get_int_prop - Decode a u32 from a device tree property
+ */
+static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
+{
+        const u32 *prop;
+        int len;
+
+        prop = of_get_property(np, name, &len);
+        if (prop && len >= 4)
+                return *prop;
+        return def;
+}
+
+/**
+ * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
+ * @addr0: value of 1st cell of a device tree PCI address.
+ * @bridge: Set this flag if the address is from a bridge 'ranges' property
+ */
+unsigned int pci_parse_of_flags(u32 addr0, int bridge)
+{
+        unsigned int flags = 0;
+
+        if (addr0 & 0x02000000) {
+                flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
+                flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
+                flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
+                if (addr0 & 0x40000000)
+                        flags |= IORESOURCE_PREFETCH
+                                 | PCI_BASE_ADDRESS_MEM_PREFETCH;
+                /* Note: We don't know whether the ROM has been left enabled
+                 * by the firmware or not. We mark it as disabled (ie, we do
+                 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
+                 * do a config space read, it will be force-enabled if needed
+                 */
+                if (!bridge && (addr0 & 0xff) == 0x30)
+                        flags |= IORESOURCE_READONLY;
+        } else if (addr0 & 0x01000000)
+                flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
+        if (flags)
+                flags |= IORESOURCE_SIZEALIGN;
+        return flags;
+}
+
+/**
+ * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
+ * @node: device tree node for the PCI device
+ * @dev: pci_dev structure for the device
+ *
+ * This function parses the 'assigned-addresses' property of a PCI devices'
+ * device tree node and writes them into the associated pci_dev structure.
+ */
+static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
+{
+        u64 base, size;
+        unsigned int flags;
+        struct resource *res;
+        const u32 *addrs;
+        u32 i;
+        int proplen;
+
+        addrs = of_get_property(node, "assigned-addresses", &proplen);
+        if (!addrs)
+                return;
+        pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
+        for (; proplen >= 20; proplen -= 20, addrs += 5) {
+                flags = pci_parse_of_flags(addrs[0], 0);
+                if (!flags)
+                        continue;
+                base = of_read_number(&addrs[1], 2);
+                size = of_read_number(&addrs[3], 2);
+                if (!size)
+                        continue;
+                i = addrs[0] & 0xff;
+                pr_debug("  base: %llx, size: %llx, i: %x\n",
+                         (unsigned long long)base,
+                         (unsigned long long)size, i);
+
+                if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
+                        res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
+                } else if (i == dev->rom_base_reg) {
+                        res = &dev->resource[PCI_ROM_RESOURCE];
+                        flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
+                } else {
+                        printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
+                        continue;
+                }
+                res->start = base;
+                res->end = base + size - 1;
+                res->flags = flags;
+                res->name = pci_name(dev);
+        }
+}
+
+/**
+ * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
+ * @node: device tree node pointer
+ * @bus: bus the device is sitting on
+ * @devfn: PCI function number, extracted from device tree by caller.
+ */
+struct pci_dev *of_create_pci_dev(struct device_node *node,
+                                 struct pci_bus *bus, int devfn)
+{
+        struct pci_dev *dev;
+        const char *type;
+
+        dev = alloc_pci_dev();
+        if (!dev)
+                return NULL;
+        type = of_get_property(node, "device_type", NULL);
+        if (type == NULL)
+                type = "";
+
+        pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
+
+        dev->bus = bus;
+        dev->sysdata = node;
+        dev->dev.parent = bus->bridge;
+        dev->dev.bus = &pci_bus_type;
+        dev->devfn = devfn;
+        dev->multifunction = 0;         /* maybe a lie? */
+
+        dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
+        dev->device = get_int_prop(node, "device-id", 0xffff);
+        dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
+        dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
+
+        dev->cfg_size = pci_cfg_space_size(dev);
+
+        dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
+                dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+        dev->class = get_int_prop(node, "class-code", 0);
+        dev->revision = get_int_prop(node, "revision-id", 0);
+
+        pr_debug("    class: 0x%x\n", dev->class);
+        pr_debug("    revision: 0x%x\n", dev->revision);
+
+        dev->current_state = 4;         /* unknown power state */
+        dev->error_state = pci_channel_io_normal;
+        dev->dma_mask = 0xffffffff;
+
+        if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
+                /* a PCI-PCI bridge */
+                dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
+                dev->rom_base_reg = PCI_ROM_ADDRESS1;
+        } else if (!strcmp(type, "cardbus")) {
+                dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
+        } else {
+                dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
+                dev->rom_base_reg = PCI_ROM_ADDRESS;
+                /* Maybe do a default OF mapping here */
+                dev->irq = NO_IRQ;
+        }
+
+        of_pci_parse_addrs(node, dev);
+
+        pr_debug("    adding to system ...\n");
+
+        pci_device_add(dev, bus);
+
+        return dev;
+}
+EXPORT_SYMBOL(of_create_pci_dev);
+
+/**
+ * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
+ * @node: device tree node of bridge
+ * @dev: pci_dev structure for the bridge
+ *
+ * of_scan_bus() calls this routine for each PCI bridge that it finds, and
+ * this routine in turn call of_scan_bus() recusively to scan for more child
+ * devices.
+ */
+void __devinit of_scan_pci_bridge(struct device_node *node,
+                                  struct pci_dev *dev)
+{
+        struct pci_bus *bus;
+        const u32 *busrange, *ranges;
+        int len, i, mode;
+        struct resource *res;
+        unsigned int flags;
+        u64 size;
+
+        pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
+
+        /* parse bus-range property */
+        busrange = of_get_property(node, "bus-range", &len);
+        if (busrange == NULL || len != 8) {
+                printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
+                       node->full_name);
+                return;
+        }
+        ranges = of_get_property(node, "ranges", &len);
+        if (ranges == NULL) {
+                printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
+                       node->full_name);
+                return;
+        }
+
+        bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
+        if (!bus) {
+                printk(KERN_ERR "Failed to create pci bus for %s\n",
+                       node->full_name);
+                return;
+        }
+
+        bus->primary = dev->bus->number;
+        bus->subordinate = busrange[1];
+        bus->bridge_ctl = 0;
+        bus->sysdata = node;
+
+        /* parse ranges property */
+        /* PCI #address-cells == 3 and #size-cells == 2 always */
+        res = &dev->resource[PCI_BRIDGE_RESOURCES];
+        for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
+                res->flags = 0;
+                bus->resource[i] = res;
+                ++res;
+        }
+        i = 1;
+        for (; len >= 32; len -= 32, ranges += 8) {
+                flags = pci_parse_of_flags(ranges[0], 1);
+                size = of_read_number(&ranges[6], 2);
+                if (flags == 0 || size == 0)
+                        continue;
+                if (flags & IORESOURCE_IO) {
+                        res = bus->resource[0];
+                        if (res->flags) {
+                                printk(KERN_ERR "PCI: ignoring extra I/O range"
+                                       " for bridge %s\n", node->full_name);
+                                continue;
+                        }
+                } else {
+                        if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
+                                printk(KERN_ERR "PCI: too many memory ranges"
+                                       " for bridge %s\n", node->full_name);
+                                continue;
+                        }
+                        res = bus->resource[i];
+                        ++i;
+                }
+                res->start = of_read_number(&ranges[1], 2);
+                res->end = res->start + size - 1;
+                res->flags = flags;
+        }
+        sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
+                bus->number);
+        pr_debug("    bus name: %s\n", bus->name);
+
+        mode = PCI_PROBE_NORMAL;
+        if (ppc_md.pci_probe_mode)
+                mode = ppc_md.pci_probe_mode(bus);
+        pr_debug("    probe mode: %d\n", mode);
+
+        if (mode == PCI_PROBE_DEVTREE)
+                of_scan_bus(node, bus);
+        else if (mode == PCI_PROBE_NORMAL)
+                pci_scan_child_bus(bus);
+}
+EXPORT_SYMBOL(of_scan_pci_bridge);
+
+/**
+ * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
+ * @node: device tree node for the PCI bus
+ * @bus: pci_bus structure for the PCI bus
+ * @rescan_existing: Flag indicating bus has already been set up
+ */
+static void __devinit __of_scan_bus(struct device_node *node,
+                                    struct pci_bus *bus, int rescan_existing)
+{
+        struct device_node *child;
+        const u32 *reg;
+        int reglen, devfn;
+        struct pci_dev *dev;
+
+        pr_debug("of_scan_bus(%s) bus no %d... \n",
+                 node->full_name, bus->number);
+
+        /* Scan direct children */
+        for_each_child_of_node(node, child) {
+                pr_debug("  * %s\n", child->full_name);
+                reg = of_get_property(child, "reg", &reglen);
+                if (reg == NULL || reglen < 20)
+                        continue;
+                devfn = (reg[0] >> 8) & 0xff;
+
+                /* create a new pci_dev for this device */
+                dev = of_create_pci_dev(child, bus, devfn);
+                if (!dev)
+                        continue;
+                pr_debug("    dev header type: %x\n", dev->hdr_type);
+        }
+
+        /* Apply all fixups necessary. We don't fixup the bus "self"
+         * for an existing bridge that is being rescanned
+         */
+        if (!rescan_existing)
+                pcibios_setup_bus_self(bus);
+        pcibios_setup_bus_devices(bus);
+
+        /* Now scan child busses */
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
+                    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
+                        struct device_node *child = pci_device_to_OF_node(dev);
+                        if (dev)
+                                of_scan_pci_bridge(child, dev);
+                }
+        }
+}
+
+/**
+ * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
+ * @node: device tree node for the PCI bus
+ * @bus: pci_bus structure for the PCI bus
+ */
+void __devinit of_scan_bus(struct device_node *node,
+                           struct pci_bus *bus)
+{
+        __of_scan_bus(node, bus, 0);
+}
+EXPORT_SYMBOL_GPL(of_scan_bus);
+
+/**
+ * of_rescan_bus - given a PCI bus node, scan for child devices
+ * @node: device tree node for the PCI bus
+ * @bus: pci_bus structure for the PCI bus
+ *
+ * Same as of_scan_bus, but for a pci_bus structure that has already been
+ * setup.
+ */
+void __devinit of_rescan_bus(struct device_node *node,
+                             struct pci_bus *bus)
+{
+        __of_scan_bus(node, bus, 1);
+}
+EXPORT_SYMBOL_GPL(of_rescan_bus);
+
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index 70e1f57f7dd8..7ceefaf3a7f5 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -32,6 +32,9 @@ struct cpu_hw_counters {
         unsigned long mmcr[3];
         struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
         u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
+        u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+        unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+        unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 };
 DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
 
@@ -62,7 +65,6 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 {
         return 0;
 }
-static inline void perf_set_pmu_inuse(int inuse) { }
 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
@@ -93,11 +95,6 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
         return 0;
 }
 
-static inline void perf_set_pmu_inuse(int inuse)
-{
-        get_lppaca()->pmcregs_in_use = inuse;
-}
-
 /*
  * The user wants a data address recorded.
  * If we're not doing instruction sampling, give them the SDAR
@@ -245,13 +242,11 @@ static void write_pmc(int idx, unsigned long val)
  * and see if any combination of alternative codes is feasible.
  * The feasible set is returned in event[].
  */
-static int power_check_constraints(u64 event[], unsigned int cflags[],
+static int power_check_constraints(struct cpu_hw_counters *cpuhw,
+                                   u64 event[], unsigned int cflags[],
                                    int n_ev)
 {
         unsigned long mask, value, nv;
-        u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
-        unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
-        unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
         unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
         int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
         int i, j;
@@ -266,21 +261,23 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
                 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
                     && !ppmu->limited_pmc_event(event[i])) {
                         ppmu->get_alternatives(event[i], cflags[i],
-                                               alternatives[i]);
-                        event[i] = alternatives[i][0];
+                                               cpuhw->alternatives[i]);
+                        event[i] = cpuhw->alternatives[i][0];
                 }
-                if (ppmu->get_constraint(event[i], &amasks[i][0],
-                                         &avalues[i][0]))
+                if (ppmu->get_constraint(event[i], &cpuhw->amasks[i][0],
+                                         &cpuhw->avalues[i][0]))
                         return -1;
         }
         value = mask = 0;
         for (i = 0; i < n_ev; ++i) {
-                nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
+                nv = (value | cpuhw->avalues[i][0]) +
+                        (value & cpuhw->avalues[i][0] & addf);
                 if ((((nv + tadd) ^ value) & mask) != 0 ||
-                    (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
+                    (((nv + tadd) ^ cpuhw->avalues[i][0]) &
+                     cpuhw->amasks[i][0]) != 0)
                         break;
                 value = nv;
-                mask |= amasks[i][0];
+                mask |= cpuhw->amasks[i][0];
         }
         if (i == n_ev)
                 return 0;       /* all OK */
@@ -291,10 +288,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
         for (i = 0; i < n_ev; ++i) {
                 choice[i] = 0;
                 n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
-                                                  alternatives[i]);
+                                                  cpuhw->alternatives[i]);
                 for (j = 1; j < n_alt[i]; ++j)
-                        ppmu->get_constraint(alternatives[i][j],
-                                             &amasks[i][j], &avalues[i][j]);
+                        ppmu->get_constraint(cpuhw->alternatives[i][j],
+                                             &cpuhw->amasks[i][j],
+                                             &cpuhw->avalues[i][j]);
         }
 
         /* enumerate all possibilities and see if any will work */
@@ -313,11 +311,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
                  * where k > j, will satisfy the constraints.
                  */
                 while (++j < n_alt[i]) {
-                        nv = (value | avalues[i][j]) +
-                                (value & avalues[i][j] & addf);
+                        nv = (value | cpuhw->avalues[i][j]) +
+                                (value & cpuhw->avalues[i][j] & addf);
                         if ((((nv + tadd) ^ value) & mask) == 0 &&
-                            (((nv + tadd) ^ avalues[i][j])
-                             & amasks[i][j]) == 0)
+                            (((nv + tadd) ^ cpuhw->avalues[i][j])
+                             & cpuhw->amasks[i][j]) == 0)
                                 break;
                 }
                 if (j >= n_alt[i]) {
@@ -339,7 +337,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
                         svalues[i] = value;
                         smasks[i] = mask;
                         value = nv;
-                        mask |= amasks[i][j];
+                        mask |= cpuhw->amasks[i][j];
                         ++i;
                         j = -1;
                 }
@@ -347,7 +345,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
 
         /* OK, we have a feasible combination, tell the caller the solution */
         for (i = 0; i < n_ev; ++i)
-                event[i] = alternatives[i][choice[i]];
+                event[i] = cpuhw->alternatives[i][choice[i]];
         return 0;
 }
 
@@ -531,8 +529,7 @@ void hw_perf_disable(void)
                  * Check if we ever enabled the PMU on this cpu.
                  */
                 if (!cpuhw->pmcs_enabled) {
-                        if (ppc_md.enable_pmcs)
-                                ppc_md.enable_pmcs();
+                        ppc_enable_pmcs();
                         cpuhw->pmcs_enabled = 1;
                 }
 
@@ -594,7 +591,7 @@ void hw_perf_enable(void)
                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
                 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
                 if (cpuhw->n_counters == 0)
-                        perf_set_pmu_inuse(0);
+                        ppc_set_pmu_inuse(0);
                 goto out_enable;
         }
 
@@ -627,7 +624,7 @@ void hw_perf_enable(void)
          * bit set and set the hardware counters to their initial values.
          * Then unfreeze the counters.
          */
-        perf_set_pmu_inuse(1);
+        ppc_set_pmu_inuse(1);
         mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
         mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
         mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
@@ -752,7 +749,7 @@ int hw_perf_group_sched_in(struct perf_counter *group_leader,
                 return -EAGAIN;
         if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
                 return -EAGAIN;
-        i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
+        i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0);
         if (i < 0)
                 return -EAGAIN;
         cpuhw->n_counters = n0 + n;
@@ -807,7 +804,7 @@ static int power_pmu_enable(struct perf_counter *counter)
         cpuhw->flags[n0] = counter->hw.counter_base;
         if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
                 goto out;
-        if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
+        if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
                 goto out;
 
         counter->hw.config = cpuhw->events[n0];
@@ -1012,6 +1009,7 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
         unsigned int cflags[MAX_HWCOUNTERS];
         int n;
         int err;
+        struct cpu_hw_counters *cpuhw;
 
         if (!ppmu)
                 return ERR_PTR(-ENXIO);
@@ -1090,7 +1088,11 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
         cflags[n] = flags;
         if (check_excludes(ctrs, cflags, n, 1))
                 return ERR_PTR(-EINVAL);
-        if (power_check_constraints(events, cflags, n + 1))
+
+        cpuhw = &get_cpu_var(cpu_hw_counters);
+        err = power_check_constraints(cpuhw, events, cflags, n + 1);
+        put_cpu_var(cpu_hw_counters);
+        if (err)
                 return ERR_PTR(-EINVAL);
 
         counter->hw.config = events[n];
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 892a9f2e6d76..0a3216433051 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -284,14 +284,13 @@ int set_dabr(unsigned long dabr)
                 return ppc_md.set_dabr(dabr);
 
         /* XXX should we have a CPU_FTR_HAS_DABR ? */
-#if defined(CONFIG_PPC64) || defined(CONFIG_6xx)
-        mtspr(SPRN_DABR, dabr);
-#endif
-
 #if defined(CONFIG_BOOKE)
         mtspr(SPRN_DAC1, dabr);
+#elif defined(CONFIG_PPC_BOOK3S)
+        mtspr(SPRN_DABR, dabr);
 #endif
 
+
         return 0;
 }
 
@@ -372,15 +371,16 @@ struct task_struct *__switch_to(struct task_struct *prev,
 
 #endif /* CONFIG_SMP */
 
-        if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
-                set_dabr(new->thread.dabr);
-
 #if defined(CONFIG_BOOKE)
         /* If new thread DAC (HW breakpoint) is the same then leave it */
         if (new->thread.dabr)
                 set_dabr(new->thread.dabr);
+#else
+        if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
+                set_dabr(new->thread.dabr);
 #endif
 
+
         new_thread = &new->thread;
         old_thread = &current->thread;
 
@@ -664,6 +664,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
                 sp_vsid |= SLB_VSID_KERNEL | llp;
                 p->thread.ksp_vsid = sp_vsid;
         }
+#endif /* CONFIG_PPC_STD_MMU_64 */
 
         /*
          * The PPC64 ABI makes use of a TOC to contain function 
@@ -671,6 +672,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
          * to the TOC entry.  The first entry is a pointer to the actual
          * function.
          */
+#ifdef CONFIG_PPC64
         kregs->nip = *((unsigned long *)ret_from_fork);
 #else
         kregs->nip = (unsigned long)ret_from_fork;
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index a538824616fd..864334b337a3 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -190,6 +190,8 @@ static int __initdata of_platform;
 
 static char __initdata prom_cmd_line[COMMAND_LINE_SIZE];
 
+static unsigned long __initdata prom_memory_limit;
+
 static unsigned long __initdata alloc_top;
 static unsigned long __initdata alloc_top_high;
 static unsigned long __initdata alloc_bottom;
@@ -484,6 +486,67 @@ static int __init prom_setprop(phandle node, const char *nodename,
         return call_prom("interpret", 1, 1, (u32)(unsigned long) cmd);
 }
 
+/* We can't use the standard versions because of RELOC headaches. */
+#define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
+                         || ('a' <= (c) && (c) <= 'f') \
+                         || ('A' <= (c) && (c) <= 'F'))
+
+#define isdigit(c)      ('0' <= (c) && (c) <= '9')
+#define islower(c)      ('a' <= (c) && (c) <= 'z')
+#define toupper(c)      (islower(c) ? ((c) - 'a' + 'A') : (c))
+
+unsigned long prom_strtoul(const char *cp, const char **endp)
+{
+        unsigned long result = 0, base = 10, value;
+
+        if (*cp == '0') {
+                base = 8;
+                cp++;
+                if (toupper(*cp) == 'X') {
+                        cp++;
+                        base = 16;
+                }
+        }
+
+        while (isxdigit(*cp) &&
+               (value = isdigit(*cp) ? *cp - '0' : toupper(*cp) - 'A' + 10) < base) {
+                result = result * base + value;
+                cp++;
+        }
+
+        if (endp)
+                *endp = cp;
+
+        return result;
+}
+
+unsigned long prom_memparse(const char *ptr, const char **retptr)
+{
+        unsigned long ret = prom_strtoul(ptr, retptr);
+        int shift = 0;
+
+        /*
+         * We can't use a switch here because GCC *may* generate a
+         * jump table which won't work, because we're not running at
+         * the address we're linked at.
+         */
+        if ('G' == **retptr || 'g' == **retptr)
+                shift = 30;
+
+        if ('M' == **retptr || 'm' == **retptr)
+                shift = 20;
+
+        if ('K' == **retptr || 'k' == **retptr)
+                shift = 10;
+
+        if (shift) {
+                ret <<= shift;
+                (*retptr)++;
+        }
+
+        return ret;
+}
+
 /*
  * Early parsing of the command line passed to the kernel, used for
  * "mem=x" and the options that affect the iommu
@@ -491,9 +554,8 @@ static int __init prom_setprop(phandle node, const char *nodename,
 static void __init early_cmdline_parse(void)
 {
         struct prom_t *_prom = &RELOC(prom);
-#ifdef CONFIG_PPC64
         const char *opt;
-#endif
+
         char *p;
         int l = 0;
 
@@ -521,6 +583,15 @@ static void __init early_cmdline_parse(void)
                         RELOC(prom_iommu_force_on) = 1;
         }
 #endif
+        opt = strstr(RELOC(prom_cmd_line), RELOC("mem="));
+        if (opt) {
+                opt += 4;
+                RELOC(prom_memory_limit) = prom_memparse(opt, (const char **)&opt);
+#ifdef CONFIG_PPC64
+                /* Align to 16 MB == size of ppc64 large page */
+                RELOC(prom_memory_limit) = ALIGN(RELOC(prom_memory_limit), 0x1000000);
+#endif
+        }
 }
 
 #ifdef CONFIG_PPC_PSERIES
@@ -1027,6 +1098,29 @@ static void __init prom_init_mem(void)
         }
 
         /*
+         * If prom_memory_limit is set we reduce the upper limits *except* for
+         * alloc_top_high. This must be the real top of RAM so we can put
+         * TCE's up there.
+         */
+
+        RELOC(alloc_top_high) = RELOC(ram_top);
+
+        if (RELOC(prom_memory_limit)) {
+                if (RELOC(prom_memory_limit) <= RELOC(alloc_bottom)) {
+                        prom_printf("Ignoring mem=%x <= alloc_bottom.\n",
+                                RELOC(prom_memory_limit));
+                        RELOC(prom_memory_limit) = 0;
+                } else if (RELOC(prom_memory_limit) >= RELOC(ram_top)) {
+                        prom_printf("Ignoring mem=%x >= ram_top.\n",
+                                RELOC(prom_memory_limit));
+                        RELOC(prom_memory_limit) = 0;
+                } else {
+                        RELOC(ram_top) = RELOC(prom_memory_limit);
+                        RELOC(rmo_top) = min(RELOC(rmo_top), RELOC(prom_memory_limit));
+                }
+        }
+
+        /*
          * Setup our top alloc point, that is top of RMO or top of
          * segment 0 when running non-LPAR.
          * Some RS64 machines have buggy firmware where claims up at
@@ -1041,6 +1135,7 @@ static void __init prom_init_mem(void)
         RELOC(alloc_top_high) = RELOC(ram_top);
 
         prom_printf("memory layout at init:\n");
+        prom_printf("  memory_limit : %x (16 MB aligned)\n", RELOC(prom_memory_limit));
         prom_printf("  alloc_bottom : %x\n", RELOC(alloc_bottom));
         prom_printf("  alloc_top    : %x\n", RELOC(alloc_top));
         prom_printf("  alloc_top_hi : %x\n", RELOC(alloc_top_high));
@@ -1259,10 +1354,6 @@ static void __init prom_initialize_tce_table(void)
  *
  * -- Cort
  */
-extern char __secondary_hold;
-extern unsigned long __secondary_hold_spinloop;
-extern unsigned long __secondary_hold_acknowledge;
-
 /*
  * We want to reference the copy of __secondary_hold_* in the
  * 0 - 0x100 address range
@@ -2399,6 +2490,10 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
         /*
          * Fill in some infos for use by the kernel later on
          */
+        if (RELOC(prom_memory_limit))
+                prom_setprop(_prom->chosen, "/chosen", "linux,memory-limit",
+                             &RELOC(prom_memory_limit),
+                             sizeof(prom_memory_limit));
 #ifdef CONFIG_PPC64
         if (RELOC(prom_iommu_off))
                 prom_setprop(_prom->chosen, "/chosen", "linux,iommu-off",
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index c434823b8c83..bf90361bb70f 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -39,6 +39,7 @@
 #include <asm/smp.h>
 #include <asm/atomic.h>
 #include <asm/time.h>
+#include <asm/mmu.h>
 
 struct rtas_t rtas = {
         .lock = __RAW_SPIN_LOCK_UNLOCKED
@@ -713,6 +714,7 @@ static void rtas_percpu_suspend_me(void *info)
 {
         long rc = H_SUCCESS;
         unsigned long msr_save;
+        u16 slb_size = mmu_slb_size;
         int cpu;
         struct rtas_suspend_me_data *data =
                 (struct rtas_suspend_me_data *)info;
@@ -735,13 +737,16 @@ static void rtas_percpu_suspend_me(void *info)
                 /* All other cpus are in H_JOIN, this cpu does
                  * the suspend.
                  */
+                slb_set_size(SLB_MIN_SIZE);
                 printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n",
                        smp_processor_id());
                 data->error = rtas_call(data->token, 0, 1, NULL);
 
-                if (data->error)
+                if (data->error) {
                         printk(KERN_DEBUG "ibm,suspend-me returned %d\n",
                                data->error);
+                        slb_set_size(slb_size);
+                }
         } else {
                 printk(KERN_ERR "H_JOIN on cpu %i failed with rc = %ld\n",
                        smp_processor_id(), rc);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index e1e3059cf34b..53bcf3d792db 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -210,6 +210,14 @@ void nvram_write_byte(unsigned char val, int addr)
 }
 EXPORT_SYMBOL(nvram_write_byte);
 
+ssize_t nvram_get_size(void)
+{
+        if (ppc_md.nvram_size)
+                return ppc_md.nvram_size();
+        return -1;
+}
+EXPORT_SYMBOL(nvram_get_size);
+
 void nvram_sync(void)
 {
         if (ppc_md.nvram_sync)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index aa6e4500635f..797ea95aae2e 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -63,6 +63,7 @@
 #include <asm/udbg.h>
 #include <asm/kexec.h>
 #include <asm/swiotlb.h>
+#include <asm/mmu_context.h>
 
 #include "setup.h"
 
@@ -143,11 +144,14 @@ early_param("smt-enabled", early_smt_enabled);
 #define check_smt_enabled()
 #endif /* CONFIG_SMP */
 
-/* Put the paca pointer into r13 and SPRG3 */
+/* Put the paca pointer into r13 and SPRG_PACA */
 void __init setup_paca(int cpu)
 {
         local_paca = &paca[cpu];
-        mtspr(SPRN_SPRG3, local_paca);
+        mtspr(SPRN_SPRG_PACA, local_paca);
+#ifdef CONFIG_PPC_BOOK3E
+        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
+#endif
 }
 
 /*
@@ -231,9 +235,6 @@ void early_setup_secondary(void)
 #endif /* CONFIG_SMP */
 
 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
-extern unsigned long __secondary_hold_spinloop;
-extern void generic_secondary_smp_init(void);
-
 void smp_release_cpus(void)
 {
         unsigned long *ptr;
@@ -454,6 +455,24 @@ static void __init irqstack_early_init(void)
 #define irqstack_early_init()
 #endif
 
+#ifdef CONFIG_PPC_BOOK3E
+static void __init exc_lvl_early_init(void)
+{
+        unsigned int i;
+
+        for_each_possible_cpu(i) {
+                critirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+                dbgirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+                mcheckirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+        }
+}
+#else
+#define exc_lvl_early_init()
+#endif
+
 /*
  * Stack space used when we detect a bad kernel stack pointer, and
  * early in SMP boots before relocation is enabled.
@@ -513,6 +532,7 @@ void __init setup_arch(char **cmdline_p)
         init_mm.brk = klimit;
         
         irqstack_early_init();
+        exc_lvl_early_init();
         emergency_stack_init();
 
 #ifdef CONFIG_PPC_STD_MMU_64
@@ -535,6 +555,10 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
         paging_init();
+
+        /* Initialize the MMU context management stuff */
+        mmu_context_init();
+
         ppc64_boot_msg(0x15, "Setup Done");
 }
 
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 0b47de07302d..d387b3937ccc 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -269,7 +269,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         cpu_callin_map[boot_cpuid] = 1;
 
         if (smp_ops)
-                max_cpus = smp_ops->probe();
+                if (smp_ops->probe)
+                        max_cpus = smp_ops->probe();
+                else
+                        max_cpus = NR_CPUS;
         else
                 max_cpus = 1;
  
@@ -412,9 +415,8 @@ int __cpuinit __cpu_up(unsigned int cpu)
                  * CPUs can take much longer to come up in the
                  * hotplug case.  Wait five seconds.
                  */
-                for (c = 25; c && !cpu_callin_map[cpu]; c--) {
-                        msleep(200);
-                }
+                for (c = 5000; c && !cpu_callin_map[cpu]; c--)
+                        msleep(1);
 #endif
 
         if (!cpu_callin_map[cpu]) {
@@ -494,7 +496,8 @@ int __devinit start_secondary(void *unused)
         preempt_disable();
         cpu_callin_map[cpu] = 1;
 
-        smp_ops->setup_cpu(cpu);
+        if (smp_ops->setup_cpu)
+                smp_ops->setup_cpu(cpu);
         if (smp_ops->take_timebase)
                 smp_ops->take_timebase();
 
@@ -557,7 +560,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
         old_mask = current->cpus_allowed;
         set_cpus_allowed(current, cpumask_of_cpu(boot_cpuid));
         
-        if (smp_ops)
+        if (smp_ops && smp_ops->setup_cpu)
                 smp_ops->setup_cpu(boot_cpuid);
 
         set_cpus_allowed(current, old_mask);
diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
index bb1cfcfdbbbb..1cc5e9e5da96 100644
--- a/arch/powerpc/kernel/sys_ppc32.c
+++ b/arch/powerpc/kernel/sys_ppc32.c
@@ -343,6 +343,18 @@ off_t ppc32_lseek(unsigned int fd, u32 offset, unsigned int origin)
         return sys_lseek(fd, (int)offset, origin);
 }
 
+long compat_sys_truncate(const char __user * path, u32 length)
+{
+        /* sign extend length */
+        return sys_truncate(path, (int)length);
+}
+
+long compat_sys_ftruncate(int fd, u32 length)
+{
+        /* sign extend length */
+        return sys_ftruncate(fd, (int)length);
+}
+
 /* Note: it is necessary to treat bufsiz as an unsigned int,
  * with the corresponding cast to a signed int to insure that the 
  * proper conversion (sign extension) between the register representation of a signed int (msr in 32-bit mode)
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index f41aec85aa49..956ab33fd73f 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -17,6 +17,7 @@
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/smp.h>
+#include <asm/pmc.h>
 
 #include "cacheinfo.h"
 
@@ -123,6 +124,8 @@ static DEFINE_PER_CPU(char, pmcs_enabled);
 
 void ppc_enable_pmcs(void)
 {
+        ppc_set_pmu_inuse(1);
+
         /* Only need to enable them once */
         if (__get_cpu_var(pmcs_enabled))
                 return;
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index eae4511ceeac..a180b4f9a4f6 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -479,7 +479,8 @@ static int __init iSeries_tb_recal(void)
                 unsigned long tb_ticks = tb - iSeries_recal_tb;
                 unsigned long titan_usec = (titan - iSeries_recal_titan) >> 12;
                 unsigned long new_tb_ticks_per_sec   = (tb_ticks * USEC_PER_SEC)/titan_usec;
-                unsigned long new_tb_ticks_per_jiffy = (new_tb_ticks_per_sec+(HZ/2))/HZ;
+                unsigned long new_tb_ticks_per_jiffy =
+                        DIV_ROUND_CLOSEST(new_tb_ticks_per_sec, HZ);
                 long tick_diff = new_tb_ticks_per_jiffy - tb_ticks_per_jiffy;
                 char sign = '+';                
                 /* make sure tb_ticks_per_sec and tb_ticks_per_jiffy are consistent */
@@ -726,6 +727,18 @@ static int __init get_freq(char *name, int cells, unsigned long *val)
         return found;
 }
 
+/* should become __cpuinit when secondary_cpu_time_init also is */
+void start_cpu_decrementer(void)
+{
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+        /* Clear any pending timer interrupts */
+        mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
+
+        /* Enable decrementer interrupt */
+        mtspr(SPRN_TCR, TCR_DIE);
+#endif /* defined(CONFIG_BOOKE) || defined(CONFIG_40x) */
+}
+
 void __init generic_calibrate_decr(void)
 {
         ppc_tb_freq = DEFAULT_TB_FREQ;          /* hardcoded default */
@@ -745,14 +758,6 @@ void __init generic_calibrate_decr(void)
                 printk(KERN_ERR "WARNING: Estimating processor frequency "
                                 "(not found)\n");
         }
-
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
-        /* Clear any pending timer interrupts */
-        mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
-
-        /* Enable decrementer interrupt */
-        mtspr(SPRN_TCR, TCR_DIE);
-#endif
 }
 
 int update_persistent_clock(struct timespec now)
@@ -913,6 +918,11 @@ static void __init init_decrementer_clockevent(void)
 
 void secondary_cpu_time_init(void)
 {
+        /* Start the decrementer on CPUs that have manual control
+         * such as BookE
+         */
+        start_cpu_decrementer();
+
         /* FIME: Should make unrelatred change to move snapshot_timebase
          * call here ! */
         register_decrementer_clockevent(smp_processor_id());
@@ -1016,6 +1026,11 @@ void __init time_init(void)
 
         write_sequnlock_irqrestore(&xtime_lock, flags);
 
+        /* Start the decrementer on CPUs that have manual control
+         * such as BookE
+         */
+        start_cpu_decrementer();
+
         /* Register the clocksource, if we're not running on iSeries */
         if (!firmware_has_feature(FW_FEATURE_ISERIES))
                 clocksource_init();
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index ad06d5c75b15..a0abce251d0a 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -203,7 +203,12 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         } else {
                 vdso_pagelist = vdso64_pagelist;
                 vdso_pages = vdso64_pages;
-                vdso_base = VDSO64_MBASE;
+                /*
+                 * On 64bit we don't have a preferred map address. This
+                 * allows get_unmapped_area to find an area near other mmaps
+                 * and most likely share a SLB entry.
+                 */
+                vdso_base = 0;
         }
 #else
         vdso_pagelist = vdso32_pagelist;
diff --git a/arch/powerpc/kernel/vdso32/Makefile b/arch/powerpc/kernel/vdso32/Makefile
index c3d57bd01a88..b54b81688132 100644
--- a/arch/powerpc/kernel/vdso32/Makefile
+++ b/arch/powerpc/kernel/vdso32/Makefile
@@ -12,6 +12,7 @@ endif
 targets := $(obj-vdso32) vdso32.so vdso32.so.dbg
 obj-vdso32 := $(addprefix $(obj)/, $(obj-vdso32))
 
+GCOV_PROFILE := n
 
 EXTRA_CFLAGS := -shared -fno-common -fno-builtin
 EXTRA_CFLAGS += -nostdlib -Wl,-soname=linux-vdso32.so.1 \
diff --git a/arch/powerpc/kernel/vdso64/Makefile b/arch/powerpc/kernel/vdso64/Makefile
index fa7f1b8f3e50..dd0c8e936775 100644
--- a/arch/powerpc/kernel/vdso64/Makefile
+++ b/arch/powerpc/kernel/vdso64/Makefile
@@ -7,6 +7,8 @@ obj-vdso64 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o
 targets := $(obj-vdso64) vdso64.so vdso64.so.dbg
 obj-vdso64 := $(addprefix $(obj)/, $(obj-vdso64))
 
+GCOV_PROFILE := n
+
 EXTRA_CFLAGS := -shared -fno-common -fno-builtin
 EXTRA_CFLAGS += -nostdlib -Wl,-soname=linux-vdso64.so.1 \
                 $(call ld-option, -Wl$(comma)--hash-style=sysv)
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index ea4d64644d02..67b6916f0e94 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -65,7 +65,7 @@ _GLOBAL(load_up_altivec)
 1:
         /* enable use of VMX after return */
 #ifdef CONFIG_PPC32
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD             /* current task's THREAD (phys) */
         oris    r9,r9,MSR_VEC@h
 #else
         ld      r4,PACACURRENT(r13)
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 819e59f6f7c7..bc7b41edbdfc 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -601,7 +601,7 @@ static void vio_dma_iommu_unmap_sg(struct device *dev,
         vio_cmo_dealloc(viodev, alloc_size);
 }
 
-struct dma_mapping_ops vio_dma_mapping_ops = {
+struct dma_map_ops vio_dma_mapping_ops = {
         .alloc_coherent = vio_dma_iommu_alloc_coherent,
         .free_coherent  = vio_dma_iommu_free_coherent,
         .map_sg         = vio_dma_iommu_map_sg,
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 244e3658983c..58da4070723d 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -239,10 +239,6 @@ SECTIONS
         }
 #endif
 
-        . = ALIGN(PAGE_SIZE);
-        _edata  =  .;
-        PROVIDE32 (edata = .);
-
         /* The initial task and kernel stack */
 #ifdef CONFIG_PPC32
         . = ALIGN(8192);
@@ -276,6 +272,10 @@ SECTIONS
                 __nosave_end = .;
         }
 
+        . = ALIGN(PAGE_SIZE);
+        _edata  =  .;
+        PROVIDE32 (edata = .);
+
 /*
  * And finally the bss
  */
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index d0c6f841bbd1..380a78cf484d 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -56,8 +56,8 @@
 .macro KVM_HANDLER ivor_nr
 _GLOBAL(kvmppc_handler_\ivor_nr)
         /* Get pointer to vcpu and record exit number. */
-        mtspr   SPRN_SPRG0, r4
-        mfspr   r4, SPRN_SPRG1
+        mtspr   SPRN_SPRG_WSCRATCH0, r4
+        mfspr   r4, SPRN_SPRG_RVCPU
         stw     r5, VCPU_GPR(r5)(r4)
         stw     r6, VCPU_GPR(r6)(r4)
         mfctr   r5
@@ -95,7 +95,7 @@ _GLOBAL(kvmppc_handler_len)
 
 
 /* Registers:
- *  SPRG0: guest r4
+ *  SPRG_SCRATCH0: guest r4
  *  r4: vcpu pointer
  *  r5: KVM exit number
  */
@@ -181,7 +181,7 @@ _GLOBAL(kvmppc_resume_host)
         stw     r3, VCPU_LR(r4)
         mfxer   r3
         stw     r3, VCPU_XER(r4)
-        mfspr   r3, SPRN_SPRG0
+        mfspr   r3, SPRN_SPRG_RSCRATCH0
         stw     r3, VCPU_GPR(r4)(r4)
         mfspr   r3, SPRN_SRR0
         stw     r3, VCPU_PC(r4)
@@ -374,7 +374,7 @@ lightweight_exit:
         mtspr   SPRN_IVPR, r8
 
         /* Save vcpu pointer for the exception handlers. */
-        mtspr   SPRN_SPRG1, r4
+        mtspr   SPRN_SPRG_WVCPU, r4
 
         /* Can't switch the stack pointer until after IVPR is switched,
          * because host interrupt handlers would get confused. */
@@ -384,13 +384,13 @@ lightweight_exit:
         /* Host interrupt handlers may have clobbered these guest-readable
          * SPRGs, so we need to reload them here with the guest's values. */
         lwz     r3, VCPU_SPRG4(r4)
-        mtspr   SPRN_SPRG4, r3
+        mtspr   SPRN_SPRG4W, r3
         lwz     r3, VCPU_SPRG5(r4)
-        mtspr   SPRN_SPRG5, r3
+        mtspr   SPRN_SPRG5W, r3
         lwz     r3, VCPU_SPRG6(r4)
-        mtspr   SPRN_SPRG6, r3
+        mtspr   SPRN_SPRG6W, r3
         lwz     r3, VCPU_SPRG7(r4)
-        mtspr   SPRN_SPRG7, r3
+        mtspr   SPRN_SPRG7W, r3
 
 #ifdef CONFIG_KVM_EXIT_TIMING
         /* save enter time */
diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index 29954dc28942..f5e7b9ce63dd 100644
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -105,7 +105,7 @@ unsigned long __init mmu_mapin_ram(void)
 
         while (s >= LARGE_PAGE_SIZE_16M) {
                 pmd_t *pmdp;
-                unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
+                unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE;
 
                 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
                 pmd_val(*pmdp++) = val;
@@ -120,7 +120,7 @@ unsigned long __init mmu_mapin_ram(void)
 
         while (s >= LARGE_PAGE_SIZE_4M) {
                 pmd_t *pmdp;
-                unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
+                unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE;
 
                 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
                 pmd_val(*pmdp) = val;
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 3e68363405b7..6fb8fc8d2fea 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -13,6 +13,7 @@ obj-y				:= fault.o mem.o pgtable.o gup.o \
                                    pgtable_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC_MMU_NOHASH)    += mmu_context_nohash.o tlb_nohash.o \
                                    tlb_nohash_low.o
+obj-$(CONFIG_PPC_BOOK3E)        += tlb_low_$(CONFIG_WORD_SIZE)e.o
 obj-$(CONFIG_PPC64)             += mmap_64.o
 hash64-$(CONFIG_PPC_NATIVE)     := hash_native_64.o
 obj-$(CONFIG_PPC_STD_MMU_64)    += hash_utils_64.o \
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index bb3d65998e6b..dc93e95b256e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -161,7 +161,7 @@ unsigned long __init mmu_mapin_ram(void)
         unsigned long virt = PAGE_OFFSET;
         phys_addr_t phys = memstart_addr;
 
-        while (cam[tlbcam_index] && tlbcam_index < ARRAY_SIZE(cam)) {
+        while (tlbcam_index < ARRAY_SIZE(cam) && cam[tlbcam_index]) {
                 settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], PAGE_KERNEL_X, 0);
                 virt += cam[tlbcam_index];
                 phys += cam[tlbcam_index];
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 14af8cedab70..b13d58932bf6 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -40,7 +40,7 @@ mmu_hash_lock:
  * The address is in r4, and r3 contains an access flag:
  * _PAGE_RW (0x400) if a write.
  * r9 contains the SRR1 value, from which we use the MSR_PR bit.
- * SPRG3 contains the physical address of the current task's thread.
+ * SPRG_THREAD contains the physical address of the current task's thread.
  *
  * Returns to the caller if the access is illegal or there is no
  * mapping for the address.  Otherwise it places an appropriate PTE
@@ -68,7 +68,7 @@ _GLOBAL(hash_page)
         /* Get PTE (linux-style) and check access */
         lis     r0,KERNELBASE@h         /* check if kernel address */
         cmplw   0,r4,r0
-        mfspr   r8,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r8,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
         ori     r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
         lwz     r5,PGDIR(r8)            /* virt page-table root */
         blt+    112f                    /* assume user more likely */
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index c46ef2ffa3d9..90df6ffe3a43 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -57,8 +57,10 @@ unsigned int mmu_huge_psizes[MMU_PAGE_COUNT] = { }; /* initialize all to 0 */
 #define HUGEPTE_CACHE_NAME(psize)       (huge_pgtable_cache_name[psize])
 
 static const char *huge_pgtable_cache_name[MMU_PAGE_COUNT] = {
-        "unused_4K", "hugepte_cache_64K", "unused_64K_AP",
-        "hugepte_cache_1M", "hugepte_cache_16M", "hugepte_cache_16G"
+        [MMU_PAGE_64K]  = "hugepte_cache_64K",
+        [MMU_PAGE_1M]   = "hugepte_cache_1M",
+        [MMU_PAGE_16M]  = "hugepte_cache_16M",
+        [MMU_PAGE_16G]  = "hugepte_cache_16G",
 };
 
 /* Flag to mark huge PD pointers.  This means pmd_bad() and pud_bad()
@@ -700,6 +702,8 @@ static void __init set_huge_psize(int psize)
                 if (mmu_huge_psizes[psize] ||
                    mmu_psize_defs[psize].shift == PAGE_SHIFT)
                         return;
+                if (WARN_ON(HUGEPTE_CACHE_NAME(psize) == NULL))
+                        return;
                 hugetlb_add_hstate(mmu_psize_defs[psize].shift - PAGE_SHIFT);
 
                 switch (mmu_psize_defs[psize].shift) {
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 3de6a0d93824..3ef5084b90ca 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -54,8 +54,6 @@
 #endif
 #define MAX_LOW_MEM     CONFIG_LOWMEM_SIZE
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 phys_addr_t total_memory;
 phys_addr_t total_lowmem;
 
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 68a821add28d..31582329cd67 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -205,6 +205,47 @@ static int __meminit vmemmap_populated(unsigned long start, int page_size)
         return 0;
 }
 
+/* On hash-based CPUs, the vmemmap is bolted in the hash table.
+ *
+ * On Book3E CPUs, the vmemmap is currently mapped in the top half of
+ * the vmalloc space using normal page tables, though the size of
+ * pages encoded in the PTEs can be different
+ */
+
+#ifdef CONFIG_PPC_BOOK3E
+static void __meminit vmemmap_create_mapping(unsigned long start,
+                                             unsigned long page_size,
+                                             unsigned long phys)
+{
+        /* Create a PTE encoding without page size */
+        unsigned long i, flags = _PAGE_PRESENT | _PAGE_ACCESSED |
+                _PAGE_KERNEL_RW;
+
+        /* PTEs only contain page size encodings up to 32M */
+        BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].enc > 0xf);
+
+        /* Encode the size in the PTE */
+        flags |= mmu_psize_defs[mmu_vmemmap_psize].enc << 8;
+
+        /* For each PTE for that area, map things. Note that we don't
+         * increment phys because all PTEs are of the large size and
+         * thus must have the low bits clear
+         */
+        for (i = 0; i < page_size; i += PAGE_SIZE)
+                BUG_ON(map_kernel_page(start + i, phys, flags));
+}
+#else /* CONFIG_PPC_BOOK3E */
+static void __meminit vmemmap_create_mapping(unsigned long start,
+                                             unsigned long page_size,
+                                             unsigned long phys)
+{
+        int  mapped = htab_bolt_mapping(start, start + page_size, phys,
+                                        PAGE_KERNEL, mmu_vmemmap_psize,
+                                        mmu_kernel_ssize);
+        BUG_ON(mapped < 0);
+}
+#endif /* CONFIG_PPC_BOOK3E */
+
 int __meminit vmemmap_populate(struct page *start_page,
                                unsigned long nr_pages, int node)
 {
@@ -215,8 +256,11 @@ int __meminit vmemmap_populate(struct page *start_page,
         /* Align to the page size of the linear mapping. */
         start = _ALIGN_DOWN(start, page_size);
 
+        pr_debug("vmemmap_populate page %p, %ld pages, node %d\n",
+                 start_page, nr_pages, node);
+        pr_debug(" -> map %lx..%lx\n", start, end);
+
         for (; start < end; start += page_size) {
-                int mapped;
                 void *p;
 
                 if (vmemmap_populated(start, page_size))
@@ -226,13 +270,10 @@ int __meminit vmemmap_populate(struct page *start_page,
                 if (!p)
                         return -ENOMEM;
 
-                pr_debug("vmemmap %08lx allocated at %p, physical %08lx.\n",
-                        start, p, __pa(p));
+                pr_debug("      * %016lx..%016lx allocated at %p\n",
+                         start, start + page_size, p);
 
-                mapped = htab_bolt_mapping(start, start + page_size, __pa(p),
-                                           pgprot_val(PAGE_KERNEL),
-                                           mmu_vmemmap_psize, mmu_kernel_ssize);
-                BUG_ON(mapped < 0);
+                vmemmap_create_mapping(start, page_size, __pa(p));
         }
 
         return 0;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index b1a727def15b..c2f93dc470e6 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -25,10 +25,20 @@
  *     also clear mm->cpu_vm_mask bits when processes are migrated
  */
 
-#undef DEBUG
-#define DEBUG_STEAL_ONLY
-#undef DEBUG_MAP_CONSISTENCY
-/*#define DEBUG_CLAMP_LAST_CONTEXT   15 */
+#define DEBUG_MAP_CONSISTENCY
+#define DEBUG_CLAMP_LAST_CONTEXT   31
+//#define DEBUG_HARDER
+
+/* We don't use DEBUG because it tends to be compiled in always nowadays
+ * and this would generate way too much output
+ */
+#ifdef DEBUG_HARDER
+#define pr_hard(args...)        printk(KERN_DEBUG args)
+#define pr_hardcont(args...)    printk(KERN_CONT args)
+#else
+#define pr_hard(args...)        do { } while(0)
+#define pr_hardcont(args...)    do { } while(0)
+#endif
 
 #include <linux/kernel.h>
 #include <linux/mm.h>
@@ -71,7 +81,7 @@ static DEFINE_SPINLOCK(context_lock);
 static unsigned int steal_context_smp(unsigned int id)
 {
         struct mm_struct *mm;
-        unsigned int cpu, max;
+        unsigned int cpu, max, i;
 
         max = last_context - first_context;
 
@@ -89,15 +99,22 @@ static unsigned int steal_context_smp(unsigned int id)
                                 id = first_context;
                         continue;
                 }
-                pr_devel("[%d] steal context %d from mm @%p\n",
-                         smp_processor_id(), id, mm);
+                pr_hardcont(" | steal %d from 0x%p", id, mm);
 
                 /* Mark this mm has having no context anymore */
                 mm->context.id = MMU_NO_CONTEXT;
 
-                /* Mark it stale on all CPUs that used this mm */
-                for_each_cpu(cpu, mm_cpumask(mm))
-                        __set_bit(id, stale_map[cpu]);
+                /* Mark it stale on all CPUs that used this mm. For threaded
+                 * implementations, we set it on all threads on each core
+                 * represented in the mask. A future implementation will use
+                 * a core map instead but this will do for now.
+                 */
+                for_each_cpu(cpu, mm_cpumask(mm)) {
+                        for (i = cpu_first_thread_in_core(cpu);
+                             i <= cpu_last_thread_in_core(cpu); i++)
+                                __set_bit(id, stale_map[i]);
+                        cpu = i - 1;
+                }
                 return id;
         }
 
@@ -126,7 +143,7 @@ static unsigned int steal_context_up(unsigned int id)
         /* Pick up the victim mm */
         mm = context_mm[id];
 
-        pr_devel("[%d] steal context %d from mm @%p\n", cpu, id, mm);
+        pr_hardcont(" | steal %d from 0x%p", id, mm);
 
         /* Flush the TLB for that context */
         local_flush_tlb_mm(mm);
@@ -173,25 +190,20 @@ static void context_check_map(void) { }
 
 void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 {
-        unsigned int id, cpu = smp_processor_id();
+        unsigned int i, id, cpu = smp_processor_id();
         unsigned long *map;
 
         /* No lockless fast path .. yet */
         spin_lock(&context_lock);
 
-#ifndef DEBUG_STEAL_ONLY
-        pr_devel("[%d] activating context for mm @%p, active=%d, id=%d\n",
-                 cpu, next, next->context.active, next->context.id);
-#endif
+        pr_hard("[%d] activating context for mm @%p, active=%d, id=%d",
+                cpu, next, next->context.active, next->context.id);
 
 #ifdef CONFIG_SMP
         /* Mark us active and the previous one not anymore */
         next->context.active++;
         if (prev) {
-#ifndef DEBUG_STEAL_ONLY
-                pr_devel(" old context %p active was: %d\n",
-                         prev, prev->context.active);
-#endif
+                pr_hardcont(" (old=0x%p a=%d)", prev, prev->context.active);
                 WARN_ON(prev->context.active < 1);
                 prev->context.active--;
         }
@@ -201,8 +213,14 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 
         /* If we already have a valid assigned context, skip all that */
         id = next->context.id;
-        if (likely(id != MMU_NO_CONTEXT))
+        if (likely(id != MMU_NO_CONTEXT)) {
+#ifdef DEBUG_MAP_CONSISTENCY
+                if (context_mm[id] != next)
+                        pr_err("MMU: mm 0x%p has id %d but context_mm[%d] says 0x%p\n",
+                               next, id, id, context_mm[id]);
+#endif
                 goto ctxt_ok;
+        }
 
         /* We really don't have a context, let's try to acquire one */
         id = next_context;
@@ -235,11 +253,7 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
         next_context = id + 1;
         context_mm[id] = next;
         next->context.id = id;
-
-#ifndef DEBUG_STEAL_ONLY
-        pr_devel("[%d] picked up new id %d, nrf is now %d\n",
-                 cpu, id, nr_free_contexts);
-#endif
+        pr_hardcont(" | new id=%d,nrf=%d", id, nr_free_contexts);
 
         context_check_map();
  ctxt_ok:
@@ -248,15 +262,21 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
          * local TLB for it and unmark it before we use it
          */
         if (test_bit(id, stale_map[cpu])) {
-                pr_devel("[%d] flushing stale context %d for mm @%p !\n",
-                         cpu, id, next);
+                pr_hardcont(" | stale flush %d [%d..%d]",
+                            id, cpu_first_thread_in_core(cpu),
+                            cpu_last_thread_in_core(cpu));
+
                 local_flush_tlb_mm(next);
 
                 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
-                __clear_bit(id, stale_map[cpu]);
+                for (i = cpu_first_thread_in_core(cpu);
+                     i <= cpu_last_thread_in_core(cpu); i++) {
+                        __clear_bit(id, stale_map[i]);
+                }
         }
 
         /* Flick the MMU and release lock */
+        pr_hardcont(" -> %d\n", id);
         set_context(id, next->pgd);
         spin_unlock(&context_lock);
 }
@@ -266,6 +286,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
  */
 int init_new_context(struct task_struct *t, struct mm_struct *mm)
 {
+        pr_hard("initing context for mm @%p\n", mm);
+
         mm->context.id = MMU_NO_CONTEXT;
         mm->context.active = 0;
 
@@ -305,7 +327,9 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                                             unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned int)(long)hcpu;
-
+#ifdef CONFIG_HOTPLUG_CPU
+        struct task_struct *p;
+#endif
         /* We don't touch CPU 0 map, it's allocated at aboot and kept
          * around forever
          */
@@ -324,8 +348,16 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                 pr_devel("MMU: Freeing stale context map for CPU %d\n", cpu);
                 kfree(stale_map[cpu]);
                 stale_map[cpu] = NULL;
-                break;
-#endif
+
+                /* We also clear the cpu_vm_mask bits of CPUs going away */
+                read_lock(&tasklist_lock);
+                for_each_process(p) {
+                        if (p->mm)
+                                cpu_mask_clear_cpu(cpu, mm_cpumask(p->mm));
+                }
+                read_unlock(&tasklist_lock);
+        break;
+#endif /* CONFIG_HOTPLUG_CPU */
         }
         return NOTIFY_OK;
 }
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index d1f9c62dc177..d2e5321d5ea6 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -36,21 +36,37 @@ static inline void _tlbil_pid(unsigned int pid)
 {
         asm volatile ("sync; tlbia; isync" : : : "memory");
 }
+#define _tlbil_pid_noind(pid)   _tlbil_pid(pid)
+
 #else /* CONFIG_40x || CONFIG_8xx */
 extern void _tlbil_all(void);
 extern void _tlbil_pid(unsigned int pid);
+#ifdef CONFIG_PPC_BOOK3E
+extern void _tlbil_pid_noind(unsigned int pid);
+#else
+#define _tlbil_pid_noind(pid)   _tlbil_pid(pid)
+#endif
 #endif /* !(CONFIG_40x || CONFIG_8xx) */
 
 /*
  * On 8xx, we directly inline tlbie, on others, it's extern
  */
 #ifdef CONFIG_8xx
-static inline void _tlbil_va(unsigned long address, unsigned int pid)
+static inline void _tlbil_va(unsigned long address, unsigned int pid,
+                             unsigned int tsize, unsigned int ind)
 {
         asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
 }
-#else /* CONFIG_8xx */
-extern void _tlbil_va(unsigned long address, unsigned int pid);
+#elif defined(CONFIG_PPC_BOOK3E)
+extern void _tlbil_va(unsigned long address, unsigned int pid,
+                      unsigned int tsize, unsigned int ind);
+#else
+extern void __tlbil_va(unsigned long address, unsigned int pid);
+static inline void _tlbil_va(unsigned long address, unsigned int pid,
+                             unsigned int tsize, unsigned int ind)
+{
+        __tlbil_va(address, pid);
+}
 #endif /* CONIFG_8xx */
 
 /*
@@ -58,10 +74,16 @@ extern void _tlbil_va(unsigned long address, unsigned int pid);
  * implementation. When that becomes the case, this will be
  * an extern.
  */
-static inline void _tlbivax_bcast(unsigned long address, unsigned int pid)
+#ifdef CONFIG_PPC_BOOK3E
+extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
+                           unsigned int tsize, unsigned int ind);
+#else
+static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
+                                   unsigned int tsize, unsigned int ind)
 {
         BUG();
 }
+#endif
 
 #else /* CONFIG_PPC_MMU_NOHASH */
 
@@ -99,7 +121,12 @@ extern unsigned int rtas_data, rtas_size;
 struct hash_pte;
 extern struct hash_pte *Hash, *Hash_end;
 extern unsigned long Hash_size, Hash_mask;
-#endif
+
+#endif /* CONFIG_PPC32 */
+
+#ifdef CONFIG_PPC64
+extern int map_kernel_page(unsigned long ea, unsigned long pa, int flags);
+#endif /* CONFIG_PPC64 */
 
 extern unsigned long ioremap_bot;
 extern unsigned long __max_low_memory;
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 627767d6169b..83f1551ec2c9 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -30,6 +30,16 @@
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
 
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+#ifdef CONFIG_SMP
+
+/*
+ * Handle batching of page table freeing on SMP. Page tables are
+ * queued up and send to be freed later by RCU in order to avoid
+ * freeing a page table page that is being walked without locks
+ */
+
 static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
 static unsigned long pte_freelist_forced_free;
 
@@ -116,27 +126,7 @@ void pte_free_finish(void)
         *batchp = NULL;
 }
 
-/*
- * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
- */
-static pte_t do_dcache_icache_coherency(pte_t pte)
-{
-        unsigned long pfn = pte_pfn(pte);
-        struct page *page;
-
-        if (unlikely(!pfn_valid(pfn)))
-                return pte;
-        page = pfn_to_page(pfn);
-
-        if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
-                pr_devel("do_dcache_icache_coherency... flushing\n");
-                flush_dcache_icache_page(page);
-                set_bit(PG_arch_1, &page->flags);
-        }
-        else
-                pr_devel("do_dcache_icache_coherency... already clean\n");
-        return __pte(pte_val(pte) | _PAGE_HWEXEC);
-}
+#endif /* CONFIG_SMP */
 
 static inline int is_exec_fault(void)
 {
@@ -145,49 +135,139 @@ static inline int is_exec_fault(void)
 
 /* We only try to do i/d cache coherency on stuff that looks like
  * reasonably "normal" PTEs. We currently require a PTE to be present
- * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE
+ * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE. We also only do that
+ * on userspace PTEs
  */
 static inline int pte_looks_normal(pte_t pte)
 {
         return (pte_val(pte) &
-                (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE)) ==
-                (_PAGE_PRESENT);
+            (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) ==
+            (_PAGE_PRESENT | _PAGE_USER);
 }
 
-#if defined(CONFIG_PPC_STD_MMU)
+struct page * maybe_pte_to_page(pte_t pte)
+{
+        unsigned long pfn = pte_pfn(pte);
+        struct page *page;
+
+        if (unlikely(!pfn_valid(pfn)))
+                return NULL;
+        page = pfn_to_page(pfn);
+        if (PageReserved(page))
+                return NULL;
+        return page;
+}
+
+#if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0
+
 /* Server-style MMU handles coherency when hashing if HW exec permission
- * is supposed per page (currently 64-bit only). Else, we always flush
- * valid PTEs in set_pte.
+ * is supposed per page (currently 64-bit only). If not, then, we always
+ * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
+ * support falls into the same category.
  */
-static inline int pte_need_exec_flush(pte_t pte, int set_pte)
+
+static pte_t set_pte_filter(pte_t pte)
 {
-        return set_pte && pte_looks_normal(pte) &&
-                !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
-                  cpu_has_feature(CPU_FTR_NOEXECUTE));
+        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
+        if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
+                                       cpu_has_feature(CPU_FTR_NOEXECUTE))) {
+                struct page *pg = maybe_pte_to_page(pte);
+                if (!pg)
+                        return pte;
+                if (!test_bit(PG_arch_1, &pg->flags)) {
+                        flush_dcache_icache_page(pg);
+                        set_bit(PG_arch_1, &pg->flags);
+                }
+        }
+        return pte;
 }
-#elif _PAGE_HWEXEC == 0
-/* Embedded type MMU without HW exec support (8xx only so far), we flush
- * the cache for any present PTE
- */
-static inline int pte_need_exec_flush(pte_t pte, int set_pte)
+
+static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
+                                     int dirty)
 {
-        return set_pte && pte_looks_normal(pte);
+        return pte;
 }
-#else
-/* Other embedded CPUs with HW exec support per-page, we flush on exec
- * fault if HWEXEC is not set
+
+#else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */
+
+/* Embedded type MMU with HW exec support. This is a bit more complicated
+ * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
+ * instead we "filter out" the exec permission for non clean pages.
  */
-static inline int pte_need_exec_flush(pte_t pte, int set_pte)
+static pte_t set_pte_filter(pte_t pte)
 {
-        return pte_looks_normal(pte) && is_exec_fault() &&
-                !(pte_val(pte) & _PAGE_HWEXEC);
+        struct page *pg;
+
+        /* No exec permission in the first place, move on */
+        if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte))
+                return pte;
+
+        /* If you set _PAGE_EXEC on weird pages you're on your own */
+        pg = maybe_pte_to_page(pte);
+        if (unlikely(!pg))
+                return pte;
+
+        /* If the page clean, we move on */
+        if (test_bit(PG_arch_1, &pg->flags))
+                return pte;
+
+        /* If it's an exec fault, we flush the cache and make it clean */
+        if (is_exec_fault()) {
+                flush_dcache_icache_page(pg);
+                set_bit(PG_arch_1, &pg->flags);
+                return pte;
+        }
+
+        /* Else, we filter out _PAGE_EXEC */
+        return __pte(pte_val(pte) & ~_PAGE_EXEC);
 }
-#endif
+
+static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
+                                     int dirty)
+{
+        struct page *pg;
+
+        /* So here, we only care about exec faults, as we use them
+         * to recover lost _PAGE_EXEC and perform I$/D$ coherency
+         * if necessary. Also if _PAGE_EXEC is already set, same deal,
+         * we just bail out
+         */
+        if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault())
+                return pte;
+
+#ifdef CONFIG_DEBUG_VM
+        /* So this is an exec fault, _PAGE_EXEC is not set. If it was
+         * an error we would have bailed out earlier in do_page_fault()
+         * but let's make sure of it
+         */
+        if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
+                return pte;
+#endif /* CONFIG_DEBUG_VM */
+
+        /* If you set _PAGE_EXEC on weird pages you're on your own */
+        pg = maybe_pte_to_page(pte);
+        if (unlikely(!pg))
+                goto bail;
+
+        /* If the page is already clean, we move on */
+        if (test_bit(PG_arch_1, &pg->flags))
+                goto bail;
+
+        /* Clean the page and set PG_arch_1 */
+        flush_dcache_icache_page(pg);
+        set_bit(PG_arch_1, &pg->flags);
+
+ bail:
+        return __pte(pte_val(pte) | _PAGE_EXEC);
+}
+
+#endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */
 
 /*
  * set_pte stores a linux PTE into the linux page table.
  */
-void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
+                pte_t pte)
 {
 #ifdef CONFIG_DEBUG_VM
         WARN_ON(pte_present(*ptep));
@@ -196,9 +276,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte
          * this context might not have been activated yet when this
          * is called.
          */
-        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
-        if (pte_need_exec_flush(pte, 1))
-                pte = do_dcache_icache_coherency(pte);
+        pte = set_pte_filter(pte);
 
         /* Perform the setting of the PTE */
         __set_pte_at(mm, addr, ptep, pte, 0);
@@ -215,8 +293,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
                           pte_t *ptep, pte_t entry, int dirty)
 {
         int changed;
-        if (!dirty && pte_need_exec_flush(entry, 0))
-                entry = do_dcache_icache_coherency(entry);
+        entry = set_access_flags_filter(entry, vma, dirty);
         changed = !pte_same(*(ptep), entry);
         if (changed) {
                 if (!(vma->vm_flags & VM_HUGETLB))
@@ -242,7 +319,7 @@ void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
         BUG_ON(pud_none(*pud));
         pmd = pmd_offset(pud, addr);
         BUG_ON(!pmd_present(*pmd));
-        BUG_ON(!spin_is_locked(pte_lockptr(mm, pmd)));
+        assert_spin_locked(pte_lockptr(mm, pmd));
 }
 #endif /* CONFIG_DEBUG_VM */
 
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 5422169626ba..cb96cb2e17cc 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -142,7 +142,7 @@ ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags)
                 flags |= _PAGE_DIRTY | _PAGE_HWWRITE;
 
         /* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */
-        flags &= ~(_PAGE_USER | _PAGE_EXEC | _PAGE_HWEXEC);
+        flags &= ~(_PAGE_USER | _PAGE_EXEC);
 
         return __ioremap_caller(addr, size, flags, __builtin_return_address(0));
 }
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index bfa7db6b2fd5..853d5565eed5 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -33,6 +33,8 @@
 #include <linux/stddef.h>
 #include <linux/vmalloc.h>
 #include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/lmb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/page.h>
@@ -55,19 +57,36 @@
 
 unsigned long ioremap_bot = IOREMAP_BASE;
 
+
+#ifdef CONFIG_PPC_MMU_NOHASH
+static void *early_alloc_pgtable(unsigned long size)
+{
+        void *pt;
+
+        if (init_bootmem_done)
+                pt = __alloc_bootmem(size, size, __pa(MAX_DMA_ADDRESS));
+        else
+                pt = __va(lmb_alloc_base(size, size,
+                                         __pa(MAX_DMA_ADDRESS)));
+        memset(pt, 0, size);
+
+        return pt;
+}
+#endif /* CONFIG_PPC_MMU_NOHASH */
+
 /*
- * map_io_page currently only called by __ioremap
- * map_io_page adds an entry to the ioremap page table
+ * map_kernel_page currently only called by __ioremap
+ * map_kernel_page adds an entry to the ioremap page table
  * and adds an entry to the HPT, possibly bolting it
  */
-static int map_io_page(unsigned long ea, unsigned long pa, int flags)
+int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
 {
         pgd_t *pgdp;
         pud_t *pudp;
         pmd_t *pmdp;
         pte_t *ptep;
 
-        if (mem_init_done) {
+        if (slab_is_available()) {
                 pgdp = pgd_offset_k(ea);
                 pudp = pud_alloc(&init_mm, pgdp, ea);
                 if (!pudp)
@@ -81,6 +100,35 @@ static int map_io_page(unsigned long ea, unsigned long pa, int flags)
                 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
                                                           __pgprot(flags)));
         } else {
+#ifdef CONFIG_PPC_MMU_NOHASH
+                /* Warning ! This will blow up if bootmem is not initialized
+                 * which our ppc64 code is keen to do that, we'll need to
+                 * fix it and/or be more careful
+                 */
+                pgdp = pgd_offset_k(ea);
+#ifdef PUD_TABLE_SIZE
+                if (pgd_none(*pgdp)) {
+                        pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
+                        BUG_ON(pudp == NULL);
+                        pgd_populate(&init_mm, pgdp, pudp);
+                }
+#endif /* PUD_TABLE_SIZE */
+                pudp = pud_offset(pgdp, ea);
+                if (pud_none(*pudp)) {
+                        pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
+                        BUG_ON(pmdp == NULL);
+                        pud_populate(&init_mm, pudp, pmdp);
+                }
+                pmdp = pmd_offset(pudp, ea);
+                if (!pmd_present(*pmdp)) {
+                        ptep = early_alloc_pgtable(PAGE_SIZE);
+                        BUG_ON(ptep == NULL);
+                        pmd_populate_kernel(&init_mm, pmdp, ptep);
+                }
+                ptep = pte_offset_kernel(pmdp, ea);
+                set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
+                                                          __pgprot(flags)));
+#else /* CONFIG_PPC_MMU_NOHASH */
                 /*
                  * If the mm subsystem is not fully up, we cannot create a
                  * linux page table entry for this mapping.  Simply bolt an
@@ -93,6 +141,7 @@ static int map_io_page(unsigned long ea, unsigned long pa, int flags)
                                "memory at %016lx !\n", pa);
                         return -ENOMEM;
                 }
+#endif /* !CONFIG_PPC_MMU_NOHASH */
         }
         return 0;
 }
@@ -124,7 +173,7 @@ void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size,
         WARN_ON(size & ~PAGE_MASK);
 
         for (i = 0; i < size; i += PAGE_SIZE)
-                if (map_io_page((unsigned long)ea+i, pa+i, flags))
+                if (map_kernel_page((unsigned long)ea+i, pa+i, flags))
                         return NULL;
 
         return (void __iomem *)ea;
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index a685652effeb..1d98ecc8eecd 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -191,7 +191,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
         unsigned long slbie_data = 0;
         unsigned long pc = KSTK_EIP(tsk);
         unsigned long stack = KSTK_ESP(tsk);
-        unsigned long unmapped_base;
+        unsigned long exec_base;
 
         /*
          * We need interrupts hard-disabled here, not just soft-disabled,
@@ -227,42 +227,44 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 
         /*
          * preload some userspace segments into the SLB.
+         * Almost all 32 and 64bit PowerPC executables are linked at
+         * 0x10000000 so it makes sense to preload this segment.
          */
-        if (test_tsk_thread_flag(tsk, TIF_32BIT))
-                unmapped_base = TASK_UNMAPPED_BASE_USER32;
-        else
-                unmapped_base = TASK_UNMAPPED_BASE_USER64;
+        exec_base = 0x10000000;
 
-        if (is_kernel_addr(pc))
-                return;
-        slb_allocate(pc);
-
-        if (esids_match(pc,stack))
+        if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
+            is_kernel_addr(exec_base))
                 return;
 
-        if (is_kernel_addr(stack))
-                return;
-        slb_allocate(stack);
+        slb_allocate(pc);
 
-        if (esids_match(pc,unmapped_base) || esids_match(stack,unmapped_base))
-                return;
+        if (!esids_match(pc, stack))
+                slb_allocate(stack);
 
-        if (is_kernel_addr(unmapped_base))
-                return;
-        slb_allocate(unmapped_base);
+        if (!esids_match(pc, exec_base) &&
+            !esids_match(stack, exec_base))
+                slb_allocate(exec_base);
 }
 
 static inline void patch_slb_encoding(unsigned int *insn_addr,
                                       unsigned int immed)
 {
-        /* Assume the instruction had a "0" immediate value, just
-         * "or" in the new value
-         */
-        *insn_addr |= immed;
+        *insn_addr = (*insn_addr & 0xffff0000) | immed;
         flush_icache_range((unsigned long)insn_addr, 4+
                            (unsigned long)insn_addr);
 }
 
+void slb_set_size(u16 size)
+{
+        extern unsigned int *slb_compare_rr_to_size;
+
+        if (mmu_slb_size == size)
+                return;
+
+        mmu_slb_size = size;
+        patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
+}
+
 void slb_initialize(void)
 {
         unsigned long linear_llp, vmalloc_llp, io_llp;
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 65190587a365..8aaa8b7eb324 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -71,6 +71,9 @@ void tlb_flush(struct mmu_gather *tlb)
                  */
                 _tlbia();
         }
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
 }
 
 /*
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 937eb90677d9..2b2f35f6985e 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -33,11 +33,6 @@
 
 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 
-/* This is declared as we are using the more or less generic
- * arch/powerpc/include/asm/tlb.h file -- tgall
- */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * A linux PTE was changed and the corresponding hash table entry
  * neesd to be flushed. This function will either perform the flush
@@ -154,6 +149,21 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
         batch->index = 0;
 }
 
+void tlb_flush(struct mmu_gather *tlb)
+{
+        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
+
+        /* If there's a TLB batch pending, then we must flush it because the
+         * pages are going to be freed and we really don't want to have a CPU
+         * access a freed page because it has a stale TLB
+         */
+        if (tlbbatch->index)
+                __flush_tlb_pending(tlbbatch);
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
+}
+
 /**
  * __flush_hash_table_range - Flush all HPTEs for a given address range
  *                            from the hash table (and the TLB). But keeps
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
new file mode 100644
index 000000000000..ef1cccf71173
--- /dev/null
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -0,0 +1,770 @@
+/*
+ *  Low leve TLB miss handlers for Book3E
+ *
+ *  Copyright (C) 2008-2009
+ *      Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cputable.h>
+#include <asm/pgtable.h>
+#include <asm/reg.h>
+#include <asm/exception-64e.h>
+#include <asm/ppc-opcode.h>
+
+#ifdef CONFIG_PPC_64K_PAGES
+#define VPTE_PMD_SHIFT  (PTE_INDEX_SIZE+1)
+#else
+#define VPTE_PMD_SHIFT  (PTE_INDEX_SIZE)
+#endif
+#define VPTE_PUD_SHIFT  (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
+#define VPTE_PGD_SHIFT  (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
+#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
+
+
+/**********************************************************************
+ *                                                                    *
+ * TLB miss handling for Book3E with TLB reservation and HES support  *
+ *                                                                    *
+ **********************************************************************/
+
+
+/* Data TLB miss */
+        START_EXCEPTION(data_tlb_miss)
+        TLB_MISS_PROLOG
+
+        /* Now we handle the fault proper. We only save DEAR in normal
+         * fault case since that's the only interesting values here.
+         * We could probably also optimize by not saving SRR0/1 in the
+         * linear mapping case but I'll leave that for later
+         */
+        mfspr   r14,SPRN_ESR
+        mfspr   r16,SPRN_DEAR           /* get faulting address */
+        srdi    r15,r16,60              /* get region */
+        cmpldi  cr0,r15,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* The page tables are mapped virtually linear. At this point, though,
+         * we don't know whether we are trying to fault in a first level
+         * virtual address or a virtual page table address. We can get that
+         * from bit 0x1 of the region ID which we have set for a page table
+         */
+        andi.   r10,r15,0x1
+        bne-    virt_page_table_tlb_miss
+
+        std     r14,EX_TLB_ESR(r12);    /* save ESR */
+        std     r16,EX_TLB_DEAR(r12);   /* save DEAR */
+
+         /* We need _PAGE_PRESENT and  _PAGE_ACCESSED set */
+        li      r11,_PAGE_PRESENT
+        oris    r11,r11,_PAGE_ACCESSED@h
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r15,0               /* Check for user region */
+
+        /* We pre-test some combination of permissions to avoid double
+         * faults:
+         *
+         * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
+         * ESR_ST   is 0x00800000
+         * _PAGE_BAP_SW is 0x00000010
+         * So the shift is >> 19. This tests for supervisor writeability.
+         * If the page happens to be supervisor writeable and not user
+         * writeable, we will take a new fault later, but that should be
+         * a rare enough case.
+         *
+         * We also move ESR_ST in _PAGE_DIRTY position
+         * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
+         *
+         * MAS1 is preset for all we need except for TID that needs to
+         * be cleared for kernel translations
+         */
+        rlwimi  r11,r14,32-19,27,27
+        rlwimi  r11,r14,32-16,19,19
+        beq     normal_tlb_miss
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r15,8               /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1          /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        beq+    normal_tlb_miss
+
+        /* We got a crappy address, just fault with whatever DEAR and ESR
+         * are here
+         */
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+/* Instruction TLB miss */
+        START_EXCEPTION(instruction_tlb_miss)
+        TLB_MISS_PROLOG
+
+        /* If we take a recursive fault, the second level handler may need
+         * to know whether we are handling a data or instruction fault in
+         * order to get to the right store fault handler. We provide that
+         * info by writing a crazy value in ESR in our exception frame
+         */
+        li      r14,-1  /* store to exception frame is done later */
+
+        /* Now we handle the fault proper. We only save DEAR in the non
+         * linear mapping case since we know the linear mapping case will
+         * not re-enter. We could indeed optimize and also not save SRR0/1
+         * in the linear mapping case but I'll leave that for later
+         *
+         * Faulting address is SRR0 which is already in r16
+         */
+        srdi    r15,r16,60              /* get region */
+        cmpldi  cr0,r15,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        li      r11,_PAGE_PRESENT|_PAGE_EXEC    /* Base perm */
+        oris    r11,r11,_PAGE_ACCESSED@h
+
+        cmpldi  cr0,r15,0                       /* Check for user region */
+        std     r14,EX_TLB_ESR(r12)             /* write crazy -1 to frame */
+        beq     normal_tlb_miss
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r15,8                       /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        beq+    normal_tlb_miss
+
+        /* We got a crappy address, just fault */
+        TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+/*
+ * This is the guts of the first-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = faulting address
+ * r15 = region ID
+ * r14 = crap (free to use)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = PTE permission mask
+ * r10 = crap (free to use)
+ */
+normal_tlb_miss:
+        /* So we first construct the page table address. We do that by
+         * shifting the bottom of the address (not the region ID) by
+         * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
+         * or'ing the fourth high bit.
+         *
+         * NOTE: For 64K pages, we do things slightly differently in
+         * order to handle the weird page table format used by linux
+         */
+        ori     r10,r15,0x1
+#ifdef CONFIG_PPC_64K_PAGES
+        /* For the top bits, 16 bytes per PTE */
+        rldicl  r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
+        /* Now create the bottom bits as 0 in position 0x8000 and
+         * the rest calculated for 8 bytes per PTE
+         */
+        rldicl  r15,r16,64-(PAGE_SHIFT-3),64-15
+        /* Insert the bottom bits in */
+        rlwimi  r14,r15,0,16,31
+#else
+        rldicl  r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
+#endif
+        sldi    r15,r10,60
+        clrrdi  r14,r14,3
+        or      r10,r15,r14
+
+BEGIN_MMU_FTR_SECTION
+        /* Set the TLB reservation and seach for existing entry. Then load
+         * the entry.
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        ld      r14,0(r10)
+        beq     normal_tlb_miss_done
+MMU_FTR_SECTION_ELSE
+        ld      r14,0(r10)
+ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
+
+finish_normal_tlb_miss:
+        /* Check if required permissions are met */
+        andc.   r15,r11,r14
+        bne-    normal_tlb_miss_access_fault
+
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE need change if !base page size, not
+         *                 yet implemented for now
+         * MAS 2   :    Defaults not useful, need to be redone
+         * MAS 3+7 :    Needs to be done
+         *
+         * TODO: mix up code below for better scheduling
+         */
+        clrrdi  r11,r16,12              /* Clear low crap in EA */
+        rlwimi  r11,r14,32-19,27,31     /* Insert WIMGE */
+        mtspr   SPRN_MAS2,r11
+
+        /* Check page size, if not standard, update MAS1 */
+        rldicl  r11,r14,64-8,64-8
+#ifdef CONFIG_PPC_64K_PAGES
+        cmpldi  cr0,r11,BOOK3E_PAGESZ_64K
+#else
+        cmpldi  cr0,r11,BOOK3E_PAGESZ_4K
+#endif
+        beq-    1f
+        mfspr   r11,SPRN_MAS1
+        rlwimi  r11,r14,31,21,24
+        rlwinm  r11,r11,0,21,19
+        mtspr   SPRN_MAS1,r11
+1:
+        /* Move RPN in position */
+        rldicr  r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
+        clrldi  r15,r11,12              /* Clear crap at the top */
+        rlwimi  r15,r14,32-8,22,25      /* Move in U bits */
+        rlwimi  r15,r14,32-2,26,31      /* Move in BAP bits */
+
+        /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
+        andi.   r11,r14,_PAGE_DIRTY
+        bne     1f
+        li      r11,MAS3_SW|MAS3_UW
+        andc    r15,r15,r11
+1:
+BEGIN_MMU_FTR_SECTION
+        srdi    r16,r15,32
+        mtspr   SPRN_MAS3,r15
+        mtspr   SPRN_MAS7,r16
+MMU_FTR_SECTION_ELSE
+        mtspr   SPRN_MAS7_MAS3,r15
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
+
+        tlbwe
+
+normal_tlb_miss_done:
+        /* We don't bother with restoring DEAR or ESR since we know we are
+         * level 0 and just going back to userland. They are only needed
+         * if you are going to take an access fault
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+normal_tlb_miss_access_fault:
+        /* We need to check if it was an instruction miss */
+        andi.   r10,r11,_PAGE_EXEC
+        bne     1f
+        ld      r14,EX_TLB_DEAR(r12)
+        ld      r15,EX_TLB_ESR(r12)
+        mtspr   SPRN_DEAR,r14
+        mtspr   SPRN_ESR,r15
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+
+/*
+ * This is the guts of the second-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = virtual page table faulting address
+ * r15 = region (top 4 bits of address)
+ * r14 = crap (free to use)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * Note that this should only ever be called as a second level handler
+ * with the current scheme when using SW load.
+ * That means we can always get the original fault DEAR at
+ * EX_TLB_DEAR-EX_TLB_SIZE(r12)
+ *
+ * It can be re-entered by the linear mapping miss handler. However, to
+ * avoid too much complication, it will restart the whole fault at level
+ * 0 so we don't care too much about clobbers
+ *
+ * XXX That code was written back when we couldn't clobber r14. We can now,
+ * so we could probably optimize things a bit
+ */
+virt_page_table_tlb_miss:
+        /* Are we hitting a kernel page table ? */
+        andi.   r10,r15,0x8
+
+        /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
+         * and we happen to have the swapper_pg_dir at offset 8 from the user
+         * pgdir in the PACA :-).
+         */
+        add     r11,r10,r13
+
+        /* If kernel, we need to clear MAS1 TID */
+        beq     1f
+        /* XXX replace the RMW cycles with immediate loads + writes */
+        mfspr   r10,SPRN_MAS1
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+1:
+BEGIN_MMU_FTR_SECTION
+        /* Search if we already have a TLB entry for that virtual address, and
+         * if we do, bail out.
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     virt_page_table_tlb_miss_done
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
+
+        /* Now, we need to walk the page tables. First check if we are in
+         * range.
+         */
+        rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
+        bne-    virt_page_table_tlb_miss_fault
+
+        /* Get the PGD pointer */
+        ld      r15,PACAPGD(r11)
+        cmpldi  cr0,r15,0
+        beq-    virt_page_table_tlb_miss_fault
+
+        /* Get to PGD entry */
+        rldicl  r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+
+#ifndef CONFIG_PPC_64K_PAGES
+        /* Get to PUD entry */
+        rldicl  r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+#endif /* CONFIG_PPC_64K_PAGES */
+
+        /* Get to PMD entry */
+        rldicl  r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+
+        /* Ok, we're all right, we can now create a kernel translation for
+         * a 4K or 64K page from r16 -> r15.
+         */
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE for now is base page size always
+         * MAS 2   :    Use defaults
+         * MAS 3+7 :    Needs to be done
+         *
+         * So we only do MAS 2 and 3 for now...
+         */
+        clrldi  r11,r15,4               /* remove region ID from RPN */
+        ori     r10,r11,1               /* Or-in SR */
+
+BEGIN_MMU_FTR_SECTION
+        srdi    r16,r10,32
+        mtspr   SPRN_MAS3,r10
+        mtspr   SPRN_MAS7,r16
+MMU_FTR_SECTION_ELSE
+        mtspr   SPRN_MAS7_MAS3,r10
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
+
+        tlbwe
+
+BEGIN_MMU_FTR_SECTION
+virt_page_table_tlb_miss_done:
+
+        /* We have overriden MAS2:EPN but currently our primary TLB miss
+         * handler will always restore it so that should not be an issue,
+         * if we ever optimize the primary handler to not write MAS2 on
+         * some cases, we'll have to restore MAS2:EPN here based on the
+         * original fault's DEAR. If we do that we have to modify the
+         * ITLB miss handler to also store SRR0 in the exception frame
+         * as DEAR.
+         *
+         * However, one nasty thing we did is we cleared the reservation
+         * (well, potentially we did). We do a trick here thus if we
+         * are not a level 0 exception (we interrupted the TLB miss) we
+         * offset the return address by -4 in order to replay the tlbsrx
+         * instruction there
+         */
+        subf    r10,r13,r12
+        cmpldi  cr0,r10,PACA_EXTLB+EX_TLB_SIZE
+        bne-    1f
+        ld      r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
+        addi    r10,r11,-4
+        std     r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
+1:
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
+        /* Return to caller, normal case */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+virt_page_table_tlb_miss_fault:
+        /* If we fault here, things are a little bit tricky. We need to call
+         * either data or instruction store fault, and we need to retreive
+         * the original fault address and ESR (for data).
+         *
+         * The thing is, we know that in normal circumstances, this is
+         * always called as a second level tlb miss for SW load or as a first
+         * level TLB miss for HW load, so we should be able to peek at the
+         * relevant informations in the first exception frame in the PACA.
+         *
+         * However, we do need to double check that, because we may just hit
+         * a stray kernel pointer or a userland attack trying to hit those
+         * areas. If that is the case, we do a data fault. (We can't get here
+         * from an instruction tlb miss anyway).
+         *
+         * Note also that when going to a fault, we must unwind the previous
+         * level as well. Since we are doing that, we don't need to clear or
+         * restore the TLB reservation neither.
+         */
+        subf    r10,r13,r12
+        cmpldi  cr0,r10,PACA_EXTLB+EX_TLB_SIZE
+        bne-    virt_page_table_tlb_miss_whacko_fault
+
+        /* We dig the original DEAR and ESR from slot 0 */
+        ld      r15,EX_TLB_DEAR+PACA_EXTLB(r13)
+        ld      r16,EX_TLB_ESR+PACA_EXTLB(r13)
+
+        /* We check for the "special" ESR value for instruction faults */
+        cmpdi   cr0,r16,-1
+        beq     1f
+        mtspr   SPRN_DEAR,r15
+        mtspr   SPRN_ESR,r16
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+virt_page_table_tlb_miss_whacko_fault:
+        /* The linear fault will restart everything so ESR and DEAR will
+         * not have been clobbered, let's just fault with what we have
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+
+/**************************************************************
+ *                                                            *
+ * TLB miss handling for Book3E with hw page table support    *
+ *                                                            *
+ **************************************************************/
+
+
+/* Data TLB miss */
+        START_EXCEPTION(data_tlb_miss_htw)
+        TLB_MISS_PROLOG
+
+        /* Now we handle the fault proper. We only save DEAR in normal
+         * fault case since that's the only interesting values here.
+         * We could probably also optimize by not saving SRR0/1 in the
+         * linear mapping case but I'll leave that for later
+         */
+        mfspr   r14,SPRN_ESR
+        mfspr   r16,SPRN_DEAR           /* get faulting address */
+        srdi    r11,r16,60              /* get region */
+        cmpldi  cr0,r11,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r11,0               /* Check for user region */
+        ld      r15,PACAPGD(r13)        /* Load user pgdir */
+        beq     htw_tlb_miss
+
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r11,8               /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1          /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        ld      r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
+        beq+    htw_tlb_miss
+
+        /* We got a crappy address, just fault with whatever DEAR and ESR
+         * are here
+         */
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+/* Instruction TLB miss */
+        START_EXCEPTION(instruction_tlb_miss_htw)
+        TLB_MISS_PROLOG
+
+        /* If we take a recursive fault, the second level handler may need
+         * to know whether we are handling a data or instruction fault in
+         * order to get to the right store fault handler. We provide that
+         * info by keeping a crazy value for ESR in r14
+         */
+        li      r14,-1  /* store to exception frame is done later */
+
+        /* Now we handle the fault proper. We only save DEAR in the non
+         * linear mapping case since we know the linear mapping case will
+         * not re-enter. We could indeed optimize and also not save SRR0/1
+         * in the linear mapping case but I'll leave that for later
+         *
+         * Faulting address is SRR0 which is already in r16
+         */
+        srdi    r11,r16,60              /* get region */
+        cmpldi  cr0,r11,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r11,0                       /* Check for user region */
+        ld      r15,PACAPGD(r13)                /* Load user pgdir */
+        beq     htw_tlb_miss
+
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r11,8                       /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        ld      r15,PACA_KERNELPGD(r13)         /* Load kernel pgdir */
+        beq+    htw_tlb_miss
+
+        /* We got a crappy address, just fault */
+        TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+
+/*
+ * This is the guts of the second-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = virtual page table faulting address
+ * r15 = PGD pointer
+ * r14 = ESR
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * It can be re-entered by the linear mapping miss handler. However, to
+ * avoid too much complication, it will save/restore things for us
+ */
+htw_tlb_miss:
+        /* Search if we already have a TLB entry for that virtual address, and
+         * if we do, bail out.
+         *
+         * MAS1:IND should be already set based on MAS4
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     htw_tlb_miss_done
+
+        /* Now, we need to walk the page tables. First check if we are in
+         * range.
+         */
+        rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
+        bne-    htw_tlb_miss_fault
+
+        /* Get the PGD pointer */
+        cmpldi  cr0,r15,0
+        beq-    htw_tlb_miss_fault
+
+        /* Get to PGD entry */
+        rldicl  r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+
+#ifndef CONFIG_PPC_64K_PAGES
+        /* Get to PUD entry */
+        rldicl  r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+#endif /* CONFIG_PPC_64K_PAGES */
+
+        /* Get to PMD entry */
+        rldicl  r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+
+        /* Ok, we're all right, we can now create an indirect entry for
+         * a 1M or 256M page.
+         *
+         * The last trick is now that because we use "half" pages for
+         * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
+         * for an added LSB bit to the RPN. For 64K pages, there is no
+         * problem as we already use 32K arrays (half PTE pages), but for
+         * 4K page we need to extract a bit from the virtual address and
+         * insert it into the "PA52" bit of the RPN.
+         */
+#ifndef CONFIG_PPC_64K_PAGES
+        rlwimi  r15,r16,32-9,20,20
+#endif
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE for now is base ind page size always
+         * MAS 2   :    Use defaults
+         * MAS 3+7 :    Needs to be done
+         */
+#ifdef CONFIG_PPC_64K_PAGES
+        ori     r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
+#else
+        ori     r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
+#endif
+
+BEGIN_MMU_FTR_SECTION
+        srdi    r16,r10,32
+        mtspr   SPRN_MAS3,r10
+        mtspr   SPRN_MAS7,r16
+MMU_FTR_SECTION_ELSE
+        mtspr   SPRN_MAS7_MAS3,r10
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
+
+        tlbwe
+
+htw_tlb_miss_done:
+        /* We don't bother with restoring DEAR or ESR since we know we are
+         * level 0 and just going back to userland. They are only needed
+         * if you are going to take an access fault
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+htw_tlb_miss_fault:
+        /* We need to check if it was an instruction miss. We know this
+         * though because r14 would contain -1
+         */
+        cmpdi   cr0,r14,-1
+        beq     1f
+        mtspr   SPRN_DEAR,r16
+        mtspr   SPRN_ESR,r14
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+/*
+ * This is the guts of "any" level TLB miss handler for kernel linear
+ * mapping misses. We are entered with:
+ *
+ *
+ * r16 = faulting address
+ * r15 = crap (free to use)
+ * r14 = ESR (data) or -1 (instruction)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * In addition we know that we will not re-enter, so in theory, we could
+ * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
+ *
+ * We also need to be careful about MAS registers here & TLB reservation,
+ * as we know we'll have clobbered them if we interrupt the main TLB miss
+ * handlers in which case we probably want to do a full restart at level
+ * 0 rather than saving / restoring the MAS.
+ *
+ * Note: If we care about performance of that core, we can easily shuffle
+ *       a few things around
+ */
+tlb_load_linear:
+        /* For now, we assume the linear mapping is contiguous and stops at
+         * linear_map_top. We also assume the size is a multiple of 1G, thus
+         * we only use 1G pages for now. That might have to be changed in a
+         * final implementation, especially when dealing with hypervisors
+         */
+        ld      r11,PACATOC(r13)
+        ld      r11,linear_map_top@got(r11)
+        ld      r10,0(r11)
+        cmpld   cr0,r10,r16
+        bge     tlb_load_linear_fault
+
+        /* MAS1 need whole new setup. */
+        li      r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
+        oris    r15,r15,MAS1_VALID@h    /* MAS1 needs V and TSIZE */
+        mtspr   SPRN_MAS1,r15
+
+        /* Already somebody there ? */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     tlb_load_linear_done
+
+        /* Now we build the remaining MAS. MAS0 and 2 should be fine
+         * with their defaults, which leaves us with MAS 3 and 7. The
+         * mapping is linear, so we just take the address, clear the
+         * region bits, and or in the permission bits which are currently
+         * hard wired
+         */
+        clrrdi  r10,r16,30              /* 1G page index */
+        clrldi  r10,r10,4               /* clear region bits */
+        ori     r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
+
+BEGIN_MMU_FTR_SECTION
+        srdi    r16,r10,32
+        mtspr   SPRN_MAS3,r10
+        mtspr   SPRN_MAS7,r16
+MMU_FTR_SECTION_ELSE
+        mtspr   SPRN_MAS7_MAS3,r10
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
+
+        tlbwe
+
+tlb_load_linear_done:
+        /* We use the "error" epilog for success as we do want to
+         * restore to the initial faulting context, whatever it was.
+         * We do that because we can't resume a fault within a TLB
+         * miss handler, due to MAS and TLB reservation being clobbered.
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
+        TLB_MISS_EPILOG_ERROR
+        rfi
+
+tlb_load_linear_fault:
+        /* We keep the DEAR and ESR around, this shouldn't have happened */
+        cmpdi   cr0,r14,-1
+        beq     1f
+        TLB_MISS_EPILOG_ERROR_SPECIAL
+        b       exc_data_storage_book3e
+1:      TLB_MISS_EPILOG_ERROR_SPECIAL
+        b       exc_instruction_storage_book3e
+
+
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+.tlb_stat_inc:
+1:      ldarx   r8,0,r9
+        addi    r8,r8,1
+        stdcx.  r8,0,r9
+        bne-    1b
+        blr
+#endif
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index ad2eb4d34dd4..2fbc680c2c71 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -7,8 +7,8 @@
  *
  *  -- BenH
  *
- * Copyright 2008 Ben Herrenschmidt <benh@kernel.crashing.org>
- *                IBM Corp.
+ * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
+ *                     IBM Corp.
  *
  *  Derived from arch/ppc/mm/init.c:
  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
@@ -34,12 +34,71 @@
 #include <linux/pagemap.h>
 #include <linux/preempt.h>
 #include <linux/spinlock.h>
+#include <linux/lmb.h>
 
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
+#include <asm/code-patching.h>
 
 #include "mmu_decl.h"
 
+#ifdef CONFIG_PPC_BOOK3E
+struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
+        [MMU_PAGE_4K] = {
+                .shift  = 12,
+                .enc    = BOOK3E_PAGESZ_4K,
+        },
+        [MMU_PAGE_16K] = {
+                .shift  = 14,
+                .enc    = BOOK3E_PAGESZ_16K,
+        },
+        [MMU_PAGE_64K] = {
+                .shift  = 16,
+                .enc    = BOOK3E_PAGESZ_64K,
+        },
+        [MMU_PAGE_1M] = {
+                .shift  = 20,
+                .enc    = BOOK3E_PAGESZ_1M,
+        },
+        [MMU_PAGE_16M] = {
+                .shift  = 24,
+                .enc    = BOOK3E_PAGESZ_16M,
+        },
+        [MMU_PAGE_256M] = {
+                .shift  = 28,
+                .enc    = BOOK3E_PAGESZ_256M,
+        },
+        [MMU_PAGE_1G] = {
+                .shift  = 30,
+                .enc    = BOOK3E_PAGESZ_1GB,
+        },
+};
+static inline int mmu_get_tsize(int psize)
+{
+        return mmu_psize_defs[psize].enc;
+}
+#else
+static inline int mmu_get_tsize(int psize)
+{
+        /* This isn't used on !Book3E for now */
+        return 0;
+}
+#endif
+
+/* The variables below are currently only used on 64-bit Book3E
+ * though this will probably be made common with other nohash
+ * implementations at some point
+ */
+#ifdef CONFIG_PPC64
+
+int mmu_linear_psize;           /* Page size used for the linear mapping */
+int mmu_pte_psize;              /* Page size used for PTE pages */
+int mmu_vmemmap_psize;          /* Page size used for the virtual mem map */
+int book3e_htw_enabled;         /* Is HW tablewalk enabled ? */
+unsigned long linear_map_top;   /* Top of linear mapping */
+
+#endif /* CONFIG_PPC64 */
+
 /*
  * Base TLB flushing operations:
  *
@@ -67,18 +126,24 @@ void local_flush_tlb_mm(struct mm_struct *mm)
 }
 EXPORT_SYMBOL(local_flush_tlb_mm);
 
-void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                            int tsize, int ind)
 {
         unsigned int pid;
 
         preempt_disable();
-        pid = vma ? vma->vm_mm->context.id : 0;
+        pid = mm ? mm->context.id : 0;
         if (pid != MMU_NO_CONTEXT)
-                _tlbil_va(vmaddr, pid);
+                _tlbil_va(vmaddr, pid, tsize, ind);
         preempt_enable();
 }
-EXPORT_SYMBOL(local_flush_tlb_page);
 
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+{
+        __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
+                               mmu_get_tsize(mmu_virtual_psize), 0);
+}
+EXPORT_SYMBOL(local_flush_tlb_page);
 
 /*
  * And here are the SMP non-local implementations
@@ -87,9 +152,17 @@ EXPORT_SYMBOL(local_flush_tlb_page);
 
 static DEFINE_SPINLOCK(tlbivax_lock);
 
+static int mm_is_core_local(struct mm_struct *mm)
+{
+        return cpumask_subset(mm_cpumask(mm),
+                              topology_thread_cpumask(smp_processor_id()));
+}
+
 struct tlb_flush_param {
         unsigned long addr;
         unsigned int pid;
+        unsigned int tsize;
+        unsigned int ind;
 };
 
 static void do_flush_tlb_mm_ipi(void *param)
@@ -103,7 +176,7 @@ static void do_flush_tlb_page_ipi(void *param)
 {
         struct tlb_flush_param *p = param;
 
-        _tlbil_va(p->addr, p->pid);
+        _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
 }
 
 
@@ -131,7 +204,7 @@ void flush_tlb_mm(struct mm_struct *mm)
         pid = mm->context.id;
         if (unlikely(pid == MMU_NO_CONTEXT))
                 goto no_context;
-        if (!cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
+        if (!mm_is_core_local(mm)) {
                 struct tlb_flush_param p = { .pid = pid };
                 /* Ignores smp_processor_id() even if set. */
                 smp_call_function_many(mm_cpumask(mm),
@@ -143,37 +216,49 @@ void flush_tlb_mm(struct mm_struct *mm)
 }
 EXPORT_SYMBOL(flush_tlb_mm);
 
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                      int tsize, int ind)
 {
         struct cpumask *cpu_mask;
         unsigned int pid;
 
         preempt_disable();
-        pid = vma ? vma->vm_mm->context.id : 0;
+        pid = mm ? mm->context.id : 0;
         if (unlikely(pid == MMU_NO_CONTEXT))
                 goto bail;
-        cpu_mask = mm_cpumask(vma->vm_mm);
-        if (!cpumask_equal(cpu_mask, cpumask_of(smp_processor_id()))) {
+        cpu_mask = mm_cpumask(mm);
+        if (!mm_is_core_local(mm)) {
                 /* If broadcast tlbivax is supported, use it */
                 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
                         int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
                         if (lock)
                                 spin_lock(&tlbivax_lock);
-                        _tlbivax_bcast(vmaddr, pid);
+                        _tlbivax_bcast(vmaddr, pid, tsize, ind);
                         if (lock)
                                 spin_unlock(&tlbivax_lock);
                         goto bail;
                 } else {
-                        struct tlb_flush_param p = { .pid = pid, .addr = vmaddr };
+                        struct tlb_flush_param p = {
+                                .pid = pid,
+                                .addr = vmaddr,
+                                .tsize = tsize,
+                                .ind = ind,
+                        };
                         /* Ignores smp_processor_id() even if set in cpu_mask */
                         smp_call_function_many(cpu_mask,
                                                do_flush_tlb_page_ipi, &p, 1);
                 }
         }
-        _tlbil_va(vmaddr, pid);
+        _tlbil_va(vmaddr, pid, tsize, ind);
  bail:
         preempt_enable();
 }
+
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+{
+        __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
+                         mmu_get_tsize(mmu_virtual_psize), 0);
+}
 EXPORT_SYMBOL(flush_tlb_page);
 
 #endif /* CONFIG_SMP */
@@ -207,3 +292,156 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
         flush_tlb_mm(vma->vm_mm);
 }
 EXPORT_SYMBOL(flush_tlb_range);
+
+void tlb_flush(struct mmu_gather *tlb)
+{
+        flush_tlb_mm(tlb->mm);
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
+}
+
+/*
+ * Below are functions specific to the 64-bit variant of Book3E though that
+ * may change in the future
+ */
+
+#ifdef CONFIG_PPC64
+
+/*
+ * Handling of virtual linear page tables or indirect TLB entries
+ * flushing when PTE pages are freed
+ */
+void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
+{
+        int tsize = mmu_psize_defs[mmu_pte_psize].enc;
+
+        if (book3e_htw_enabled) {
+                unsigned long start = address & PMD_MASK;
+                unsigned long end = address + PMD_SIZE;
+                unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
+
+                /* This isn't the most optimal, ideally we would factor out the
+                 * while preempt & CPU mask mucking around, or even the IPI but
+                 * it will do for now
+                 */
+                while (start < end) {
+                        __flush_tlb_page(tlb->mm, start, tsize, 1);
+                        start += size;
+                }
+        } else {
+                unsigned long rmask = 0xf000000000000000ul;
+                unsigned long rid = (address & rmask) | 0x1000000000000000ul;
+                unsigned long vpte = address & ~rmask;
+
+#ifdef CONFIG_PPC_64K_PAGES
+                vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
+#else
+                vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
+#endif
+                vpte |= rid;
+                __flush_tlb_page(tlb->mm, vpte, tsize, 0);
+        }
+}
+
+/*
+ * Early initialization of the MMU TLB code
+ */
+static void __early_init_mmu(int boot_cpu)
+{
+        extern unsigned int interrupt_base_book3e;
+        extern unsigned int exc_data_tlb_miss_htw_book3e;
+        extern unsigned int exc_instruction_tlb_miss_htw_book3e;
+
+        unsigned int *ibase = &interrupt_base_book3e;
+        unsigned int mas4;
+
+        /* XXX This will have to be decided at runtime, but right
+         * now our boot and TLB miss code hard wires it. Ideally
+         * we should find out a suitable page size and patch the
+         * TLB miss code (either that or use the PACA to store
+         * the value we want)
+         */
+        mmu_linear_psize = MMU_PAGE_1G;
+
+        /* XXX This should be decided at runtime based on supported
+         * page sizes in the TLB, but for now let's assume 16M is
+         * always there and a good fit (which it probably is)
+         */
+        mmu_vmemmap_psize = MMU_PAGE_16M;
+
+        /* Check if HW tablewalk is present, and if yes, enable it by:
+         *
+         * - patching the TLB miss handlers to branch to the
+         *   one dedicates to it
+         *
+         * - setting the global book3e_htw_enabled
+         *
+         * - Set MAS4:INDD and default page size
+         */
+
+        /* XXX This code only checks for TLB 0 capabilities and doesn't
+         *     check what page size combos are supported by the HW. It
+         *     also doesn't handle the case where a separate array holds
+         *     the IND entries from the array loaded by the PT.
+         */
+        if (boot_cpu) {
+                unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+
+                /* Check if HW loader is supported */
+                if ((tlb0cfg & TLBnCFG_IND) &&
+                    (tlb0cfg & TLBnCFG_PT)) {
+                        patch_branch(ibase + (0x1c0 / 4),
+                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
+                        patch_branch(ibase + (0x1e0 / 4),
+                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
+                        book3e_htw_enabled = 1;
+                }
+                pr_info("MMU: Book3E Page Tables %s\n",
+                        book3e_htw_enabled ? "Enabled" : "Disabled");
+        }
+
+        /* Set MAS4 based on page table setting */
+
+        mas4 = 0x4 << MAS4_WIMGED_SHIFT;
+        if (book3e_htw_enabled) {
+                mas4 |= mas4 | MAS4_INDD;
+#ifdef CONFIG_PPC_64K_PAGES
+                mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
+                mmu_pte_psize = MMU_PAGE_256M;
+#else
+                mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
+                mmu_pte_psize = MMU_PAGE_1M;
+#endif
+        } else {
+#ifdef CONFIG_PPC_64K_PAGES
+                mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
+#else
+                mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
+#endif
+                mmu_pte_psize = mmu_virtual_psize;
+        }
+        mtspr(SPRN_MAS4, mas4);
+
+        /* Set the global containing the top of the linear mapping
+         * for use by the TLB miss code
+         */
+        linear_map_top = lmb_end_of_DRAM();
+
+        /* A sync won't hurt us after mucking around with
+         * the MMU configuration
+         */
+        mb();
+}
+
+void __init early_init_mmu(void)
+{
+        __early_init_mmu(1);
+}
+
+void __cpuinit early_init_mmu_secondary(void)
+{
+        __early_init_mmu(0);
+}
+
+#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 3037911279b1..bbdc5b577b85 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -39,7 +39,7 @@
 /*
  * 40x implementation needs only tlbil_va
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         /* We run the search with interrupts disabled because we have to change
          * the PID and I don't want to preempt when that happens.
          */
@@ -71,7 +71,7 @@ _GLOBAL(_tlbil_va)
  * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
  * of the TLB for everything else.
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         mfspr   r5,SPRN_MMUCR
         rlwimi  r5,r4,0,24,31                   /* Set TID */
 
@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid)
  * to have the larger code path before the _SECTION_ELSE
  */
 
-#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
-                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 /*
  * Flush MMU TLB on the local processor
  */
@@ -170,7 +168,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
  * Flush MMU TLB for a particular address, but only on the local processor
  * (no broadcast)
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         mfmsr   r10
         wrteei  0
         slwi    r4,r4,16
@@ -191,6 +189,85 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         isync
 1:      wrtee   r10
         blr
+#elif defined(CONFIG_PPC_BOOK3E)
+/*
+ * New Book3E (>= 2.06) implementation
+ *
+ * Note: We may be able to get away without the interrupt masking stuff
+ * if we save/restore MAS6 on exceptions that might modify it
+ */
+_GLOBAL(_tlbil_pid)
+        slwi    r4,r3,MAS6_SPID_SHIFT
+        mfmsr   r10
+        wrteei  0
+        mtspr   SPRN_MAS6,r4
+        PPC_TLBILX_PID(0,0)
+        wrtee   r10
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_pid_noind)
+        slwi    r4,r3,MAS6_SPID_SHIFT
+        mfmsr   r10
+        ori     r4,r4,MAS6_SIND
+        wrteei  0
+        mtspr   SPRN_MAS6,r4
+        PPC_TLBILX_PID(0,0)
+        wrtee   r10
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_all)
+        PPC_TLBILX_ALL(0,0)
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_va)
+        mfmsr   r10
+        wrteei  0
+        cmpwi   cr0,r6,0
+        slwi    r4,r4,MAS6_SPID_SHIFT
+        rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+        beq     1f
+        rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+        PPC_TLBILX_VA(0,r3)
+        msync
+        isync
+        wrtee   r10
+        blr
+
+_GLOBAL(_tlbivax_bcast)
+        mfmsr   r10
+        wrteei  0
+        cmpwi   cr0,r6,0
+        slwi    r4,r4,MAS6_SPID_SHIFT
+        rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+        beq     1f
+        rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+        PPC_TLBIVAX(0,r3)
+        eieio
+        tlbsync
+        sync
+        wrtee   r10
+        blr
+
+_GLOBAL(set_context)
+#ifdef CONFIG_BDI_SWITCH
+        /* Context switch the PTE pointer for the Abatron BDI2000.
+         * The PGDIR is the second parameter.
+         */
+        lis     r5, abatron_pteptrs@h
+        ori     r5, r5, abatron_pteptrs@l
+        stw     r4, 0x4(r5)
+#endif
+        mtspr   SPRN_PID,r3
+        isync                   /* Force context change */
+        blr
 #else
 #error Unsupported processor type !
 #endif
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index a6e43cb6f825..ec64264f7a50 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -40,6 +40,16 @@ config HCU4
         help
           This option enables support for the Nestal Maschinen HCU4 board.
 
+config HOTFOOT
+        bool "Hotfoot"
+        depends on 40x
+        default n
+        select 405EP
+        select PPC40x_SIMPLE
+        select PCI
+        help
+         This option enables support for the ESTEEM 195E Hotfoot board.
+
 config KILAUEA
         bool "Kilauea"
         depends on 40x
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index 5fd5a5974001..546bbc229d19 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -54,7 +54,8 @@ static char *board[] __initdata = {
         "amcc,acadia",
         "amcc,haleakala",
         "amcc,kilauea",
-        "amcc,makalu"
+        "amcc,makalu",
+        "est,hotfoot"
 };
 
 static int __init ppc40x_probe(void)
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 90e3192611a4..7486bffd3ebb 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -129,6 +129,18 @@ config REDWOOD
         help
           This option enables support for the AMCC PPC460SX Redwood board.
 
+config EIGER
+        bool "Eiger"
+        depends on 44x
+        default n
+        select PPC44x_SIMPLE
+        select 460SX
+        select PCI
+        select PPC4xx_PCI_EXPRESS
+        select IBM_NEW_EMAC_RGMII
+        help
+          This option enables support for the AMCC PPC460SX evaluation board.
+
 config YOSEMITE
         bool "Yosemite"
         depends on 44x
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 5bcd441885e8..e8c23ccaa1fc 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -55,6 +55,7 @@ static char *board[] __initdata = {
         "amcc,canyonlands",
         "amcc,glacier",
         "ibm,ebony",
+        "amcc,eiger",
         "amcc,katmai",
         "amcc,rainier",
         "amcc,redwood",
diff --git a/arch/powerpc/platforms/82xx/mgcoge.c b/arch/powerpc/platforms/82xx/mgcoge.c
index c2af169c1d1d..7a5de9eb3c73 100644
--- a/arch/powerpc/platforms/82xx/mgcoge.c
+++ b/arch/powerpc/platforms/82xx/mgcoge.c
@@ -50,16 +50,63 @@ struct cpm_pin {
 static __initdata struct cpm_pin mgcoge_pins[] = {
 
         /* SMC2 */
-        {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 
         /* SCC4 */
-        {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3,  9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3,  8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {4, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {4, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2,  9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2,  8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+        /* FCC1 */
+        {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+
+        {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* FCC2 */
+        {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+        {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* MDC */
+        {0, 13, CPM_PIN_OUTPUT | CPM_PIN_GPIO},
+
+#if defined(CONFIG_I2C_CPM)
+        /* I2C */
+        {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+        {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+#endif
 };
 
 static void __init init_ioports(void)
@@ -68,12 +115,16 @@ static void __init init_ioports(void)
 
         for (i = 0; i < ARRAY_SIZE(mgcoge_pins); i++) {
                 const struct cpm_pin *pin = &mgcoge_pins[i];
-                cpm2_set_pin(pin->port - 1, pin->pin, pin->flags);
+                cpm2_set_pin(pin->port, pin->pin, pin->flags);
         }
 
         cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9,  CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
 }
 
 static void __init mgcoge_setup_arch(void)
diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c
index 8054c685d323..30394b409b3f 100644
--- a/arch/powerpc/platforms/82xx/mpc8272_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c
@@ -29,7 +29,6 @@
 #include <sysdev/fsl_soc.h>
 #include <sysdev/cpm2_pic.h>
 
-#include "pq2ads.h"
 #include "pq2.h"
 
 static void __init mpc8272_ads_pic_init(void)
@@ -100,6 +99,15 @@ static struct cpm_pin mpc8272_ads_pins[] = {
         /* I2C */
         {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
         {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+
+        /* USB */
+        {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 };
 
 static void __init init_ioports(void)
@@ -113,6 +121,8 @@ static void __init init_ioports(void)
 
         cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
         cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
         cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
@@ -144,12 +154,22 @@ static void __init mpc8272_ads_setup_arch(void)
                 return;
         }
 
+#define BCSR1_FETHIEN           0x08000000
+#define BCSR1_FETH_RST          0x04000000
+#define BCSR1_RS232_EN1         0x02000000
+#define BCSR1_RS232_EN2         0x01000000
+#define BCSR3_USB_nEN           0x80000000
+#define BCSR3_FETHIEN2          0x10000000
+#define BCSR3_FETH2_RST         0x08000000
+
         clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
         setbits32(&bcsr[1], BCSR1_FETH_RST);
 
         clrbits32(&bcsr[3], BCSR3_FETHIEN2);
         setbits32(&bcsr[3], BCSR3_FETH2_RST);
 
+        clrbits32(&bcsr[3], BCSR3_USB_nEN);
+
         iounmap(bcsr);
 
         init_ioports();
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 083ebee9a16d..f49a2548c5ff 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -75,11 +75,11 @@ config MPC837x_MDS
           This option enables support for the MPC837x MDS Processor Board.
 
 config MPC837x_RDB
-        bool "Freescale MPC837x RDB"
+        bool "Freescale MPC837x RDB/WLAN"
         select DEFAULT_UIMAGE
         select PPC_MPC837x
         help
-          This option enables support for the MPC837x RDB Board.
+          This option enables support for the MPC837x RDB and WLAN Boards.
 
 config SBC834x
         bool "Wind River SBC834x"
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 76f3b32a155e..a1908d261240 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -17,10 +17,32 @@
 #include <asm/time.h>
 #include <asm/ipic.h>
 #include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
 
 #include "mpc83xx.h"
 
+static void mpc837x_rdb_sd_cfg(void)
+{
+        void __iomem *im;
+
+        im = ioremap(get_immrbase(), 0x1000);
+        if (!im) {
+                WARN_ON(1);
+                return;
+        }
+
+        /*
+         * On RDB boards (in contrast to MDS) USBB pins are used for SD only,
+         * so we can safely mux them away from the USB block.
+         */
+        clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK,
+                                                 MPC837X_SICRL_SD);
+        clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK,
+                                                 MPC837X_SICRH_SD);
+        iounmap(im);
+}
+
 /* ************************************************************************
  *
  * Setup the architecture
@@ -42,6 +64,7 @@ static void __init mpc837x_rdb_setup_arch(void)
                 mpc83xx_add_bridge(np);
 #endif
         mpc837x_usb_cfg();
+        mpc837x_rdb_sd_cfg();
 }
 
 static struct of_device_id mpc837x_ids[] = {
@@ -86,11 +109,12 @@ static int __init mpc837x_rdb_probe(void)
 
         return of_flat_dt_is_compatible(root, "fsl,mpc8377rdb") ||
                of_flat_dt_is_compatible(root, "fsl,mpc8378rdb") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8379rdb");
+               of_flat_dt_is_compatible(root, "fsl,mpc8379rdb") ||
+               of_flat_dt_is_compatible(root, "fsl,mpc8377wlan");
 }
 
 define_machine(mpc837x_rdb) {
-        .name                   = "MPC837x RDB",
+        .name                   = "MPC837x RDB/WLAN",
         .probe                  = mpc837x_rdb_probe,
         .setup_arch             = mpc837x_rdb_setup_arch,
         .init_IRQ               = mpc837x_rdb_init_IRQ,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index d1dc5b0b4fbf..0fea8811d45b 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -30,6 +30,8 @@
 #define MPC8315_SICRL_USB_ULPI     0x00000054
 #define MPC837X_SICRL_USB_MASK     0xf0000000
 #define MPC837X_SICRL_USB_ULPI     0x50000000
+#define MPC837X_SICRL_USBB_MASK    0x30000000
+#define MPC837X_SICRL_SD           0x20000000
 
 /* system i/o configuration register high */
 #define MPC83XX_SICRH_OFFS         0x118
@@ -38,6 +40,8 @@
 #define MPC831X_SICRH_USB_ULPI     0x000000a0
 #define MPC8315_SICRH_USB_MASK     0x0000ff00
 #define MPC8315_SICRH_USB_ULPI     0x00000000
+#define MPC837X_SICRH_SPI_MASK     0x00000003
+#define MPC837X_SICRH_SD           0x00000001
 
 /* USB Control Register */
 #define FSL_USB2_CONTROL_OFFS      0x500
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a9b416688975..d3a975e8fd3e 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -55,6 +55,15 @@ config MPC85xx_DS
         help
           This option enables support for the MPC85xx DS (MPC8544 DS) board
 
+config MPC85xx_RDB
+        bool "Freescale MPC85xx RDB"
+        select PPC_I8259
+        select DEFAULT_UIMAGE
+        select FSL_ULI1575
+        select SWIOTLB
+        help
+          This option enables support for the MPC85xx RDB (P2020 RDB) board
+
 config SOCRATES
         bool "Socrates"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 835733f2b12c..9098aea0cf32 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
 obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
 obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
 obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8560)     += sbc8560.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
 obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 obj-$(CONFIG_KSI8560)     += ksi8560.o
-obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file
+obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 055ff417bae9..004b7d36cdb7 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -96,7 +96,8 @@ static void __init mpc8536_ds_setup_arch(void)
 #ifdef CONFIG_SWIOTLB
         if (lmb_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_pci_dma_ops);
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
         }
 #endif
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 849c0ac0025f..544011a562fb 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -192,7 +192,8 @@ static void __init mpc85xx_ds_setup_arch(void)
 #ifdef CONFIG_SWIOTLB
         if (lmb_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_pci_dma_ops);
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
         }
 #endif
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index bfb32834ab0c..3909d57b86e3 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -47,6 +47,7 @@
 #include <asm/udbg.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include <sysdev/simple_gpio.h>
 #include <asm/qe.h>
 #include <asm/qe_ic.h>
 #include <asm/mpic.h>
@@ -254,7 +255,8 @@ static void __init mpc85xx_mds_setup_arch(void)
 #ifdef CONFIG_SWIOTLB
         if (lmb_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_pci_dma_ops);
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
         }
 #endif
 }
@@ -304,6 +306,9 @@ static struct of_device_id mpc85xx_ids[] = {
 
 static int __init mpc85xx_publish_devices(void)
 {
+        if (machine_is(mpc8569_mds))
+                simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
+
         /* Publish the QE devices */
         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
new file mode 100644
index 000000000000..c8468de4acf6
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -0,0 +1,141 @@
+/*
+ * MPC85xx RDB Board Setup
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+
+void __init mpc85xx_rdb_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (np == NULL) {
+                printk(KERN_ERR "Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                printk(KERN_ERR "Failed to map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        mpic = mpic_alloc(np, r.start,
+                  MPIC_PRIMARY | MPIC_WANTS_RESET |
+                  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                  MPIC_SINGLE_DEST_CPU,
+                  0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_init(mpic);
+
+}
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+static void __init mpc85xx_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
+                        fsl_add_bridge(np, 0);
+        }
+
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+        printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
+}
+
+static struct of_device_id __initdata mpc85xxrdb_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .compatible = "gianfar", },
+        {},
+};
+
+static int __init mpc85xxrdb_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
+}
+machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2020_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
+                return 1;
+        return 0;
+}
+
+define_machine(p2020_rdb) {
+        .name                   = "P2020 RDB",
+        .probe                  = p2020_rdb_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index cc27807a8b64..a5ad1c7794bf 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -267,6 +267,43 @@ arch_initcall(sbc8560_rtc_init);
 
 #endif  /* M48T59 */
 
+static __u8 __iomem *brstcr;
+
+static int __init sbc8560_bdrstcr_init(void)
+{
+        struct device_node *np;
+        struct resource res;
+
+        np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
+        if (np == NULL) {
+                printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
+                return -ENODEV;
+        }
+
+        of_address_to_resource(np, 0, &res);
+
+        printk(KERN_INFO "sbc8560: Found BRSTCR at i/o 0x%x\n", res.start);
+
+        brstcr = ioremap(res.start, res.end - res.start);
+        if(!brstcr)
+                printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
+
+        of_node_put(np);
+
+        return 0;
+}
+
+arch_initcall(sbc8560_bdrstcr_init);
+
+void sbc8560_rstcr_restart(char * cmd)
+{
+        local_irq_disable();
+        if(brstcr)
+                clrbits8(brstcr, 0x80);
+
+        while(1);
+}
+
 define_machine(sbc8560) {
         .name                   = "SBC8560",
         .probe                  = sbc8560_probe,
@@ -274,7 +311,7 @@ define_machine(sbc8560) {
         .init_IRQ               = sbc8560_pic_init,
         .show_cpuinfo           = sbc8560_show_cpuinfo,
         .get_irq                = mpic_get_irq,
-        .restart                = fsl_rstcr_restart,
+        .restart                = sbc8560_rstcr_restart,
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
 };
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 62c592ede641..04160a4cc699 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -25,7 +25,6 @@
 
 #include <sysdev/fsl_soc.h>
 
-extern volatile unsigned long __secondary_hold_acknowledge;
 extern void __early_start(void);
 
 #define BOOT_ENTRY_ADDR_UPPER   0
@@ -80,46 +79,24 @@ smp_85xx_kick_cpu(int nr)
 }
 
 static void __init
-smp_85xx_basic_setup(int cpu_nr)
-{
-        /* Clear any pending timer interrupts */
-        mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
-
-        /* Enable decrementer interrupt */
-        mtspr(SPRN_TCR, TCR_DIE);
-}
-
-static void __init
 smp_85xx_setup_cpu(int cpu_nr)
 {
         mpic_setup_this_cpu();
-
-        smp_85xx_basic_setup(cpu_nr);
 }
 
 struct smp_ops_t smp_85xx_ops = {
         .kick_cpu = smp_85xx_kick_cpu,
 };
 
-static int __init smp_dummy_probe(void)
-{
-        return NR_CPUS;
-}
-
 void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
 
-        smp_85xx_ops.message_pass = NULL;
-
         np = of_find_node_by_type(NULL, "open-pic");
         if (np) {
                 smp_85xx_ops.probe = smp_mpic_probe;
                 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
                 smp_85xx_ops.message_pass = smp_mpic_message_pass;
-        } else {
-                smp_85xx_ops.probe = smp_dummy_probe;
-                smp_85xx_ops.setup_cpu = smp_85xx_basic_setup;
         }
 
         if (cpu_has_feature(CPU_FTR_DBELL))
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 2efa052975e6..287f7bd17dd9 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -102,8 +102,8 @@ static unsigned int gef_ppc9a_get_pcb_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 8) & 0xff;
+        reg = ioread32be(ppc9a_regs);
+        return (reg >> 16) & 0xff;
 }
 
 /* Return the board (software) revision */
@@ -111,8 +111,8 @@ static unsigned int gef_ppc9a_get_board_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 16) & 0xff;
+        reg = ioread32be(ppc9a_regs);
+        return (reg >> 8) & 0xff;
 }
 
 /* Return the FPGA revision */
@@ -120,8 +120,26 @@ static unsigned int gef_ppc9a_get_fpga_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 24) & 0xf;
+        reg = ioread32be(ppc9a_regs);
+        return reg & 0xf;
+}
+
+/* Return VME Geographical Address */
+static unsigned int gef_ppc9a_get_vme_geo_addr(void)
+{
+        unsigned int reg;
+
+        reg = ioread32be(ppc9a_regs + 0x4);
+        return reg & 0x1f;
+}
+
+/* Return VME System Controller Status */
+static unsigned int gef_ppc9a_get_vme_is_syscon(void)
+{
+        unsigned int reg;
+
+        reg = ioread32be(ppc9a_regs + 0x4);
+        return (reg >> 9) & 0x1;
 }
 
 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
@@ -131,10 +149,15 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
-                ('A' + gef_ppc9a_get_board_rev() - 1));
+                ('A' + gef_ppc9a_get_board_rev()));
         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+        seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
+
+        seq_printf(m, "VME syscon\t: %s\n",
+                gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 }
 
 static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 66327024a6a6..2aa69a69bcc8 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -105,7 +105,8 @@ mpc86xx_hpcn_setup_arch(void)
 #ifdef CONFIG_SWIOTLB
         if (lmb_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_pci_dma_ops);
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
         }
 #endif
 }
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
index d84bbb508ee7..eacea0e3fcc8 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -27,7 +27,6 @@
 #include "mpc86xx.h"
 
 extern void __secondary_start_mpc86xx(void);
-extern unsigned long __secondary_hold_acknowledge;
 
 #define MCM_PORT_CONFIG_OFFSET  0x10
 
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 61187bec7506..9efc8bda01b4 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -57,15 +57,35 @@ config E200
 
 endchoice
 
-config PPC_BOOK3S_64
-        def_bool y
+choice
+        prompt "Processor Type"
         depends on PPC64
+        help
+          There are two families of 64 bit PowerPC chips supported.
+          The most common ones are the desktop and server CPUs
+          (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
+
+          The other are the "embedded" processors compliant with the
+          "Book 3E" variant of the architecture
+
+config PPC_BOOK3S_64
+        bool "Server processors"
         select PPC_FPU
 
+config PPC_BOOK3E_64
+        bool "Embedded processors"
+        select PPC_FPU # Make it a choice ?
+
+endchoice
+
 config PPC_BOOK3S
         def_bool y
         depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
 
+config PPC_BOOK3E
+        def_bool y
+        depends on PPC_BOOK3E_64
+
 config POWER4_ONLY
         bool "Optimize for POWER4"
         depends on PPC64 && PPC_BOOK3S
@@ -125,7 +145,7 @@ config 4xx
 
 config BOOKE
         bool
-        depends on E200 || E500 || 44x
+        depends on E200 || E500 || 44x || PPC_BOOK3E
         default y
 
 config FSL_BOOKE
@@ -223,9 +243,17 @@ config PPC_MMU_NOHASH
         def_bool y
         depends on !PPC_STD_MMU
 
+config PPC_MMU_NOHASH_32
+        def_bool y
+        depends on PPC_MMU_NOHASH && PPC32
+
+config PPC_MMU_NOHASH_64
+        def_bool y
+        depends on PPC_MMU_NOHASH && PPC64
+
 config PPC_BOOK3E_MMU
         def_bool y
-        depends on FSL_BOOKE
+        depends on FSL_BOOKE || PPC_BOOK3E
 
 config PPC_MM_SLICES
         bool
@@ -257,7 +285,7 @@ config PPC_PERF_CTRS
          This enables the powerpc-specific perf_counter back-end.
 
 config SMP
-        depends on PPC_STD_MMU || FSL_BOOKE
+        depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE
         bool "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
index 443035366c12..9290a7a442d0 100644
--- a/arch/powerpc/platforms/amigaone/setup.c
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -110,13 +110,16 @@ void __init amigaone_init_IRQ(void)
         irq_set_default_host(i8259_get_host());
 }
 
-void __init amigaone_init(void)
+static int __init request_isa_regions(void)
 {
         request_region(0x00, 0x20, "dma1");
         request_region(0x40, 0x20, "timer");
         request_region(0x80, 0x10, "dma page reg");
         request_region(0xc0, 0x20, "dma2");
+
+        return 0;
 }
+machine_device_initcall(amigaone, request_isa_regions);
 
 void amigaone_restart(char *cmd)
 {
@@ -161,7 +164,6 @@ define_machine(amigaone) {
         .name                   = "AmigaOne",
         .probe                  = amigaone_probe,
         .setup_arch             = amigaone_setup_arch,
-        .init                   = amigaone_init,
         .show_cpuinfo           = amigaone_show_cpuinfo,
         .init_IRQ               = amigaone_init_IRQ,
         .restart                = amigaone_restart,
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 50f17bdd3c16..48cd7d2e1b75 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -80,13 +80,6 @@ config SPU_FS_64K_LS
           uses 4K pages. This can improve performances of applications
           using multiple SPEs by lowering the TLB pressure on them.
 
-config SPU_TRACE
-        tristate "SPU event tracing support"
-        depends on SPU_FS && MARKERS
-        help
-          This option allows reading a trace of spu-related events through
-          the sputrace file in procfs.
-
 config SPU_BASE
         bool
         default n
diff --git a/arch/powerpc/platforms/cell/celleb_setup.c b/arch/powerpc/platforms/cell/celleb_setup.c
index 07c234f6b2b6..e53845579770 100644
--- a/arch/powerpc/platforms/cell/celleb_setup.c
+++ b/arch/powerpc/platforms/cell/celleb_setup.c
@@ -80,8 +80,7 @@ static void celleb_show_cpuinfo(struct seq_file *m)
 
 static int __init celleb_machine_type_hack(char *ptr)
 {
-        strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
-        celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
+        strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
         return 0;
 }
 
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 5b34fc211f35..416db17eb18f 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -642,7 +642,7 @@ static int dma_fixed_dma_supported(struct device *dev, u64 mask)
 
 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
 
-struct dma_mapping_ops dma_iommu_fixed_ops = {
+struct dma_map_ops dma_iommu_fixed_ops = {
         .alloc_coherent = dma_fixed_alloc_coherent,
         .free_coherent  = dma_fixed_free_coherent,
         .map_sg         = dma_fixed_map_sg,
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index bc97fada48c6..f774530075b7 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -58,8 +58,6 @@
  */
 static cpumask_t of_spin_map;
 
-extern void generic_secondary_smp_init(unsigned long);
-
 /**
  * smp_startup_cpu() - start the given cpu
  *
diff --git a/arch/powerpc/platforms/cell/spufs/Makefile b/arch/powerpc/platforms/cell/spufs/Makefile
index 99610a6361f2..b93f877ba504 100644
--- a/arch/powerpc/platforms/cell/spufs/Makefile
+++ b/arch/powerpc/platforms/cell/spufs/Makefile
@@ -4,7 +4,8 @@ spufs-y += inode.o file.o context.o syscalls.o coredump.o
 spufs-y += sched.o backing_ops.o hw_ops.o run.o gang.o
 spufs-y += switch.o fault.o lscsa_alloc.o
 
-obj-$(CONFIG_SPU_TRACE) += sputrace.o
+# magic for the trace events
+CFLAGS_sched.o := -I$(src)
 
 # Rules to build switch.o with the help of SPU tool chain
 SPU_CROSS       := spu-
diff --git a/arch/powerpc/platforms/cell/spufs/context.c b/arch/powerpc/platforms/cell/spufs/context.c
index db5398c0339f..0c87bcd2452a 100644
--- a/arch/powerpc/platforms/cell/spufs/context.c
+++ b/arch/powerpc/platforms/cell/spufs/context.c
@@ -28,6 +28,7 @@
 #include <asm/spu.h>
 #include <asm/spu_csa.h>
 #include "spufs.h"
+#include "sputrace.h"
 
 
 atomic_t nr_spu_contexts = ATOMIC_INIT(0);
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index d6a519e6e1c1..ab8aef9bb8ea 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -38,6 +38,7 @@
 #include <asm/uaccess.h>
 
 #include "spufs.h"
+#include "sputrace.h"
 
 #define SPUFS_MMAP_4K (PAGE_SIZE == 0x1000)
 
diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c
index f085369301b1..bb5b77c66d05 100644
--- a/arch/powerpc/platforms/cell/spufs/sched.c
+++ b/arch/powerpc/platforms/cell/spufs/sched.c
@@ -47,6 +47,8 @@
 #include <asm/spu_csa.h>
 #include <asm/spu_priv1.h>
 #include "spufs.h"
+#define CREATE_TRACE_POINTS
+#include "sputrace.h"
 
 struct spu_prio_array {
         DECLARE_BITMAP(bitmap, MAX_PRIO);
diff --git a/arch/powerpc/platforms/cell/spufs/spufs.h b/arch/powerpc/platforms/cell/spufs/spufs.h
index ae31573bea4a..c448bac65518 100644
--- a/arch/powerpc/platforms/cell/spufs/spufs.h
+++ b/arch/powerpc/platforms/cell/spufs/spufs.h
@@ -373,9 +373,4 @@ extern void spu_free_lscsa(struct spu_state *csa);
 extern void spuctx_switch_state(struct spu_context *ctx,
                 enum spu_utilization_state new_state);
 
-#define spu_context_trace(name, ctx, spu) \
-        trace_mark(name, "ctx %p spu %p", ctx, spu);
-#define spu_context_nospu_trace(name, ctx) \
-        trace_mark(name, "ctx %p", ctx);
-
 #endif
diff --git a/arch/powerpc/platforms/cell/spufs/sputrace.c b/arch/powerpc/platforms/cell/spufs/sputrace.c
deleted file mode 100644
index d0b1f3f4d9c8..000000000000
--- a/arch/powerpc/platforms/cell/spufs/sputrace.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2007 IBM Deutschland Entwicklung GmbH
- *      Released under GPL v2.
- *
- * Partially based on net/ipv4/tcp_probe.c.
- *
- * Simple tracing facility for spu contexts.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/marker.h>
-#include <linux/proc_fs.h>
-#include <linux/wait.h>
-#include <asm/atomic.h>
-#include <asm/uaccess.h>
-#include "spufs.h"
-
-struct spu_probe {
-        const char *name;
-        const char *format;
-        marker_probe_func *probe_func;
-};
-
-struct sputrace {
-        ktime_t tstamp;
-        int owner_tid; /* owner */
-        int curr_tid;
-        const char *name;
-        int number;
-};
-
-static int bufsize __read_mostly = 16384;
-MODULE_PARM_DESC(bufsize, "Log buffer size (number of records)");
-module_param(bufsize, int, 0);
-
-
-static DEFINE_SPINLOCK(sputrace_lock);
-static DECLARE_WAIT_QUEUE_HEAD(sputrace_wait);
-static ktime_t sputrace_start;
-static unsigned long sputrace_head, sputrace_tail;
-static struct sputrace *sputrace_log;
-static int sputrace_logging;
-
-static int sputrace_used(void)
-{
-        return (sputrace_head - sputrace_tail) % bufsize;
-}
-
-static inline int sputrace_avail(void)
-{
-        return bufsize - sputrace_used();
-}
-
-static int sputrace_sprint(char *tbuf, int n)
-{
-        const struct sputrace *t = sputrace_log + sputrace_tail % bufsize;
-        struct timespec tv =
-                ktime_to_timespec(ktime_sub(t->tstamp, sputrace_start));
-
-        return snprintf(tbuf, n,
-                "[%lu.%09lu] %d: %s (ctxthread = %d, spu = %d)\n",
-                (unsigned long) tv.tv_sec,
-                (unsigned long) tv.tv_nsec,
-                t->curr_tid,
-                t->name,
-                t->owner_tid,
-                t->number);
-}
-
-static ssize_t sputrace_read(struct file *file, char __user *buf,
-                size_t len, loff_t *ppos)
-{
-        int error = 0, cnt = 0;
-
-        if (!buf || len < 0)
-                return -EINVAL;
-
-        while (cnt < len) {
-                char tbuf[128];
-                int width;
-
-                /* If we have data ready to return, don't block waiting
-                 * for more */
-                if (cnt > 0 && sputrace_used() == 0)
-                        break;
-
-                error = wait_event_interruptible(sputrace_wait,
-                                                 sputrace_used() > 0);
-                if (error)
-                        break;
-
-                spin_lock(&sputrace_lock);
-                if (sputrace_head == sputrace_tail) {
-                        spin_unlock(&sputrace_lock);
-                        continue;
-                }
-
-                width = sputrace_sprint(tbuf, sizeof(tbuf));
-                if (width < len)
-                        sputrace_tail = (sputrace_tail + 1) % bufsize;
-                spin_unlock(&sputrace_lock);
-
-                if (width >= len)
-                        break;
-
-                error = copy_to_user(buf + cnt, tbuf, width);
-                if (error)
-                        break;
-                cnt += width;
-        }
-
-        return cnt == 0 ? error : cnt;
-}
-
-static int sputrace_open(struct inode *inode, struct file *file)
-{
-        int rc;
-
-        spin_lock(&sputrace_lock);
-        if (sputrace_logging) {
-                rc = -EBUSY;
-                goto out;
-        }
-
-        sputrace_logging = 1;
-        sputrace_head = sputrace_tail = 0;
-        sputrace_start = ktime_get();
-        rc = 0;
-
-out:
-        spin_unlock(&sputrace_lock);
-        return rc;
-}
-
-static int sputrace_release(struct inode *inode, struct file *file)
-{
-        spin_lock(&sputrace_lock);
-        sputrace_logging = 0;
-        spin_unlock(&sputrace_lock);
-        return 0;
-}
-
-static const struct file_operations sputrace_fops = {
-        .owner   = THIS_MODULE,
-        .open    = sputrace_open,
-        .read    = sputrace_read,
-        .release = sputrace_release,
-};
-
-static void sputrace_log_item(const char *name, struct spu_context *ctx,
-                struct spu *spu)
-{
-        spin_lock(&sputrace_lock);
-
-        if (!sputrace_logging) {
-                spin_unlock(&sputrace_lock);
-                return;
-        }
-
-        if (sputrace_avail() > 1) {
-                struct sputrace *t = sputrace_log + sputrace_head;
-
-                t->tstamp = ktime_get();
-                t->owner_tid = ctx->tid;
-                t->name = name;
-                t->curr_tid = current->pid;
-                t->number = spu ? spu->number : -1;
-
-                sputrace_head = (sputrace_head + 1) % bufsize;
-        } else {
-                printk(KERN_WARNING
-                       "sputrace: lost samples due to full buffer.\n");
-        }
-        spin_unlock(&sputrace_lock);
-
-        wake_up(&sputrace_wait);
-}
-
-static void spu_context_event(void *probe_private, void *call_data,
-                const char *format, va_list *args)
-{
-        struct spu_probe *p = probe_private;
-        struct spu_context *ctx;
-        struct spu *spu;
-
-        ctx = va_arg(*args, struct spu_context *);
-        spu = va_arg(*args, struct spu *);
-
-        sputrace_log_item(p->name, ctx, spu);
-}
-
-static void spu_context_nospu_event(void *probe_private, void *call_data,
-                const char *format, va_list *args)
-{
-        struct spu_probe *p = probe_private;
-        struct spu_context *ctx;
-
-        ctx = va_arg(*args, struct spu_context *);
-
-        sputrace_log_item(p->name, ctx, NULL);
-}
-
-struct spu_probe spu_probes[] = {
-        { "spu_bind_context__enter", "ctx %p spu %p", spu_context_event },
-        { "spu_unbind_context__enter", "ctx %p spu %p", spu_context_event },
-        { "spu_get_idle__enter", "ctx %p", spu_context_nospu_event },
-        { "spu_get_idle__found", "ctx %p spu %p", spu_context_event },
-        { "spu_get_idle__not_found", "ctx %p", spu_context_nospu_event },
-        { "spu_find_victim__enter", "ctx %p", spu_context_nospu_event },
-        { "spusched_tick__preempt", "ctx %p spu %p", spu_context_event },
-        { "spusched_tick__newslice", "ctx %p", spu_context_nospu_event },
-        { "spu_yield__enter", "ctx %p", spu_context_nospu_event },
-        { "spu_deactivate__enter", "ctx %p", spu_context_nospu_event },
-        { "__spu_deactivate__unload", "ctx %p spu %p", spu_context_event },
-        { "spufs_ps_fault__enter", "ctx %p", spu_context_nospu_event },
-        { "spufs_ps_fault__sleep", "ctx %p", spu_context_nospu_event },
-        { "spufs_ps_fault__wake", "ctx %p spu %p", spu_context_event },
-        { "spufs_ps_fault__insert", "ctx %p spu %p", spu_context_event },
-        { "spu_acquire_saved__enter", "ctx %p", spu_context_nospu_event },
-        { "destroy_spu_context__enter", "ctx %p", spu_context_nospu_event },
-        { "spufs_stop_callback__enter", "ctx %p spu %p", spu_context_event },
-};
-
-static int __init sputrace_init(void)
-{
-        struct proc_dir_entry *entry;
-        int i, error = -ENOMEM;
-
-        sputrace_log = kcalloc(bufsize, sizeof(struct sputrace), GFP_KERNEL);
-        if (!sputrace_log)
-                goto out;
-
-        entry = proc_create("sputrace", S_IRUSR, NULL, &sputrace_fops);
-        if (!entry)
-                goto out_free_log;
-
-        for (i = 0; i < ARRAY_SIZE(spu_probes); i++) {
-                struct spu_probe *p = &spu_probes[i];
-
-                error = marker_probe_register(p->name, p->format,
-                                              p->probe_func, p);
-                if (error)
-                        printk(KERN_INFO "Unable to register probe %s\n",
-                                        p->name);
-        }
-
-        return 0;
-
-out_free_log:
-        kfree(sputrace_log);
-out:
-        return -ENOMEM;
-}
-
-static void __exit sputrace_exit(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(spu_probes); i++)
-                marker_probe_unregister(spu_probes[i].name,
-                        spu_probes[i].probe_func, &spu_probes[i]);
-
-        remove_proc_entry("sputrace", NULL);
-        kfree(sputrace_log);
-        marker_synchronize_unregister();
-}
-
-module_init(sputrace_init);
-module_exit(sputrace_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/cell/spufs/sputrace.h b/arch/powerpc/platforms/cell/spufs/sputrace.h
new file mode 100644
index 000000000000..db2656aa4103
--- /dev/null
+++ b/arch/powerpc/platforms/cell/spufs/sputrace.h
@@ -0,0 +1,39 @@
+#if !defined(_TRACE_SPUFS_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_SPUFS_H
+
+#include <linux/tracepoint.h>
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM spufs
+
+TRACE_EVENT(spufs_context,
+        TP_PROTO(struct spu_context *ctx, struct spu *spu, const char *name),
+        TP_ARGS(ctx, spu, name),
+
+        TP_STRUCT__entry(
+                __field(const char *, name)
+                __field(int, owner_tid)
+                __field(int, number)
+        ),
+
+        TP_fast_assign(
+                __entry->name = name;
+                __entry->owner_tid = ctx->tid;
+                __entry->number = spu ? spu->number : -1;
+        ),
+
+        TP_printk("%s (ctxthread = %d, spu = %d)",
+                __entry->name, __entry->owner_tid, __entry->number)
+);
+
+#define spu_context_trace(name, ctx, spu) \
+        trace_spufs_context(ctx, spu, __stringify(name))
+#define spu_context_nospu_trace(name, ctx) \
+        trace_spufs_context(ctx, NULL, __stringify(name))
+
+#endif /* _TRACE_SPUFS_H */
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE sputrace
+#include <trace/define_trace.h>
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 2f581521eb9b..5369653dcf6a 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -47,7 +47,7 @@ system_reset_iSeries:
         LOAD_REG_ADDR(r13, paca)
         mulli   r0,r23,PACA_SIZE
         add     r13,r13,r0
-        mtspr   SPRN_SPRG3,r13          /* Save it away for the future */
+        mtspr   SPRN_SPRG_PACA,r13      /* Save it away for the future */
         mfmsr   r24
         ori     r24,r24,MSR_RI
         mtmsrd  r24                     /* RI on */
@@ -116,7 +116,7 @@ iSeries_secondary_smp_loop:
 #endif /* CONFIG_SMP */
         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
         sc                              /* Invoke the hypervisor via a system call */
-        mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
+        mfspr   r13,SPRN_SPRG_PACA      /* Put r13 back ???? */
         b       2b                      /* If SMP not configured, secondaries
                                          * loop forever */
 
@@ -126,34 +126,45 @@ iSeries_secondary_smp_loop:
 
         .globl data_access_iSeries
 data_access_iSeries:
-        mtspr   SPRN_SPRG1,r13
+        mtspr   SPRN_SPRG_SCRATCH0,r13
 BEGIN_FTR_SECTION
-        mtspr   SPRN_SPRG2,r12
-        mfspr   r13,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        srdi    r13,r13,60
-        rlwimi  r13,r12,16,0x20
-        mfcr    r12
-        cmpwi   r13,0x2c
+        mfspr   r13,SPRN_SPRG_PACA
+        std     r9,PACA_EXSLB+EX_R9(r13)
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        mfspr   r10,SPRN_DAR
+        mfspr   r9,SPRN_DSISR
+        srdi    r10,r10,60
+        rlwimi  r10,r9,16,0x20
+        mfcr    r9
+        cmpwi   r10,0x2c
         beq     .do_stab_bolted_iSeries
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        ld      r11,PACA_EXSLB+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r12,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R13(r13)
+        EXCEPTION_PROLOG_ISERIES_1
+FTR_SECTION_ELSE
         EXCEPTION_PROLOG_1(PACA_EXGEN)
         EXCEPTION_PROLOG_ISERIES_1
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
         b       data_access_common
 
 .do_stab_bolted_iSeries:
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-        EXCEPTION_PROLOG_1(PACA_EXSLB)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXSLB+EX_R13(r13)
         EXCEPTION_PROLOG_ISERIES_1
         b       .do_stab_bolted
 
         .globl  data_access_slb_iSeries
 data_access_slb_iSeries:
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
+        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_DAR
         std     r9,PACA_EXSLB+EX_R9(r13)
@@ -165,7 +176,7 @@ data_access_slb_iSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         ld      r12,PACALPPACAPTR(r13)
         ld      r12,LPPACASRR1(r12)
@@ -175,8 +186,8 @@ data_access_slb_iSeries:
 
         .globl  instruction_access_slb_iSeries
 instruction_access_slb_iSeries:
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
+        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         ld      r3,PACALPPACAPTR(r13)
         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
@@ -189,7 +200,7 @@ instruction_access_slb_iSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         ld      r12,PACALPPACAPTR(r13)
         ld      r12,LPPACASRR1(r12)
@@ -200,7 +211,7 @@ slb_miss_user_iseries:
         std     r10,PACA_EXGEN+EX_R10(r13)
         std     r11,PACA_EXGEN+EX_R11(r13)
         std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG1
+        mfspr   r10,SPRG_SCRATCH0
         ld      r11,PACA_EXSLB+EX_R9(r13)
         ld      r12,PACA_EXSLB+EX_R3(r13)
         std     r10,PACA_EXGEN+EX_R13(r13)
@@ -221,7 +232,7 @@ slb_miss_user_iseries:
         .globl  system_call_iSeries
 system_call_iSeries:
         mr      r9,r13
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
         EXCEPTION_PROLOG_ISERIES_1
         b       system_call_common
 
diff --git a/arch/powerpc/platforms/iseries/exception.h b/arch/powerpc/platforms/iseries/exception.h
index ced45a8fa1aa..bae3fba5ad8e 100644
--- a/arch/powerpc/platforms/iseries/exception.h
+++ b/arch/powerpc/platforms/iseries/exception.h
@@ -24,7 +24,7 @@
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  */
-#include <asm/exception.h>
+#include <asm/exception-64s.h>
 
 #define EXCEPTION_PROLOG_ISERIES_1                                      \
         mfmsr   r10;                                                    \
@@ -38,7 +38,7 @@
         .globl label##_iSeries;                                         \
 label##_iSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
         EXCEPTION_PROLOG_1(area);                                       \
         EXCEPTION_PROLOG_ISERIES_1;                                     \
         b       label##_common
@@ -47,7 +47,7 @@ label##_iSeries:							\
         .globl label##_iSeries;                                         \
 label##_iSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
         EXCEPTION_PROLOG_1(PACA_EXGEN);                                 \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         cmpwi   0,r10,0;                                                \
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index fef4d5150517..0d9343df35bc 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -872,7 +872,7 @@ static int proc_mf_dump_cmdline(char *page, char **start, off_t off,
                 count = 256 - off;
 
         dma_addr = iseries_hv_map(page, off + count, DMA_FROM_DEVICE);
-        if (dma_mapping_error(NULL, dma_addr))
+        if (dma_addr == DMA_ERROR_CODE)
                 return -ENOMEM;
         memset(page, 0, off + count);
         memset(&vsp_cmd, 0, sizeof(vsp_cmd));
diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c
index 43911d8b0206..75b296bc51af 100644
--- a/arch/powerpc/platforms/pasemi/idle.c
+++ b/arch/powerpc/platforms/pasemi/idle.c
@@ -90,7 +90,7 @@ machine_late_initcall(pasemi, pasemi_idle_init);
 static int __init idle_param(char *p)
 {
         int i;
-        for (i = 0; i < sizeof(modes)/sizeof(struct sleep_mode); i++) {
+        for (i = 0; i < ARRAY_SIZE(modes); i++) {
                 if (!strcmp(modes[i].name, p)) {
                         current_mode = i;
                         break;
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 65c585b8b00d..08d94e4cedd3 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -44,14 +44,6 @@
  */
 #undef DEBUG_FREQ
 
-/*
- * There is a problem with the core cpufreq code on SMP kernels,
- * it won't recalculate the Bogomips properly
- */
-#ifdef CONFIG_SMP
-#warning "WARNING, CPUFREQ not recommended on SMP kernels"
-#endif
-
 extern void low_choose_7447a_dfs(int dfs);
 extern void low_choose_750fx_pll(int pll);
 extern void low_sleep_handler(void);
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index e6c0040ee797..fbc9bbd74dbd 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -2419,13 +2419,13 @@ static int __init probe_motherboard(void)
         dt = of_find_node_by_name(NULL, "device-tree");
         if (dt != NULL)
                 model = of_get_property(dt, "model", NULL);
-        for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
+        for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) {
             if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
                 pmac_mb = pmac_mb_defs[i];
                 goto found;
             }
         }
-        for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
+        for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
             if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
                 pmac_mb = pmac_mb_defs[i];
                 goto found;
@@ -2589,9 +2589,16 @@ static void __init probe_uninorth(void)
         if (address == 0)
                 return;
         uninorth_base = ioremap(address, 0x40000);
+        if (uninorth_base == NULL)
+                return;
         uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
-        if (uninorth_maj == 3 || uninorth_maj == 4)
+        if (uninorth_maj == 3 || uninorth_maj == 4) {
                 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
+                if (u3_ht_base == NULL) {
+                        iounmap(uninorth_base);
+                        return;
+                }
+        }
 
         printk(KERN_INFO "Found %s memory controller & host bridge"
                " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 04cdd32624d4..e81403b245b5 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -1286,3 +1286,64 @@ static void fixup_k2_sata(struct pci_dev* dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
 
+/*
+ * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
+ * configured by the firmware. The bridge itself seems to ignore them but it
+ * causes problems with Linux which then re-assigns devices below the bridge,
+ * thus changing addresses of those devices from what was in the device-tree,
+ * which sucks when those are video cards using offb
+ *
+ * We could just mark it transparent but I prefer fixing up the resources to
+ * properly show what's going on here, as I have some doubts about having them
+ * badly configured potentially being an issue for DMA.
+ *
+ * We leave PIO alone, it seems to be fine
+ *
+ * Oh and there's another funny bug. The OF properties advertize the region
+ * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
+ * actually not true, this region is the memory mapped config space. So we
+ * also need to filter it out or we'll map things in the wrong place.
+ */
+static void fixup_u4_pcie(struct pci_dev* dev)
+{
+        struct pci_controller *host = pci_bus_to_host(dev->bus);
+        struct resource *region = NULL;
+        u32 reg;
+        int i;
+
+        /* Only do that on PowerMac */
+        if (!machine_is(powermac))
+                return;
+
+        /* Find the largest MMIO region */
+        for (i = 0; i < 3; i++) {
+                struct resource *r = &host->mem_resources[i];
+                if (!(r->flags & IORESOURCE_MEM))
+                        continue;
+                /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
+                 * are reserved by HW for other things
+                 */
+                if (r->start >= 0xf0000000 && r->start < 0xf3000000)
+                        continue;
+                if (!region || (r->end - r->start) >
+                    (region->end - region->start))
+                        region = r;
+        }
+        /* Nothing found, bail */
+        if (region == 0)
+                return;
+
+        /* Print things out */
+        printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
+
+        /* Fixup bridge config space. We know it's a Mac, resource aren't
+         * offset so let's just blast them as-is. We also know that they
+         * fit in 32 bits
+         */
+        reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
+        pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
+        pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
+        pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
+        pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 6d4da7b46b41..937a38e73178 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -408,7 +408,7 @@ static void __init smp_psurge_setup_cpu(int cpu_nr)
         /* reset the entry point so if we get another intr we won't
          * try to startup again */
         out_be32(psurge_start, 0x100);
-        if (setup_irq(30, &psurge_irqaction))
+        if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 }
 
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 846eb8b57fd1..189a25b80735 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -23,8 +23,8 @@
 #include <linux/memory_hotplug.h>
 #include <linux/lmb.h>
 
+#include <asm/cell-regs.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 3f763c5284ac..e34b305a7a52 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -27,7 +27,7 @@
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
+#include <asm/cell-regs.h>
 
 #include "platform.h"
 
@@ -694,7 +694,7 @@ static int ps3_dma_supported(struct device *_dev, u64 mask)
         return mask >= DMA_BIT_MASK(32);
 }
 
-static struct dma_mapping_ops ps3_sb_dma_ops = {
+static struct dma_map_ops ps3_sb_dma_ops = {
         .alloc_coherent = ps3_alloc_coherent,
         .free_coherent = ps3_free_coherent,
         .map_sg = ps3_sb_map_sg,
@@ -704,7 +704,7 @@ static struct dma_mapping_ops ps3_sb_dma_ops = {
         .unmap_page = ps3_unmap_page,
 };
 
-static struct dma_mapping_ops ps3_ioc0_dma_ops = {
+static struct dma_map_ops ps3_ioc0_dma_ops = {
         .alloc_coherent = ps3_alloc_coherent,
         .free_coherent = ps3_free_coherent,
         .map_sg = ps3_ioc0_map_sg,
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index ad152a0e3946..b6fa3e4b51b5 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -151,7 +151,7 @@ struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn)
         if (dn->child)
                 eeh_add_device_tree_early(dn);
 
-        scan_phb(phb);
+        pcibios_scan_phb(phb, dn);
         pcibios_finish_adding_to_bus(phb->bus);
 
         return phb;
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index b6f1b137d427..2e2bbe120b90 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -20,6 +20,7 @@
 #include <asm/machdep.h>
 #include <asm/uaccess.h>
 #include <asm/pSeries_reconfig.h>
+#include <asm/mmu.h>
 
 
 
@@ -439,9 +440,15 @@ static int do_update_property(char *buf, size_t bufsize)
         if (!newprop)
                 return -ENOMEM;
 
+        if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size"))
+                slb_set_size(*(int *)value);
+
         oldprop = of_find_property(np, name,NULL);
-        if (!oldprop)
+        if (!oldprop) {
+                if (strlen(name))
+                        return prom_add_property(np, newprop);
                 return -ENODEV;
+        }
 
         rc = prom_update_property(np, newprop, oldprop);
         if (rc)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 8d75ea21296f..ca5f2e10972c 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -223,10 +223,6 @@ static void pseries_lpar_enable_pmcs(void)
         set = 1UL << 63;
         reset = 0;
         plpar_hcall_norets(H_PERFMON, set, reset);
-
-        /* instruct hypervisor to maintain PMCs */
-        if (firmware_has_feature(FW_FEATURE_SPLPAR))
-                get_lppaca()->pmcregs_in_use = 1;
 }
 
 static void __init pseries_discover_pic(void)
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 1f8f6cfb94f7..440000cc7130 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -56,8 +56,6 @@
  */
 static cpumask_t of_spin_map;
 
-extern void generic_secondary_smp_init(unsigned long);
-
 /**
  * smp_startup_cpu() - start the given cpu
  *
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cbb3bed75d3c..757a83fe5e59 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1057,6 +1057,10 @@ int fsl_rio_setup(struct of_device *dev)
                         law_start, law_size);
 
         ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
+        if (!ops) {
+                rc = -ENOMEM;
+                goto err_ops;
+        }
         ops->lcread = fsl_local_config_read;
         ops->lcwrite = fsl_local_config_write;
         ops->cread = fsl_rio_config_read;
@@ -1064,6 +1068,10 @@ int fsl_rio_setup(struct of_device *dev)
         ops->dsend = fsl_rio_doorbell_send;
 
         port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+        if (!port) {
+                rc = -ENOMEM;
+                goto err_port;
+        }
         port->id = 0;
         port->index = 0;
 
@@ -1071,7 +1079,7 @@ int fsl_rio_setup(struct of_device *dev)
         if (!priv) {
                 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
                 rc = -ENOMEM;
-                goto err;
+                goto err_priv;
         }
 
         INIT_LIST_HEAD(&port->dbells);
@@ -1169,11 +1177,13 @@ int fsl_rio_setup(struct of_device *dev)
 
         return 0;
 err:
-        if (priv)
-                iounmap(priv->regs_win);
-        kfree(ops);
+        iounmap(priv->regs_win);
         kfree(priv);
+err_priv:
         kfree(port);
+err_port:
+        kfree(ops);
+err_ops:
         return rc;
 }
 
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 95dbc643c4fc..adca4affcf1f 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -37,6 +37,7 @@
 #include <asm/irq.h>
 #include <asm/time.h>
 #include <asm/prom.h>
+#include <asm/machdep.h>
 #include <sysdev/fsl_soc.h>
 #include <mm/mmu_decl.h>
 #include <asm/cpm2.h>
@@ -383,8 +384,9 @@ static int __init setup_rstcr(void)
                 if (!rstcr)
                         printk (KERN_EMERG "Error: reset control register "
                                         "not mapped!\n");
-        } else
-                printk (KERN_INFO "rstcr compatible register does not exist!\n");
+        } else if (ppc_md.restart == fsl_rstcr_restart)
+                printk(KERN_ERR "No RSTCR register, warm reboot won't work\n");
+
         if (np)
                 of_node_put(np);
         return 0;
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 69e2630c9062..cb7689c4bfbd 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -735,8 +735,10 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
         ipic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
                                        NR_IPIC_INTS,
                                        &ipic_host_ops, 0);
-        if (ipic->irqhost == NULL)
+        if (ipic->irqhost == NULL) {
+                kfree(ipic);
                 return NULL;
+        }
 
         ipic->regs = ioremap(res.start, res.end - res.start + 1);
 
@@ -781,6 +783,9 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
         primary_ipic = ipic;
         irq_set_default_host(primary_ipic->irqhost);
 
+        ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
+        ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
+
         printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
                         primary_ipic->regs);
 
diff --git a/arch/powerpc/sysdev/mmio_nvram.c b/arch/powerpc/sysdev/mmio_nvram.c
index 7b49633a4bd0..207324209065 100644
--- a/arch/powerpc/sysdev/mmio_nvram.c
+++ b/arch/powerpc/sysdev/mmio_nvram.c
@@ -53,6 +53,23 @@ static ssize_t mmio_nvram_read(char *buf, size_t count, loff_t *index)
         return count;
 }
 
+static unsigned char mmio_nvram_read_val(int addr)
+{
+        unsigned long flags;
+        unsigned char val;
+
+        if (addr >= mmio_nvram_len)
+                return 0xff;
+
+        spin_lock_irqsave(&mmio_nvram_lock, flags);
+
+        val = ioread8(mmio_nvram_start + addr);
+
+        spin_unlock_irqrestore(&mmio_nvram_lock, flags);
+
+        return val;
+}
+
 static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
 {
         unsigned long flags;
@@ -72,6 +89,19 @@ static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
         return count;
 }
 
+void mmio_nvram_write_val(int addr, unsigned char val)
+{
+        unsigned long flags;
+
+        if (addr < mmio_nvram_len) {
+                spin_lock_irqsave(&mmio_nvram_lock, flags);
+
+                iowrite8(val, mmio_nvram_start + addr);
+
+                spin_unlock_irqrestore(&mmio_nvram_lock, flags);
+        }
+}
+
 static ssize_t mmio_nvram_get_size(void)
 {
         return mmio_nvram_len;
@@ -114,6 +144,8 @@ int __init mmio_nvram_init(void)
         printk(KERN_INFO "mmio NVRAM, %luk at 0x%lx mapped to %p\n",
                mmio_nvram_len >> 10, nvram_addr, mmio_nvram_start);
 
+        ppc_md.nvram_read_val   = mmio_nvram_read_val;
+        ppc_md.nvram_write_val  = mmio_nvram_write_val;
         ppc_md.nvram_read       = mmio_nvram_read;
         ppc_md.nvram_write      = mmio_nvram_write;
         ppc_md.nvram_size       = mmio_nvram_get_size;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 3981ae4cb58e..30c44e6b0413 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -230,14 +230,16 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
 {
         unsigned int    isu = src_no >> mpic->isu_shift;
         unsigned int    idx = src_no & mpic->isu_mask;
+        unsigned int    val;
 
+        val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
+                         reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
         if (reg == 0)
-                return mpic->isu_reg0_shadow[idx];
-        else
+                val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
+                        mpic->isu_reg0_shadow[src_no];
 #endif
-                return _mpic_read(mpic->reg_type, &mpic->isus[isu],
-                                  reg + (idx * MPIC_INFO(IRQ_STRIDE)));
+        return val;
 }
 
 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -251,7 +253,8 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
         if (reg == 0)
-                mpic->isu_reg0_shadow[idx] = value;
+                mpic->isu_reg0_shadow[src_no] =
+                        value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 #endif
 }
 
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index 3485288dce31..8e7a7767dd5c 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -105,14 +105,14 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
         unsigned long flags;
 
+        qe_gpio_set(gc, gpio, val);
+
         spin_lock_irqsave(&qe_gc->lock, flags);
 
         __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
 
         spin_unlock_irqrestore(&qe_gc->lock, flags);
 
-        qe_gpio_set(gc, gpio, val);
-
         return 0;
 }
 
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 074905c3ee5a..3faa42e03a85 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -339,8 +339,10 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
 
         qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
                                         NR_QE_IC_INTS, &qe_ic_host_ops, 0);
-        if (qe_ic->irqhost == NULL)
+        if (qe_ic->irqhost == NULL) {
+                kfree(qe_ic);
                 return;
+        }
 
         qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
 
@@ -352,6 +354,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
 
         if (qe_ic->virq_low == NO_IRQ) {
                 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
+                kfree(qe_ic);
                 return;
         }
 
diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
index 85ab97ab840a..faa81b6a6612 100644
--- a/arch/powerpc/xmon/Makefile
+++ b/arch/powerpc/xmon/Makefile
@@ -2,6 +2,8 @@
 
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
+GCOV_PROFILE := n
+
 ifdef CONFIG_PPC64
 EXTRA_CFLAGS += -mno-minimal-toc
 endif
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index e1f33a81e5e1..0e09a45ac79a 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2570,7 +2570,7 @@ static void xmon_print_symbol(unsigned long address, const char *mid,
         printf("%s", after);
 }
 
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 static void dump_slb(void)
 {
         int i;