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authorScott Wood <scottwood@freescale.com>2007-07-16 12:28:18 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-10-03 21:36:35 -0400
commitccf0d68e835003f19d5a9463d5a8c1e092d3a31a (patch)
treec604aa02660434e15c20b138dcbd175eae0f0196 /arch/powerpc
parentd948a29ea7a9514f588dafb61d5a6da68131c3ba (diff)
[POWERPC] 8xx: Fix CONFIG_PIN_TLB.
1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig1
-rw-r--r--arch/powerpc/kernel/head_8xx.S4
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b387e1ed5177..37ff383393bd 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -600,6 +600,7 @@ config CONSISTENT_START_BOOL
600 600
601config CONSISTENT_START 601config CONSISTENT_START
602 hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL 602 hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
603 default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
603 default "0xff100000" if NOT_COHERENT_CACHE 604 default "0xff100000" if NOT_COHERENT_CACHE
604 605
605config CONSISTENT_SIZE_BOOL 606config CONSISTENT_SIZE_BOOL
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 96cea8e753c4..9c30938aad52 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -727,13 +727,13 @@ initial_mmu:
727 mtspr SPRN_MD_TWC, r9 727 mtspr SPRN_MD_TWC, r9
728 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 728 li r11, MI_BOOTINIT /* Create RPN for address 0 */
729 addis r11, r11, 0x0080 /* Add 8M */ 729 addis r11, r11, 0x0080 /* Add 8M */
730 mtspr SPRN_MD_RPN, r8 730 mtspr SPRN_MD_RPN, r11
731 731
732 addis r8, r8, 0x0080 /* Add 8M */ 732 addis r8, r8, 0x0080 /* Add 8M */
733 mtspr SPRN_MD_EPN, r8 733 mtspr SPRN_MD_EPN, r8
734 mtspr SPRN_MD_TWC, r9 734 mtspr SPRN_MD_TWC, r9
735 addis r11, r11, 0x0080 /* Add 8M */ 735 addis r11, r11, 0x0080 /* Add 8M */
736 mtspr SPRN_MD_RPN, r8 736 mtspr SPRN_MD_RPN, r11
737#endif 737#endif
738 738
739 /* Since the cache is enabled according to the information we 739 /* Since the cache is enabled according to the information we