diff options
author | LEROY Christophe <christophe.leroy@c-s.fr> | 2013-11-22 11:57:31 -0500 |
---|---|---|
committer | Scott Wood <scottwood@freescale.com> | 2013-11-22 17:56:48 -0500 |
commit | ae2163be10ac6090e7aeed72591e2d7fabb1cdda (patch) | |
tree | 1f6f4ba3beb2358c53bb951e3002c83de824163d /arch/powerpc | |
parent | cbf8a358be27ceecea5bd44cf82ab01683fcc90c (diff) |
powerpc/8xx: mfspr SPRN_TBRx in lieu of mftb/mftbu is not supported
Commit beb2dc0a7a84be003ce54e98b95d65cc66e6e536 breaks the MPC8xx which
seems to not support using mfspr SPRN_TBRx instead of mftb/mftbu
despite what is written in the reference manual.
This patch reverts to the use of mftb/mftbu when CONFIG_8xx is
selected.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/boot/util.S | 14 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc_asm.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 7 | ||||
-rw-r--r-- | arch/powerpc/include/asm/timex.h | 8 | ||||
-rw-r--r-- | arch/powerpc/kernel/vdso32/gettimeofday.S | 6 |
5 files changed, 37 insertions, 0 deletions
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S index 5143228e3e5f..6636b1d7821b 100644 --- a/arch/powerpc/boot/util.S +++ b/arch/powerpc/boot/util.S | |||
@@ -71,18 +71,32 @@ udelay: | |||
71 | add r4,r4,r5 | 71 | add r4,r4,r5 |
72 | addi r4,r4,-1 | 72 | addi r4,r4,-1 |
73 | divw r4,r4,r5 /* BUS ticks */ | 73 | divw r4,r4,r5 /* BUS ticks */ |
74 | #ifdef CONFIG_8xx | ||
75 | 1: mftbu r5 | ||
76 | mftb r6 | ||
77 | mftbu r7 | ||
78 | #else | ||
74 | 1: mfspr r5, SPRN_TBRU | 79 | 1: mfspr r5, SPRN_TBRU |
75 | mfspr r6, SPRN_TBRL | 80 | mfspr r6, SPRN_TBRL |
76 | mfspr r7, SPRN_TBRU | 81 | mfspr r7, SPRN_TBRU |
82 | #endif | ||
77 | cmpw 0,r5,r7 | 83 | cmpw 0,r5,r7 |
78 | bne 1b /* Get [synced] base time */ | 84 | bne 1b /* Get [synced] base time */ |
79 | addc r9,r6,r4 /* Compute end time */ | 85 | addc r9,r6,r4 /* Compute end time */ |
80 | addze r8,r5 | 86 | addze r8,r5 |
87 | #ifdef CONFIG_8xx | ||
88 | 2: mftbu r5 | ||
89 | #else | ||
81 | 2: mfspr r5, SPRN_TBRU | 90 | 2: mfspr r5, SPRN_TBRU |
91 | #endif | ||
82 | cmpw 0,r5,r8 | 92 | cmpw 0,r5,r8 |
83 | blt 2b | 93 | blt 2b |
84 | bgt 3f | 94 | bgt 3f |
95 | #ifdef CONFIG_8xx | ||
96 | mftb r6 | ||
97 | #else | ||
85 | mfspr r6, SPRN_TBRL | 98 | mfspr r6, SPRN_TBRL |
99 | #endif | ||
86 | cmpw 0,r6,r9 | 100 | cmpw 0,r6,r9 |
87 | blt 2b | 101 | blt 2b |
88 | 3: blr | 102 | 3: blr |
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 3c1acc31a092..f595b98079ee 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h | |||
@@ -366,6 +366,8 @@ BEGIN_FTR_SECTION_NESTED(96); \ | |||
366 | cmpwi dest,0; \ | 366 | cmpwi dest,0; \ |
367 | beq- 90b; \ | 367 | beq- 90b; \ |
368 | END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) | 368 | END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) |
369 | #elif defined(CONFIG_8xx) | ||
370 | #define MFTB(dest) mftb dest | ||
369 | #else | 371 | #else |
370 | #define MFTB(dest) mfspr dest, SPRN_TBRL | 372 | #define MFTB(dest) mfspr dest, SPRN_TBRL |
371 | #endif | 373 | #endif |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 5c45787d551e..fa8388ed94c5 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -1174,12 +1174,19 @@ | |||
1174 | 1174 | ||
1175 | #else /* __powerpc64__ */ | 1175 | #else /* __powerpc64__ */ |
1176 | 1176 | ||
1177 | #if defined(CONFIG_8xx) | ||
1178 | #define mftbl() ({unsigned long rval; \ | ||
1179 | asm volatile("mftbl %0" : "=r" (rval)); rval;}) | ||
1180 | #define mftbu() ({unsigned long rval; \ | ||
1181 | asm volatile("mftbu %0" : "=r" (rval)); rval;}) | ||
1182 | #else | ||
1177 | #define mftbl() ({unsigned long rval; \ | 1183 | #define mftbl() ({unsigned long rval; \ |
1178 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ | 1184 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1179 | "i" (SPRN_TBRL)); rval;}) | 1185 | "i" (SPRN_TBRL)); rval;}) |
1180 | #define mftbu() ({unsigned long rval; \ | 1186 | #define mftbu() ({unsigned long rval; \ |
1181 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ | 1187 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1182 | "i" (SPRN_TBRU)); rval;}) | 1188 | "i" (SPRN_TBRU)); rval;}) |
1189 | #endif | ||
1183 | #endif /* !__powerpc64__ */ | 1190 | #endif /* !__powerpc64__ */ |
1184 | 1191 | ||
1185 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) | 1192 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) |
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h index 18908caa1f3b..2cf846edb3fc 100644 --- a/arch/powerpc/include/asm/timex.h +++ b/arch/powerpc/include/asm/timex.h | |||
@@ -29,7 +29,11 @@ static inline cycles_t get_cycles(void) | |||
29 | ret = 0; | 29 | ret = 0; |
30 | 30 | ||
31 | __asm__ __volatile__( | 31 | __asm__ __volatile__( |
32 | #ifdef CONFIG_8xx | ||
33 | "97: mftb %0\n" | ||
34 | #else | ||
32 | "97: mfspr %0, %2\n" | 35 | "97: mfspr %0, %2\n" |
36 | #endif | ||
33 | "99:\n" | 37 | "99:\n" |
34 | ".section __ftr_fixup,\"a\"\n" | 38 | ".section __ftr_fixup,\"a\"\n" |
35 | ".align 2\n" | 39 | ".align 2\n" |
@@ -41,7 +45,11 @@ static inline cycles_t get_cycles(void) | |||
41 | " .long 0\n" | 45 | " .long 0\n" |
42 | " .long 0\n" | 46 | " .long 0\n" |
43 | ".previous" | 47 | ".previous" |
48 | #ifdef CONFIG_8xx | ||
49 | : "=r" (ret) : "i" (CPU_FTR_601)); | ||
50 | #else | ||
44 | : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); | 51 | : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); |
52 | #endif | ||
45 | return ret; | 53 | return ret; |
46 | #endif | 54 | #endif |
47 | } | 55 | } |
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S index 6b1f2a6d5517..6b2b69616e77 100644 --- a/arch/powerpc/kernel/vdso32/gettimeofday.S +++ b/arch/powerpc/kernel/vdso32/gettimeofday.S | |||
@@ -232,9 +232,15 @@ __do_get_tspec: | |||
232 | lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) | 232 | lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) |
233 | 233 | ||
234 | /* Get a stable TB value */ | 234 | /* Get a stable TB value */ |
235 | #ifdef CONFIG_8xx | ||
236 | 2: mftbu r3 | ||
237 | mftbl r4 | ||
238 | mftbu r0 | ||
239 | #else | ||
235 | 2: mfspr r3, SPRN_TBRU | 240 | 2: mfspr r3, SPRN_TBRU |
236 | mfspr r4, SPRN_TBRL | 241 | mfspr r4, SPRN_TBRL |
237 | mfspr r0, SPRN_TBRU | 242 | mfspr r0, SPRN_TBRU |
243 | #endif | ||
238 | cmplw cr0,r3,r0 | 244 | cmplw cr0,r3,r0 |
239 | bne- 2b | 245 | bne- 2b |
240 | 246 | ||