diff options
author | Zang Roy-r61911 <tie-fei.zang@freescale.com> | 2007-07-10 06:46:35 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-07-23 11:27:07 -0400 |
commit | 9ac4dd301eebb3cd8de801e02bfc91f296e56f63 (patch) | |
tree | 9f4dbb37dc809c94156151f997093ac00a38b928 /arch/powerpc | |
parent | 55c44991e2910519bab274c857d95a08100ff5f7 (diff) |
[POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx
Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and
PCIe on 85xx/86xx.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8641_hpcn.dts | 8 | ||||
-rw-r--r-- | arch/powerpc/platforms/86xx/mpc86xx.h | 5 | ||||
-rw-r--r-- | arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 11 | ||||
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.c | 244 | ||||
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 145 |
5 files changed, 187 insertions, 226 deletions
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 6a78a2b37c08..5d82709cfcbb 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts | |||
@@ -211,8 +211,8 @@ | |||
211 | interrupt-parent = <&mpic>; | 211 | interrupt-parent = <&mpic>; |
212 | }; | 212 | }; |
213 | 213 | ||
214 | pci@8000 { | 214 | pcie@8000 { |
215 | compatible = "86xx"; | 215 | compatible = "fsl,mpc8641-pcie"; |
216 | device_type = "pci"; | 216 | device_type = "pci"; |
217 | #interrupt-cells = <1>; | 217 | #interrupt-cells = <1>; |
218 | #size-cells = <2>; | 218 | #size-cells = <2>; |
@@ -399,8 +399,8 @@ | |||
399 | 399 | ||
400 | }; | 400 | }; |
401 | 401 | ||
402 | pci@9000 { | 402 | pcie@9000 { |
403 | compatible = "86xx"; | 403 | compatible = "fsl,mpc8641-pcie"; |
404 | device_type = "pci"; | 404 | device_type = "pci"; |
405 | #interrupt-cells = <1>; | 405 | #interrupt-cells = <1>; |
406 | #size-cells = <2>; | 406 | #size-cells = <2>; |
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h index 23f7ed2a7f88..525ffa1904f9 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx.h +++ b/arch/powerpc/platforms/86xx/mpc86xx.h | |||
@@ -15,11 +15,6 @@ | |||
15 | * mpc86xx_* files. Mostly for use by mpc86xx_setup(). | 15 | * mpc86xx_* files. Mostly for use by mpc86xx_setup(). |
16 | */ | 16 | */ |
17 | 17 | ||
18 | extern int mpc86xx_add_bridge(struct device_node *dev); | ||
19 | |||
20 | extern int mpc86xx_exclude_device(struct pci_controller *hose, | ||
21 | u_char bus, u_char devfn); | ||
22 | |||
23 | extern void __init mpc86xx_smp_init(void); | 18 | extern void __init mpc86xx_smp_init(void); |
24 | 19 | ||
25 | #endif /* __MPC86XX_H__ */ | 20 | #endif /* __MPC86XX_H__ */ |
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index 5b01ec7c13dc..e67e10d3272f 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include <asm/mpic.h> | 32 | #include <asm/mpic.h> |
33 | 33 | ||
34 | #include <sysdev/fsl_pci.h> | ||
34 | #include <sysdev/fsl_soc.h> | 35 | #include <sysdev/fsl_soc.h> |
35 | 36 | ||
36 | #include "mpc86xx.h" | 37 | #include "mpc86xx.h" |
@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void) | |||
344 | } | 345 | } |
345 | 346 | ||
346 | #ifdef CONFIG_PCI | 347 | #ifdef CONFIG_PCI |
347 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) | 348 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { |
348 | mpc86xx_add_bridge(np); | 349 | struct resource rsrc; |
350 | of_address_to_resource(np, 0, &rsrc); | ||
351 | if ((rsrc.start & 0xfffff) == 0x8000) | ||
352 | fsl_add_bridge(np, 1); | ||
353 | else | ||
354 | fsl_add_bridge(np, 0); | ||
355 | } | ||
349 | #endif | 356 | #endif |
350 | 357 | ||
351 | printk("MPC86xx HPCN board from Freescale Semiconductor\n"); | 358 | printk("MPC86xx HPCN board from Freescale Semiconductor\n"); |
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 24ba1b6b31fb..10c47b56702e 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
@@ -1,136 +1,98 @@ | |||
1 | /* | 1 | /* |
2 | * MPC86XX pci setup code | 2 | * MPC85xx/86xx PCI/PCIE support routing. |
3 | * | 3 | * |
4 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | 4 | * Copyright 2007 Freescale Semiconductor, Inc |
5 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> | ||
6 | * | 5 | * |
7 | * Copyright 2006 Freescale Semiconductor Inc. | 6 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
7 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | ||
8 | * Rewrite the routing for Frescale PCI and PCI Express | ||
9 | * Roy Zang <tie-fei.zang@freescale.com> | ||
8 | * | 10 | * |
9 | * This program is free software; you can redistribute it and/or modify it | 11 | * This program is free software; you can redistribute it and/or modify it |
10 | * under the terms of the GNU General Public License as published by the | 12 | * under the terms of the GNU General Public License as published by the |
11 | * Free Software Foundation; either version 2 of the License, or (at your | 13 | * Free Software Foundation; either version 2 of the License, or (at your |
12 | * option) any later version. | 14 | * option) any later version. |
13 | */ | 15 | */ |
14 | 16 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/pci.h> | 17 | #include <linux/pci.h> |
19 | #include <linux/serial.h> | 18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/bootmem.h> | ||
20 | 22 | ||
21 | #include <asm/system.h> | ||
22 | #include <asm/atomic.h> | ||
23 | #include <asm/io.h> | 23 | #include <asm/io.h> |
24 | #include <asm/prom.h> | 24 | #include <asm/prom.h> |
25 | #include <asm/pci-bridge.h> | 25 | #include <asm/pci-bridge.h> |
26 | #include <asm/machdep.h> | ||
26 | #include <sysdev/fsl_soc.h> | 27 | #include <sysdev/fsl_soc.h> |
27 | #include <sysdev/fsl_pci.h> | 28 | #include <sysdev/fsl_pci.h> |
28 | 29 | ||
29 | #include "../platforms/86xx/mpc86xx.h" | 30 | /* atmu setup for fsl pci/pcie controller */ |
30 | 31 | void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) | |
31 | #undef DEBUG | ||
32 | |||
33 | #ifdef DEBUG | ||
34 | #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) | ||
35 | #else | ||
36 | #define DBG(fmt, args...) | ||
37 | #endif | ||
38 | |||
39 | struct pcie_outbound_window_regs { | ||
40 | uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ | ||
41 | uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ | ||
42 | uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ | ||
43 | char res1[4]; | ||
44 | uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ | ||
45 | char res2[12]; | ||
46 | }; | ||
47 | |||
48 | struct pcie_inbound_window_regs { | ||
49 | uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ | ||
50 | char res1[4]; | ||
51 | uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ | ||
52 | uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ | ||
53 | uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ | ||
54 | char res2[12]; | ||
55 | }; | ||
56 | |||
57 | static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) | ||
58 | { | 32 | { |
59 | volatile struct ccsr_pex *pcie; | 33 | struct ccsr_pci __iomem *pci; |
60 | volatile struct pcie_outbound_window_regs *pcieow; | 34 | int i; |
61 | volatile struct pcie_inbound_window_regs *pcieiw; | ||
62 | int i = 0; | ||
63 | 35 | ||
64 | DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, | 36 | pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, |
65 | rsrc->end - rsrc->start + 1); | 37 | rsrc->end - rsrc->start + 1); |
66 | pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); | 38 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); |
67 | 39 | ||
68 | /* Disable all windows (except pexowar0 since its ignored) */ | 40 | /* Disable all windows (except powar0 since its ignored) */ |
69 | pcie->pexowar1 = 0; | 41 | for(i = 1; i < 5; i++) |
70 | pcie->pexowar2 = 0; | 42 | out_be32(&pci->pow[i].powar, 0); |
71 | pcie->pexowar3 = 0; | 43 | for(i = 0; i < 3; i++) |
72 | pcie->pexowar4 = 0; | 44 | out_be32(&pci->piw[i].piwar, 0); |
73 | pcie->pexiwar1 = 0; | 45 | |
74 | pcie->pexiwar2 = 0; | 46 | /* Setup outbound MEM window */ |
75 | pcie->pexiwar3 = 0; | 47 | for(i = 0; i < 3; i++) |
76 | 48 | if (hose->mem_resources[i].flags & IORESOURCE_MEM){ | |
77 | pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; | 49 | pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", |
78 | pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; | 50 | hose->mem_resources[i].start, |
79 | 51 | hose->mem_resources[i].end | |
80 | /* Setup outbound MEM window */ | 52 | - hose->mem_resources[i].start + 1); |
81 | for(i = 0; i < 3; i++) | 53 | out_be32(&pci->pow[i+1].potar, |
82 | if (hose->mem_resources[i].flags & IORESOURCE_MEM){ | 54 | (hose->mem_resources[i].start >> 12) |
83 | DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", | 55 | & 0x000fffff); |
84 | hose->mem_resources[i].start, | 56 | out_be32(&pci->pow[i+1].potear, 0); |
85 | hose->mem_resources[i].end | 57 | out_be32(&pci->pow[i+1].powbar, |
86 | - hose->mem_resources[i].start + 1); | 58 | (hose->mem_resources[i].start >> 12) |
87 | pcieow->pexotar = (hose->mem_resources[i].start) >> 12 | 59 | & 0x000fffff); |
88 | & 0x000fffff; | 60 | /* Enable, Mem R/W */ |
89 | pcieow->pexotear = 0; | 61 | out_be32(&pci->pow[i+1].powar, 0x80044000 |
90 | pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 | 62 | | (__ilog2(hose->mem_resources[i].end |
91 | & 0x000fffff; | 63 | - hose->mem_resources[i].start + 1) - 1)); |
92 | /* Enable, Mem R/W */ | 64 | } |
93 | pcieow->pexowar = 0x80044000 | | 65 | |
94 | (__ilog2(hose->mem_resources[i].end | 66 | /* Setup outbound IO window */ |
95 | - hose->mem_resources[i].start + 1) | 67 | if (hose->io_resource.flags & IORESOURCE_IO){ |
96 | - 1); | 68 | pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", |
97 | pcieow++; | 69 | hose->io_resource.start, |
98 | } | 70 | hose->io_resource.end - hose->io_resource.start + 1, |
99 | 71 | hose->io_base_phys); | |
100 | /* Setup outbound IO window */ | 72 | out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) |
101 | if (hose->io_resource.flags & IORESOURCE_IO){ | 73 | & 0x000fffff); |
102 | DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", | 74 | out_be32(&pci->pow[i+1].potear, 0); |
103 | hose->io_resource.start, | 75 | out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) |
104 | hose->io_resource.end - hose->io_resource.start + 1, | 76 | & 0x000fffff); |
105 | hose->io_base_phys); | 77 | /* Enable, IO R/W */ |
106 | pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; | 78 | out_be32(&pci->pow[i+1].powar, 0x80088000 |
107 | pcieow->pexotear = 0; | 79 | | (__ilog2(hose->io_resource.end |
108 | pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; | 80 | - hose->io_resource.start + 1) - 1)); |
109 | /* Enable, IO R/W */ | 81 | } |
110 | pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end | 82 | |
111 | - hose->io_resource.start + 1) - 1); | 83 | /* Setup 2G inbound Memory Window @ 1 */ |
112 | } | 84 | out_be32(&pci->piw[2].pitar, 0x00000000); |
113 | 85 | out_be32(&pci->piw[2].piwbar,0x00000000); | |
114 | /* Setup 2G inbound Memory Window @ 0 */ | 86 | out_be32(&pci->piw[2].piwar, PIWAR_2G); |
115 | pcieiw->pexitar = 0x00000000; | ||
116 | pcieiw->pexiwbar = 0x00000000; | ||
117 | /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ | ||
118 | pcieiw->pexiwar = 0xa0f5501e; | ||
119 | } | 87 | } |
120 | 88 | ||
121 | static void __init | 89 | void __init setup_pci_cmd(struct pci_controller *hose) |
122 | mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) | ||
123 | { | 90 | { |
124 | u16 cmd; | 91 | u16 cmd; |
125 | |||
126 | DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", | ||
127 | pcie_offset, pcie_size); | ||
128 | |||
129 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); | 92 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
130 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | 93 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
131 | | PCI_COMMAND_IO; | 94 | | PCI_COMMAND_IO; |
132 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); | 95 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
133 | |||
134 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); | 96 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); |
135 | } | 97 | } |
136 | 98 | ||
@@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) | |||
167 | } | 129 | } |
168 | } | 130 | } |
169 | 131 | ||
132 | int __init fsl_pcie_check_link(struct pci_controller *hose) | ||
133 | { | ||
134 | u16 val; | ||
135 | early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); | ||
136 | if (val < PCIE_LTSSM_L0) | ||
137 | return 1; | ||
138 | return 0; | ||
139 | } | ||
170 | 140 | ||
171 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); | 141 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
172 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); | ||
173 | |||
174 | #define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */ | ||
175 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | ||
176 | |||
177 | int __init mpc86xx_add_bridge(struct device_node *dev) | ||
178 | { | 142 | { |
179 | int len; | 143 | int len; |
180 | struct pci_controller *hose; | 144 | struct pci_controller *hose; |
181 | struct resource rsrc; | 145 | struct resource rsrc; |
182 | const int *bus_range; | 146 | const int *bus_range; |
183 | int has_address = 0; | ||
184 | int primary = 0; | ||
185 | u16 val; | ||
186 | 147 | ||
187 | DBG("Adding PCIE host bridge %s\n", dev->full_name); | 148 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
188 | 149 | ||
189 | /* Fetch host bridge registers address */ | 150 | /* Fetch host bridge registers address */ |
190 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); | 151 | if (of_address_to_resource(dev, 0, &rsrc)) { |
152 | printk(KERN_WARNING "Can't get pci register base!"); | ||
153 | return -ENOMEM; | ||
154 | } | ||
191 | 155 | ||
192 | /* Get bus range if any */ | 156 | /* Get bus range if any */ |
193 | bus_range = of_get_property(dev, "bus-range", &len); | 157 | bus_range = of_get_property(dev, "bus-range", &len); |
194 | if (bus_range == NULL || len < 2 * sizeof(int)) | 158 | if (bus_range == NULL || len < 2 * sizeof(int)) |
195 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | 159 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
196 | " bus 0\n", dev->full_name); | 160 | " bus 0\n", dev->full_name); |
197 | 161 | ||
198 | pci_assign_all_buses = 1; | 162 | pci_assign_all_buses = 1; |
199 | hose = pcibios_alloc_controller(dev); | 163 | hose = pcibios_alloc_controller(dev); |
200 | if (!hose) | 164 | if (!hose) |
201 | return -ENOMEM; | 165 | return -ENOMEM; |
202 | 166 | ||
203 | hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | | ||
204 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; | ||
205 | |||
206 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | 167 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
207 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | 168 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
208 | 169 | ||
209 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); | 170 | /* check PCI express bridge */ |
210 | 171 | if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || | |
211 | /* Probe the hose link training status */ | 172 | of_device_is_compatible(dev, "fsl,mpc8641-pcie")) |
212 | early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); | 173 | hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | |
213 | if (val < PCIE_LTSSM_L0) | 174 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
214 | return -ENXIO; | ||
215 | 175 | ||
216 | /* Setup the PCIE host controller. */ | 176 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); |
217 | mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); | 177 | setup_pci_cmd(hose); |
218 | 178 | ||
219 | if ((rsrc.start & 0xfffff) == 0x8000) | 179 | /* check PCI express link status */ |
220 | primary = 1; | 180 | if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || |
181 | of_device_is_compatible(dev, "fsl,mpc8641-pcie")) | ||
182 | if (fsl_pcie_check_link(hose)) | ||
183 | return -ENXIO; | ||
221 | 184 | ||
222 | printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " | 185 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." |
223 | "Firmware bus number: %d->%d\n", | 186 | "Firmware bus number: %d->%d\n", |
224 | (unsigned long) rsrc.start, | 187 | (unsigned long long)rsrc.start, hose->first_busno, |
225 | hose->first_busno, hose->last_busno); | 188 | hose->last_busno); |
226 | 189 | ||
227 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | 190 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
228 | hose, hose->cfg_addr, hose->cfg_data); | 191 | hose, hose->cfg_addr, hose->cfg_data); |
229 | 192 | ||
230 | /* Interpret the "ranges" property */ | 193 | /* Interpret the "ranges" property */ |
231 | /* This also maps the I/O region and sets isa_io/mem_base */ | 194 | /* This also maps the I/O region and sets isa_io/mem_base */ |
232 | pci_process_bridge_OF_ranges(hose, dev, primary); | 195 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
233 | 196 | ||
234 | /* Setup PEX window registers */ | 197 | /* Setup PEX window registers */ |
235 | setup_pcie_atmu(hose, &rsrc); | 198 | setup_pci_atmu(hose, &rsrc); |
236 | 199 | ||
237 | return 0; | 200 | return 0; |
238 | } | 201 | } |
202 | |||
203 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); | ||
204 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); | ||
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 8d9779c84bea..700d47827994 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
@@ -11,84 +11,77 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #ifdef __KERNEL__ | 13 | #ifdef __KERNEL__ |
14 | #ifndef __POWERPC_FSL_PCIE_H | 14 | #ifndef __POWERPC_FSL_PCI_H |
15 | #define __POWERPC_FSL_PCIE_H | 15 | #define __POWERPC_FSL_PCI_H |
16 | 16 | ||
17 | /* PCIE Express IO block registers in 85xx/86xx */ | 17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ |
18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | ||
19 | #define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ | ||
18 | 20 | ||
19 | struct ccsr_pex { | 21 | /* PCI/PCI Express outbound window reg */ |
20 | __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */ | 22 | struct pci_outbound_window_regs { |
21 | __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */ | 23 | __be32 potar; /* 0x.0 - Outbound translation address register */ |
22 | u8 __iomem res1[4]; | 24 | __be32 potear; /* 0x.4 - Outbound translation extended address register */ |
23 | __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */ | 25 | __be32 powbar; /* 0x.8 - Outbound window base address register */ |
24 | __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */ | 26 | u8 res1[4]; |
25 | u8 __iomem res2[12]; | 27 | __be32 powar; /* 0x.10 - Outbound window attributes register */ |
26 | __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */ | 28 | u8 res2[12]; |
27 | __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */ | ||
28 | __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */ | ||
29 | __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */ | ||
30 | u8 __iomem res3[3024]; | ||
31 | __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */ | ||
32 | __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/ | ||
33 | u8 __iomem res4[8]; | ||
34 | __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/ | ||
35 | u8 __iomem res5[12]; | ||
36 | __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */ | ||
37 | __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/ | ||
38 | __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/ | ||
39 | u8 __iomem res6[4]; | ||
40 | __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/ | ||
41 | u8 __iomem res7[12]; | ||
42 | __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */ | ||
43 | __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/ | ||
44 | __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/ | ||
45 | u8 __iomem res8[4]; | ||
46 | __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/ | ||
47 | u8 __iomem res9[12]; | ||
48 | __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */ | ||
49 | __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/ | ||
50 | __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/ | ||
51 | u8 __iomem res10[4]; | ||
52 | __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/ | ||
53 | u8 __iomem res11[12]; | ||
54 | __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */ | ||
55 | __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/ | ||
56 | __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/ | ||
57 | u8 __iomem res12[4]; | ||
58 | __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/ | ||
59 | u8 __iomem res13[12]; | ||
60 | u8 __iomem res14[256]; | ||
61 | __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */ | ||
62 | u8 __iomem res15[4]; | ||
63 | __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */ | ||
64 | __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */ | ||
65 | __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */ | ||
66 | u8 __iomem res16[12]; | ||
67 | __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */ | ||
68 | u8 __iomem res17[4]; | ||
69 | __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */ | ||
70 | __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */ | ||
71 | __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */ | ||
72 | u8 __iomem res18[12]; | ||
73 | __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */ | ||
74 | u8 __iomem res19[4]; | ||
75 | __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */ | ||
76 | __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */ | ||
77 | __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */ | ||
78 | u8 __iomem res20[12]; | ||
79 | __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */ | ||
80 | u8 __iomem res21[4]; | ||
81 | __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */ | ||
82 | u8 __iomem res22[4]; | ||
83 | __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */ | ||
84 | u8 __iomem res23[12]; | ||
85 | __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */ | ||
86 | u8 __iomem res24[4]; | ||
87 | __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */ | ||
88 | __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */ | ||
89 | __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */ | ||
90 | __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */ | ||
91 | }; | 29 | }; |
92 | 30 | ||
93 | #endif /* __POWERPC_FSL_PCIE_H */ | 31 | /* PCI/PCI Express inbound window reg */ |
32 | struct pci_inbound_window_regs { | ||
33 | __be32 pitar; /* 0x.0 - Inbound translation address register */ | ||
34 | u8 res1[4]; | ||
35 | __be32 piwbar; /* 0x.8 - Inbound window base address register */ | ||
36 | __be32 piwbear; /* 0x.c - Inbound window base extended address register */ | ||
37 | __be32 piwar; /* 0x.10 - Inbound window attributes register */ | ||
38 | u8 res2[12]; | ||
39 | }; | ||
40 | |||
41 | /* PCI/PCI Express IO block registers for 85xx/86xx */ | ||
42 | struct ccsr_pci { | ||
43 | __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ | ||
44 | __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ | ||
45 | __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | ||
46 | __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ | ||
47 | __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ | ||
48 | u8 res2[12]; | ||
49 | __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ | ||
50 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ | ||
51 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ | ||
52 | __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ | ||
53 | u8 res3[3024]; | ||
54 | |||
55 | /* PCI/PCI Express outbound window 0-4 | ||
56 | * Window 0 is the default window and is the only window enabled upon reset. | ||
57 | * The default outbound register set is used when a transaction misses | ||
58 | * in all of the other outbound windows. | ||
59 | */ | ||
60 | struct pci_outbound_window_regs pow[5]; | ||
61 | |||
62 | u8 res14[256]; | ||
63 | |||
64 | /* PCI/PCI Express inbound window 3-1 | ||
65 | * inbound window 1 supports only a 32-bit base address and does not | ||
66 | * define an inbound window base extended address register. | ||
67 | */ | ||
68 | struct pci_inbound_window_regs piw[3]; | ||
69 | |||
70 | __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ | ||
71 | u8 res21[4]; | ||
72 | __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ | ||
73 | u8 res22[4]; | ||
74 | __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ | ||
75 | u8 res23[12]; | ||
76 | __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ | ||
77 | u8 res24[4]; | ||
78 | __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ | ||
79 | __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ | ||
80 | __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ | ||
81 | __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ | ||
82 | }; | ||
83 | |||
84 | extern int fsl_add_bridge(struct device_node *dev, int is_primary); | ||
85 | |||
86 | #endif /* __POWERPC_FSL_PCI_H */ | ||
94 | #endif /* __KERNEL__ */ | 87 | #endif /* __KERNEL__ */ |