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authorKumar Gala <galak@kernel.crashing.org>2011-10-20 03:21:09 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:37 -0500
commit4e36afa7c5cd7d4585048263cbdc2b955117f590 (patch)
treeac3a4b7d60714aff2beda44c91d54dffaa9b74ad /arch/powerpc
parent4de0e39cb883b26af667c660383ac26df525ae0b (diff)
powerpc/85xx: Rework P1020RDB device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi174
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts232
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dtsi242
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi407
5 files changed, 492 insertions, 631 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
new file mode 100644
index 000000000000..fc924c5ffebe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -0,0 +1,174 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1020-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1020-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1020-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1020-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145/include/ "pq3-usb2-dr-1.dtsi"
146
147/include/ "pq3-esdhc-0.dtsi"
148/include/ "pq3-sec3.3-0.dtsi"
149
150/include/ "pq3-mpic.dtsi"
151/include/ "pq3-mpic-timer-B.dtsi"
152
153/include/ "pq3-etsec2-0.dtsi"
154 enet0: enet0_grp2: ethernet@b0000 {
155 };
156
157/include/ "pq3-etsec2-1.dtsi"
158 enet1: enet1_grp2: ethernet@b1000 {
159 };
160
161/include/ "pq3-etsec2-2.dtsi"
162 enet2: enet2_grp2: ethernet@b2000 {
163 };
164
165 global-utilities@e0000 {
166 compatible = "fsl,p1020-guts";
167 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr;
169 };
170};
171
172/include/ "pq3-etsec2-grp2-0.dtsi"
173/include/ "pq3-etsec2-grp2-1.dtsi"
174/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
new file mode 100644
index 000000000000..6f0376e554eb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1020@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1020@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index b31e7ecf24f8..518bf99b1f50 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,245 +9,26 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1020si.dtsi" 12/include/ "fsl/p1020si-pre.dtsi"
13
14/ { 13/ {
15 model = "fsl,P1020RDB"; 14 model = "fsl,P1020RDB";
16 compatible = "fsl,P1020RDB"; 15 compatible = "fsl,P1020RDB";
17 16
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory { 17 memory {
29 device_type = "memory"; 18 device_type = "memory";
30 }; 19 };
31 20
32 localbus@ffe05000 { 21 board_lbc: lbc: localbus@ffe05000 {
22 reg = <0 0xffe05000 0 0x1000>;
33 23
34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 25 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
36 0x1 0x0 0x0 0xffa00000 0x00040000 26 0x1 0x0 0x0 0xffa00000 0x00040000
37 0x2 0x0 0x0 0xffb00000 0x00020000>; 27 0x2 0x0 0x0 0xffb00000 0x00020000>;
38
39 nor@0,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x1000000>;
44 bank-width = <2>;
45 device-width = <1>;
46
47 partition@0 {
48 /* This location must not be altered */
49 /* 256KB for Vitesse 7385 Switch firmware */
50 reg = <0x0 0x00040000>;
51 label = "NOR (RO) Vitesse-7385 Firmware";
52 read-only;
53 };
54
55 partition@40000 {
56 /* 256KB for DTB Image */
57 reg = <0x00040000 0x00040000>;
58 label = "NOR (RO) DTB Image";
59 read-only;
60 };
61
62 partition@80000 {
63 /* 3.5 MB for Linux Kernel Image */
64 reg = <0x00080000 0x00380000>;
65 label = "NOR (RO) Linux Kernel Image";
66 read-only;
67 };
68
69 partition@400000 {
70 /* 11MB for JFFS2 based Root file System */
71 reg = <0x00400000 0x00b00000>;
72 label = "NOR (RW) JFFS2 Root File System";
73 };
74
75 partition@f00000 {
76 /* This location must not be altered */
77 /* 512KB for u-boot Bootloader Image */
78 /* 512KB for u-boot Environment Variables */
79 reg = <0x00f00000 0x00100000>;
80 label = "NOR (RO) U-Boot Image";
81 read-only;
82 };
83 };
84
85 nand@1,0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "fsl,p1020-fcm-nand",
89 "fsl,elbc-fcm-nand";
90 reg = <0x1 0x0 0x40000>;
91
92 partition@0 {
93 /* This location must not be altered */
94 /* 1MB for u-boot Bootloader Image */
95 reg = <0x0 0x00100000>;
96 label = "NAND (RO) U-Boot Image";
97 read-only;
98 };
99
100 partition@100000 {
101 /* 1MB for DTB Image */
102 reg = <0x00100000 0x00100000>;
103 label = "NAND (RO) DTB Image";
104 read-only;
105 };
106
107 partition@200000 {
108 /* 4MB for Linux Kernel Image */
109 reg = <0x00200000 0x00400000>;
110 label = "NAND (RO) Linux Kernel Image";
111 read-only;
112 };
113
114 partition@600000 {
115 /* 4MB for Compressed Root file System Image */
116 reg = <0x00600000 0x00400000>;
117 label = "NAND (RO) Compressed RFS Image";
118 read-only;
119 };
120
121 partition@a00000 {
122 /* 7MB for JFFS2 based Root file System */
123 reg = <0x00a00000 0x00700000>;
124 label = "NAND (RW) JFFS2 Root File System";
125 };
126
127 partition@1100000 {
128 /* 15MB for JFFS2 based Root file System */
129 reg = <0x01100000 0x00f00000>;
130 label = "NAND (RW) Writable User area";
131 };
132 };
133
134 L2switch@2,0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "vitesse-7385";
138 reg = <0x2 0x0 0x20000>;
139 };
140
141 }; 28 };
142 29
143 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
144 i2c@3000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
145 rtc@68 {
146 compatible = "dallas,ds1339";
147 reg = <0x68>;
148 };
149 };
150
151 spi@7000 {
152 flash@0 {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "spansion,s25sl12801";
156 reg = <0>;
157 spi-max-frequency = <40000000>; /* input clock */
158
159 partition@u-boot {
160 /* 512KB for u-boot Bootloader Image */
161 reg = <0x0 0x00080000>;
162 label = "u-boot";
163 read-only;
164 };
165
166 partition@dtb {
167 /* 512KB for DTB Image */
168 reg = <0x00080000 0x00080000>;
169 label = "dtb";
170 read-only;
171 };
172
173 partition@kernel {
174 /* 4MB for Linux Kernel Image */
175 reg = <0x00100000 0x00400000>;
176 label = "kernel";
177 read-only;
178 };
179
180 partition@fs {
181 /* 4MB for Compressed RFS Image */
182 reg = <0x00500000 0x00400000>;
183 label = "file system";
184 read-only;
185 };
186
187 partition@jffs-fs {
188 /* 7MB for JFFS2 based RFS */
189 reg = <0x00900000 0x00700000>;
190 label = "file system jffs2";
191 };
192 };
193 };
194
195 mdio@24000 {
196
197 phy0: ethernet-phy@0 {
198 interrupt-parent = <&mpic>;
199 interrupts = <3 1>;
200 reg = <0x0>;
201 };
202
203 phy1: ethernet-phy@1 {
204 interrupt-parent = <&mpic>;
205 interrupts = <2 1>;
206 reg = <0x1>;
207 };
208 };
209
210 mdio@25000 {
211
212 tbi0: tbi-phy@11 {
213 reg = <0x11>;
214 device_type = "tbi-phy";
215 };
216 };
217
218 enet0: ethernet@b0000 {
219 fixed-link = <1 1 1000 0 0>;
220 phy-connection-type = "rgmii-id";
221
222 };
223
224 enet1: ethernet@b1000 {
225 phy-handle = <&phy0>;
226 tbi-handle = <&tbi0>;
227 phy-connection-type = "sgmii";
228
229 };
230
231 enet2: ethernet@b2000 {
232 phy-handle = <&phy1>;
233 phy-connection-type = "rgmii-id";
234
235 };
236
237 usb@22000 {
238 phy_type = "ulpi";
239 };
240
241 /* USB2 is shared with localbus, so it must be disabled
242 by default. We can't put 'status = "disabled";' here
243 since U-Boot doesn't clear the status property when
244 it enables USB2. OTOH, U-Boot does create a new node
245 when there isn't any. So, just comment it out.
246 usb@23000 {
247 phy_type = "ulpi";
248 };
249 */
250
251 }; 32 };
252 33
253 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
@@ -280,3 +61,6 @@
280 }; 61 };
281 }; 62 };
282}; 63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb.dtsi b/arch/powerpc/boot/dts/p1020rdb.dtsi
new file mode 100644
index 000000000000..37389464ad89
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dtsi
@@ -0,0 +1,242 @@
1/*
2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR (RO) DTB Image";
56 read-only;
57 };
58
59 partition@80000 {
60 /* 3.5 MB for Linux Kernel Image */
61 reg = <0x00080000 0x00380000>;
62 label = "NOR (RO) Linux Kernel Image";
63 read-only;
64 };
65
66 partition@400000 {
67 /* 11MB for JFFS2 based Root file System */
68 reg = <0x00400000 0x00b00000>;
69 label = "NOR (RW) JFFS2 Root File System";
70 };
71
72 partition@f00000 {
73 /* This location must not be altered */
74 /* 512KB for u-boot Bootloader Image */
75 /* 512KB for u-boot Environment Variables */
76 reg = <0x00f00000 0x00100000>;
77 label = "NOR (RO) U-Boot Image";
78 read-only;
79 };
80 };
81
82 nand@1,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "fsl,p1020-fcm-nand",
86 "fsl,elbc-fcm-nand";
87 reg = <0x1 0x0 0x40000>;
88
89 partition@0 {
90 /* This location must not be altered */
91 /* 1MB for u-boot Bootloader Image */
92 reg = <0x0 0x00100000>;
93 label = "NAND (RO) U-Boot Image";
94 read-only;
95 };
96
97 partition@100000 {
98 /* 1MB for DTB Image */
99 reg = <0x00100000 0x00100000>;
100 label = "NAND (RO) DTB Image";
101 read-only;
102 };
103
104 partition@200000 {
105 /* 4MB for Linux Kernel Image */
106 reg = <0x00200000 0x00400000>;
107 label = "NAND (RO) Linux Kernel Image";
108 read-only;
109 };
110
111 partition@600000 {
112 /* 4MB for Compressed Root file System Image */
113 reg = <0x00600000 0x00400000>;
114 label = "NAND (RO) Compressed RFS Image";
115 read-only;
116 };
117
118 partition@a00000 {
119 /* 7MB for JFFS2 based Root file System */
120 reg = <0x00a00000 0x00700000>;
121 label = "NAND (RW) JFFS2 Root File System";
122 };
123
124 partition@1100000 {
125 /* 15MB for JFFS2 based Root file System */
126 reg = <0x01100000 0x00f00000>;
127 label = "NAND (RW) Writable User area";
128 };
129 };
130
131 L2switch@2,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "vitesse-7385";
135 reg = <0x2 0x0 0x20000>;
136 };
137};
138
139&board_soc {
140 i2c@3000 {
141 rtc@68 {
142 compatible = "dallas,ds1339";
143 reg = <0x68>;
144 };
145 };
146
147 spi@7000 {
148 flash@0 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "spansion,s25sl12801";
152 reg = <0>;
153 spi-max-frequency = <40000000>; /* input clock */
154
155 partition@u-boot {
156 /* 512KB for u-boot Bootloader Image */
157 reg = <0x0 0x00080000>;
158 label = "u-boot";
159 read-only;
160 };
161
162 partition@dtb {
163 /* 512KB for DTB Image */
164 reg = <0x00080000 0x00080000>;
165 label = "dtb";
166 read-only;
167 };
168
169 partition@kernel {
170 /* 4MB for Linux Kernel Image */
171 reg = <0x00100000 0x00400000>;
172 label = "kernel";
173 read-only;
174 };
175
176 partition@fs {
177 /* 4MB for Compressed RFS Image */
178 reg = <0x00500000 0x00400000>;
179 label = "file system";
180 read-only;
181 };
182
183 partition@jffs-fs {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "file system jffs2";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 /* USB2 is shared with localbus, so it must be disabled
196 by default. We can't put 'status = "disabled";' here
197 since U-Boot doesn't clear the status property when
198 it enables USB2. OTOH, U-Boot does create a new node
199 when there isn't any. So, just comment it out.
200 usb@23000 {
201 phy_type = "ulpi";
202 };
203 */
204
205 mdio@24000 {
206 phy0: ethernet-phy@0 {
207 interrupt-parent = <&mpic>;
208 interrupts = <3 1>;
209 reg = <0x0>;
210 };
211
212 phy1: ethernet-phy@1 {
213 interrupt-parent = <&mpic>;
214 interrupts = <2 1>;
215 reg = <0x1>;
216 };
217 };
218
219 mdio@25000 {
220 tbi0: tbi-phy@11 {
221 reg = <0x11>;
222 device_type = "tbi-phy";
223 };
224 };
225
226 enet0: ethernet@b0000 {
227 fixed-link = <1 1 1000 0 0>;
228 phy-connection-type = "rgmii-id";
229
230 };
231
232 enet1: ethernet@b1000 {
233 phy-handle = <&phy0>;
234 tbi-handle = <&tbi0>;
235 phy-connection-type = "sgmii";
236 };
237
238 enet2: ethernet@b2000 {
239 phy-handle = <&phy1>;
240 phy-connection-type = "rgmii-id";
241 };
242};
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
deleted file mode 100644
index b08c848551cf..000000000000
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ /dev/null
@@ -1,407 +0,0 @@
1/*
2 * P1020si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,P1020@0 {
24 device_type = "cpu";
25 reg = <0x0>;
26 next-level-cache = <&L2>;
27 };
28
29 PowerPC,P1020@1 {
30 device_type = "cpu";
31 reg = <0x1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 localbus@ffe05000 {
37 #address-cells = <2>;
38 #size-cells = <1>;
39 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
40 reg = <0 0xffe05000 0 0x1000>;
41 interrupts = <19 2 0 0>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p1020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <16 2 0 0>;
62 };
63
64 memory-controller@2000 {
65 compatible = "fsl,p1020-memory-controller";
66 reg = <0x2000 0x1000>;
67 interrupts = <16 2 0 0>;
68 };
69
70 i2c@3000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 cell-index = <0>;
74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>;
76 interrupts = <43 2 0 0>;
77 dfsrr;
78 };
79
80 i2c@3100 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 cell-index = <1>;
84 compatible = "fsl-i2c";
85 reg = <0x3100 0x100>;
86 interrupts = <43 2 0 0>;
87 dfsrr;
88 };
89
90 serial0: serial@4500 {
91 cell-index = <0>;
92 device_type = "serial";
93 compatible = "ns16550";
94 reg = <0x4500 0x100>;
95 clock-frequency = <0>;
96 interrupts = <42 2 0 0>;
97 };
98
99 serial1: serial@4600 {
100 cell-index = <1>;
101 device_type = "serial";
102 compatible = "ns16550";
103 reg = <0x4600 0x100>;
104 clock-frequency = <0>;
105 interrupts = <42 2 0 0>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,p1020-espi", "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2 0 0>;
114 fsl,espi-num-chipselects = <4>;
115 };
116
117 gpio: gpio-controller@f000 {
118 #gpio-cells = <2>;
119 compatible = "fsl,mpc8572-gpio";
120 reg = <0xf000 0x100>;
121 interrupts = <47 0x2 0 0>;
122 gpio-controller;
123 };
124
125 L2: l2-cache-controller@20000 {
126 compatible = "fsl,p1020-l2-cache-controller";
127 reg = <0x20000 0x1000>;
128 cache-line-size = <32>; // 32 bytes
129 cache-size = <0x40000>; // L2,256K
130 interrupts = <16 2 0 0>;
131 };
132
133 dma@21300 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "fsl,eloplus-dma";
137 reg = <0x21300 0x4>;
138 ranges = <0x0 0x21100 0x200>;
139 cell-index = <0>;
140 dma-channel@0 {
141 compatible = "fsl,eloplus-dma-channel";
142 reg = <0x0 0x80>;
143 cell-index = <0>;
144 interrupts = <20 2 0 0>;
145 };
146 dma-channel@80 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x80 0x80>;
149 cell-index = <1>;
150 interrupts = <21 2 0 0>;
151 };
152 dma-channel@100 {
153 compatible = "fsl,eloplus-dma-channel";
154 reg = <0x100 0x80>;
155 cell-index = <2>;
156 interrupts = <22 2 0 0>;
157 };
158 dma-channel@180 {
159 compatible = "fsl,eloplus-dma-channel";
160 reg = <0x180 0x80>;
161 cell-index = <3>;
162 interrupts = <23 2 0 0>;
163 };
164 };
165
166 mdio@24000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,etsec2-mdio";
170 reg = <0x24000 0x1000 0xb0030 0x4>;
171
172 };
173
174 mdio@25000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,etsec2-tbi";
178 reg = <0x25000 0x1000 0xb1030 0x4>;
179
180 };
181
182 enet0: ethernet@b0000 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 device_type = "network";
186 model = "eTSEC";
187 compatible = "fsl,etsec2";
188 fsl,num_rx_queues = <0x8>;
189 fsl,num_tx_queues = <0x8>;
190 fsl,magic-packet;
191 local-mac-address = [ 00 00 00 00 00 00 ];
192
193 queue-group@0 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 reg = <0xb0000 0x1000>;
197 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
198 };
199
200 queue-group@1 {
201 #address-cells = <1>;
202 #size-cells = <1>;
203 reg = <0xb4000 0x1000>;
204 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
205 };
206 };
207
208 enet1: ethernet@b1000 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 device_type = "network";
212 model = "eTSEC";
213 compatible = "fsl,etsec2";
214 fsl,num_rx_queues = <0x8>;
215 fsl,num_tx_queues = <0x8>;
216 fsl,magic-packet;
217 local-mac-address = [ 00 00 00 00 00 00 ];
218
219 queue-group@0 {
220 #address-cells = <1>;
221 #size-cells = <1>;
222 reg = <0xb1000 0x1000>;
223 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
224 };
225
226 queue-group@1 {
227 #address-cells = <1>;
228 #size-cells = <1>;
229 reg = <0xb5000 0x1000>;
230 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
231 };
232 };
233
234 enet2: ethernet@b2000 {
235 #address-cells = <1>;
236 #size-cells = <1>;
237 device_type = "network";
238 model = "eTSEC";
239 compatible = "fsl,etsec2";
240 fsl,num_rx_queues = <0x8>;
241 fsl,num_tx_queues = <0x8>;
242 fsl,magic-packet;
243 local-mac-address = [ 00 00 00 00 00 00 ];
244
245 queue-group@0 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 reg = <0xb2000 0x1000>;
249 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
250 };
251
252 queue-group@1 {
253 #address-cells = <1>;
254 #size-cells = <1>;
255 reg = <0xb6000 0x1000>;
256 interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
257 };
258 };
259
260 usb@22000 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "fsl-usb2-dr";
264 reg = <0x22000 0x1000>;
265 interrupts = <28 0x2 0 0>;
266 };
267
268 /* USB2 is shared with localbus, so it must be disabled
269 by default. We can't put 'status = "disabled";' here
270 since U-Boot doesn't clear the status property when
271 it enables USB2. OTOH, U-Boot does create a new node
272 when there isn't any. So, just comment it out.
273 usb@23000 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 compatible = "fsl-usb2-dr";
277 reg = <0x23000 0x1000>;
278 interrupts = <46 0x2 0 0>;
279 phy_type = "ulpi";
280 };
281 */
282
283 sdhci@2e000 {
284 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
285 reg = <0x2e000 0x1000>;
286 interrupts = <72 0x2 0 0>;
287 /* Filled in by U-Boot */
288 clock-frequency = <0>;
289 };
290
291 crypto@30000 {
292 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
293 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
294 "fsl,sec2.0";
295 reg = <0x30000 0x10000>;
296 interrupts = <45 2 0 0 58 2 0 0>;
297 fsl,num-channels = <4>;
298 fsl,channel-fifo-len = <24>;
299 fsl,exec-units-mask = <0x97c>;
300 fsl,descriptor-types-mask = <0x3a30abf>;
301 };
302
303 mpic: pic@40000 {
304 interrupt-controller;
305 #address-cells = <0>;
306 #interrupt-cells = <4>;
307 reg = <0x40000 0x40000>;
308 compatible = "chrp,open-pic";
309 device_type = "open-pic";
310 };
311
312 timer@41100 {
313 compatible = "fsl,mpic-global-timer";
314 reg = <0x41100 0x100 0x41300 4>;
315 interrupts = <0 0 3 0
316 1 0 3 0
317 2 0 3 0
318 3 0 3 0>;
319 };
320
321 timer@42100 {
322 compatible = "fsl,mpic-global-timer";
323 reg = <0x42100 0x100 0x42300 4>;
324 interrupts = <4 0 3 0
325 5 0 3 0
326 6 0 3 0
327 7 0 3 0>;
328 };
329
330 msi@41600 {
331 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
332 reg = <0x41600 0x80>;
333 msi-available-ranges = <0 0x100>;
334 interrupts = <
335 0xe0 0 0 0
336 0xe1 0 0 0
337 0xe2 0 0 0
338 0xe3 0 0 0
339 0xe4 0 0 0
340 0xe5 0 0 0
341 0xe6 0 0 0
342 0xe7 0 0 0>;
343 };
344
345 global-utilities@e0000 { //global utilities block
346 compatible = "fsl,p1020-guts","fsl,p2020-guts";
347 reg = <0xe0000 0x1000>;
348 fsl,has-rstcr;
349 };
350 };
351
352 pci0: pcie@ffe09000 {
353 compatible = "fsl,mpc8548-pcie";
354 device_type = "pci";
355 #size-cells = <2>;
356 #address-cells = <3>;
357 bus-range = <0 255>;
358 clock-frequency = <33333333>;
359 interrupts = <16 2 0 0>;
360
361 pcie@0 {
362 reg = <0 0 0 0 0>;
363 #interrupt-cells = <1>;
364 #size-cells = <2>;
365 #address-cells = <3>;
366 device_type = "pci";
367 interrupts = <16 2 0 0>;
368 interrupt-map-mask = <0xf800 0 0 7>;
369 interrupt-map = <
370 /* IDSEL 0x0 */
371 0000 0x0 0x0 0x1 &mpic 0x4 0x1
372 0000 0x0 0x0 0x2 &mpic 0x5 0x1
373 0000 0x0 0x0 0x3 &mpic 0x6 0x1
374 0000 0x0 0x0 0x4 &mpic 0x7 0x1
375 >;
376 };
377
378 };
379
380 pci1: pcie@ffe0a000 {
381 compatible = "fsl,mpc8548-pcie";
382 device_type = "pci";
383 #size-cells = <2>;
384 #address-cells = <3>;
385 bus-range = <0 255>;
386 clock-frequency = <33333333>;
387 interrupts = <16 2 0 0>;
388
389 pcie@0 {
390 reg = <0 0 0 0 0>;
391 #interrupt-cells = <1>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 interrupts = <16 2 0 0>;
396 interrupt-map-mask = <0xf800 0 0 7>;
397
398 interrupt-map = <
399 /* IDSEL 0x0 */
400 0000 0x0 0x0 0x1 &mpic 0x0 0x1
401 0000 0x0 0x0 0x2 &mpic 0x1 0x1
402 0000 0x0 0x0 0x3 &mpic 0x2 0x1
403 0000 0x0 0x0 0x4 &mpic 0x3 0x1
404 >;
405 };
406 };
407};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 02:23:27 -0500