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authorStephen Rothwell <sfr@canb.auug.org.au>2006-05-19 02:42:49 -0400
committerPaul Mackerras <paulus@samba.org>2006-05-24 02:08:56 -0400
commitb58b7f98670ab6dd7774b67ff1655a787321209f (patch)
tree3d7b4f3685f8743842e46f599b7c8a304d734014 /arch/powerpc
parent3c06da5ae5358e9d325d541a053e1059e9654bcc (diff)
[PATCH] powerpc: tidy up iseries/pci.c
Remove some unused counters. No need to allocate iomm_table and iobar_table, which means that iomm_table_initialize is not longer needed. Use kzalloc where sensible. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/platforms/iseries/pci.c78
1 files changed, 11 insertions, 67 deletions
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c
index 428ffb5cf044..91a94747eda9 100644
--- a/arch/powerpc/platforms/iseries/pci.c
+++ b/arch/powerpc/platforms/iseries/pci.c
@@ -57,15 +57,6 @@ LIST_HEAD(iSeries_Global_Device_List);
57 57
58static int DeviceCount; 58static int DeviceCount;
59 59
60/* Counters and control flags. */
61static long Pci_Io_Read_Count;
62static long Pci_Io_Write_Count;
63#if 0
64static long Pci_Cfg_Read_Count;
65static long Pci_Cfg_Write_Count;
66#endif
67static long Pci_Error_Count;
68
69static int Pci_Retry_Max = 3; /* Only retry 3 times */ 60static int Pci_Retry_Max = 3; /* Only retry 3 times */
70static int Pci_Error_Flag = 1; /* Set Retry Error on. */ 61static int Pci_Error_Flag = 1; /* Set Retry Error on. */
71 62
@@ -79,41 +70,19 @@ static struct pci_ops iSeries_pci_ops;
79#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL 70#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
80#define BASE_IO_MEMORY 0xE000000000000000UL 71#define BASE_IO_MEMORY 0xE000000000000000UL
81 72
82static unsigned long max_io_memory = 0xE000000000000000UL; 73static unsigned long max_io_memory = BASE_IO_MEMORY;
83static long current_iomm_table_entry; 74static long current_iomm_table_entry;
84 75
85/* 76/*
86 * Lookup Tables. 77 * Lookup Tables.
87 */ 78 */
88static struct device_node **iomm_table; 79static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
89static u8 *iobar_table; 80static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
90 81
91/* 82static const char pci_io_text[] = "iSeries PCI I/O";
92 * Static and Global variables
93 */
94static char *pci_io_text = "iSeries PCI I/O";
95static DEFINE_SPINLOCK(iomm_table_lock); 83static DEFINE_SPINLOCK(iomm_table_lock);
96 84
97/* 85/*
98 * iomm_table_initialize
99 *
100 * Allocates and initalizes the Address Translation Table and Bar
101 * Tables to get them ready for use. Must be called before any
102 * I/O space is handed out to the device BARs.
103 */
104static void iomm_table_initialize(void)
105{
106 spin_lock(&iomm_table_lock);
107 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
108 GFP_KERNEL);
109 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
110 GFP_KERNEL);
111 spin_unlock(&iomm_table_lock);
112 if ((iomm_table == NULL) || (iobar_table == NULL))
113 panic("PCI: I/O tables allocation failed.\n");
114}
115
116/*
117 * iomm_table_allocate_entry 86 * iomm_table_allocate_entry
118 * 87 *
119 * Adds pci_dev entry in address translation table 88 * Adds pci_dev entry in address translation table
@@ -140,9 +109,8 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
140 */ 109 */
141 spin_lock(&iomm_table_lock); 110 spin_lock(&iomm_table_lock);
142 bar_res->name = pci_io_text; 111 bar_res->name = pci_io_text;
143 bar_res->start = 112 bar_res->start = BASE_IO_MEMORY +
144 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; 113 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
145 bar_res->start += BASE_IO_MEMORY;
146 bar_res->end = bar_res->start + bar_size - 1; 114 bar_res->end = bar_res->start + bar_size - 1;
147 /* 115 /*
148 * Allocate the number of table entries needed for BAR. 116 * Allocate the number of table entries needed for BAR.
@@ -154,7 +122,7 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
154 ++current_iomm_table_entry; 122 ++current_iomm_table_entry;
155 } 123 }
156 max_io_memory = BASE_IO_MEMORY + 124 max_io_memory = BASE_IO_MEMORY +
157 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry); 125 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
158 spin_unlock(&iomm_table_lock); 126 spin_unlock(&iomm_table_lock);
159} 127}
160 128
@@ -171,13 +139,10 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
171 */ 139 */
172static void allocate_device_bars(struct pci_dev *dev) 140static void allocate_device_bars(struct pci_dev *dev)
173{ 141{
174 struct resource *bar_res;
175 int bar_num; 142 int bar_num;
176 143
177 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) { 144 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
178 bar_res = &dev->resource[bar_num];
179 iomm_table_allocate_entry(dev, bar_num); 145 iomm_table_allocate_entry(dev, bar_num);
180 }
181} 146}
182 147
183/* 148/*
@@ -205,10 +170,9 @@ static struct device_node *build_device_node(HvBusNumber Bus,
205 struct device_node *node; 170 struct device_node *node;
206 struct pci_dn *pdn; 171 struct pci_dn *pdn;
207 172
208 node = kmalloc(sizeof(struct device_node), GFP_KERNEL); 173 node = kzalloc(sizeof(struct device_node), GFP_KERNEL);
209 if (node == NULL) 174 if (node == NULL)
210 return NULL; 175 return NULL;
211 memset(node, 0, sizeof(struct device_node));
212 pdn = kzalloc(sizeof(*pdn), GFP_KERNEL); 176 pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
213 if (pdn == NULL) { 177 if (pdn == NULL) {
214 kfree(node); 178 kfree(node);
@@ -224,7 +188,7 @@ static struct device_node *build_device_node(HvBusNumber Bus,
224} 188}
225 189
226/* 190/*
227 * unsigned long __init find_and_init_phbs(void) 191 * iSeries_pcibios_init
228 * 192 *
229 * Description: 193 * Description:
230 * This function checks for all possible system PCI host bridges that connect 194 * This function checks for all possible system PCI host bridges that connect
@@ -232,7 +196,7 @@ static struct device_node *build_device_node(HvBusNumber Bus,
232 * ownership status. A pci_controller is built for any bus which is partially 196 * ownership status. A pci_controller is built for any bus which is partially
233 * owned or fully owned by this guest partition. 197 * owned or fully owned by this guest partition.
234 */ 198 */
235unsigned long __init find_and_init_phbs(void) 199void iSeries_pcibios_init(void)
236{ 200{
237 struct pci_controller *phb; 201 struct pci_controller *phb;
238 HvBusNumber bus; 202 HvBusNumber bus;
@@ -263,18 +227,6 @@ unsigned long __init find_and_init_phbs(void)
263 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X", 227 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
264 bus, ret); 228 bus, ret);
265 } 229 }
266 return 0;
267}
268
269/*
270 * iSeries_pcibios_init
271 *
272 * Chance to initialize and structures or variable before PCI Bus walk.
273 */
274void iSeries_pcibios_init(void)
275{
276 iomm_table_initialize();
277 find_and_init_phbs();
278} 230}
279 231
280/* 232/*
@@ -331,8 +283,7 @@ static void scan_PHB_slots(struct pci_controller *Phb)
331 int IdSel; 283 int IdSel;
332 const int MaxAgents = 8; 284 const int MaxAgents = 8;
333 285
334 DevInfo = (struct HvCallPci_DeviceInfo*) 286 DevInfo = kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
335 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
336 if (DevInfo == NULL) 287 if (DevInfo == NULL)
337 return; 288 return;
338 289
@@ -622,7 +573,6 @@ static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
622 if (ret != 0) { 573 if (ret != 0) {
623 struct pci_dn *pdn = PCI_DN(DevNode); 574 struct pci_dn *pdn = PCI_DN(DevNode);
624 575
625 ++Pci_Error_Count;
626 (*retry)++; 576 (*retry)++;
627 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", 577 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
628 TextHdr, pdn->busno, pdn->devfn, 578 TextHdr, pdn->busno, pdn->devfn,
@@ -704,7 +654,6 @@ u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
704 return 0xff; 654 return 0xff;
705 } 655 }
706 do { 656 do {
707 ++Pci_Io_Read_Count;
708 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); 657 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
709 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); 658 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
710 659
@@ -734,7 +683,6 @@ u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
734 return 0xffff; 683 return 0xffff;
735 } 684 }
736 do { 685 do {
737 ++Pci_Io_Read_Count;
738 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, 686 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
739 BarOffset, 0); 687 BarOffset, 0);
740 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); 688 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
@@ -765,7 +713,6 @@ u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
765 return 0xffffffff; 713 return 0xffffffff;
766 } 714 }
767 do { 715 do {
768 ++Pci_Io_Read_Count;
769 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, 716 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
770 BarOffset, 0); 717 BarOffset, 0);
771 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); 718 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
@@ -803,7 +750,6 @@ void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
803 return; 750 return;
804 } 751 }
805 do { 752 do {
806 ++Pci_Io_Write_Count;
807 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); 753 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
808 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); 754 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
809} 755}
@@ -831,7 +777,6 @@ void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
831 return; 777 return;
832 } 778 }
833 do { 779 do {
834 ++Pci_Io_Write_Count;
835 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); 780 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
836 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); 781 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
837} 782}
@@ -859,7 +804,6 @@ void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
859 return; 804 return;
860 } 805 }
861 do { 806 do {
862 ++Pci_Io_Write_Count;
863 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); 807 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
864 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); 808 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
865} 809}