diff options
author | Kevin Corry <kevcorry@us.ibm.com> | 2006-10-24 12:31:21 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-10-25 00:20:21 -0400 |
commit | bffd4927ba4377aa38be5450e20e0fecd2523fe3 (patch) | |
tree | dcdb8bb69c631b85f084ce52ef101325b5054647 /arch/powerpc | |
parent | 22b8c9f5baeb440a716ea760ff05290221565b4c (diff) |
[POWERPC] cell: add shadow registers for pmd_reg
Many of the registers in the performance monitoring unit are write-only.
We need to save a "shadow" copy when we write to those registers so we
can retrieve the values if we need them later.
The new cbe_pmd_shadow_regs structure is added to the cbe_regs_map structure
so we have the appropriate per-node copies of these shadow values.
Signed-off-by: Kevin Corry <kevcorry@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/platforms/cell/cbe_regs.c | 17 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/cbe_regs.h | 35 |
2 files changed, 52 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/cell/cbe_regs.c b/arch/powerpc/platforms/cell/cbe_regs.c index 5e3e0e925e4e..5a91b75c2f01 100644 --- a/arch/powerpc/platforms/cell/cbe_regs.c +++ b/arch/powerpc/platforms/cell/cbe_regs.c | |||
@@ -30,6 +30,7 @@ static struct cbe_regs_map | |||
30 | struct cbe_pmd_regs __iomem *pmd_regs; | 30 | struct cbe_pmd_regs __iomem *pmd_regs; |
31 | struct cbe_iic_regs __iomem *iic_regs; | 31 | struct cbe_iic_regs __iomem *iic_regs; |
32 | struct cbe_mic_tm_regs __iomem *mic_tm_regs; | 32 | struct cbe_mic_tm_regs __iomem *mic_tm_regs; |
33 | struct cbe_pmd_shadow_regs pmd_shadow_regs; | ||
33 | } cbe_regs_maps[MAX_CBE]; | 34 | } cbe_regs_maps[MAX_CBE]; |
34 | static int cbe_regs_map_count; | 35 | static int cbe_regs_map_count; |
35 | 36 | ||
@@ -80,6 +81,22 @@ struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu) | |||
80 | } | 81 | } |
81 | EXPORT_SYMBOL_GPL(cbe_get_cpu_pmd_regs); | 82 | EXPORT_SYMBOL_GPL(cbe_get_cpu_pmd_regs); |
82 | 83 | ||
84 | struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np) | ||
85 | { | ||
86 | struct cbe_regs_map *map = cbe_find_map(np); | ||
87 | if (map == NULL) | ||
88 | return NULL; | ||
89 | return &map->pmd_shadow_regs; | ||
90 | } | ||
91 | |||
92 | struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu) | ||
93 | { | ||
94 | struct cbe_regs_map *map = cbe_thread_map[cpu].regs; | ||
95 | if (map == NULL) | ||
96 | return NULL; | ||
97 | return &map->pmd_shadow_regs; | ||
98 | } | ||
99 | |||
83 | struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np) | 100 | struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np) |
84 | { | 101 | { |
85 | struct cbe_regs_map *map = cbe_find_map(np); | 102 | struct cbe_regs_map *map = cbe_find_map(np); |
diff --git a/arch/powerpc/platforms/cell/cbe_regs.h b/arch/powerpc/platforms/cell/cbe_regs.h index 02bdbc1cd6e7..d352f110ef9c 100644 --- a/arch/powerpc/platforms/cell/cbe_regs.h +++ b/arch/powerpc/platforms/cell/cbe_regs.h | |||
@@ -121,6 +121,41 @@ extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np); | |||
121 | extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu); | 121 | extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu); |
122 | 122 | ||
123 | /* | 123 | /* |
124 | * PMU shadow registers | ||
125 | * | ||
126 | * Many of the registers in the performance monitoring unit are write-only, | ||
127 | * so we need to save a copy of what we write to those registers. | ||
128 | * | ||
129 | * The actual data counters are read/write. However, writing to the counters | ||
130 | * only takes effect if the PMU is enabled. Otherwise the value is stored in | ||
131 | * a hardware latch until the next time the PMU is enabled. So we save a copy | ||
132 | * of the counter values if we need to read them back while the PMU is | ||
133 | * disabled. The counter_value_in_latch field is a bitmap indicating which | ||
134 | * counters currently have a value waiting to be written. | ||
135 | */ | ||
136 | |||
137 | #define NR_PHYS_CTRS 4 | ||
138 | #define NR_CTRS (NR_PHYS_CTRS * 2) | ||
139 | |||
140 | struct cbe_pmd_shadow_regs { | ||
141 | u32 group_control; | ||
142 | u32 debug_bus_control; | ||
143 | u32 trace_address; | ||
144 | u32 ext_tr_timer; | ||
145 | u32 pm_status; | ||
146 | u32 pm_control; | ||
147 | u32 pm_interval; | ||
148 | u32 pm_start_stop; | ||
149 | u32 pm07_control[NR_CTRS]; | ||
150 | |||
151 | u32 pm_ctr[NR_PHYS_CTRS]; | ||
152 | u32 counter_value_in_latch; | ||
153 | }; | ||
154 | |||
155 | extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np); | ||
156 | extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu); | ||
157 | |||
158 | /* | ||
124 | * | 159 | * |
125 | * IIC unit register definitions | 160 | * IIC unit register definitions |
126 | * | 161 | * |