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authorPeter Korsgaard <jacmet@sunsite.dk>2009-06-09 07:43:32 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-06-15 22:45:31 -0400
commitb7d66c88c968379ebe683a28c4005895497ebbad (patch)
tree58997c1d300f4f90c1b63479aec9dd8c1f55c054 /arch/powerpc
parent4dc2a6cf82746c1e632aad0cd38615a35f8df075 (diff)
powerpc/mpc83xx: Fix usb mux setup for mpc834x
usb0 and usb1 mux settings in the sicrl register were swapped (twice!) in mpc834x_usb_cfg(), leading to various strange issues with fsl-ehci and full speed devices. The USB port config on mpc834x is done using 2 muxes: Port 0 is always used for MPH port 0, and port 1 can either be used for MPH port 1 or DR (unless DR uses UTMI phy or OTG, then it uses both ports) - See 8349 RM figure 1-4.. mpc8349_usb_cfg() had this inverted for the DR, and it also had the bit positions of the usb0 / usb1 mux settings swapped. It would basically work if you specified port1 instead of port0 for the MPH controller (and happened to use ULPI phys), which is what all the 834x dts have done, even though that configuration is physically invalid. Instead fix mpc8349_usb_cfg() and adjust the dts files to match reality. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/asp834x-redboot.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts2
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts2
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h4
-rw-r--r--arch/powerpc/platforms/83xx/usb.c10
6 files changed, 11 insertions, 11 deletions
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 7da84fd7be93..261d10c4534b 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -167,7 +167,7 @@
167 interrupt-parent = <&ipic>; 167 interrupt-parent = <&ipic>;
168 interrupts = <39 0x8>; 168 interrupts = <39 0x8>;
169 phy_type = "ulpi"; 169 phy_type = "ulpi";
170 port1; 170 port0;
171 }; 171 };
172 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 172 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
173 usb@23000 { 173 usb@23000 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index e3eeaeda9187..feeeb7f9d609 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -156,7 +156,7 @@
156 interrupt-parent = <&ipic>; 156 interrupt-parent = <&ipic>;
157 interrupts = <39 0x8>; 157 interrupts = <39 0x8>;
158 phy_type = "ulpi"; 158 phy_type = "ulpi";
159 port1; 159 port0;
160 }; 160 };
161 161
162 usb@23000 { 162 usb@23000 {
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index a2553a6f9009..230febb9b72f 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -153,7 +153,7 @@
153 interrupt-parent = <&ipic>; 153 interrupt-parent = <&ipic>;
154 interrupts = <39 0x8>; 154 interrupts = <39 0x8>;
155 phy_type = "ulpi"; 155 phy_type = "ulpi";
156 port1; 156 port0;
157 }; 157 };
158 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 158 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
159 usb@23000 { 159 usb@23000 {
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 5fb6f6684b0e..2d9fa68f641c 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -144,7 +144,7 @@
144 interrupt-parent = <&ipic>; 144 interrupt-parent = <&ipic>;
145 interrupts = <39 0x8>; 145 interrupts = <39 0x8>;
146 phy_type = "ulpi"; 146 phy_type = "ulpi";
147 port1; 147 port0;
148 }; 148 };
149 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 149 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
150 usb@23000 { 150 usb@23000 {
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 83cfe51526ec..d1dc5b0b4fbf 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -22,8 +22,8 @@
22/* system i/o configuration register low */ 22/* system i/o configuration register low */
23#define MPC83XX_SICRL_OFFS 0x114 23#define MPC83XX_SICRL_OFFS 0x114
24#define MPC834X_SICRL_USB_MASK 0x60000000 24#define MPC834X_SICRL_USB_MASK 0x60000000
25#define MPC834X_SICRL_USB0 0x40000000 25#define MPC834X_SICRL_USB0 0x20000000
26#define MPC834X_SICRL_USB1 0x20000000 26#define MPC834X_SICRL_USB1 0x40000000
27#define MPC831X_SICRL_USB_MASK 0x00000c00 27#define MPC831X_SICRL_USB_MASK 0x00000c00
28#define MPC831X_SICRL_USB_ULPI 0x00000800 28#define MPC831X_SICRL_USB_ULPI 0x00000800
29#define MPC8315_SICRL_USB_MASK 0x000000fc 29#define MPC8315_SICRL_USB_MASK 0x000000fc
diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c
index 11e1fac17c7f..3ba4bb7d41bb 100644
--- a/arch/powerpc/platforms/83xx/usb.c
+++ b/arch/powerpc/platforms/83xx/usb.c
@@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void)
47 sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ 47 sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
48 48
49 prop = of_get_property(np, "phy_type", NULL); 49 prop = of_get_property(np, "phy_type", NULL);
50 port1_is_dr = 1;
50 if (prop && (!strcmp(prop, "utmi") || 51 if (prop && (!strcmp(prop, "utmi") ||
51 !strcmp(prop, "utmi_wide"))) { 52 !strcmp(prop, "utmi_wide"))) {
52 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; 53 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
53 sicrh |= MPC834X_SICRH_USB_UTMI; 54 sicrh |= MPC834X_SICRH_USB_UTMI;
54 port1_is_dr = 1; 55 port0_is_dr = 1;
55 } else if (prop && !strcmp(prop, "serial")) { 56 } else if (prop && !strcmp(prop, "serial")) {
56 dr_mode = of_get_property(np, "dr_mode", NULL); 57 dr_mode = of_get_property(np, "dr_mode", NULL);
57 if (dr_mode && !strcmp(dr_mode, "otg")) { 58 if (dr_mode && !strcmp(dr_mode, "otg")) {
58 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; 59 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
59 port1_is_dr = 1; 60 port0_is_dr = 1;
60 } else { 61 } else {
61 sicrl |= MPC834X_SICRL_USB0; 62 sicrl |= MPC834X_SICRL_USB1;
62 } 63 }
63 } else if (prop && !strcmp(prop, "ulpi")) { 64 } else if (prop && !strcmp(prop, "ulpi")) {
64 sicrl |= MPC834X_SICRL_USB0; 65 sicrl |= MPC834X_SICRL_USB1;
65 } else { 66 } else {
66 printk(KERN_WARNING "834x USB PHY type not supported\n"); 67 printk(KERN_WARNING "834x USB PHY type not supported\n");
67 } 68 }
68 port0_is_dr = 1;
69 of_node_put(np); 69 of_node_put(np);
70 } 70 }
71 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph"); 71 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");