aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/sysdev
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2006-06-29 05:24:36 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 13:26:21 -0400
commitd1bef4ed5faf7d9872337b33c4269e45ae1bf960 (patch)
treea88c58e3102396382e9137a25a884af14421f6a6 /arch/powerpc/sysdev
parentcfb9e32f2ff32ef5265c1c80fe68dd1a7f03a604 (diff)
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/i8259.c2
-rw-r--r--arch/powerpc/sysdev/ipic.c2
-rw-r--r--arch/powerpc/sysdev/mpic.c8
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index b7ac32fdd776..2bff30f6d635 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -208,7 +208,7 @@ void __init i8259_init(unsigned long intack_addr, int offset)
208 spin_unlock_irqrestore(&i8259_lock, flags); 208 spin_unlock_irqrestore(&i8259_lock, flags);
209 209
210 for (i = 0; i < NUM_ISA_INTERRUPTS; ++i) 210 for (i = 0; i < NUM_ISA_INTERRUPTS; ++i)
211 irq_desc[offset + i].handler = &i8259_pic; 211 irq_desc[offset + i].chip = &i8259_pic;
212 212
213 /* reserve our resources */ 213 /* reserve our resources */
214 setup_irq(offset + 2, &i8259_irqaction); 214 setup_irq(offset + 2, &i8259_irqaction);
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 8f01e0f1d847..46801f5ec03f 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -472,7 +472,7 @@ void __init ipic_init(phys_addr_t phys_addr,
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); 472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473 473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) { 474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].handler = &ipic; 475 irq_desc[i+irq_offset].chip = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL; 476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 } 477 }
478 478
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index bffe50d02c99..f4613ee6b7a2 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -379,14 +379,14 @@ static inline u32 mpic_physmask(u32 cpumask)
379/* Get the mpic structure from the IPI number */ 379/* Get the mpic structure from the IPI number */
380static inline struct mpic * mpic_from_ipi(unsigned int ipi) 380static inline struct mpic * mpic_from_ipi(unsigned int ipi)
381{ 381{
382 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi); 382 return container_of(irq_desc[ipi].chip, struct mpic, hc_ipi);
383} 383}
384#endif 384#endif
385 385
386/* Get the mpic structure from the irq number */ 386/* Get the mpic structure from the irq number */
387static inline struct mpic * mpic_from_irq(unsigned int irq) 387static inline struct mpic * mpic_from_irq(unsigned int irq)
388{ 388{
389 return container_of(irq_desc[irq].handler, struct mpic, hc_irq); 389 return container_of(irq_desc[irq].chip, struct mpic, hc_irq);
390} 390}
391 391
392/* Send an EOI */ 392/* Send an EOI */
@@ -752,7 +752,7 @@ void __init mpic_init(struct mpic *mpic)
752 if (!(mpic->flags & MPIC_PRIMARY)) 752 if (!(mpic->flags & MPIC_PRIMARY))
753 continue; 753 continue;
754 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU; 754 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
755 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi; 755 irq_desc[mpic->ipi_offset+i].chip = &mpic->hc_ipi;
756#endif /* CONFIG_SMP */ 756#endif /* CONFIG_SMP */
757 } 757 }
758 758
@@ -813,7 +813,7 @@ void __init mpic_init(struct mpic *mpic)
813 /* init linux descriptors */ 813 /* init linux descriptors */
814 if (i < mpic->irq_count) { 814 if (i < mpic->irq_count) {
815 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0; 815 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
816 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq; 816 irq_desc[mpic->irq_offset+i].chip = &mpic->hc_irq;
817 } 817 }
818 } 818 }
819 819