diff options
author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-05-23 12:38:58 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2008-06-10 11:39:18 -0400 |
commit | 9572653ee01a2134ae3a1d7aa29ce9d026a6afe9 (patch) | |
tree | c136d6fbcd38eff44473abc6f4d6262181b63c3e /arch/powerpc/sysdev | |
parent | 5e41486c408eb4206aee09303631427f57771691 (diff) |
powerpc/QE: prepare QE PIO code for GPIO LIB support
- split and export __par_io_config_pin() out of par_io_config_pin(), so we
could use the prefixed version with GPIO LIB API;
- rename struct port_regs to qe_pio_regs, and place it into qe.h;
- rename #define NUM_OF_PINS to QE_PIO_PINS, and place it into qe.h.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-By: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r-- | arch/powerpc/sysdev/qe_lib/qe_io.c | 94 |
1 files changed, 45 insertions, 49 deletions
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c index 93916a48afec..7c87460179ef 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_io.c +++ b/arch/powerpc/sysdev/qe_lib/qe_io.c | |||
@@ -28,21 +28,7 @@ | |||
28 | 28 | ||
29 | #undef DEBUG | 29 | #undef DEBUG |
30 | 30 | ||
31 | #define NUM_OF_PINS 32 | 31 | static struct qe_pio_regs __iomem *par_io; |
32 | |||
33 | struct port_regs { | ||
34 | __be32 cpodr; /* Open drain register */ | ||
35 | __be32 cpdata; /* Data register */ | ||
36 | __be32 cpdir1; /* Direction register */ | ||
37 | __be32 cpdir2; /* Direction register */ | ||
38 | __be32 cppar1; /* Pin assignment register */ | ||
39 | __be32 cppar2; /* Pin assignment register */ | ||
40 | #ifdef CONFIG_PPC_85xx | ||
41 | u8 pad[8]; | ||
42 | #endif | ||
43 | }; | ||
44 | |||
45 | static struct port_regs __iomem *par_io; | ||
46 | static int num_par_io_ports = 0; | 32 | static int num_par_io_ports = 0; |
47 | 33 | ||
48 | int par_io_init(struct device_node *np) | 34 | int par_io_init(struct device_node *np) |
@@ -64,69 +50,79 @@ int par_io_init(struct device_node *np) | |||
64 | return 0; | 50 | return 0; |
65 | } | 51 | } |
66 | 52 | ||
67 | int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | 53 | void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, |
68 | int assignment, int has_irq) | 54 | int open_drain, int assignment, int has_irq) |
69 | { | 55 | { |
70 | u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val; | 56 | u32 pin_mask1bit; |
71 | 57 | u32 pin_mask2bits; | |
72 | if (!par_io) | 58 | u32 new_mask2bits; |
73 | return -1; | 59 | u32 tmp_val; |
74 | 60 | ||
75 | /* calculate pin location for single and 2 bits information */ | 61 | /* calculate pin location for single and 2 bits information */ |
76 | pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1))); | 62 | pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); |
77 | 63 | ||
78 | /* Set open drain, if required */ | 64 | /* Set open drain, if required */ |
79 | tmp_val = in_be32(&par_io[port].cpodr); | 65 | tmp_val = in_be32(&par_io->cpodr); |
80 | if (open_drain) | 66 | if (open_drain) |
81 | out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val); | 67 | out_be32(&par_io->cpodr, pin_mask1bit | tmp_val); |
82 | else | 68 | else |
83 | out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val); | 69 | out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val); |
84 | 70 | ||
85 | /* define direction */ | 71 | /* define direction */ |
86 | tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? | 72 | tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? |
87 | in_be32(&par_io[port].cpdir2) : | 73 | in_be32(&par_io->cpdir2) : |
88 | in_be32(&par_io[port].cpdir1); | 74 | in_be32(&par_io->cpdir1); |
89 | 75 | ||
90 | /* get all bits mask for 2 bit per port */ | 76 | /* get all bits mask for 2 bit per port */ |
91 | pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS - | 77 | pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - |
92 | (pin % (NUM_OF_PINS / 2) + 1) * 2)); | 78 | (pin % (QE_PIO_PINS / 2) + 1) * 2)); |
93 | 79 | ||
94 | /* Get the final mask we need for the right definition */ | 80 | /* Get the final mask we need for the right definition */ |
95 | new_mask2bits = (u32) (dir << (NUM_OF_PINS - | 81 | new_mask2bits = (u32) (dir << (QE_PIO_PINS - |
96 | (pin % (NUM_OF_PINS / 2) + 1) * 2)); | 82 | (pin % (QE_PIO_PINS / 2) + 1) * 2)); |
97 | 83 | ||
98 | /* clear and set 2 bits mask */ | 84 | /* clear and set 2 bits mask */ |
99 | if (pin > (NUM_OF_PINS / 2) - 1) { | 85 | if (pin > (QE_PIO_PINS / 2) - 1) { |
100 | out_be32(&par_io[port].cpdir2, | 86 | out_be32(&par_io->cpdir2, |
101 | ~pin_mask2bits & tmp_val); | 87 | ~pin_mask2bits & tmp_val); |
102 | tmp_val &= ~pin_mask2bits; | 88 | tmp_val &= ~pin_mask2bits; |
103 | out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val); | 89 | out_be32(&par_io->cpdir2, new_mask2bits | tmp_val); |
104 | } else { | 90 | } else { |
105 | out_be32(&par_io[port].cpdir1, | 91 | out_be32(&par_io->cpdir1, |
106 | ~pin_mask2bits & tmp_val); | 92 | ~pin_mask2bits & tmp_val); |
107 | tmp_val &= ~pin_mask2bits; | 93 | tmp_val &= ~pin_mask2bits; |
108 | out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val); | 94 | out_be32(&par_io->cpdir1, new_mask2bits | tmp_val); |
109 | } | 95 | } |
110 | /* define pin assignment */ | 96 | /* define pin assignment */ |
111 | tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? | 97 | tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? |
112 | in_be32(&par_io[port].cppar2) : | 98 | in_be32(&par_io->cppar2) : |
113 | in_be32(&par_io[port].cppar1); | 99 | in_be32(&par_io->cppar1); |
114 | 100 | ||
115 | new_mask2bits = (u32) (assignment << (NUM_OF_PINS - | 101 | new_mask2bits = (u32) (assignment << (QE_PIO_PINS - |
116 | (pin % (NUM_OF_PINS / 2) + 1) * 2)); | 102 | (pin % (QE_PIO_PINS / 2) + 1) * 2)); |
117 | /* clear and set 2 bits mask */ | 103 | /* clear and set 2 bits mask */ |
118 | if (pin > (NUM_OF_PINS / 2) - 1) { | 104 | if (pin > (QE_PIO_PINS / 2) - 1) { |
119 | out_be32(&par_io[port].cppar2, | 105 | out_be32(&par_io->cppar2, |
120 | ~pin_mask2bits & tmp_val); | 106 | ~pin_mask2bits & tmp_val); |
121 | tmp_val &= ~pin_mask2bits; | 107 | tmp_val &= ~pin_mask2bits; |
122 | out_be32(&par_io[port].cppar2, new_mask2bits | tmp_val); | 108 | out_be32(&par_io->cppar2, new_mask2bits | tmp_val); |
123 | } else { | 109 | } else { |
124 | out_be32(&par_io[port].cppar1, | 110 | out_be32(&par_io->cppar1, |
125 | ~pin_mask2bits & tmp_val); | 111 | ~pin_mask2bits & tmp_val); |
126 | tmp_val &= ~pin_mask2bits; | 112 | tmp_val &= ~pin_mask2bits; |
127 | out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val); | 113 | out_be32(&par_io->cppar1, new_mask2bits | tmp_val); |
128 | } | 114 | } |
115 | } | ||
116 | EXPORT_SYMBOL(__par_io_config_pin); | ||
117 | |||
118 | int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | ||
119 | int assignment, int has_irq) | ||
120 | { | ||
121 | if (!par_io || port >= num_par_io_ports) | ||
122 | return -EINVAL; | ||
129 | 123 | ||
124 | __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment, | ||
125 | has_irq); | ||
130 | return 0; | 126 | return 0; |
131 | } | 127 | } |
132 | EXPORT_SYMBOL(par_io_config_pin); | 128 | EXPORT_SYMBOL(par_io_config_pin); |
@@ -137,10 +133,10 @@ int par_io_data_set(u8 port, u8 pin, u8 val) | |||
137 | 133 | ||
138 | if (port >= num_par_io_ports) | 134 | if (port >= num_par_io_ports) |
139 | return -EINVAL; | 135 | return -EINVAL; |
140 | if (pin >= NUM_OF_PINS) | 136 | if (pin >= QE_PIO_PINS) |
141 | return -EINVAL; | 137 | return -EINVAL; |
142 | /* calculate pin location */ | 138 | /* calculate pin location */ |
143 | pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin)); | 139 | pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); |
144 | 140 | ||
145 | tmp_val = in_be32(&par_io[port].cpdata); | 141 | tmp_val = in_be32(&par_io[port].cpdata); |
146 | 142 | ||