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authorJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:15 -0400
committerJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:59 -0400
commit07f9479a40cc778bc1462ada11f95b01360ae4ff (patch)
tree0676cf38df3844004bb3ebfd99dfa67a4a8998f5 /arch/powerpc/sysdev
parent9d5e6bdb3013acfb311ab407eeca0b6a6a3dedbf (diff)
parentcd2e49e90f1cae7726c9a2c54488d881d7f1cd1c (diff)
Merge branch 'master' into for-next
Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/Makefile2
-rw-r--r--arch/powerpc/sysdev/axonram.c2
-rw-r--r--arch/powerpc/sysdev/bestcomm/bestcomm.h2
-rw-r--r--arch/powerpc/sysdev/bestcomm/bestcomm_priv.h2
-rw-r--r--arch/powerpc/sysdev/cpm1.c6
-rw-r--r--arch/powerpc/sysdev/cpm2_pic.c47
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c43
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c5
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c100
-rw-r--r--arch/powerpc/sysdev/i8259.c8
-rw-r--r--arch/powerpc/sysdev/indirect_pci.c2
-rw-r--r--arch/powerpc/sysdev/ipic.c22
-rw-r--r--arch/powerpc/sysdev/mpc8xx_pic.c11
-rw-r--r--arch/powerpc/sysdev/mpc8xxx_gpio.c12
-rw-r--r--arch/powerpc/sysdev/mpic.c128
-rw-r--r--arch/powerpc/sysdev/mpic_pasemi_msi.c8
-rw-r--r--arch/powerpc/sysdev/mpic_u3msi.c8
-rw-r--r--arch/powerpc/sysdev/mv64x60_pic.c5
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h2
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_ic.c16
-rw-r--r--arch/powerpc/sysdev/tsi108_pci.c6
-rw-r--r--arch/powerpc/sysdev/uic.c41
-rw-r--r--arch/powerpc/sysdev/xilinx_intc.c20
23 files changed, 246 insertions, 252 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9c2973479142..1e0c933ef772 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
20obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o 20obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o 21obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o 22obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
23obj-$(CONFIG_RAPIDIO) += fsl_rio.o 23obj-$(CONFIG_FSL_RIO) += fsl_rio.o
24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 24obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
25obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 25obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
26obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ 26obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index 27402c7d309d..1636dd896707 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -95,7 +95,7 @@ axon_ram_irq_handler(int irq, void *dev)
95 95
96 BUG_ON(!bank); 96 BUG_ON(!bank);
97 97
98 dev_err(&device->dev, "Correctable memory error occured\n"); 98 dev_err(&device->dev, "Correctable memory error occurred\n");
99 bank->ecc_counter++; 99 bank->ecc_counter++;
100 return IRQ_HANDLED; 100 return IRQ_HANDLED;
101} 101}
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.h b/arch/powerpc/sysdev/bestcomm/bestcomm.h
index 23a95f80dfdb..a0e2e6b19b57 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.h
+++ b/arch/powerpc/sysdev/bestcomm/bestcomm.h
@@ -20,7 +20,7 @@
20 * struct bcom_bd - Structure describing a generic BestComm buffer descriptor 20 * struct bcom_bd - Structure describing a generic BestComm buffer descriptor
21 * @status: The current status of this buffer. Exact meaning depends on the 21 * @status: The current status of this buffer. Exact meaning depends on the
22 * task type 22 * task type
23 * @data: An array of u32 extra data. Size of array is task dependant. 23 * @data: An array of u32 extra data. Size of array is task dependent.
24 * 24 *
25 * Note: Don't dereference a bcom_bd pointer as an array. The size of the 25 * Note: Don't dereference a bcom_bd pointer as an array. The size of the
26 * bcom_bd is variable. Use bcom_get_bd() instead. 26 * bcom_bd is variable. Use bcom_get_bd() instead.
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h b/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
index eb0d1c883c31..3b52f3ffbdf8 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
+++ b/arch/powerpc/sysdev/bestcomm/bestcomm_priv.h
@@ -97,7 +97,7 @@ struct bcom_task_header {
97 u8 reserved[8]; 97 u8 reserved[8];
98}; 98};
99 99
100/* Descriptors stucture & co */ 100/* Descriptors structure & co */
101#define BCOM_DESC_NOP 0x000001f8 101#define BCOM_DESC_NOP 0x000001f8
102#define BCOM_LCD_MASK 0x80000000 102#define BCOM_LCD_MASK 0x80000000
103#define BCOM_DRD_EXTENDED 0x40000000 103#define BCOM_DRD_EXTENDED 0x40000000
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 0476bcc7c3e1..e0bc944eb23f 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -103,8 +103,8 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
103{ 103{
104 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); 104 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
105 105
106 irq_to_desc(virq)->status |= IRQ_LEVEL; 106 irq_set_status_flags(virq, IRQ_LEVEL);
107 set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); 107 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
108 return 0; 108 return 0;
109} 109}
110 110
@@ -223,7 +223,7 @@ void __init cpm_reset(void)
223 223
224 /* Set SDMA Bus Request priority 5. 224 /* Set SDMA Bus Request priority 5.
225 * On 860T, this also enables FEC priority 6. I am not sure 225 * On 860T, this also enables FEC priority 6. I am not sure
226 * this is what we realy want for some applications, but the 226 * this is what we really want for some applications, but the
227 * manual recommends it. 227 * manual recommends it.
228 * Bit 25, FAM can also be set to use FEC aggressive mode (860T). 228 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
229 */ 229 */
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 473032556715..5495c1be472b 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -115,32 +115,25 @@ static void cpm2_ack(struct irq_data *d)
115 115
116static void cpm2_end_irq(struct irq_data *d) 116static void cpm2_end_irq(struct irq_data *d)
117{ 117{
118 struct irq_desc *desc;
119 int bit, word; 118 int bit, word;
120 unsigned int irq_nr = virq_to_hw(d->irq); 119 unsigned int irq_nr = virq_to_hw(d->irq);
121 120
122 desc = irq_to_desc(irq_nr); 121 bit = irq_to_siubit[irq_nr];
123 if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) 122 word = irq_to_siureg[irq_nr];
124 && desc->action) {
125
126 bit = irq_to_siubit[irq_nr];
127 word = irq_to_siureg[irq_nr];
128 123
129 ppc_cached_irq_mask[word] |= 1 << bit; 124 ppc_cached_irq_mask[word] |= 1 << bit;
130 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 125 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
131 126
132 /* 127 /*
133 * Work around large numbers of spurious IRQs on PowerPC 82xx 128 * Work around large numbers of spurious IRQs on PowerPC 82xx
134 * systems. 129 * systems.
135 */ 130 */
136 mb(); 131 mb();
137 }
138} 132}
139 133
140static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) 134static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
141{ 135{
142 unsigned int src = virq_to_hw(d->irq); 136 unsigned int src = virq_to_hw(d->irq);
143 struct irq_desc *desc = irq_to_desc(d->irq);
144 unsigned int vold, vnew, edibit; 137 unsigned int vold, vnew, edibit;
145 138
146 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or 139 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
@@ -162,13 +155,11 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
162 goto err_sense; 155 goto err_sense;
163 } 156 }
164 157
165 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 158 irqd_set_trigger_type(d, flow_type);
166 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 159 if (flow_type & IRQ_TYPE_LEVEL_LOW)
167 if (flow_type & IRQ_TYPE_LEVEL_LOW) { 160 __irq_set_handler_locked(d->irq, handle_level_irq);
168 desc->status |= IRQ_LEVEL; 161 else
169 desc->handle_irq = handle_level_irq; 162 __irq_set_handler_locked(d->irq, handle_edge_irq);
170 } else
171 desc->handle_irq = handle_edge_irq;
172 163
173 /* internal IRQ senses are LEVEL_LOW 164 /* internal IRQ senses are LEVEL_LOW
174 * EXT IRQ and Port C IRQ senses are programmable 165 * EXT IRQ and Port C IRQ senses are programmable
@@ -179,7 +170,8 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
179 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) 170 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
180 edibit = (31 - (CPM2_IRQ_PORTC0 - src)); 171 edibit = (31 - (CPM2_IRQ_PORTC0 - src));
181 else 172 else
182 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; 173 return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
174 IRQ_SET_MASK_OK_NOCOPY : -EINVAL;
183 175
184 vold = in_be32(&cpm2_intctl->ic_siexr); 176 vold = in_be32(&cpm2_intctl->ic_siexr);
185 177
@@ -190,7 +182,7 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
190 182
191 if (vold != vnew) 183 if (vold != vnew)
192 out_be32(&cpm2_intctl->ic_siexr, vnew); 184 out_be32(&cpm2_intctl->ic_siexr, vnew);
193 return 0; 185 return IRQ_SET_MASK_OK_NOCOPY;
194 186
195err_sense: 187err_sense:
196 pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); 188 pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
@@ -204,6 +196,7 @@ static struct irq_chip cpm2_pic = {
204 .irq_ack = cpm2_ack, 196 .irq_ack = cpm2_ack,
205 .irq_eoi = cpm2_end_irq, 197 .irq_eoi = cpm2_end_irq,
206 .irq_set_type = cpm2_set_irq_type, 198 .irq_set_type = cpm2_set_irq_type,
199 .flags = IRQCHIP_EOI_IF_HANDLED,
207}; 200};
208 201
209unsigned int cpm2_get_irq(void) 202unsigned int cpm2_get_irq(void)
@@ -226,8 +219,8 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
226{ 219{
227 pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); 220 pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
228 221
229 irq_to_desc(virq)->status |= IRQ_LEVEL; 222 irq_set_status_flags(virq, IRQ_LEVEL);
230 set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq); 223 irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
231 return 0; 224 return 0;
232} 225}
233 226
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 58e09b2833f2..d5679dc1e20f 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -64,10 +64,10 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
64 struct fsl_msi *msi_data = h->host_data; 64 struct fsl_msi *msi_data = h->host_data;
65 struct irq_chip *chip = &fsl_msi_chip; 65 struct irq_chip *chip = &fsl_msi_chip;
66 66
67 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; 67 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
68 68
69 set_irq_chip_data(virq, msi_data); 69 irq_set_chip_data(virq, msi_data);
70 set_irq_chip_and_handler(virq, chip, handle_edge_irq); 70 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
71 71
72 return 0; 72 return 0;
73} 73}
@@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
110 list_for_each_entry(entry, &pdev->msi_list, list) { 110 list_for_each_entry(entry, &pdev->msi_list, list) {
111 if (entry->irq == NO_IRQ) 111 if (entry->irq == NO_IRQ)
112 continue; 112 continue;
113 msi_data = get_irq_data(entry->irq); 113 msi_data = irq_get_handler_data(entry->irq);
114 set_irq_msi(entry->irq, NULL); 114 irq_set_msi_desc(entry->irq, NULL);
115 msi_bitmap_free_hwirqs(&msi_data->bitmap, 115 msi_bitmap_free_hwirqs(&msi_data->bitmap,
116 virq_to_hw(entry->irq), 1); 116 virq_to_hw(entry->irq), 1);
117 irq_dispose_mapping(entry->irq); 117 irq_dispose_mapping(entry->irq);
@@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
168 rc = -ENOSPC; 168 rc = -ENOSPC;
169 goto out_free; 169 goto out_free;
170 } 170 }
171 set_irq_data(virq, msi_data); 171 irq_set_handler_data(virq, msi_data);
172 set_irq_msi(virq, entry); 172 irq_set_msi_desc(virq, entry);
173 173
174 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); 174 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
175 write_msi_msg(virq, &msg); 175 write_msi_msg(virq, &msg);
@@ -183,7 +183,8 @@ out_free:
183 183
184static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) 184static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
185{ 185{
186 struct irq_chip *chip = get_irq_desc_chip(desc); 186 struct irq_chip *chip = irq_desc_get_chip(desc);
187 struct irq_data *idata = irq_desc_get_irq_data(desc);
187 unsigned int cascade_irq; 188 unsigned int cascade_irq;
188 struct fsl_msi *msi_data; 189 struct fsl_msi *msi_data;
189 int msir_index = -1; 190 int msir_index = -1;
@@ -192,20 +193,20 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
192 u32 have_shift = 0; 193 u32 have_shift = 0;
193 struct fsl_msi_cascade_data *cascade_data; 194 struct fsl_msi_cascade_data *cascade_data;
194 195
195 cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq); 196 cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq);
196 msi_data = cascade_data->msi_data; 197 msi_data = cascade_data->msi_data;
197 198
198 raw_spin_lock(&desc->lock); 199 raw_spin_lock(&desc->lock);
199 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { 200 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
200 if (chip->irq_mask_ack) 201 if (chip->irq_mask_ack)
201 chip->irq_mask_ack(&desc->irq_data); 202 chip->irq_mask_ack(idata);
202 else { 203 else {
203 chip->irq_mask(&desc->irq_data); 204 chip->irq_mask(idata);
204 chip->irq_ack(&desc->irq_data); 205 chip->irq_ack(idata);
205 } 206 }
206 } 207 }
207 208
208 if (unlikely(desc->status & IRQ_INPROGRESS)) 209 if (unlikely(irqd_irq_inprogress(idata)))
209 goto unlock; 210 goto unlock;
210 211
211 msir_index = cascade_data->index; 212 msir_index = cascade_data->index;
@@ -213,7 +214,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
213 if (msir_index >= NR_MSI_REG) 214 if (msir_index >= NR_MSI_REG)
214 cascade_irq = NO_IRQ; 215 cascade_irq = NO_IRQ;
215 216
216 desc->status |= IRQ_INPROGRESS; 217 irqd_set_chained_irq_inprogress(idata);
217 switch (msi_data->feature & FSL_PIC_IP_MASK) { 218 switch (msi_data->feature & FSL_PIC_IP_MASK) {
218 case FSL_PIC_IP_MPIC: 219 case FSL_PIC_IP_MPIC:
219 msir_value = fsl_msi_read(msi_data->msi_regs, 220 msir_value = fsl_msi_read(msi_data->msi_regs,
@@ -235,15 +236,15 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
235 have_shift += intr_index + 1; 236 have_shift += intr_index + 1;
236 msir_value = msir_value >> (intr_index + 1); 237 msir_value = msir_value >> (intr_index + 1);
237 } 238 }
238 desc->status &= ~IRQ_INPROGRESS; 239 irqd_clr_chained_irq_inprogress(idata);
239 240
240 switch (msi_data->feature & FSL_PIC_IP_MASK) { 241 switch (msi_data->feature & FSL_PIC_IP_MASK) {
241 case FSL_PIC_IP_MPIC: 242 case FSL_PIC_IP_MPIC:
242 chip->irq_eoi(&desc->irq_data); 243 chip->irq_eoi(idata);
243 break; 244 break;
244 case FSL_PIC_IP_IPIC: 245 case FSL_PIC_IP_IPIC:
245 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) 246 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
246 chip->irq_unmask(&desc->irq_data); 247 chip->irq_unmask(idata);
247 break; 248 break;
248 } 249 }
249unlock: 250unlock:
@@ -261,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
261 for (i = 0; i < NR_MSI_REG; i++) { 262 for (i = 0; i < NR_MSI_REG; i++) {
262 virq = msi->msi_virqs[i]; 263 virq = msi->msi_virqs[i];
263 if (virq != NO_IRQ) { 264 if (virq != NO_IRQ) {
264 cascade_data = get_irq_data(virq); 265 cascade_data = irq_get_handler_data(virq);
265 kfree(cascade_data); 266 kfree(cascade_data);
266 irq_dispose_mapping(virq); 267 irq_dispose_mapping(virq);
267 } 268 }
@@ -297,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
297 msi->msi_virqs[irq_index] = virt_msir; 298 msi->msi_virqs[irq_index] = virt_msir;
298 cascade_data->index = offset + irq_index; 299 cascade_data->index = offset + irq_index;
299 cascade_data->msi_data = msi; 300 cascade_data->msi_data = msi;
300 set_irq_data(virt_msir, cascade_data); 301 irq_set_handler_data(virt_msir, cascade_data);
301 set_irq_chained_handler(virt_msir, fsl_msi_cascade); 302 irq_set_chained_handler(virt_msir, fsl_msi_cascade);
302 303
303 return 0; 304 return 0;
304} 305}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f8f7f28c6343..68ca9290df94 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -324,6 +324,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
324 struct resource rsrc; 324 struct resource rsrc;
325 const int *bus_range; 325 const int *bus_range;
326 326
327 if (!of_device_is_available(dev)) {
328 pr_warning("%s: disabled\n", dev->full_name);
329 return -ENODEV;
330 }
331
327 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 332 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
328 333
329 /* Fetch host bridge registers address */ 334 /* Fetch host bridge registers address */
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 3eff2c3a9ad5..49798532b477 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -482,7 +482,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
482} 482}
483 483
484/** 484/**
485 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue 485 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
486 * @mport: Master port with outbound message queue 486 * @mport: Master port with outbound message queue
487 * @rdev: Target of outbound message 487 * @rdev: Target of outbound message
488 * @mbox: Outbound mailbox 488 * @mbox: Outbound mailbox
@@ -492,8 +492,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
492 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 492 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
493 * %0 on success or %-EINVAL on failure. 493 * %0 on success or %-EINVAL on failure.
494 */ 494 */
495int 495static int
496rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 496fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
497 void *buffer, size_t len) 497 void *buffer, size_t len)
498{ 498{
499 struct rio_priv *priv = mport->priv; 499 struct rio_priv *priv = mport->priv;
@@ -502,9 +502,8 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
502 + priv->msg_tx_ring.tx_slot; 502 + priv->msg_tx_ring.tx_slot;
503 int ret = 0; 503 int ret = 0;
504 504
505 pr_debug 505 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
506 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", 506 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
507 rdev->destid, mbox, (int)buffer, len);
508 507
509 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 508 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
510 ret = -EINVAL; 509 ret = -EINVAL;
@@ -554,8 +553,6 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
554 return ret; 553 return ret;
555} 554}
556 555
557EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
558
559/** 556/**
560 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 557 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
561 * @irq: Linux interrupt number 558 * @irq: Linux interrupt number
@@ -600,7 +597,7 @@ fsl_rio_tx_handler(int irq, void *dev_instance)
600} 597}
601 598
602/** 599/**
603 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox 600 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
604 * @mport: Master port implementing the outbound message unit 601 * @mport: Master port implementing the outbound message unit
605 * @dev_id: Device specific pointer to pass on event 602 * @dev_id: Device specific pointer to pass on event
606 * @mbox: Mailbox to open 603 * @mbox: Mailbox to open
@@ -610,7 +607,8 @@ fsl_rio_tx_handler(int irq, void *dev_instance)
610 * and enables the outbound message unit. Returns %0 on success and 607 * and enables the outbound message unit. Returns %0 on success and
611 * %-EINVAL or %-ENOMEM on failure. 608 * %-EINVAL or %-ENOMEM on failure.
612 */ 609 */
613int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 610static int
611fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
614{ 612{
615 int i, j, rc = 0; 613 int i, j, rc = 0;
616 struct rio_priv *priv = mport->priv; 614 struct rio_priv *priv = mport->priv;
@@ -706,14 +704,14 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr
706} 704}
707 705
708/** 706/**
709 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox 707 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
710 * @mport: Master port implementing the outbound message unit 708 * @mport: Master port implementing the outbound message unit
711 * @mbox: Mailbox to close 709 * @mbox: Mailbox to close
712 * 710 *
713 * Disables the outbound message unit, free all buffers, and 711 * Disables the outbound message unit, free all buffers, and
714 * frees the outbound message interrupt. 712 * frees the outbound message interrupt.
715 */ 713 */
716void rio_close_outb_mbox(struct rio_mport *mport, int mbox) 714static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
717{ 715{
718 struct rio_priv *priv = mport->priv; 716 struct rio_priv *priv = mport->priv;
719 /* Disable inbound message unit */ 717 /* Disable inbound message unit */
@@ -770,7 +768,7 @@ fsl_rio_rx_handler(int irq, void *dev_instance)
770} 768}
771 769
772/** 770/**
773 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox 771 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
774 * @mport: Master port implementing the inbound message unit 772 * @mport: Master port implementing the inbound message unit
775 * @dev_id: Device specific pointer to pass on event 773 * @dev_id: Device specific pointer to pass on event
776 * @mbox: Mailbox to open 774 * @mbox: Mailbox to open
@@ -780,7 +778,8 @@ fsl_rio_rx_handler(int irq, void *dev_instance)
780 * and enables the inbound message unit. Returns %0 on success 778 * and enables the inbound message unit. Returns %0 on success
781 * and %-EINVAL or %-ENOMEM on failure. 779 * and %-EINVAL or %-ENOMEM on failure.
782 */ 780 */
783int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 781static int
782fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
784{ 783{
785 int i, rc = 0; 784 int i, rc = 0;
786 struct rio_priv *priv = mport->priv; 785 struct rio_priv *priv = mport->priv;
@@ -844,14 +843,14 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri
844} 843}
845 844
846/** 845/**
847 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox 846 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
848 * @mport: Master port implementing the inbound message unit 847 * @mport: Master port implementing the inbound message unit
849 * @mbox: Mailbox to close 848 * @mbox: Mailbox to close
850 * 849 *
851 * Disables the inbound message unit, free all buffers, and 850 * Disables the inbound message unit, free all buffers, and
852 * frees the inbound message interrupt. 851 * frees the inbound message interrupt.
853 */ 852 */
854void rio_close_inb_mbox(struct rio_mport *mport, int mbox) 853static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
855{ 854{
856 struct rio_priv *priv = mport->priv; 855 struct rio_priv *priv = mport->priv;
857 /* Disable inbound message unit */ 856 /* Disable inbound message unit */
@@ -866,7 +865,7 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
866} 865}
867 866
868/** 867/**
869 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 868 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
870 * @mport: Master port implementing the inbound message unit 869 * @mport: Master port implementing the inbound message unit
871 * @mbox: Inbound mailbox number 870 * @mbox: Inbound mailbox number
872 * @buf: Buffer to add to inbound queue 871 * @buf: Buffer to add to inbound queue
@@ -874,12 +873,12 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
874 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 873 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
875 * %0 on success or %-EINVAL on failure. 874 * %0 on success or %-EINVAL on failure.
876 */ 875 */
877int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 876static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
878{ 877{
879 int rc = 0; 878 int rc = 0;
880 struct rio_priv *priv = mport->priv; 879 struct rio_priv *priv = mport->priv;
881 880
882 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 881 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
883 priv->msg_rx_ring.rx_slot); 882 priv->msg_rx_ring.rx_slot);
884 883
885 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 884 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
@@ -898,17 +897,15 @@ int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
898 return rc; 897 return rc;
899} 898}
900 899
901EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
902
903/** 900/**
904 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit 901 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
905 * @mport: Master port implementing the inbound message unit 902 * @mport: Master port implementing the inbound message unit
906 * @mbox: Inbound mailbox number 903 * @mbox: Inbound mailbox number
907 * 904 *
908 * Gets the next available inbound message from the inbound message queue. 905 * Gets the next available inbound message from the inbound message queue.
909 * A pointer to the message is returned on success or NULL on failure. 906 * A pointer to the message is returned on success or NULL on failure.
910 */ 907 */
911void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) 908static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
912{ 909{
913 struct rio_priv *priv = mport->priv; 910 struct rio_priv *priv = mport->priv;
914 u32 phys_buf, virt_buf; 911 u32 phys_buf, virt_buf;
@@ -945,8 +942,6 @@ void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
945 return buf; 942 return buf;
946} 943}
947 944
948EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
949
950/** 945/**
951 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 946 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
952 * @irq: Linux interrupt number 947 * @irq: Linux interrupt number
@@ -1293,28 +1288,6 @@ err_out:
1293 return rc; 1288 return rc;
1294} 1289}
1295 1290
1296static char *cmdline = NULL;
1297
1298static int fsl_rio_get_hdid(int index)
1299{
1300 /* XXX Need to parse multiple entries in some format */
1301 if (!cmdline)
1302 return -1;
1303
1304 return simple_strtol(cmdline, NULL, 0);
1305}
1306
1307static int fsl_rio_get_cmdline(char *s)
1308{
1309 if (!s)
1310 return 0;
1311
1312 cmdline = s;
1313 return 1;
1314}
1315
1316__setup("riohdid=", fsl_rio_get_cmdline);
1317
1318static inline void fsl_rio_info(struct device *dev, u32 ccsr) 1291static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1319{ 1292{
1320 const char *str; 1293 const char *str;
@@ -1431,13 +1404,19 @@ int fsl_rio_setup(struct platform_device *dev)
1431 ops->cwrite = fsl_rio_config_write; 1404 ops->cwrite = fsl_rio_config_write;
1432 ops->dsend = fsl_rio_doorbell_send; 1405 ops->dsend = fsl_rio_doorbell_send;
1433 ops->pwenable = fsl_rio_pw_enable; 1406 ops->pwenable = fsl_rio_pw_enable;
1407 ops->open_outb_mbox = fsl_open_outb_mbox;
1408 ops->open_inb_mbox = fsl_open_inb_mbox;
1409 ops->close_outb_mbox = fsl_close_outb_mbox;
1410 ops->close_inb_mbox = fsl_close_inb_mbox;
1411 ops->add_outb_message = fsl_add_outb_message;
1412 ops->add_inb_buffer = fsl_add_inb_buffer;
1413 ops->get_inb_message = fsl_get_inb_message;
1434 1414
1435 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 1415 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1436 if (!port) { 1416 if (!port) {
1437 rc = -ENOMEM; 1417 rc = -ENOMEM;
1438 goto err_port; 1418 goto err_port;
1439 } 1419 }
1440 port->id = 0;
1441 port->index = 0; 1420 port->index = 0;
1442 1421
1443 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); 1422 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
@@ -1453,6 +1432,14 @@ int fsl_rio_setup(struct platform_device *dev)
1453 port->iores.flags = IORESOURCE_MEM; 1432 port->iores.flags = IORESOURCE_MEM;
1454 port->iores.name = "rio_io_win"; 1433 port->iores.name = "rio_io_win";
1455 1434
1435 if (request_resource(&iomem_resource, &port->iores) < 0) {
1436 dev_err(&dev->dev, "RIO: Error requesting master port region"
1437 " 0x%016llx-0x%016llx\n",
1438 (u64)port->iores.start, (u64)port->iores.end);
1439 rc = -ENOMEM;
1440 goto err_res;
1441 }
1442
1456 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 1443 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1457 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 1444 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1458 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 1445 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
@@ -1468,11 +1455,8 @@ int fsl_rio_setup(struct platform_device *dev)
1468 priv->dev = &dev->dev; 1455 priv->dev = &dev->dev;
1469 1456
1470 port->ops = ops; 1457 port->ops = ops;
1471 port->host_deviceid = fsl_rio_get_hdid(port->id);
1472
1473 port->priv = priv; 1458 port->priv = priv;
1474 port->phys_efptr = 0x100; 1459 port->phys_efptr = 0x100;
1475 rio_register_mport(port);
1476 1460
1477 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1461 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1478 rio_regs_win = priv->regs_win; 1462 rio_regs_win = priv->regs_win;
@@ -1519,6 +1503,9 @@ int fsl_rio_setup(struct platform_device *dev)
1519 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1503 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1520 port->sys_size ? 65536 : 256); 1504 port->sys_size ? 65536 : 256);
1521 1505
1506 if (rio_register_mport(port))
1507 goto err;
1508
1522 if (port->host_deviceid >= 0) 1509 if (port->host_deviceid >= 0)
1523 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 1510 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
1524 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); 1511 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
@@ -1559,6 +1546,7 @@ int fsl_rio_setup(struct platform_device *dev)
1559 return 0; 1546 return 0;
1560err: 1547err:
1561 iounmap(priv->regs_win); 1548 iounmap(priv->regs_win);
1549err_res:
1562 kfree(priv); 1550 kfree(priv);
1563err_priv: 1551err_priv:
1564 kfree(port); 1552 kfree(port);
@@ -1572,18 +1560,10 @@ err_ops:
1572 */ 1560 */
1573static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) 1561static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
1574{ 1562{
1575 int rc;
1576 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", 1563 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1577 dev->dev.of_node->full_name); 1564 dev->dev.of_node->full_name);
1578 1565
1579 rc = fsl_rio_setup(dev); 1566 return fsl_rio_setup(dev);
1580 if (rc)
1581 goto out;
1582
1583 /* Enumerate all registered ports */
1584 rc = rio_init_mports();
1585out:
1586 return rc;
1587}; 1567};
1588 1568
1589static const struct of_device_id fsl_of_rio_rpn_ids[] = { 1569static const struct of_device_id fsl_of_rio_rpn_ids[] = {
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index aeda4c8d0a0a..142770cb84b6 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -175,13 +175,13 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
175 175
176 /* We block the internal cascade */ 176 /* We block the internal cascade */
177 if (hw == 2) 177 if (hw == 2)
178 irq_to_desc(virq)->status |= IRQ_NOREQUEST; 178 irq_set_status_flags(virq, IRQ_NOREQUEST);
179 179
180 /* We use the level handler only for now, we might want to 180 /* We use the level handler only for now, we might want to
181 * be more cautious here but that works for now 181 * be more cautious here but that works for now
182 */ 182 */
183 irq_to_desc(virq)->status |= IRQ_LEVEL; 183 irq_set_status_flags(virq, IRQ_LEVEL);
184 set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); 184 irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
185 return 0; 185 return 0;
186} 186}
187 187
@@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
191 i8259_mask_irq(irq_get_irq_data(virq)); 191 i8259_mask_irq(irq_get_irq_data(virq));
192 192
193 /* remove chip and handler */ 193 /* remove chip and handler */
194 set_irq_chip_and_handler(virq, NULL, NULL); 194 irq_set_chip_and_handler(virq, NULL, NULL);
195 195
196 /* Make sure it's completed */ 196 /* Make sure it's completed */
197 synchronize_irq(virq); 197 synchronize_irq(virq);
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 7ed809676642..82fdad885d20 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -117,7 +117,7 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
117 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | 117 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
118 (devfn << 8) | reg | cfg_type)); 118 (devfn << 8) | reg | cfg_type));
119 119
120 /* surpress setting of PCI_PRIMARY_BUS */ 120 /* suppress setting of PCI_PRIMARY_BUS */
121 if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) 121 if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
122 if ((offset == PCI_PRIMARY_BUS) && 122 if ((offset == PCI_PRIMARY_BUS) &&
123 (bus->number == hose->first_busno)) 123 (bus->number == hose->first_busno))
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 497047dc986e..fa438be962b7 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -605,7 +605,6 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
605{ 605{
606 struct ipic *ipic = ipic_from_irq(d->irq); 606 struct ipic *ipic = ipic_from_irq(d->irq);
607 unsigned int src = ipic_irq_to_hw(d->irq); 607 unsigned int src = ipic_irq_to_hw(d->irq);
608 struct irq_desc *desc = irq_to_desc(d->irq);
609 unsigned int vold, vnew, edibit; 608 unsigned int vold, vnew, edibit;
610 609
611 if (flow_type == IRQ_TYPE_NONE) 610 if (flow_type == IRQ_TYPE_NONE)
@@ -623,17 +622,16 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
623 printk(KERN_ERR "ipic: edge sense not supported on internal " 622 printk(KERN_ERR "ipic: edge sense not supported on internal "
624 "interrupts\n"); 623 "interrupts\n");
625 return -EINVAL; 624 return -EINVAL;
625
626 } 626 }
627 627
628 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 628 irqd_set_trigger_type(d, flow_type);
629 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
630 if (flow_type & IRQ_TYPE_LEVEL_LOW) { 629 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
631 desc->status |= IRQ_LEVEL; 630 __irq_set_handler_locked(d->irq, handle_level_irq);
632 desc->handle_irq = handle_level_irq; 631 d->chip = &ipic_level_irq_chip;
633 desc->irq_data.chip = &ipic_level_irq_chip;
634 } else { 632 } else {
635 desc->handle_irq = handle_edge_irq; 633 __irq_set_handler_locked(d->irq, handle_edge_irq);
636 desc->irq_data.chip = &ipic_edge_irq_chip; 634 d->chip = &ipic_edge_irq_chip;
637 } 635 }
638 636
639 /* only EXT IRQ senses are programmable on ipic 637 /* only EXT IRQ senses are programmable on ipic
@@ -655,7 +653,7 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
655 } 653 }
656 if (vold != vnew) 654 if (vold != vnew)
657 ipic_write(ipic->regs, IPIC_SECNR, vnew); 655 ipic_write(ipic->regs, IPIC_SECNR, vnew);
658 return 0; 656 return IRQ_SET_MASK_OK_NOCOPY;
659} 657}
660 658
661/* level interrupts and edge interrupts have different ack operations */ 659/* level interrupts and edge interrupts have different ack operations */
@@ -687,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq,
687{ 685{
688 struct ipic *ipic = h->host_data; 686 struct ipic *ipic = h->host_data;
689 687
690 set_irq_chip_data(virq, ipic); 688 irq_set_chip_data(virq, ipic);
691 set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); 689 irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
692 690
693 /* Set default irq type */ 691 /* Set default irq type */
694 set_irq_type(virq, IRQ_TYPE_NONE); 692 irq_set_irq_type(virq, IRQ_TYPE_NONE);
695 693
696 return 0; 694 return 0;
697} 695}
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 1a75a7fb4a99..a88800ff4d01 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -72,13 +72,6 @@ static void mpc8xx_end_irq(struct irq_data *d)
72 72
73static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) 73static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
74{ 74{
75 struct irq_desc *desc = irq_to_desc(d->irq);
76
77 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
78 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
79 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
80 desc->status |= IRQ_LEVEL;
81
82 if (flow_type & IRQ_TYPE_EDGE_FALLING) { 75 if (flow_type & IRQ_TYPE_EDGE_FALLING) {
83 irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; 76 irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq;
84 unsigned int siel = in_be32(&siu_reg->sc_siel); 77 unsigned int siel = in_be32(&siu_reg->sc_siel);
@@ -87,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
87 if ((hw & 1) == 0) { 80 if ((hw & 1) == 0) {
88 siel |= (0x80000000 >> hw); 81 siel |= (0x80000000 >> hw);
89 out_be32(&siu_reg->sc_siel, siel); 82 out_be32(&siu_reg->sc_siel, siel);
90 desc->handle_irq = handle_edge_irq; 83 __irq_set_handler_locked(d->irq, handle_edge_irq);
91 } 84 }
92 } 85 }
93 return 0; 86 return 0;
@@ -124,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
124 pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); 117 pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
125 118
126 /* Set default irq handle */ 119 /* Set default irq handle */
127 set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); 120 irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
128 return 0; 121 return 0;
129} 122}
130 123
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 232e701245d7..0892a2841c2b 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145 145
146static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) 146static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
147{ 147{
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); 148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
149 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 149 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
150 unsigned int mask; 150 unsigned int mask;
151 151
@@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
278 if (mpc8xxx_gc->of_dev_id_data) 278 if (mpc8xxx_gc->of_dev_id_data)
279 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; 279 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
280 280
281 set_irq_chip_data(virq, h->host_data); 281 irq_set_chip_data(virq, h->host_data);
282 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); 282 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
283 set_irq_type(virq, IRQ_TYPE_NONE); 283 irq_set_irq_type(virq, IRQ_TYPE_NONE);
284 284
285 return 0; 285 return 0;
286} 286}
@@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
369 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); 369 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
370 out_be32(mm_gc->regs + GPIO_IMR, 0); 370 out_be32(mm_gc->regs + GPIO_IMR, 0);
371 371
372 set_irq_data(hwirq, mpc8xxx_gc); 372 irq_set_handler_data(hwirq, mpc8xxx_gc);
373 set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); 373 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
374 374
375skip_irq: 375skip_irq:
376 return; 376 return;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index eb7021815e2d..f91c065bed5a 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -147,6 +147,16 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
147 147
148#endif /* CONFIG_MPIC_WEIRD */ 148#endif /* CONFIG_MPIC_WEIRD */
149 149
150static inline unsigned int mpic_processor_id(struct mpic *mpic)
151{
152 unsigned int cpu = 0;
153
154 if (mpic->flags & MPIC_PRIMARY)
155 cpu = hard_smp_processor_id();
156
157 return cpu;
158}
159
150/* 160/*
151 * Register accessor functions 161 * Register accessor functions
152 */ 162 */
@@ -210,19 +220,14 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
210 220
211static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 221static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
212{ 222{
213 unsigned int cpu = 0; 223 unsigned int cpu = mpic_processor_id(mpic);
214 224
215 if (mpic->flags & MPIC_PRIMARY)
216 cpu = hard_smp_processor_id();
217 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); 225 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
218} 226}
219 227
220static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) 228static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
221{ 229{
222 unsigned int cpu = 0; 230 unsigned int cpu = mpic_processor_id(mpic);
223
224 if (mpic->flags & MPIC_PRIMARY)
225 cpu = hard_smp_processor_id();
226 231
227 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); 232 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
228} 233}
@@ -356,7 +361,7 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
356} 361}
357 362
358static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, 363static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
359 unsigned int irqflags) 364 bool level)
360{ 365{
361 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 366 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
362 unsigned long flags; 367 unsigned long flags;
@@ -365,14 +370,14 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
365 if (fixup->base == NULL) 370 if (fixup->base == NULL)
366 return; 371 return;
367 372
368 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", 373 DBG("startup_ht_interrupt(0x%x) index: %d\n",
369 source, irqflags, fixup->index); 374 source, fixup->index);
370 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 375 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
371 /* Enable and configure */ 376 /* Enable and configure */
372 writeb(0x10 + 2 * fixup->index, fixup->base + 2); 377 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
373 tmp = readl(fixup->base + 4); 378 tmp = readl(fixup->base + 4);
374 tmp &= ~(0x23U); 379 tmp &= ~(0x23U);
375 if (irqflags & IRQ_LEVEL) 380 if (level)
376 tmp |= 0x22; 381 tmp |= 0x22;
377 writel(tmp, fixup->base + 4); 382 writel(tmp, fixup->base + 4);
378 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); 383 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
@@ -384,8 +389,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
384#endif 389#endif
385} 390}
386 391
387static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, 392static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
388 unsigned int irqflags)
389{ 393{
390 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; 394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
391 unsigned long flags; 395 unsigned long flags;
@@ -394,7 +398,7 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
394 if (fixup->base == NULL) 398 if (fixup->base == NULL)
395 return; 399 return;
396 400
397 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); 401 DBG("shutdown_ht_interrupt(0x%x)\n", source);
398 402
399 /* Disable */ 403 /* Disable */
400 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); 404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
@@ -611,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq)
611 if (irq < NUM_ISA_INTERRUPTS) 615 if (irq < NUM_ISA_INTERRUPTS)
612 return NULL; 616 return NULL;
613 617
614 return get_irq_chip_data(irq); 618 return irq_get_chip_data(irq);
615} 619}
616 620
617/* Determine if the linux irq is an IPI */ 621/* Determine if the linux irq is an IPI */
@@ -645,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d)
645/* Get the mpic structure from the irq number */ 649/* Get the mpic structure from the irq number */
646static inline struct mpic * mpic_from_irq(unsigned int irq) 650static inline struct mpic * mpic_from_irq(unsigned int irq)
647{ 651{
648 return get_irq_chip_data(irq); 652 return irq_get_chip_data(irq);
649} 653}
650 654
651/* Get the mpic structure from the irq data */ 655/* Get the mpic structure from the irq data */
@@ -733,7 +737,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d)
733 737
734 mpic_unmask_irq(d); 738 mpic_unmask_irq(d);
735 739
736 if (irq_to_desc(d->irq)->status & IRQ_LEVEL) 740 if (irqd_is_level_type(d))
737 mpic_ht_end_irq(mpic, src); 741 mpic_ht_end_irq(mpic, src);
738} 742}
739 743
@@ -743,7 +747,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d)
743 unsigned int src = mpic_irq_to_hw(d->irq); 747 unsigned int src = mpic_irq_to_hw(d->irq);
744 748
745 mpic_unmask_irq(d); 749 mpic_unmask_irq(d);
746 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); 750 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
747 751
748 return 0; 752 return 0;
749} 753}
@@ -753,7 +757,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d)
753 struct mpic *mpic = mpic_from_irq_data(d); 757 struct mpic *mpic = mpic_from_irq_data(d);
754 unsigned int src = mpic_irq_to_hw(d->irq); 758 unsigned int src = mpic_irq_to_hw(d->irq);
755 759
756 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); 760 mpic_shutdown_ht_interrupt(mpic, src);
757 mpic_mask_irq(d); 761 mpic_mask_irq(d);
758} 762}
759 763
@@ -770,7 +774,7 @@ static void mpic_end_ht_irq(struct irq_data *d)
770 * latched another edge interrupt coming in anyway 774 * latched another edge interrupt coming in anyway
771 */ 775 */
772 776
773 if (irq_to_desc(d->irq)->status & IRQ_LEVEL) 777 if (irqd_is_level_type(d))
774 mpic_ht_end_irq(mpic, src); 778 mpic_ht_end_irq(mpic, src);
775 mpic_eoi(mpic); 779 mpic_eoi(mpic);
776} 780}
@@ -859,7 +863,6 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
859{ 863{
860 struct mpic *mpic = mpic_from_irq_data(d); 864 struct mpic *mpic = mpic_from_irq_data(d);
861 unsigned int src = mpic_irq_to_hw(d->irq); 865 unsigned int src = mpic_irq_to_hw(d->irq);
862 struct irq_desc *desc = irq_to_desc(d->irq);
863 unsigned int vecpri, vold, vnew; 866 unsigned int vecpri, vold, vnew;
864 867
865 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 868 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
@@ -874,10 +877,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
874 if (flow_type == IRQ_TYPE_NONE) 877 if (flow_type == IRQ_TYPE_NONE)
875 flow_type = IRQ_TYPE_LEVEL_LOW; 878 flow_type = IRQ_TYPE_LEVEL_LOW;
876 879
877 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 880 irqd_set_trigger_type(d, flow_type);
878 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
879 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
880 desc->status |= IRQ_LEVEL;
881 881
882 if (mpic_is_ht_interrupt(mpic, src)) 882 if (mpic_is_ht_interrupt(mpic, src))
883 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 883 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
@@ -892,7 +892,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
892 if (vold != vnew) 892 if (vold != vnew)
893 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); 893 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
894 894
895 return 0; 895 return IRQ_SET_MASK_OK_NOCOPY;;
896} 896}
897 897
898void mpic_set_vector(unsigned int virq, unsigned int vector) 898void mpic_set_vector(unsigned int virq, unsigned int vector)
@@ -913,6 +913,20 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
913 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 913 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
914} 914}
915 915
916void mpic_set_destination(unsigned int virq, unsigned int cpuid)
917{
918 struct mpic *mpic = mpic_from_irq(virq);
919 unsigned int src = mpic_irq_to_hw(virq);
920
921 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
922 mpic, virq, src, cpuid);
923
924 if (src >= mpic->irq_count)
925 return;
926
927 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
928}
929
916static struct irq_chip mpic_irq_chip = { 930static struct irq_chip mpic_irq_chip = {
917 .irq_mask = mpic_mask_irq, 931 .irq_mask = mpic_mask_irq,
918 .irq_unmask = mpic_unmask_irq, 932 .irq_unmask = mpic_unmask_irq,
@@ -964,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
964 WARN_ON(!(mpic->flags & MPIC_PRIMARY)); 978 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
965 979
966 DBG("mpic: mapping as IPI\n"); 980 DBG("mpic: mapping as IPI\n");
967 set_irq_chip_data(virq, mpic); 981 irq_set_chip_data(virq, mpic);
968 set_irq_chip_and_handler(virq, &mpic->hc_ipi, 982 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
969 handle_percpu_irq); 983 handle_percpu_irq);
970 return 0; 984 return 0;
971 } 985 }
@@ -987,11 +1001,21 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
987 1001
988 DBG("mpic: mapping to irq chip @%p\n", chip); 1002 DBG("mpic: mapping to irq chip @%p\n", chip);
989 1003
990 set_irq_chip_data(virq, mpic); 1004 irq_set_chip_data(virq, mpic);
991 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); 1005 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
992 1006
993 /* Set default irq type */ 1007 /* Set default irq type */
994 set_irq_type(virq, IRQ_TYPE_NONE); 1008 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1009
1010 /* If the MPIC was reset, then all vectors have already been
1011 * initialized. Otherwise, a per source lazy initialization
1012 * is done here.
1013 */
1014 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1015 mpic_set_vector(virq, hw);
1016 mpic_set_destination(virq, mpic_processor_id(mpic));
1017 mpic_irq_set_priority(virq, 8);
1018 }
995 1019
996 return 0; 1020 return 0;
997} 1021}
@@ -1040,6 +1064,11 @@ static struct irq_host_ops mpic_host_ops = {
1040 .xlate = mpic_host_xlate, 1064 .xlate = mpic_host_xlate,
1041}; 1065};
1042 1066
1067static int mpic_reset_prohibited(struct device_node *node)
1068{
1069 return node && of_get_property(node, "pic-no-reset", NULL);
1070}
1071
1043/* 1072/*
1044 * Exported functions 1073 * Exported functions
1045 */ 1074 */
@@ -1160,7 +1189,15 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1160 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1189 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1161 1190
1162 /* Reset */ 1191 /* Reset */
1163 if (flags & MPIC_WANTS_RESET) { 1192
1193 /* When using a device-node, reset requests are only honored if the MPIC
1194 * is allowed to reset.
1195 */
1196 if (mpic_reset_prohibited(node))
1197 mpic->flags |= MPIC_NO_RESET;
1198
1199 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1200 printk(KERN_DEBUG "mpic: Resetting\n");
1164 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1201 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1165 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1202 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1166 | MPIC_GREG_GCONF_RESET); 1203 | MPIC_GREG_GCONF_RESET);
@@ -1320,22 +1357,21 @@ void __init mpic_init(struct mpic *mpic)
1320 1357
1321 mpic_pasemi_msi_init(mpic); 1358 mpic_pasemi_msi_init(mpic);
1322 1359
1323 if (mpic->flags & MPIC_PRIMARY) 1360 cpu = mpic_processor_id(mpic);
1324 cpu = hard_smp_processor_id();
1325 else
1326 cpu = 0;
1327 1361
1328 for (i = 0; i < mpic->num_sources; i++) { 1362 if (!(mpic->flags & MPIC_NO_RESET)) {
1329 /* start with vector = source number, and masked */ 1363 for (i = 0; i < mpic->num_sources; i++) {
1330 u32 vecpri = MPIC_VECPRI_MASK | i | 1364 /* start with vector = source number, and masked */
1331 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1365 u32 vecpri = MPIC_VECPRI_MASK | i |
1366 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1332 1367
1333 /* check if protected */ 1368 /* check if protected */
1334 if (mpic->protected && test_bit(i, mpic->protected)) 1369 if (mpic->protected && test_bit(i, mpic->protected))
1335 continue; 1370 continue;
1336 /* init hw */ 1371 /* init hw */
1337 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); 1372 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1338 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); 1373 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1374 }
1339 } 1375 }
1340 1376
1341 /* Init spurious vector */ 1377 /* Init spurious vector */
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 0b7794acfce1..38e62382070c 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
81 if (entry->irq == NO_IRQ) 81 if (entry->irq == NO_IRQ)
82 continue; 82 continue;
83 83
84 set_irq_msi(entry->irq, NULL); 84 irq_set_msi_desc(entry->irq, NULL);
85 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, 85 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
86 virq_to_hw(entry->irq), ALLOC_CHUNK); 86 virq_to_hw(entry->irq), ALLOC_CHUNK);
87 irq_dispose_mapping(entry->irq); 87 irq_dispose_mapping(entry->irq);
@@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
131 */ 131 */
132 mpic_set_vector(virq, 0); 132 mpic_set_vector(virq, 0);
133 133
134 set_irq_msi(virq, entry); 134 irq_set_msi_desc(virq, entry);
135 set_irq_chip(virq, &mpic_pasemi_msi_chip); 135 irq_set_chip(virq, &mpic_pasemi_msi_chip);
136 set_irq_type(virq, IRQ_TYPE_EDGE_RISING); 136 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
137 137
138 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ 138 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
139 "addr 0x%x\n", virq, hwirq, msg.address_lo); 139 "addr 0x%x\n", virq, hwirq, msg.address_lo);
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 71900ac78270..9a7aa0ed9c1c 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
129 if (entry->irq == NO_IRQ) 129 if (entry->irq == NO_IRQ)
130 continue; 130 continue;
131 131
132 set_irq_msi(entry->irq, NULL); 132 irq_set_msi_desc(entry->irq, NULL);
133 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, 133 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
134 virq_to_hw(entry->irq), 1); 134 virq_to_hw(entry->irq), 1);
135 irq_dispose_mapping(entry->irq); 135 irq_dispose_mapping(entry->irq);
@@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
166 return -ENOSPC; 166 return -ENOSPC;
167 } 167 }
168 168
169 set_irq_msi(virq, entry); 169 irq_set_msi_desc(virq, entry);
170 set_irq_chip(virq, &mpic_u3msi_chip); 170 irq_set_chip(virq, &mpic_u3msi_chip);
171 set_irq_type(virq, IRQ_TYPE_EDGE_RISING); 171 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
172 172
173 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", 173 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
174 virq, hwirq, (unsigned long)addr); 174 virq, hwirq, (unsigned long)addr);
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index bc61ebb8987c..e9c633c7c083 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -213,11 +213,12 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
213{ 213{
214 int level1; 214 int level1;
215 215
216 irq_to_desc(virq)->status |= IRQ_LEVEL; 216 irq_set_status_flags(virq, IRQ_LEVEL);
217 217
218 level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; 218 level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
219 BUG_ON(level1 > MV64x60_LEVEL1_GPP); 219 BUG_ON(level1 > MV64x60_LEVEL1_GPP);
220 set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq); 220 irq_set_chip_and_handler(virq, mv64x60_chips[level1],
221 handle_level_irq);
221 222
222 return 0; 223 return 0;
223} 224}
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 56d9e5deccbf..c39a134e8684 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -324,7 +324,7 @@
324#define PESDR0_460EX_IHS2 0x036D 324#define PESDR0_460EX_IHS2 0x036D
325 325
326/* 326/*
327 * 460SX addtional DCRs 327 * 460SX additional DCRs
328 */ 328 */
329#define PESDRn_460SX_RCEI 0x02 329#define PESDRn_460SX_RCEI 0x02
330 330
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 8c9ded8ea07c..832d6924ad1c 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg
189 189
190static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) 190static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191{ 191{
192 return get_irq_chip_data(virq); 192 return irq_get_chip_data(virq);
193} 193}
194 194
195static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) 195static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
@@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
267 /* Default chip */ 267 /* Default chip */
268 chip = &qe_ic->hc_irq; 268 chip = &qe_ic->hc_irq;
269 269
270 set_irq_chip_data(virq, qe_ic); 270 irq_set_chip_data(virq, qe_ic);
271 irq_to_desc(virq)->status |= IRQ_LEVEL; 271 irq_set_status_flags(virq, IRQ_LEVEL);
272 272
273 set_irq_chip_and_handler(virq, chip, handle_level_irq); 273 irq_set_chip_and_handler(virq, chip, handle_level_irq);
274 274
275 return 0; 275 return 0;
276} 276}
@@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
386 386
387 qe_ic_write(qe_ic->regs, QEIC_CICR, temp); 387 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
388 388
389 set_irq_data(qe_ic->virq_low, qe_ic); 389 irq_set_handler_data(qe_ic->virq_low, qe_ic);
390 set_irq_chained_handler(qe_ic->virq_low, low_handler); 390 irq_set_chained_handler(qe_ic->virq_low, low_handler);
391 391
392 if (qe_ic->virq_high != NO_IRQ && 392 if (qe_ic->virq_high != NO_IRQ &&
393 qe_ic->virq_high != qe_ic->virq_low) { 393 qe_ic->virq_high != qe_ic->virq_low) {
394 set_irq_data(qe_ic->virq_high, qe_ic); 394 irq_set_handler_data(qe_ic->virq_high, qe_ic);
395 set_irq_chained_handler(qe_ic->virq_high, high_handler); 395 irq_set_chained_handler(qe_ic->virq_high, high_handler);
396 } 396 }
397} 397}
398 398
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 02c91db90037..4d18658116e5 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -391,8 +391,8 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
391 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); 391 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
392 if ((virq >= 1) && (virq <= 4)){ 392 if ((virq >= 1) && (virq <= 4)){
393 irq = virq + IRQ_PCI_INTAD_BASE - 1; 393 irq = virq + IRQ_PCI_INTAD_BASE - 1;
394 irq_to_desc(irq)->status |= IRQ_LEVEL; 394 irq_set_status_flags(irq, IRQ_LEVEL);
395 set_irq_chip(irq, &tsi108_pci_irq); 395 irq_set_chip(irq, &tsi108_pci_irq);
396 } 396 }
397 return 0; 397 return 0;
398} 398}
@@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node)
431 431
432void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) 432void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
433{ 433{
434 struct irq_chip *chip = get_irq_desc_chip(desc); 434 struct irq_chip *chip = irq_desc_get_chip(desc);
435 unsigned int cascade_irq = get_pci_source(); 435 unsigned int cascade_irq = get_pci_source();
436 436
437 if (cascade_irq != NO_IRQ) 437 if (cascade_irq != NO_IRQ)
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 835f7958b237..5d9138516628 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -57,7 +57,6 @@ struct uic {
57 57
58static void uic_unmask_irq(struct irq_data *d) 58static void uic_unmask_irq(struct irq_data *d)
59{ 59{
60 struct irq_desc *desc = irq_to_desc(d->irq);
61 struct uic *uic = irq_data_get_irq_chip_data(d); 60 struct uic *uic = irq_data_get_irq_chip_data(d);
62 unsigned int src = uic_irq_to_hw(d->irq); 61 unsigned int src = uic_irq_to_hw(d->irq);
63 unsigned long flags; 62 unsigned long flags;
@@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d)
66 sr = 1 << (31-src); 65 sr = 1 << (31-src);
67 spin_lock_irqsave(&uic->lock, flags); 66 spin_lock_irqsave(&uic->lock, flags);
68 /* ack level-triggered interrupts here */ 67 /* ack level-triggered interrupts here */
69 if (desc->status & IRQ_LEVEL) 68 if (irqd_is_level_type(d))
70 mtdcr(uic->dcrbase + UIC_SR, sr); 69 mtdcr(uic->dcrbase + UIC_SR, sr);
71 er = mfdcr(uic->dcrbase + UIC_ER); 70 er = mfdcr(uic->dcrbase + UIC_ER);
72 er |= sr; 71 er |= sr;
@@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d)
101 100
102static void uic_mask_ack_irq(struct irq_data *d) 101static void uic_mask_ack_irq(struct irq_data *d)
103{ 102{
104 struct irq_desc *desc = irq_to_desc(d->irq);
105 struct uic *uic = irq_data_get_irq_chip_data(d); 103 struct uic *uic = irq_data_get_irq_chip_data(d);
106 unsigned int src = uic_irq_to_hw(d->irq); 104 unsigned int src = uic_irq_to_hw(d->irq);
107 unsigned long flags; 105 unsigned long flags;
@@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d)
120 * level interrupts are ack'ed after the actual 118 * level interrupts are ack'ed after the actual
121 * isr call in the uic_unmask_irq() 119 * isr call in the uic_unmask_irq()
122 */ 120 */
123 if (!(desc->status & IRQ_LEVEL)) 121 if (!irqd_is_level_type(d))
124 mtdcr(uic->dcrbase + UIC_SR, sr); 122 mtdcr(uic->dcrbase + UIC_SR, sr);
125 spin_unlock_irqrestore(&uic->lock, flags); 123 spin_unlock_irqrestore(&uic->lock, flags);
126} 124}
@@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
129{ 127{
130 struct uic *uic = irq_data_get_irq_chip_data(d); 128 struct uic *uic = irq_data_get_irq_chip_data(d);
131 unsigned int src = uic_irq_to_hw(d->irq); 129 unsigned int src = uic_irq_to_hw(d->irq);
132 struct irq_desc *desc = irq_to_desc(d->irq);
133 unsigned long flags; 130 unsigned long flags;
134 int trigger, polarity; 131 int trigger, polarity;
135 u32 tr, pr, mask; 132 u32 tr, pr, mask;
@@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
166 mtdcr(uic->dcrbase + UIC_PR, pr); 163 mtdcr(uic->dcrbase + UIC_PR, pr);
167 mtdcr(uic->dcrbase + UIC_TR, tr); 164 mtdcr(uic->dcrbase + UIC_TR, tr);
168 165
169 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
170 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
171 if (!trigger)
172 desc->status |= IRQ_LEVEL;
173
174 spin_unlock_irqrestore(&uic->lock, flags); 166 spin_unlock_irqrestore(&uic->lock, flags);
175 167
176 return 0; 168 return 0;
@@ -190,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq,
190{ 182{
191 struct uic *uic = h->host_data; 183 struct uic *uic = h->host_data;
192 184
193 set_irq_chip_data(virq, uic); 185 irq_set_chip_data(virq, uic);
194 /* Despite the name, handle_level_irq() works for both level 186 /* Despite the name, handle_level_irq() works for both level
195 * and edge irqs on UIC. FIXME: check this is correct */ 187 * and edge irqs on UIC. FIXME: check this is correct */
196 set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); 188 irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
197 189
198 /* Set default irq type */ 190 /* Set default irq type */
199 set_irq_type(virq, IRQ_TYPE_NONE); 191 irq_set_irq_type(virq, IRQ_TYPE_NONE);
200 192
201 return 0; 193 return 0;
202} 194}
@@ -220,17 +212,18 @@ static struct irq_host_ops uic_host_ops = {
220 212
221void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) 213void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
222{ 214{
223 struct irq_chip *chip = get_irq_desc_chip(desc); 215 struct irq_chip *chip = irq_desc_get_chip(desc);
224 struct uic *uic = get_irq_data(virq); 216 struct irq_data *idata = irq_desc_get_irq_data(desc);
217 struct uic *uic = irq_get_handler_data(virq);
225 u32 msr; 218 u32 msr;
226 int src; 219 int src;
227 int subvirq; 220 int subvirq;
228 221
229 raw_spin_lock(&desc->lock); 222 raw_spin_lock(&desc->lock);
230 if (desc->status & IRQ_LEVEL) 223 if (irqd_is_level_type(idata))
231 chip->irq_mask(&desc->irq_data); 224 chip->irq_mask(idata);
232 else 225 else
233 chip->irq_mask_ack(&desc->irq_data); 226 chip->irq_mask_ack(idata);
234 raw_spin_unlock(&desc->lock); 227 raw_spin_unlock(&desc->lock);
235 228
236 msr = mfdcr(uic->dcrbase + UIC_MSR); 229 msr = mfdcr(uic->dcrbase + UIC_MSR);
@@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
244 237
245uic_irq_ret: 238uic_irq_ret:
246 raw_spin_lock(&desc->lock); 239 raw_spin_lock(&desc->lock);
247 if (desc->status & IRQ_LEVEL) 240 if (irqd_is_level_type(idata))
248 chip->irq_ack(&desc->irq_data); 241 chip->irq_ack(idata);
249 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) 242 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
250 chip->irq_unmask(&desc->irq_data); 243 chip->irq_unmask(idata);
251 raw_spin_unlock(&desc->lock); 244 raw_spin_unlock(&desc->lock);
252} 245}
253 246
@@ -336,8 +329,8 @@ void __init uic_init_tree(void)
336 329
337 cascade_virq = irq_of_parse_and_map(np, 0); 330 cascade_virq = irq_of_parse_and_map(np, 0);
338 331
339 set_irq_data(cascade_virq, uic); 332 irq_set_handler_data(cascade_virq, uic);
340 set_irq_chained_handler(cascade_virq, uic_irq_cascade); 333 irq_set_chained_handler(cascade_virq, uic_irq_cascade);
341 334
342 /* FIXME: setup critical cascade?? */ 335 /* FIXME: setup critical cascade?? */
343 } 336 }
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 7436f3ed4df6..0a13fc19e287 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -79,12 +79,6 @@ static void xilinx_intc_mask(struct irq_data *d)
79 79
80static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) 80static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
81{ 81{
82 struct irq_desc *desc = irq_to_desc(d->irq);
83
84 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
85 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
86 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
87 desc->status |= IRQ_LEVEL;
88 return 0; 82 return 0;
89} 83}
90 84
@@ -170,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
170static int xilinx_intc_map(struct irq_host *h, unsigned int virq, 164static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
171 irq_hw_number_t irq) 165 irq_hw_number_t irq)
172{ 166{
173 set_irq_chip_data(virq, h->host_data); 167 irq_set_chip_data(virq, h->host_data);
174 168
175 if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || 169 if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
176 xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { 170 xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
177 set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip, 171 irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
178 handle_level_irq); 172 handle_level_irq);
179 } else { 173 } else {
180 set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip, 174 irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
181 handle_edge_irq); 175 handle_edge_irq);
182 } 176 }
183 return 0; 177 return 0;
184} 178}
@@ -229,7 +223,7 @@ int xilinx_intc_get_irq(void)
229 */ 223 */
230static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) 224static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
231{ 225{
232 struct irq_chip *chip = get_irq_desc_chip(desc); 226 struct irq_chip *chip = irq_desc_get_chip(desc);
233 unsigned int cascade_irq = i8259_irq(); 227 unsigned int cascade_irq = i8259_irq();
234 228
235 if (cascade_irq) 229 if (cascade_irq)
@@ -256,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void)
256 } 250 }
257 251
258 i8259_init(cascade_node, 0); 252 i8259_init(cascade_node, 0);
259 set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); 253 irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
260 254
261 /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ 255 /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
262 /* This looks like a dirty hack to me --gcl */ 256 /* This looks like a dirty hack to me --gcl */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-28 11:39:15 -0400