Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc update from Benjamin Herrenschmidt:
 "The main highlights this time around are:

   - A pile of addition POWER8 bits and nits, such as updated
     performance counter support (Michael Ellerman), new branch history
     buffer support (Anshuman Khandual), base support for the new PCI
     host bridge when not using the hypervisor (Gavin Shan) and other
     random related bits and fixes from various contributors.

   - Some rework of our page table format by Aneesh Kumar which fixes a
     thing or two and paves the way for THP support.  THP itself will
     not make it this time around however.

   - More Freescale updates, including Altivec support on the new e6500
     cores, new PCI controller support, and a pile of new boards support
     and updates.

   - The usual batch of trivial cleanups & fixes"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (156 commits)
  powerpc: Fix build error for book3e
  powerpc: Context switch the new EBB SPRs
  powerpc: Turn on the EBB H/FSCR bits
  powerpc: Replace CPU_FTR_BCTAR with CPU_FTR_ARCH_207S
  powerpc: Setup BHRB instructions facility in HFSCR for POWER8
  powerpc: Fix interrupt range check on debug exception
  powerpc: Update tlbie/tlbiel as per ISA doc
  powerpc: Print page size info during boot
  powerpc: print both base and actual page size on hash failure
  powerpc: Fix hpte_decode to use the correct decoding for page sizes
  powerpc: Decode the pte-lp-encoding bits correctly.
  powerpc: Use encode avpn where we need only avpn values
  powerpc: Reduce PTE table memory wastage
  powerpc: Move the pte free routines from common header
  powerpc: Reduce the PTE_INDEX_SIZE
  powerpc: Switch 16GB and 16MB explicit hugepages to a different page table format
  powerpc: New hugepage directory format
  powerpc: Don't truncate pgd_index wrongly
  powerpc: Don't hard code the size of pte page
  powerpc: Save DAR and DSISR in pt_regs on MCE
  ...

8 files changed, 105 insertions, 46 deletions

diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index a84fecf63c4d..ab4cb5476472 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -19,6 +19,7 @@ config PPC_MSI_BITMAP
         default y if MPIC
         default y if FSL_PCI
         default y if PPC4xx_MSI
+        default y if POWERNV_MSI
 
 source "arch/powerpc/sysdev/xics/Kconfig"
 
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 178c99427b1c..ab02db3d02d8 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -333,6 +333,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
         return 0;
 }
 
+static struct lock_class_key fsl_msi_irq_class;
+
 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
                                int offset, int irq_index)
 {
@@ -351,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
                 dev_err(&dev->dev, "No memory for MSI cascade data\n");
                 return -ENOMEM;
         }
-
+        irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
         msi->msi_virqs[irq_index] = virt_msir;
         cascade_data->index = offset;
         cascade_data->msi_data = msi;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084dba19b..cffe7edac858 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,16 +54,63 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
         return;
 }
 
-static int __init fsl_pcie_check_link(struct pci_controller *hose)
+static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
+                                    int, int, u32 *);
+
+static int fsl_pcie_check_link(struct pci_controller *hose)
 {
-        u32 val;
+        u32 val = 0;
+
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+                if (hose->ops->read == fsl_indirect_read_config) {
+                        struct pci_bus bus;
+                        bus.number = 0;
+                        bus.sysdata = hose;
+                        bus.ops = hose->ops;
+                        indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
+                } else
+                        early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+                if (val < PCIE_LTSSM_L0)
+                        return 1;
+        } else {
+                struct ccsr_pci __iomem *pci = hose->private_data;
+                /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
+                val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
+                                >> PEX_CSR0_LTSSM_SHIFT;
+                if (val != PEX_CSR0_LTSSM_L0)
+                        return 1;
+        }
 
-        early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
-        if (val < PCIE_LTSSM_L0)
-                return 1;
         return 0;
 }
 
+static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int offset, int len, u32 *val)
+{
+        struct pci_controller *hose = pci_bus_to_host(bus);
+
+        if (fsl_pcie_check_link(hose))
+                hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+        else
+                hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+
+        return indirect_read_config(bus, devfn, offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops =
+{
+        .read = fsl_indirect_read_config,
+        .write = indirect_write_config,
+};
+
+static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
+                                          resource_size_t cfg_addr,
+                                          resource_size_t cfg_data, u32 flags)
+{
+        setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
+        hose->ops = &fsl_indirect_pci_ops;
+}
+
 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 
 #define MAX_PHYS_ADDR_BITS      40
@@ -106,7 +153,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
                 flags |= 0x10000000; /* enable relaxed ordering */
 
         for (i = 0; size > 0; i++) {
-                unsigned int bits = min(__ilog2(size),
+                unsigned int bits = min(ilog2(size),
                                         __ffs(pci_addr | phys_addr));
 
                 if (index + i >= 5)
@@ -126,10 +173,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
 }
 
 /* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose,
-                                  struct resource *rsrc)
+static void setup_pci_atmu(struct pci_controller *hose)
 {
-        struct ccsr_pci __iomem *pci;
+        struct ccsr_pci __iomem *pci = hose->private_data;
         int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
         u64 mem, sz, paddr_hi = 0;
         u64 paddr_lo = ULLONG_MAX;
@@ -140,15 +186,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
         const u64 *reg;
         int len;
 
-        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
-                 (u64)rsrc->start, (u64)resource_size(rsrc));
-
-        pci = ioremap(rsrc->start, resource_size(rsrc));
-        if (!pci) {
-            dev_err(hose->parent, "Unable to map ATMU registers\n");
-            return;
-        }
-
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
                 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
                         win_idx = 2;
@@ -196,7 +233,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
                         out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
                         /* Enable, IO R/W */
                         out_be32(&pci->pow[j].powar, 0x80088000
-                                | (__ilog2(hose->io_resource.end
+                                | (ilog2(hose->io_resource.end
                                 - hose->io_resource.start + 1) - 1));
                 }
         }
@@ -207,12 +244,12 @@ static void setup_pci_atmu(struct pci_controller *hose,
 
         if (paddr_hi == paddr_lo) {
                 pr_err("%s: No outbound window space\n", name);
-                goto out;
+                return;
         }
 
         if (paddr_lo == 0) {
                 pr_err("%s: No space for inbound window\n", name);
-                goto out;
+                return;
         }
 
         /* setup PCSRBAR/PEXCSRBAR */
@@ -261,7 +298,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
         }
 
         sz = min(mem, paddr_lo);
-        mem_log = __ilog2_u64(sz);
+        mem_log = ilog2(sz);
 
         /* PCIe can overmap inbound & outbound since RX & TX are separated */
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
@@ -290,7 +327,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
                  * SWIOTLB and access the full range of memory
                  */
                 if (sz != mem) {
-                        mem_log = __ilog2_u64(mem);
+                        mem_log = ilog2(mem);
 
                         /* Size window up if we dont fit in exact power-of-2 */
                         if ((1ull << mem_log) != mem)
@@ -327,7 +364,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
                 sz -= 1ull << mem_log;
 
                 if (sz) {
-                        mem_log = __ilog2_u64(sz);
+                        mem_log = ilog2(sz);
                         piwar |= (mem_log - 1);
 
                         out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
@@ -358,9 +395,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
                 pr_info("%s: DMA window size is 0x%llx\n", name,
                         (u64)hose->dma_window_size);
         }
-
-out:
-        iounmap(pci);
 }
 
 static void __init setup_pci_cmd(struct pci_controller *hose)
@@ -429,6 +463,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         const int *bus_range;
         u8 hdr_type, progif;
         struct device_node *dev;
+        struct ccsr_pci __iomem *pci;
 
         dev = pdev->dev.of_node;
 
@@ -461,8 +496,18 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         hose->first_busno = bus_range ? bus_range[0] : 0x0;
         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 
-        setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
-                PPC_INDIRECT_TYPE_BIG_ENDIAN);
+        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
+                 (u64)rsrc.start, (u64)resource_size(&rsrc));
+
+        pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
+        if (!hose->private_data)
+                goto no_bridge;
+
+        fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+                               PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+        if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
+                hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
                 /* For PCIE read HEADER_TYPE to identify controler mode */
@@ -500,11 +545,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 
         /* Setup PEX window registers */
-        setup_pci_atmu(hose, &rsrc);
+        setup_pci_atmu(hose);
 
         return 0;
 
 no_bridge:
+        iounmap(hose->private_data);
         /* unmap cfg_data & cfg_addr separately if not on same page */
         if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
             ((unsigned long)hose->cfg_addr & PAGE_MASK))
@@ -681,6 +727,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
         WARN_ON(hose->dn->data);
         hose->dn->data = pcie;
         hose->ops = &mpc83xx_pcie_ops;
+        hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 
         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
@@ -766,8 +813,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
                 if (ret)
                         goto err0;
         } else {
-                setup_indirect_pci(hose, rsrc_cfg.start,
-                                   rsrc_cfg.start + 4, 0);
+                fsl_setup_indirect_pci(hose, rsrc_cfg.start,
+                                       rsrc_cfg.start + 4, 0);
         }
 
         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
@@ -836,6 +883,7 @@ static const struct of_device_id pci_ids[] = {
         { .compatible = "fsl,qoriq-pcie-v2.2", },
         { .compatible = "fsl,qoriq-pcie-v2.3", },
         { .compatible = "fsl,qoriq-pcie-v2.4", },
+        { .compatible = "fsl,qoriq-pcie-v3.0", },
 
         /*
          * The following entries are for compatibility with older device
@@ -927,7 +975,7 @@ static int fsl_pci_resume(struct device *dev)
                 return -ENODEV;
         }
 
-        setup_pci_atmu(hose, &pci_rsrc);
+        setup_pci_atmu(hose);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c495c00c8740..72b5625330e2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -14,9 +14,12 @@
 #ifndef __POWERPC_FSL_PCI_H
 #define __POWERPC_FSL_PCI_H
 
+struct platform_device;
+
 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
 #define PCIE_LTSSM_L0   0x16            /* L0 state */
 #define PCIE_IP_REV_2_2         0x02080202 /* PCIE IP block version Rev2.2 */
+#define PCIE_IP_REV_3_0         0x02080300 /* PCIE IP block version Rev3.0 */
 #define PIWAR_EN                0x80000000      /* Enable */
 #define PIWAR_PF                0x20000000      /* prefetch */
 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
@@ -89,6 +92,16 @@ struct ccsr_pci {
         __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
         __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
         __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
+        u8      res_e38[200];
+        __be32  pdb_stat;               /* 0x.f00 - PCIE Debug Status */
+        u8      res_f04[16];
+        __be32  pex_csr0;               /* 0x.f14 - PEX Control/Status register 0*/
+#define PEX_CSR0_LTSSM_MASK     0xFC
+#define PEX_CSR0_LTSSM_SHIFT    2
+#define PEX_CSR0_LTSSM_L0       0x11
+        __be32  pex_csr1;               /* 0x.f18 - PEX Control/Status register 1*/
+        u8      res_f1c[228];
+
 };
 
 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 82fdad885d20..c6c8b526a4f6 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,9 +20,8 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 
-static int
-indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                     int len, u32 *val)
+int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+                         int offset, int len, u32 *val)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
         volatile void __iomem *cfg_data;
@@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
         return PCIBIOS_SUCCESSFUL;
 }
 
-static int
-indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                      int len, u32 val)
+int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+                          int offset, int len, u32 val)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
         volatile void __iomem *cfg_data;
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 41ac3dfac98e..3c251993bacd 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,6 +22,6 @@ config UCC
 
 config QE_USB
         bool
-        default y if USB_GADGET_FSL_QE
+        default y if USB_FSL_QE
         help
           QE USB Controller support
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index 9afba924e94f..af79e1ea74b6 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -62,10 +62,7 @@ static int  __init add_rtc(void)
         pd = platform_device_register_simple("rtc_cmos", -1,
                                              &res[0], num_res);
 
-        if (IS_ERR(pd))
-                return PTR_ERR(pd);
-
-        return 0;
+        return PTR_RET(pd);
 }
 fs_initcall(add_rtc);
 
diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
index 48861d3fcd07..89db29d17c25 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -81,7 +81,7 @@ static void icp_native_set_cpu_priority(unsigned char cppr)
         iosync();
 }
 
-static void icp_native_eoi(struct irq_data *d)
+void icp_native_eoi(struct irq_data *d)
 {
         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);