POWERPC: overhaul with cpm2_map mechanism

Incorporating the new way of cpm2 immr access, introduced in the previous
patch, into CPM2 peripheral devices (fs_enet and cpm_uart). Both ppc and
powerpc approved working( real actions taken in powerpc only, ppc just
has a wrapper to keep init stuff consistent).

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>

2 files changed, 97 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c
index 73376f9c1560..ec265995d5d8 100644
--- a/arch/powerpc/sysdev/cpm2_common.c
+++ b/arch/powerpc/sysdev/cpm2_common.c
@@ -130,6 +130,96 @@ cpm2_fastbrg(uint brg, uint rate, int div16)
         cpm2_unmap(bp);
 }
 
+int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
+{
+        int ret = 0;
+        int shift;
+        int i, bits = 0;
+        cpmux_t *im_cpmux;
+        u32 *reg;
+        u32 mask = 7;
+        u8 clk_map [24][3] = {
+                {CPM_CLK_FCC1, CPM_BRG5, 0},
+                {CPM_CLK_FCC1, CPM_BRG6, 1},
+                {CPM_CLK_FCC1, CPM_BRG7, 2},
+                {CPM_CLK_FCC1, CPM_BRG8, 3},
+                {CPM_CLK_FCC1, CPM_CLK9, 4},
+                {CPM_CLK_FCC1, CPM_CLK10, 5},
+                {CPM_CLK_FCC1, CPM_CLK11, 6},
+                {CPM_CLK_FCC1, CPM_CLK12, 7},
+                {CPM_CLK_FCC2, CPM_BRG5, 0},
+                {CPM_CLK_FCC2, CPM_BRG6, 1},
+                {CPM_CLK_FCC2, CPM_BRG7, 2},
+                {CPM_CLK_FCC2, CPM_BRG8, 3},
+                {CPM_CLK_FCC2, CPM_CLK13, 4},
+                {CPM_CLK_FCC2, CPM_CLK14, 5},
+                {CPM_CLK_FCC2, CPM_CLK15, 6},
+                {CPM_CLK_FCC2, CPM_CLK16, 7},
+                {CPM_CLK_FCC3, CPM_BRG5, 0},
+                {CPM_CLK_FCC3, CPM_BRG6, 1},
+                {CPM_CLK_FCC3, CPM_BRG7, 2},
+                {CPM_CLK_FCC3, CPM_BRG8, 3},
+                {CPM_CLK_FCC3, CPM_CLK13, 4},
+                {CPM_CLK_FCC3, CPM_CLK14, 5},
+                {CPM_CLK_FCC3, CPM_CLK15, 6},
+                {CPM_CLK_FCC3, CPM_CLK16, 7}
+                };
+
+        im_cpmux = cpm2_map(im_cpmux);
+
+        switch (target) {
+        case CPM_CLK_SCC1:
+                reg = &im_cpmux->cmx_scr;
+                shift = 24;
+        case CPM_CLK_SCC2:
+                reg = &im_cpmux->cmx_scr;
+                shift = 16;
+                break;
+        case CPM_CLK_SCC3:
+                reg = &im_cpmux->cmx_scr;
+                shift = 8;
+                break;
+        case CPM_CLK_SCC4:
+                reg = &im_cpmux->cmx_scr;
+                shift = 0;
+                break;
+        case CPM_CLK_FCC1:
+                reg = &im_cpmux->cmx_fcr;
+                shift = 24;
+                break;
+        case CPM_CLK_FCC2:
+                reg = &im_cpmux->cmx_fcr;
+                shift = 16;
+                break;
+        case CPM_CLK_FCC3:
+                reg = &im_cpmux->cmx_fcr;
+                shift = 8;
+                break;
+        default:
+                printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
+                return -EINVAL;
+        }
+
+        if (mode == CPM_CLK_RX)
+                shift +=3;
+
+        for (i=0; i<24; i++) {
+                if (clk_map[i][0] == target && clk_map[i][1] == clock) {
+                        bits = clk_map[i][2];
+                        break;
+                }
+        }
+        if (i == sizeof(clk_map)/3)
+            ret = -EINVAL;
+
+        bits <<= shift;
+        mask <<= shift;
+        out_be32(reg, (in_be32(reg) & ~mask) | bits);
+
+        cpm2_unmap(im_cpmux);
+        return ret;
+}
+
 /*
  * dpalloc / dpfree bits.
  */
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 0b8a03cc3042..4e72bb983636 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -36,6 +36,7 @@
 #include <mm/mmu_decl.h>
 #include <asm/cpm2.h>
 
+extern void init_fcc_ioports(struct fs_platform_info*);
 static phys_addr_t immrbase = -1;
 
 phys_addr_t get_immrbase(void)
@@ -630,6 +631,9 @@ static int __init fs_enet_of_init(void)
                         goto unreg;
                 }
 
+                fs_enet_data.clk_rx = *((u32 *) get_property(np, "rx-clock", NULL));
+                fs_enet_data.clk_tx = *((u32 *) get_property(np, "tx-clock", NULL));
+
                 if (strstr(model, "FCC")) {
                         int fcc_index = fs_get_fcc_index(*id);
 
@@ -646,6 +650,7 @@ static int __init fs_enet_of_init(void)
                         snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
                                                         (u32)res.start, fs_enet_data.phy_addr);
                         fs_enet_data.bus_id = (char*)&bus_id[(*id)];
+                        fs_enet_data.init_ioports = init_fcc_ioports;
                 }
 
                 of_node_put(phy);
@@ -717,6 +722,8 @@ static int __init cpm_uart_of_init(void)
                 cpm_uart_data.tx_buf_size = 32;
                 cpm_uart_data.rx_num_fifo = 4;
                 cpm_uart_data.rx_buf_size = 32;
+                cpm_uart_data.clk_rx = *((u32 *) get_property(np, "rx-clock", NULL));
+                cpm_uart_data.clk_tx = *((u32 *) get_property(np, "tx-clock", NULL));
 
                 ret =
                     platform_device_add_data(cpm_uart_dev, &cpm_uart_data,