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authorKumar Gala <galak@kernel.crashing.org>2008-01-14 18:02:19 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-23 20:31:16 -0500
commit72b122cc301858dcf283fe6731e61322c9772cf4 (patch)
treea2feead9fd094a3e77d3be7e25d9a38cd49f4c84 /arch/powerpc/sysdev
parentb188b2aefe2b0e7d34c98106e20214f806f812a3 (diff)
[POWERPC] FSL: Rework PCI/PCIe support for 85xx/86xx
The current PCI code for Freescale 85xx/86xx was treating the virtual P2P PCIe bridge as a transparent bridge. Rather than doing that fixup the virtual P2P bridge by copying the resources from the PHB. Also, fixup a bit of the code for dealing with resource_size_t being 64-bits and how we set ATMU registers for >4G. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c150
1 files changed, 62 insertions, 88 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4b1d5120c122..bf13c2174a4e 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -33,8 +33,8 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
33 struct ccsr_pci __iomem *pci; 33 struct ccsr_pci __iomem *pci;
34 int i; 34 int i;
35 35
36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, 36 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
37 rsrc->end - rsrc->start + 1); 37 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
39 39
40 /* Disable all windows (except powar0 since its ignored) */ 40 /* Disable all windows (except powar0 since its ignored) */
@@ -46,17 +46,17 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
46 /* Setup outbound MEM window */ 46 /* Setup outbound MEM window */
47 for(i = 0; i < 3; i++) 47 for(i = 0; i < 3; i++)
48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", 49 resource_size_t pci_addr_start =
50 hose->mem_resources[i].start, 50 hose->mem_resources[i].start -
51 hose->mem_resources[i].end 51 hose->pci_mem_offset;
52 - hose->mem_resources[i].start + 1); 52 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
53 out_be32(&pci->pow[i+1].potar, 53 (u64)hose->mem_resources[i].start,
54 (hose->mem_resources[i].start >> 12) 54 (u64)hose->mem_resources[i].end
55 & 0x000fffff); 55 - (u64)hose->mem_resources[i].start + 1);
56 out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
56 out_be32(&pci->pow[i+1].potear, 0); 57 out_be32(&pci->pow[i+1].potear, 0);
57 out_be32(&pci->pow[i+1].powbar, 58 out_be32(&pci->pow[i+1].powbar,
58 (hose->mem_resources[i].start >> 12) 59 (hose->mem_resources[i].start >> 12));
59 & 0x000fffff);
60 /* Enable, Mem R/W */ 60 /* Enable, Mem R/W */
61 out_be32(&pci->pow[i+1].powar, 0x80044000 61 out_be32(&pci->pow[i+1].powar, 0x80044000
62 | (__ilog2(hose->mem_resources[i].end 62 | (__ilog2(hose->mem_resources[i].end
@@ -65,15 +65,14 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
65 65
66 /* Setup outbound IO window */ 66 /* Setup outbound IO window */
67 if (hose->io_resource.flags & IORESOURCE_IO){ 67 if (hose->io_resource.flags & IORESOURCE_IO){
68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", 68 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
69 hose->io_resource.start, 69 "phy base 0x%016llx.\n",
70 hose->io_resource.end - hose->io_resource.start + 1, 70 (u64)hose->io_resource.start,
71 hose->io_base_phys); 71 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) 72 (u64)hose->io_base_phys);
73 & 0x000fffff); 73 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
74 out_be32(&pci->pow[i+1].potear, 0); 74 out_be32(&pci->pow[i+1].potear, 0);
75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
76 & 0x000fffff);
77 /* Enable, IO R/W */ 76 /* Enable, IO R/W */
78 out_be32(&pci->pow[i+1].powar, 0x80088000 77 out_be32(&pci->pow[i+1].powar, 0x80088000
79 | (__ilog2(hose->io_resource.end 78 | (__ilog2(hose->io_resource.end
@@ -107,55 +106,17 @@ void __init setup_pci_cmd(struct pci_controller *hose)
107 } 106 }
108} 107}
109 108
110static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) 109static int fsl_pcie_bus_fixup;
111{
112 struct resource *res;
113 int i, res_idx = PCI_BRIDGE_RESOURCES;
114 struct pci_controller *hose;
115 110
111static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
112{
116 /* if we aren't a PCIe don't bother */ 113 /* if we aren't a PCIe don't bother */
117 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 114 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
118 return ; 115 return ;
119 116
120 /* 117 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
121 * Make the bridge be transparent. 118 fsl_pcie_bus_fixup = 1;
122 */ 119 return ;
123 dev->transparent = 1;
124
125 hose = pci_bus_to_host(dev->bus);
126 if (!hose) {
127 printk(KERN_ERR "Can't find hose for bus %d\n",
128 dev->bus->number);
129 return;
130 }
131
132 /* Clear out any of the virtual P2P bridge registers */
133 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
134 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
135 pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
136 pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
137 pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
138 pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
139 pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
140 pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
141 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
142 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
143
144 if (hose->io_resource.flags) {
145 res = &dev->resource[res_idx++];
146 res->start = hose->io_resource.start;
147 res->end = hose->io_resource.end;
148 res->flags = hose->io_resource.flags;
149 update_bridge_resource(dev, res);
150 }
151
152 for (i = 0; i < 3; i++) {
153 res = &dev->resource[res_idx + i];
154 res->start = hose->mem_resources[i].start;
155 res->end = hose->mem_resources[i].end;
156 res->flags = hose->mem_resources[i].flags;
157 update_bridge_resource(dev, res);
158 }
159} 120}
160 121
161int __init fsl_pcie_check_link(struct pci_controller *hose) 122int __init fsl_pcie_check_link(struct pci_controller *hose)
@@ -172,11 +133,24 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
172 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 133 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
173 int i; 134 int i;
174 135
175 /* deal with bogus pci_bus when we don't have anything connected on PCIe */ 136 if ((bus->parent == hose->bus) &&
176 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { 137 ((fsl_pcie_bus_fixup &&
177 if (bus->parent) { 138 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
178 for (i = 0; i < 4; ++i) 139 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
179 bus->resource[i] = bus->parent->resource[i]; 140 {
141 for (i = 0; i < 4; ++i) {
142 struct resource *res = bus->resource[i];
143 struct resource *par = bus->parent->resource[i];
144 if (res) {
145 res->start = 0;
146 res->end = 0;
147 res->flags = 0;
148 }
149 if (res && par) {
150 res->start = par->start;
151 res->end = par->end;
152 res->flags = par->flags;
153 }
180 } 154 }
181 } 155 }
182} 156}
@@ -240,23 +214,23 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
240 return 0; 214 return 0;
241} 215}
242 216
243DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent); 217DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
244DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent); 218DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
245DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent); 219DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
246DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent); 220DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
247DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent); 221DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
248DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent); 222DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
249DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent); 223DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
250DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent); 224DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
251DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent); 225DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
252DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent); 226DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
253DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent); 227DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
254DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent); 228DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
255DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent); 229DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
256DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent); 230DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
257DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent); 231DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
258DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent); 232DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
259DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent); 233DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
260DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent); 234DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
261DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent); 235DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
262DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_transparent); 236DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 02:36:37 -0500