Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Ben Herrenschmidt:
 "Here is the bulk of the powerpc changes for this merge window.  It got
  a bit delayed in part because I wasn't paying attention, and in part
  because I discovered I had a core PCI change without a PCI maintainer
  ack in it.  Bjorn eventually agreed it was ok to merge it though we'll
  probably improve it later and I didn't want to rebase to add his ack.

  There is going to be a bit more next week, essentially fixes that I
  still want to sort through and test.

  The biggest item this time is the support to build the ppc64 LE kernel
  with our new v2 ABI.  We previously supported v2 userspace but the
  kernel itself was a tougher nut to crack.  This is now sorted mostly
  thanks to Anton and Rusty.

  We also have a fairly big series from Cedric that add support for
  64-bit LE zImage boot wrapper.  This was made harder by the fact that
  traditionally our zImage wrapper was always 32-bit, but our new LE
  toolchains don't really support 32-bit anymore (it's somewhat there
  but not really "supported") so we didn't want to rely on it.  This
  meant more churn that just endian fixes.

  This brings some more LE bits as well, such as the ability to run in
  LE mode without a hypervisor (ie. under OPAL firmware) by doing the
  right OPAL call to reinitialize the CPU to take HV interrupts in the
  right mode and the usual pile of endian fixes.

  There's another series from Gavin adding EEH improvements (one day we
  *will* have a release with less than 20 EEH patches, I promise!).

  Another highlight is the support for the "Split core" functionality on
  P8 by Michael.  This allows a P8 core to be split into "sub cores" of
  4 threads which allows the subcores to run different guests under KVM
  (the HW still doesn't support a partition per thread).

  And then the usual misc bits and fixes ..."

[ Further delayed by gmail deciding that BenH is a dirty spammer.
  Google knows.  ]

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits)
  powerpc/powernv: Add missing include to LPC code
  selftests/powerpc: Test the THP bug we fixed in the previous commit
  powerpc/mm: Check paca psize is up to date for huge mappings
  powerpc/powernv: Pass buffer size to OPAL validate flash call
  powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC()
  powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC()
  powerpc/powernv: Set memory_block_size_bytes to 256MB
  powerpc: Allow ppc_md platform hook to override memory_block_size_bytes
  powerpc/powernv: Fix endian issues in memory error handling code
  powerpc/eeh: Skip eeh sysfs when eeh is disabled
  powerpc: 64bit sendfile is capped at 2GB
  powerpc/powernv: Provide debugfs access to the LPC bus via OPAL
  powerpc/serial: Use saner flags when creating legacy ports
  powerpc: Add cpu family documentation
  powerpc/xmon: Fix up xmon format strings
  powerpc/powernv: Add calls to support little endian host
  powerpc: Document sysfs DSCR interface
  powerpc: Fix regression of per-CPU DSCR setting
  powerpc: Split __SYSFS_SPRSETUP macro
  arch: powerpc/fadump: Cleaning up inconsistent NULL checks
  ...

8 files changed, 255 insertions, 15 deletions

diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7baa70d6dc01..a19332a38715 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -7,6 +7,12 @@ config PPC4xx_PCI_EXPRESS
         depends on PCI && 4xx
         default n
 
+config PPC4xx_HSTA_MSI
+        bool
+        depends on PCI_MSI
+        depends on PCI && 4xx
+        default n
+
 config PPC4xx_MSI
         bool
         depends on PCI_MSI
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index afbcc37aa094..f7cb2a1b01fa 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
 endif
+obj-$(CONFIG_PPC4xx_HSTA_MSI)   += ppc4xx_hsta_msi.o
 obj-$(CONFIG_PPC4xx_MSI)        += ppc4xx_msi.o
 obj-$(CONFIG_PPC4xx_CPM)        += ppc4xx_cpm.o
 obj-$(CONFIG_PPC4xx_GPIO)       += ppc4xx_gpio.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3f415e252ea5..4bd091a05583 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1150,8 +1150,7 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
         pci = hose->private_data;
 
         /* Enable PTOD, ENL23D & EXL23D */
-        out_be32(&pci->pex_pme_mes_disr, 0);
-        setbits32(&pci->pex_pme_mes_disr,
+        clrbits32(&pci->pex_pme_mes_disr,
                   PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
 
         out_be32(&pci->pex_pme_mes_ier, 0);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cf2b0840a672..c04b718307c8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -391,8 +391,10 @@ int fsl_rio_setup(struct platform_device *dev)
         ops->get_inb_message = fsl_get_inb_message;
 
         rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
-        if (!rmu_node)
+        if (!rmu_node) {
+                dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
                 goto err_rmu;
+        }
         rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
         if (rc) {
                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
@@ -413,6 +415,7 @@ int fsl_rio_setup(struct platform_device *dev)
         /*set up doobell node*/
         np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
         if (!np) {
+                dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
                 rc = -ENODEV;
                 goto err_dbell;
         }
@@ -441,6 +444,7 @@ int fsl_rio_setup(struct platform_device *dev)
         /*set up port write node*/
         np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
         if (!np) {
+                dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
                 rc = -ENODEV;
                 goto err_pw;
         }
@@ -633,14 +637,18 @@ int fsl_rio_setup(struct platform_device *dev)
         return 0;
 err:
         kfree(pw);
+        pw = NULL;
 err_pw:
         kfree(dbell);
+        dbell = NULL;
 err_dbell:
         iounmap(rmu_regs_win);
+        rmu_regs_win = NULL;
 err_rmu:
         kfree(ops);
 err_ops:
         iounmap(rio_regs_win);
+        rio_regs_win = NULL;
 err_rio_regs:
         return rc;
 }
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 00e224a1048c..b48197ae44d0 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -881,9 +881,9 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
         rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
                          "msg_rx", (void *)mport);
         if (rc < 0) {
-                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
-                        rmu->msg_tx_ring.virt_buffer[i],
-                        rmu->msg_tx_ring.phys_buffer[i]);
+                dma_free_coherent(priv->dev,
+                        rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
+                        rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
                 goto out;
         }
 
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8209744b2829..be33c9768ea1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1588,10 +1588,6 @@ void __init mpic_init(struct mpic *mpic)
                         num_timers = 8;
         }
 
-        /* FSL mpic error interrupt intialization */
-        if (mpic->flags & MPIC_FSL_HAS_EIMR)
-                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
-
         /* Initialize timers to our reserved vectors and mask them for now */
         for (i = 0; i < num_timers; i++) {
                 unsigned int offset = mpic_tm_offset(mpic, i);
@@ -1675,6 +1671,10 @@ void __init mpic_init(struct mpic *mpic)
                         irq_set_chained_handler(virq, &mpic_cascade);
                 }
         }
+
+        /* FSL mpic error interrupt intialization */
+        if (mpic->flags & MPIC_FSL_HAS_EIMR)
+                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
 }
 
 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
diff --git a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
new file mode 100644
index 000000000000..11c888416f0a
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
@@ -0,0 +1,215 @@
+/*
+ * MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
+ * generation of the interrupt.
+ *
+ * Copyright © 2013 Alistair Popple <alistair@popple.id.au> IBM Corporation
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/semaphore.h>
+#include <asm/msi_bitmap.h>
+
+struct ppc4xx_hsta_msi {
+        struct device *dev;
+
+        /* The ioremapped HSTA MSI IO space */
+        u32 __iomem *data;
+
+        /* Physical address of HSTA MSI IO space */
+        u64 address;
+        struct msi_bitmap bmp;
+
+        /* An array mapping offsets to hardware IRQs */
+        int *irq_map;
+
+        /* Number of hwirqs supported */
+        int irq_count;
+};
+static struct ppc4xx_hsta_msi ppc4xx_hsta_msi;
+
+static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        struct msi_msg msg;
+        struct msi_desc *entry;
+        int irq, hwirq;
+        u64 addr;
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                irq = msi_bitmap_alloc_hwirqs(&ppc4xx_hsta_msi.bmp, 1);
+                if (irq < 0) {
+                        pr_debug("%s: Failed to allocate msi interrupt\n",
+                                 __func__);
+                        return irq;
+                }
+
+                hwirq = ppc4xx_hsta_msi.irq_map[irq];
+                if (hwirq == NO_IRQ) {
+                        pr_err("%s: Failed mapping irq %d\n", __func__, irq);
+                        return -EINVAL;
+                }
+
+                /*
+                 * HSTA generates interrupts on writes to 128-bit aligned
+                 * addresses.
+                 */
+                addr = ppc4xx_hsta_msi.address + irq*0x10;
+                msg.address_hi = upper_32_bits(addr);
+                msg.address_lo = lower_32_bits(addr);
+
+                /* Data is not used by the HSTA. */
+                msg.data = 0;
+
+                pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq,
+                         (((u64) msg.address_hi) << 32) | msg.address_lo);
+
+                if (irq_set_msi_desc(hwirq, entry)) {
+                        pr_err(
+                        "%s: Invalid hwirq %d specified in device tree\n",
+                        __func__, hwirq);
+                        msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
+                        return -EINVAL;
+                }
+                write_msi_msg(hwirq, &msg);
+        }
+
+        return 0;
+}
+
+static int hsta_find_hwirq_offset(int hwirq)
+{
+        int irq;
+
+        /* Find the offset given the hwirq */
+        for (irq = 0; irq < ppc4xx_hsta_msi.irq_count; irq++)
+                if (ppc4xx_hsta_msi.irq_map[irq] == hwirq)
+                        return irq;
+
+        return -EINVAL;
+}
+
+static void hsta_teardown_msi_irqs(struct pci_dev *dev)
+{
+        struct msi_desc *entry;
+        int irq;
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                if (entry->irq == NO_IRQ)
+                        continue;
+
+                irq = hsta_find_hwirq_offset(entry->irq);
+
+                /* entry->irq should always be in irq_map */
+                BUG_ON(irq < 0);
+                irq_set_msi_desc(entry->irq, NULL);
+                msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
+                pr_debug("%s: Teardown IRQ %u (index %u)\n", __func__,
+                         entry->irq, irq);
+        }
+}
+
+static int hsta_msi_check_device(struct pci_dev *pdev, int nvec, int type)
+{
+        /* We don't support MSI-X */
+        if (type == PCI_CAP_ID_MSIX) {
+                pr_debug("%s: MSI-X not supported.\n", __func__);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int hsta_msi_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct resource *mem;
+        int irq, ret, irq_count;
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (IS_ERR(mem)) {
+                dev_err(dev, "Unable to get mmio space\n");
+                return -EINVAL;
+        }
+
+        irq_count = of_irq_count(dev->of_node);
+        if (!irq_count) {
+                dev_err(dev, "Unable to find IRQ range\n");
+                return -EINVAL;
+        }
+
+        ppc4xx_hsta_msi.dev = dev;
+        ppc4xx_hsta_msi.address = mem->start;
+        ppc4xx_hsta_msi.data = ioremap(mem->start, resource_size(mem));
+        ppc4xx_hsta_msi.irq_count = irq_count;
+        if (IS_ERR(ppc4xx_hsta_msi.data)) {
+                dev_err(dev, "Unable to map memory\n");
+                return -ENOMEM;
+        }
+
+        ret = msi_bitmap_alloc(&ppc4xx_hsta_msi.bmp, irq_count, dev->of_node);
+        if (ret)
+                goto out;
+
+        ppc4xx_hsta_msi.irq_map = kmalloc(sizeof(int) * irq_count, GFP_KERNEL);
+        if (IS_ERR(ppc4xx_hsta_msi.irq_map)) {
+                ret = -ENOMEM;
+                goto out1;
+        }
+
+        /* Setup a mapping from irq offsets to hardware irq numbers */
+        for (irq = 0; irq < irq_count; irq++) {
+                ppc4xx_hsta_msi.irq_map[irq] =
+                        irq_of_parse_and_map(dev->of_node, irq);
+                if (ppc4xx_hsta_msi.irq_map[irq] == NO_IRQ) {
+                        dev_err(dev, "Unable to map IRQ\n");
+                        ret = -EINVAL;
+                        goto out2;
+                }
+        }
+
+        ppc_md.setup_msi_irqs = hsta_setup_msi_irqs;
+        ppc_md.teardown_msi_irqs = hsta_teardown_msi_irqs;
+        ppc_md.msi_check_device = hsta_msi_check_device;
+        return 0;
+
+out2:
+        kfree(ppc4xx_hsta_msi.irq_map);
+
+out1:
+        msi_bitmap_free(&ppc4xx_hsta_msi.bmp);
+
+out:
+        iounmap(ppc4xx_hsta_msi.data);
+        return ret;
+}
+
+static const struct of_device_id hsta_msi_ids[] = {
+        {
+                .compatible = "ibm,hsta-msi",
+        },
+        {}
+};
+
+static struct platform_driver hsta_msi_driver = {
+        .probe = hsta_msi_probe,
+        .driver = {
+                .name = "hsta-msi",
+                .owner = THIS_MODULE,
+                .of_match_table = hsta_msi_ids,
+        },
+};
+
+static int hsta_msi_init(void)
+{
+        return platform_driver_register(&hsta_msi_driver);
+}
+subsys_initcall(hsta_msi_init);
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 4914fd3f41ec..df6e2fc4ff92 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -176,8 +176,12 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
                 return -ENXIO;
         }
 
-        /* Check that we are fully contained within 32 bits space */
-        if (res->end > 0xffffffff) {
+        /* Check that we are fully contained within 32 bits space if we are not
+         * running on a 460sx or 476fpe which have 64 bit bus addresses.
+         */
+        if (res->end > 0xffffffff &&
+            !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx")
+              || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) {
                 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
                        hose->dn->full_name);
                 return -ENXIO;
@@ -1440,7 +1444,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
                 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
 #endif
 #ifdef CONFIG_476FPE
-        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
+        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe")
+                || of_device_is_compatible(np, "ibm,plb-pciex-476gtr"))
                 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
 #endif
         if (ppc4xx_pciex_hwops == NULL) {
@@ -1751,7 +1756,10 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port	*port,
                         dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
                                         | DCRO_PEGPL_OMRxMSKL_VAL);
-                else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                else if (of_device_is_compatible(
+                                port->node, "ibm,plb-pciex-476fpe") ||
+                        of_device_is_compatible(
+                                port->node, "ibm,plb-pciex-476gtr"))
                         dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
                                         | DCRO_PEGPL_OMRxMSKL_VAL);
@@ -1881,7 +1889,10 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
                         sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
 
                 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
-                    of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                    of_device_is_compatible(
+                            port->node, "ibm,plb-pciex-476fpe") ||
+                    of_device_is_compatible(
+                            port->node, "ibm,plb-pciex-476gtr"))
                         sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
 
                 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));