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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-14 10:31:13 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-17 22:55:43 -0500
commit7a96c6b22efbd84e195836e192a3ce478cd6e14c (patch)
treeadf9c9c5e1bb9d89d8536bf49c049beb5e9458d7 /arch/powerpc/sysdev
parentbb7f20b1c639606def3b91f4e4aca6daeee5d80a (diff)
powerpc: Fix MSI support on U4 bridge PCIe slot
On machines using the Apple U4 bridge (AKA IBM CPC945) PCIe interface such as the latest generation G5 machines x16 slot or the x16 slot of the PowerStation, MSIs are currently broken (and will oops when enabling). This fixes the oops and implements proper support for those. Instead of using the PCIe <-> HT bridge conversion, on such slots we need to use a bunch of magic registers in the bridge as the MSI target, encoding the interrupt number in the low bits of the address itself Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/mpic_msi.c11
-rw-r--r--arch/powerpc/sysdev/mpic_u3msi.c46
2 files changed, 49 insertions, 8 deletions
diff --git a/arch/powerpc/sysdev/mpic_msi.c b/arch/powerpc/sysdev/mpic_msi.c
index 1d44eee80fa1..0f67cd79d481 100644
--- a/arch/powerpc/sysdev/mpic_msi.c
+++ b/arch/powerpc/sysdev/mpic_msi.c
@@ -39,7 +39,12 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
39 39
40 pr_debug("mpic: found U3, guessing msi allocator setup\n"); 40 pr_debug("mpic: found U3, guessing msi allocator setup\n");
41 41
42 /* Reserve source numbers we know are reserved in the HW */ 42 /* Reserve source numbers we know are reserved in the HW.
43 *
44 * This is a bit of a mix of U3 and U4 reserves but that's going
45 * to work fine, we have plenty enugh numbers left so let's just
46 * mark anything we don't like reserved.
47 */
43 for (i = 0; i < 8; i++) 48 for (i = 0; i < 8; i++)
44 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i); 49 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
45 50
@@ -49,6 +54,10 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
49 for (i = 100; i < 105; i++) 54 for (i = 100; i < 105; i++)
50 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i); 55 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
51 56
57 for (i = 124; i < mpic->irq_count; i++)
58 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
59
60
52 np = NULL; 61 np = NULL;
53 while ((np = of_find_all_nodes(np))) { 62 while ((np = of_find_all_nodes(np))) {
54 pr_debug("mpic: mapping hwirqs for %s\n", np->full_name); 63 pr_debug("mpic: mapping hwirqs for %s\n", np->full_name);
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index d3caf23e6312..bcbfe79c704b 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -64,12 +64,12 @@ static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
64 return addr; 64 return addr;
65} 65}
66 66
67static u64 find_ht_magic_addr(struct pci_dev *pdev) 67static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
68{ 68{
69 struct pci_bus *bus; 69 struct pci_bus *bus;
70 unsigned int pos; 70 unsigned int pos;
71 71
72 for (bus = pdev->bus; bus; bus = bus->parent) { 72 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) {
73 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); 73 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
74 if (pos) 74 if (pos)
75 return read_ht_magic_addr(bus->self, pos); 75 return read_ht_magic_addr(bus->self, pos);
@@ -78,13 +78,41 @@ static u64 find_ht_magic_addr(struct pci_dev *pdev)
78 return 0; 78 return 0;
79} 79}
80 80
81static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
82{
83 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
84
85 /* U4 PCIe MSIs need to write to the special register in
86 * the bridge that generates interrupts. There should be
87 * theorically a register at 0xf8005000 where you just write
88 * the MSI number and that triggers the right interrupt, but
89 * unfortunately, this is busted in HW, the bridge endian swaps
90 * the value and hits the wrong nibble in the register.
91 *
92 * So instead we use another register set which is used normally
93 * for converting HT interrupts to MPIC interrupts, which decodes
94 * the interrupt number as part of the low address bits
95 *
96 * This will not work if we ever use more than one legacy MSI in
97 * a block but we never do. For one MSI or multiple MSI-X where
98 * each interrupt address can be specified separately, it works
99 * just fine.
100 */
101 if (of_device_is_compatible(hose->dn, "u4-pcie") ||
102 of_device_is_compatible(hose->dn, "U4-pcie"))
103 return 0xf8004000 | (hwirq << 4);
104
105 return 0;
106}
107
81static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type) 108static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
82{ 109{
83 if (type == PCI_CAP_ID_MSIX) 110 if (type == PCI_CAP_ID_MSIX)
84 pr_debug("u3msi: MSI-X untested, trying anyway.\n"); 111 pr_debug("u3msi: MSI-X untested, trying anyway.\n");
85 112
86 /* If we can't find a magic address then MSI ain't gonna work */ 113 /* If we can't find a magic address then MSI ain't gonna work */
87 if (find_ht_magic_addr(pdev) == 0) { 114 if (find_ht_magic_addr(pdev, 0) == 0 &&
115 find_u4_magic_addr(pdev, 0) == 0) {
88 pr_debug("u3msi: no magic address found for %s\n", 116 pr_debug("u3msi: no magic address found for %s\n",
89 pci_name(pdev)); 117 pci_name(pdev));
90 return -ENXIO; 118 return -ENXIO;
@@ -118,10 +146,6 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
118 u64 addr; 146 u64 addr;
119 int hwirq; 147 int hwirq;
120 148
121 addr = find_ht_magic_addr(pdev);
122 msg.address_lo = addr & 0xFFFFFFFF;
123 msg.address_hi = addr >> 32;
124
125 list_for_each_entry(entry, &pdev->msi_list, list) { 149 list_for_each_entry(entry, &pdev->msi_list, list) {
126 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); 150 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
127 if (hwirq < 0) { 151 if (hwirq < 0) {
@@ -129,6 +153,12 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
129 return hwirq; 153 return hwirq;
130 } 154 }
131 155
156 addr = find_ht_magic_addr(pdev, hwirq);
157 if (addr == 0)
158 addr = find_u4_magic_addr(pdev, hwirq);
159 msg.address_lo = addr & 0xFFFFFFFF;
160 msg.address_hi = addr >> 32;
161
132 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); 162 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
133 if (virq == NO_IRQ) { 163 if (virq == NO_IRQ) {
134 pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq); 164 pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq);
@@ -143,6 +173,8 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
143 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", 173 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
144 virq, hwirq, (unsigned long)addr); 174 virq, hwirq, (unsigned long)addr);
145 175
176 printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
177 virq, hwirq, (unsigned long)addr);
146 msg.data = hwirq; 178 msg.data = hwirq;
147 write_msi_msg(virq, &msg); 179 write_msi_msg(virq, &msg);
148 180