Merge remote-tracking branch 'jwb/next' into next

Conflicts:
	arch/powerpc/platforms/40x/ppc40x_simple.c

2 files changed, 84 insertions, 8 deletions

diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 862f11b3821e..4f05f7542346 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -185,9 +185,15 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
  out:
         dma_offset_set = 1;
         pci_dram_offset = res->start;
+        hose->dma_window_base_cur = res->start;
+        hose->dma_window_size = resource_size(res);
 
         printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
                pci_dram_offset);
+        printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
+               (unsigned long long)hose->dma_window_base_cur);
+        printk(KERN_INFO "DMA window size 0x%016llx\n",
+               (unsigned long long)hose->dma_window_size);
         return 0;
 }
 
@@ -647,6 +653,7 @@ static unsigned int ppc4xx_pciex_port_count;
 
 struct ppc4xx_pciex_hwops
 {
+        bool want_sdr;
         int (*core_init)(struct device_node *np);
         int (*port_init_hw)(struct ppc4xx_pciex_port *port);
         int (*setup_utl)(struct ppc4xx_pciex_port *port);
@@ -916,6 +923,7 @@ static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
 
 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
         .core_init      = ppc440spe_pciex_core_init,
         .port_init_hw   = ppc440speA_pciex_init_port_hw,
         .setup_utl      = ppc440speA_pciex_init_utl,
@@ -924,6 +932,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
 
 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
         .core_init      = ppc440spe_pciex_core_init,
         .port_init_hw   = ppc440speB_pciex_init_port_hw,
         .setup_utl      = ppc440speB_pciex_init_utl,
@@ -1034,6 +1043,7 @@ static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 
 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
         .core_init      = ppc460ex_pciex_core_init,
         .port_init_hw   = ppc460ex_pciex_init_port_hw,
         .setup_utl      = ppc460ex_pciex_init_utl,
@@ -1181,6 +1191,7 @@ done:
 }
 
 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
+        .want_sdr       = true,
         .core_init      = ppc460sx_pciex_core_init,
         .port_init_hw   = ppc460sx_pciex_init_port_hw,
         .setup_utl      = ppc460sx_pciex_init_utl,
@@ -1276,6 +1287,7 @@ static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
 
 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
 {
+        .want_sdr       = true,
         .core_init      = ppc405ex_pciex_core_init,
         .port_init_hw   = ppc405ex_pciex_init_port_hw,
         .setup_utl      = ppc405ex_pciex_init_utl,
@@ -1284,6 +1296,52 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
 
 #endif /* CONFIG_40x */
 
+#ifdef CONFIG_476FPE
+static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
+{
+        return 4;
+}
+
+static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
+{
+        u32 timeout_ms = 20;
+        u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
+        void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
+                                      0x1000);
+
+        printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
+
+        if (mbase == NULL) {
+                printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
+                                    port->index);
+                return;
+        }
+                
+        while (timeout_ms--) {
+                val = in_le32(mbase + PECFG_TLDLP);
+
+                if ((val & mask) == mask)
+                        break;
+                msleep(10);
+        }
+
+        if (val & PECFG_TLDLP_PRESENT) {
+                printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
+                port->link = 1;
+        } else
+                printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
+
+        iounmap(mbase);
+        return;
+}
+
+static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
+{
+        .core_init      = ppc_476fpe_pciex_core_init,
+        .check_link     = ppc_476fpe_pciex_check_link,
+};
+#endif /* CONFIG_476FPE */
+
 /* Check that the core has been initied and if not, do it */
 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
 {
@@ -1309,6 +1367,10 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
         if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
                 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
 #endif
+#ifdef CONFIG_476FPE
+        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
+                ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
+#endif
         if (ppc4xx_pciex_hwops == NULL) {
                 printk(KERN_WARNING "PCIE: unknown host type %s\n",
                        np->full_name);
@@ -1617,6 +1679,10 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port	*port,
                         dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
                                         | DCRO_PEGPL_OMRxMSKL_VAL);
+                else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
+                                sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
+                                        | DCRO_PEGPL_OMRxMSKL_VAL);
                 else
                         dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                 sa | DCRO_PEGPL_OMR1MSKL_UOT
@@ -1739,9 +1805,10 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
                 /* Calculate window size */
                 sa = (0xffffffffffffffffull << ilog2(size));
                 if (res->flags & IORESOURCE_PREFETCH)
-                        sa |= 0x8;
+                        sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
 
-                if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
+                if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
+                    of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
                         sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
 
                 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
@@ -1972,13 +2039,15 @@ static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
         }
 
         port->node = of_node_get(np);
-        pval = of_get_property(np, "sdr-base", NULL);
-        if (pval == NULL) {
-                printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
-                       np->full_name);
-                return;
+        if (ppc4xx_pciex_hwops->want_sdr) {
+                pval = of_get_property(np, "sdr-base", NULL);
+                if (pval == NULL) {
+                        printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
+                               np->full_name);
+                        return;
+                }
+                port->sdr_base = *pval;
         }
-        port->sdr_base = *pval;
 
         /* Check if device_type property is set to "pci" or "pci-endpoint".
          * Resulting from this setup this PCIe port will be configured
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 32ce763a375a..bb4821938ab1 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -476,6 +476,13 @@
 #define DCRO_PEGPL_OMR1MSKL_UOT  0x00000002
 #define DCRO_PEGPL_OMR3MSKL_IO   0x00000002
 
+/* 476FPE */
+#define PCCFG_LCPA                      0x270
+#define PECFG_TLDLP                     0x3F8
+#define PECFG_TLDLP_LNKUP               0x00000008
+#define PECFG_TLDLP_PRESENT             0x00000010
+#define DCRO_PEGPL_476FPE_OMR1MSKL_UOT   0x00000004
+
 /* SDR Bit Mappings */
 #define PESDRx_RCSSET_HLDPLB    0x10000000
 #define PESDRx_RCSSET_RSTGU     0x01000000